1 //===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for PowerPC,
11 // converting from a legalized dag to a PPC dag.
13 //===----------------------------------------------------------------------===//
16 #include "MCTargetDesc/PPCPredicates.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCTargetMachine.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/IR/GlobalAlias.h"
27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/IR/GlobalVariable.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Module.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetOptions.h"
39 #define DEBUG_TYPE "ppc-codegen"
41 // FIXME: Remove this once the bug has been fixed!
42 cl::opt<bool> ANDIGlueBug("expose-ppc-andi-glue-bug",
43 cl::desc("expose the ANDI glue bug on PPC"), cl::Hidden);
45 cl::opt<bool> UseBitPermRewriter("ppc-use-bit-perm-rewriter", cl::init(true),
46 cl::desc("use aggressive ppc isel for bit permutations"), cl::Hidden);
47 cl::opt<bool> BPermRewriterNoMasking("ppc-bit-perm-rewriter-stress-rotates",
48 cl::desc("stress rotate selection in aggressive ppc isel for "
49 "bit permutations"), cl::Hidden);
52 void initializePPCDAGToDAGISelPass(PassRegistry&);
56 //===--------------------------------------------------------------------===//
57 /// PPCDAGToDAGISel - PPC specific code to select PPC machine
58 /// instructions for SelectionDAG operations.
60 class PPCDAGToDAGISel : public SelectionDAGISel {
61 const PPCTargetMachine &TM;
62 const PPCTargetLowering *PPCLowering;
63 const PPCSubtarget *PPCSubTarget;
64 unsigned GlobalBaseReg;
66 explicit PPCDAGToDAGISel(PPCTargetMachine &tm)
67 : SelectionDAGISel(tm), TM(tm),
68 PPCLowering(TM.getSubtargetImpl()->getTargetLowering()),
69 PPCSubTarget(TM.getSubtargetImpl()) {
70 initializePPCDAGToDAGISelPass(*PassRegistry::getPassRegistry());
73 bool runOnMachineFunction(MachineFunction &MF) override {
74 // Make sure we re-emit a set of the global base reg if necessary
76 PPCLowering = TM.getSubtargetImpl()->getTargetLowering();
77 PPCSubTarget = TM.getSubtargetImpl();
78 SelectionDAGISel::runOnMachineFunction(MF);
80 if (!PPCSubTarget->isSVR4ABI())
86 void PreprocessISelDAG() override;
87 void PostprocessISelDAG() override;
89 /// getI32Imm - Return a target constant with the specified value, of type
91 inline SDValue getI32Imm(unsigned Imm) {
92 return CurDAG->getTargetConstant(Imm, MVT::i32);
95 /// getI64Imm - Return a target constant with the specified value, of type
97 inline SDValue getI64Imm(uint64_t Imm) {
98 return CurDAG->getTargetConstant(Imm, MVT::i64);
101 /// getSmallIPtrImm - Return a target constant of pointer type.
102 inline SDValue getSmallIPtrImm(unsigned Imm) {
103 return CurDAG->getTargetConstant(Imm, PPCLowering->getPointerTy());
106 /// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s
107 /// with any number of 0s on either side. The 1s are allowed to wrap from
108 /// LSB to MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs.
109 /// 0x0F0F0000 is not, since all 1s are not contiguous.
110 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME);
113 /// isRotateAndMask - Returns true if Mask and Shift can be folded into a
114 /// rotate and mask opcode and mask operation.
115 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool isShiftMask,
116 unsigned &SH, unsigned &MB, unsigned &ME);
118 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
119 /// base register. Return the virtual register that holds this value.
120 SDNode *getGlobalBaseReg();
122 SDNode *getFrameIndex(SDNode *SN, SDNode *N, unsigned Offset = 0);
124 // Select - Convert the specified operand from a target-independent to a
125 // target-specific node if it hasn't already been changed.
126 SDNode *Select(SDNode *N) override;
128 SDNode *SelectBitfieldInsert(SDNode *N);
129 SDNode *SelectBitPermutation(SDNode *N);
131 /// SelectCC - Select a comparison of the specified values with the
132 /// specified condition code, returning the CR# of the expression.
133 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDLoc dl);
135 /// SelectAddrImm - Returns true if the address N can be represented by
136 /// a base register plus a signed 16-bit displacement [r+imm].
137 bool SelectAddrImm(SDValue N, SDValue &Disp,
139 return PPCLowering->SelectAddressRegImm(N, Disp, Base, *CurDAG, false);
142 /// SelectAddrImmOffs - Return true if the operand is valid for a preinc
143 /// immediate field. Note that the operand at this point is already the
144 /// result of a prior SelectAddressRegImm call.
145 bool SelectAddrImmOffs(SDValue N, SDValue &Out) const {
146 if (N.getOpcode() == ISD::TargetConstant ||
147 N.getOpcode() == ISD::TargetGlobalAddress) {
155 /// SelectAddrIdx - Given the specified addressed, check to see if it can be
156 /// represented as an indexed [r+r] operation. Returns false if it can
157 /// be represented by [r+imm], which are preferred.
158 bool SelectAddrIdx(SDValue N, SDValue &Base, SDValue &Index) {
159 return PPCLowering->SelectAddressRegReg(N, Base, Index, *CurDAG);
162 /// SelectAddrIdxOnly - Given the specified addressed, force it to be
163 /// represented as an indexed [r+r] operation.
164 bool SelectAddrIdxOnly(SDValue N, SDValue &Base, SDValue &Index) {
165 return PPCLowering->SelectAddressRegRegOnly(N, Base, Index, *CurDAG);
168 /// SelectAddrImmX4 - Returns true if the address N can be represented by
169 /// a base register plus a signed 16-bit displacement that is a multiple of 4.
170 /// Suitable for use by STD and friends.
171 bool SelectAddrImmX4(SDValue N, SDValue &Disp, SDValue &Base) {
172 return PPCLowering->SelectAddressRegImm(N, Disp, Base, *CurDAG, true);
175 // Select an address into a single register.
176 bool SelectAddr(SDValue N, SDValue &Base) {
181 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
182 /// inline asm expressions. It is always correct to compute the value into
183 /// a register. The case of adding a (possibly relocatable) constant to a
184 /// register can be improved, but it is wrong to substitute Reg+Reg for
185 /// Reg in an asm, because the load or store opcode would have to change.
186 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
188 std::vector<SDValue> &OutOps) override {
189 // We need to make sure that this one operand does not end up in r0
190 // (because we might end up lowering this as 0(%op)).
191 const TargetRegisterInfo *TRI = TM.getSubtargetImpl()->getRegisterInfo();
192 const TargetRegisterClass *TRC = TRI->getPointerRegClass(*MF, /*Kind=*/1);
193 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
195 SDValue(CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
196 SDLoc(Op), Op.getValueType(),
199 OutOps.push_back(NewOp);
203 void InsertVRSaveCode(MachineFunction &MF);
205 const char *getPassName() const override {
206 return "PowerPC DAG->DAG Pattern Instruction Selection";
209 // Include the pieces autogenerated from the target description.
210 #include "PPCGenDAGISel.inc"
213 SDNode *SelectSETCC(SDNode *N);
215 void PeepholePPC64();
216 void PeepholePPC64ZExt();
217 void PeepholeCROps();
219 SDValue combineToCMPB(SDNode *N);
221 bool AllUsersSelectZero(SDNode *N);
222 void SwapAllSelectUsers(SDNode *N);
226 /// InsertVRSaveCode - Once the entire function has been instruction selected,
227 /// all virtual registers are created and all machine instructions are built,
228 /// check to see if we need to save/restore VRSAVE. If so, do it.
229 void PPCDAGToDAGISel::InsertVRSaveCode(MachineFunction &Fn) {
230 // Check to see if this function uses vector registers, which means we have to
231 // save and restore the VRSAVE register and update it with the regs we use.
233 // In this case, there will be virtual registers of vector type created
234 // by the scheduler. Detect them now.
235 bool HasVectorVReg = false;
236 for (unsigned i = 0, e = RegInfo->getNumVirtRegs(); i != e; ++i) {
237 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
238 if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) {
239 HasVectorVReg = true;
243 if (!HasVectorVReg) return; // nothing to do.
245 // If we have a vector register, we want to emit code into the entry and exit
246 // blocks to save and restore the VRSAVE register. We do this here (instead
247 // of marking all vector instructions as clobbering VRSAVE) for two reasons:
249 // 1. This (trivially) reduces the load on the register allocator, by not
250 // having to represent the live range of the VRSAVE register.
251 // 2. This (more significantly) allows us to create a temporary virtual
252 // register to hold the saved VRSAVE value, allowing this temporary to be
253 // register allocated, instead of forcing it to be spilled to the stack.
255 // Create two vregs - one to hold the VRSAVE register that is live-in to the
256 // function and one for the value after having bits or'd into it.
257 unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
258 unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
260 const TargetInstrInfo &TII = *TM.getSubtargetImpl()->getInstrInfo();
261 MachineBasicBlock &EntryBB = *Fn.begin();
263 // Emit the following code into the entry block:
264 // InVRSAVE = MFVRSAVE
265 // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
266 // MTVRSAVE UpdatedVRSAVE
267 MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
268 BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE);
269 BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE),
270 UpdatedVRSAVE).addReg(InVRSAVE);
271 BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
273 // Find all return blocks, outputting a restore in each epilog.
274 for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
275 if (!BB->empty() && BB->back().isReturn()) {
276 IP = BB->end(); --IP;
278 // Skip over all terminator instructions, which are part of the return
280 MachineBasicBlock::iterator I2 = IP;
281 while (I2 != BB->begin() && (--I2)->isTerminator())
284 // Emit: MTVRSAVE InVRSave
285 BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
291 /// getGlobalBaseReg - Output the instructions required to put the
292 /// base address to use for accessing globals into a register.
294 SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
295 if (!GlobalBaseReg) {
296 const TargetInstrInfo &TII = *TM.getSubtargetImpl()->getInstrInfo();
297 // Insert the set of GlobalBaseReg into the first MBB of the function
298 MachineBasicBlock &FirstMBB = MF->front();
299 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
300 const Module *M = MF->getFunction()->getParent();
303 if (PPCLowering->getPointerTy() == MVT::i32) {
304 if (PPCSubTarget->isTargetELF()) {
305 GlobalBaseReg = PPC::R30;
306 if (M->getPICLevel() == PICLevel::Small) {
307 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MoveGOTtoLR));
308 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
310 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));
311 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
312 unsigned TempReg = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
313 BuildMI(FirstMBB, MBBI, dl,
314 TII.get(PPC::UpdateGBR)).addReg(GlobalBaseReg)
315 .addReg(TempReg, RegState::Define).addReg(GlobalBaseReg);
316 MF->getInfo<PPCFunctionInfo>()->setUsesPICBase(true);
320 RegInfo->createVirtualRegister(&PPC::GPRC_NOR0RegClass);
321 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));
322 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
325 GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::G8RC_NOX0RegClass);
326 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8));
327 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg);
330 return CurDAG->getRegister(GlobalBaseReg,
331 PPCLowering->getPointerTy()).getNode();
334 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
335 /// or 64-bit immediate, and if the value can be accurately represented as a
336 /// sign extension from a 16-bit value. If so, this returns true and the
338 static bool isIntS16Immediate(SDNode *N, short &Imm) {
339 if (N->getOpcode() != ISD::Constant)
342 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
343 if (N->getValueType(0) == MVT::i32)
344 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
346 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
349 static bool isIntS16Immediate(SDValue Op, short &Imm) {
350 return isIntS16Immediate(Op.getNode(), Imm);
354 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
355 /// operand. If so Imm will receive the 32-bit value.
356 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
357 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
358 Imm = cast<ConstantSDNode>(N)->getZExtValue();
364 /// isInt64Immediate - This method tests to see if the node is a 64-bit constant
365 /// operand. If so Imm will receive the 64-bit value.
366 static bool isInt64Immediate(SDNode *N, uint64_t &Imm) {
367 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
368 Imm = cast<ConstantSDNode>(N)->getZExtValue();
374 // isInt32Immediate - This method tests to see if a constant operand.
375 // If so Imm will receive the 32 bit value.
376 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
377 return isInt32Immediate(N.getNode(), Imm);
381 // isOpcWithIntImmediate - This method tests to see if the node is a specific
382 // opcode and that it has a immediate integer right operand.
383 // If so Imm will receive the 32 bit value.
384 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
385 return N->getOpcode() == Opc
386 && isInt32Immediate(N->getOperand(1).getNode(), Imm);
389 SDNode *PPCDAGToDAGISel::getFrameIndex(SDNode *SN, SDNode *N, unsigned Offset) {
391 int FI = cast<FrameIndexSDNode>(N)->getIndex();
392 SDValue TFI = CurDAG->getTargetFrameIndex(FI, N->getValueType(0));
393 unsigned Opc = N->getValueType(0) == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
395 return CurDAG->SelectNodeTo(SN, Opc, N->getValueType(0), TFI,
396 getSmallIPtrImm(Offset));
397 return CurDAG->getMachineNode(Opc, dl, N->getValueType(0), TFI,
398 getSmallIPtrImm(Offset));
401 bool PPCDAGToDAGISel::isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
405 if (isShiftedMask_32(Val)) {
406 // look for the first non-zero bit
407 MB = countLeadingZeros(Val);
408 // look for the first zero bit after the run of ones
409 ME = countLeadingZeros((Val - 1) ^ Val);
412 Val = ~Val; // invert mask
413 if (isShiftedMask_32(Val)) {
414 // effectively look for the first zero bit
415 ME = countLeadingZeros(Val) - 1;
416 // effectively look for the first one bit after the run of zeros
417 MB = countLeadingZeros((Val - 1) ^ Val) + 1;
425 bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask,
426 bool isShiftMask, unsigned &SH,
427 unsigned &MB, unsigned &ME) {
428 // Don't even go down this path for i64, since different logic will be
429 // necessary for rldicl/rldicr/rldimi.
430 if (N->getValueType(0) != MVT::i32)
434 unsigned Indeterminant = ~0; // bit mask marking indeterminant results
435 unsigned Opcode = N->getOpcode();
436 if (N->getNumOperands() != 2 ||
437 !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31))
440 if (Opcode == ISD::SHL) {
441 // apply shift left to mask if it comes first
442 if (isShiftMask) Mask = Mask << Shift;
443 // determine which bits are made indeterminant by shift
444 Indeterminant = ~(0xFFFFFFFFu << Shift);
445 } else if (Opcode == ISD::SRL) {
446 // apply shift right to mask if it comes first
447 if (isShiftMask) Mask = Mask >> Shift;
448 // determine which bits are made indeterminant by shift
449 Indeterminant = ~(0xFFFFFFFFu >> Shift);
450 // adjust for the left rotate
452 } else if (Opcode == ISD::ROTL) {
458 // if the mask doesn't intersect any Indeterminant bits
459 if (Mask && !(Mask & Indeterminant)) {
461 // make sure the mask is still a mask (wrap arounds may not be)
462 return isRunOfOnes(Mask, MB, ME);
467 /// SelectBitfieldInsert - turn an or of two masked values into
468 /// the rotate left word immediate then mask insert (rlwimi) instruction.
469 SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
470 SDValue Op0 = N->getOperand(0);
471 SDValue Op1 = N->getOperand(1);
474 APInt LKZ, LKO, RKZ, RKO;
475 CurDAG->computeKnownBits(Op0, LKZ, LKO);
476 CurDAG->computeKnownBits(Op1, RKZ, RKO);
478 unsigned TargetMask = LKZ.getZExtValue();
479 unsigned InsertMask = RKZ.getZExtValue();
481 if ((TargetMask | InsertMask) == 0xFFFFFFFF) {
482 unsigned Op0Opc = Op0.getOpcode();
483 unsigned Op1Opc = Op1.getOpcode();
484 unsigned Value, SH = 0;
485 TargetMask = ~TargetMask;
486 InsertMask = ~InsertMask;
488 // If the LHS has a foldable shift and the RHS does not, then swap it to the
489 // RHS so that we can fold the shift into the insert.
490 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
491 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
492 Op0.getOperand(0).getOpcode() == ISD::SRL) {
493 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
494 Op1.getOperand(0).getOpcode() != ISD::SRL) {
496 std::swap(Op0Opc, Op1Opc);
497 std::swap(TargetMask, InsertMask);
500 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
501 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
502 Op1.getOperand(0).getOpcode() != ISD::SRL) {
504 std::swap(Op0Opc, Op1Opc);
505 std::swap(TargetMask, InsertMask);
510 if (isRunOfOnes(InsertMask, MB, ME)) {
513 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
514 isInt32Immediate(Op1.getOperand(1), Value)) {
515 Op1 = Op1.getOperand(0);
516 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value;
518 if (Op1Opc == ISD::AND) {
519 // The AND mask might not be a constant, and we need to make sure that
520 // if we're going to fold the masking with the insert, all bits not
521 // know to be zero in the mask are known to be one.
523 CurDAG->computeKnownBits(Op1.getOperand(1), MKZ, MKO);
524 bool CanFoldMask = InsertMask == MKO.getZExtValue();
526 unsigned SHOpc = Op1.getOperand(0).getOpcode();
527 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && CanFoldMask &&
528 isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) {
529 // Note that Value must be in range here (less than 32) because
530 // otherwise there would not be any bits set in InsertMask.
531 Op1 = Op1.getOperand(0).getOperand(0);
532 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value;
537 SDValue Ops[] = { Op0, Op1, getI32Imm(SH), getI32Imm(MB),
539 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops);
545 // Predict the number of instructions that would be generated by calling
547 static unsigned SelectInt64CountDirect(int64_t Imm) {
548 // Assume no remaining bits.
549 unsigned Remainder = 0;
550 // Assume no shift required.
553 // If it can't be represented as a 32 bit value.
554 if (!isInt<32>(Imm)) {
555 Shift = countTrailingZeros<uint64_t>(Imm);
556 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
558 // If the shifted value fits 32 bits.
559 if (isInt<32>(ImmSh)) {
560 // Go with the shifted value.
563 // Still stuck with a 64 bit value.
570 // Intermediate operand.
573 // Handle first 32 bits.
574 unsigned Lo = Imm & 0xFFFF;
575 unsigned Hi = (Imm >> 16) & 0xFFFF;
578 if (isInt<16>(Imm)) {
582 // Handle the Hi bits and Lo bits.
589 // If no shift, we're done.
590 if (!Shift) return Result;
592 // Shift for next step if the upper 32-bits were not zero.
596 // Add in the last bits as required.
597 if ((Hi = (Remainder >> 16) & 0xFFFF))
599 if ((Lo = Remainder & 0xFFFF))
605 static uint64_t Rot64(uint64_t Imm, unsigned R) {
606 return (Imm << R) | (Imm >> (64 - R));
609 static unsigned SelectInt64Count(int64_t Imm) {
610 unsigned Count = SelectInt64CountDirect(Imm);
614 for (unsigned r = 1; r < 63; ++r) {
615 uint64_t RImm = Rot64(Imm, r);
616 unsigned RCount = SelectInt64CountDirect(RImm) + 1;
617 Count = std::min(Count, RCount);
619 // See comments in SelectInt64 for an explanation of the logic below.
620 unsigned LS = findLastSet(RImm);
624 uint64_t OnesMask = -(int64_t) (UINT64_C(1) << (LS+1));
625 uint64_t RImmWithOnes = RImm | OnesMask;
627 RCount = SelectInt64CountDirect(RImmWithOnes) + 1;
628 Count = std::min(Count, RCount);
634 // Select a 64-bit constant. For cost-modeling purposes, SelectInt64Count
635 // (above) needs to be kept in sync with this function.
636 static SDNode *SelectInt64Direct(SelectionDAG *CurDAG, SDLoc dl, int64_t Imm) {
637 // Assume no remaining bits.
638 unsigned Remainder = 0;
639 // Assume no shift required.
642 // If it can't be represented as a 32 bit value.
643 if (!isInt<32>(Imm)) {
644 Shift = countTrailingZeros<uint64_t>(Imm);
645 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
647 // If the shifted value fits 32 bits.
648 if (isInt<32>(ImmSh)) {
649 // Go with the shifted value.
652 // Still stuck with a 64 bit value.
659 // Intermediate operand.
662 // Handle first 32 bits.
663 unsigned Lo = Imm & 0xFFFF;
664 unsigned Hi = (Imm >> 16) & 0xFFFF;
666 auto getI32Imm = [CurDAG](unsigned Imm) {
667 return CurDAG->getTargetConstant(Imm, MVT::i32);
671 if (isInt<16>(Imm)) {
673 Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo));
675 // Handle the Hi bits.
676 unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8;
677 Result = CurDAG->getMachineNode(OpC, dl, MVT::i64, getI32Imm(Hi));
679 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
680 SDValue(Result, 0), getI32Imm(Lo));
683 Result = CurDAG->getMachineNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi));
686 // If no shift, we're done.
687 if (!Shift) return Result;
689 // Shift for next step if the upper 32-bits were not zero.
691 Result = CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64,
694 getI32Imm(63 - Shift));
697 // Add in the last bits as required.
698 if ((Hi = (Remainder >> 16) & 0xFFFF)) {
699 Result = CurDAG->getMachineNode(PPC::ORIS8, dl, MVT::i64,
700 SDValue(Result, 0), getI32Imm(Hi));
702 if ((Lo = Remainder & 0xFFFF)) {
703 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
704 SDValue(Result, 0), getI32Imm(Lo));
710 static SDNode *SelectInt64(SelectionDAG *CurDAG, SDLoc dl, int64_t Imm) {
711 unsigned Count = SelectInt64CountDirect(Imm);
713 return SelectInt64Direct(CurDAG, dl, Imm);
720 for (unsigned r = 1; r < 63; ++r) {
721 uint64_t RImm = Rot64(Imm, r);
722 unsigned RCount = SelectInt64CountDirect(RImm) + 1;
723 if (RCount < Count) {
730 // If the immediate to generate has many trailing zeros, it might be
731 // worthwhile to generate a rotated value with too many leading ones
732 // (because that's free with li/lis's sign-extension semantics), and then
733 // mask them off after rotation.
735 unsigned LS = findLastSet(RImm);
736 // We're adding (63-LS) higher-order ones, and we expect to mask them off
737 // after performing the inverse rotation by (64-r). So we need that:
738 // 63-LS == 64-r => LS == r-1
742 uint64_t OnesMask = -(int64_t) (UINT64_C(1) << (LS+1));
743 uint64_t RImmWithOnes = RImm | OnesMask;
745 RCount = SelectInt64CountDirect(RImmWithOnes) + 1;
746 if (RCount < Count) {
749 MatImm = RImmWithOnes;
755 return SelectInt64Direct(CurDAG, dl, Imm);
757 auto getI32Imm = [CurDAG](unsigned Imm) {
758 return CurDAG->getTargetConstant(Imm, MVT::i32);
761 SDValue Val = SDValue(SelectInt64Direct(CurDAG, dl, MatImm), 0);
762 return CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64, Val,
763 getI32Imm(64 - RMin), getI32Imm(MaskEnd));
766 // Select a 64-bit constant.
767 static SDNode *SelectInt64(SelectionDAG *CurDAG, SDNode *N) {
771 int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue();
772 return SelectInt64(CurDAG, dl, Imm);
776 class BitPermutationSelector {
780 // The bit number in the value, using a convention where bit 0 is the
789 ValueBit(SDValue V, unsigned I, Kind K = Variable)
790 : V(V), Idx(I), K(K) {}
791 ValueBit(Kind K = Variable)
792 : V(SDValue(nullptr, 0)), Idx(UINT32_MAX), K(K) {}
794 bool isZero() const {
795 return K == ConstZero;
798 bool hasValue() const {
799 return K == Variable;
802 SDValue getValue() const {
803 assert(hasValue() && "Cannot get the value of a constant bit");
807 unsigned getValueBitIndex() const {
808 assert(hasValue() && "Cannot get the value bit index of a constant bit");
813 // A bit group has the same underlying value and the same rotate factor.
817 unsigned StartIdx, EndIdx;
819 // This rotation amount assumes that the lower 32 bits of the quantity are
820 // replicated in the high 32 bits by the rotation operator (which is done
821 // by rlwinm and friends in 64-bit mode).
823 // Did converting to Repl32 == true change the rotation factor? If it did,
824 // it decreased it by 32.
826 // Was this group coalesced after setting Repl32 to true?
827 bool Repl32Coalesced;
829 BitGroup(SDValue V, unsigned R, unsigned S, unsigned E)
830 : V(V), RLAmt(R), StartIdx(S), EndIdx(E), Repl32(false), Repl32CR(false),
831 Repl32Coalesced(false) {
832 DEBUG(dbgs() << "\tbit group for " << V.getNode() << " RLAmt = " << R <<
833 " [" << S << ", " << E << "]\n");
837 // Information on each (Value, RLAmt) pair (like the number of groups
838 // associated with each) used to choose the lowering method.
839 struct ValueRotInfo {
843 unsigned FirstGroupStartIdx;
847 : RLAmt(UINT32_MAX), NumGroups(0), FirstGroupStartIdx(UINT32_MAX),
850 // For sorting (in reverse order) by NumGroups, and then by
851 // FirstGroupStartIdx.
852 bool operator < (const ValueRotInfo &Other) const {
853 // We need to sort so that the non-Repl32 come first because, when we're
854 // doing masking, the Repl32 bit groups might be subsumed into the 64-bit
855 // masking operation.
856 if (Repl32 < Other.Repl32)
858 else if (Repl32 > Other.Repl32)
860 else if (NumGroups > Other.NumGroups)
862 else if (NumGroups < Other.NumGroups)
864 else if (FirstGroupStartIdx < Other.FirstGroupStartIdx)
870 // Return true if something interesting was deduced, return false if we're
871 // providing only a generic representation of V (or something else likewise
872 // uninteresting for instruction selection).
873 bool getValueBits(SDValue V, SmallVector<ValueBit, 64> &Bits) {
874 switch (V.getOpcode()) {
877 if (isa<ConstantSDNode>(V.getOperand(1))) {
878 unsigned RotAmt = V.getConstantOperandVal(1);
880 SmallVector<ValueBit, 64> LHSBits(Bits.size());
881 getValueBits(V.getOperand(0), LHSBits);
883 for (unsigned i = 0; i < Bits.size(); ++i)
884 Bits[i] = LHSBits[i < RotAmt ? i + (Bits.size() - RotAmt) : i - RotAmt];
890 if (isa<ConstantSDNode>(V.getOperand(1))) {
891 unsigned ShiftAmt = V.getConstantOperandVal(1);
893 SmallVector<ValueBit, 64> LHSBits(Bits.size());
894 getValueBits(V.getOperand(0), LHSBits);
896 for (unsigned i = ShiftAmt; i < Bits.size(); ++i)
897 Bits[i] = LHSBits[i - ShiftAmt];
899 for (unsigned i = 0; i < ShiftAmt; ++i)
900 Bits[i] = ValueBit(ValueBit::ConstZero);
906 if (isa<ConstantSDNode>(V.getOperand(1))) {
907 unsigned ShiftAmt = V.getConstantOperandVal(1);
909 SmallVector<ValueBit, 64> LHSBits(Bits.size());
910 getValueBits(V.getOperand(0), LHSBits);
912 for (unsigned i = 0; i < Bits.size() - ShiftAmt; ++i)
913 Bits[i] = LHSBits[i + ShiftAmt];
915 for (unsigned i = Bits.size() - ShiftAmt; i < Bits.size(); ++i)
916 Bits[i] = ValueBit(ValueBit::ConstZero);
922 if (isa<ConstantSDNode>(V.getOperand(1))) {
923 uint64_t Mask = V.getConstantOperandVal(1);
925 SmallVector<ValueBit, 64> LHSBits(Bits.size());
926 bool LHSTrivial = getValueBits(V.getOperand(0), LHSBits);
928 for (unsigned i = 0; i < Bits.size(); ++i)
929 if (((Mask >> i) & 1) == 1)
930 Bits[i] = LHSBits[i];
932 Bits[i] = ValueBit(ValueBit::ConstZero);
934 // Mark this as interesting, only if the LHS was also interesting. This
935 // prevents the overall procedure from matching a single immediate 'and'
936 // (which is non-optimal because such an and might be folded with other
937 // things if we don't select it here).
942 SmallVector<ValueBit, 64> LHSBits(Bits.size()), RHSBits(Bits.size());
943 getValueBits(V.getOperand(0), LHSBits);
944 getValueBits(V.getOperand(1), RHSBits);
946 bool AllDisjoint = true;
947 for (unsigned i = 0; i < Bits.size(); ++i)
948 if (LHSBits[i].isZero())
949 Bits[i] = RHSBits[i];
950 else if (RHSBits[i].isZero())
951 Bits[i] = LHSBits[i];
964 for (unsigned i = 0; i < Bits.size(); ++i)
965 Bits[i] = ValueBit(V, i);
970 // For each value (except the constant ones), compute the left-rotate amount
971 // to get it from its original to final position.
972 void computeRotationAmounts() {
974 RLAmt.resize(Bits.size());
975 for (unsigned i = 0; i < Bits.size(); ++i)
976 if (Bits[i].hasValue()) {
977 unsigned VBI = Bits[i].getValueBitIndex();
981 RLAmt[i] = Bits.size() - (VBI - i);
982 } else if (Bits[i].isZero()) {
984 RLAmt[i] = UINT32_MAX;
986 llvm_unreachable("Unknown value bit type");
990 // Collect groups of consecutive bits with the same underlying value and
991 // rotation factor. If we're doing late masking, we ignore zeros, otherwise
992 // they break up groups.
993 void collectBitGroups(bool LateMask) {
996 unsigned LastRLAmt = RLAmt[0];
997 SDValue LastValue = Bits[0].hasValue() ? Bits[0].getValue() : SDValue();
998 unsigned LastGroupStartIdx = 0;
999 for (unsigned i = 1; i < Bits.size(); ++i) {
1000 unsigned ThisRLAmt = RLAmt[i];
1001 SDValue ThisValue = Bits[i].hasValue() ? Bits[i].getValue() : SDValue();
1002 if (LateMask && !ThisValue) {
1003 ThisValue = LastValue;
1004 ThisRLAmt = LastRLAmt;
1005 // If we're doing late masking, then the first bit group always starts
1006 // at zero (even if the first bits were zero).
1007 if (BitGroups.empty())
1008 LastGroupStartIdx = 0;
1011 // If this bit has the same underlying value and the same rotate factor as
1012 // the last one, then they're part of the same group.
1013 if (ThisRLAmt == LastRLAmt && ThisValue == LastValue)
1016 if (LastValue.getNode())
1017 BitGroups.push_back(BitGroup(LastValue, LastRLAmt, LastGroupStartIdx,
1019 LastRLAmt = ThisRLAmt;
1020 LastValue = ThisValue;
1021 LastGroupStartIdx = i;
1023 if (LastValue.getNode())
1024 BitGroups.push_back(BitGroup(LastValue, LastRLAmt, LastGroupStartIdx,
1027 if (BitGroups.empty())
1030 // We might be able to combine the first and last groups.
1031 if (BitGroups.size() > 1) {
1032 // If the first and last groups are the same, then remove the first group
1033 // in favor of the last group, making the ending index of the last group
1034 // equal to the ending index of the to-be-removed first group.
1035 if (BitGroups[0].StartIdx == 0 &&
1036 BitGroups[BitGroups.size()-1].EndIdx == Bits.size()-1 &&
1037 BitGroups[0].V == BitGroups[BitGroups.size()-1].V &&
1038 BitGroups[0].RLAmt == BitGroups[BitGroups.size()-1].RLAmt) {
1039 DEBUG(dbgs() << "\tcombining final bit group with inital one\n");
1040 BitGroups[BitGroups.size()-1].EndIdx = BitGroups[0].EndIdx;
1041 BitGroups.erase(BitGroups.begin());
1046 // Take all (SDValue, RLAmt) pairs and sort them by the number of groups
1047 // associated with each. If there is a degeneracy, pick the one that occurs
1048 // first (in the final value).
1049 void collectValueRotInfo() {
1052 for (auto &BG : BitGroups) {
1053 unsigned RLAmtKey = BG.RLAmt + (BG.Repl32 ? 64 : 0);
1054 ValueRotInfo &VRI = ValueRots[std::make_pair(BG.V, RLAmtKey)];
1056 VRI.RLAmt = BG.RLAmt;
1057 VRI.Repl32 = BG.Repl32;
1059 VRI.FirstGroupStartIdx = std::min(VRI.FirstGroupStartIdx, BG.StartIdx);
1062 // Now that we've collected the various ValueRotInfo instances, we need to
1064 ValueRotsVec.clear();
1065 for (auto &I : ValueRots) {
1066 ValueRotsVec.push_back(I.second);
1068 std::sort(ValueRotsVec.begin(), ValueRotsVec.end());
1071 // In 64-bit mode, rlwinm and friends have a rotation operator that
1072 // replicates the low-order 32 bits into the high-order 32-bits. The mask
1073 // indices of these instructions can only be in the lower 32 bits, so they
1074 // can only represent some 64-bit bit groups. However, when they can be used,
1075 // the 32-bit replication can be used to represent, as a single bit group,
1076 // otherwise separate bit groups. We'll convert to replicated-32-bit bit
1077 // groups when possible. Returns true if any of the bit groups were
1079 void assignRepl32BitGroups() {
1080 // If we have bits like this:
1082 // Indices: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1083 // V bits: ... 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24
1084 // Groups: | RLAmt = 8 | RLAmt = 40 |
1086 // But, making use of a 32-bit operation that replicates the low-order 32
1087 // bits into the high-order 32 bits, this can be one bit group with a RLAmt
1090 auto IsAllLow32 = [this](BitGroup & BG) {
1091 if (BG.StartIdx <= BG.EndIdx) {
1092 for (unsigned i = BG.StartIdx; i <= BG.EndIdx; ++i) {
1093 if (!Bits[i].hasValue())
1095 if (Bits[i].getValueBitIndex() >= 32)
1099 for (unsigned i = BG.StartIdx; i < Bits.size(); ++i) {
1100 if (!Bits[i].hasValue())
1102 if (Bits[i].getValueBitIndex() >= 32)
1105 for (unsigned i = 0; i <= BG.EndIdx; ++i) {
1106 if (!Bits[i].hasValue())
1108 if (Bits[i].getValueBitIndex() >= 32)
1116 for (auto &BG : BitGroups) {
1117 if (BG.StartIdx < 32 && BG.EndIdx < 32) {
1118 if (IsAllLow32(BG)) {
1119 if (BG.RLAmt >= 32) {
1126 DEBUG(dbgs() << "\t32-bit replicated bit group for " <<
1127 BG.V.getNode() << " RLAmt = " << BG.RLAmt <<
1128 " [" << BG.StartIdx << ", " << BG.EndIdx << "]\n");
1133 // Now walk through the bit groups, consolidating where possible.
1134 for (auto I = BitGroups.begin(); I != BitGroups.end();) {
1135 // We might want to remove this bit group by merging it with the previous
1136 // group (which might be the ending group).
1137 auto IP = (I == BitGroups.begin()) ?
1138 std::prev(BitGroups.end()) : std::prev(I);
1139 if (I->Repl32 && IP->Repl32 && I->V == IP->V && I->RLAmt == IP->RLAmt &&
1140 I->StartIdx == (IP->EndIdx + 1) % 64 && I != IP) {
1142 DEBUG(dbgs() << "\tcombining 32-bit replicated bit group for " <<
1143 I->V.getNode() << " RLAmt = " << I->RLAmt <<
1144 " [" << I->StartIdx << ", " << I->EndIdx <<
1145 "] with group with range [" <<
1146 IP->StartIdx << ", " << IP->EndIdx << "]\n");
1148 IP->EndIdx = I->EndIdx;
1149 IP->Repl32CR = IP->Repl32CR || I->Repl32CR;
1150 IP->Repl32Coalesced = true;
1151 I = BitGroups.erase(I);
1154 // There is a special case worth handling: If there is a single group
1155 // covering the entire upper 32 bits, and it can be merged with both
1156 // the next and previous groups (which might be the same group), then
1157 // do so. If it is the same group (so there will be only one group in
1158 // total), then we need to reverse the order of the range so that it
1159 // covers the entire 64 bits.
1160 if (I->StartIdx == 32 && I->EndIdx == 63) {
1161 assert(std::next(I) == BitGroups.end() &&
1162 "bit group ends at index 63 but there is another?");
1163 auto IN = BitGroups.begin();
1165 if (IP->Repl32 && IN->Repl32 && I->V == IP->V && I->V == IN->V &&
1166 (I->RLAmt % 32) == IP->RLAmt && (I->RLAmt % 32) == IN->RLAmt &&
1167 IP->EndIdx == 31 && IN->StartIdx == 0 && I != IP &&
1170 DEBUG(dbgs() << "\tcombining bit group for " <<
1171 I->V.getNode() << " RLAmt = " << I->RLAmt <<
1172 " [" << I->StartIdx << ", " << I->EndIdx <<
1173 "] with 32-bit replicated groups with ranges [" <<
1174 IP->StartIdx << ", " << IP->EndIdx << "] and [" <<
1175 IN->StartIdx << ", " << IN->EndIdx << "]\n");
1178 // There is only one other group; change it to cover the whole
1179 // range (backward, so that it can still be Repl32 but cover the
1180 // whole 64-bit range).
1183 IP->Repl32CR = IP->Repl32CR || I->RLAmt >= 32;
1184 IP->Repl32Coalesced = true;
1185 I = BitGroups.erase(I);
1187 // There are two separate groups, one before this group and one
1188 // after us (at the beginning). We're going to remove this group,
1189 // but also the group at the very beginning.
1190 IP->EndIdx = IN->EndIdx;
1191 IP->Repl32CR = IP->Repl32CR || IN->Repl32CR || I->RLAmt >= 32;
1192 IP->Repl32Coalesced = true;
1193 I = BitGroups.erase(I);
1194 BitGroups.erase(BitGroups.begin());
1197 // This must be the last group in the vector (and we might have
1198 // just invalidated the iterator above), so break here.
1208 SDValue getI32Imm(unsigned Imm) {
1209 return CurDAG->getTargetConstant(Imm, MVT::i32);
1212 uint64_t getZerosMask() {
1214 for (unsigned i = 0; i < Bits.size(); ++i) {
1215 if (Bits[i].hasValue())
1217 Mask |= (UINT64_C(1) << i);
1223 // Depending on the number of groups for a particular value, it might be
1224 // better to rotate, mask explicitly (using andi/andis), and then or the
1225 // result. Select this part of the result first.
1226 void SelectAndParts32(SDLoc dl, SDValue &Res, unsigned *InstCnt) {
1227 if (BPermRewriterNoMasking)
1230 for (ValueRotInfo &VRI : ValueRotsVec) {
1232 for (unsigned i = 0; i < Bits.size(); ++i) {
1233 if (!Bits[i].hasValue() || Bits[i].getValue() != VRI.V)
1235 if (RLAmt[i] != VRI.RLAmt)
1240 // Compute the masks for andi/andis that would be necessary.
1241 unsigned ANDIMask = (Mask & UINT16_MAX), ANDISMask = Mask >> 16;
1242 assert((ANDIMask != 0 || ANDISMask != 0) &&
1243 "No set bits in mask for value bit groups");
1244 bool NeedsRotate = VRI.RLAmt != 0;
1246 // We're trying to minimize the number of instructions. If we have one
1247 // group, using one of andi/andis can break even. If we have three
1248 // groups, we can use both andi and andis and break even (to use both
1249 // andi and andis we also need to or the results together). We need four
1250 // groups if we also need to rotate. To use andi/andis we need to do more
1251 // than break even because rotate-and-mask instructions tend to be easier
1254 // FIXME: We've biased here against using andi/andis, which is right for
1255 // POWER cores, but not optimal everywhere. For example, on the A2,
1256 // andi/andis have single-cycle latency whereas the rotate-and-mask
1257 // instructions take two cycles, and it would be better to bias toward
1258 // andi/andis in break-even cases.
1260 unsigned NumAndInsts = (unsigned) NeedsRotate +
1261 (unsigned) (ANDIMask != 0) +
1262 (unsigned) (ANDISMask != 0) +
1263 (unsigned) (ANDIMask != 0 && ANDISMask != 0) +
1264 (unsigned) (bool) Res;
1266 DEBUG(dbgs() << "\t\trotation groups for " << VRI.V.getNode() <<
1267 " RL: " << VRI.RLAmt << ":" <<
1268 "\n\t\t\tisel using masking: " << NumAndInsts <<
1269 " using rotates: " << VRI.NumGroups << "\n");
1271 if (NumAndInsts >= VRI.NumGroups)
1274 DEBUG(dbgs() << "\t\t\t\tusing masking\n");
1276 if (InstCnt) *InstCnt += NumAndInsts;
1281 { VRI.V, getI32Imm(VRI.RLAmt), getI32Imm(0), getI32Imm(31) };
1282 VRot = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32,
1288 SDValue ANDIVal, ANDISVal;
1290 ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo, dl, MVT::i32,
1291 VRot, getI32Imm(ANDIMask)), 0);
1293 ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo, dl, MVT::i32,
1294 VRot, getI32Imm(ANDISMask)), 0);
1298 TotalVal = ANDISVal;
1302 TotalVal = SDValue(CurDAG->getMachineNode(PPC::OR, dl, MVT::i32,
1303 ANDIVal, ANDISVal), 0);
1308 Res = SDValue(CurDAG->getMachineNode(PPC::OR, dl, MVT::i32,
1311 // Now, remove all groups with this underlying value and rotation
1313 for (auto I = BitGroups.begin(); I != BitGroups.end();) {
1314 if (I->V == VRI.V && I->RLAmt == VRI.RLAmt)
1315 I = BitGroups.erase(I);
1322 // Instruction selection for the 32-bit case.
1323 SDNode *Select32(SDNode *N, bool LateMask, unsigned *InstCnt) {
1327 if (InstCnt) *InstCnt = 0;
1329 // Take care of cases that should use andi/andis first.
1330 SelectAndParts32(dl, Res, InstCnt);
1332 // If we've not yet selected a 'starting' instruction, and we have no zeros
1333 // to fill in, select the (Value, RLAmt) with the highest priority (largest
1334 // number of groups), and start with this rotated value.
1335 if ((!HasZeros || LateMask) && !Res) {
1336 ValueRotInfo &VRI = ValueRotsVec[0];
1338 if (InstCnt) *InstCnt += 1;
1340 { VRI.V, getI32Imm(VRI.RLAmt), getI32Imm(0), getI32Imm(31) };
1341 Res = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0);
1346 // Now, remove all groups with this underlying value and rotation factor.
1347 for (auto I = BitGroups.begin(); I != BitGroups.end();) {
1348 if (I->V == VRI.V && I->RLAmt == VRI.RLAmt)
1349 I = BitGroups.erase(I);
1355 if (InstCnt) *InstCnt += BitGroups.size();
1357 // Insert the other groups (one at a time).
1358 for (auto &BG : BitGroups) {
1361 { BG.V, getI32Imm(BG.RLAmt), getI32Imm(Bits.size() - BG.EndIdx - 1),
1362 getI32Imm(Bits.size() - BG.StartIdx - 1) };
1363 Res = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0);
1366 { Res, BG.V, getI32Imm(BG.RLAmt), getI32Imm(Bits.size() - BG.EndIdx - 1),
1367 getI32Imm(Bits.size() - BG.StartIdx - 1) };
1368 Res = SDValue(CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops), 0);
1373 unsigned Mask = (unsigned) getZerosMask();
1375 unsigned ANDIMask = (Mask & UINT16_MAX), ANDISMask = Mask >> 16;
1376 assert((ANDIMask != 0 || ANDISMask != 0) &&
1377 "No set bits in zeros mask?");
1379 if (InstCnt) *InstCnt += (unsigned) (ANDIMask != 0) +
1380 (unsigned) (ANDISMask != 0) +
1381 (unsigned) (ANDIMask != 0 && ANDISMask != 0);
1383 SDValue ANDIVal, ANDISVal;
1385 ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo, dl, MVT::i32,
1386 Res, getI32Imm(ANDIMask)), 0);
1388 ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo, dl, MVT::i32,
1389 Res, getI32Imm(ANDISMask)), 0);
1396 Res = SDValue(CurDAG->getMachineNode(PPC::OR, dl, MVT::i32,
1397 ANDIVal, ANDISVal), 0);
1400 return Res.getNode();
1403 unsigned SelectRotMask64Count(unsigned RLAmt, bool Repl32,
1404 unsigned MaskStart, unsigned MaskEnd,
1406 // In the notation used by the instructions, 'start' and 'end' are reversed
1407 // because bits are counted from high to low order.
1408 unsigned InstMaskStart = 64 - MaskEnd - 1,
1409 InstMaskEnd = 64 - MaskStart - 1;
1414 if ((!IsIns && (InstMaskEnd == 63 || InstMaskStart == 0)) ||
1415 InstMaskEnd == 63 - RLAmt)
1421 // For 64-bit values, not all combinations of rotates and masks are
1422 // available. Produce one if it is available.
1423 SDValue SelectRotMask64(SDValue V, SDLoc dl, unsigned RLAmt, bool Repl32,
1424 unsigned MaskStart, unsigned MaskEnd,
1425 unsigned *InstCnt = nullptr) {
1426 // In the notation used by the instructions, 'start' and 'end' are reversed
1427 // because bits are counted from high to low order.
1428 unsigned InstMaskStart = 64 - MaskEnd - 1,
1429 InstMaskEnd = 64 - MaskStart - 1;
1431 if (InstCnt) *InstCnt += 1;
1434 // This rotation amount assumes that the lower 32 bits of the quantity
1435 // are replicated in the high 32 bits by the rotation operator (which is
1436 // done by rlwinm and friends).
1437 assert(InstMaskStart >= 32 && "Mask cannot start out of range");
1438 assert(InstMaskEnd >= 32 && "Mask cannot end out of range");
1440 { V, getI32Imm(RLAmt), getI32Imm(InstMaskStart - 32),
1441 getI32Imm(InstMaskEnd - 32) };
1442 return SDValue(CurDAG->getMachineNode(PPC::RLWINM8, dl, MVT::i64,
1446 if (InstMaskEnd == 63) {
1448 { V, getI32Imm(RLAmt), getI32Imm(InstMaskStart) };
1449 return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Ops), 0);
1452 if (InstMaskStart == 0) {
1454 { V, getI32Imm(RLAmt), getI32Imm(InstMaskEnd) };
1455 return SDValue(CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64, Ops), 0);
1458 if (InstMaskEnd == 63 - RLAmt) {
1460 { V, getI32Imm(RLAmt), getI32Imm(InstMaskStart) };
1461 return SDValue(CurDAG->getMachineNode(PPC::RLDIC, dl, MVT::i64, Ops), 0);
1464 // We cannot do this with a single instruction, so we'll use two. The
1465 // problem is that we're not free to choose both a rotation amount and mask
1466 // start and end independently. We can choose an arbitrary mask start and
1467 // end, but then the rotation amount is fixed. Rotation, however, can be
1468 // inverted, and so by applying an "inverse" rotation first, we can get the
1470 if (InstCnt) *InstCnt += 1;
1472 // The rotation mask for the second instruction must be MaskStart.
1473 unsigned RLAmt2 = MaskStart;
1474 // The first instruction must rotate V so that the overall rotation amount
1476 unsigned RLAmt1 = (64 + RLAmt - RLAmt2) % 64;
1478 V = SelectRotMask64(V, dl, RLAmt1, false, 0, 63);
1479 return SelectRotMask64(V, dl, RLAmt2, false, MaskStart, MaskEnd);
1482 // For 64-bit values, not all combinations of rotates and masks are
1483 // available. Produce a rotate-mask-and-insert if one is available.
1484 SDValue SelectRotMaskIns64(SDValue Base, SDValue V, SDLoc dl, unsigned RLAmt,
1485 bool Repl32, unsigned MaskStart,
1486 unsigned MaskEnd, unsigned *InstCnt = nullptr) {
1487 // In the notation used by the instructions, 'start' and 'end' are reversed
1488 // because bits are counted from high to low order.
1489 unsigned InstMaskStart = 64 - MaskEnd - 1,
1490 InstMaskEnd = 64 - MaskStart - 1;
1492 if (InstCnt) *InstCnt += 1;
1495 // This rotation amount assumes that the lower 32 bits of the quantity
1496 // are replicated in the high 32 bits by the rotation operator (which is
1497 // done by rlwinm and friends).
1498 assert(InstMaskStart >= 32 && "Mask cannot start out of range");
1499 assert(InstMaskEnd >= 32 && "Mask cannot end out of range");
1501 { Base, V, getI32Imm(RLAmt), getI32Imm(InstMaskStart - 32),
1502 getI32Imm(InstMaskEnd - 32) };
1503 return SDValue(CurDAG->getMachineNode(PPC::RLWIMI8, dl, MVT::i64,
1507 if (InstMaskEnd == 63 - RLAmt) {
1509 { Base, V, getI32Imm(RLAmt), getI32Imm(InstMaskStart) };
1510 return SDValue(CurDAG->getMachineNode(PPC::RLDIMI, dl, MVT::i64, Ops), 0);
1513 // We cannot do this with a single instruction, so we'll use two. The
1514 // problem is that we're not free to choose both a rotation amount and mask
1515 // start and end independently. We can choose an arbitrary mask start and
1516 // end, but then the rotation amount is fixed. Rotation, however, can be
1517 // inverted, and so by applying an "inverse" rotation first, we can get the
1519 if (InstCnt) *InstCnt += 1;
1521 // The rotation mask for the second instruction must be MaskStart.
1522 unsigned RLAmt2 = MaskStart;
1523 // The first instruction must rotate V so that the overall rotation amount
1525 unsigned RLAmt1 = (64 + RLAmt - RLAmt2) % 64;
1527 V = SelectRotMask64(V, dl, RLAmt1, false, 0, 63);
1528 return SelectRotMaskIns64(Base, V, dl, RLAmt2, false, MaskStart, MaskEnd);
1531 void SelectAndParts64(SDLoc dl, SDValue &Res, unsigned *InstCnt) {
1532 if (BPermRewriterNoMasking)
1535 // The idea here is the same as in the 32-bit version, but with additional
1536 // complications from the fact that Repl32 might be true. Because we
1537 // aggressively convert bit groups to Repl32 form (which, for small
1538 // rotation factors, involves no other change), and then coalesce, it might
1539 // be the case that a single 64-bit masking operation could handle both
1540 // some Repl32 groups and some non-Repl32 groups. If converting to Repl32
1541 // form allowed coalescing, then we must use a 32-bit rotaton in order to
1542 // completely capture the new combined bit group.
1544 for (ValueRotInfo &VRI : ValueRotsVec) {
1547 // We need to add to the mask all bits from the associated bit groups.
1548 // If Repl32 is false, we need to add bits from bit groups that have
1549 // Repl32 true, but are trivially convertable to Repl32 false. Such a
1550 // group is trivially convertable if it overlaps only with the lower 32
1551 // bits, and the group has not been coalesced.
1552 auto MatchingBG = [VRI](BitGroup &BG) {
1556 unsigned EffRLAmt = BG.RLAmt;
1557 if (!VRI.Repl32 && BG.Repl32) {
1558 if (BG.StartIdx < 32 && BG.EndIdx < 32 && BG.StartIdx <= BG.EndIdx &&
1559 !BG.Repl32Coalesced) {
1565 } else if (VRI.Repl32 != BG.Repl32) {
1569 if (VRI.RLAmt != EffRLAmt)
1575 for (auto &BG : BitGroups) {
1576 if (!MatchingBG(BG))
1579 if (BG.StartIdx <= BG.EndIdx) {
1580 for (unsigned i = BG.StartIdx; i <= BG.EndIdx; ++i)
1581 Mask |= (UINT64_C(1) << i);
1583 for (unsigned i = BG.StartIdx; i < Bits.size(); ++i)
1584 Mask |= (UINT64_C(1) << i);
1585 for (unsigned i = 0; i <= BG.EndIdx; ++i)
1586 Mask |= (UINT64_C(1) << i);
1590 // We can use the 32-bit andi/andis technique if the mask does not
1591 // require any higher-order bits. This can save an instruction compared
1592 // to always using the general 64-bit technique.
1593 bool Use32BitInsts = isUInt<32>(Mask);
1594 // Compute the masks for andi/andis that would be necessary.
1595 unsigned ANDIMask = (Mask & UINT16_MAX),
1596 ANDISMask = (Mask >> 16) & UINT16_MAX;
1598 bool NeedsRotate = VRI.RLAmt || (VRI.Repl32 && !isUInt<32>(Mask));
1600 unsigned NumAndInsts = (unsigned) NeedsRotate +
1601 (unsigned) (bool) Res;
1603 NumAndInsts += (unsigned) (ANDIMask != 0) + (unsigned) (ANDISMask != 0) +
1604 (unsigned) (ANDIMask != 0 && ANDISMask != 0);
1606 NumAndInsts += SelectInt64Count(Mask) + /* and */ 1;
1608 unsigned NumRLInsts = 0;
1609 bool FirstBG = true;
1610 for (auto &BG : BitGroups) {
1611 if (!MatchingBG(BG))
1614 SelectRotMask64Count(BG.RLAmt, BG.Repl32, BG.StartIdx, BG.EndIdx,
1619 DEBUG(dbgs() << "\t\trotation groups for " << VRI.V.getNode() <<
1620 " RL: " << VRI.RLAmt << (VRI.Repl32 ? " (32):" : ":") <<
1621 "\n\t\t\tisel using masking: " << NumAndInsts <<
1622 " using rotates: " << NumRLInsts << "\n");
1624 // When we'd use andi/andis, we bias toward using the rotates (andi only
1625 // has a record form, and is cracked on POWER cores). However, when using
1626 // general 64-bit constant formation, bias toward the constant form,
1627 // because that exposes more opportunities for CSE.
1628 if (NumAndInsts > NumRLInsts)
1630 if (Use32BitInsts && NumAndInsts == NumRLInsts)
1633 DEBUG(dbgs() << "\t\t\t\tusing masking\n");
1635 if (InstCnt) *InstCnt += NumAndInsts;
1638 // We actually need to generate a rotation if we have a non-zero rotation
1639 // factor or, in the Repl32 case, if we care about any of the
1640 // higher-order replicated bits. In the latter case, we generate a mask
1641 // backward so that it actually includes the entire 64 bits.
1642 if (VRI.RLAmt || (VRI.Repl32 && !isUInt<32>(Mask)))
1643 VRot = SelectRotMask64(VRI.V, dl, VRI.RLAmt, VRI.Repl32,
1644 VRI.Repl32 ? 31 : 0, VRI.Repl32 ? 30 : 63);
1649 if (Use32BitInsts) {
1650 assert((ANDIMask != 0 || ANDISMask != 0) &&
1651 "No set bits in mask when using 32-bit ands for 64-bit value");
1653 SDValue ANDIVal, ANDISVal;
1655 ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo8, dl, MVT::i64,
1656 VRot, getI32Imm(ANDIMask)), 0);
1658 ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo8, dl, MVT::i64,
1659 VRot, getI32Imm(ANDISMask)), 0);
1662 TotalVal = ANDISVal;
1666 TotalVal = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
1667 ANDIVal, ANDISVal), 0);
1669 TotalVal = SDValue(SelectInt64(CurDAG, dl, Mask), 0);
1671 SDValue(CurDAG->getMachineNode(PPC::AND8, dl, MVT::i64,
1672 VRot, TotalVal), 0);
1678 Res = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
1681 // Now, remove all groups with this underlying value and rotation
1683 for (auto I = BitGroups.begin(); I != BitGroups.end();) {
1685 I = BitGroups.erase(I);
1692 // Instruction selection for the 64-bit case.
1693 SDNode *Select64(SDNode *N, bool LateMask, unsigned *InstCnt) {
1697 if (InstCnt) *InstCnt = 0;
1699 // Take care of cases that should use andi/andis first.
1700 SelectAndParts64(dl, Res, InstCnt);
1702 // If we've not yet selected a 'starting' instruction, and we have no zeros
1703 // to fill in, select the (Value, RLAmt) with the highest priority (largest
1704 // number of groups), and start with this rotated value.
1705 if ((!HasZeros || LateMask) && !Res) {
1706 // If we have both Repl32 groups and non-Repl32 groups, the non-Repl32
1707 // groups will come first, and so the VRI representing the largest number
1708 // of groups might not be first (it might be the first Repl32 groups).
1709 unsigned MaxGroupsIdx = 0;
1710 if (!ValueRotsVec[0].Repl32) {
1711 for (unsigned i = 0, ie = ValueRotsVec.size(); i < ie; ++i)
1712 if (ValueRotsVec[i].Repl32) {
1713 if (ValueRotsVec[i].NumGroups > ValueRotsVec[0].NumGroups)
1719 ValueRotInfo &VRI = ValueRotsVec[MaxGroupsIdx];
1720 bool NeedsRotate = false;
1723 } else if (VRI.Repl32) {
1724 for (auto &BG : BitGroups) {
1725 if (BG.V != VRI.V || BG.RLAmt != VRI.RLAmt ||
1726 BG.Repl32 != VRI.Repl32)
1729 // We don't need a rotate if the bit group is confined to the lower
1731 if (BG.StartIdx < 32 && BG.EndIdx < 32 && BG.StartIdx < BG.EndIdx)
1740 Res = SelectRotMask64(VRI.V, dl, VRI.RLAmt, VRI.Repl32,
1741 VRI.Repl32 ? 31 : 0, VRI.Repl32 ? 30 : 63,
1746 // Now, remove all groups with this underlying value and rotation factor.
1748 for (auto I = BitGroups.begin(); I != BitGroups.end();) {
1749 if (I->V == VRI.V && I->RLAmt == VRI.RLAmt && I->Repl32 == VRI.Repl32)
1750 I = BitGroups.erase(I);
1756 // Because 64-bit rotates are more flexible than inserts, we might have a
1757 // preference regarding which one we do first (to save one instruction).
1759 for (auto I = BitGroups.begin(), IE = BitGroups.end(); I != IE; ++I) {
1760 if (SelectRotMask64Count(I->RLAmt, I->Repl32, I->StartIdx, I->EndIdx,
1762 SelectRotMask64Count(I->RLAmt, I->Repl32, I->StartIdx, I->EndIdx,
1764 if (I != BitGroups.begin()) {
1767 BitGroups.insert(BitGroups.begin(), BG);
1774 // Insert the other groups (one at a time).
1775 for (auto &BG : BitGroups) {
1777 Res = SelectRotMask64(BG.V, dl, BG.RLAmt, BG.Repl32, BG.StartIdx,
1778 BG.EndIdx, InstCnt);
1780 Res = SelectRotMaskIns64(Res, BG.V, dl, BG.RLAmt, BG.Repl32,
1781 BG.StartIdx, BG.EndIdx, InstCnt);
1785 uint64_t Mask = getZerosMask();
1787 // We can use the 32-bit andi/andis technique if the mask does not
1788 // require any higher-order bits. This can save an instruction compared
1789 // to always using the general 64-bit technique.
1790 bool Use32BitInsts = isUInt<32>(Mask);
1791 // Compute the masks for andi/andis that would be necessary.
1792 unsigned ANDIMask = (Mask & UINT16_MAX),
1793 ANDISMask = (Mask >> 16) & UINT16_MAX;
1795 if (Use32BitInsts) {
1796 assert((ANDIMask != 0 || ANDISMask != 0) &&
1797 "No set bits in mask when using 32-bit ands for 64-bit value");
1799 if (InstCnt) *InstCnt += (unsigned) (ANDIMask != 0) +
1800 (unsigned) (ANDISMask != 0) +
1801 (unsigned) (ANDIMask != 0 && ANDISMask != 0);
1803 SDValue ANDIVal, ANDISVal;
1805 ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo8, dl, MVT::i64,
1806 Res, getI32Imm(ANDIMask)), 0);
1808 ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo8, dl, MVT::i64,
1809 Res, getI32Imm(ANDISMask)), 0);
1816 Res = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
1817 ANDIVal, ANDISVal), 0);
1819 if (InstCnt) *InstCnt += SelectInt64Count(Mask) + /* and */ 1;
1821 SDValue MaskVal = SDValue(SelectInt64(CurDAG, dl, Mask), 0);
1823 SDValue(CurDAG->getMachineNode(PPC::AND8, dl, MVT::i64,
1828 return Res.getNode();
1831 SDNode *Select(SDNode *N, bool LateMask, unsigned *InstCnt = nullptr) {
1832 // Fill in BitGroups.
1833 collectBitGroups(LateMask);
1834 if (BitGroups.empty())
1837 // For 64-bit values, figure out when we can use 32-bit instructions.
1838 if (Bits.size() == 64)
1839 assignRepl32BitGroups();
1841 // Fill in ValueRotsVec.
1842 collectValueRotInfo();
1844 if (Bits.size() == 32) {
1845 return Select32(N, LateMask, InstCnt);
1847 assert(Bits.size() == 64 && "Not 64 bits here?");
1848 return Select64(N, LateMask, InstCnt);
1854 SmallVector<ValueBit, 64> Bits;
1857 SmallVector<unsigned, 64> RLAmt;
1859 SmallVector<BitGroup, 16> BitGroups;
1861 DenseMap<std::pair<SDValue, unsigned>, ValueRotInfo> ValueRots;
1862 SmallVector<ValueRotInfo, 16> ValueRotsVec;
1864 SelectionDAG *CurDAG;
1867 BitPermutationSelector(SelectionDAG *DAG)
1870 // Here we try to match complex bit permutations into a set of
1871 // rotate-and-shift/shift/and/or instructions, using a set of heuristics
1872 // known to produce optimial code for common cases (like i32 byte swapping).
1873 SDNode *Select(SDNode *N) {
1874 Bits.resize(N->getValueType(0).getSizeInBits());
1875 if (!getValueBits(SDValue(N, 0), Bits))
1878 DEBUG(dbgs() << "Considering bit-permutation-based instruction"
1879 " selection for: ");
1880 DEBUG(N->dump(CurDAG));
1882 // Fill it RLAmt and set HasZeros.
1883 computeRotationAmounts();
1886 return Select(N, false);
1888 // We currently have two techniques for handling results with zeros: early
1889 // masking (the default) and late masking. Late masking is sometimes more
1890 // efficient, but because the structure of the bit groups is different, it
1891 // is hard to tell without generating both and comparing the results. With
1892 // late masking, we ignore zeros in the resulting value when inserting each
1893 // set of bit groups, and then mask in the zeros at the end. With early
1894 // masking, we only insert the non-zero parts of the result at every step.
1896 unsigned InstCnt, InstCntLateMask;
1897 DEBUG(dbgs() << "\tEarly masking:\n");
1898 SDNode *RN = Select(N, false, &InstCnt);
1899 DEBUG(dbgs() << "\t\tisel would use " << InstCnt << " instructions\n");
1901 DEBUG(dbgs() << "\tLate masking:\n");
1902 SDNode *RNLM = Select(N, true, &InstCntLateMask);
1903 DEBUG(dbgs() << "\t\tisel would use " << InstCntLateMask <<
1906 if (InstCnt <= InstCntLateMask) {
1907 DEBUG(dbgs() << "\tUsing early-masking for isel\n");
1911 DEBUG(dbgs() << "\tUsing late-masking for isel\n");
1915 } // anonymous namespace
1917 SDNode *PPCDAGToDAGISel::SelectBitPermutation(SDNode *N) {
1918 if (N->getValueType(0) != MVT::i32 &&
1919 N->getValueType(0) != MVT::i64)
1922 if (!UseBitPermRewriter)
1925 switch (N->getOpcode()) {
1932 BitPermutationSelector BPS(CurDAG);
1933 return BPS.Select(N);
1940 /// SelectCC - Select a comparison of the specified values with the specified
1941 /// condition code, returning the CR# of the expression.
1942 SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS,
1943 ISD::CondCode CC, SDLoc dl) {
1944 // Always select the LHS.
1947 if (LHS.getValueType() == MVT::i32) {
1949 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1950 if (isInt32Immediate(RHS, Imm)) {
1951 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
1952 if (isUInt<16>(Imm))
1953 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
1954 getI32Imm(Imm & 0xFFFF)), 0);
1955 // If this is a 16-bit signed immediate, fold it.
1956 if (isInt<16>((int)Imm))
1957 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
1958 getI32Imm(Imm & 0xFFFF)), 0);
1960 // For non-equality comparisons, the default code would materialize the
1961 // constant, then compare against it, like this:
1963 // ori r2, r2, 22136
1965 // Since we are just comparing for equality, we can emit this instead:
1966 // xoris r0,r3,0x1234
1967 // cmplwi cr0,r0,0x5678
1969 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS, dl, MVT::i32, LHS,
1970 getI32Imm(Imm >> 16)), 0);
1971 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, Xor,
1972 getI32Imm(Imm & 0xFFFF)), 0);
1975 } else if (ISD::isUnsignedIntSetCC(CC)) {
1976 if (isInt32Immediate(RHS, Imm) && isUInt<16>(Imm))
1977 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
1978 getI32Imm(Imm & 0xFFFF)), 0);
1982 if (isIntS16Immediate(RHS, SImm))
1983 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
1984 getI32Imm((int)SImm & 0xFFFF)),
1988 } else if (LHS.getValueType() == MVT::i64) {
1990 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1991 if (isInt64Immediate(RHS.getNode(), Imm)) {
1992 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
1993 if (isUInt<16>(Imm))
1994 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
1995 getI32Imm(Imm & 0xFFFF)), 0);
1996 // If this is a 16-bit signed immediate, fold it.
1998 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
1999 getI32Imm(Imm & 0xFFFF)), 0);
2001 // For non-equality comparisons, the default code would materialize the
2002 // constant, then compare against it, like this:
2004 // ori r2, r2, 22136
2006 // Since we are just comparing for equality, we can emit this instead:
2007 // xoris r0,r3,0x1234
2008 // cmpldi cr0,r0,0x5678
2010 if (isUInt<32>(Imm)) {
2011 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS8, dl, MVT::i64, LHS,
2012 getI64Imm(Imm >> 16)), 0);
2013 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, Xor,
2014 getI64Imm(Imm & 0xFFFF)), 0);
2018 } else if (ISD::isUnsignedIntSetCC(CC)) {
2019 if (isInt64Immediate(RHS.getNode(), Imm) && isUInt<16>(Imm))
2020 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
2021 getI64Imm(Imm & 0xFFFF)), 0);
2025 if (isIntS16Immediate(RHS, SImm))
2026 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
2027 getI64Imm(SImm & 0xFFFF)),
2031 } else if (LHS.getValueType() == MVT::f32) {
2034 assert(LHS.getValueType() == MVT::f64 && "Unknown vt!");
2035 Opc = PPCSubTarget->hasVSX() ? PPC::XSCMPUDP : PPC::FCMPUD;
2037 return SDValue(CurDAG->getMachineNode(Opc, dl, MVT::i32, LHS, RHS), 0);
2040 static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {
2046 llvm_unreachable("Should be lowered by legalize!");
2047 default: llvm_unreachable("Unknown condition!");
2049 case ISD::SETEQ: return PPC::PRED_EQ;
2051 case ISD::SETNE: return PPC::PRED_NE;
2053 case ISD::SETLT: return PPC::PRED_LT;
2055 case ISD::SETLE: return PPC::PRED_LE;
2057 case ISD::SETGT: return PPC::PRED_GT;
2059 case ISD::SETGE: return PPC::PRED_GE;
2060 case ISD::SETO: return PPC::PRED_NU;
2061 case ISD::SETUO: return PPC::PRED_UN;
2062 // These two are invalid for floating point. Assume we have int.
2063 case ISD::SETULT: return PPC::PRED_LT;
2064 case ISD::SETUGT: return PPC::PRED_GT;
2068 /// getCRIdxForSetCC - Return the index of the condition register field
2069 /// associated with the SetCC condition, and whether or not the field is
2070 /// treated as inverted. That is, lt = 0; ge = 0 inverted.
2071 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert) {
2074 default: llvm_unreachable("Unknown condition!");
2076 case ISD::SETLT: return 0; // Bit #0 = SETOLT
2078 case ISD::SETGT: return 1; // Bit #1 = SETOGT
2080 case ISD::SETEQ: return 2; // Bit #2 = SETOEQ
2081 case ISD::SETUO: return 3; // Bit #3 = SETUO
2083 case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE
2085 case ISD::SETLE: Invert = true; return 1; // !Bit #1 = SETULE
2087 case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE
2088 case ISD::SETO: Invert = true; return 3; // !Bit #3 = SETO
2093 llvm_unreachable("Invalid branch code: should be expanded by legalize");
2094 // These are invalid for floating point. Assume integer.
2095 case ISD::SETULT: return 0;
2096 case ISD::SETUGT: return 1;
2100 // getVCmpInst: return the vector compare instruction for the specified
2101 // vector type and condition code. Since this is for altivec specific code,
2102 // only support the altivec types (v16i8, v8i16, v4i32, and v4f32).
2103 static unsigned int getVCmpInst(MVT VecVT, ISD::CondCode CC,
2104 bool HasVSX, bool &Swap, bool &Negate) {
2108 if (VecVT.isFloatingPoint()) {
2109 /* Handle some cases by swapping input operands. */
2111 case ISD::SETLE: CC = ISD::SETGE; Swap = true; break;
2112 case ISD::SETLT: CC = ISD::SETGT; Swap = true; break;
2113 case ISD::SETOLE: CC = ISD::SETOGE; Swap = true; break;
2114 case ISD::SETOLT: CC = ISD::SETOGT; Swap = true; break;
2115 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break;
2116 case ISD::SETUGT: CC = ISD::SETULT; Swap = true; break;
2119 /* Handle some cases by negating the result. */
2121 case ISD::SETNE: CC = ISD::SETEQ; Negate = true; break;
2122 case ISD::SETUNE: CC = ISD::SETOEQ; Negate = true; break;
2123 case ISD::SETULE: CC = ISD::SETOGT; Negate = true; break;
2124 case ISD::SETULT: CC = ISD::SETOGE; Negate = true; break;
2127 /* We have instructions implementing the remaining cases. */
2131 if (VecVT == MVT::v4f32)
2132 return HasVSX ? PPC::XVCMPEQSP : PPC::VCMPEQFP;
2133 else if (VecVT == MVT::v2f64)
2134 return PPC::XVCMPEQDP;
2138 if (VecVT == MVT::v4f32)
2139 return HasVSX ? PPC::XVCMPGTSP : PPC::VCMPGTFP;
2140 else if (VecVT == MVT::v2f64)
2141 return PPC::XVCMPGTDP;
2145 if (VecVT == MVT::v4f32)
2146 return HasVSX ? PPC::XVCMPGESP : PPC::VCMPGEFP;
2147 else if (VecVT == MVT::v2f64)
2148 return PPC::XVCMPGEDP;
2153 llvm_unreachable("Invalid floating-point vector compare condition");
2155 /* Handle some cases by swapping input operands. */
2157 case ISD::SETGE: CC = ISD::SETLE; Swap = true; break;
2158 case ISD::SETLT: CC = ISD::SETGT; Swap = true; break;
2159 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break;
2160 case ISD::SETULT: CC = ISD::SETUGT; Swap = true; break;
2163 /* Handle some cases by negating the result. */
2165 case ISD::SETNE: CC = ISD::SETEQ; Negate = true; break;
2166 case ISD::SETUNE: CC = ISD::SETUEQ; Negate = true; break;
2167 case ISD::SETLE: CC = ISD::SETGT; Negate = true; break;
2168 case ISD::SETULE: CC = ISD::SETUGT; Negate = true; break;
2171 /* We have instructions implementing the remaining cases. */
2175 if (VecVT == MVT::v16i8)
2176 return PPC::VCMPEQUB;
2177 else if (VecVT == MVT::v8i16)
2178 return PPC::VCMPEQUH;
2179 else if (VecVT == MVT::v4i32)
2180 return PPC::VCMPEQUW;
2183 if (VecVT == MVT::v16i8)
2184 return PPC::VCMPGTSB;
2185 else if (VecVT == MVT::v8i16)
2186 return PPC::VCMPGTSH;
2187 else if (VecVT == MVT::v4i32)
2188 return PPC::VCMPGTSW;
2191 if (VecVT == MVT::v16i8)
2192 return PPC::VCMPGTUB;
2193 else if (VecVT == MVT::v8i16)
2194 return PPC::VCMPGTUH;
2195 else if (VecVT == MVT::v4i32)
2196 return PPC::VCMPGTUW;
2201 llvm_unreachable("Invalid integer vector compare condition");
2205 SDNode *PPCDAGToDAGISel::SelectSETCC(SDNode *N) {
2208 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
2209 EVT PtrVT = CurDAG->getTargetLoweringInfo().getPointerTy();
2210 bool isPPC64 = (PtrVT == MVT::i64);
2212 if (!PPCSubTarget->useCRBits() &&
2213 isInt32Immediate(N->getOperand(1), Imm)) {
2214 // We can codegen setcc op, imm very efficiently compared to a brcond.
2215 // Check for those cases here.
2218 SDValue Op = N->getOperand(0);
2222 Op = SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Op), 0);
2223 SDValue Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) };
2224 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2229 SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
2230 Op, getI32Imm(~0U)), 0);
2231 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
2235 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
2236 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2240 SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Op), 0);
2241 T = SDValue(CurDAG->getMachineNode(PPC::ANDC, dl, MVT::i32, T, Op), 0);
2242 SDValue Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
2243 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2246 } else if (Imm == ~0U) { // setcc op, -1
2247 SDValue Op = N->getOperand(0);
2252 Op = SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
2253 Op, getI32Imm(1)), 0);
2254 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
2255 SDValue(CurDAG->getMachineNode(PPC::LI, dl,
2261 Op = SDValue(CurDAG->getMachineNode(PPC::NOR, dl, MVT::i32, Op, Op), 0);
2262 SDNode *AD = CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
2263 Op, getI32Imm(~0U));
2264 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0),
2265 Op, SDValue(AD, 1));
2268 SDValue AD = SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Op,
2270 SDValue AN = SDValue(CurDAG->getMachineNode(PPC::AND, dl, MVT::i32, AD,
2272 SDValue Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
2273 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2276 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
2277 Op = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops),
2279 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op,
2286 SDValue LHS = N->getOperand(0);
2287 SDValue RHS = N->getOperand(1);
2289 // Altivec Vector compare instructions do not set any CR register by default and
2290 // vector compare operations return the same type as the operands.
2291 if (LHS.getValueType().isVector()) {
2292 EVT VecVT = LHS.getValueType();
2294 unsigned int VCmpInst = getVCmpInst(VecVT.getSimpleVT(), CC,
2295 PPCSubTarget->hasVSX(), Swap, Negate);
2297 std::swap(LHS, RHS);
2300 SDValue VCmp(CurDAG->getMachineNode(VCmpInst, dl, VecVT, LHS, RHS), 0);
2301 return CurDAG->SelectNodeTo(N, PPCSubTarget->hasVSX() ? PPC::XXLNOR :
2306 return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS);
2309 if (PPCSubTarget->useCRBits())
2313 unsigned Idx = getCRIdxForSetCC(CC, Inv);
2314 SDValue CCReg = SelectCC(LHS, RHS, CC, dl);
2317 // Force the ccreg into CR7.
2318 SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
2320 SDValue InFlag(nullptr, 0); // Null incoming flag value.
2321 CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, CR7Reg, CCReg,
2322 InFlag).getValue(1);
2324 IntCR = SDValue(CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg,
2327 SDValue Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31),
2328 getI32Imm(31), getI32Imm(31) };
2330 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2332 // Get the specified bit.
2334 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0);
2335 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
2339 // Select - Convert the specified operand from a target-independent to a
2340 // target-specific node if it hasn't already been changed.
2341 SDNode *PPCDAGToDAGISel::Select(SDNode *N) {
2343 if (N->isMachineOpcode()) {
2345 return nullptr; // Already selected.
2348 // In case any misguided DAG-level optimizations form an ADD with a
2349 // TargetConstant operand, crash here instead of miscompiling (by selecting
2350 // an r+r add instead of some kind of r+i add).
2351 if (N->getOpcode() == ISD::ADD &&
2352 N->getOperand(1).getOpcode() == ISD::TargetConstant)
2353 llvm_unreachable("Invalid ADD with TargetConstant operand");
2355 // Try matching complex bit permutations before doing anything else.
2356 if (SDNode *NN = SelectBitPermutation(N))
2359 switch (N->getOpcode()) {
2362 case ISD::Constant: {
2363 if (N->getValueType(0) == MVT::i64)
2364 return SelectInt64(CurDAG, N);
2369 SDNode *SN = SelectSETCC(N);
2374 case PPCISD::GlobalBaseReg:
2375 return getGlobalBaseReg();
2377 case ISD::FrameIndex:
2378 return getFrameIndex(N, N);
2380 case PPCISD::MFOCRF: {
2381 SDValue InFlag = N->getOperand(1);
2382 return CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32,
2383 N->getOperand(0), InFlag);
2386 case PPCISD::READ_TIME_BASE: {
2387 return CurDAG->getMachineNode(PPC::ReadTB, dl, MVT::i32, MVT::i32,
2388 MVT::Other, N->getOperand(0));
2391 case PPCISD::SRA_ADDZE: {
2392 SDValue N0 = N->getOperand(0);
2394 CurDAG->getTargetConstant(*cast<ConstantSDNode>(N->getOperand(1))->
2395 getConstantIntValue(), N->getValueType(0));
2396 if (N->getValueType(0) == MVT::i64) {
2398 CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, MVT::Glue,
2400 return CurDAG->SelectNodeTo(N, PPC::ADDZE8, MVT::i64,
2401 SDValue(Op, 0), SDValue(Op, 1));
2403 assert(N->getValueType(0) == MVT::i32 &&
2404 "Expecting i64 or i32 in PPCISD::SRA_ADDZE");
2406 CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Glue,
2408 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
2409 SDValue(Op, 0), SDValue(Op, 1));
2414 // Handle preincrement loads.
2415 LoadSDNode *LD = cast<LoadSDNode>(N);
2416 EVT LoadedVT = LD->getMemoryVT();
2418 // Normal loads are handled by code generated from the .td file.
2419 if (LD->getAddressingMode() != ISD::PRE_INC)
2422 SDValue Offset = LD->getOffset();
2423 if (Offset.getOpcode() == ISD::TargetConstant ||
2424 Offset.getOpcode() == ISD::TargetGlobalAddress) {
2427 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
2428 if (LD->getValueType(0) != MVT::i64) {
2429 // Handle PPC32 integer and normal FP loads.
2430 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
2431 switch (LoadedVT.getSimpleVT().SimpleTy) {
2432 default: llvm_unreachable("Invalid PPC load type!");
2433 case MVT::f64: Opcode = PPC::LFDU; break;
2434 case MVT::f32: Opcode = PPC::LFSU; break;
2435 case MVT::i32: Opcode = PPC::LWZU; break;
2436 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
2438 case MVT::i8: Opcode = PPC::LBZU; break;
2441 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
2442 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
2443 switch (LoadedVT.getSimpleVT().SimpleTy) {
2444 default: llvm_unreachable("Invalid PPC load type!");
2445 case MVT::i64: Opcode = PPC::LDU; break;
2446 case MVT::i32: Opcode = PPC::LWZU8; break;
2447 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
2449 case MVT::i8: Opcode = PPC::LBZU8; break;
2453 SDValue Chain = LD->getChain();
2454 SDValue Base = LD->getBasePtr();
2455 SDValue Ops[] = { Offset, Base, Chain };
2456 return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0),
2457 PPCLowering->getPointerTy(),
2461 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
2462 if (LD->getValueType(0) != MVT::i64) {
2463 // Handle PPC32 integer and normal FP loads.
2464 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
2465 switch (LoadedVT.getSimpleVT().SimpleTy) {
2466 default: llvm_unreachable("Invalid PPC load type!");
2467 case MVT::f64: Opcode = PPC::LFDUX; break;
2468 case MVT::f32: Opcode = PPC::LFSUX; break;
2469 case MVT::i32: Opcode = PPC::LWZUX; break;
2470 case MVT::i16: Opcode = isSExt ? PPC::LHAUX : PPC::LHZUX; break;
2472 case MVT::i8: Opcode = PPC::LBZUX; break;
2475 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
2476 assert((!isSExt || LoadedVT == MVT::i16 || LoadedVT == MVT::i32) &&
2477 "Invalid sext update load");
2478 switch (LoadedVT.getSimpleVT().SimpleTy) {
2479 default: llvm_unreachable("Invalid PPC load type!");
2480 case MVT::i64: Opcode = PPC::LDUX; break;
2481 case MVT::i32: Opcode = isSExt ? PPC::LWAUX : PPC::LWZUX8; break;
2482 case MVT::i16: Opcode = isSExt ? PPC::LHAUX8 : PPC::LHZUX8; break;
2484 case MVT::i8: Opcode = PPC::LBZUX8; break;
2488 SDValue Chain = LD->getChain();
2489 SDValue Base = LD->getBasePtr();
2490 SDValue Ops[] = { Base, Offset, Chain };
2491 return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0),
2492 PPCLowering->getPointerTy(),
2498 unsigned Imm, Imm2, SH, MB, ME;
2501 // If this is an and of a value rotated between 0 and 31 bits and then and'd
2502 // with a mask, emit rlwinm
2503 if (isInt32Immediate(N->getOperand(1), Imm) &&
2504 isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH, MB, ME)) {
2505 SDValue Val = N->getOperand(0).getOperand(0);
2506 SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
2507 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2509 // If this is just a masked value where the input is not handled above, and
2510 // is not a rotate-left (handled by a pattern in the .td file), emit rlwinm
2511 if (isInt32Immediate(N->getOperand(1), Imm) &&
2512 isRunOfOnes(Imm, MB, ME) &&
2513 N->getOperand(0).getOpcode() != ISD::ROTL) {
2514 SDValue Val = N->getOperand(0);
2515 SDValue Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) };
2516 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2518 // If this is a 64-bit zero-extension mask, emit rldicl.
2519 if (isInt64Immediate(N->getOperand(1).getNode(), Imm64) &&
2521 SDValue Val = N->getOperand(0);
2522 MB = 64 - CountTrailingOnes_64(Imm64);
2525 // If the operand is a logical right shift, we can fold it into this
2526 // instruction: rldicl(rldicl(x, 64-n, n), 0, mb) -> rldicl(x, 64-n, mb)
2527 // for n <= mb. The right shift is really a left rotate followed by a
2528 // mask, and this mask is a more-restrictive sub-mask of the mask implied
2530 if (Val.getOpcode() == ISD::SRL &&
2531 isInt32Immediate(Val.getOperand(1).getNode(), Imm) && Imm <= MB) {
2532 assert(Imm < 64 && "Illegal shift amount");
2533 Val = Val.getOperand(0);
2537 SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB) };
2538 return CurDAG->SelectNodeTo(N, PPC::RLDICL, MVT::i64, Ops);
2540 // AND X, 0 -> 0, not "rlwinm 32".
2541 if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) {
2542 ReplaceUses(SDValue(N, 0), N->getOperand(1));
2545 // ISD::OR doesn't get all the bitfield insertion fun.
2546 // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert
2547 if (isInt32Immediate(N->getOperand(1), Imm) &&
2548 N->getOperand(0).getOpcode() == ISD::OR &&
2549 isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) {
2552 if (isRunOfOnes(Imm, MB, ME)) {
2553 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2554 N->getOperand(0).getOperand(1),
2555 getI32Imm(0), getI32Imm(MB),getI32Imm(ME) };
2556 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops);
2560 // Other cases are autogenerated.
2564 if (N->getValueType(0) == MVT::i32)
2565 if (SDNode *I = SelectBitfieldInsert(N))
2569 if (N->getOperand(0)->getOpcode() == ISD::FrameIndex &&
2570 isIntS16Immediate(N->getOperand(1), Imm)) {
2571 APInt LHSKnownZero, LHSKnownOne;
2572 CurDAG->computeKnownBits(N->getOperand(0), LHSKnownZero, LHSKnownOne);
2574 // If this is equivalent to an add, then we can fold it with the
2575 // FrameIndex calculation.
2576 if ((LHSKnownZero.getZExtValue()|~(uint64_t)Imm) == ~0ULL)
2577 return getFrameIndex(N, N->getOperand(0).getNode(), (int)Imm);
2580 // Other cases are autogenerated.
2585 if (N->getOperand(0)->getOpcode() == ISD::FrameIndex &&
2586 isIntS16Immediate(N->getOperand(1), Imm))
2587 return getFrameIndex(N, N->getOperand(0).getNode(), (int)Imm);
2592 unsigned Imm, SH, MB, ME;
2593 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
2594 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
2595 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2596 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
2597 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2600 // Other cases are autogenerated.
2604 unsigned Imm, SH, MB, ME;
2605 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
2606 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
2607 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2608 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
2609 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2612 // Other cases are autogenerated.
2615 // FIXME: Remove this once the ANDI glue bug is fixed:
2616 case PPCISD::ANDIo_1_EQ_BIT:
2617 case PPCISD::ANDIo_1_GT_BIT: {
2621 EVT InVT = N->getOperand(0).getValueType();
2622 assert((InVT == MVT::i64 || InVT == MVT::i32) &&
2623 "Invalid input type for ANDIo_1_EQ_BIT");
2625 unsigned Opcode = (InVT == MVT::i64) ? PPC::ANDIo8 : PPC::ANDIo;
2626 SDValue AndI(CurDAG->getMachineNode(Opcode, dl, InVT, MVT::Glue,
2628 CurDAG->getTargetConstant(1, InVT)), 0);
2629 SDValue CR0Reg = CurDAG->getRegister(PPC::CR0, MVT::i32);
2631 CurDAG->getTargetConstant(N->getOpcode() == PPCISD::ANDIo_1_EQ_BIT ?
2632 PPC::sub_eq : PPC::sub_gt, MVT::i32);
2634 return CurDAG->SelectNodeTo(N, TargetOpcode::EXTRACT_SUBREG, MVT::i1,
2636 SDValue(AndI.getNode(), 1) /* glue */);
2638 case ISD::SELECT_CC: {
2639 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
2640 EVT PtrVT = CurDAG->getTargetLoweringInfo().getPointerTy();
2641 bool isPPC64 = (PtrVT == MVT::i64);
2643 // If this is a select of i1 operands, we'll pattern match it.
2644 if (PPCSubTarget->useCRBits() &&
2645 N->getOperand(0).getValueType() == MVT::i1)
2648 // Handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
2650 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2651 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
2652 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
2653 if (N1C->isNullValue() && N3C->isNullValue() &&
2654 N2C->getZExtValue() == 1ULL && CC == ISD::SETNE &&
2655 // FIXME: Implement this optzn for PPC64.
2656 N->getValueType(0) == MVT::i32) {
2658 CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
2659 N->getOperand(0), getI32Imm(~0U));
2660 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
2661 SDValue(Tmp, 0), N->getOperand(0),
2665 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl);
2667 if (N->getValueType(0) == MVT::i1) {
2668 // An i1 select is: (c & t) | (!c & f).
2670 unsigned Idx = getCRIdxForSetCC(CC, Inv);
2674 default: llvm_unreachable("Invalid CC index");
2675 case 0: SRI = PPC::sub_lt; break;
2676 case 1: SRI = PPC::sub_gt; break;
2677 case 2: SRI = PPC::sub_eq; break;
2678 case 3: SRI = PPC::sub_un; break;
2681 SDValue CCBit = CurDAG->getTargetExtractSubreg(SRI, dl, MVT::i1, CCReg);
2683 SDValue NotCCBit(CurDAG->getMachineNode(PPC::CRNOR, dl, MVT::i1,
2685 SDValue C = Inv ? NotCCBit : CCBit,
2686 NotC = Inv ? CCBit : NotCCBit;
2688 SDValue CAndT(CurDAG->getMachineNode(PPC::CRAND, dl, MVT::i1,
2689 C, N->getOperand(2)), 0);
2690 SDValue NotCAndF(CurDAG->getMachineNode(PPC::CRAND, dl, MVT::i1,
2691 NotC, N->getOperand(3)), 0);
2693 return CurDAG->SelectNodeTo(N, PPC::CROR, MVT::i1, CAndT, NotCAndF);
2696 unsigned BROpc = getPredicateForSetCC(CC);
2698 unsigned SelectCCOp;
2699 if (N->getValueType(0) == MVT::i32)
2700 SelectCCOp = PPC::SELECT_CC_I4;
2701 else if (N->getValueType(0) == MVT::i64)
2702 SelectCCOp = PPC::SELECT_CC_I8;
2703 else if (N->getValueType(0) == MVT::f32)
2704 SelectCCOp = PPC::SELECT_CC_F4;
2705 else if (N->getValueType(0) == MVT::f64)
2706 if (PPCSubTarget->hasVSX())
2707 SelectCCOp = PPC::SELECT_CC_VSFRC;
2709 SelectCCOp = PPC::SELECT_CC_F8;
2710 else if (N->getValueType(0) == MVT::v2f64 ||
2711 N->getValueType(0) == MVT::v2i64)
2712 SelectCCOp = PPC::SELECT_CC_VSRC;
2714 SelectCCOp = PPC::SELECT_CC_VRRC;
2716 SDValue Ops[] = { CCReg, N->getOperand(2), N->getOperand(3),
2718 return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops);
2721 if (PPCSubTarget->hasVSX()) {
2722 SDValue Ops[] = { N->getOperand(2), N->getOperand(1), N->getOperand(0) };
2723 return CurDAG->SelectNodeTo(N, PPC::XXSEL, N->getValueType(0), Ops);
2727 case ISD::VECTOR_SHUFFLE:
2728 if (PPCSubTarget->hasVSX() && (N->getValueType(0) == MVT::v2f64 ||
2729 N->getValueType(0) == MVT::v2i64)) {
2730 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
2732 SDValue Op1 = N->getOperand(SVN->getMaskElt(0) < 2 ? 0 : 1),
2733 Op2 = N->getOperand(SVN->getMaskElt(1) < 2 ? 0 : 1);
2736 for (int i = 0; i < 2; ++i)
2737 if (SVN->getMaskElt(i) <= 0 || SVN->getMaskElt(i) == 2)
2742 // For little endian, we must swap the input operands and adjust
2743 // the mask elements (reverse and invert them).
2744 if (PPCSubTarget->isLittleEndian()) {
2745 std::swap(Op1, Op2);
2746 unsigned tmp = DM[0];
2751 SDValue DMV = CurDAG->getTargetConstant(DM[1] | (DM[0] << 1), MVT::i32);
2753 if (Op1 == Op2 && DM[0] == 0 && DM[1] == 0 &&
2754 Op1.getOpcode() == ISD::SCALAR_TO_VECTOR &&
2755 isa<LoadSDNode>(Op1.getOperand(0))) {
2756 LoadSDNode *LD = cast<LoadSDNode>(Op1.getOperand(0));
2757 SDValue Base, Offset;
2759 if (LD->isUnindexed() &&
2760 SelectAddrIdxOnly(LD->getBasePtr(), Base, Offset)) {
2761 SDValue Chain = LD->getChain();
2762 SDValue Ops[] = { Base, Offset, Chain };
2763 return CurDAG->SelectNodeTo(N, PPC::LXVDSX,
2764 N->getValueType(0), Ops);
2768 SDValue Ops[] = { Op1, Op2, DMV };
2769 return CurDAG->SelectNodeTo(N, PPC::XXPERMDI, N->getValueType(0), Ops);
2775 bool IsPPC64 = PPCSubTarget->isPPC64();
2776 SDValue Ops[] = { N->getOperand(1), N->getOperand(0) };
2777 return CurDAG->SelectNodeTo(N, N->getOpcode() == PPCISD::BDNZ ?
2778 (IsPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
2779 (IsPPC64 ? PPC::BDZ8 : PPC::BDZ),
2782 case PPCISD::COND_BRANCH: {
2783 // Op #0 is the Chain.
2784 // Op #1 is the PPC::PRED_* number.
2786 // Op #3 is the Dest MBB
2787 // Op #4 is the Flag.
2788 // Prevent PPC::PRED_* from being selected into LI.
2790 getI32Imm(cast<ConstantSDNode>(N->getOperand(1))->getZExtValue());
2791 SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3),
2792 N->getOperand(0), N->getOperand(4) };
2793 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops);
2796 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
2797 unsigned PCC = getPredicateForSetCC(CC);
2799 if (N->getOperand(2).getValueType() == MVT::i1) {
2803 default: llvm_unreachable("Unexpected Boolean-operand predicate");
2804 case PPC::PRED_LT: Opc = PPC::CRANDC; Swap = true; break;
2805 case PPC::PRED_LE: Opc = PPC::CRORC; Swap = true; break;
2806 case PPC::PRED_EQ: Opc = PPC::CREQV; Swap = false; break;
2807 case PPC::PRED_GE: Opc = PPC::CRORC; Swap = false; break;
2808 case PPC::PRED_GT: Opc = PPC::CRANDC; Swap = false; break;
2809 case PPC::PRED_NE: Opc = PPC::CRXOR; Swap = false; break;
2812 SDValue BitComp(CurDAG->getMachineNode(Opc, dl, MVT::i1,
2813 N->getOperand(Swap ? 3 : 2),
2814 N->getOperand(Swap ? 2 : 3)), 0);
2815 return CurDAG->SelectNodeTo(N, PPC::BC, MVT::Other,
2816 BitComp, N->getOperand(4), N->getOperand(0));
2819 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl);
2820 SDValue Ops[] = { getI32Imm(PCC), CondCode,
2821 N->getOperand(4), N->getOperand(0) };
2822 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops);
2825 // FIXME: Should custom lower this.
2826 SDValue Chain = N->getOperand(0);
2827 SDValue Target = N->getOperand(1);
2828 unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
2829 unsigned Reg = Target.getValueType() == MVT::i32 ? PPC::BCTR : PPC::BCTR8;
2830 Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, Target,
2832 return CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain);
2834 case PPCISD::TOC_ENTRY: {
2835 assert ((PPCSubTarget->isPPC64() || PPCSubTarget->isSVR4ABI()) &&
2836 "Only supported for 64-bit ABI and 32-bit SVR4");
2837 if (PPCSubTarget->isSVR4ABI() && !PPCSubTarget->isPPC64()) {
2838 SDValue GA = N->getOperand(0);
2839 return CurDAG->getMachineNode(PPC::LWZtoc, dl, MVT::i32, GA,
2843 // For medium and large code model, we generate two instructions as
2844 // described below. Otherwise we allow SelectCodeCommon to handle this,
2845 // selecting one of LDtoc, LDtocJTI, LDtocCPT, and LDtocBA.
2846 CodeModel::Model CModel = TM.getCodeModel();
2847 if (CModel != CodeModel::Medium && CModel != CodeModel::Large)
2850 // The first source operand is a TargetGlobalAddress or a TargetJumpTable.
2851 // If it is an externally defined symbol, a symbol with common linkage,
2852 // a non-local function address, or a jump table address, or if we are
2853 // generating code for large code model, we generate:
2854 // LDtocL(<ga:@sym>, ADDIStocHA(%X2, <ga:@sym>))
2855 // Otherwise we generate:
2856 // ADDItocL(ADDIStocHA(%X2, <ga:@sym>), <ga:@sym>)
2857 SDValue GA = N->getOperand(0);
2858 SDValue TOCbase = N->getOperand(1);
2859 SDNode *Tmp = CurDAG->getMachineNode(PPC::ADDIStocHA, dl, MVT::i64,
2862 if (isa<JumpTableSDNode>(GA) || isa<BlockAddressSDNode>(GA) ||
2863 CModel == CodeModel::Large)
2864 return CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA,
2867 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(GA)) {
2868 const GlobalValue *GValue = G->getGlobal();
2869 if ((GValue->getType()->getElementType()->isFunctionTy() &&
2870 (GValue->isDeclaration() || GValue->isWeakForLinker())) ||
2871 GValue->isDeclaration() || GValue->hasCommonLinkage() ||
2872 GValue->hasAvailableExternallyLinkage())
2873 return CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA,
2877 return CurDAG->getMachineNode(PPC::ADDItocL, dl, MVT::i64,
2878 SDValue(Tmp, 0), GA);
2880 case PPCISD::PPC32_PICGOT: {
2881 // Generate a PIC-safe GOT reference.
2882 assert(!PPCSubTarget->isPPC64() && PPCSubTarget->isSVR4ABI() &&
2883 "PPCISD::PPC32_PICGOT is only supported for 32-bit SVR4");
2884 return CurDAG->SelectNodeTo(N, PPC::PPC32PICGOT, PPCLowering->getPointerTy(), MVT::i32);
2886 case PPCISD::VADD_SPLAT: {
2887 // This expands into one of three sequences, depending on whether
2888 // the first operand is odd or even, positive or negative.
2889 assert(isa<ConstantSDNode>(N->getOperand(0)) &&
2890 isa<ConstantSDNode>(N->getOperand(1)) &&
2891 "Invalid operand on VADD_SPLAT!");
2893 int Elt = N->getConstantOperandVal(0);
2894 int EltSize = N->getConstantOperandVal(1);
2895 unsigned Opc1, Opc2, Opc3;
2899 Opc1 = PPC::VSPLTISB;
2900 Opc2 = PPC::VADDUBM;
2901 Opc3 = PPC::VSUBUBM;
2903 } else if (EltSize == 2) {
2904 Opc1 = PPC::VSPLTISH;
2905 Opc2 = PPC::VADDUHM;
2906 Opc3 = PPC::VSUBUHM;
2909 assert(EltSize == 4 && "Invalid element size on VADD_SPLAT!");
2910 Opc1 = PPC::VSPLTISW;
2911 Opc2 = PPC::VADDUWM;
2912 Opc3 = PPC::VSUBUWM;
2916 if ((Elt & 1) == 0) {
2917 // Elt is even, in the range [-32,-18] + [16,30].
2919 // Convert: VADD_SPLAT elt, size
2920 // Into: tmp = VSPLTIS[BHW] elt
2921 // VADDU[BHW]M tmp, tmp
2922 // Where: [BHW] = B for size = 1, H for size = 2, W for size = 4
2923 SDValue EltVal = getI32Imm(Elt >> 1);
2924 SDNode *Tmp = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
2925 SDValue TmpVal = SDValue(Tmp, 0);
2926 return CurDAG->getMachineNode(Opc2, dl, VT, TmpVal, TmpVal);
2928 } else if (Elt > 0) {
2929 // Elt is odd and positive, in the range [17,31].
2931 // Convert: VADD_SPLAT elt, size
2932 // Into: tmp1 = VSPLTIS[BHW] elt-16
2933 // tmp2 = VSPLTIS[BHW] -16
2934 // VSUBU[BHW]M tmp1, tmp2
2935 SDValue EltVal = getI32Imm(Elt - 16);
2936 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
2937 EltVal = getI32Imm(-16);
2938 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
2939 return CurDAG->getMachineNode(Opc3, dl, VT, SDValue(Tmp1, 0),
2943 // Elt is odd and negative, in the range [-31,-17].
2945 // Convert: VADD_SPLAT elt, size
2946 // Into: tmp1 = VSPLTIS[BHW] elt+16
2947 // tmp2 = VSPLTIS[BHW] -16
2948 // VADDU[BHW]M tmp1, tmp2
2949 SDValue EltVal = getI32Imm(Elt + 16);
2950 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
2951 EltVal = getI32Imm(-16);
2952 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
2953 return CurDAG->getMachineNode(Opc2, dl, VT, SDValue(Tmp1, 0),
2959 return SelectCode(N);
2962 // If the target supports the cmpb instruction, do the idiom recognition here.
2963 // We don't do this as a DAG combine because we don't want to do it as nodes
2964 // are being combined (because we might miss part of the eventual idiom). We
2965 // don't want to do it during instruction selection because we want to reuse
2966 // the logic for lowering the masking operations already part of the
2967 // instruction selector.
2968 SDValue PPCDAGToDAGISel::combineToCMPB(SDNode *N) {
2971 assert(N->getOpcode() == ISD::OR &&
2972 "Only OR nodes are supported for CMPB");
2975 if (!PPCSubTarget->hasCMPB())
2978 if (N->getValueType(0) != MVT::i32 &&
2979 N->getValueType(0) != MVT::i64)
2982 EVT VT = N->getValueType(0);
2985 bool BytesFound[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
2986 uint64_t Mask = 0, Alt = 0;
2988 auto IsByteSelectCC = [this](SDValue O, unsigned &b,
2989 uint64_t &Mask, uint64_t &Alt,
2990 SDValue &LHS, SDValue &RHS) {
2991 if (O.getOpcode() != ISD::SELECT_CC)
2993 ISD::CondCode CC = cast<CondCodeSDNode>(O.getOperand(4))->get();
2995 if (!isa<ConstantSDNode>(O.getOperand(2)) ||
2996 !isa<ConstantSDNode>(O.getOperand(3)))
2999 uint64_t PM = O.getConstantOperandVal(2);
3000 uint64_t PAlt = O.getConstantOperandVal(3);
3001 for (b = 0; b < 8; ++b) {
3002 uint64_t Mask = UINT64_C(0xFF) << (8*b);
3003 if (PM && (PM & Mask) == PM && (PAlt & Mask) == PAlt)
3012 if (!isa<ConstantSDNode>(O.getOperand(1)) ||
3013 O.getConstantOperandVal(1) != 0) {
3014 SDValue Op0 = O.getOperand(0), Op1 = O.getOperand(1);
3015 if (Op0.getOpcode() == ISD::TRUNCATE)
3016 Op0 = Op0.getOperand(0);
3017 if (Op1.getOpcode() == ISD::TRUNCATE)
3018 Op1 = Op1.getOperand(0);
3020 if (Op0.getOpcode() == ISD::SRL && Op1.getOpcode() == ISD::SRL &&
3021 Op0.getOperand(1) == Op1.getOperand(1) && CC == ISD::SETEQ &&
3022 isa<ConstantSDNode>(Op0.getOperand(1))) {
3024 unsigned Bits = Op0.getValueType().getSizeInBits();
3027 if (Op0.getConstantOperandVal(1) != Bits-8)
3030 LHS = Op0.getOperand(0);
3031 RHS = Op1.getOperand(0);
3035 // When we have small integers (i16 to be specific), the form present
3036 // post-legalization uses SETULT in the SELECT_CC for the
3037 // higher-order byte, depending on the fact that the
3038 // even-higher-order bytes are known to all be zero, for example:
3039 // select_cc (xor $lhs, $rhs), 256, 65280, 0, setult
3040 // (so when the second byte is the same, because all higher-order
3041 // bits from bytes 3 and 4 are known to be zero, the result of the
3042 // xor can be at most 255)
3043 if (Op0.getOpcode() == ISD::XOR && CC == ISD::SETULT &&
3044 isa<ConstantSDNode>(O.getOperand(1))) {
3046 uint64_t ULim = O.getConstantOperandVal(1);
3047 if (ULim != (UINT64_C(1) << b*8))
3050 // Now we need to make sure that the upper bytes are known to be
3052 unsigned Bits = Op0.getValueType().getSizeInBits();
3053 if (!CurDAG->MaskedValueIsZero(Op0,
3054 APInt::getHighBitsSet(Bits, Bits - (b+1)*8)))
3057 LHS = Op0.getOperand(0);
3058 RHS = Op0.getOperand(1);
3065 if (CC != ISD::SETEQ)
3068 SDValue Op = O.getOperand(0);
3069 if (Op.getOpcode() == ISD::AND) {
3070 if (!isa<ConstantSDNode>(Op.getOperand(1)))
3072 if (Op.getConstantOperandVal(1) != (UINT64_C(0xFF) << (8*b)))
3075 SDValue XOR = Op.getOperand(0);
3076 if (XOR.getOpcode() == ISD::TRUNCATE)
3077 XOR = XOR.getOperand(0);
3078 if (XOR.getOpcode() != ISD::XOR)
3081 LHS = XOR.getOperand(0);
3082 RHS = XOR.getOperand(1);
3084 } else if (Op.getOpcode() == ISD::SRL) {
3085 if (!isa<ConstantSDNode>(Op.getOperand(1)))
3087 unsigned Bits = Op.getValueType().getSizeInBits();
3090 if (Op.getConstantOperandVal(1) != Bits-8)
3093 SDValue XOR = Op.getOperand(0);
3094 if (XOR.getOpcode() == ISD::TRUNCATE)
3095 XOR = XOR.getOperand(0);
3096 if (XOR.getOpcode() != ISD::XOR)
3099 LHS = XOR.getOperand(0);
3100 RHS = XOR.getOperand(1);
3107 SmallVector<SDValue, 8> Queue(1, SDValue(N, 0));
3108 while (!Queue.empty()) {
3109 SDValue V = Queue.pop_back_val();
3111 for (const SDValue &O : V.getNode()->ops()) {
3113 uint64_t M = 0, A = 0;
3115 if (O.getOpcode() == ISD::OR) {
3117 } else if (IsByteSelectCC(O, b, M, A, OLHS, ORHS)) {
3121 BytesFound[b] = true;
3124 } else if ((LHS == ORHS && RHS == OLHS) ||
3125 (RHS == ORHS && LHS == OLHS)) {
3126 BytesFound[b] = true;
3138 unsigned LastB = 0, BCnt = 0;
3139 for (unsigned i = 0; i < 8; ++i)
3140 if (BytesFound[LastB]) {
3145 if (!LastB || BCnt < 2)
3148 // Because we'll be zero-extending the output anyway if don't have a specific
3149 // value for each input byte (via the Mask), we can 'anyext' the inputs.
3150 if (LHS.getValueType() != VT) {
3151 LHS = CurDAG->getAnyExtOrTrunc(LHS, dl, VT);
3152 RHS = CurDAG->getAnyExtOrTrunc(RHS, dl, VT);
3155 Res = CurDAG->getNode(PPCISD::CMPB, dl, VT, LHS, RHS);
3157 bool NonTrivialMask = ((int64_t) Mask) != INT64_C(-1);
3158 if (NonTrivialMask && !Alt) {
3159 // Res = Mask & CMPB
3160 Res = CurDAG->getNode(ISD::AND, dl, VT, Res, CurDAG->getConstant(Mask, VT));
3162 // Res = (CMPB & Mask) | (~CMPB & Alt)
3163 // Which, as suggested here:
3164 // https://graphics.stanford.edu/~seander/bithacks.html#MaskedMerge
3165 // can be written as:
3166 // Res = Alt ^ ((Alt ^ Mask) & CMPB)
3167 // useful because the (Alt ^ Mask) can be pre-computed.
3168 Res = CurDAG->getNode(ISD::AND, dl, VT, Res,
3169 CurDAG->getConstant(Mask ^ Alt, VT));
3170 Res = CurDAG->getNode(ISD::XOR, dl, VT, Res, CurDAG->getConstant(Alt, VT));
3176 void PPCDAGToDAGISel::PreprocessISelDAG() {
3177 SelectionDAG::allnodes_iterator Position(CurDAG->getRoot().getNode());
3180 bool MadeChange = false;
3181 while (Position != CurDAG->allnodes_begin()) {
3182 SDNode *N = --Position;
3187 switch (N->getOpcode()) {
3190 Res = combineToCMPB(N);
3195 DEBUG(dbgs() << "PPC DAG preprocessing replacing:\nOld: ");
3196 DEBUG(N->dump(CurDAG));
3197 DEBUG(dbgs() << "\nNew: ");
3198 DEBUG(Res.getNode()->dump(CurDAG));
3199 DEBUG(dbgs() << "\n");
3201 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Res);
3207 CurDAG->RemoveDeadNodes();
3210 /// PostprocessISelDAG - Perform some late peephole optimizations
3211 /// on the DAG representation.
3212 void PPCDAGToDAGISel::PostprocessISelDAG() {
3214 // Skip peepholes at -O0.
3215 if (TM.getOptLevel() == CodeGenOpt::None)
3220 PeepholePPC64ZExt();
3223 // Check if all users of this node will become isel where the second operand
3224 // is the constant zero. If this is so, and if we can negate the condition,
3225 // then we can flip the true and false operands. This will allow the zero to
3226 // be folded with the isel so that we don't need to materialize a register
3228 bool PPCDAGToDAGISel::AllUsersSelectZero(SDNode *N) {
3229 // If we're not using isel, then this does not matter.
3230 if (!PPCSubTarget->hasISEL())
3233 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
3236 if (!User->isMachineOpcode())
3238 if (User->getMachineOpcode() != PPC::SELECT_I4 &&
3239 User->getMachineOpcode() != PPC::SELECT_I8)
3242 SDNode *Op2 = User->getOperand(2).getNode();
3243 if (!Op2->isMachineOpcode())
3246 if (Op2->getMachineOpcode() != PPC::LI &&
3247 Op2->getMachineOpcode() != PPC::LI8)
3250 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op2->getOperand(0));
3254 if (!C->isNullValue())
3261 void PPCDAGToDAGISel::SwapAllSelectUsers(SDNode *N) {
3262 SmallVector<SDNode *, 4> ToReplace;
3263 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
3266 assert((User->getMachineOpcode() == PPC::SELECT_I4 ||
3267 User->getMachineOpcode() == PPC::SELECT_I8) &&
3268 "Must have all select users");
3269 ToReplace.push_back(User);
3272 for (SmallVector<SDNode *, 4>::iterator UI = ToReplace.begin(),
3273 UE = ToReplace.end(); UI != UE; ++UI) {
3276 CurDAG->getMachineNode(User->getMachineOpcode(), SDLoc(User),
3277 User->getValueType(0), User->getOperand(0),
3278 User->getOperand(2),
3279 User->getOperand(1));
3281 DEBUG(dbgs() << "CR Peephole replacing:\nOld: ");
3282 DEBUG(User->dump(CurDAG));
3283 DEBUG(dbgs() << "\nNew: ");
3284 DEBUG(ResNode->dump(CurDAG));
3285 DEBUG(dbgs() << "\n");
3287 ReplaceUses(User, ResNode);
3291 void PPCDAGToDAGISel::PeepholeCROps() {
3295 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
3296 E = CurDAG->allnodes_end(); I != E; ++I) {
3297 MachineSDNode *MachineNode = dyn_cast<MachineSDNode>(I);
3298 if (!MachineNode || MachineNode->use_empty())
3300 SDNode *ResNode = MachineNode;
3302 bool Op1Set = false, Op1Unset = false,
3304 Op2Set = false, Op2Unset = false,
3307 unsigned Opcode = MachineNode->getMachineOpcode();
3318 SDValue Op = MachineNode->getOperand(1);
3319 if (Op.isMachineOpcode()) {
3320 if (Op.getMachineOpcode() == PPC::CRSET)
3322 else if (Op.getMachineOpcode() == PPC::CRUNSET)
3324 else if (Op.getMachineOpcode() == PPC::CRNOR &&
3325 Op.getOperand(0) == Op.getOperand(1))
3331 case PPC::SELECT_I4:
3332 case PPC::SELECT_I8:
3333 case PPC::SELECT_F4:
3334 case PPC::SELECT_F8:
3335 case PPC::SELECT_VRRC:
3336 case PPC::SELECT_VSFRC:
3337 case PPC::SELECT_VSRC: {
3338 SDValue Op = MachineNode->getOperand(0);
3339 if (Op.isMachineOpcode()) {
3340 if (Op.getMachineOpcode() == PPC::CRSET)
3342 else if (Op.getMachineOpcode() == PPC::CRUNSET)
3344 else if (Op.getMachineOpcode() == PPC::CRNOR &&
3345 Op.getOperand(0) == Op.getOperand(1))
3352 bool SelectSwap = false;
3356 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
3358 ResNode = MachineNode->getOperand(0).getNode();
3361 ResNode = MachineNode->getOperand(1).getNode();
3364 ResNode = MachineNode->getOperand(0).getNode();
3365 else if (Op1Unset || Op2Unset)
3366 // x & 0 = 0 & y = 0
3367 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
3370 // ~x & y = andc(y, x)
3371 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
3372 MVT::i1, MachineNode->getOperand(1),
3373 MachineNode->getOperand(0).
3376 // x & ~y = andc(x, y)
3377 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
3378 MVT::i1, MachineNode->getOperand(0),
3379 MachineNode->getOperand(1).
3381 else if (AllUsersSelectZero(MachineNode))
3382 ResNode = CurDAG->getMachineNode(PPC::CRNAND, SDLoc(MachineNode),
3383 MVT::i1, MachineNode->getOperand(0),
3384 MachineNode->getOperand(1)),
3388 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
3389 // nand(x, x) -> nor(x, x)
3390 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3391 MVT::i1, MachineNode->getOperand(0),
3392 MachineNode->getOperand(0));
3394 // nand(1, y) -> nor(y, y)
3395 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3396 MVT::i1, MachineNode->getOperand(1),
3397 MachineNode->getOperand(1));
3399 // nand(x, 1) -> nor(x, x)
3400 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3401 MVT::i1, MachineNode->getOperand(0),
3402 MachineNode->getOperand(0));
3403 else if (Op1Unset || Op2Unset)
3404 // nand(x, 0) = nand(0, y) = 1
3405 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
3408 // nand(~x, y) = ~(~x & y) = x | ~y = orc(x, y)
3409 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
3410 MVT::i1, MachineNode->getOperand(0).
3412 MachineNode->getOperand(1));
3414 // nand(x, ~y) = ~x | y = orc(y, x)
3415 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
3416 MVT::i1, MachineNode->getOperand(1).
3418 MachineNode->getOperand(0));
3419 else if (AllUsersSelectZero(MachineNode))
3420 ResNode = CurDAG->getMachineNode(PPC::CRAND, SDLoc(MachineNode),
3421 MVT::i1, MachineNode->getOperand(0),
3422 MachineNode->getOperand(1)),
3426 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
3428 ResNode = MachineNode->getOperand(0).getNode();
3429 else if (Op1Set || Op2Set)
3430 // x | 1 = 1 | y = 1
3431 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
3435 ResNode = MachineNode->getOperand(1).getNode();
3438 ResNode = MachineNode->getOperand(0).getNode();
3440 // ~x | y = orc(y, x)
3441 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
3442 MVT::i1, MachineNode->getOperand(1),
3443 MachineNode->getOperand(0).
3446 // x | ~y = orc(x, y)
3447 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
3448 MVT::i1, MachineNode->getOperand(0),
3449 MachineNode->getOperand(1).
3451 else if (AllUsersSelectZero(MachineNode))
3452 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3453 MVT::i1, MachineNode->getOperand(0),
3454 MachineNode->getOperand(1)),
3458 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
3460 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
3463 // xor(1, y) -> nor(y, y)
3464 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3465 MVT::i1, MachineNode->getOperand(1),
3466 MachineNode->getOperand(1));
3468 // xor(x, 1) -> nor(x, x)
3469 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3470 MVT::i1, MachineNode->getOperand(0),
3471 MachineNode->getOperand(0));
3474 ResNode = MachineNode->getOperand(1).getNode();
3477 ResNode = MachineNode->getOperand(0).getNode();
3479 // xor(~x, y) = eqv(x, y)
3480 ResNode = CurDAG->getMachineNode(PPC::CREQV, SDLoc(MachineNode),
3481 MVT::i1, MachineNode->getOperand(0).
3483 MachineNode->getOperand(1));
3485 // xor(x, ~y) = eqv(x, y)
3486 ResNode = CurDAG->getMachineNode(PPC::CREQV, SDLoc(MachineNode),
3487 MVT::i1, MachineNode->getOperand(0),
3488 MachineNode->getOperand(1).
3490 else if (AllUsersSelectZero(MachineNode))
3491 ResNode = CurDAG->getMachineNode(PPC::CREQV, SDLoc(MachineNode),
3492 MVT::i1, MachineNode->getOperand(0),
3493 MachineNode->getOperand(1)),
3497 if (Op1Set || Op2Set)
3499 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
3502 // nor(0, y) = ~y -> nor(y, y)
3503 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3504 MVT::i1, MachineNode->getOperand(1),
3505 MachineNode->getOperand(1));
3508 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3509 MVT::i1, MachineNode->getOperand(0),
3510 MachineNode->getOperand(0));
3512 // nor(~x, y) = andc(x, y)
3513 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
3514 MVT::i1, MachineNode->getOperand(0).
3516 MachineNode->getOperand(1));
3518 // nor(x, ~y) = andc(y, x)
3519 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
3520 MVT::i1, MachineNode->getOperand(1).
3522 MachineNode->getOperand(0));
3523 else if (AllUsersSelectZero(MachineNode))
3524 ResNode = CurDAG->getMachineNode(PPC::CROR, SDLoc(MachineNode),
3525 MVT::i1, MachineNode->getOperand(0),
3526 MachineNode->getOperand(1)),
3530 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
3532 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
3536 ResNode = MachineNode->getOperand(1).getNode();
3539 ResNode = MachineNode->getOperand(0).getNode();
3541 // eqv(0, y) = ~y -> nor(y, y)
3542 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3543 MVT::i1, MachineNode->getOperand(1),
3544 MachineNode->getOperand(1));
3547 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3548 MVT::i1, MachineNode->getOperand(0),
3549 MachineNode->getOperand(0));
3551 // eqv(~x, y) = xor(x, y)
3552 ResNode = CurDAG->getMachineNode(PPC::CRXOR, SDLoc(MachineNode),
3553 MVT::i1, MachineNode->getOperand(0).
3555 MachineNode->getOperand(1));
3557 // eqv(x, ~y) = xor(x, y)
3558 ResNode = CurDAG->getMachineNode(PPC::CRXOR, SDLoc(MachineNode),
3559 MVT::i1, MachineNode->getOperand(0),
3560 MachineNode->getOperand(1).
3562 else if (AllUsersSelectZero(MachineNode))
3563 ResNode = CurDAG->getMachineNode(PPC::CRXOR, SDLoc(MachineNode),
3564 MVT::i1, MachineNode->getOperand(0),
3565 MachineNode->getOperand(1)),
3569 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
3571 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
3575 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3576 MVT::i1, MachineNode->getOperand(1),
3577 MachineNode->getOperand(1));
3578 else if (Op1Unset || Op2Set)
3579 // andc(0, y) = andc(x, 1) = 0
3580 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
3584 ResNode = MachineNode->getOperand(0).getNode();
3586 // andc(~x, y) = ~(x | y) = nor(x, y)
3587 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3588 MVT::i1, MachineNode->getOperand(0).
3590 MachineNode->getOperand(1));
3592 // andc(x, ~y) = x & y
3593 ResNode = CurDAG->getMachineNode(PPC::CRAND, SDLoc(MachineNode),
3594 MVT::i1, MachineNode->getOperand(0),
3595 MachineNode->getOperand(1).
3597 else if (AllUsersSelectZero(MachineNode))
3598 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
3599 MVT::i1, MachineNode->getOperand(1),
3600 MachineNode->getOperand(0)),
3604 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
3606 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
3608 else if (Op1Set || Op2Unset)
3609 // orc(1, y) = orc(x, 0) = 1
3610 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
3614 ResNode = MachineNode->getOperand(0).getNode();
3617 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3618 MVT::i1, MachineNode->getOperand(1),
3619 MachineNode->getOperand(1));
3621 // orc(~x, y) = ~(x & y) = nand(x, y)
3622 ResNode = CurDAG->getMachineNode(PPC::CRNAND, SDLoc(MachineNode),
3623 MVT::i1, MachineNode->getOperand(0).
3625 MachineNode->getOperand(1));
3627 // orc(x, ~y) = x | y
3628 ResNode = CurDAG->getMachineNode(PPC::CROR, SDLoc(MachineNode),
3629 MVT::i1, MachineNode->getOperand(0),
3630 MachineNode->getOperand(1).
3632 else if (AllUsersSelectZero(MachineNode))
3633 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
3634 MVT::i1, MachineNode->getOperand(1),
3635 MachineNode->getOperand(0)),
3638 case PPC::SELECT_I4:
3639 case PPC::SELECT_I8:
3640 case PPC::SELECT_F4:
3641 case PPC::SELECT_F8:
3642 case PPC::SELECT_VRRC:
3643 case PPC::SELECT_VSFRC:
3644 case PPC::SELECT_VSRC:
3646 ResNode = MachineNode->getOperand(1).getNode();
3648 ResNode = MachineNode->getOperand(2).getNode();
3650 ResNode = CurDAG->getMachineNode(MachineNode->getMachineOpcode(),
3652 MachineNode->getValueType(0),
3653 MachineNode->getOperand(0).
3655 MachineNode->getOperand(2),
3656 MachineNode->getOperand(1));
3661 ResNode = CurDAG->getMachineNode(Opcode == PPC::BC ? PPC::BCn :
3665 MachineNode->getOperand(0).
3667 MachineNode->getOperand(1),
3668 MachineNode->getOperand(2));
3669 // FIXME: Handle Op1Set, Op1Unset here too.
3673 // If we're inverting this node because it is used only by selects that
3674 // we'd like to swap, then swap the selects before the node replacement.
3676 SwapAllSelectUsers(MachineNode);
3678 if (ResNode != MachineNode) {
3679 DEBUG(dbgs() << "CR Peephole replacing:\nOld: ");
3680 DEBUG(MachineNode->dump(CurDAG));
3681 DEBUG(dbgs() << "\nNew: ");
3682 DEBUG(ResNode->dump(CurDAG));
3683 DEBUG(dbgs() << "\n");
3685 ReplaceUses(MachineNode, ResNode);
3690 CurDAG->RemoveDeadNodes();
3691 } while (IsModified);
3694 // Gather the set of 32-bit operations that are known to have their
3695 // higher-order 32 bits zero, where ToPromote contains all such operations.
3696 static bool PeepholePPC64ZExtGather(SDValue Op32,
3697 SmallPtrSetImpl<SDNode *> &ToPromote) {
3698 if (!Op32.isMachineOpcode())
3701 // First, check for the "frontier" instructions (those that will clear the
3702 // higher-order 32 bits.
3704 // For RLWINM and RLWNM, we need to make sure that the mask does not wrap
3705 // around. If it does not, then these instructions will clear the
3706 // higher-order bits.
3707 if ((Op32.getMachineOpcode() == PPC::RLWINM ||
3708 Op32.getMachineOpcode() == PPC::RLWNM) &&
3709 Op32.getConstantOperandVal(2) <= Op32.getConstantOperandVal(3)) {
3710 ToPromote.insert(Op32.getNode());
3714 // SLW and SRW always clear the higher-order bits.
3715 if (Op32.getMachineOpcode() == PPC::SLW ||
3716 Op32.getMachineOpcode() == PPC::SRW) {
3717 ToPromote.insert(Op32.getNode());
3721 // For LI and LIS, we need the immediate to be positive (so that it is not
3723 if (Op32.getMachineOpcode() == PPC::LI ||
3724 Op32.getMachineOpcode() == PPC::LIS) {
3725 if (!isUInt<15>(Op32.getConstantOperandVal(0)))
3728 ToPromote.insert(Op32.getNode());
3732 // LHBRX and LWBRX always clear the higher-order bits.
3733 if (Op32.getMachineOpcode() == PPC::LHBRX ||
3734 Op32.getMachineOpcode() == PPC::LWBRX) {
3735 ToPromote.insert(Op32.getNode());
3739 // CNTLZW always produces a 64-bit value in [0,32], and so is zero extended.
3740 if (Op32.getMachineOpcode() == PPC::CNTLZW) {
3741 ToPromote.insert(Op32.getNode());
3745 // Next, check for those instructions we can look through.
3747 // Assuming the mask does not wrap around, then the higher-order bits are
3748 // taken directly from the first operand.
3749 if (Op32.getMachineOpcode() == PPC::RLWIMI &&
3750 Op32.getConstantOperandVal(3) <= Op32.getConstantOperandVal(4)) {
3751 SmallPtrSet<SDNode *, 16> ToPromote1;
3752 if (!PeepholePPC64ZExtGather(Op32.getOperand(0), ToPromote1))
3755 ToPromote.insert(Op32.getNode());
3756 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
3760 // For OR, the higher-order bits are zero if that is true for both operands.
3761 // For SELECT_I4, the same is true (but the relevant operand numbers are
3763 if (Op32.getMachineOpcode() == PPC::OR ||
3764 Op32.getMachineOpcode() == PPC::SELECT_I4) {
3765 unsigned B = Op32.getMachineOpcode() == PPC::SELECT_I4 ? 1 : 0;
3766 SmallPtrSet<SDNode *, 16> ToPromote1;
3767 if (!PeepholePPC64ZExtGather(Op32.getOperand(B+0), ToPromote1))
3769 if (!PeepholePPC64ZExtGather(Op32.getOperand(B+1), ToPromote1))
3772 ToPromote.insert(Op32.getNode());
3773 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
3777 // For ORI and ORIS, we need the higher-order bits of the first operand to be
3778 // zero, and also for the constant to be positive (so that it is not sign
3780 if (Op32.getMachineOpcode() == PPC::ORI ||
3781 Op32.getMachineOpcode() == PPC::ORIS) {
3782 SmallPtrSet<SDNode *, 16> ToPromote1;
3783 if (!PeepholePPC64ZExtGather(Op32.getOperand(0), ToPromote1))
3785 if (!isUInt<15>(Op32.getConstantOperandVal(1)))
3788 ToPromote.insert(Op32.getNode());
3789 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
3793 // The higher-order bits of AND are zero if that is true for at least one of
3795 if (Op32.getMachineOpcode() == PPC::AND) {
3796 SmallPtrSet<SDNode *, 16> ToPromote1, ToPromote2;
3798 PeepholePPC64ZExtGather(Op32.getOperand(0), ToPromote1);
3800 PeepholePPC64ZExtGather(Op32.getOperand(1), ToPromote2);
3801 if (!Op0OK && !Op1OK)
3804 ToPromote.insert(Op32.getNode());
3807 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
3810 ToPromote.insert(ToPromote2.begin(), ToPromote2.end());
3815 // For ANDI and ANDIS, the higher-order bits are zero if either that is true
3816 // of the first operand, or if the second operand is positive (so that it is
3817 // not sign extended).
3818 if (Op32.getMachineOpcode() == PPC::ANDIo ||
3819 Op32.getMachineOpcode() == PPC::ANDISo) {
3820 SmallPtrSet<SDNode *, 16> ToPromote1;
3822 PeepholePPC64ZExtGather(Op32.getOperand(0), ToPromote1);
3823 bool Op1OK = isUInt<15>(Op32.getConstantOperandVal(1));
3824 if (!Op0OK && !Op1OK)
3827 ToPromote.insert(Op32.getNode());
3830 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
3838 void PPCDAGToDAGISel::PeepholePPC64ZExt() {
3839 if (!PPCSubTarget->isPPC64())
3842 // When we zero-extend from i32 to i64, we use a pattern like this:
3843 // def : Pat<(i64 (zext i32:$in)),
3844 // (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32),
3846 // There are several 32-bit shift/rotate instructions, however, that will
3847 // clear the higher-order bits of their output, rendering the RLDICL
3848 // unnecessary. When that happens, we remove it here, and redefine the
3849 // relevant 32-bit operation to be a 64-bit operation.
3851 SelectionDAG::allnodes_iterator Position(CurDAG->getRoot().getNode());
3854 bool MadeChange = false;
3855 while (Position != CurDAG->allnodes_begin()) {
3856 SDNode *N = --Position;
3857 // Skip dead nodes and any non-machine opcodes.
3858 if (N->use_empty() || !N->isMachineOpcode())
3861 if (N->getMachineOpcode() != PPC::RLDICL)
3864 if (N->getConstantOperandVal(1) != 0 ||
3865 N->getConstantOperandVal(2) != 32)
3868 SDValue ISR = N->getOperand(0);
3869 if (!ISR.isMachineOpcode() ||
3870 ISR.getMachineOpcode() != TargetOpcode::INSERT_SUBREG)
3873 if (!ISR.hasOneUse())
3876 if (ISR.getConstantOperandVal(2) != PPC::sub_32)
3879 SDValue IDef = ISR.getOperand(0);
3880 if (!IDef.isMachineOpcode() ||
3881 IDef.getMachineOpcode() != TargetOpcode::IMPLICIT_DEF)
3884 // We now know that we're looking at a canonical i32 -> i64 zext. See if we
3885 // can get rid of it.
3887 SDValue Op32 = ISR->getOperand(1);
3888 if (!Op32.isMachineOpcode())
3891 // There are some 32-bit instructions that always clear the high-order 32
3892 // bits, there are also some instructions (like AND) that we can look
3894 SmallPtrSet<SDNode *, 16> ToPromote;
3895 if (!PeepholePPC64ZExtGather(Op32, ToPromote))
3898 // If the ToPromote set contains nodes that have uses outside of the set
3899 // (except for the original INSERT_SUBREG), then abort the transformation.
3900 bool OutsideUse = false;
3901 for (SDNode *PN : ToPromote) {
3902 for (SDNode *UN : PN->uses()) {
3903 if (!ToPromote.count(UN) && UN != ISR.getNode()) {
3917 // We now know that this zero extension can be removed by promoting to
3918 // nodes in ToPromote to 64-bit operations, where for operations in the
3919 // frontier of the set, we need to insert INSERT_SUBREGs for their
3921 for (SDNode *PN : ToPromote) {
3923 switch (PN->getMachineOpcode()) {
3925 llvm_unreachable("Don't know the 64-bit variant of this instruction");
3926 case PPC::RLWINM: NewOpcode = PPC::RLWINM8; break;
3927 case PPC::RLWNM: NewOpcode = PPC::RLWNM8; break;
3928 case PPC::SLW: NewOpcode = PPC::SLW8; break;
3929 case PPC::SRW: NewOpcode = PPC::SRW8; break;
3930 case PPC::LI: NewOpcode = PPC::LI8; break;
3931 case PPC::LIS: NewOpcode = PPC::LIS8; break;
3932 case PPC::LHBRX: NewOpcode = PPC::LHBRX8; break;
3933 case PPC::LWBRX: NewOpcode = PPC::LWBRX8; break;
3934 case PPC::CNTLZW: NewOpcode = PPC::CNTLZW8; break;
3935 case PPC::RLWIMI: NewOpcode = PPC::RLWIMI8; break;
3936 case PPC::OR: NewOpcode = PPC::OR8; break;
3937 case PPC::SELECT_I4: NewOpcode = PPC::SELECT_I8; break;
3938 case PPC::ORI: NewOpcode = PPC::ORI8; break;
3939 case PPC::ORIS: NewOpcode = PPC::ORIS8; break;
3940 case PPC::AND: NewOpcode = PPC::AND8; break;
3941 case PPC::ANDIo: NewOpcode = PPC::ANDIo8; break;
3942 case PPC::ANDISo: NewOpcode = PPC::ANDISo8; break;
3945 // Note: During the replacement process, the nodes will be in an
3946 // inconsistent state (some instructions will have operands with values
3947 // of the wrong type). Once done, however, everything should be right
3950 SmallVector<SDValue, 4> Ops;
3951 for (const SDValue &V : PN->ops()) {
3952 if (!ToPromote.count(V.getNode()) && V.getValueType() == MVT::i32 &&
3953 !isa<ConstantSDNode>(V)) {
3954 SDValue ReplOpOps[] = { ISR.getOperand(0), V, ISR.getOperand(2) };
3956 CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, SDLoc(V),
3957 ISR.getNode()->getVTList(), ReplOpOps);
3958 Ops.push_back(SDValue(ReplOp, 0));
3964 // Because all to-be-promoted nodes only have users that are other
3965 // promoted nodes (or the original INSERT_SUBREG), we can safely replace
3966 // the i32 result value type with i64.
3968 SmallVector<EVT, 2> NewVTs;
3969 SDVTList VTs = PN->getVTList();
3970 for (unsigned i = 0, ie = VTs.NumVTs; i != ie; ++i)
3971 if (VTs.VTs[i] == MVT::i32)
3972 NewVTs.push_back(MVT::i64);
3974 NewVTs.push_back(VTs.VTs[i]);
3976 DEBUG(dbgs() << "PPC64 ZExt Peephole morphing:\nOld: ");
3977 DEBUG(PN->dump(CurDAG));
3979 CurDAG->SelectNodeTo(PN, NewOpcode, CurDAG->getVTList(NewVTs), Ops);
3981 DEBUG(dbgs() << "\nNew: ");
3982 DEBUG(PN->dump(CurDAG));
3983 DEBUG(dbgs() << "\n");
3986 // Now we replace the original zero extend and its associated INSERT_SUBREG
3987 // with the value feeding the INSERT_SUBREG (which has now been promoted to
3990 DEBUG(dbgs() << "PPC64 ZExt Peephole replacing:\nOld: ");
3991 DEBUG(N->dump(CurDAG));
3992 DEBUG(dbgs() << "\nNew: ");
3993 DEBUG(Op32.getNode()->dump(CurDAG));
3994 DEBUG(dbgs() << "\n");
3996 ReplaceUses(N, Op32.getNode());
4000 CurDAG->RemoveDeadNodes();
4003 void PPCDAGToDAGISel::PeepholePPC64() {
4004 // These optimizations are currently supported only for 64-bit SVR4.
4005 if (PPCSubTarget->isDarwin() || !PPCSubTarget->isPPC64())
4008 SelectionDAG::allnodes_iterator Position(CurDAG->getRoot().getNode());
4011 while (Position != CurDAG->allnodes_begin()) {
4012 SDNode *N = --Position;
4013 // Skip dead nodes and any non-machine opcodes.
4014 if (N->use_empty() || !N->isMachineOpcode())
4018 unsigned StorageOpcode = N->getMachineOpcode();
4020 switch (StorageOpcode) {
4051 // If this is a load or store with a zero offset, we may be able to
4052 // fold an add-immediate into the memory operation.
4053 if (!isa<ConstantSDNode>(N->getOperand(FirstOp)) ||
4054 N->getConstantOperandVal(FirstOp) != 0)
4057 SDValue Base = N->getOperand(FirstOp + 1);
4058 if (!Base.isMachineOpcode())
4062 bool ReplaceFlags = true;
4064 // When the feeding operation is an add-immediate of some sort,
4065 // determine whether we need to add relocation information to the
4066 // target flags on the immediate operand when we fold it into the
4067 // load instruction.
4069 // For something like ADDItocL, the relocation information is
4070 // inferred from the opcode; when we process it in the AsmPrinter,
4071 // we add the necessary relocation there. A load, though, can receive
4072 // relocation from various flavors of ADDIxxx, so we need to carry
4073 // the relocation information in the target flags.
4074 switch (Base.getMachineOpcode()) {
4079 // In some cases (such as TLS) the relocation information
4080 // is already in place on the operand, so copying the operand
4082 ReplaceFlags = false;
4083 // For these cases, the immediate may not be divisible by 4, in
4084 // which case the fold is illegal for DS-form instructions. (The
4085 // other cases provide aligned addresses and are always safe.)
4086 if ((StorageOpcode == PPC::LWA ||
4087 StorageOpcode == PPC::LD ||
4088 StorageOpcode == PPC::STD) &&
4089 (!isa<ConstantSDNode>(Base.getOperand(1)) ||
4090 Base.getConstantOperandVal(1) % 4 != 0))
4093 case PPC::ADDIdtprelL:
4094 Flags = PPCII::MO_DTPREL_LO;
4096 case PPC::ADDItlsldL:
4097 Flags = PPCII::MO_TLSLD_LO;
4100 Flags = PPCII::MO_TOC_LO;
4104 // We found an opportunity. Reverse the operands from the add
4105 // immediate and substitute them into the load or store. If
4106 // needed, update the target flags for the immediate operand to
4107 // reflect the necessary relocation information.
4108 DEBUG(dbgs() << "Folding add-immediate into mem-op:\nBase: ");
4109 DEBUG(Base->dump(CurDAG));
4110 DEBUG(dbgs() << "\nN: ");
4111 DEBUG(N->dump(CurDAG));
4112 DEBUG(dbgs() << "\n");
4114 SDValue ImmOpnd = Base.getOperand(1);
4116 // If the relocation information isn't already present on the
4117 // immediate operand, add it now.
4119 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(ImmOpnd)) {
4121 const GlobalValue *GV = GA->getGlobal();
4122 // We can't perform this optimization for data whose alignment
4123 // is insufficient for the instruction encoding.
4124 if (GV->getAlignment() < 4 &&
4125 (StorageOpcode == PPC::LD || StorageOpcode == PPC::STD ||
4126 StorageOpcode == PPC::LWA)) {
4127 DEBUG(dbgs() << "Rejected this candidate for alignment.\n\n");
4130 ImmOpnd = CurDAG->getTargetGlobalAddress(GV, dl, MVT::i64, 0, Flags);
4131 } else if (ConstantPoolSDNode *CP =
4132 dyn_cast<ConstantPoolSDNode>(ImmOpnd)) {
4133 const Constant *C = CP->getConstVal();
4134 ImmOpnd = CurDAG->getTargetConstantPool(C, MVT::i64,
4140 if (FirstOp == 1) // Store
4141 (void)CurDAG->UpdateNodeOperands(N, N->getOperand(0), ImmOpnd,
4142 Base.getOperand(0), N->getOperand(3));
4144 (void)CurDAG->UpdateNodeOperands(N, ImmOpnd, Base.getOperand(0),
4147 // The add-immediate may now be dead, in which case remove it.
4148 if (Base.getNode()->use_empty())
4149 CurDAG->RemoveDeadNode(Base.getNode());
4154 /// createPPCISelDag - This pass converts a legalized DAG into a
4155 /// PowerPC-specific DAG, ready for instruction scheduling.
4157 FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) {
4158 return new PPCDAGToDAGISel(TM);
4161 static void initializePassOnce(PassRegistry &Registry) {
4162 const char *Name = "PowerPC DAG->DAG Pattern Instruction Selection";
4163 PassInfo *PI = new PassInfo(Name, "ppc-codegen", &SelectionDAGISel::ID,
4164 nullptr, false, false);
4165 Registry.registerPass(*PI, true);
4168 void llvm::initializePPCDAGToDAGISelPass(PassRegistry &Registry) {
4169 CALL_ONCE_INITIALIZATION(initializePassOnce);