1 //===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for PowerPC,
11 // converting from a legalized dag to a PPC dag.
13 //===----------------------------------------------------------------------===//
16 #include "MCTargetDesc/PPCPredicates.h"
17 #include "PPCTargetMachine.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/SelectionDAGISel.h"
23 #include "llvm/IR/Constants.h"
24 #include "llvm/IR/Function.h"
25 #include "llvm/IR/GlobalAlias.h"
26 #include "llvm/IR/GlobalValue.h"
27 #include "llvm/IR/GlobalVariable.h"
28 #include "llvm/IR/Intrinsics.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetOptions.h"
37 #define DEBUG_TYPE "ppc-codegen"
39 // FIXME: Remove this once the bug has been fixed!
40 cl::opt<bool> ANDIGlueBug("expose-ppc-andi-glue-bug",
41 cl::desc("expose the ANDI glue bug on PPC"), cl::Hidden);
44 void initializePPCDAGToDAGISelPass(PassRegistry&);
48 //===--------------------------------------------------------------------===//
49 /// PPCDAGToDAGISel - PPC specific code to select PPC machine
50 /// instructions for SelectionDAG operations.
52 class PPCDAGToDAGISel : public SelectionDAGISel {
53 const PPCTargetMachine &TM;
54 const PPCTargetLowering *PPCLowering;
55 const PPCSubtarget *PPCSubTarget;
56 unsigned GlobalBaseReg;
58 explicit PPCDAGToDAGISel(PPCTargetMachine &tm)
59 : SelectionDAGISel(tm), TM(tm),
60 PPCLowering(TM.getTargetLowering()),
61 PPCSubTarget(TM.getSubtargetImpl()) {
62 initializePPCDAGToDAGISelPass(*PassRegistry::getPassRegistry());
65 bool runOnMachineFunction(MachineFunction &MF) override {
66 // Make sure we re-emit a set of the global base reg if necessary
68 PPCLowering = TM.getTargetLowering();
69 PPCSubTarget = TM.getSubtargetImpl();
70 SelectionDAGISel::runOnMachineFunction(MF);
72 if (!PPCSubTarget->isSVR4ABI())
78 void PostprocessISelDAG() override;
80 /// getI32Imm - Return a target constant with the specified value, of type
82 inline SDValue getI32Imm(unsigned Imm) {
83 return CurDAG->getTargetConstant(Imm, MVT::i32);
86 /// getI64Imm - Return a target constant with the specified value, of type
88 inline SDValue getI64Imm(uint64_t Imm) {
89 return CurDAG->getTargetConstant(Imm, MVT::i64);
92 /// getSmallIPtrImm - Return a target constant of pointer type.
93 inline SDValue getSmallIPtrImm(unsigned Imm) {
94 return CurDAG->getTargetConstant(Imm, PPCLowering->getPointerTy());
97 /// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s
98 /// with any number of 0s on either side. The 1s are allowed to wrap from
99 /// LSB to MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs.
100 /// 0x0F0F0000 is not, since all 1s are not contiguous.
101 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME);
104 /// isRotateAndMask - Returns true if Mask and Shift can be folded into a
105 /// rotate and mask opcode and mask operation.
106 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool isShiftMask,
107 unsigned &SH, unsigned &MB, unsigned &ME);
109 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
110 /// base register. Return the virtual register that holds this value.
111 SDNode *getGlobalBaseReg();
113 // Select - Convert the specified operand from a target-independent to a
114 // target-specific node if it hasn't already been changed.
115 SDNode *Select(SDNode *N) override;
117 SDNode *SelectBitfieldInsert(SDNode *N);
119 /// SelectCC - Select a comparison of the specified values with the
120 /// specified condition code, returning the CR# of the expression.
121 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDLoc dl);
123 /// SelectAddrImm - Returns true if the address N can be represented by
124 /// a base register plus a signed 16-bit displacement [r+imm].
125 bool SelectAddrImm(SDValue N, SDValue &Disp,
127 return PPCLowering->SelectAddressRegImm(N, Disp, Base, *CurDAG, false);
130 /// SelectAddrImmOffs - Return true if the operand is valid for a preinc
131 /// immediate field. Note that the operand at this point is already the
132 /// result of a prior SelectAddressRegImm call.
133 bool SelectAddrImmOffs(SDValue N, SDValue &Out) const {
134 if (N.getOpcode() == ISD::TargetConstant ||
135 N.getOpcode() == ISD::TargetGlobalAddress) {
143 /// SelectAddrIdx - Given the specified addressed, check to see if it can be
144 /// represented as an indexed [r+r] operation. Returns false if it can
145 /// be represented by [r+imm], which are preferred.
146 bool SelectAddrIdx(SDValue N, SDValue &Base, SDValue &Index) {
147 return PPCLowering->SelectAddressRegReg(N, Base, Index, *CurDAG);
150 /// SelectAddrIdxOnly - Given the specified addressed, force it to be
151 /// represented as an indexed [r+r] operation.
152 bool SelectAddrIdxOnly(SDValue N, SDValue &Base, SDValue &Index) {
153 return PPCLowering->SelectAddressRegRegOnly(N, Base, Index, *CurDAG);
156 /// SelectAddrImmX4 - Returns true if the address N can be represented by
157 /// a base register plus a signed 16-bit displacement that is a multiple of 4.
158 /// Suitable for use by STD and friends.
159 bool SelectAddrImmX4(SDValue N, SDValue &Disp, SDValue &Base) {
160 return PPCLowering->SelectAddressRegImm(N, Disp, Base, *CurDAG, true);
163 // Select an address into a single register.
164 bool SelectAddr(SDValue N, SDValue &Base) {
169 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
170 /// inline asm expressions. It is always correct to compute the value into
171 /// a register. The case of adding a (possibly relocatable) constant to a
172 /// register can be improved, but it is wrong to substitute Reg+Reg for
173 /// Reg in an asm, because the load or store opcode would have to change.
174 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
176 std::vector<SDValue> &OutOps) override {
177 OutOps.push_back(Op);
181 void InsertVRSaveCode(MachineFunction &MF);
183 const char *getPassName() const override {
184 return "PowerPC DAG->DAG Pattern Instruction Selection";
187 // Include the pieces autogenerated from the target description.
188 #include "PPCGenDAGISel.inc"
191 SDNode *SelectSETCC(SDNode *N);
193 void PeepholePPC64();
194 void PeepholeCROps();
196 bool AllUsersSelectZero(SDNode *N);
197 void SwapAllSelectUsers(SDNode *N);
201 /// InsertVRSaveCode - Once the entire function has been instruction selected,
202 /// all virtual registers are created and all machine instructions are built,
203 /// check to see if we need to save/restore VRSAVE. If so, do it.
204 void PPCDAGToDAGISel::InsertVRSaveCode(MachineFunction &Fn) {
205 // Check to see if this function uses vector registers, which means we have to
206 // save and restore the VRSAVE register and update it with the regs we use.
208 // In this case, there will be virtual registers of vector type created
209 // by the scheduler. Detect them now.
210 bool HasVectorVReg = false;
211 for (unsigned i = 0, e = RegInfo->getNumVirtRegs(); i != e; ++i) {
212 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
213 if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) {
214 HasVectorVReg = true;
218 if (!HasVectorVReg) return; // nothing to do.
220 // If we have a vector register, we want to emit code into the entry and exit
221 // blocks to save and restore the VRSAVE register. We do this here (instead
222 // of marking all vector instructions as clobbering VRSAVE) for two reasons:
224 // 1. This (trivially) reduces the load on the register allocator, by not
225 // having to represent the live range of the VRSAVE register.
226 // 2. This (more significantly) allows us to create a temporary virtual
227 // register to hold the saved VRSAVE value, allowing this temporary to be
228 // register allocated, instead of forcing it to be spilled to the stack.
230 // Create two vregs - one to hold the VRSAVE register that is live-in to the
231 // function and one for the value after having bits or'd into it.
232 unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
233 unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
235 const TargetInstrInfo &TII = *TM.getInstrInfo();
236 MachineBasicBlock &EntryBB = *Fn.begin();
238 // Emit the following code into the entry block:
239 // InVRSAVE = MFVRSAVE
240 // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
241 // MTVRSAVE UpdatedVRSAVE
242 MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
243 BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE);
244 BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE),
245 UpdatedVRSAVE).addReg(InVRSAVE);
246 BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
248 // Find all return blocks, outputting a restore in each epilog.
249 for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
250 if (!BB->empty() && BB->back().isReturn()) {
251 IP = BB->end(); --IP;
253 // Skip over all terminator instructions, which are part of the return
255 MachineBasicBlock::iterator I2 = IP;
256 while (I2 != BB->begin() && (--I2)->isTerminator())
259 // Emit: MTVRSAVE InVRSave
260 BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
266 /// getGlobalBaseReg - Output the instructions required to put the
267 /// base address to use for accessing globals into a register.
269 SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
270 if (!GlobalBaseReg) {
271 const TargetInstrInfo &TII = *TM.getInstrInfo();
272 // Insert the set of GlobalBaseReg into the first MBB of the function
273 MachineBasicBlock &FirstMBB = MF->front();
274 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
277 if (PPCLowering->getPointerTy() == MVT::i32) {
278 GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::GPRC_NOR0RegClass);
279 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));
280 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
282 GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::G8RC_NOX0RegClass);
283 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8));
284 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg);
287 return CurDAG->getRegister(GlobalBaseReg,
288 PPCLowering->getPointerTy()).getNode();
291 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
292 /// or 64-bit immediate, and if the value can be accurately represented as a
293 /// sign extension from a 16-bit value. If so, this returns true and the
295 static bool isIntS16Immediate(SDNode *N, short &Imm) {
296 if (N->getOpcode() != ISD::Constant)
299 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
300 if (N->getValueType(0) == MVT::i32)
301 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
303 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
306 static bool isIntS16Immediate(SDValue Op, short &Imm) {
307 return isIntS16Immediate(Op.getNode(), Imm);
311 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
312 /// operand. If so Imm will receive the 32-bit value.
313 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
314 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
315 Imm = cast<ConstantSDNode>(N)->getZExtValue();
321 /// isInt64Immediate - This method tests to see if the node is a 64-bit constant
322 /// operand. If so Imm will receive the 64-bit value.
323 static bool isInt64Immediate(SDNode *N, uint64_t &Imm) {
324 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
325 Imm = cast<ConstantSDNode>(N)->getZExtValue();
331 // isInt32Immediate - This method tests to see if a constant operand.
332 // If so Imm will receive the 32 bit value.
333 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
334 return isInt32Immediate(N.getNode(), Imm);
338 // isOpcWithIntImmediate - This method tests to see if the node is a specific
339 // opcode and that it has a immediate integer right operand.
340 // If so Imm will receive the 32 bit value.
341 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
342 return N->getOpcode() == Opc
343 && isInt32Immediate(N->getOperand(1).getNode(), Imm);
346 bool PPCDAGToDAGISel::isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
350 if (isShiftedMask_32(Val)) {
351 // look for the first non-zero bit
352 MB = countLeadingZeros(Val);
353 // look for the first zero bit after the run of ones
354 ME = countLeadingZeros((Val - 1) ^ Val);
357 Val = ~Val; // invert mask
358 if (isShiftedMask_32(Val)) {
359 // effectively look for the first zero bit
360 ME = countLeadingZeros(Val) - 1;
361 // effectively look for the first one bit after the run of zeros
362 MB = countLeadingZeros((Val - 1) ^ Val) + 1;
370 bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask,
371 bool isShiftMask, unsigned &SH,
372 unsigned &MB, unsigned &ME) {
373 // Don't even go down this path for i64, since different logic will be
374 // necessary for rldicl/rldicr/rldimi.
375 if (N->getValueType(0) != MVT::i32)
379 unsigned Indeterminant = ~0; // bit mask marking indeterminant results
380 unsigned Opcode = N->getOpcode();
381 if (N->getNumOperands() != 2 ||
382 !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31))
385 if (Opcode == ISD::SHL) {
386 // apply shift left to mask if it comes first
387 if (isShiftMask) Mask = Mask << Shift;
388 // determine which bits are made indeterminant by shift
389 Indeterminant = ~(0xFFFFFFFFu << Shift);
390 } else if (Opcode == ISD::SRL) {
391 // apply shift right to mask if it comes first
392 if (isShiftMask) Mask = Mask >> Shift;
393 // determine which bits are made indeterminant by shift
394 Indeterminant = ~(0xFFFFFFFFu >> Shift);
395 // adjust for the left rotate
397 } else if (Opcode == ISD::ROTL) {
403 // if the mask doesn't intersect any Indeterminant bits
404 if (Mask && !(Mask & Indeterminant)) {
406 // make sure the mask is still a mask (wrap arounds may not be)
407 return isRunOfOnes(Mask, MB, ME);
412 /// SelectBitfieldInsert - turn an or of two masked values into
413 /// the rotate left word immediate then mask insert (rlwimi) instruction.
414 SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
415 SDValue Op0 = N->getOperand(0);
416 SDValue Op1 = N->getOperand(1);
419 APInt LKZ, LKO, RKZ, RKO;
420 CurDAG->computeKnownBits(Op0, LKZ, LKO);
421 CurDAG->computeKnownBits(Op1, RKZ, RKO);
423 unsigned TargetMask = LKZ.getZExtValue();
424 unsigned InsertMask = RKZ.getZExtValue();
426 if ((TargetMask | InsertMask) == 0xFFFFFFFF) {
427 unsigned Op0Opc = Op0.getOpcode();
428 unsigned Op1Opc = Op1.getOpcode();
429 unsigned Value, SH = 0;
430 TargetMask = ~TargetMask;
431 InsertMask = ~InsertMask;
433 // If the LHS has a foldable shift and the RHS does not, then swap it to the
434 // RHS so that we can fold the shift into the insert.
435 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
436 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
437 Op0.getOperand(0).getOpcode() == ISD::SRL) {
438 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
439 Op1.getOperand(0).getOpcode() != ISD::SRL) {
441 std::swap(Op0Opc, Op1Opc);
442 std::swap(TargetMask, InsertMask);
445 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
446 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
447 Op1.getOperand(0).getOpcode() != ISD::SRL) {
449 std::swap(Op0Opc, Op1Opc);
450 std::swap(TargetMask, InsertMask);
455 if (isRunOfOnes(InsertMask, MB, ME)) {
458 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
459 isInt32Immediate(Op1.getOperand(1), Value)) {
460 Op1 = Op1.getOperand(0);
461 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value;
463 if (Op1Opc == ISD::AND) {
464 // The AND mask might not be a constant, and we need to make sure that
465 // if we're going to fold the masking with the insert, all bits not
466 // know to be zero in the mask are known to be one.
468 CurDAG->computeKnownBits(Op1.getOperand(1), MKZ, MKO);
469 bool CanFoldMask = InsertMask == MKO.getZExtValue();
471 unsigned SHOpc = Op1.getOperand(0).getOpcode();
472 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && CanFoldMask &&
473 isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) {
474 // Note that Value must be in range here (less than 32) because
475 // otherwise there would not be any bits set in InsertMask.
476 Op1 = Op1.getOperand(0).getOperand(0);
477 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value;
482 SDValue Ops[] = { Op0, Op1, getI32Imm(SH), getI32Imm(MB),
484 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops);
490 /// SelectCC - Select a comparison of the specified values with the specified
491 /// condition code, returning the CR# of the expression.
492 SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS,
493 ISD::CondCode CC, SDLoc dl) {
494 // Always select the LHS.
497 if (LHS.getValueType() == MVT::i32) {
499 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
500 if (isInt32Immediate(RHS, Imm)) {
501 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
503 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
504 getI32Imm(Imm & 0xFFFF)), 0);
505 // If this is a 16-bit signed immediate, fold it.
506 if (isInt<16>((int)Imm))
507 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
508 getI32Imm(Imm & 0xFFFF)), 0);
510 // For non-equality comparisons, the default code would materialize the
511 // constant, then compare against it, like this:
515 // Since we are just comparing for equality, we can emit this instead:
516 // xoris r0,r3,0x1234
517 // cmplwi cr0,r0,0x5678
519 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS, dl, MVT::i32, LHS,
520 getI32Imm(Imm >> 16)), 0);
521 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, Xor,
522 getI32Imm(Imm & 0xFFFF)), 0);
525 } else if (ISD::isUnsignedIntSetCC(CC)) {
526 if (isInt32Immediate(RHS, Imm) && isUInt<16>(Imm))
527 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
528 getI32Imm(Imm & 0xFFFF)), 0);
532 if (isIntS16Immediate(RHS, SImm))
533 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
534 getI32Imm((int)SImm & 0xFFFF)),
538 } else if (LHS.getValueType() == MVT::i64) {
540 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
541 if (isInt64Immediate(RHS.getNode(), Imm)) {
542 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
544 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
545 getI32Imm(Imm & 0xFFFF)), 0);
546 // If this is a 16-bit signed immediate, fold it.
548 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
549 getI32Imm(Imm & 0xFFFF)), 0);
551 // For non-equality comparisons, the default code would materialize the
552 // constant, then compare against it, like this:
556 // Since we are just comparing for equality, we can emit this instead:
557 // xoris r0,r3,0x1234
558 // cmpldi cr0,r0,0x5678
560 if (isUInt<32>(Imm)) {
561 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS8, dl, MVT::i64, LHS,
562 getI64Imm(Imm >> 16)), 0);
563 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, Xor,
564 getI64Imm(Imm & 0xFFFF)), 0);
568 } else if (ISD::isUnsignedIntSetCC(CC)) {
569 if (isInt64Immediate(RHS.getNode(), Imm) && isUInt<16>(Imm))
570 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
571 getI64Imm(Imm & 0xFFFF)), 0);
575 if (isIntS16Immediate(RHS, SImm))
576 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
577 getI64Imm(SImm & 0xFFFF)),
581 } else if (LHS.getValueType() == MVT::f32) {
584 assert(LHS.getValueType() == MVT::f64 && "Unknown vt!");
585 Opc = PPCSubTarget->hasVSX() ? PPC::XSCMPUDP : PPC::FCMPUD;
587 return SDValue(CurDAG->getMachineNode(Opc, dl, MVT::i32, LHS, RHS), 0);
590 static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {
596 llvm_unreachable("Should be lowered by legalize!");
597 default: llvm_unreachable("Unknown condition!");
599 case ISD::SETEQ: return PPC::PRED_EQ;
601 case ISD::SETNE: return PPC::PRED_NE;
603 case ISD::SETLT: return PPC::PRED_LT;
605 case ISD::SETLE: return PPC::PRED_LE;
607 case ISD::SETGT: return PPC::PRED_GT;
609 case ISD::SETGE: return PPC::PRED_GE;
610 case ISD::SETO: return PPC::PRED_NU;
611 case ISD::SETUO: return PPC::PRED_UN;
612 // These two are invalid for floating point. Assume we have int.
613 case ISD::SETULT: return PPC::PRED_LT;
614 case ISD::SETUGT: return PPC::PRED_GT;
618 /// getCRIdxForSetCC - Return the index of the condition register field
619 /// associated with the SetCC condition, and whether or not the field is
620 /// treated as inverted. That is, lt = 0; ge = 0 inverted.
621 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert) {
624 default: llvm_unreachable("Unknown condition!");
626 case ISD::SETLT: return 0; // Bit #0 = SETOLT
628 case ISD::SETGT: return 1; // Bit #1 = SETOGT
630 case ISD::SETEQ: return 2; // Bit #2 = SETOEQ
631 case ISD::SETUO: return 3; // Bit #3 = SETUO
633 case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE
635 case ISD::SETLE: Invert = true; return 1; // !Bit #1 = SETULE
637 case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE
638 case ISD::SETO: Invert = true; return 3; // !Bit #3 = SETO
643 llvm_unreachable("Invalid branch code: should be expanded by legalize");
644 // These are invalid for floating point. Assume integer.
645 case ISD::SETULT: return 0;
646 case ISD::SETUGT: return 1;
650 // getVCmpInst: return the vector compare instruction for the specified
651 // vector type and condition code. Since this is for altivec specific code,
652 // only support the altivec types (v16i8, v8i16, v4i32, and v4f32).
653 static unsigned int getVCmpInst(MVT::SimpleValueType VecVT, ISD::CondCode CC,
660 if (VecVT == MVT::v16i8)
661 return PPC::VCMPEQUB;
662 else if (VecVT == MVT::v8i16)
663 return PPC::VCMPEQUH;
664 else if (VecVT == MVT::v4i32)
665 return PPC::VCMPEQUW;
666 // v4f32 != v4f32 could be translate to unordered not equal
667 else if (VecVT == MVT::v4f32)
668 return HasVSX ? PPC::XVCMPEQSP : PPC::VCMPEQFP;
669 else if (VecVT == MVT::v2f64)
670 return PPC::XVCMPEQDP;
676 if (VecVT == MVT::v16i8)
677 return PPC::VCMPGTSB;
678 else if (VecVT == MVT::v8i16)
679 return PPC::VCMPGTSH;
680 else if (VecVT == MVT::v4i32)
681 return PPC::VCMPGTSW;
682 else if (VecVT == MVT::v4f32)
683 return HasVSX ? PPC::XVCMPGTSP : PPC::VCMPGTFP;
684 else if (VecVT == MVT::v2f64)
685 return PPC::XVCMPGTDP;
691 if (VecVT == MVT::v16i8)
692 return PPC::VCMPGTUB;
693 else if (VecVT == MVT::v8i16)
694 return PPC::VCMPGTUH;
695 else if (VecVT == MVT::v4i32)
696 return PPC::VCMPGTUW;
699 if (VecVT == MVT::v4f32)
700 return HasVSX ? PPC::XVCMPEQSP : PPC::VCMPEQFP;
701 else if (VecVT == MVT::v2f64)
702 return PPC::XVCMPEQDP;
707 if (VecVT == MVT::v4f32)
708 return HasVSX ? PPC::XVCMPGTSP : PPC::VCMPGTFP;
709 else if (VecVT == MVT::v2f64)
710 return PPC::XVCMPGTDP;
713 if (VecVT == MVT::v4f32)
714 return HasVSX ? PPC::XVCMPGESP : PPC::VCMPGEFP;
715 else if (VecVT == MVT::v2f64)
716 return PPC::XVCMPGEDP;
721 llvm_unreachable("Invalid integer vector compare condition");
724 // getVCmpEQInst: return the equal compare instruction for the specified vector
725 // type. Since this is for altivec specific code, only support the altivec
726 // types (v16i8, v8i16, v4i32, and v4f32).
727 static unsigned int getVCmpEQInst(MVT::SimpleValueType VecVT, bool HasVSX) {
730 return PPC::VCMPEQUB;
732 return PPC::VCMPEQUH;
734 return PPC::VCMPEQUW;
736 return HasVSX ? PPC::XVCMPEQSP : PPC::VCMPEQFP;
738 return PPC::XVCMPEQDP;
740 llvm_unreachable("Invalid integer vector compare condition");
744 SDNode *PPCDAGToDAGISel::SelectSETCC(SDNode *N) {
747 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
748 EVT PtrVT = CurDAG->getTargetLoweringInfo().getPointerTy();
749 bool isPPC64 = (PtrVT == MVT::i64);
751 if (!PPCSubTarget->useCRBits() &&
752 isInt32Immediate(N->getOperand(1), Imm)) {
753 // We can codegen setcc op, imm very efficiently compared to a brcond.
754 // Check for those cases here.
757 SDValue Op = N->getOperand(0);
761 Op = SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Op), 0);
762 SDValue Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) };
763 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
768 SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
769 Op, getI32Imm(~0U)), 0);
770 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
774 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
775 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
779 SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Op), 0);
780 T = SDValue(CurDAG->getMachineNode(PPC::ANDC, dl, MVT::i32, T, Op), 0);
781 SDValue Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
782 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
785 } else if (Imm == ~0U) { // setcc op, -1
786 SDValue Op = N->getOperand(0);
791 Op = SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
792 Op, getI32Imm(1)), 0);
793 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
794 SDValue(CurDAG->getMachineNode(PPC::LI, dl,
800 Op = SDValue(CurDAG->getMachineNode(PPC::NOR, dl, MVT::i32, Op, Op), 0);
801 SDNode *AD = CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
803 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0),
807 SDValue AD = SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Op,
809 SDValue AN = SDValue(CurDAG->getMachineNode(PPC::AND, dl, MVT::i32, AD,
811 SDValue Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
812 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
815 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
816 Op = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops),
818 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op,
825 SDValue LHS = N->getOperand(0);
826 SDValue RHS = N->getOperand(1);
828 // Altivec Vector compare instructions do not set any CR register by default and
829 // vector compare operations return the same type as the operands.
830 if (LHS.getValueType().isVector()) {
831 EVT VecVT = LHS.getValueType();
832 MVT::SimpleValueType VT = VecVT.getSimpleVT().SimpleTy;
833 unsigned int VCmpInst = getVCmpInst(VT, CC, PPCSubTarget->hasVSX());
839 return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS);
843 SDValue VCmp(CurDAG->getMachineNode(VCmpInst, dl, VecVT, LHS, RHS), 0);
844 return CurDAG->SelectNodeTo(N, PPCSubTarget->hasVSX() ? PPC::XXLNOR :
851 return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, RHS, LHS);
855 return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS);
859 // Small optimization: Altivec provides a 'Vector Compare Greater Than
860 // or Equal To' instruction (vcmpgefp), so in this case there is no
861 // need for extra logic for the equal compare.
862 if (VecVT.getSimpleVT().isFloatingPoint()) {
863 return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS);
865 SDValue VCmpGT(CurDAG->getMachineNode(VCmpInst, dl, VecVT, LHS, RHS), 0);
866 unsigned int VCmpEQInst = getVCmpEQInst(VT, PPCSubTarget->hasVSX());
867 SDValue VCmpEQ(CurDAG->getMachineNode(VCmpEQInst, dl, VecVT, LHS, RHS), 0);
868 return CurDAG->SelectNodeTo(N, PPCSubTarget->hasVSX() ? PPC::XXLOR :
870 VecVT, VCmpGT, VCmpEQ);
876 SDValue VCmpLE(CurDAG->getMachineNode(VCmpInst, dl, VecVT, RHS, LHS), 0);
877 unsigned int VCmpEQInst = getVCmpEQInst(VT, PPCSubTarget->hasVSX());
878 SDValue VCmpEQ(CurDAG->getMachineNode(VCmpEQInst, dl, VecVT, LHS, RHS), 0);
879 return CurDAG->SelectNodeTo(N, PPCSubTarget->hasVSX() ? PPC::XXLOR :
881 VecVT, VCmpLE, VCmpEQ);
884 llvm_unreachable("Invalid vector compare type: should be expanded by legalize");
888 if (PPCSubTarget->useCRBits())
892 unsigned Idx = getCRIdxForSetCC(CC, Inv);
893 SDValue CCReg = SelectCC(LHS, RHS, CC, dl);
896 // Force the ccreg into CR7.
897 SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
899 SDValue InFlag(nullptr, 0); // Null incoming flag value.
900 CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, CR7Reg, CCReg,
903 IntCR = SDValue(CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg,
906 SDValue Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31),
907 getI32Imm(31), getI32Imm(31) };
909 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
911 // Get the specified bit.
913 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0);
914 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
918 // Select - Convert the specified operand from a target-independent to a
919 // target-specific node if it hasn't already been changed.
920 SDNode *PPCDAGToDAGISel::Select(SDNode *N) {
922 if (N->isMachineOpcode()) {
924 return nullptr; // Already selected.
927 switch (N->getOpcode()) {
930 case ISD::Constant: {
931 if (N->getValueType(0) == MVT::i64) {
933 int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue();
934 // Assume no remaining bits.
935 unsigned Remainder = 0;
936 // Assume no shift required.
939 // If it can't be represented as a 32 bit value.
940 if (!isInt<32>(Imm)) {
941 Shift = countTrailingZeros<uint64_t>(Imm);
942 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
944 // If the shifted value fits 32 bits.
945 if (isInt<32>(ImmSh)) {
946 // Go with the shifted value.
949 // Still stuck with a 64 bit value.
956 // Intermediate operand.
959 // Handle first 32 bits.
960 unsigned Lo = Imm & 0xFFFF;
961 unsigned Hi = (Imm >> 16) & 0xFFFF;
964 if (isInt<16>(Imm)) {
966 Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo));
968 // Handle the Hi bits.
969 unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8;
970 Result = CurDAG->getMachineNode(OpC, dl, MVT::i64, getI32Imm(Hi));
972 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
973 SDValue(Result, 0), getI32Imm(Lo));
976 Result = CurDAG->getMachineNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi));
979 // If no shift, we're done.
980 if (!Shift) return Result;
982 // Shift for next step if the upper 32-bits were not zero.
984 Result = CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64,
987 getI32Imm(63 - Shift));
990 // Add in the last bits as required.
991 if ((Hi = (Remainder >> 16) & 0xFFFF)) {
992 Result = CurDAG->getMachineNode(PPC::ORIS8, dl, MVT::i64,
993 SDValue(Result, 0), getI32Imm(Hi));
995 if ((Lo = Remainder & 0xFFFF)) {
996 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
997 SDValue(Result, 0), getI32Imm(Lo));
1006 SDNode *SN = SelectSETCC(N);
1011 case PPCISD::GlobalBaseReg:
1012 return getGlobalBaseReg();
1014 case ISD::FrameIndex: {
1015 int FI = cast<FrameIndexSDNode>(N)->getIndex();
1016 SDValue TFI = CurDAG->getTargetFrameIndex(FI, N->getValueType(0));
1017 unsigned Opc = N->getValueType(0) == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
1019 return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), TFI,
1020 getSmallIPtrImm(0));
1021 return CurDAG->getMachineNode(Opc, dl, N->getValueType(0), TFI,
1022 getSmallIPtrImm(0));
1025 case PPCISD::MFOCRF: {
1026 SDValue InFlag = N->getOperand(1);
1027 return CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32,
1028 N->getOperand(0), InFlag);
1032 // FIXME: since this depends on the setting of the carry flag from the srawi
1033 // we should really be making notes about that for the scheduler.
1034 // FIXME: It sure would be nice if we could cheaply recognize the
1035 // srl/add/sra pattern the dag combiner will generate for this as
1036 // sra/addze rather than having to handle sdiv ourselves. oh well.
1038 if (isInt32Immediate(N->getOperand(1), Imm)) {
1039 SDValue N0 = N->getOperand(0);
1040 if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
1042 CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Glue,
1043 N0, getI32Imm(Log2_32(Imm)));
1044 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
1045 SDValue(Op, 0), SDValue(Op, 1));
1046 } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
1048 CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Glue,
1049 N0, getI32Imm(Log2_32(-Imm)));
1051 SDValue(CurDAG->getMachineNode(PPC::ADDZE, dl, MVT::i32,
1052 SDValue(Op, 0), SDValue(Op, 1)),
1054 return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
1058 // Other cases are autogenerated.
1063 // Handle preincrement loads.
1064 LoadSDNode *LD = cast<LoadSDNode>(N);
1065 EVT LoadedVT = LD->getMemoryVT();
1067 // Normal loads are handled by code generated from the .td file.
1068 if (LD->getAddressingMode() != ISD::PRE_INC)
1071 SDValue Offset = LD->getOffset();
1072 if (Offset.getOpcode() == ISD::TargetConstant ||
1073 Offset.getOpcode() == ISD::TargetGlobalAddress) {
1076 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
1077 if (LD->getValueType(0) != MVT::i64) {
1078 // Handle PPC32 integer and normal FP loads.
1079 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
1080 switch (LoadedVT.getSimpleVT().SimpleTy) {
1081 default: llvm_unreachable("Invalid PPC load type!");
1082 case MVT::f64: Opcode = PPC::LFDU; break;
1083 case MVT::f32: Opcode = PPC::LFSU; break;
1084 case MVT::i32: Opcode = PPC::LWZU; break;
1085 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
1087 case MVT::i8: Opcode = PPC::LBZU; break;
1090 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
1091 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
1092 switch (LoadedVT.getSimpleVT().SimpleTy) {
1093 default: llvm_unreachable("Invalid PPC load type!");
1094 case MVT::i64: Opcode = PPC::LDU; break;
1095 case MVT::i32: Opcode = PPC::LWZU8; break;
1096 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
1098 case MVT::i8: Opcode = PPC::LBZU8; break;
1102 SDValue Chain = LD->getChain();
1103 SDValue Base = LD->getBasePtr();
1104 SDValue Ops[] = { Offset, Base, Chain };
1105 return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0),
1106 PPCLowering->getPointerTy(),
1110 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
1111 if (LD->getValueType(0) != MVT::i64) {
1112 // Handle PPC32 integer and normal FP loads.
1113 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
1114 switch (LoadedVT.getSimpleVT().SimpleTy) {
1115 default: llvm_unreachable("Invalid PPC load type!");
1116 case MVT::f64: Opcode = PPC::LFDUX; break;
1117 case MVT::f32: Opcode = PPC::LFSUX; break;
1118 case MVT::i32: Opcode = PPC::LWZUX; break;
1119 case MVT::i16: Opcode = isSExt ? PPC::LHAUX : PPC::LHZUX; break;
1121 case MVT::i8: Opcode = PPC::LBZUX; break;
1124 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
1125 assert((!isSExt || LoadedVT == MVT::i16 || LoadedVT == MVT::i32) &&
1126 "Invalid sext update load");
1127 switch (LoadedVT.getSimpleVT().SimpleTy) {
1128 default: llvm_unreachable("Invalid PPC load type!");
1129 case MVT::i64: Opcode = PPC::LDUX; break;
1130 case MVT::i32: Opcode = isSExt ? PPC::LWAUX : PPC::LWZUX8; break;
1131 case MVT::i16: Opcode = isSExt ? PPC::LHAUX8 : PPC::LHZUX8; break;
1133 case MVT::i8: Opcode = PPC::LBZUX8; break;
1137 SDValue Chain = LD->getChain();
1138 SDValue Base = LD->getBasePtr();
1139 SDValue Ops[] = { Base, Offset, Chain };
1140 return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0),
1141 PPCLowering->getPointerTy(),
1147 unsigned Imm, Imm2, SH, MB, ME;
1150 // If this is an and of a value rotated between 0 and 31 bits and then and'd
1151 // with a mask, emit rlwinm
1152 if (isInt32Immediate(N->getOperand(1), Imm) &&
1153 isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH, MB, ME)) {
1154 SDValue Val = N->getOperand(0).getOperand(0);
1155 SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
1156 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
1158 // If this is just a masked value where the input is not handled above, and
1159 // is not a rotate-left (handled by a pattern in the .td file), emit rlwinm
1160 if (isInt32Immediate(N->getOperand(1), Imm) &&
1161 isRunOfOnes(Imm, MB, ME) &&
1162 N->getOperand(0).getOpcode() != ISD::ROTL) {
1163 SDValue Val = N->getOperand(0);
1164 SDValue Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) };
1165 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
1167 // If this is a 64-bit zero-extension mask, emit rldicl.
1168 if (isInt64Immediate(N->getOperand(1).getNode(), Imm64) &&
1170 SDValue Val = N->getOperand(0);
1171 MB = 64 - CountTrailingOnes_64(Imm64);
1174 // If the operand is a logical right shift, we can fold it into this
1175 // instruction: rldicl(rldicl(x, 64-n, n), 0, mb) -> rldicl(x, 64-n, mb)
1176 // for n <= mb. The right shift is really a left rotate followed by a
1177 // mask, and this mask is a more-restrictive sub-mask of the mask implied
1179 if (Val.getOpcode() == ISD::SRL &&
1180 isInt32Immediate(Val.getOperand(1).getNode(), Imm) && Imm <= MB) {
1181 assert(Imm < 64 && "Illegal shift amount");
1182 Val = Val.getOperand(0);
1186 SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB) };
1187 return CurDAG->SelectNodeTo(N, PPC::RLDICL, MVT::i64, Ops);
1189 // AND X, 0 -> 0, not "rlwinm 32".
1190 if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) {
1191 ReplaceUses(SDValue(N, 0), N->getOperand(1));
1194 // ISD::OR doesn't get all the bitfield insertion fun.
1195 // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert
1196 if (isInt32Immediate(N->getOperand(1), Imm) &&
1197 N->getOperand(0).getOpcode() == ISD::OR &&
1198 isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) {
1201 if (isRunOfOnes(Imm, MB, ME)) {
1202 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1203 N->getOperand(0).getOperand(1),
1204 getI32Imm(0), getI32Imm(MB),getI32Imm(ME) };
1205 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops);
1209 // Other cases are autogenerated.
1213 if (N->getValueType(0) == MVT::i32)
1214 if (SDNode *I = SelectBitfieldInsert(N))
1217 // Other cases are autogenerated.
1220 unsigned Imm, SH, MB, ME;
1221 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
1222 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
1223 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1224 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
1225 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
1228 // Other cases are autogenerated.
1232 unsigned Imm, SH, MB, ME;
1233 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
1234 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
1235 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1236 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
1237 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
1240 // Other cases are autogenerated.
1243 // FIXME: Remove this once the ANDI glue bug is fixed:
1244 case PPCISD::ANDIo_1_EQ_BIT:
1245 case PPCISD::ANDIo_1_GT_BIT: {
1249 EVT InVT = N->getOperand(0).getValueType();
1250 assert((InVT == MVT::i64 || InVT == MVT::i32) &&
1251 "Invalid input type for ANDIo_1_EQ_BIT");
1253 unsigned Opcode = (InVT == MVT::i64) ? PPC::ANDIo8 : PPC::ANDIo;
1254 SDValue AndI(CurDAG->getMachineNode(Opcode, dl, InVT, MVT::Glue,
1256 CurDAG->getTargetConstant(1, InVT)), 0);
1257 SDValue CR0Reg = CurDAG->getRegister(PPC::CR0, MVT::i32);
1259 CurDAG->getTargetConstant(N->getOpcode() == PPCISD::ANDIo_1_EQ_BIT ?
1260 PPC::sub_eq : PPC::sub_gt, MVT::i32);
1262 return CurDAG->SelectNodeTo(N, TargetOpcode::EXTRACT_SUBREG, MVT::i1,
1264 SDValue(AndI.getNode(), 1) /* glue */);
1266 case ISD::SELECT_CC: {
1267 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1268 EVT PtrVT = CurDAG->getTargetLoweringInfo().getPointerTy();
1269 bool isPPC64 = (PtrVT == MVT::i64);
1271 // If this is a select of i1 operands, we'll pattern match it.
1272 if (PPCSubTarget->useCRBits() &&
1273 N->getOperand(0).getValueType() == MVT::i1)
1276 // Handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
1278 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1279 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
1280 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
1281 if (N1C->isNullValue() && N3C->isNullValue() &&
1282 N2C->getZExtValue() == 1ULL && CC == ISD::SETNE &&
1283 // FIXME: Implement this optzn for PPC64.
1284 N->getValueType(0) == MVT::i32) {
1286 CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
1287 N->getOperand(0), getI32Imm(~0U));
1288 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
1289 SDValue(Tmp, 0), N->getOperand(0),
1293 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl);
1295 if (N->getValueType(0) == MVT::i1) {
1296 // An i1 select is: (c & t) | (!c & f).
1298 unsigned Idx = getCRIdxForSetCC(CC, Inv);
1302 default: llvm_unreachable("Invalid CC index");
1303 case 0: SRI = PPC::sub_lt; break;
1304 case 1: SRI = PPC::sub_gt; break;
1305 case 2: SRI = PPC::sub_eq; break;
1306 case 3: SRI = PPC::sub_un; break;
1309 SDValue CCBit = CurDAG->getTargetExtractSubreg(SRI, dl, MVT::i1, CCReg);
1311 SDValue NotCCBit(CurDAG->getMachineNode(PPC::CRNOR, dl, MVT::i1,
1313 SDValue C = Inv ? NotCCBit : CCBit,
1314 NotC = Inv ? CCBit : NotCCBit;
1316 SDValue CAndT(CurDAG->getMachineNode(PPC::CRAND, dl, MVT::i1,
1317 C, N->getOperand(2)), 0);
1318 SDValue NotCAndF(CurDAG->getMachineNode(PPC::CRAND, dl, MVT::i1,
1319 NotC, N->getOperand(3)), 0);
1321 return CurDAG->SelectNodeTo(N, PPC::CROR, MVT::i1, CAndT, NotCAndF);
1324 unsigned BROpc = getPredicateForSetCC(CC);
1326 unsigned SelectCCOp;
1327 if (N->getValueType(0) == MVT::i32)
1328 SelectCCOp = PPC::SELECT_CC_I4;
1329 else if (N->getValueType(0) == MVT::i64)
1330 SelectCCOp = PPC::SELECT_CC_I8;
1331 else if (N->getValueType(0) == MVT::f32)
1332 SelectCCOp = PPC::SELECT_CC_F4;
1333 else if (N->getValueType(0) == MVT::f64)
1334 SelectCCOp = PPC::SELECT_CC_F8;
1336 SelectCCOp = PPC::SELECT_CC_VRRC;
1338 SDValue Ops[] = { CCReg, N->getOperand(2), N->getOperand(3),
1340 return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops);
1343 if (PPCSubTarget->hasVSX()) {
1344 SDValue Ops[] = { N->getOperand(2), N->getOperand(1), N->getOperand(0) };
1345 return CurDAG->SelectNodeTo(N, PPC::XXSEL, N->getValueType(0), Ops);
1349 case ISD::VECTOR_SHUFFLE:
1350 if (PPCSubTarget->hasVSX() && (N->getValueType(0) == MVT::v2f64 ||
1351 N->getValueType(0) == MVT::v2i64)) {
1352 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
1354 SDValue Op1 = N->getOperand(SVN->getMaskElt(0) < 2 ? 0 : 1),
1355 Op2 = N->getOperand(SVN->getMaskElt(1) < 2 ? 0 : 1);
1358 for (int i = 0; i < 2; ++i)
1359 if (SVN->getMaskElt(i) <= 0 || SVN->getMaskElt(i) == 2)
1364 SDValue DMV = CurDAG->getTargetConstant(DM[1] | (DM[0] << 1), MVT::i32);
1366 if (Op1 == Op2 && DM[0] == 0 && DM[1] == 0 &&
1367 Op1.getOpcode() == ISD::SCALAR_TO_VECTOR &&
1368 isa<LoadSDNode>(Op1.getOperand(0))) {
1369 LoadSDNode *LD = cast<LoadSDNode>(Op1.getOperand(0));
1370 SDValue Base, Offset;
1372 if (LD->isUnindexed() &&
1373 SelectAddrIdxOnly(LD->getBasePtr(), Base, Offset)) {
1374 SDValue Chain = LD->getChain();
1375 SDValue Ops[] = { Base, Offset, Chain };
1376 return CurDAG->SelectNodeTo(N, PPC::LXVDSX,
1377 N->getValueType(0), Ops);
1381 SDValue Ops[] = { Op1, Op2, DMV };
1382 return CurDAG->SelectNodeTo(N, PPC::XXPERMDI, N->getValueType(0), Ops);
1388 bool IsPPC64 = PPCSubTarget->isPPC64();
1389 SDValue Ops[] = { N->getOperand(1), N->getOperand(0) };
1390 return CurDAG->SelectNodeTo(N, N->getOpcode() == PPCISD::BDNZ ?
1391 (IsPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
1392 (IsPPC64 ? PPC::BDZ8 : PPC::BDZ),
1395 case PPCISD::COND_BRANCH: {
1396 // Op #0 is the Chain.
1397 // Op #1 is the PPC::PRED_* number.
1399 // Op #3 is the Dest MBB
1400 // Op #4 is the Flag.
1401 // Prevent PPC::PRED_* from being selected into LI.
1403 getI32Imm(cast<ConstantSDNode>(N->getOperand(1))->getZExtValue());
1404 SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3),
1405 N->getOperand(0), N->getOperand(4) };
1406 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops);
1409 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
1410 unsigned PCC = getPredicateForSetCC(CC);
1412 if (N->getOperand(2).getValueType() == MVT::i1) {
1416 default: llvm_unreachable("Unexpected Boolean-operand predicate");
1417 case PPC::PRED_LT: Opc = PPC::CRANDC; Swap = true; break;
1418 case PPC::PRED_LE: Opc = PPC::CRORC; Swap = true; break;
1419 case PPC::PRED_EQ: Opc = PPC::CREQV; Swap = false; break;
1420 case PPC::PRED_GE: Opc = PPC::CRORC; Swap = false; break;
1421 case PPC::PRED_GT: Opc = PPC::CRANDC; Swap = false; break;
1422 case PPC::PRED_NE: Opc = PPC::CRXOR; Swap = false; break;
1425 SDValue BitComp(CurDAG->getMachineNode(Opc, dl, MVT::i1,
1426 N->getOperand(Swap ? 3 : 2),
1427 N->getOperand(Swap ? 2 : 3)), 0);
1428 return CurDAG->SelectNodeTo(N, PPC::BC, MVT::Other,
1429 BitComp, N->getOperand(4), N->getOperand(0));
1432 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl);
1433 SDValue Ops[] = { getI32Imm(PCC), CondCode,
1434 N->getOperand(4), N->getOperand(0) };
1435 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops);
1438 // FIXME: Should custom lower this.
1439 SDValue Chain = N->getOperand(0);
1440 SDValue Target = N->getOperand(1);
1441 unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
1442 unsigned Reg = Target.getValueType() == MVT::i32 ? PPC::BCTR : PPC::BCTR8;
1443 Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, Target,
1445 return CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain);
1447 case PPCISD::TOC_ENTRY: {
1448 assert (PPCSubTarget->isPPC64() && "Only supported for 64-bit ABI");
1450 // For medium and large code model, we generate two instructions as
1451 // described below. Otherwise we allow SelectCodeCommon to handle this,
1452 // selecting one of LDtoc, LDtocJTI, and LDtocCPT.
1453 CodeModel::Model CModel = TM.getCodeModel();
1454 if (CModel != CodeModel::Medium && CModel != CodeModel::Large)
1457 // The first source operand is a TargetGlobalAddress or a
1458 // TargetJumpTable. If it is an externally defined symbol, a symbol
1459 // with common linkage, a function address, or a jump table address,
1460 // or if we are generating code for large code model, we generate:
1461 // LDtocL(<ga:@sym>, ADDIStocHA(%X2, <ga:@sym>))
1462 // Otherwise we generate:
1463 // ADDItocL(ADDIStocHA(%X2, <ga:@sym>), <ga:@sym>)
1464 SDValue GA = N->getOperand(0);
1465 SDValue TOCbase = N->getOperand(1);
1466 SDNode *Tmp = CurDAG->getMachineNode(PPC::ADDIStocHA, dl, MVT::i64,
1469 if (isa<JumpTableSDNode>(GA) || CModel == CodeModel::Large)
1470 return CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA,
1473 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(GA)) {
1474 const GlobalValue *GValue = G->getGlobal();
1475 if (GValue->getType()->getElementType()->isFunctionTy() ||
1476 GValue->isDeclaration() || GValue->hasCommonLinkage() ||
1477 GValue->hasAvailableExternallyLinkage())
1478 return CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA,
1482 return CurDAG->getMachineNode(PPC::ADDItocL, dl, MVT::i64,
1483 SDValue(Tmp, 0), GA);
1485 case PPCISD::VADD_SPLAT: {
1486 // This expands into one of three sequences, depending on whether
1487 // the first operand is odd or even, positive or negative.
1488 assert(isa<ConstantSDNode>(N->getOperand(0)) &&
1489 isa<ConstantSDNode>(N->getOperand(1)) &&
1490 "Invalid operand on VADD_SPLAT!");
1492 int Elt = N->getConstantOperandVal(0);
1493 int EltSize = N->getConstantOperandVal(1);
1494 unsigned Opc1, Opc2, Opc3;
1498 Opc1 = PPC::VSPLTISB;
1499 Opc2 = PPC::VADDUBM;
1500 Opc3 = PPC::VSUBUBM;
1502 } else if (EltSize == 2) {
1503 Opc1 = PPC::VSPLTISH;
1504 Opc2 = PPC::VADDUHM;
1505 Opc3 = PPC::VSUBUHM;
1508 assert(EltSize == 4 && "Invalid element size on VADD_SPLAT!");
1509 Opc1 = PPC::VSPLTISW;
1510 Opc2 = PPC::VADDUWM;
1511 Opc3 = PPC::VSUBUWM;
1515 if ((Elt & 1) == 0) {
1516 // Elt is even, in the range [-32,-18] + [16,30].
1518 // Convert: VADD_SPLAT elt, size
1519 // Into: tmp = VSPLTIS[BHW] elt
1520 // VADDU[BHW]M tmp, tmp
1521 // Where: [BHW] = B for size = 1, H for size = 2, W for size = 4
1522 SDValue EltVal = getI32Imm(Elt >> 1);
1523 SDNode *Tmp = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
1524 SDValue TmpVal = SDValue(Tmp, 0);
1525 return CurDAG->getMachineNode(Opc2, dl, VT, TmpVal, TmpVal);
1527 } else if (Elt > 0) {
1528 // Elt is odd and positive, in the range [17,31].
1530 // Convert: VADD_SPLAT elt, size
1531 // Into: tmp1 = VSPLTIS[BHW] elt-16
1532 // tmp2 = VSPLTIS[BHW] -16
1533 // VSUBU[BHW]M tmp1, tmp2
1534 SDValue EltVal = getI32Imm(Elt - 16);
1535 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
1536 EltVal = getI32Imm(-16);
1537 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
1538 return CurDAG->getMachineNode(Opc3, dl, VT, SDValue(Tmp1, 0),
1542 // Elt is odd and negative, in the range [-31,-17].
1544 // Convert: VADD_SPLAT elt, size
1545 // Into: tmp1 = VSPLTIS[BHW] elt+16
1546 // tmp2 = VSPLTIS[BHW] -16
1547 // VADDU[BHW]M tmp1, tmp2
1548 SDValue EltVal = getI32Imm(Elt + 16);
1549 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
1550 EltVal = getI32Imm(-16);
1551 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
1552 return CurDAG->getMachineNode(Opc2, dl, VT, SDValue(Tmp1, 0),
1558 return SelectCode(N);
1561 /// PostprocessISelDAG - Perform some late peephole optimizations
1562 /// on the DAG representation.
1563 void PPCDAGToDAGISel::PostprocessISelDAG() {
1565 // Skip peepholes at -O0.
1566 if (TM.getOptLevel() == CodeGenOpt::None)
1573 // Check if all users of this node will become isel where the second operand
1574 // is the constant zero. If this is so, and if we can negate the condition,
1575 // then we can flip the true and false operands. This will allow the zero to
1576 // be folded with the isel so that we don't need to materialize a register
1578 bool PPCDAGToDAGISel::AllUsersSelectZero(SDNode *N) {
1579 // If we're not using isel, then this does not matter.
1580 if (!PPCSubTarget->hasISEL())
1583 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
1586 if (!User->isMachineOpcode())
1588 if (User->getMachineOpcode() != PPC::SELECT_I4 &&
1589 User->getMachineOpcode() != PPC::SELECT_I8)
1592 SDNode *Op2 = User->getOperand(2).getNode();
1593 if (!Op2->isMachineOpcode())
1596 if (Op2->getMachineOpcode() != PPC::LI &&
1597 Op2->getMachineOpcode() != PPC::LI8)
1600 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op2->getOperand(0));
1604 if (!C->isNullValue())
1611 void PPCDAGToDAGISel::SwapAllSelectUsers(SDNode *N) {
1612 SmallVector<SDNode *, 4> ToReplace;
1613 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
1616 assert((User->getMachineOpcode() == PPC::SELECT_I4 ||
1617 User->getMachineOpcode() == PPC::SELECT_I8) &&
1618 "Must have all select users");
1619 ToReplace.push_back(User);
1622 for (SmallVector<SDNode *, 4>::iterator UI = ToReplace.begin(),
1623 UE = ToReplace.end(); UI != UE; ++UI) {
1626 CurDAG->getMachineNode(User->getMachineOpcode(), SDLoc(User),
1627 User->getValueType(0), User->getOperand(0),
1628 User->getOperand(2),
1629 User->getOperand(1));
1631 DEBUG(dbgs() << "CR Peephole replacing:\nOld: ");
1632 DEBUG(User->dump(CurDAG));
1633 DEBUG(dbgs() << "\nNew: ");
1634 DEBUG(ResNode->dump(CurDAG));
1635 DEBUG(dbgs() << "\n");
1637 ReplaceUses(User, ResNode);
1641 void PPCDAGToDAGISel::PeepholeCROps() {
1645 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
1646 E = CurDAG->allnodes_end(); I != E; ++I) {
1647 MachineSDNode *MachineNode = dyn_cast<MachineSDNode>(I);
1648 if (!MachineNode || MachineNode->use_empty())
1650 SDNode *ResNode = MachineNode;
1652 bool Op1Set = false, Op1Unset = false,
1654 Op2Set = false, Op2Unset = false,
1657 unsigned Opcode = MachineNode->getMachineOpcode();
1668 SDValue Op = MachineNode->getOperand(1);
1669 if (Op.isMachineOpcode()) {
1670 if (Op.getMachineOpcode() == PPC::CRSET)
1672 else if (Op.getMachineOpcode() == PPC::CRUNSET)
1674 else if (Op.getMachineOpcode() == PPC::CRNOR &&
1675 Op.getOperand(0) == Op.getOperand(1))
1681 case PPC::SELECT_I4:
1682 case PPC::SELECT_I8:
1683 case PPC::SELECT_F4:
1684 case PPC::SELECT_F8:
1685 case PPC::SELECT_VRRC: {
1686 SDValue Op = MachineNode->getOperand(0);
1687 if (Op.isMachineOpcode()) {
1688 if (Op.getMachineOpcode() == PPC::CRSET)
1690 else if (Op.getMachineOpcode() == PPC::CRUNSET)
1692 else if (Op.getMachineOpcode() == PPC::CRNOR &&
1693 Op.getOperand(0) == Op.getOperand(1))
1700 bool SelectSwap = false;
1704 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
1706 ResNode = MachineNode->getOperand(0).getNode();
1709 ResNode = MachineNode->getOperand(1).getNode();
1712 ResNode = MachineNode->getOperand(0).getNode();
1713 else if (Op1Unset || Op2Unset)
1714 // x & 0 = 0 & y = 0
1715 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
1718 // ~x & y = andc(y, x)
1719 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
1720 MVT::i1, MachineNode->getOperand(1),
1721 MachineNode->getOperand(0).
1724 // x & ~y = andc(x, y)
1725 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
1726 MVT::i1, MachineNode->getOperand(0),
1727 MachineNode->getOperand(1).
1729 else if (AllUsersSelectZero(MachineNode))
1730 ResNode = CurDAG->getMachineNode(PPC::CRNAND, SDLoc(MachineNode),
1731 MVT::i1, MachineNode->getOperand(0),
1732 MachineNode->getOperand(1)),
1736 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
1737 // nand(x, x) -> nor(x, x)
1738 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1739 MVT::i1, MachineNode->getOperand(0),
1740 MachineNode->getOperand(0));
1742 // nand(1, y) -> nor(y, y)
1743 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1744 MVT::i1, MachineNode->getOperand(1),
1745 MachineNode->getOperand(1));
1747 // nand(x, 1) -> nor(x, x)
1748 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1749 MVT::i1, MachineNode->getOperand(0),
1750 MachineNode->getOperand(0));
1751 else if (Op1Unset || Op2Unset)
1752 // nand(x, 0) = nand(0, y) = 1
1753 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
1756 // nand(~x, y) = ~(~x & y) = x | ~y = orc(x, y)
1757 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
1758 MVT::i1, MachineNode->getOperand(0).
1760 MachineNode->getOperand(1));
1762 // nand(x, ~y) = ~x | y = orc(y, x)
1763 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
1764 MVT::i1, MachineNode->getOperand(1).
1766 MachineNode->getOperand(0));
1767 else if (AllUsersSelectZero(MachineNode))
1768 ResNode = CurDAG->getMachineNode(PPC::CRAND, SDLoc(MachineNode),
1769 MVT::i1, MachineNode->getOperand(0),
1770 MachineNode->getOperand(1)),
1774 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
1776 ResNode = MachineNode->getOperand(0).getNode();
1777 else if (Op1Set || Op2Set)
1778 // x | 1 = 1 | y = 1
1779 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
1783 ResNode = MachineNode->getOperand(1).getNode();
1786 ResNode = MachineNode->getOperand(0).getNode();
1788 // ~x | y = orc(y, x)
1789 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
1790 MVT::i1, MachineNode->getOperand(1),
1791 MachineNode->getOperand(0).
1794 // x | ~y = orc(x, y)
1795 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
1796 MVT::i1, MachineNode->getOperand(0),
1797 MachineNode->getOperand(1).
1799 else if (AllUsersSelectZero(MachineNode))
1800 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1801 MVT::i1, MachineNode->getOperand(0),
1802 MachineNode->getOperand(1)),
1806 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
1808 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
1811 // xor(1, y) -> nor(y, y)
1812 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1813 MVT::i1, MachineNode->getOperand(1),
1814 MachineNode->getOperand(1));
1816 // xor(x, 1) -> nor(x, x)
1817 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1818 MVT::i1, MachineNode->getOperand(0),
1819 MachineNode->getOperand(0));
1822 ResNode = MachineNode->getOperand(1).getNode();
1825 ResNode = MachineNode->getOperand(0).getNode();
1827 // xor(~x, y) = eqv(x, y)
1828 ResNode = CurDAG->getMachineNode(PPC::CREQV, SDLoc(MachineNode),
1829 MVT::i1, MachineNode->getOperand(0).
1831 MachineNode->getOperand(1));
1833 // xor(x, ~y) = eqv(x, y)
1834 ResNode = CurDAG->getMachineNode(PPC::CREQV, SDLoc(MachineNode),
1835 MVT::i1, MachineNode->getOperand(0),
1836 MachineNode->getOperand(1).
1838 else if (AllUsersSelectZero(MachineNode))
1839 ResNode = CurDAG->getMachineNode(PPC::CREQV, SDLoc(MachineNode),
1840 MVT::i1, MachineNode->getOperand(0),
1841 MachineNode->getOperand(1)),
1845 if (Op1Set || Op2Set)
1847 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
1850 // nor(0, y) = ~y -> nor(y, y)
1851 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1852 MVT::i1, MachineNode->getOperand(1),
1853 MachineNode->getOperand(1));
1856 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1857 MVT::i1, MachineNode->getOperand(0),
1858 MachineNode->getOperand(0));
1860 // nor(~x, y) = andc(x, y)
1861 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
1862 MVT::i1, MachineNode->getOperand(0).
1864 MachineNode->getOperand(1));
1866 // nor(x, ~y) = andc(y, x)
1867 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
1868 MVT::i1, MachineNode->getOperand(1).
1870 MachineNode->getOperand(0));
1871 else if (AllUsersSelectZero(MachineNode))
1872 ResNode = CurDAG->getMachineNode(PPC::CROR, SDLoc(MachineNode),
1873 MVT::i1, MachineNode->getOperand(0),
1874 MachineNode->getOperand(1)),
1878 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
1880 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
1884 ResNode = MachineNode->getOperand(1).getNode();
1887 ResNode = MachineNode->getOperand(0).getNode();
1889 // eqv(0, y) = ~y -> nor(y, y)
1890 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1891 MVT::i1, MachineNode->getOperand(1),
1892 MachineNode->getOperand(1));
1895 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1896 MVT::i1, MachineNode->getOperand(0),
1897 MachineNode->getOperand(0));
1899 // eqv(~x, y) = xor(x, y)
1900 ResNode = CurDAG->getMachineNode(PPC::CRXOR, SDLoc(MachineNode),
1901 MVT::i1, MachineNode->getOperand(0).
1903 MachineNode->getOperand(1));
1905 // eqv(x, ~y) = xor(x, y)
1906 ResNode = CurDAG->getMachineNode(PPC::CRXOR, SDLoc(MachineNode),
1907 MVT::i1, MachineNode->getOperand(0),
1908 MachineNode->getOperand(1).
1910 else if (AllUsersSelectZero(MachineNode))
1911 ResNode = CurDAG->getMachineNode(PPC::CRXOR, SDLoc(MachineNode),
1912 MVT::i1, MachineNode->getOperand(0),
1913 MachineNode->getOperand(1)),
1917 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
1919 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
1923 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1924 MVT::i1, MachineNode->getOperand(1),
1925 MachineNode->getOperand(1));
1926 else if (Op1Unset || Op2Set)
1927 // andc(0, y) = andc(x, 1) = 0
1928 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
1932 ResNode = MachineNode->getOperand(0).getNode();
1934 // andc(~x, y) = ~(x | y) = nor(x, y)
1935 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1936 MVT::i1, MachineNode->getOperand(0).
1938 MachineNode->getOperand(1));
1940 // andc(x, ~y) = x & y
1941 ResNode = CurDAG->getMachineNode(PPC::CRAND, SDLoc(MachineNode),
1942 MVT::i1, MachineNode->getOperand(0),
1943 MachineNode->getOperand(1).
1945 else if (AllUsersSelectZero(MachineNode))
1946 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
1947 MVT::i1, MachineNode->getOperand(1),
1948 MachineNode->getOperand(0)),
1952 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
1954 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
1956 else if (Op1Set || Op2Unset)
1957 // orc(1, y) = orc(x, 0) = 1
1958 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
1962 ResNode = MachineNode->getOperand(0).getNode();
1965 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1966 MVT::i1, MachineNode->getOperand(1),
1967 MachineNode->getOperand(1));
1969 // orc(~x, y) = ~(x & y) = nand(x, y)
1970 ResNode = CurDAG->getMachineNode(PPC::CRNAND, SDLoc(MachineNode),
1971 MVT::i1, MachineNode->getOperand(0).
1973 MachineNode->getOperand(1));
1975 // orc(x, ~y) = x | y
1976 ResNode = CurDAG->getMachineNode(PPC::CROR, SDLoc(MachineNode),
1977 MVT::i1, MachineNode->getOperand(0),
1978 MachineNode->getOperand(1).
1980 else if (AllUsersSelectZero(MachineNode))
1981 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
1982 MVT::i1, MachineNode->getOperand(1),
1983 MachineNode->getOperand(0)),
1986 case PPC::SELECT_I4:
1987 case PPC::SELECT_I8:
1988 case PPC::SELECT_F4:
1989 case PPC::SELECT_F8:
1990 case PPC::SELECT_VRRC:
1992 ResNode = MachineNode->getOperand(1).getNode();
1994 ResNode = MachineNode->getOperand(2).getNode();
1996 ResNode = CurDAG->getMachineNode(MachineNode->getMachineOpcode(),
1998 MachineNode->getValueType(0),
1999 MachineNode->getOperand(0).
2001 MachineNode->getOperand(2),
2002 MachineNode->getOperand(1));
2007 ResNode = CurDAG->getMachineNode(Opcode == PPC::BC ? PPC::BCn :
2011 MachineNode->getOperand(0).
2013 MachineNode->getOperand(1),
2014 MachineNode->getOperand(2));
2015 // FIXME: Handle Op1Set, Op1Unset here too.
2019 // If we're inverting this node because it is used only by selects that
2020 // we'd like to swap, then swap the selects before the node replacement.
2022 SwapAllSelectUsers(MachineNode);
2024 if (ResNode != MachineNode) {
2025 DEBUG(dbgs() << "CR Peephole replacing:\nOld: ");
2026 DEBUG(MachineNode->dump(CurDAG));
2027 DEBUG(dbgs() << "\nNew: ");
2028 DEBUG(ResNode->dump(CurDAG));
2029 DEBUG(dbgs() << "\n");
2031 ReplaceUses(MachineNode, ResNode);
2036 CurDAG->RemoveDeadNodes();
2037 } while (IsModified);
2040 void PPCDAGToDAGISel::PeepholePPC64() {
2041 // These optimizations are currently supported only for 64-bit SVR4.
2042 if (PPCSubTarget->isDarwin() || !PPCSubTarget->isPPC64())
2045 SelectionDAG::allnodes_iterator Position(CurDAG->getRoot().getNode());
2048 while (Position != CurDAG->allnodes_begin()) {
2049 SDNode *N = --Position;
2050 // Skip dead nodes and any non-machine opcodes.
2051 if (N->use_empty() || !N->isMachineOpcode())
2055 unsigned StorageOpcode = N->getMachineOpcode();
2057 switch (StorageOpcode) {
2088 // If this is a load or store with a zero offset, we may be able to
2089 // fold an add-immediate into the memory operation.
2090 if (!isa<ConstantSDNode>(N->getOperand(FirstOp)) ||
2091 N->getConstantOperandVal(FirstOp) != 0)
2094 SDValue Base = N->getOperand(FirstOp + 1);
2095 if (!Base.isMachineOpcode())
2099 bool ReplaceFlags = true;
2101 // When the feeding operation is an add-immediate of some sort,
2102 // determine whether we need to add relocation information to the
2103 // target flags on the immediate operand when we fold it into the
2104 // load instruction.
2106 // For something like ADDItocL, the relocation information is
2107 // inferred from the opcode; when we process it in the AsmPrinter,
2108 // we add the necessary relocation there. A load, though, can receive
2109 // relocation from various flavors of ADDIxxx, so we need to carry
2110 // the relocation information in the target flags.
2111 switch (Base.getMachineOpcode()) {
2116 // In some cases (such as TLS) the relocation information
2117 // is already in place on the operand, so copying the operand
2119 ReplaceFlags = false;
2120 // For these cases, the immediate may not be divisible by 4, in
2121 // which case the fold is illegal for DS-form instructions. (The
2122 // other cases provide aligned addresses and are always safe.)
2123 if ((StorageOpcode == PPC::LWA ||
2124 StorageOpcode == PPC::LD ||
2125 StorageOpcode == PPC::STD) &&
2126 (!isa<ConstantSDNode>(Base.getOperand(1)) ||
2127 Base.getConstantOperandVal(1) % 4 != 0))
2130 case PPC::ADDIdtprelL:
2131 Flags = PPCII::MO_DTPREL_LO;
2133 case PPC::ADDItlsldL:
2134 Flags = PPCII::MO_TLSLD_LO;
2137 Flags = PPCII::MO_TOC_LO;
2141 // We found an opportunity. Reverse the operands from the add
2142 // immediate and substitute them into the load or store. If
2143 // needed, update the target flags for the immediate operand to
2144 // reflect the necessary relocation information.
2145 DEBUG(dbgs() << "Folding add-immediate into mem-op:\nBase: ");
2146 DEBUG(Base->dump(CurDAG));
2147 DEBUG(dbgs() << "\nN: ");
2148 DEBUG(N->dump(CurDAG));
2149 DEBUG(dbgs() << "\n");
2151 SDValue ImmOpnd = Base.getOperand(1);
2153 // If the relocation information isn't already present on the
2154 // immediate operand, add it now.
2156 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(ImmOpnd)) {
2158 const GlobalValue *GV = GA->getGlobal();
2159 // We can't perform this optimization for data whose alignment
2160 // is insufficient for the instruction encoding.
2161 if (GV->getAlignment() < 4 &&
2162 (StorageOpcode == PPC::LD || StorageOpcode == PPC::STD ||
2163 StorageOpcode == PPC::LWA)) {
2164 DEBUG(dbgs() << "Rejected this candidate for alignment.\n\n");
2167 ImmOpnd = CurDAG->getTargetGlobalAddress(GV, dl, MVT::i64, 0, Flags);
2168 } else if (ConstantPoolSDNode *CP =
2169 dyn_cast<ConstantPoolSDNode>(ImmOpnd)) {
2170 const Constant *C = CP->getConstVal();
2171 ImmOpnd = CurDAG->getTargetConstantPool(C, MVT::i64,
2177 if (FirstOp == 1) // Store
2178 (void)CurDAG->UpdateNodeOperands(N, N->getOperand(0), ImmOpnd,
2179 Base.getOperand(0), N->getOperand(3));
2181 (void)CurDAG->UpdateNodeOperands(N, ImmOpnd, Base.getOperand(0),
2184 // The add-immediate may now be dead, in which case remove it.
2185 if (Base.getNode()->use_empty())
2186 CurDAG->RemoveDeadNode(Base.getNode());
2191 /// createPPCISelDag - This pass converts a legalized DAG into a
2192 /// PowerPC-specific DAG, ready for instruction scheduling.
2194 FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) {
2195 return new PPCDAGToDAGISel(TM);
2198 static void initializePassOnce(PassRegistry &Registry) {
2199 const char *Name = "PowerPC DAG->DAG Pattern Instruction Selection";
2200 PassInfo *PI = new PassInfo(Name, "ppc-codegen", &SelectionDAGISel::ID,
2201 nullptr, false, false);
2202 Registry.registerPass(*PI, true);
2205 void llvm::initializePPCDAGToDAGISelPass(PassRegistry &Registry) {
2206 CALL_ONCE_INITIALIZATION(initializePassOnce);