1 //===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for PowerPC,
11 // converting from a legalized dag to a PPC dag.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "ppc-codegen"
17 #include "MCTargetDesc/PPCPredicates.h"
18 #include "PPCTargetMachine.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/Constants.h"
25 #include "llvm/Function.h"
26 #include "llvm/GlobalValue.h"
27 #include "llvm/GlobalVariable.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/Target/TargetOptions.h"
37 //===--------------------------------------------------------------------===//
38 /// PPCDAGToDAGISel - PPC specific code to select PPC machine
39 /// instructions for SelectionDAG operations.
41 class PPCDAGToDAGISel : public SelectionDAGISel {
42 const PPCTargetMachine &TM;
43 const PPCTargetLowering &PPCLowering;
44 const PPCSubtarget &PPCSubTarget;
45 unsigned GlobalBaseReg;
47 explicit PPCDAGToDAGISel(PPCTargetMachine &tm)
48 : SelectionDAGISel(tm), TM(tm),
49 PPCLowering(*TM.getTargetLowering()),
50 PPCSubTarget(*TM.getSubtargetImpl()) {}
52 virtual bool runOnMachineFunction(MachineFunction &MF) {
53 // Make sure we re-emit a set of the global base reg if necessary
55 SelectionDAGISel::runOnMachineFunction(MF);
57 if (!PPCSubTarget.isSVR4ABI())
63 /// getI32Imm - Return a target constant with the specified value, of type
65 inline SDValue getI32Imm(unsigned Imm) {
66 return CurDAG->getTargetConstant(Imm, MVT::i32);
69 /// getI64Imm - Return a target constant with the specified value, of type
71 inline SDValue getI64Imm(uint64_t Imm) {
72 return CurDAG->getTargetConstant(Imm, MVT::i64);
75 /// getSmallIPtrImm - Return a target constant of pointer type.
76 inline SDValue getSmallIPtrImm(unsigned Imm) {
77 return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy());
80 /// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s
81 /// with any number of 0s on either side. The 1s are allowed to wrap from
82 /// LSB to MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs.
83 /// 0x0F0F0000 is not, since all 1s are not contiguous.
84 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME);
87 /// isRotateAndMask - Returns true if Mask and Shift can be folded into a
88 /// rotate and mask opcode and mask operation.
89 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool isShiftMask,
90 unsigned &SH, unsigned &MB, unsigned &ME);
92 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
93 /// base register. Return the virtual register that holds this value.
94 SDNode *getGlobalBaseReg();
96 // Select - Convert the specified operand from a target-independent to a
97 // target-specific node if it hasn't already been changed.
98 SDNode *Select(SDNode *N);
100 SDNode *SelectBitfieldInsert(SDNode *N);
102 /// SelectCC - Select a comparison of the specified values with the
103 /// specified condition code, returning the CR# of the expression.
104 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, DebugLoc dl);
106 /// SelectAddrImm - Returns true if the address N can be represented by
107 /// a base register plus a signed 16-bit displacement [r+imm].
108 bool SelectAddrImm(SDValue N, SDValue &Disp,
110 return PPCLowering.SelectAddressRegImm(N, Disp, Base, *CurDAG);
113 /// SelectAddrImmOffs - Return true if the operand is valid for a preinc
114 /// immediate field. Because preinc imms have already been validated, just
116 bool SelectAddrImmOffs(SDValue N, SDValue &Out) const {
117 if (isa<ConstantSDNode>(N) || N.getOpcode() == PPCISD::Lo ||
118 N.getOpcode() == ISD::TargetGlobalAddress) {
126 /// SelectAddrIdxOffs - Return true if the operand is valid for a preinc
127 /// index field. Because preinc imms have already been validated, just
129 bool SelectAddrIdxOffs(SDValue N, SDValue &Out) const {
130 if (isa<ConstantSDNode>(N) || N.getOpcode() == PPCISD::Lo ||
131 N.getOpcode() == ISD::TargetGlobalAddress)
138 /// SelectAddrIdx - Given the specified addressed, check to see if it can be
139 /// represented as an indexed [r+r] operation. Returns false if it can
140 /// be represented by [r+imm], which are preferred.
141 bool SelectAddrIdx(SDValue N, SDValue &Base, SDValue &Index) {
142 return PPCLowering.SelectAddressRegReg(N, Base, Index, *CurDAG);
145 /// SelectAddrIdxOnly - Given the specified addressed, force it to be
146 /// represented as an indexed [r+r] operation.
147 bool SelectAddrIdxOnly(SDValue N, SDValue &Base, SDValue &Index) {
148 return PPCLowering.SelectAddressRegRegOnly(N, Base, Index, *CurDAG);
151 /// SelectAddrImmShift - Returns true if the address N can be represented by
152 /// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable
153 /// for use by STD and friends.
154 bool SelectAddrImmShift(SDValue N, SDValue &Disp, SDValue &Base) {
155 return PPCLowering.SelectAddressRegImmShift(N, Disp, Base, *CurDAG);
158 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
159 /// inline asm expressions. It is always correct to compute the value into
160 /// a register. The case of adding a (possibly relocatable) constant to a
161 /// register can be improved, but it is wrong to substitute Reg+Reg for
162 /// Reg in an asm, because the load or store opcode would have to change.
163 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
165 std::vector<SDValue> &OutOps) {
166 OutOps.push_back(Op);
170 void InsertVRSaveCode(MachineFunction &MF);
172 virtual const char *getPassName() const {
173 return "PowerPC DAG->DAG Pattern Instruction Selection";
176 // Include the pieces autogenerated from the target description.
177 #include "PPCGenDAGISel.inc"
180 SDNode *SelectSETCC(SDNode *N);
184 /// InsertVRSaveCode - Once the entire function has been instruction selected,
185 /// all virtual registers are created and all machine instructions are built,
186 /// check to see if we need to save/restore VRSAVE. If so, do it.
187 void PPCDAGToDAGISel::InsertVRSaveCode(MachineFunction &Fn) {
188 // Check to see if this function uses vector registers, which means we have to
189 // save and restore the VRSAVE register and update it with the regs we use.
191 // In this case, there will be virtual registers of vector type created
192 // by the scheduler. Detect them now.
193 bool HasVectorVReg = false;
194 for (unsigned i = 0, e = RegInfo->getNumVirtRegs(); i != e; ++i) {
195 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
196 if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) {
197 HasVectorVReg = true;
201 if (!HasVectorVReg) return; // nothing to do.
203 // If we have a vector register, we want to emit code into the entry and exit
204 // blocks to save and restore the VRSAVE register. We do this here (instead
205 // of marking all vector instructions as clobbering VRSAVE) for two reasons:
207 // 1. This (trivially) reduces the load on the register allocator, by not
208 // having to represent the live range of the VRSAVE register.
209 // 2. This (more significantly) allows us to create a temporary virtual
210 // register to hold the saved VRSAVE value, allowing this temporary to be
211 // register allocated, instead of forcing it to be spilled to the stack.
213 // Create two vregs - one to hold the VRSAVE register that is live-in to the
214 // function and one for the value after having bits or'd into it.
215 unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
216 unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
218 const TargetInstrInfo &TII = *TM.getInstrInfo();
219 MachineBasicBlock &EntryBB = *Fn.begin();
221 // Emit the following code into the entry block:
222 // InVRSAVE = MFVRSAVE
223 // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
224 // MTVRSAVE UpdatedVRSAVE
225 MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
226 BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE);
227 BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE),
228 UpdatedVRSAVE).addReg(InVRSAVE);
229 BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
231 // Find all return blocks, outputting a restore in each epilog.
232 for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
233 if (!BB->empty() && BB->back().isReturn()) {
234 IP = BB->end(); --IP;
236 // Skip over all terminator instructions, which are part of the return
238 MachineBasicBlock::iterator I2 = IP;
239 while (I2 != BB->begin() && (--I2)->isTerminator())
242 // Emit: MTVRSAVE InVRSave
243 BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
249 /// getGlobalBaseReg - Output the instructions required to put the
250 /// base address to use for accessing globals into a register.
252 SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
253 if (!GlobalBaseReg) {
254 const TargetInstrInfo &TII = *TM.getInstrInfo();
255 // Insert the set of GlobalBaseReg into the first MBB of the function
256 MachineBasicBlock &FirstMBB = MF->front();
257 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
260 if (PPCLowering.getPointerTy() == MVT::i32) {
261 GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
262 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));
263 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
265 GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::G8RCRegClass);
266 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8));
267 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg);
270 return CurDAG->getRegister(GlobalBaseReg,
271 PPCLowering.getPointerTy()).getNode();
274 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
275 /// or 64-bit immediate, and if the value can be accurately represented as a
276 /// sign extension from a 16-bit value. If so, this returns true and the
278 static bool isIntS16Immediate(SDNode *N, short &Imm) {
279 if (N->getOpcode() != ISD::Constant)
282 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
283 if (N->getValueType(0) == MVT::i32)
284 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
286 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
289 static bool isIntS16Immediate(SDValue Op, short &Imm) {
290 return isIntS16Immediate(Op.getNode(), Imm);
294 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
295 /// operand. If so Imm will receive the 32-bit value.
296 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
297 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
298 Imm = cast<ConstantSDNode>(N)->getZExtValue();
304 /// isInt64Immediate - This method tests to see if the node is a 64-bit constant
305 /// operand. If so Imm will receive the 64-bit value.
306 static bool isInt64Immediate(SDNode *N, uint64_t &Imm) {
307 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
308 Imm = cast<ConstantSDNode>(N)->getZExtValue();
314 // isInt32Immediate - This method tests to see if a constant operand.
315 // If so Imm will receive the 32 bit value.
316 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
317 return isInt32Immediate(N.getNode(), Imm);
321 // isOpcWithIntImmediate - This method tests to see if the node is a specific
322 // opcode and that it has a immediate integer right operand.
323 // If so Imm will receive the 32 bit value.
324 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
325 return N->getOpcode() == Opc
326 && isInt32Immediate(N->getOperand(1).getNode(), Imm);
329 bool PPCDAGToDAGISel::isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
330 if (isShiftedMask_32(Val)) {
331 // look for the first non-zero bit
332 MB = CountLeadingZeros_32(Val);
333 // look for the first zero bit after the run of ones
334 ME = CountLeadingZeros_32((Val - 1) ^ Val);
337 Val = ~Val; // invert mask
338 if (isShiftedMask_32(Val)) {
339 // effectively look for the first zero bit
340 ME = CountLeadingZeros_32(Val) - 1;
341 // effectively look for the first one bit after the run of zeros
342 MB = CountLeadingZeros_32((Val - 1) ^ Val) + 1;
350 bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask,
351 bool isShiftMask, unsigned &SH,
352 unsigned &MB, unsigned &ME) {
353 // Don't even go down this path for i64, since different logic will be
354 // necessary for rldicl/rldicr/rldimi.
355 if (N->getValueType(0) != MVT::i32)
359 unsigned Indeterminant = ~0; // bit mask marking indeterminant results
360 unsigned Opcode = N->getOpcode();
361 if (N->getNumOperands() != 2 ||
362 !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31))
365 if (Opcode == ISD::SHL) {
366 // apply shift left to mask if it comes first
367 if (isShiftMask) Mask = Mask << Shift;
368 // determine which bits are made indeterminant by shift
369 Indeterminant = ~(0xFFFFFFFFu << Shift);
370 } else if (Opcode == ISD::SRL) {
371 // apply shift right to mask if it comes first
372 if (isShiftMask) Mask = Mask >> Shift;
373 // determine which bits are made indeterminant by shift
374 Indeterminant = ~(0xFFFFFFFFu >> Shift);
375 // adjust for the left rotate
377 } else if (Opcode == ISD::ROTL) {
383 // if the mask doesn't intersect any Indeterminant bits
384 if (Mask && !(Mask & Indeterminant)) {
386 // make sure the mask is still a mask (wrap arounds may not be)
387 return isRunOfOnes(Mask, MB, ME);
392 /// SelectBitfieldInsert - turn an or of two masked values into
393 /// the rotate left word immediate then mask insert (rlwimi) instruction.
394 SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
395 SDValue Op0 = N->getOperand(0);
396 SDValue Op1 = N->getOperand(1);
397 DebugLoc dl = N->getDebugLoc();
399 APInt LKZ, LKO, RKZ, RKO;
400 CurDAG->ComputeMaskedBits(Op0, LKZ, LKO);
401 CurDAG->ComputeMaskedBits(Op1, RKZ, RKO);
403 unsigned TargetMask = LKZ.getZExtValue();
404 unsigned InsertMask = RKZ.getZExtValue();
406 if ((TargetMask | InsertMask) == 0xFFFFFFFF) {
407 unsigned Op0Opc = Op0.getOpcode();
408 unsigned Op1Opc = Op1.getOpcode();
409 unsigned Value, SH = 0;
410 TargetMask = ~TargetMask;
411 InsertMask = ~InsertMask;
413 // If the LHS has a foldable shift and the RHS does not, then swap it to the
414 // RHS so that we can fold the shift into the insert.
415 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
416 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
417 Op0.getOperand(0).getOpcode() == ISD::SRL) {
418 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
419 Op1.getOperand(0).getOpcode() != ISD::SRL) {
421 std::swap(Op0Opc, Op1Opc);
422 std::swap(TargetMask, InsertMask);
425 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
426 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
427 Op1.getOperand(0).getOpcode() != ISD::SRL) {
429 std::swap(Op0Opc, Op1Opc);
430 std::swap(TargetMask, InsertMask);
435 if (InsertMask && isRunOfOnes(InsertMask, MB, ME)) {
438 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
439 isInt32Immediate(Op1.getOperand(1), Value)) {
440 Op1 = Op1.getOperand(0);
441 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value;
443 if (Op1Opc == ISD::AND) {
444 unsigned SHOpc = Op1.getOperand(0).getOpcode();
445 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) &&
446 isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) {
447 Op1 = Op1.getOperand(0).getOperand(0);
448 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value;
450 Op1 = Op1.getOperand(0);
455 SDValue Ops[] = { Op0, Op1, getI32Imm(SH), getI32Imm(MB),
457 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5);
463 /// SelectCC - Select a comparison of the specified values with the specified
464 /// condition code, returning the CR# of the expression.
465 SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS,
466 ISD::CondCode CC, DebugLoc dl) {
467 // Always select the LHS.
470 if (LHS.getValueType() == MVT::i32) {
472 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
473 if (isInt32Immediate(RHS, Imm)) {
474 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
476 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
477 getI32Imm(Imm & 0xFFFF)), 0);
478 // If this is a 16-bit signed immediate, fold it.
479 if (isInt<16>((int)Imm))
480 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
481 getI32Imm(Imm & 0xFFFF)), 0);
483 // For non-equality comparisons, the default code would materialize the
484 // constant, then compare against it, like this:
488 // Since we are just comparing for equality, we can emit this instead:
489 // xoris r0,r3,0x1234
490 // cmplwi cr0,r0,0x5678
492 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS, dl, MVT::i32, LHS,
493 getI32Imm(Imm >> 16)), 0);
494 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, Xor,
495 getI32Imm(Imm & 0xFFFF)), 0);
498 } else if (ISD::isUnsignedIntSetCC(CC)) {
499 if (isInt32Immediate(RHS, Imm) && isUInt<16>(Imm))
500 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
501 getI32Imm(Imm & 0xFFFF)), 0);
505 if (isIntS16Immediate(RHS, SImm))
506 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
507 getI32Imm((int)SImm & 0xFFFF)),
511 } else if (LHS.getValueType() == MVT::i64) {
513 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
514 if (isInt64Immediate(RHS.getNode(), Imm)) {
515 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
517 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
518 getI32Imm(Imm & 0xFFFF)), 0);
519 // If this is a 16-bit signed immediate, fold it.
521 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
522 getI32Imm(Imm & 0xFFFF)), 0);
524 // For non-equality comparisons, the default code would materialize the
525 // constant, then compare against it, like this:
529 // Since we are just comparing for equality, we can emit this instead:
530 // xoris r0,r3,0x1234
531 // cmpldi cr0,r0,0x5678
533 if (isUInt<32>(Imm)) {
534 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS8, dl, MVT::i64, LHS,
535 getI64Imm(Imm >> 16)), 0);
536 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, Xor,
537 getI64Imm(Imm & 0xFFFF)), 0);
541 } else if (ISD::isUnsignedIntSetCC(CC)) {
542 if (isInt64Immediate(RHS.getNode(), Imm) && isUInt<16>(Imm))
543 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
544 getI64Imm(Imm & 0xFFFF)), 0);
548 if (isIntS16Immediate(RHS, SImm))
549 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
550 getI64Imm(SImm & 0xFFFF)),
554 } else if (LHS.getValueType() == MVT::f32) {
557 assert(LHS.getValueType() == MVT::f64 && "Unknown vt!");
560 return SDValue(CurDAG->getMachineNode(Opc, dl, MVT::i32, LHS, RHS), 0);
563 static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {
569 llvm_unreachable("Should be lowered by legalize!");
570 default: llvm_unreachable("Unknown condition!");
572 case ISD::SETEQ: return PPC::PRED_EQ;
574 case ISD::SETNE: return PPC::PRED_NE;
576 case ISD::SETLT: return PPC::PRED_LT;
578 case ISD::SETLE: return PPC::PRED_LE;
580 case ISD::SETGT: return PPC::PRED_GT;
582 case ISD::SETGE: return PPC::PRED_GE;
583 case ISD::SETO: return PPC::PRED_NU;
584 case ISD::SETUO: return PPC::PRED_UN;
585 // These two are invalid for floating point. Assume we have int.
586 case ISD::SETULT: return PPC::PRED_LT;
587 case ISD::SETUGT: return PPC::PRED_GT;
591 /// getCRIdxForSetCC - Return the index of the condition register field
592 /// associated with the SetCC condition, and whether or not the field is
593 /// treated as inverted. That is, lt = 0; ge = 0 inverted.
595 /// If this returns with Other != -1, then the returned comparison is an or of
596 /// two simpler comparisons. In this case, Invert is guaranteed to be false.
597 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert, int &Other) {
601 default: llvm_unreachable("Unknown condition!");
603 case ISD::SETLT: return 0; // Bit #0 = SETOLT
605 case ISD::SETGT: return 1; // Bit #1 = SETOGT
607 case ISD::SETEQ: return 2; // Bit #2 = SETOEQ
608 case ISD::SETUO: return 3; // Bit #3 = SETUO
610 case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE
612 case ISD::SETLE: Invert = true; return 1; // !Bit #1 = SETULE
614 case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE
615 case ISD::SETO: Invert = true; return 3; // !Bit #3 = SETO
620 llvm_unreachable("Invalid branch code: should be expanded by legalize");
621 // These are invalid for floating point. Assume integer.
622 case ISD::SETULT: return 0;
623 case ISD::SETUGT: return 1;
627 // getVCmpInst: return the vector compare instruction for the specified
628 // vector type and condition code. Since this is for altivec specific code,
629 // only support the altivec types (v16i8, v8i16, v4i32, and v4f32).
630 static unsigned int getVCmpInst(MVT::SimpleValueType VecVT, ISD::CondCode CC) {
636 if (VecVT == MVT::v16i8)
637 return PPC::VCMPEQUB;
638 else if (VecVT == MVT::v8i16)
639 return PPC::VCMPEQUH;
640 else if (VecVT == MVT::v4i32)
641 return PPC::VCMPEQUW;
642 // v4f32 != v4f32 could be translate to unordered not equal
643 else if (VecVT == MVT::v4f32)
644 return PPC::VCMPEQFP;
650 if (VecVT == MVT::v16i8)
651 return PPC::VCMPGTSB;
652 else if (VecVT == MVT::v8i16)
653 return PPC::VCMPGTSH;
654 else if (VecVT == MVT::v4i32)
655 return PPC::VCMPGTSW;
656 else if (VecVT == MVT::v4f32)
657 return PPC::VCMPGTFP;
663 if (VecVT == MVT::v16i8)
664 return PPC::VCMPGTUB;
665 else if (VecVT == MVT::v8i16)
666 return PPC::VCMPGTUH;
667 else if (VecVT == MVT::v4i32)
668 return PPC::VCMPGTUW;
671 if (VecVT == MVT::v4f32)
672 return PPC::VCMPEQFP;
677 if (VecVT == MVT::v4f32)
678 return PPC::VCMPGTFP;
681 if (VecVT == MVT::v4f32)
682 return PPC::VCMPGEFP;
687 llvm_unreachable("Invalid integer vector compare condition");
690 // getVCmpEQInst: return the equal compare instruction for the specified vector
691 // type. Since this is for altivec specific code, only support the altivec
692 // types (v16i8, v8i16, v4i32, and v4f32).
693 static unsigned int getVCmpEQInst(MVT::SimpleValueType VecVT) {
696 return PPC::VCMPEQUB;
698 return PPC::VCMPEQUH;
700 return PPC::VCMPEQUW;
702 return PPC::VCMPEQFP;
704 llvm_unreachable("Invalid integer vector compare condition");
709 SDNode *PPCDAGToDAGISel::SelectSETCC(SDNode *N) {
710 DebugLoc dl = N->getDebugLoc();
712 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
713 EVT PtrVT = CurDAG->getTargetLoweringInfo().getPointerTy();
714 bool isPPC64 = (PtrVT == MVT::i64);
716 if (isInt32Immediate(N->getOperand(1), Imm)) {
717 // We can codegen setcc op, imm very efficiently compared to a brcond.
718 // Check for those cases here.
721 SDValue Op = N->getOperand(0);
725 Op = SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Op), 0);
726 SDValue Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) };
727 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
732 SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
733 Op, getI32Imm(~0U)), 0);
734 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
738 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
739 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
743 SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Op), 0);
744 T = SDValue(CurDAG->getMachineNode(PPC::ANDC, dl, MVT::i32, T, Op), 0);
745 SDValue Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
746 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
749 } else if (Imm == ~0U) { // setcc op, -1
750 SDValue Op = N->getOperand(0);
755 Op = SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
756 Op, getI32Imm(1)), 0);
757 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
758 SDValue(CurDAG->getMachineNode(PPC::LI, dl,
764 Op = SDValue(CurDAG->getMachineNode(PPC::NOR, dl, MVT::i32, Op, Op), 0);
765 SDNode *AD = CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
767 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0),
771 SDValue AD = SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Op,
773 SDValue AN = SDValue(CurDAG->getMachineNode(PPC::AND, dl, MVT::i32, AD,
775 SDValue Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
776 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
779 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
780 Op = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops, 4),
782 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op,
789 SDValue LHS = N->getOperand(0);
790 SDValue RHS = N->getOperand(1);
792 // Altivec Vector compare instructions do not set any CR register by default and
793 // vector compare operations return the same type as the operands.
794 if (LHS.getValueType().isVector()) {
795 EVT VecVT = LHS.getValueType();
796 MVT::SimpleValueType VT = VecVT.getSimpleVT().SimpleTy;
797 unsigned int VCmpInst = getVCmpInst(VT, CC);
803 return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS);
807 SDValue VCmp(CurDAG->getMachineNode(VCmpInst, dl, VecVT, LHS, RHS), 0);
808 return CurDAG->SelectNodeTo(N, PPC::VNOR, VecVT, VCmp, VCmp);
813 return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, RHS, LHS);
817 return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS);
821 // Small optimization: Altivec provides a 'Vector Compare Greater Than
822 // or Equal To' instruction (vcmpgefp), so in this case there is no
823 // need for extra logic for the equal compare.
824 if (VecVT.getSimpleVT().isFloatingPoint()) {
825 return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS);
827 SDValue VCmpGT(CurDAG->getMachineNode(VCmpInst, dl, VecVT, LHS, RHS), 0);
828 unsigned int VCmpEQInst = getVCmpEQInst(VT);
829 SDValue VCmpEQ(CurDAG->getMachineNode(VCmpEQInst, dl, VecVT, LHS, RHS), 0);
830 return CurDAG->SelectNodeTo(N, PPC::VOR, VecVT, VCmpGT, VCmpEQ);
836 SDValue VCmpLE(CurDAG->getMachineNode(VCmpInst, dl, VecVT, RHS, LHS), 0);
837 unsigned int VCmpEQInst = getVCmpEQInst(VT);
838 SDValue VCmpEQ(CurDAG->getMachineNode(VCmpEQInst, dl, VecVT, LHS, RHS), 0);
839 return CurDAG->SelectNodeTo(N, PPC::VOR, VecVT, VCmpLE, VCmpEQ);
842 llvm_unreachable("Invalid vector compare type: should be expanded by legalize");
848 unsigned Idx = getCRIdxForSetCC(CC, Inv, OtherCondIdx);
849 SDValue CCReg = SelectCC(LHS, RHS, CC, dl);
852 // Force the ccreg into CR7.
853 SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
855 SDValue InFlag(0, 0); // Null incoming flag value.
856 CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, CR7Reg, CCReg,
859 if (PPCSubTarget.hasMFOCRF() && OtherCondIdx == -1)
860 IntCR = SDValue(CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg,
863 IntCR = SDValue(CurDAG->getMachineNode(PPC::MFCRpseud, dl, MVT::i32,
866 SDValue Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31),
867 getI32Imm(31), getI32Imm(31) };
868 if (OtherCondIdx == -1 && !Inv)
869 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
871 // Get the specified bit.
873 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0);
875 assert(OtherCondIdx == -1 && "Can't have split plus negation");
876 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
879 // Otherwise, we have to turn an operation like SETONE -> SETOLT | SETOGT.
880 // We already got the bit for the first part of the comparison (e.g. SETULE).
882 // Get the other bit of the comparison.
883 Ops[1] = getI32Imm((32-(3-OtherCondIdx)) & 31);
885 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0);
887 return CurDAG->SelectNodeTo(N, PPC::OR, MVT::i32, Tmp, OtherCond);
891 // Select - Convert the specified operand from a target-independent to a
892 // target-specific node if it hasn't already been changed.
893 SDNode *PPCDAGToDAGISel::Select(SDNode *N) {
894 DebugLoc dl = N->getDebugLoc();
895 if (N->isMachineOpcode())
896 return NULL; // Already selected.
898 switch (N->getOpcode()) {
901 case ISD::Constant: {
902 if (N->getValueType(0) == MVT::i64) {
904 int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue();
905 // Assume no remaining bits.
906 unsigned Remainder = 0;
907 // Assume no shift required.
910 // If it can't be represented as a 32 bit value.
911 if (!isInt<32>(Imm)) {
912 Shift = CountTrailingZeros_64(Imm);
913 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
915 // If the shifted value fits 32 bits.
916 if (isInt<32>(ImmSh)) {
917 // Go with the shifted value.
920 // Still stuck with a 64 bit value.
927 // Intermediate operand.
930 // Handle first 32 bits.
931 unsigned Lo = Imm & 0xFFFF;
932 unsigned Hi = (Imm >> 16) & 0xFFFF;
935 if (isInt<16>(Imm)) {
937 Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo));
939 // Handle the Hi bits.
940 unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8;
941 Result = CurDAG->getMachineNode(OpC, dl, MVT::i64, getI32Imm(Hi));
943 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
944 SDValue(Result, 0), getI32Imm(Lo));
947 Result = CurDAG->getMachineNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi));
950 // If no shift, we're done.
951 if (!Shift) return Result;
953 // Shift for next step if the upper 32-bits were not zero.
955 Result = CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64,
958 getI32Imm(63 - Shift));
961 // Add in the last bits as required.
962 if ((Hi = (Remainder >> 16) & 0xFFFF)) {
963 Result = CurDAG->getMachineNode(PPC::ORIS8, dl, MVT::i64,
964 SDValue(Result, 0), getI32Imm(Hi));
966 if ((Lo = Remainder & 0xFFFF)) {
967 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
968 SDValue(Result, 0), getI32Imm(Lo));
977 return SelectSETCC(N);
978 case PPCISD::GlobalBaseReg:
979 return getGlobalBaseReg();
981 case ISD::FrameIndex: {
982 int FI = cast<FrameIndexSDNode>(N)->getIndex();
983 SDValue TFI = CurDAG->getTargetFrameIndex(FI, N->getValueType(0));
984 unsigned Opc = N->getValueType(0) == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
986 return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), TFI,
988 return CurDAG->getMachineNode(Opc, dl, N->getValueType(0), TFI,
993 SDValue InFlag = N->getOperand(1);
994 // Use MFOCRF if supported.
995 if (PPCSubTarget.hasMFOCRF())
996 return CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32,
997 N->getOperand(0), InFlag);
999 return CurDAG->getMachineNode(PPC::MFCRpseud, dl, MVT::i32,
1000 N->getOperand(0), InFlag);
1004 // FIXME: since this depends on the setting of the carry flag from the srawi
1005 // we should really be making notes about that for the scheduler.
1006 // FIXME: It sure would be nice if we could cheaply recognize the
1007 // srl/add/sra pattern the dag combiner will generate for this as
1008 // sra/addze rather than having to handle sdiv ourselves. oh well.
1010 if (isInt32Immediate(N->getOperand(1), Imm)) {
1011 SDValue N0 = N->getOperand(0);
1012 if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
1014 CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Glue,
1015 N0, getI32Imm(Log2_32(Imm)));
1016 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
1017 SDValue(Op, 0), SDValue(Op, 1));
1018 } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
1020 CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Glue,
1021 N0, getI32Imm(Log2_32(-Imm)));
1023 SDValue(CurDAG->getMachineNode(PPC::ADDZE, dl, MVT::i32,
1024 SDValue(Op, 0), SDValue(Op, 1)),
1026 return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
1030 // Other cases are autogenerated.
1035 // Handle preincrement loads.
1036 LoadSDNode *LD = cast<LoadSDNode>(N);
1037 EVT LoadedVT = LD->getMemoryVT();
1039 // Normal loads are handled by code generated from the .td file.
1040 if (LD->getAddressingMode() != ISD::PRE_INC)
1043 SDValue Offset = LD->getOffset();
1044 if (isa<ConstantSDNode>(Offset) ||
1045 Offset.getOpcode() == ISD::TargetGlobalAddress) {
1048 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
1049 if (LD->getValueType(0) != MVT::i64) {
1050 // Handle PPC32 integer and normal FP loads.
1051 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
1052 switch (LoadedVT.getSimpleVT().SimpleTy) {
1053 default: llvm_unreachable("Invalid PPC load type!");
1054 case MVT::f64: Opcode = PPC::LFDU; break;
1055 case MVT::f32: Opcode = PPC::LFSU; break;
1056 case MVT::i32: Opcode = PPC::LWZU; break;
1057 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
1059 case MVT::i8: Opcode = PPC::LBZU; break;
1062 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
1063 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
1064 switch (LoadedVT.getSimpleVT().SimpleTy) {
1065 default: llvm_unreachable("Invalid PPC load type!");
1066 case MVT::i64: Opcode = PPC::LDU; break;
1067 case MVT::i32: Opcode = PPC::LWZU8; break;
1068 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
1070 case MVT::i8: Opcode = PPC::LBZU8; break;
1074 SDValue Chain = LD->getChain();
1075 SDValue Base = LD->getBasePtr();
1076 SDValue Ops[] = { Offset, Base, Chain };
1077 return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0),
1078 PPCLowering.getPointerTy(),
1079 MVT::Other, Ops, 3);
1082 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
1083 if (LD->getValueType(0) != MVT::i64) {
1084 // Handle PPC32 integer and normal FP loads.
1085 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
1086 switch (LoadedVT.getSimpleVT().SimpleTy) {
1087 default: llvm_unreachable("Invalid PPC load type!");
1088 case MVT::f64: Opcode = PPC::LFDUX; break;
1089 case MVT::f32: Opcode = PPC::LFSUX; break;
1090 case MVT::i32: Opcode = PPC::LWZUX; break;
1091 case MVT::i16: Opcode = isSExt ? PPC::LHAUX : PPC::LHZUX; break;
1093 case MVT::i8: Opcode = PPC::LBZUX; break;
1096 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
1097 assert((!isSExt || LoadedVT == MVT::i16 || LoadedVT == MVT::i32) &&
1098 "Invalid sext update load");
1099 switch (LoadedVT.getSimpleVT().SimpleTy) {
1100 default: llvm_unreachable("Invalid PPC load type!");
1101 case MVT::i64: Opcode = PPC::LDUX; break;
1102 case MVT::i32: Opcode = isSExt ? PPC::LWAUX : PPC::LWZUX8; break;
1103 case MVT::i16: Opcode = isSExt ? PPC::LHAUX8 : PPC::LHZUX8; break;
1105 case MVT::i8: Opcode = PPC::LBZUX8; break;
1109 SDValue Chain = LD->getChain();
1110 SDValue Base = LD->getBasePtr();
1111 SDValue Ops[] = { Offset, Base, Chain };
1112 return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0),
1113 PPCLowering.getPointerTy(),
1114 MVT::Other, Ops, 3);
1119 unsigned Imm, Imm2, SH, MB, ME;
1122 // If this is an and of a value rotated between 0 and 31 bits and then and'd
1123 // with a mask, emit rlwinm
1124 if (isInt32Immediate(N->getOperand(1), Imm) &&
1125 isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH, MB, ME)) {
1126 SDValue Val = N->getOperand(0).getOperand(0);
1127 SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
1128 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
1130 // If this is just a masked value where the input is not handled above, and
1131 // is not a rotate-left (handled by a pattern in the .td file), emit rlwinm
1132 if (isInt32Immediate(N->getOperand(1), Imm) &&
1133 isRunOfOnes(Imm, MB, ME) &&
1134 N->getOperand(0).getOpcode() != ISD::ROTL) {
1135 SDValue Val = N->getOperand(0);
1136 SDValue Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) };
1137 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
1139 // If this is a 64-bit zero-extension mask, emit rldicl.
1140 if (isInt64Immediate(N->getOperand(1).getNode(), Imm64) &&
1142 SDValue Val = N->getOperand(0);
1143 MB = 64 - CountTrailingOnes_64(Imm64);
1144 SDValue Ops[] = { Val, getI32Imm(0), getI32Imm(MB) };
1145 return CurDAG->SelectNodeTo(N, PPC::RLDICL, MVT::i64, Ops, 3);
1147 // AND X, 0 -> 0, not "rlwinm 32".
1148 if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) {
1149 ReplaceUses(SDValue(N, 0), N->getOperand(1));
1152 // ISD::OR doesn't get all the bitfield insertion fun.
1153 // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert
1154 if (isInt32Immediate(N->getOperand(1), Imm) &&
1155 N->getOperand(0).getOpcode() == ISD::OR &&
1156 isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) {
1159 if (isRunOfOnes(Imm, MB, ME)) {
1160 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1161 N->getOperand(0).getOperand(1),
1162 getI32Imm(0), getI32Imm(MB),getI32Imm(ME) };
1163 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5);
1167 // Other cases are autogenerated.
1171 if (N->getValueType(0) == MVT::i32)
1172 if (SDNode *I = SelectBitfieldInsert(N))
1175 // Other cases are autogenerated.
1178 unsigned Imm, SH, MB, ME;
1179 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
1180 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
1181 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1182 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
1183 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
1186 // Other cases are autogenerated.
1190 unsigned Imm, SH, MB, ME;
1191 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
1192 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
1193 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1194 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
1195 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
1198 // Other cases are autogenerated.
1201 case ISD::SELECT_CC: {
1202 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1203 EVT PtrVT = CurDAG->getTargetLoweringInfo().getPointerTy();
1204 bool isPPC64 = (PtrVT == MVT::i64);
1206 // Handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
1208 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1209 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
1210 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
1211 if (N1C->isNullValue() && N3C->isNullValue() &&
1212 N2C->getZExtValue() == 1ULL && CC == ISD::SETNE &&
1213 // FIXME: Implement this optzn for PPC64.
1214 N->getValueType(0) == MVT::i32) {
1216 CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
1217 N->getOperand(0), getI32Imm(~0U));
1218 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
1219 SDValue(Tmp, 0), N->getOperand(0),
1223 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl);
1224 unsigned BROpc = getPredicateForSetCC(CC);
1226 unsigned SelectCCOp;
1227 if (N->getValueType(0) == MVT::i32)
1228 SelectCCOp = PPC::SELECT_CC_I4;
1229 else if (N->getValueType(0) == MVT::i64)
1230 SelectCCOp = PPC::SELECT_CC_I8;
1231 else if (N->getValueType(0) == MVT::f32)
1232 SelectCCOp = PPC::SELECT_CC_F4;
1233 else if (N->getValueType(0) == MVT::f64)
1234 SelectCCOp = PPC::SELECT_CC_F8;
1236 SelectCCOp = PPC::SELECT_CC_VRRC;
1238 SDValue Ops[] = { CCReg, N->getOperand(2), N->getOperand(3),
1240 return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops, 4);
1242 case PPCISD::COND_BRANCH: {
1243 // Op #0 is the Chain.
1244 // Op #1 is the PPC::PRED_* number.
1246 // Op #3 is the Dest MBB
1247 // Op #4 is the Flag.
1248 // Prevent PPC::PRED_* from being selected into LI.
1250 getI32Imm(cast<ConstantSDNode>(N->getOperand(1))->getZExtValue());
1251 SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3),
1252 N->getOperand(0), N->getOperand(4) };
1253 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 5);
1256 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
1257 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl);
1258 SDValue Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode,
1259 N->getOperand(4), N->getOperand(0) };
1260 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 4);
1263 // FIXME: Should custom lower this.
1264 SDValue Chain = N->getOperand(0);
1265 SDValue Target = N->getOperand(1);
1266 unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
1267 unsigned Reg = Target.getValueType() == MVT::i32 ? PPC::BCTR : PPC::BCTR8;
1268 Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, Target,
1270 return CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain);
1272 case PPCISD::TOC_ENTRY: {
1273 assert (PPCSubTarget.isPPC64() && "Only supported for 64-bit ABI");
1275 // For medium code model, we generate two instructions as described
1276 // below. Otherwise we allow SelectCodeCommon to handle this, selecting
1277 // one of LDtoc, LDtocJTI, and LDtocCPT.
1278 if (TM.getCodeModel() != CodeModel::Medium)
1281 // The first source operand is a TargetGlobalAddress or a
1282 // TargetJumpTable. If it is an externally defined symbol, a symbol
1283 // with common linkage, a function address, or a jump table address,
1285 // LDtocL(<ga:@sym>, ADDIStocHA(%X2, <ga:@sym>))
1286 // Otherwise we generate:
1287 // ADDItocL(ADDIStocHA(%X2, <ga:@sym>), <ga:@sym>)
1288 SDValue GA = N->getOperand(0);
1289 SDValue TOCbase = N->getOperand(1);
1290 SDNode *Tmp = CurDAG->getMachineNode(PPC::ADDIStocHA, dl, MVT::i64,
1293 if (isa<JumpTableSDNode>(GA))
1294 return CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA,
1297 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(GA)) {
1298 const GlobalValue *GValue = G->getGlobal();
1299 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GValue);
1300 assert((GVar || isa<Function>(GValue)) &&
1301 "Unexpected global value subclass!");
1303 // An external variable is one without an initializer. For these,
1304 // for variables with common linkage, and for Functions, generate
1306 if (!GVar || !GVar->hasInitializer() || GValue->hasCommonLinkage())
1307 return CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA,
1311 return CurDAG->getMachineNode(PPC::ADDItocL, dl, MVT::i64,
1312 SDValue(Tmp, 0), GA);
1316 return SelectCode(N);
1321 /// createPPCISelDag - This pass converts a legalized DAG into a
1322 /// PowerPC-specific DAG, ready for instruction scheduling.
1324 FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) {
1325 return new PPCDAGToDAGISel(TM);