1 //===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for PowerPC,
11 // converting from a legalized dag to a PPC dag.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "ppc-codegen"
17 #include "PPCPredicates.h"
18 #include "PPCTargetMachine.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/CodeGen/SelectionDAGISel.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/Constants.h"
27 #include "llvm/Function.h"
28 #include "llvm/GlobalValue.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
37 //===--------------------------------------------------------------------===//
38 /// PPCDAGToDAGISel - PPC specific code to select PPC machine
39 /// instructions for SelectionDAG operations.
41 class PPCDAGToDAGISel : public SelectionDAGISel {
42 const PPCTargetMachine &TM;
43 const PPCTargetLowering &PPCLowering;
44 const PPCSubtarget &PPCSubTarget;
45 unsigned GlobalBaseReg;
47 explicit PPCDAGToDAGISel(PPCTargetMachine &tm)
48 : SelectionDAGISel(tm), TM(tm),
49 PPCLowering(*TM.getTargetLowering()),
50 PPCSubTarget(*TM.getSubtargetImpl()) {}
52 virtual bool runOnMachineFunction(MachineFunction &MF) {
53 // Make sure we re-emit a set of the global base reg if necessary
55 SelectionDAGISel::runOnMachineFunction(MF);
61 /// getI32Imm - Return a target constant with the specified value, of type
63 inline SDValue getI32Imm(unsigned Imm) {
64 return CurDAG->getTargetConstant(Imm, MVT::i32);
67 /// getI64Imm - Return a target constant with the specified value, of type
69 inline SDValue getI64Imm(uint64_t Imm) {
70 return CurDAG->getTargetConstant(Imm, MVT::i64);
73 /// getSmallIPtrImm - Return a target constant of pointer type.
74 inline SDValue getSmallIPtrImm(unsigned Imm) {
75 return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy());
78 /// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s
79 /// with any number of 0s on either side. The 1s are allowed to wrap from
80 /// LSB to MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs.
81 /// 0x0F0F0000 is not, since all 1s are not contiguous.
82 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME);
85 /// isRotateAndMask - Returns true if Mask and Shift can be folded into a
86 /// rotate and mask opcode and mask operation.
87 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool isShiftMask,
88 unsigned &SH, unsigned &MB, unsigned &ME);
90 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
91 /// base register. Return the virtual register that holds this value.
92 SDNode *getGlobalBaseReg();
94 // Select - Convert the specified operand from a target-independent to a
95 // target-specific node if it hasn't already been changed.
96 SDNode *Select(SDNode *N);
98 SDNode *SelectBitfieldInsert(SDNode *N);
100 /// SelectCC - Select a comparison of the specified values with the
101 /// specified condition code, returning the CR# of the expression.
102 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, DebugLoc dl);
104 /// SelectAddrImm - Returns true if the address N can be represented by
105 /// a base register plus a signed 16-bit displacement [r+imm].
106 bool SelectAddrImm(SDValue N, SDValue &Disp,
108 return PPCLowering.SelectAddressRegImm(N, Disp, Base, *CurDAG);
111 /// SelectAddrImmOffs - Return true if the operand is valid for a preinc
112 /// immediate field. Because preinc imms have already been validated, just
114 bool SelectAddrImmOffs(SDValue N, SDValue &Out) const {
119 /// SelectAddrIdx - Given the specified addressed, check to see if it can be
120 /// represented as an indexed [r+r] operation. Returns false if it can
121 /// be represented by [r+imm], which are preferred.
122 bool SelectAddrIdx(SDValue N, SDValue &Base, SDValue &Index) {
123 return PPCLowering.SelectAddressRegReg(N, Base, Index, *CurDAG);
126 /// SelectAddrIdxOnly - Given the specified addressed, force it to be
127 /// represented as an indexed [r+r] operation.
128 bool SelectAddrIdxOnly(SDValue N, SDValue &Base, SDValue &Index) {
129 return PPCLowering.SelectAddressRegRegOnly(N, Base, Index, *CurDAG);
132 /// SelectAddrImmShift - Returns true if the address N can be represented by
133 /// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable
134 /// for use by STD and friends.
135 bool SelectAddrImmShift(SDValue N, SDValue &Disp, SDValue &Base) {
136 return PPCLowering.SelectAddressRegImmShift(N, Disp, Base, *CurDAG);
139 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
140 /// inline asm expressions. It is always correct to compute the value into
141 /// a register. The case of adding a (possibly relocatable) constant to a
142 /// register can be improved, but it is wrong to substitute Reg+Reg for
143 /// Reg in an asm, because the load or store opcode would have to change.
144 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
146 std::vector<SDValue> &OutOps) {
147 OutOps.push_back(Op);
151 void InsertVRSaveCode(MachineFunction &MF);
153 virtual const char *getPassName() const {
154 return "PowerPC DAG->DAG Pattern Instruction Selection";
157 // Include the pieces autogenerated from the target description.
158 #include "PPCGenDAGISel.inc"
161 SDNode *SelectSETCC(SDNode *N);
165 /// InsertVRSaveCode - Once the entire function has been instruction selected,
166 /// all virtual registers are created and all machine instructions are built,
167 /// check to see if we need to save/restore VRSAVE. If so, do it.
168 void PPCDAGToDAGISel::InsertVRSaveCode(MachineFunction &Fn) {
169 // Check to see if this function uses vector registers, which means we have to
170 // save and restore the VRSAVE register and update it with the regs we use.
172 // In this case, there will be virtual registers of vector type created
173 // by the scheduler. Detect them now.
174 bool HasVectorVReg = false;
175 for (unsigned i = 0, e = RegInfo->getNumVirtRegs(); i != e; ++i) {
176 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
177 if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) {
178 HasVectorVReg = true;
182 if (!HasVectorVReg) return; // nothing to do.
184 // If we have a vector register, we want to emit code into the entry and exit
185 // blocks to save and restore the VRSAVE register. We do this here (instead
186 // of marking all vector instructions as clobbering VRSAVE) for two reasons:
188 // 1. This (trivially) reduces the load on the register allocator, by not
189 // having to represent the live range of the VRSAVE register.
190 // 2. This (more significantly) allows us to create a temporary virtual
191 // register to hold the saved VRSAVE value, allowing this temporary to be
192 // register allocated, instead of forcing it to be spilled to the stack.
194 // Create two vregs - one to hold the VRSAVE register that is live-in to the
195 // function and one for the value after having bits or'd into it.
196 unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
197 unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
199 const TargetInstrInfo &TII = *TM.getInstrInfo();
200 MachineBasicBlock &EntryBB = *Fn.begin();
202 // Emit the following code into the entry block:
203 // InVRSAVE = MFVRSAVE
204 // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
205 // MTVRSAVE UpdatedVRSAVE
206 MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
207 BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE);
208 BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE),
209 UpdatedVRSAVE).addReg(InVRSAVE);
210 BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
212 // Find all return blocks, outputting a restore in each epilog.
213 for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
214 if (!BB->empty() && BB->back().getDesc().isReturn()) {
215 IP = BB->end(); --IP;
217 // Skip over all terminator instructions, which are part of the return
219 MachineBasicBlock::iterator I2 = IP;
220 while (I2 != BB->begin() && (--I2)->getDesc().isTerminator())
223 // Emit: MTVRSAVE InVRSave
224 BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
230 /// getGlobalBaseReg - Output the instructions required to put the
231 /// base address to use for accessing globals into a register.
233 SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
234 if (!GlobalBaseReg) {
235 const TargetInstrInfo &TII = *TM.getInstrInfo();
236 // Insert the set of GlobalBaseReg into the first MBB of the function
237 MachineBasicBlock &FirstMBB = MF->front();
238 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
241 if (PPCLowering.getPointerTy() == MVT::i32) {
242 GlobalBaseReg = RegInfo->createVirtualRegister(PPC::GPRCRegisterClass);
243 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));
244 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
246 GlobalBaseReg = RegInfo->createVirtualRegister(PPC::G8RCRegisterClass);
247 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8));
248 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg);
251 return CurDAG->getRegister(GlobalBaseReg,
252 PPCLowering.getPointerTy()).getNode();
255 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
256 /// or 64-bit immediate, and if the value can be accurately represented as a
257 /// sign extension from a 16-bit value. If so, this returns true and the
259 static bool isIntS16Immediate(SDNode *N, short &Imm) {
260 if (N->getOpcode() != ISD::Constant)
263 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
264 if (N->getValueType(0) == MVT::i32)
265 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
267 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
270 static bool isIntS16Immediate(SDValue Op, short &Imm) {
271 return isIntS16Immediate(Op.getNode(), Imm);
275 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
276 /// operand. If so Imm will receive the 32-bit value.
277 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
278 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
279 Imm = cast<ConstantSDNode>(N)->getZExtValue();
285 /// isInt64Immediate - This method tests to see if the node is a 64-bit constant
286 /// operand. If so Imm will receive the 64-bit value.
287 static bool isInt64Immediate(SDNode *N, uint64_t &Imm) {
288 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
289 Imm = cast<ConstantSDNode>(N)->getZExtValue();
295 // isInt32Immediate - This method tests to see if a constant operand.
296 // If so Imm will receive the 32 bit value.
297 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
298 return isInt32Immediate(N.getNode(), Imm);
302 // isOpcWithIntImmediate - This method tests to see if the node is a specific
303 // opcode and that it has a immediate integer right operand.
304 // If so Imm will receive the 32 bit value.
305 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
306 return N->getOpcode() == Opc
307 && isInt32Immediate(N->getOperand(1).getNode(), Imm);
310 bool PPCDAGToDAGISel::isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
311 if (isShiftedMask_32(Val)) {
312 // look for the first non-zero bit
313 MB = CountLeadingZeros_32(Val);
314 // look for the first zero bit after the run of ones
315 ME = CountLeadingZeros_32((Val - 1) ^ Val);
318 Val = ~Val; // invert mask
319 if (isShiftedMask_32(Val)) {
320 // effectively look for the first zero bit
321 ME = CountLeadingZeros_32(Val) - 1;
322 // effectively look for the first one bit after the run of zeros
323 MB = CountLeadingZeros_32((Val - 1) ^ Val) + 1;
331 bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask,
332 bool isShiftMask, unsigned &SH,
333 unsigned &MB, unsigned &ME) {
334 // Don't even go down this path for i64, since different logic will be
335 // necessary for rldicl/rldicr/rldimi.
336 if (N->getValueType(0) != MVT::i32)
340 unsigned Indeterminant = ~0; // bit mask marking indeterminant results
341 unsigned Opcode = N->getOpcode();
342 if (N->getNumOperands() != 2 ||
343 !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31))
346 if (Opcode == ISD::SHL) {
347 // apply shift left to mask if it comes first
348 if (isShiftMask) Mask = Mask << Shift;
349 // determine which bits are made indeterminant by shift
350 Indeterminant = ~(0xFFFFFFFFu << Shift);
351 } else if (Opcode == ISD::SRL) {
352 // apply shift right to mask if it comes first
353 if (isShiftMask) Mask = Mask >> Shift;
354 // determine which bits are made indeterminant by shift
355 Indeterminant = ~(0xFFFFFFFFu >> Shift);
356 // adjust for the left rotate
358 } else if (Opcode == ISD::ROTL) {
364 // if the mask doesn't intersect any Indeterminant bits
365 if (Mask && !(Mask & Indeterminant)) {
367 // make sure the mask is still a mask (wrap arounds may not be)
368 return isRunOfOnes(Mask, MB, ME);
373 /// SelectBitfieldInsert - turn an or of two masked values into
374 /// the rotate left word immediate then mask insert (rlwimi) instruction.
375 SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
376 SDValue Op0 = N->getOperand(0);
377 SDValue Op1 = N->getOperand(1);
378 DebugLoc dl = N->getDebugLoc();
380 APInt LKZ, LKO, RKZ, RKO;
381 CurDAG->ComputeMaskedBits(Op0, APInt::getAllOnesValue(32), LKZ, LKO);
382 CurDAG->ComputeMaskedBits(Op1, APInt::getAllOnesValue(32), RKZ, RKO);
384 unsigned TargetMask = LKZ.getZExtValue();
385 unsigned InsertMask = RKZ.getZExtValue();
387 if ((TargetMask | InsertMask) == 0xFFFFFFFF) {
388 unsigned Op0Opc = Op0.getOpcode();
389 unsigned Op1Opc = Op1.getOpcode();
390 unsigned Value, SH = 0;
391 TargetMask = ~TargetMask;
392 InsertMask = ~InsertMask;
394 // If the LHS has a foldable shift and the RHS does not, then swap it to the
395 // RHS so that we can fold the shift into the insert.
396 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
397 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
398 Op0.getOperand(0).getOpcode() == ISD::SRL) {
399 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
400 Op1.getOperand(0).getOpcode() != ISD::SRL) {
402 std::swap(Op0Opc, Op1Opc);
403 std::swap(TargetMask, InsertMask);
406 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
407 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
408 Op1.getOperand(0).getOpcode() != ISD::SRL) {
410 std::swap(Op0Opc, Op1Opc);
411 std::swap(TargetMask, InsertMask);
416 if (InsertMask && isRunOfOnes(InsertMask, MB, ME)) {
419 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
420 isInt32Immediate(Op1.getOperand(1), Value)) {
421 Op1 = Op1.getOperand(0);
422 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value;
424 if (Op1Opc == ISD::AND) {
425 unsigned SHOpc = Op1.getOperand(0).getOpcode();
426 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) &&
427 isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) {
428 Op1 = Op1.getOperand(0).getOperand(0);
429 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value;
431 Op1 = Op1.getOperand(0);
436 SDValue Ops[] = { Op0, Op1, getI32Imm(SH), getI32Imm(MB),
438 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5);
444 /// SelectCC - Select a comparison of the specified values with the specified
445 /// condition code, returning the CR# of the expression.
446 SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS,
447 ISD::CondCode CC, DebugLoc dl) {
448 // Always select the LHS.
451 if (LHS.getValueType() == MVT::i32) {
453 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
454 if (isInt32Immediate(RHS, Imm)) {
455 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
457 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
458 getI32Imm(Imm & 0xFFFF)), 0);
459 // If this is a 16-bit signed immediate, fold it.
460 if (isInt<16>((int)Imm))
461 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
462 getI32Imm(Imm & 0xFFFF)), 0);
464 // For non-equality comparisons, the default code would materialize the
465 // constant, then compare against it, like this:
469 // Since we are just comparing for equality, we can emit this instead:
470 // xoris r0,r3,0x1234
471 // cmplwi cr0,r0,0x5678
473 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS, dl, MVT::i32, LHS,
474 getI32Imm(Imm >> 16)), 0);
475 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, Xor,
476 getI32Imm(Imm & 0xFFFF)), 0);
479 } else if (ISD::isUnsignedIntSetCC(CC)) {
480 if (isInt32Immediate(RHS, Imm) && isUInt<16>(Imm))
481 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
482 getI32Imm(Imm & 0xFFFF)), 0);
486 if (isIntS16Immediate(RHS, SImm))
487 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
488 getI32Imm((int)SImm & 0xFFFF)),
492 } else if (LHS.getValueType() == MVT::i64) {
494 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
495 if (isInt64Immediate(RHS.getNode(), Imm)) {
496 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
498 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
499 getI32Imm(Imm & 0xFFFF)), 0);
500 // If this is a 16-bit signed immediate, fold it.
502 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
503 getI32Imm(Imm & 0xFFFF)), 0);
505 // For non-equality comparisons, the default code would materialize the
506 // constant, then compare against it, like this:
510 // Since we are just comparing for equality, we can emit this instead:
511 // xoris r0,r3,0x1234
512 // cmpldi cr0,r0,0x5678
514 if (isUInt<32>(Imm)) {
515 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS8, dl, MVT::i64, LHS,
516 getI64Imm(Imm >> 16)), 0);
517 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, Xor,
518 getI64Imm(Imm & 0xFFFF)), 0);
522 } else if (ISD::isUnsignedIntSetCC(CC)) {
523 if (isInt64Immediate(RHS.getNode(), Imm) && isUInt<16>(Imm))
524 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
525 getI64Imm(Imm & 0xFFFF)), 0);
529 if (isIntS16Immediate(RHS, SImm))
530 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
531 getI64Imm(SImm & 0xFFFF)),
535 } else if (LHS.getValueType() == MVT::f32) {
538 assert(LHS.getValueType() == MVT::f64 && "Unknown vt!");
541 return SDValue(CurDAG->getMachineNode(Opc, dl, MVT::i32, LHS, RHS), 0);
544 static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {
550 llvm_unreachable("Should be lowered by legalize!");
551 default: llvm_unreachable("Unknown condition!");
553 case ISD::SETEQ: return PPC::PRED_EQ;
555 case ISD::SETNE: return PPC::PRED_NE;
557 case ISD::SETLT: return PPC::PRED_LT;
559 case ISD::SETLE: return PPC::PRED_LE;
561 case ISD::SETGT: return PPC::PRED_GT;
563 case ISD::SETGE: return PPC::PRED_GE;
564 case ISD::SETO: return PPC::PRED_NU;
565 case ISD::SETUO: return PPC::PRED_UN;
566 // These two are invalid for floating point. Assume we have int.
567 case ISD::SETULT: return PPC::PRED_LT;
568 case ISD::SETUGT: return PPC::PRED_GT;
572 /// getCRIdxForSetCC - Return the index of the condition register field
573 /// associated with the SetCC condition, and whether or not the field is
574 /// treated as inverted. That is, lt = 0; ge = 0 inverted.
576 /// If this returns with Other != -1, then the returned comparison is an or of
577 /// two simpler comparisons. In this case, Invert is guaranteed to be false.
578 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert, int &Other) {
582 default: llvm_unreachable("Unknown condition!");
584 case ISD::SETLT: return 0; // Bit #0 = SETOLT
586 case ISD::SETGT: return 1; // Bit #1 = SETOGT
588 case ISD::SETEQ: return 2; // Bit #2 = SETOEQ
589 case ISD::SETUO: return 3; // Bit #3 = SETUO
591 case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE
593 case ISD::SETLE: Invert = true; return 1; // !Bit #1 = SETULE
595 case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE
596 case ISD::SETO: Invert = true; return 3; // !Bit #3 = SETO
601 llvm_unreachable("Invalid branch code: should be expanded by legalize");
602 // These are invalid for floating point. Assume integer.
603 case ISD::SETULT: return 0;
604 case ISD::SETUGT: return 1;
609 SDNode *PPCDAGToDAGISel::SelectSETCC(SDNode *N) {
610 DebugLoc dl = N->getDebugLoc();
612 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
613 if (isInt32Immediate(N->getOperand(1), Imm)) {
614 // We can codegen setcc op, imm very efficiently compared to a brcond.
615 // Check for those cases here.
618 SDValue Op = N->getOperand(0);
622 Op = SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Op), 0);
623 SDValue Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) };
624 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
628 SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
629 Op, getI32Imm(~0U)), 0);
630 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
634 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
635 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
639 SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Op), 0);
640 T = SDValue(CurDAG->getMachineNode(PPC::ANDC, dl, MVT::i32, T, Op), 0);
641 SDValue Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
642 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
645 } else if (Imm == ~0U) { // setcc op, -1
646 SDValue Op = N->getOperand(0);
650 Op = SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
651 Op, getI32Imm(1)), 0);
652 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
653 SDValue(CurDAG->getMachineNode(PPC::LI, dl,
658 Op = SDValue(CurDAG->getMachineNode(PPC::NOR, dl, MVT::i32, Op, Op), 0);
659 SDNode *AD = CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
661 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0),
665 SDValue AD = SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Op,
667 SDValue AN = SDValue(CurDAG->getMachineNode(PPC::AND, dl, MVT::i32, AD,
669 SDValue Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
670 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
673 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
674 Op = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops, 4),
676 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op,
685 unsigned Idx = getCRIdxForSetCC(CC, Inv, OtherCondIdx);
686 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl);
689 // Force the ccreg into CR7.
690 SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
692 SDValue InFlag(0, 0); // Null incoming flag value.
693 CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, CR7Reg, CCReg,
696 if (PPCSubTarget.isGigaProcessor() && OtherCondIdx == -1)
697 IntCR = SDValue(CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg,
700 IntCR = SDValue(CurDAG->getMachineNode(PPC::MFCRpseud, dl, MVT::i32,
703 SDValue Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31),
704 getI32Imm(31), getI32Imm(31) };
705 if (OtherCondIdx == -1 && !Inv)
706 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
708 // Get the specified bit.
710 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0);
712 assert(OtherCondIdx == -1 && "Can't have split plus negation");
713 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
716 // Otherwise, we have to turn an operation like SETONE -> SETOLT | SETOGT.
717 // We already got the bit for the first part of the comparison (e.g. SETULE).
719 // Get the other bit of the comparison.
720 Ops[1] = getI32Imm((32-(3-OtherCondIdx)) & 31);
722 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0);
724 return CurDAG->SelectNodeTo(N, PPC::OR, MVT::i32, Tmp, OtherCond);
728 // Select - Convert the specified operand from a target-independent to a
729 // target-specific node if it hasn't already been changed.
730 SDNode *PPCDAGToDAGISel::Select(SDNode *N) {
731 DebugLoc dl = N->getDebugLoc();
732 if (N->isMachineOpcode())
733 return NULL; // Already selected.
735 switch (N->getOpcode()) {
738 case ISD::Constant: {
739 if (N->getValueType(0) == MVT::i64) {
741 int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue();
742 // Assume no remaining bits.
743 unsigned Remainder = 0;
744 // Assume no shift required.
747 // If it can't be represented as a 32 bit value.
748 if (!isInt<32>(Imm)) {
749 Shift = CountTrailingZeros_64(Imm);
750 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
752 // If the shifted value fits 32 bits.
753 if (isInt<32>(ImmSh)) {
754 // Go with the shifted value.
757 // Still stuck with a 64 bit value.
764 // Intermediate operand.
767 // Handle first 32 bits.
768 unsigned Lo = Imm & 0xFFFF;
769 unsigned Hi = (Imm >> 16) & 0xFFFF;
772 if (isInt<16>(Imm)) {
774 Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo));
776 // Handle the Hi bits.
777 unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8;
778 Result = CurDAG->getMachineNode(OpC, dl, MVT::i64, getI32Imm(Hi));
780 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
781 SDValue(Result, 0), getI32Imm(Lo));
784 Result = CurDAG->getMachineNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi));
787 // If no shift, we're done.
788 if (!Shift) return Result;
790 // Shift for next step if the upper 32-bits were not zero.
792 Result = CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64,
795 getI32Imm(63 - Shift));
798 // Add in the last bits as required.
799 if ((Hi = (Remainder >> 16) & 0xFFFF)) {
800 Result = CurDAG->getMachineNode(PPC::ORIS8, dl, MVT::i64,
801 SDValue(Result, 0), getI32Imm(Hi));
803 if ((Lo = Remainder & 0xFFFF)) {
804 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
805 SDValue(Result, 0), getI32Imm(Lo));
814 return SelectSETCC(N);
815 case PPCISD::GlobalBaseReg:
816 return getGlobalBaseReg();
818 case ISD::FrameIndex: {
819 int FI = cast<FrameIndexSDNode>(N)->getIndex();
820 SDValue TFI = CurDAG->getTargetFrameIndex(FI, N->getValueType(0));
821 unsigned Opc = N->getValueType(0) == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
823 return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), TFI,
825 return CurDAG->getMachineNode(Opc, dl, N->getValueType(0), TFI,
830 SDValue InFlag = N->getOperand(1);
831 // Use MFOCRF if supported.
832 if (PPCSubTarget.isGigaProcessor())
833 return CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32,
834 N->getOperand(0), InFlag);
836 return CurDAG->getMachineNode(PPC::MFCRpseud, dl, MVT::i32,
837 N->getOperand(0), InFlag);
841 // FIXME: since this depends on the setting of the carry flag from the srawi
842 // we should really be making notes about that for the scheduler.
843 // FIXME: It sure would be nice if we could cheaply recognize the
844 // srl/add/sra pattern the dag combiner will generate for this as
845 // sra/addze rather than having to handle sdiv ourselves. oh well.
847 if (isInt32Immediate(N->getOperand(1), Imm)) {
848 SDValue N0 = N->getOperand(0);
849 if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
851 CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Glue,
852 N0, getI32Imm(Log2_32(Imm)));
853 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
854 SDValue(Op, 0), SDValue(Op, 1));
855 } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
857 CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Glue,
858 N0, getI32Imm(Log2_32(-Imm)));
860 SDValue(CurDAG->getMachineNode(PPC::ADDZE, dl, MVT::i32,
861 SDValue(Op, 0), SDValue(Op, 1)),
863 return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
867 // Other cases are autogenerated.
872 // Handle preincrement loads.
873 LoadSDNode *LD = cast<LoadSDNode>(N);
874 EVT LoadedVT = LD->getMemoryVT();
876 // Normal loads are handled by code generated from the .td file.
877 if (LD->getAddressingMode() != ISD::PRE_INC)
880 SDValue Offset = LD->getOffset();
881 if (isa<ConstantSDNode>(Offset) ||
882 Offset.getOpcode() == ISD::TargetGlobalAddress) {
885 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
886 if (LD->getValueType(0) != MVT::i64) {
887 // Handle PPC32 integer and normal FP loads.
888 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
889 switch (LoadedVT.getSimpleVT().SimpleTy) {
890 default: llvm_unreachable("Invalid PPC load type!");
891 case MVT::f64: Opcode = PPC::LFDU; break;
892 case MVT::f32: Opcode = PPC::LFSU; break;
893 case MVT::i32: Opcode = PPC::LWZU; break;
894 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
896 case MVT::i8: Opcode = PPC::LBZU; break;
899 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
900 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
901 switch (LoadedVT.getSimpleVT().SimpleTy) {
902 default: llvm_unreachable("Invalid PPC load type!");
903 case MVT::i64: Opcode = PPC::LDU; break;
904 case MVT::i32: Opcode = PPC::LWZU8; break;
905 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
907 case MVT::i8: Opcode = PPC::LBZU8; break;
911 SDValue Chain = LD->getChain();
912 SDValue Base = LD->getBasePtr();
913 SDValue Ops[] = { Offset, Base, Chain };
915 return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0),
916 PPCLowering.getPointerTy(),
919 llvm_unreachable("R+R preindex loads not supported yet!");
924 unsigned Imm, Imm2, SH, MB, ME;
926 // If this is an and of a value rotated between 0 and 31 bits and then and'd
927 // with a mask, emit rlwinm
928 if (isInt32Immediate(N->getOperand(1), Imm) &&
929 isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH, MB, ME)) {
930 SDValue Val = N->getOperand(0).getOperand(0);
931 SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
932 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
934 // If this is just a masked value where the input is not handled above, and
935 // is not a rotate-left (handled by a pattern in the .td file), emit rlwinm
936 if (isInt32Immediate(N->getOperand(1), Imm) &&
937 isRunOfOnes(Imm, MB, ME) &&
938 N->getOperand(0).getOpcode() != ISD::ROTL) {
939 SDValue Val = N->getOperand(0);
940 SDValue Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) };
941 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
943 // AND X, 0 -> 0, not "rlwinm 32".
944 if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) {
945 ReplaceUses(SDValue(N, 0), N->getOperand(1));
948 // ISD::OR doesn't get all the bitfield insertion fun.
949 // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert
950 if (isInt32Immediate(N->getOperand(1), Imm) &&
951 N->getOperand(0).getOpcode() == ISD::OR &&
952 isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) {
955 if (isRunOfOnes(Imm, MB, ME)) {
956 SDValue Ops[] = { N->getOperand(0).getOperand(0),
957 N->getOperand(0).getOperand(1),
958 getI32Imm(0), getI32Imm(MB),getI32Imm(ME) };
959 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5);
963 // Other cases are autogenerated.
967 if (N->getValueType(0) == MVT::i32)
968 if (SDNode *I = SelectBitfieldInsert(N))
971 // Other cases are autogenerated.
974 unsigned Imm, SH, MB, ME;
975 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
976 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
977 SDValue Ops[] = { N->getOperand(0).getOperand(0),
978 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
979 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
982 // Other cases are autogenerated.
986 unsigned Imm, SH, MB, ME;
987 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
988 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
989 SDValue Ops[] = { N->getOperand(0).getOperand(0),
990 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
991 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
994 // Other cases are autogenerated.
997 case ISD::SELECT_CC: {
998 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1000 // Handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
1001 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1002 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
1003 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
1004 if (N1C->isNullValue() && N3C->isNullValue() &&
1005 N2C->getZExtValue() == 1ULL && CC == ISD::SETNE &&
1006 // FIXME: Implement this optzn for PPC64.
1007 N->getValueType(0) == MVT::i32) {
1009 CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
1010 N->getOperand(0), getI32Imm(~0U));
1011 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
1012 SDValue(Tmp, 0), N->getOperand(0),
1016 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl);
1017 unsigned BROpc = getPredicateForSetCC(CC);
1019 unsigned SelectCCOp;
1020 if (N->getValueType(0) == MVT::i32)
1021 SelectCCOp = PPC::SELECT_CC_I4;
1022 else if (N->getValueType(0) == MVT::i64)
1023 SelectCCOp = PPC::SELECT_CC_I8;
1024 else if (N->getValueType(0) == MVT::f32)
1025 SelectCCOp = PPC::SELECT_CC_F4;
1026 else if (N->getValueType(0) == MVT::f64)
1027 SelectCCOp = PPC::SELECT_CC_F8;
1029 SelectCCOp = PPC::SELECT_CC_VRRC;
1031 SDValue Ops[] = { CCReg, N->getOperand(2), N->getOperand(3),
1033 return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops, 4);
1035 case PPCISD::COND_BRANCH: {
1036 // Op #0 is the Chain.
1037 // Op #1 is the PPC::PRED_* number.
1039 // Op #3 is the Dest MBB
1040 // Op #4 is the Flag.
1041 // Prevent PPC::PRED_* from being selected into LI.
1043 getI32Imm(cast<ConstantSDNode>(N->getOperand(1))->getZExtValue());
1044 SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3),
1045 N->getOperand(0), N->getOperand(4) };
1046 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 5);
1049 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
1050 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl);
1051 SDValue Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode,
1052 N->getOperand(4), N->getOperand(0) };
1053 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 4);
1056 // FIXME: Should custom lower this.
1057 SDValue Chain = N->getOperand(0);
1058 SDValue Target = N->getOperand(1);
1059 unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
1060 Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Target,
1062 return CurDAG->SelectNodeTo(N, PPC::BCTR, MVT::Other, Chain);
1066 return SelectCode(N);
1071 /// createPPCISelDag - This pass converts a legalized DAG into a
1072 /// PowerPC-specific DAG, ready for instruction scheduling.
1074 FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) {
1075 return new PPCDAGToDAGISel(TM);