1 //===-- PPC32ISelDAGToDAG.cpp - PPC32 pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for 32 bit PowerPC,
11 // converting from a legalized dag to a PPC dag.
13 //===----------------------------------------------------------------------===//
16 #include "PPC32TargetMachine.h"
17 #include "PPC32ISelLowering.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/SSARegMap.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/SelectionDAGISel.h"
23 #include "llvm/Target/TargetOptions.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/Constants.h"
26 #include "llvm/GlobalValue.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/MathExtras.h"
32 Statistic<> FusedFP ("ppc-codegen", "Number of fused fp operations");
33 Statistic<> FrameOff("ppc-codegen", "Number of frame idx offsets collapsed");
35 //===--------------------------------------------------------------------===//
36 /// PPC32DAGToDAGISel - PPC32 specific code to select PPC32 machine
37 /// instructions for SelectionDAG operations.
39 class PPC32DAGToDAGISel : public SelectionDAGISel {
40 PPC32TargetLowering PPC32Lowering;
41 unsigned GlobalBaseReg;
43 PPC32DAGToDAGISel(TargetMachine &TM)
44 : SelectionDAGISel(PPC32Lowering), PPC32Lowering(TM) {}
46 virtual bool runOnFunction(Function &Fn) {
47 // Make sure we re-emit a set of the global base reg if necessary
49 return SelectionDAGISel::runOnFunction(Fn);
52 /// getI32Imm - Return a target constant with the specified value, of type
54 inline SDOperand getI32Imm(unsigned Imm) {
55 return CurDAG->getTargetConstant(Imm, MVT::i32);
58 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
59 /// base register. Return the virtual register that holds this value.
60 SDOperand getGlobalBaseReg();
62 // Select - Convert the specified operand from a target-independent to a
63 // target-specific node if it hasn't already been changed.
64 SDOperand Select(SDOperand Op);
66 SDNode *SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
67 unsigned OCHi, unsigned OCLo,
68 bool IsArithmetic = false,
70 SDNode *SelectBitfieldInsert(SDNode *N);
72 /// SelectCC - Select a comparison of the specified values with the
73 /// specified condition code, returning the CR# of the expression.
74 SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
76 /// SelectAddr - Given the specified address, return the two operands for a
77 /// load/store instruction, and return true if it should be an indexed [r+r]
79 bool SelectAddr(SDOperand Addr, SDOperand &Op1, SDOperand &Op2);
81 SDOperand BuildSDIVSequence(SDNode *N);
82 SDOperand BuildUDIVSequence(SDNode *N);
84 /// InstructionSelectBasicBlock - This callback is invoked by
85 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
86 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) {
88 // Select target instructions for the DAG.
89 DAG.setRoot(Select(DAG.getRoot()));
91 DAG.RemoveDeadNodes();
93 // Emit machine code to BB.
94 ScheduleAndEmitDAG(DAG);
97 virtual const char *getPassName() const {
98 return "PowerPC DAG->DAG Pattern Instruction Selection";
101 // Include the pieces autogenerated from the target description.
102 #include "PPC32GenDAGISel.inc"
107 /// getGlobalBaseReg - Output the instructions required to put the
108 /// base address to use for accessing globals into a register.
110 SDOperand PPC32DAGToDAGISel::getGlobalBaseReg() {
111 if (!GlobalBaseReg) {
112 // Insert the set of GlobalBaseReg into the first MBB of the function
113 MachineBasicBlock &FirstMBB = BB->getParent()->front();
114 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
115 SSARegMap *RegMap = BB->getParent()->getSSARegMap();
116 GlobalBaseReg = RegMap->createVirtualRegister(PPC32::GPRCRegisterClass);
117 BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
118 BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg);
120 return CurDAG->getRegister(GlobalBaseReg, MVT::i32);
124 // isIntImmediate - This method tests to see if a constant operand.
125 // If so Imm will receive the 32 bit value.
126 static bool isIntImmediate(SDNode *N, unsigned& Imm) {
127 if (N->getOpcode() == ISD::Constant) {
128 Imm = cast<ConstantSDNode>(N)->getValue();
134 // isOprShiftImm - Returns true if the specified operand is a shift opcode with
135 // a immediate shift count less than 32.
136 static bool isOprShiftImm(SDNode *N, unsigned& Opc, unsigned& SH) {
137 Opc = N->getOpcode();
138 return (Opc == ISD::SHL || Opc == ISD::SRL || Opc == ISD::SRA) &&
139 isIntImmediate(N->getOperand(1).Val, SH) && SH < 32;
142 // isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s with
143 // any number of 0s on either side. The 1s are allowed to wrap from LSB to
144 // MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 0x0F0F0000 is
145 // not, since all 1s are not contiguous.
146 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
147 if (isShiftedMask_32(Val)) {
148 // look for the first non-zero bit
149 MB = CountLeadingZeros_32(Val);
150 // look for the first zero bit after the run of ones
151 ME = CountLeadingZeros_32((Val - 1) ^ Val);
154 Val = ~Val; // invert mask
155 if (isShiftedMask_32(Val)) {
156 // effectively look for the first zero bit
157 ME = CountLeadingZeros_32(Val) - 1;
158 // effectively look for the first one bit after the run of zeros
159 MB = CountLeadingZeros_32((Val - 1) ^ Val) + 1;
167 // isRotateAndMask - Returns true if Mask and Shift can be folded in to a rotate
168 // and mask opcode and mask operation.
169 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask,
170 unsigned &SH, unsigned &MB, unsigned &ME) {
172 unsigned Indeterminant = ~0; // bit mask marking indeterminant results
173 unsigned Opcode = N->getOpcode();
174 if (N->getNumOperands() != 2 ||
175 !isIntImmediate(N->getOperand(1).Val, Shift) || (Shift > 31))
178 if (Opcode == ISD::SHL) {
179 // apply shift left to mask if it comes first
180 if (IsShiftMask) Mask = Mask << Shift;
181 // determine which bits are made indeterminant by shift
182 Indeterminant = ~(0xFFFFFFFFu << Shift);
183 } else if (Opcode == ISD::SRA || Opcode == ISD::SRL) {
184 // apply shift right to mask if it comes first
185 if (IsShiftMask) Mask = Mask >> Shift;
186 // determine which bits are made indeterminant by shift
187 Indeterminant = ~(0xFFFFFFFFu >> Shift);
188 // adjust for the left rotate
194 // if the mask doesn't intersect any Indeterminant bits
195 if (Mask && !(Mask & Indeterminant)) {
197 // make sure the mask is still a mask (wrap arounds may not be)
198 return isRunOfOnes(Mask, MB, ME);
203 // isOpcWithIntImmediate - This method tests to see if the node is a specific
204 // opcode and that it has a immediate integer right operand.
205 // If so Imm will receive the 32 bit value.
206 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
207 return N->getOpcode() == Opc && isIntImmediate(N->getOperand(1).Val, Imm);
210 // isOprNot - Returns true if the specified operand is an xor with immediate -1.
211 static bool isOprNot(SDNode *N) {
213 return isOpcWithIntImmediate(N, ISD::XOR, Imm) && (signed)Imm == -1;
216 // Immediate constant composers.
217 // Lo16 - grabs the lo 16 bits from a 32 bit constant.
218 // Hi16 - grabs the hi 16 bits from a 32 bit constant.
219 // HA16 - computes the hi bits required if the lo bits are add/subtracted in
221 static unsigned Lo16(unsigned x) { return x & 0x0000FFFF; }
222 static unsigned Hi16(unsigned x) { return Lo16(x >> 16); }
223 static unsigned HA16(unsigned x) { return Hi16((signed)x - (signed short)x); }
225 // isIntImmediate - This method tests to see if a constant operand.
226 // If so Imm will receive the 32 bit value.
227 static bool isIntImmediate(SDOperand N, unsigned& Imm) {
228 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
229 Imm = (unsigned)CN->getSignExtended();
235 /// SelectBitfieldInsert - turn an or of two masked values into
236 /// the rotate left word immediate then mask insert (rlwimi) instruction.
237 /// Returns true on success, false if the caller still needs to select OR.
239 /// Patterns matched:
240 /// 1. or shl, and 5. or and, and
241 /// 2. or and, shl 6. or shl, shr
242 /// 3. or shr, and 7. or shr, shl
244 SDNode *PPC32DAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
245 bool IsRotate = false;
246 unsigned TgtMask = 0xFFFFFFFF, InsMask = 0xFFFFFFFF, SH = 0;
249 SDOperand Op0 = N->getOperand(0);
250 SDOperand Op1 = N->getOperand(1);
252 unsigned Op0Opc = Op0.getOpcode();
253 unsigned Op1Opc = Op1.getOpcode();
255 // Verify that we have the correct opcodes
256 if (ISD::SHL != Op0Opc && ISD::SRL != Op0Opc && ISD::AND != Op0Opc)
258 if (ISD::SHL != Op1Opc && ISD::SRL != Op1Opc && ISD::AND != Op1Opc)
261 // Generate Mask value for Target
262 if (isIntImmediate(Op0.getOperand(1), Value)) {
264 case ISD::SHL: TgtMask <<= Value; break;
265 case ISD::SRL: TgtMask >>= Value; break;
266 case ISD::AND: TgtMask &= Value; break;
272 // Generate Mask value for Insert
273 if (!isIntImmediate(Op1.getOperand(1), Value))
280 if (Op0Opc == ISD::SRL) IsRotate = true;
286 if (Op0Opc == ISD::SHL) IsRotate = true;
293 // If both of the inputs are ANDs and one of them has a logical shift by
294 // constant as its input, make that AND the inserted value so that we can
295 // combine the shift into the rotate part of the rlwimi instruction
296 bool IsAndWithShiftOp = false;
297 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
298 if (Op1.getOperand(0).getOpcode() == ISD::SHL ||
299 Op1.getOperand(0).getOpcode() == ISD::SRL) {
300 if (isIntImmediate(Op1.getOperand(0).getOperand(1), Value)) {
301 SH = Op1.getOperand(0).getOpcode() == ISD::SHL ? Value : 32 - Value;
302 IsAndWithShiftOp = true;
304 } else if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
305 Op0.getOperand(0).getOpcode() == ISD::SRL) {
306 if (isIntImmediate(Op0.getOperand(0).getOperand(1), Value)) {
308 std::swap(TgtMask, InsMask);
309 SH = Op1.getOperand(0).getOpcode() == ISD::SHL ? Value : 32 - Value;
310 IsAndWithShiftOp = true;
315 // Verify that the Target mask and Insert mask together form a full word mask
316 // and that the Insert mask is a run of set bits (which implies both are runs
317 // of set bits). Given that, Select the arguments and generate the rlwimi
320 if (((TgtMask & InsMask) == 0) && isRunOfOnes(InsMask, MB, ME)) {
321 bool fullMask = (TgtMask ^ InsMask) == 0xFFFFFFFF;
322 bool Op0IsAND = Op0Opc == ISD::AND;
323 // Check for rotlwi / rotrwi here, a special case of bitfield insert
324 // where both bitfield halves are sourced from the same value.
325 if (IsRotate && fullMask &&
326 N->getOperand(0).getOperand(0) == N->getOperand(1).getOperand(0)) {
327 Op0 = CurDAG->getTargetNode(PPC::RLWINM, MVT::i32,
328 Select(N->getOperand(0).getOperand(0)),
329 getI32Imm(SH), getI32Imm(0), getI32Imm(31));
332 SDOperand Tmp1 = (Op0IsAND && fullMask) ? Select(Op0.getOperand(0))
334 SDOperand Tmp2 = IsAndWithShiftOp ? Select(Op1.getOperand(0).getOperand(0))
335 : Select(Op1.getOperand(0));
336 Op0 = CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Tmp1, Tmp2,
337 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
343 // SelectIntImmediateExpr - Choose code for integer operations with an immediate
345 SDNode *PPC32DAGToDAGISel::SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
346 unsigned OCHi, unsigned OCLo,
349 // Check to make sure this is a constant.
350 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(RHS);
351 // Exit if not a constant.
353 // Extract immediate.
354 unsigned C = (unsigned)CN->getValue();
355 // Negate if required (ISD::SUB).
357 // Get the hi and lo portions of constant.
358 unsigned Hi = IsArithmetic ? HA16(C) : Hi16(C);
359 unsigned Lo = Lo16(C);
361 // If two instructions are needed and usage indicates it would be better to
362 // load immediate into a register, bail out.
363 if (Hi && Lo && CN->use_size() > 2) return false;
365 // Select the first operand.
366 SDOperand Opr0 = Select(LHS);
368 if (Lo) // Add in the lo-part.
369 Opr0 = CurDAG->getTargetNode(OCLo, MVT::i32, Opr0, getI32Imm(Lo));
370 if (Hi) // Add in the hi-part.
371 Opr0 = CurDAG->getTargetNode(OCHi, MVT::i32, Opr0, getI32Imm(Hi));
375 /// SelectAddr - Given the specified address, return the two operands for a
376 /// load/store instruction, and return true if it should be an indexed [r+r]
378 bool PPC32DAGToDAGISel::SelectAddr(SDOperand Addr, SDOperand &Op1,
381 if (Addr.getOpcode() == ISD::ADD) {
382 if (isIntImmediate(Addr.getOperand(1), imm) && isInt16(imm)) {
383 Op1 = getI32Imm(Lo16(imm));
384 if (FrameIndexSDNode *FI =
385 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
387 Op2 = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
389 Op2 = Select(Addr.getOperand(0));
393 Op1 = Select(Addr.getOperand(0));
394 Op2 = Select(Addr.getOperand(1));
395 return true; // [r+r]
399 // Now check if we're dealing with a global, and whether or not we should emit
400 // an optimized load or store for statics.
401 if (GlobalAddressSDNode *GN = dyn_cast<GlobalAddressSDNode>(Addr)) {
402 GlobalValue *GV = GN->getGlobal();
403 if (!GV->hasWeakLinkage() && !GV->isExternal()) {
404 Op1 = CurDAG->getTargetGlobalAddress(GV, MVT::i32);
406 Op2 = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(),
409 Op2 = CurDAG->getTargetNode(PPC::LIS, MVT::i32, Op1);
412 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Addr)) {
414 Op2 = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
416 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Addr)) {
419 Op2 = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(),Op1);
421 Op2 = CurDAG->getTargetNode(PPC::LIS, MVT::i32, Op1);
429 /// SelectCC - Select a comparison of the specified values with the specified
430 /// condition code, returning the CR# of the expression.
431 SDOperand PPC32DAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS,
433 // Always select the LHS.
436 // Use U to determine whether the SETCC immediate range is signed or not.
437 if (MVT::isInteger(LHS.getValueType())) {
438 bool U = ISD::isUnsignedIntSetCC(CC);
440 if (isIntImmediate(RHS, Imm) &&
441 ((U && isUInt16(Imm)) || (!U && isInt16(Imm))))
442 return CurDAG->getTargetNode(U ? PPC::CMPLWI : PPC::CMPWI, MVT::i32,
443 LHS, getI32Imm(Lo16(Imm)));
444 return CurDAG->getTargetNode(U ? PPC::CMPLW : PPC::CMPW, MVT::i32,
447 return CurDAG->getTargetNode(PPC::FCMPU, MVT::i32, LHS, Select(RHS));
451 /// getBCCForSetCC - Returns the PowerPC condition branch mnemonic corresponding
453 static unsigned getBCCForSetCC(ISD::CondCode CC) {
455 default: assert(0 && "Unknown condition!"); abort();
456 case ISD::SETEQ: return PPC::BEQ;
457 case ISD::SETNE: return PPC::BNE;
459 case ISD::SETLT: return PPC::BLT;
461 case ISD::SETLE: return PPC::BLE;
463 case ISD::SETGT: return PPC::BGT;
465 case ISD::SETGE: return PPC::BGE;
470 /// getCRIdxForSetCC - Return the index of the condition register field
471 /// associated with the SetCC condition, and whether or not the field is
472 /// treated as inverted. That is, lt = 0; ge = 0 inverted.
473 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool& Inv) {
475 default: assert(0 && "Unknown condition!"); abort();
477 case ISD::SETLT: Inv = false; return 0;
479 case ISD::SETGE: Inv = true; return 0;
481 case ISD::SETGT: Inv = false; return 1;
483 case ISD::SETLE: Inv = true; return 1;
484 case ISD::SETEQ: Inv = false; return 2;
485 case ISD::SETNE: Inv = true; return 2;
490 // Structure used to return the necessary information to codegen an SDIV as
493 int m; // magic number
494 int s; // shift amount
498 unsigned int m; // magic number
499 int a; // add indicator
500 int s; // shift amount
503 /// magic - calculate the magic numbers required to codegen an integer sdiv as
504 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
506 static struct ms magic(int d) {
508 unsigned int ad, anc, delta, q1, r1, q2, r2, t;
509 const unsigned int two31 = 0x80000000U;
513 t = two31 + ((unsigned int)d >> 31);
514 anc = t - 1 - t%ad; // absolute value of nc
515 p = 31; // initialize p
516 q1 = two31/anc; // initialize q1 = 2p/abs(nc)
517 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc))
518 q2 = two31/ad; // initialize q2 = 2p/abs(d)
519 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d))
522 q1 = 2*q1; // update q1 = 2p/abs(nc)
523 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
524 if (r1 >= anc) { // must be unsigned comparison
528 q2 = 2*q2; // update q2 = 2p/abs(d)
529 r2 = 2*r2; // update r2 = rem(2p/abs(d))
530 if (r2 >= ad) { // must be unsigned comparison
535 } while (q1 < delta || (q1 == delta && r1 == 0));
538 if (d < 0) mag.m = -mag.m; // resulting magic number
539 mag.s = p - 32; // resulting shift
543 /// magicu - calculate the magic numbers required to codegen an integer udiv as
544 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
545 static struct mu magicu(unsigned d)
548 unsigned int nc, delta, q1, r1, q2, r2;
550 magu.a = 0; // initialize "add" indicator
552 p = 31; // initialize p
553 q1 = 0x80000000/nc; // initialize q1 = 2p/nc
554 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc)
555 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d
556 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d)
559 if (r1 >= nc - r1 ) {
560 q1 = 2*q1 + 1; // update q1
561 r1 = 2*r1 - nc; // update r1
564 q1 = 2*q1; // update q1
565 r1 = 2*r1; // update r1
567 if (r2 + 1 >= d - r2) {
568 if (q2 >= 0x7FFFFFFF) magu.a = 1;
569 q2 = 2*q2 + 1; // update q2
570 r2 = 2*r2 + 1 - d; // update r2
573 if (q2 >= 0x80000000) magu.a = 1;
574 q2 = 2*q2; // update q2
575 r2 = 2*r2 + 1; // update r2
578 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
579 magu.m = q2 + 1; // resulting magic number
580 magu.s = p - 32; // resulting shift
584 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
585 /// return a DAG expression to select that will generate the same value by
586 /// multiplying by a magic number. See:
587 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
588 SDOperand PPC32DAGToDAGISel::BuildSDIVSequence(SDNode *N) {
589 int d = (int)cast<ConstantSDNode>(N->getOperand(1))->getValue();
590 ms magics = magic(d);
591 // Multiply the numerator (operand 0) by the magic value
592 SDOperand Q = CurDAG->getNode(ISD::MULHS, MVT::i32, N->getOperand(0),
593 CurDAG->getConstant(magics.m, MVT::i32));
594 // If d > 0 and m < 0, add the numerator
595 if (d > 0 && magics.m < 0)
596 Q = CurDAG->getNode(ISD::ADD, MVT::i32, Q, N->getOperand(0));
597 // If d < 0 and m > 0, subtract the numerator.
598 if (d < 0 && magics.m > 0)
599 Q = CurDAG->getNode(ISD::SUB, MVT::i32, Q, N->getOperand(0));
600 // Shift right algebraic if shift value is nonzero
602 Q = CurDAG->getNode(ISD::SRA, MVT::i32, Q,
603 CurDAG->getConstant(magics.s, MVT::i32));
604 // Extract the sign bit and add it to the quotient
606 CurDAG->getNode(ISD::SRL, MVT::i32, Q, CurDAG->getConstant(31, MVT::i32));
607 return CurDAG->getNode(ISD::ADD, MVT::i32, Q, T);
610 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
611 /// return a DAG expression to select that will generate the same value by
612 /// multiplying by a magic number. See:
613 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
614 SDOperand PPC32DAGToDAGISel::BuildUDIVSequence(SDNode *N) {
615 unsigned d = (unsigned)cast<ConstantSDNode>(N->getOperand(1))->getValue();
616 mu magics = magicu(d);
617 // Multiply the numerator (operand 0) by the magic value
618 SDOperand Q = CurDAG->getNode(ISD::MULHU, MVT::i32, N->getOperand(0),
619 CurDAG->getConstant(magics.m, MVT::i32));
621 return CurDAG->getNode(ISD::SRL, MVT::i32, Q,
622 CurDAG->getConstant(magics.s, MVT::i32));
624 SDOperand NPQ = CurDAG->getNode(ISD::SUB, MVT::i32, N->getOperand(0), Q);
625 NPQ = CurDAG->getNode(ISD::SRL, MVT::i32, NPQ,
626 CurDAG->getConstant(1, MVT::i32));
627 NPQ = CurDAG->getNode(ISD::ADD, MVT::i32, NPQ, Q);
628 return CurDAG->getNode(ISD::SRL, MVT::i32, NPQ,
629 CurDAG->getConstant(magics.s-1, MVT::i32));
633 // Select - Convert the specified operand from a target-independent to a
634 // target-specific node if it hasn't already been changed.
635 SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
637 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
638 N->getOpcode() < PPCISD::FIRST_NUMBER)
639 return Op; // Already selected.
641 // If this has already been converted, use it.
642 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
643 if (CGMI != CodeGenMap.end()) return CGMI->second;
645 switch (N->getOpcode()) {
647 case ISD::TokenFactor: {
649 if (N->getNumOperands() == 2) {
650 SDOperand Op0 = Select(N->getOperand(0));
651 SDOperand Op1 = Select(N->getOperand(1));
652 New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Op0, Op1);
654 std::vector<SDOperand> Ops;
655 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
656 Ops.push_back(Select(N->getOperand(i)));
657 New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Ops);
660 if (!N->hasOneUse()) CodeGenMap[Op] = New;
663 case ISD::CopyFromReg: {
664 SDOperand Chain = Select(N->getOperand(0));
665 if (Chain == N->getOperand(0)) return Op; // No change
666 SDOperand New = CurDAG->getCopyFromReg(Chain,
667 cast<RegisterSDNode>(N->getOperand(1))->getReg(), N->getValueType(0));
668 return New.getValue(Op.ResNo);
670 case ISD::CopyToReg: {
671 SDOperand Chain = Select(N->getOperand(0));
672 SDOperand Reg = N->getOperand(1);
673 SDOperand Val = Select(N->getOperand(2));
674 SDOperand New = CurDAG->getNode(ISD::CopyToReg, MVT::Other,
676 if (!N->hasOneUse()) CodeGenMap[Op] = New;
680 if (N->getValueType(0) == MVT::i32)
681 CurDAG->SelectNodeTo(N, PPC::IMPLICIT_DEF_GPR, MVT::i32);
683 CurDAG->SelectNodeTo(N, PPC::IMPLICIT_DEF_FP, N->getValueType(0));
684 return SDOperand(N, 0);
685 case ISD::FrameIndex: {
686 int FI = cast<FrameIndexSDNode>(N)->getIndex();
687 CurDAG->SelectNodeTo(N, PPC::ADDI, MVT::i32,
688 CurDAG->getTargetFrameIndex(FI, MVT::i32),
690 return SDOperand(N, 0);
692 case ISD::ConstantPool: {
693 Constant *C = cast<ConstantPoolSDNode>(N)->get();
694 SDOperand Tmp, CPI = CurDAG->getTargetConstantPool(C, MVT::i32);
696 Tmp = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(),CPI);
698 Tmp = CurDAG->getTargetNode(PPC::LIS, MVT::i32, CPI);
699 CurDAG->SelectNodeTo(N, PPC::LA, MVT::i32, Tmp, CPI);
700 return SDOperand(N, 0);
702 case ISD::GlobalAddress: {
703 GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
705 SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i32);
707 Tmp = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(), GA);
709 Tmp = CurDAG->getTargetNode(PPC::LIS, MVT::i32, GA);
711 if (GV->hasWeakLinkage() || GV->isExternal())
712 CurDAG->SelectNodeTo(N, PPC::LWZ, MVT::i32, GA, Tmp);
714 CurDAG->SelectNodeTo(N, PPC::LA, MVT::i32, Tmp, GA);
715 return SDOperand(N, 0);
717 case ISD::DYNAMIC_STACKALLOC: {
718 // FIXME: We are currently ignoring the requested alignment for handling
719 // greater than the stack alignment. This will need to be revisited at some
720 // point. Align = N.getOperand(2);
721 if (!isa<ConstantSDNode>(N->getOperand(2)) ||
722 cast<ConstantSDNode>(N->getOperand(2))->getValue() != 0) {
723 std::cerr << "Cannot allocate stack object with greater alignment than"
724 << " the stack alignment yet!";
727 SDOperand Chain = Select(N->getOperand(0));
728 SDOperand Amt = Select(N->getOperand(1));
730 SDOperand R1Reg = CurDAG->getRegister(PPC::R1, MVT::i32);
732 SDOperand R1Val = CurDAG->getCopyFromReg(Chain, PPC::R1, MVT::i32);
733 Chain = R1Val.getValue(1);
735 // Subtract the amount (guaranteed to be a multiple of the stack alignment)
736 // from the stack pointer, giving us the result pointer.
737 SDOperand Result = CurDAG->getTargetNode(PPC::SUBF, MVT::i32, Amt, R1Val);
739 // Copy this result back into R1.
740 Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, Chain, R1Reg, Result);
742 // Copy this result back out of R1 to make sure we're not using the stack
743 // space without decrementing the stack pointer.
744 Result = CurDAG->getCopyFromReg(Chain, PPC::R1, MVT::i32);
746 // Finally, replace the DYNAMIC_STACKALLOC with the copyfromreg.
747 CodeGenMap[Op.getValue(0)] = Result;
748 CodeGenMap[Op.getValue(1)] = Result.getValue(1);
749 return SDOperand(Result.Val, Op.ResNo);
752 CurDAG->SelectNodeTo(N, PPC::FSEL, N->getValueType(0),
753 Select(N->getOperand(0)),
754 Select(N->getOperand(1)),
755 Select(N->getOperand(2)));
756 return SDOperand(N, 0);
758 CurDAG->SelectNodeTo(N, PPC::FCFID, N->getValueType(0),
759 Select(N->getOperand(0)));
760 return SDOperand(N, 0);
762 CurDAG->SelectNodeTo(N, PPC::FCTIDZ, N->getValueType(0),
763 Select(N->getOperand(0)));
764 return SDOperand(N, 0);
766 CurDAG->SelectNodeTo(N, PPC::FCTIWZ, N->getValueType(0),
767 Select(N->getOperand(0)));
768 return SDOperand(N, 0);
770 MVT::ValueType Ty = N->getValueType(0);
771 if (!NoExcessFPPrecision) { // Match FMA ops
772 if (N->getOperand(0).getOpcode() == ISD::FMUL &&
773 N->getOperand(0).Val->hasOneUse()) {
774 ++FusedFP; // Statistic
775 CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FMADD : PPC::FMADDS, Ty,
776 Select(N->getOperand(0).getOperand(0)),
777 Select(N->getOperand(0).getOperand(1)),
778 Select(N->getOperand(1)));
779 return SDOperand(N, 0);
780 } else if (N->getOperand(1).getOpcode() == ISD::FMUL &&
781 N->getOperand(1).hasOneUse()) {
782 ++FusedFP; // Statistic
783 CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FMADD : PPC::FMADDS, Ty,
784 Select(N->getOperand(1).getOperand(0)),
785 Select(N->getOperand(1).getOperand(1)),
786 Select(N->getOperand(0)));
787 return SDOperand(N, 0);
791 CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FADD : PPC::FADDS, Ty,
792 Select(N->getOperand(0)), Select(N->getOperand(1)));
793 return SDOperand(N, 0);
796 MVT::ValueType Ty = N->getValueType(0);
798 if (!NoExcessFPPrecision) { // Match FMA ops
799 if (N->getOperand(0).getOpcode() == ISD::FMUL &&
800 N->getOperand(0).Val->hasOneUse()) {
801 ++FusedFP; // Statistic
802 CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FMSUB : PPC::FMSUBS, Ty,
803 Select(N->getOperand(0).getOperand(0)),
804 Select(N->getOperand(0).getOperand(1)),
805 Select(N->getOperand(1)));
806 return SDOperand(N, 0);
807 } else if (N->getOperand(1).getOpcode() == ISD::FMUL &&
808 N->getOperand(1).Val->hasOneUse()) {
809 ++FusedFP; // Statistic
810 CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FNMSUB : PPC::FNMSUBS, Ty,
811 Select(N->getOperand(1).getOperand(0)),
812 Select(N->getOperand(1).getOperand(1)),
813 Select(N->getOperand(0)));
814 return SDOperand(N, 0);
817 CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FSUB : PPC::FSUBS, Ty,
818 Select(N->getOperand(0)),
819 Select(N->getOperand(1)));
820 return SDOperand(N, 0);
824 if (isIntImmediate(N->getOperand(1), Imm)) {
825 if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
827 CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
828 Select(N->getOperand(0)),
829 getI32Imm(Log2_32(Imm)));
830 CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
831 Op.getValue(0), Op.getValue(1));
832 return SDOperand(N, 0);
833 } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
835 CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
836 Select(N->getOperand(0)),
837 getI32Imm(Log2_32(-Imm)));
839 CurDAG->getTargetNode(PPC::ADDZE, MVT::i32, Op.getValue(0),
841 CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
842 return SDOperand(N, 0);
844 SDOperand Result = Select(BuildSDIVSequence(N));
845 CodeGenMap[Op] = Result;
850 // Other cases are autogenerated.
854 // If this is a divide by constant, we can emit code using some magic
855 // constants to implement it as a multiply instead.
857 if (isIntImmediate(N->getOperand(1), Imm) && Imm) {
858 SDOperand Result = Select(BuildUDIVSequence(N));
859 CodeGenMap[Op] = Result;
863 // Other cases are autogenerated.
868 // If this is an and of a value rotated between 0 and 31 bits and then and'd
869 // with a mask, emit rlwinm
870 if (isIntImmediate(N->getOperand(1), Imm) && (isShiftedMask_32(Imm) ||
871 isShiftedMask_32(~Imm))) {
874 if (isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB, ME)) {
875 Val = Select(N->getOperand(0).getOperand(0));
877 Val = Select(N->getOperand(0));
878 isRunOfOnes(Imm, MB, ME);
881 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Val, getI32Imm(SH),
882 getI32Imm(MB), getI32Imm(ME));
883 return SDOperand(N, 0);
886 // Other cases are autogenerated.
890 if (SDNode *I = SelectBitfieldInsert(N))
891 return CodeGenMap[Op] = SDOperand(I, 0);
893 if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0),
895 PPC::ORIS, PPC::ORI))
896 return CodeGenMap[Op] = SDOperand(I, 0);
898 // Other cases are autogenerated.
901 unsigned Imm, SH, MB, ME;
902 if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
903 isRotateAndMask(N, Imm, true, SH, MB, ME))
904 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32,
905 Select(N->getOperand(0).getOperand(0)),
906 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
907 else if (isIntImmediate(N->getOperand(1), Imm))
908 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Select(N->getOperand(0)),
909 getI32Imm(Imm), getI32Imm(0), getI32Imm(31-Imm));
911 CurDAG->SelectNodeTo(N, PPC::SLW, MVT::i32, Select(N->getOperand(0)),
912 Select(N->getOperand(1)));
913 return SDOperand(N, 0);
916 unsigned Imm, SH, MB, ME;
917 if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
918 isRotateAndMask(N, Imm, true, SH, MB, ME))
919 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32,
920 Select(N->getOperand(0).getOperand(0)),
921 getI32Imm(SH & 0x1F), getI32Imm(MB), getI32Imm(ME));
922 else if (isIntImmediate(N->getOperand(1), Imm))
923 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Select(N->getOperand(0)),
924 getI32Imm((32-Imm) & 0x1F), getI32Imm(Imm),
927 CurDAG->SelectNodeTo(N, PPC::SRW, MVT::i32, Select(N->getOperand(0)),
928 Select(N->getOperand(1)));
929 return SDOperand(N, 0);
932 unsigned Imm, SH, MB, ME;
933 if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
934 isRotateAndMask(N, Imm, true, SH, MB, ME))
935 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32,
936 Select(N->getOperand(0).getOperand(0)),
937 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
938 else if (isIntImmediate(N->getOperand(1), Imm))
939 CurDAG->SelectNodeTo(N, PPC::SRAWI, MVT::i32, Select(N->getOperand(0)),
942 CurDAG->SelectNodeTo(N, PPC::SRAW, MVT::i32, Select(N->getOperand(0)),
943 Select(N->getOperand(1)));
944 return SDOperand(N, 0);
947 unsigned Opc = N->getValueType(0) == MVT::f32 ? PPC::FMULS : PPC::FMUL;
948 CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), Select(N->getOperand(0)),
949 Select(N->getOperand(1)));
950 return SDOperand(N, 0);
953 unsigned Opc = N->getValueType(0) == MVT::f32 ? PPC::FDIVS : PPC::FDIV;
954 CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), Select(N->getOperand(0)),
955 Select(N->getOperand(1)));
956 return SDOperand(N, 0);
959 CurDAG->SelectNodeTo(N, PPC::FABS, N->getValueType(0),
960 Select(N->getOperand(0)));
961 return SDOperand(N, 0);
963 assert(MVT::f64 == N->getValueType(0) &&
964 MVT::f32 == N->getOperand(0).getValueType() && "Illegal FP_EXTEND");
965 // We need to emit an FMR to make sure that the result has the right value
967 CurDAG->SelectNodeTo(N, PPC::FMR, MVT::f64, Select(N->getOperand(0)));
968 return SDOperand(N, 0);
970 assert(MVT::f32 == N->getValueType(0) &&
971 MVT::f64 == N->getOperand(0).getValueType() && "Illegal FP_ROUND");
972 CurDAG->SelectNodeTo(N, PPC::FRSP, MVT::f32, Select(N->getOperand(0)));
973 return SDOperand(N, 0);
975 SDOperand Val = Select(N->getOperand(0));
976 MVT::ValueType Ty = N->getValueType(0);
977 if (Val.Val->hasOneUse()) {
979 switch (Val.isTargetOpcode() ? Val.getTargetOpcode() : 0) {
980 default: Opc = 0; break;
981 case PPC::FABS: Opc = PPC::FNABS; break;
982 case PPC::FMADD: Opc = PPC::FNMADD; break;
983 case PPC::FMADDS: Opc = PPC::FNMADDS; break;
984 case PPC::FMSUB: Opc = PPC::FNMSUB; break;
985 case PPC::FMSUBS: Opc = PPC::FNMSUBS; break;
987 // If we inverted the opcode, then emit the new instruction with the
988 // inverted opcode and the original instruction's operands. Otherwise,
989 // fall through and generate a fneg instruction.
991 if (PPC::FNABS == Opc)
992 CurDAG->SelectNodeTo(N, Opc, Ty, Val.getOperand(0));
994 CurDAG->SelectNodeTo(N, Opc, Ty, Val.getOperand(0),
995 Val.getOperand(1), Val.getOperand(2));
996 return SDOperand(N, 0);
999 CurDAG->SelectNodeTo(N, PPC::FNEG, Ty, Val);
1000 return SDOperand(N, 0);
1003 MVT::ValueType Ty = N->getValueType(0);
1004 CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FSQRT : PPC::FSQRTS, Ty,
1005 Select(N->getOperand(0)));
1006 return SDOperand(N, 0);
1009 case ISD::ADD_PARTS: {
1010 SDOperand LHSL = Select(N->getOperand(0));
1011 SDOperand LHSH = Select(N->getOperand(1));
1014 bool ME = false, ZE = false;
1015 if (isIntImmediate(N->getOperand(3), Imm)) {
1016 ME = (signed)Imm == -1;
1020 std::vector<SDOperand> Result;
1021 SDOperand CarryFromLo;
1022 if (isIntImmediate(N->getOperand(2), Imm) &&
1023 ((signed)Imm >= -32768 || (signed)Imm < 32768)) {
1024 // Codegen the low 32 bits of the add. Interestingly, there is no
1025 // shifted form of add immediate carrying.
1026 CarryFromLo = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
1027 LHSL, getI32Imm(Imm));
1029 CarryFromLo = CurDAG->getTargetNode(PPC::ADDC, MVT::i32, MVT::Flag,
1030 LHSL, Select(N->getOperand(2)));
1032 CarryFromLo = CarryFromLo.getValue(1);
1034 // Codegen the high 32 bits, adding zero, minus one, or the full value
1035 // along with the carry flag produced by addc/addic.
1038 ResultHi = CurDAG->getTargetNode(PPC::ADDZE, MVT::i32, LHSH, CarryFromLo);
1040 ResultHi = CurDAG->getTargetNode(PPC::ADDME, MVT::i32, LHSH, CarryFromLo);
1042 ResultHi = CurDAG->getTargetNode(PPC::ADDE, MVT::i32, LHSH,
1043 Select(N->getOperand(3)), CarryFromLo);
1044 Result.push_back(CarryFromLo.getValue(0));
1045 Result.push_back(ResultHi);
1047 CodeGenMap[Op.getValue(0)] = Result[0];
1048 CodeGenMap[Op.getValue(1)] = Result[1];
1049 return Result[Op.ResNo];
1051 case ISD::SUB_PARTS: {
1052 SDOperand LHSL = Select(N->getOperand(0));
1053 SDOperand LHSH = Select(N->getOperand(1));
1054 SDOperand RHSL = Select(N->getOperand(2));
1055 SDOperand RHSH = Select(N->getOperand(3));
1057 std::vector<SDOperand> Result;
1058 Result.push_back(CurDAG->getTargetNode(PPC::SUBFC, MVT::i32, MVT::Flag,
1060 Result.push_back(CurDAG->getTargetNode(PPC::SUBFE, MVT::i32, RHSH, LHSH,
1061 Result[0].getValue(1)));
1062 CodeGenMap[Op.getValue(0)] = Result[0];
1063 CodeGenMap[Op.getValue(1)] = Result[1];
1064 return Result[Op.ResNo];
1070 case ISD::SEXTLOAD: {
1072 bool isIdx = SelectAddr(N->getOperand(1), Op1, Op2);
1074 MVT::ValueType TypeBeingLoaded = (N->getOpcode() == ISD::LOAD) ?
1075 N->getValueType(0) : cast<VTSDNode>(N->getOperand(3))->getVT();
1077 switch (TypeBeingLoaded) {
1078 default: N->dump(); assert(0 && "Cannot load this type!");
1080 case MVT::i8: Opc = isIdx ? PPC::LBZX : PPC::LBZ; break;
1082 if (N->getOpcode() == ISD::SEXTLOAD) { // SEXT load?
1083 Opc = isIdx ? PPC::LHAX : PPC::LHA;
1085 Opc = isIdx ? PPC::LHZX : PPC::LHZ;
1088 case MVT::i32: Opc = isIdx ? PPC::LWZX : PPC::LWZ; break;
1089 case MVT::f32: Opc = isIdx ? PPC::LFSX : PPC::LFS; break;
1090 case MVT::f64: Opc = isIdx ? PPC::LFDX : PPC::LFD; break;
1093 CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
1094 Op1, Op2, Select(N->getOperand(0)));
1095 return SDOperand(N, Op.ResNo);
1098 case ISD::TRUNCSTORE:
1100 SDOperand AddrOp1, AddrOp2;
1101 bool isIdx = SelectAddr(N->getOperand(2), AddrOp1, AddrOp2);
1104 if (N->getOpcode() == ISD::STORE) {
1105 switch (N->getOperand(1).getValueType()) {
1106 default: assert(0 && "unknown Type in store");
1107 case MVT::i32: Opc = isIdx ? PPC::STWX : PPC::STW; break;
1108 case MVT::f64: Opc = isIdx ? PPC::STFDX : PPC::STFD; break;
1109 case MVT::f32: Opc = isIdx ? PPC::STFSX : PPC::STFS; break;
1111 } else { //ISD::TRUNCSTORE
1112 switch(cast<VTSDNode>(N->getOperand(4))->getVT()) {
1113 default: assert(0 && "unknown Type in store");
1114 case MVT::i8: Opc = isIdx ? PPC::STBX : PPC::STB; break;
1115 case MVT::i16: Opc = isIdx ? PPC::STHX : PPC::STH; break;
1119 CurDAG->SelectNodeTo(N, Opc, MVT::Other, Select(N->getOperand(1)),
1120 AddrOp1, AddrOp2, Select(N->getOperand(0)));
1121 return SDOperand(N, 0);
1126 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
1127 if (isIntImmediate(N->getOperand(1), Imm)) {
1128 // We can codegen setcc op, imm very efficiently compared to a brcond.
1129 // Check for those cases here.
1132 SDOperand Op = Select(N->getOperand(0));
1134 default: assert(0 && "Unhandled SetCC condition"); abort();
1136 Op = CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op);
1137 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(27),
1138 getI32Imm(5), getI32Imm(31));
1141 SDOperand AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
1142 Op, getI32Imm(~0U));
1143 CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, AD.getValue(1));
1147 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(1),
1148 getI32Imm(31), getI32Imm(31));
1151 SDOperand T = CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op);
1152 T = CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op);;
1153 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, T, getI32Imm(1),
1154 getI32Imm(31), getI32Imm(31));
1158 return SDOperand(N, 0);
1159 } else if (Imm == ~0U) { // setcc op, -1
1160 SDOperand Op = Select(N->getOperand(0));
1162 default: assert(0 && "Unhandled SetCC condition"); abort();
1164 Op = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
1166 CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
1167 CurDAG->getTargetNode(PPC::LI, MVT::i32,
1172 Op = CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op);
1173 SDOperand AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
1174 Op, getI32Imm(~0U));
1175 CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, AD.getValue(1));
1179 SDOperand AD = CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op,
1181 SDOperand AN = CurDAG->getTargetNode(PPC::AND, MVT::i32, AD, Op);
1182 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, AN, getI32Imm(1),
1183 getI32Imm(31), getI32Imm(31));
1187 Op = CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Op, getI32Imm(1),
1188 getI32Imm(31), getI32Imm(31));
1189 CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, getI32Imm(1));
1192 return SDOperand(N, 0);
1197 unsigned Idx = getCRIdxForSetCC(CC, Inv);
1198 SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
1201 // Force the ccreg into CR7.
1202 SDOperand CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
1204 std::vector<MVT::ValueType> VTs;
1205 VTs.push_back(MVT::Other);
1206 VTs.push_back(MVT::Flag); // NONSTANDARD CopyToReg node: defines a flag
1207 std::vector<SDOperand> Ops;
1208 Ops.push_back(CurDAG->getEntryNode());
1209 Ops.push_back(CR7Reg);
1210 Ops.push_back(CCReg);
1211 CCReg = CurDAG->getNode(ISD::CopyToReg, VTs, Ops).getValue(1);
1213 if (TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor())
1214 IntCR = CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg, CCReg);
1216 IntCR = CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg);
1219 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, IntCR,
1220 getI32Imm(32-(3-Idx)), getI32Imm(31), getI32Imm(31));
1223 CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, IntCR,
1224 getI32Imm(32-(3-Idx)), getI32Imm(31),getI32Imm(31));
1225 CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
1228 return SDOperand(N, 0);
1231 case ISD::SELECT_CC: {
1232 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1234 // handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
1235 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1236 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
1237 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
1238 if (N1C->isNullValue() && N3C->isNullValue() &&
1239 N2C->getValue() == 1ULL && CC == ISD::SETNE) {
1240 SDOperand LHS = Select(N->getOperand(0));
1242 CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
1243 LHS, getI32Imm(~0U));
1244 CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, Tmp, LHS,
1246 return SDOperand(N, 0);
1249 SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
1250 unsigned BROpc = getBCCForSetCC(CC);
1252 bool isFP = MVT::isFloatingPoint(N->getValueType(0));
1253 unsigned SelectCCOp = isFP ? PPC::SELECT_CC_FP : PPC::SELECT_CC_Int;
1254 CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), CCReg,
1255 Select(N->getOperand(2)), Select(N->getOperand(3)),
1257 return SDOperand(N, 0);
1260 case ISD::CALLSEQ_START:
1261 case ISD::CALLSEQ_END: {
1262 unsigned Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
1263 unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
1264 PPC::ADJCALLSTACKDOWN : PPC::ADJCALLSTACKUP;
1265 CurDAG->SelectNodeTo(N, Opc, MVT::Other,
1266 getI32Imm(Amt), Select(N->getOperand(0)));
1267 return SDOperand(N, 0);
1270 case ISD::TAILCALL: {
1271 SDOperand Chain = Select(N->getOperand(0));
1273 unsigned CallOpcode;
1274 std::vector<SDOperand> CallOperands;
1276 if (GlobalAddressSDNode *GASD =
1277 dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) {
1278 CallOpcode = PPC::CALLpcrel;
1279 CallOperands.push_back(CurDAG->getTargetGlobalAddress(GASD->getGlobal(),
1281 } else if (ExternalSymbolSDNode *ESSDN =
1282 dyn_cast<ExternalSymbolSDNode>(N->getOperand(1))) {
1283 CallOpcode = PPC::CALLpcrel;
1284 CallOperands.push_back(N->getOperand(1));
1286 // Copy the callee address into the CTR register.
1287 SDOperand Callee = Select(N->getOperand(1));
1288 Chain = CurDAG->getTargetNode(PPC::MTCTR, MVT::Other, Callee, Chain);
1290 // Copy the callee address into R12 on darwin.
1291 SDOperand R12 = CurDAG->getRegister(PPC::R12, MVT::i32);
1292 Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, Chain, R12, Callee);
1294 CallOperands.push_back(getI32Imm(20)); // Information to encode indcall
1295 CallOperands.push_back(getI32Imm(0)); // Information to encode indcall
1296 CallOperands.push_back(R12);
1297 CallOpcode = PPC::CALLindirect;
1300 unsigned GPR_idx = 0, FPR_idx = 0;
1301 static const unsigned GPR[] = {
1302 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1303 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1305 static const unsigned FPR[] = {
1306 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1307 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1310 SDOperand InFlag; // Null incoming flag value.
1312 for (unsigned i = 2, e = N->getNumOperands(); i != e; ++i) {
1313 unsigned DestReg = 0;
1314 MVT::ValueType RegTy = N->getOperand(i).getValueType();
1315 if (RegTy == MVT::i32) {
1316 assert(GPR_idx < 8 && "Too many int args");
1317 DestReg = GPR[GPR_idx++];
1319 assert(MVT::isFloatingPoint(N->getOperand(i).getValueType()) &&
1320 "Unpromoted integer arg?");
1321 assert(FPR_idx < 13 && "Too many fp args");
1322 DestReg = FPR[FPR_idx++];
1325 if (N->getOperand(i).getOpcode() != ISD::UNDEF) {
1326 SDOperand Val = Select(N->getOperand(i));
1327 Chain = CurDAG->getCopyToReg(Chain, DestReg, Val, InFlag);
1328 InFlag = Chain.getValue(1);
1329 CallOperands.push_back(CurDAG->getRegister(DestReg, RegTy));
1333 // Finally, once everything is in registers to pass to the call, emit the
1336 CallOperands.push_back(InFlag); // Strong dep on register copies.
1338 CallOperands.push_back(Chain); // Weak dep on whatever occurs before
1339 Chain = CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
1342 std::vector<SDOperand> CallResults;
1344 // If the call has results, copy the values out of the ret val registers.
1345 switch (N->getValueType(0)) {
1346 default: assert(0 && "Unexpected ret value!");
1347 case MVT::Other: break;
1349 if (N->getValueType(1) == MVT::i32) {
1350 Chain = CurDAG->getCopyFromReg(Chain, PPC::R4, MVT::i32,
1351 Chain.getValue(1)).getValue(1);
1352 CallResults.push_back(Chain.getValue(0));
1353 Chain = CurDAG->getCopyFromReg(Chain, PPC::R3, MVT::i32,
1354 Chain.getValue(1)).getValue(1);
1355 CallResults.push_back(Chain.getValue(0));
1357 Chain = CurDAG->getCopyFromReg(Chain, PPC::R3, MVT::i32,
1358 Chain.getValue(1)).getValue(1);
1359 CallResults.push_back(Chain.getValue(0));
1364 Chain = CurDAG->getCopyFromReg(Chain, PPC::F1, N->getValueType(0),
1365 Chain.getValue(1)).getValue(1);
1366 CallResults.push_back(Chain.getValue(0));
1370 CallResults.push_back(Chain);
1371 for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
1372 CodeGenMap[Op.getValue(i)] = CallResults[i];
1373 return CallResults[Op.ResNo];
1376 SDOperand Chain = Select(N->getOperand(0)); // Token chain.
1378 if (N->getNumOperands() == 2) {
1379 SDOperand Val = Select(N->getOperand(1));
1380 if (N->getOperand(1).getValueType() == MVT::i32) {
1381 Chain = CurDAG->getCopyToReg(Chain, PPC::R3, Val);
1383 assert(MVT::isFloatingPoint(N->getOperand(1).getValueType()));
1384 Chain = CurDAG->getCopyToReg(Chain, PPC::F1, Val);
1386 } else if (N->getNumOperands() > 1) {
1387 assert(N->getOperand(1).getValueType() == MVT::i32 &&
1388 N->getOperand(2).getValueType() == MVT::i32 &&
1389 N->getNumOperands() == 3 && "Unknown two-register ret value!");
1390 Chain = CurDAG->getCopyToReg(Chain, PPC::R4, Select(N->getOperand(1)));
1391 Chain = CurDAG->getCopyToReg(Chain, PPC::R3, Select(N->getOperand(2)));
1394 // Finally, select this to a blr (return) instruction.
1395 CurDAG->SelectNodeTo(N, PPC::BLR, MVT::Other, Chain);
1396 return SDOperand(N, 0);
1399 CurDAG->SelectNodeTo(N, PPC::B, MVT::Other, N->getOperand(1),
1400 Select(N->getOperand(0)));
1401 return SDOperand(N, 0);
1403 case ISD::BRTWOWAY_CC: {
1404 SDOperand Chain = Select(N->getOperand(0));
1405 MachineBasicBlock *Dest =
1406 cast<BasicBlockSDNode>(N->getOperand(4))->getBasicBlock();
1407 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
1408 SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC);
1409 unsigned Opc = getBCCForSetCC(CC);
1411 // If this is a two way branch, then grab the fallthrough basic block
1412 // argument and build a PowerPC branch pseudo-op, suitable for long branch
1413 // conversion if necessary by the branch selection pass. Otherwise, emit a
1414 // standard conditional branch.
1415 if (N->getOpcode() == ISD::BRTWOWAY_CC) {
1416 MachineBasicBlock *Fallthrough =
1417 cast<BasicBlockSDNode>(N->getOperand(5))->getBasicBlock();
1418 SDOperand CB = CurDAG->getTargetNode(PPC::COND_BRANCH, MVT::Other,
1419 CondCode, getI32Imm(Opc),
1420 N->getOperand(4), N->getOperand(5),
1422 CurDAG->SelectNodeTo(N, PPC::B, MVT::Other, N->getOperand(5), CB);
1424 // Iterate to the next basic block
1425 ilist<MachineBasicBlock>::iterator It = BB;
1428 // If the fallthrough path is off the end of the function, which would be
1429 // undefined behavior, set it to be the same as the current block because
1430 // we have nothing better to set it to, and leaving it alone will cause
1431 // the PowerPC Branch Selection pass to crash.
1432 if (It == BB->getParent()->end()) It = Dest;
1433 CurDAG->SelectNodeTo(N, PPC::COND_BRANCH, MVT::Other, CondCode,
1434 getI32Imm(Opc), N->getOperand(4),
1435 CurDAG->getBasicBlock(It), Chain);
1437 return SDOperand(N, 0);
1441 return SelectCode(Op);
1445 /// createPPC32ISelDag - This pass converts a legalized DAG into a
1446 /// PowerPC-specific DAG, ready for instruction scheduling.
1448 FunctionPass *llvm::createPPC32ISelDag(TargetMachine &TM) {
1449 return new PPC32DAGToDAGISel(TM);