1 //===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for PowerPC,
11 // converting from a legalized dag to a PPC dag.
13 //===----------------------------------------------------------------------===//
16 #include "PPCTargetMachine.h"
17 #include "PPCISelLowering.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/SSARegMap.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/SelectionDAGISel.h"
23 #include "llvm/Target/TargetOptions.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/Constants.h"
26 #include "llvm/GlobalValue.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/MathExtras.h"
33 Statistic<> FrameOff("ppc-codegen", "Number of frame idx offsets collapsed");
35 //===--------------------------------------------------------------------===//
36 /// PPCDAGToDAGISel - PPC specific code to select PPC machine
37 /// instructions for SelectionDAG operations.
39 class PPCDAGToDAGISel : public SelectionDAGISel {
40 PPCTargetLowering PPCLowering;
41 unsigned GlobalBaseReg;
43 PPCDAGToDAGISel(TargetMachine &TM)
44 : SelectionDAGISel(PPCLowering), PPCLowering(TM) {}
46 virtual bool runOnFunction(Function &Fn) {
47 // Make sure we re-emit a set of the global base reg if necessary
49 return SelectionDAGISel::runOnFunction(Fn);
52 /// getI32Imm - Return a target constant with the specified value, of type
54 inline SDOperand getI32Imm(unsigned Imm) {
55 return CurDAG->getTargetConstant(Imm, MVT::i32);
58 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
59 /// base register. Return the virtual register that holds this value.
60 SDOperand getGlobalBaseReg();
62 // Select - Convert the specified operand from a target-independent to a
63 // target-specific node if it hasn't already been changed.
64 SDOperand Select(SDOperand Op);
66 SDNode *SelectBitfieldInsert(SDNode *N);
68 /// SelectCC - Select a comparison of the specified values with the
69 /// specified condition code, returning the CR# of the expression.
70 SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
72 /// SelectAddrImm - Returns true if the address N can be represented by
73 /// a base register plus a signed 16-bit displacement [r+imm].
74 bool SelectAddrImm(SDOperand N, SDOperand &Disp, SDOperand &Base);
76 /// SelectAddrIdx - Given the specified addressed, check to see if it can be
77 /// represented as an indexed [r+r] operation. Returns false if it can
78 /// be represented by [r+imm], which are preferred.
79 bool SelectAddrIdx(SDOperand N, SDOperand &Base, SDOperand &Index);
81 /// SelectAddrIdxOnly - Given the specified addressed, force it to be
82 /// represented as an indexed [r+r] operation.
83 bool SelectAddrIdxOnly(SDOperand N, SDOperand &Base, SDOperand &Index);
85 SDOperand BuildSDIVSequence(SDNode *N);
86 SDOperand BuildUDIVSequence(SDNode *N);
88 /// InstructionSelectBasicBlock - This callback is invoked by
89 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
90 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
92 virtual const char *getPassName() const {
93 return "PowerPC DAG->DAG Pattern Instruction Selection";
96 // Include the pieces autogenerated from the target description.
97 #include "PPCGenDAGISel.inc"
100 SDOperand SelectADD_PARTS(SDOperand Op);
101 SDOperand SelectSUB_PARTS(SDOperand Op);
102 SDOperand SelectSETCC(SDOperand Op);
103 SDOperand SelectCALL(SDOperand Op);
107 /// InstructionSelectBasicBlock - This callback is invoked by
108 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
109 void PPCDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
112 // The selection process is inherently a bottom-up recursive process (users
113 // select their uses before themselves). Given infinite stack space, we
114 // could just start selecting on the root and traverse the whole graph. In
115 // practice however, this causes us to run out of stack space on large basic
116 // blocks. To avoid this problem, select the entry node, then all its uses,
117 // iteratively instead of recursively.
118 std::vector<SDOperand> Worklist;
119 Worklist.push_back(DAG.getEntryNode());
121 // Note that we can do this in the PPC target (scanning forward across token
122 // chain edges) because no nodes ever get folded across these edges. On a
123 // target like X86 which supports load/modify/store operations, this would
124 // have to be more careful.
125 while (!Worklist.empty()) {
126 SDOperand Node = Worklist.back();
129 // Chose from the least deep of the top two nodes.
130 if (!Worklist.empty() &&
131 Worklist.back().Val->getNodeDepth() < Node.Val->getNodeDepth())
132 std::swap(Worklist.back(), Node);
134 if ((Node.Val->getOpcode() >= ISD::BUILTIN_OP_END &&
135 Node.Val->getOpcode() < PPCISD::FIRST_NUMBER) ||
136 CodeGenMap.count(Node)) continue;
138 for (SDNode::use_iterator UI = Node.Val->use_begin(),
139 E = Node.Val->use_end(); UI != E; ++UI) {
140 // Scan the values. If this use has a value that is a token chain, add it
143 for (unsigned i = 0, e = User->getNumValues(); i != e; ++i)
144 if (User->getValueType(i) == MVT::Other) {
145 Worklist.push_back(SDOperand(User, i));
150 // Finally, legalize this node.
154 // Select target instructions for the DAG.
155 DAG.setRoot(Select(DAG.getRoot()));
157 DAG.RemoveDeadNodes();
159 // Emit machine code to BB.
160 ScheduleAndEmitDAG(DAG);
163 /// getGlobalBaseReg - Output the instructions required to put the
164 /// base address to use for accessing globals into a register.
166 SDOperand PPCDAGToDAGISel::getGlobalBaseReg() {
167 if (!GlobalBaseReg) {
168 // Insert the set of GlobalBaseReg into the first MBB of the function
169 MachineBasicBlock &FirstMBB = BB->getParent()->front();
170 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
171 SSARegMap *RegMap = BB->getParent()->getSSARegMap();
172 // FIXME: when we get to LP64, we will need to create the appropriate
173 // type of register here.
174 GlobalBaseReg = RegMap->createVirtualRegister(PPC::GPRCRegisterClass);
175 BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
176 BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg);
178 return CurDAG->getRegister(GlobalBaseReg, MVT::i32);
182 // isIntImmediate - This method tests to see if a constant operand.
183 // If so Imm will receive the 32 bit value.
184 static bool isIntImmediate(SDNode *N, unsigned& Imm) {
185 if (N->getOpcode() == ISD::Constant) {
186 Imm = cast<ConstantSDNode>(N)->getValue();
192 // isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s with
193 // any number of 0s on either side. The 1s are allowed to wrap from LSB to
194 // MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 0x0F0F0000 is
195 // not, since all 1s are not contiguous.
196 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
197 if (isShiftedMask_32(Val)) {
198 // look for the first non-zero bit
199 MB = CountLeadingZeros_32(Val);
200 // look for the first zero bit after the run of ones
201 ME = CountLeadingZeros_32((Val - 1) ^ Val);
204 Val = ~Val; // invert mask
205 if (isShiftedMask_32(Val)) {
206 // effectively look for the first zero bit
207 ME = CountLeadingZeros_32(Val) - 1;
208 // effectively look for the first one bit after the run of zeros
209 MB = CountLeadingZeros_32((Val - 1) ^ Val) + 1;
217 // isRotateAndMask - Returns true if Mask and Shift can be folded into a rotate
218 // and mask opcode and mask operation.
219 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask,
220 unsigned &SH, unsigned &MB, unsigned &ME) {
221 // Don't even go down this path for i64, since different logic will be
222 // necessary for rldicl/rldicr/rldimi.
223 if (N->getValueType(0) != MVT::i32)
227 unsigned Indeterminant = ~0; // bit mask marking indeterminant results
228 unsigned Opcode = N->getOpcode();
229 if (N->getNumOperands() != 2 ||
230 !isIntImmediate(N->getOperand(1).Val, Shift) || (Shift > 31))
233 if (Opcode == ISD::SHL) {
234 // apply shift left to mask if it comes first
235 if (IsShiftMask) Mask = Mask << Shift;
236 // determine which bits are made indeterminant by shift
237 Indeterminant = ~(0xFFFFFFFFu << Shift);
238 } else if (Opcode == ISD::SRL) {
239 // apply shift right to mask if it comes first
240 if (IsShiftMask) Mask = Mask >> Shift;
241 // determine which bits are made indeterminant by shift
242 Indeterminant = ~(0xFFFFFFFFu >> Shift);
243 // adjust for the left rotate
249 // if the mask doesn't intersect any Indeterminant bits
250 if (Mask && !(Mask & Indeterminant)) {
252 // make sure the mask is still a mask (wrap arounds may not be)
253 return isRunOfOnes(Mask, MB, ME);
258 // isOpcWithIntImmediate - This method tests to see if the node is a specific
259 // opcode and that it has a immediate integer right operand.
260 // If so Imm will receive the 32 bit value.
261 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
262 return N->getOpcode() == Opc && isIntImmediate(N->getOperand(1).Val, Imm);
265 // isIntImmediate - This method tests to see if a constant operand.
266 // If so Imm will receive the 32 bit value.
267 static bool isIntImmediate(SDOperand N, unsigned& Imm) {
268 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
269 Imm = (unsigned)CN->getSignExtended();
275 /// SelectBitfieldInsert - turn an or of two masked values into
276 /// the rotate left word immediate then mask insert (rlwimi) instruction.
277 /// Returns true on success, false if the caller still needs to select OR.
279 /// Patterns matched:
280 /// 1. or shl, and 5. or and, and
281 /// 2. or and, shl 6. or shl, shr
282 /// 3. or shr, and 7. or shr, shl
284 SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
285 bool IsRotate = false;
286 unsigned TgtMask = 0xFFFFFFFF, InsMask = 0xFFFFFFFF, SH = 0;
289 SDOperand Op0 = N->getOperand(0);
290 SDOperand Op1 = N->getOperand(1);
292 unsigned Op0Opc = Op0.getOpcode();
293 unsigned Op1Opc = Op1.getOpcode();
295 // Verify that we have the correct opcodes
296 if (ISD::SHL != Op0Opc && ISD::SRL != Op0Opc && ISD::AND != Op0Opc)
298 if (ISD::SHL != Op1Opc && ISD::SRL != Op1Opc && ISD::AND != Op1Opc)
301 // Generate Mask value for Target
302 if (isIntImmediate(Op0.getOperand(1), Value)) {
304 case ISD::SHL: TgtMask <<= Value; break;
305 case ISD::SRL: TgtMask >>= Value; break;
306 case ISD::AND: TgtMask &= Value; break;
312 // Generate Mask value for Insert
313 if (!isIntImmediate(Op1.getOperand(1), Value))
320 if (Op0Opc == ISD::SRL) IsRotate = true;
326 if (Op0Opc == ISD::SHL) IsRotate = true;
333 // If both of the inputs are ANDs and one of them has a logical shift by
334 // constant as its input, make that AND the inserted value so that we can
335 // combine the shift into the rotate part of the rlwimi instruction
336 bool IsAndWithShiftOp = false;
337 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
338 if (Op1.getOperand(0).getOpcode() == ISD::SHL ||
339 Op1.getOperand(0).getOpcode() == ISD::SRL) {
340 if (isIntImmediate(Op1.getOperand(0).getOperand(1), Value)) {
341 SH = Op1.getOperand(0).getOpcode() == ISD::SHL ? Value : 32 - Value;
342 IsAndWithShiftOp = true;
344 } else if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
345 Op0.getOperand(0).getOpcode() == ISD::SRL) {
346 if (isIntImmediate(Op0.getOperand(0).getOperand(1), Value)) {
348 std::swap(TgtMask, InsMask);
349 SH = Op1.getOperand(0).getOpcode() == ISD::SHL ? Value : 32 - Value;
350 IsAndWithShiftOp = true;
355 // Verify that the Target mask and Insert mask together form a full word mask
356 // and that the Insert mask is a run of set bits (which implies both are runs
357 // of set bits). Given that, Select the arguments and generate the rlwimi
360 if (((TgtMask & InsMask) == 0) && isRunOfOnes(InsMask, MB, ME)) {
361 bool fullMask = (TgtMask ^ InsMask) == 0xFFFFFFFF;
362 bool Op0IsAND = Op0Opc == ISD::AND;
363 // Check for rotlwi / rotrwi here, a special case of bitfield insert
364 // where both bitfield halves are sourced from the same value.
365 if (IsRotate && fullMask &&
366 N->getOperand(0).getOperand(0) == N->getOperand(1).getOperand(0)) {
367 Op0 = CurDAG->getTargetNode(PPC::RLWINM, MVT::i32,
368 Select(N->getOperand(0).getOperand(0)),
369 getI32Imm(SH), getI32Imm(0), getI32Imm(31));
372 SDOperand Tmp1 = (Op0IsAND && fullMask) ? Select(Op0.getOperand(0))
374 SDOperand Tmp2 = IsAndWithShiftOp ? Select(Op1.getOperand(0).getOperand(0))
375 : Select(Op1.getOperand(0));
376 Op0 = CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Tmp1, Tmp2,
377 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
383 /// SelectAddrImm - Returns true if the address N can be represented by
384 /// a base register plus a signed 16-bit displacement [r+imm].
385 bool PPCDAGToDAGISel::SelectAddrImm(SDOperand N, SDOperand &Disp,
387 if (N.getOpcode() == ISD::ADD) {
389 if (isIntImmediate(N.getOperand(1), imm) && isInt16(imm)) {
390 Disp = getI32Imm(imm & 0xFFFF);
391 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
392 Base = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
394 Base = Select(N.getOperand(0));
396 return true; // [r+i]
397 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
398 // Match LOAD (ADD (X, Lo(G))).
399 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
400 && "Cannot handle constant offsets yet!");
401 Disp = N.getOperand(1).getOperand(0); // The global address.
402 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
403 Disp.getOpcode() == ISD::TargetConstantPool);
404 Base = Select(N.getOperand(0));
405 return true; // [&g+r]
407 return false; // [r+r]
410 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
411 Base = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
414 return true; // [r+0]
417 /// SelectAddrIdx - Given the specified addressed, check to see if it can be
418 /// represented as an indexed [r+r] operation. Returns false if it can
419 /// be represented by [r+imm], which are preferred.
420 bool PPCDAGToDAGISel::SelectAddrIdx(SDOperand N, SDOperand &Base,
422 // Check to see if we can represent this as an [r+imm] address instead,
423 // which will fail if the address is more profitably represented as an
425 if (SelectAddrImm(N, Base, Index))
428 if (N.getOpcode() == ISD::ADD) {
429 Base = Select(N.getOperand(0));
430 Index = Select(N.getOperand(1));
434 Base = CurDAG->getRegister(PPC::R0, MVT::i32);
439 /// SelectAddrIdxOnly - Given the specified addressed, force it to be
440 /// represented as an indexed [r+r] operation.
441 bool PPCDAGToDAGISel::SelectAddrIdxOnly(SDOperand N, SDOperand &Base,
443 if (N.getOpcode() == ISD::ADD) {
444 Base = Select(N.getOperand(0));
445 Index = Select(N.getOperand(1));
449 Base = CurDAG->getRegister(PPC::R0, MVT::i32);
454 /// SelectCC - Select a comparison of the specified values with the specified
455 /// condition code, returning the CR# of the expression.
456 SDOperand PPCDAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS,
458 // Always select the LHS.
461 // Use U to determine whether the SETCC immediate range is signed or not.
462 if (MVT::isInteger(LHS.getValueType())) {
463 bool U = ISD::isUnsignedIntSetCC(CC);
465 if (isIntImmediate(RHS, Imm) &&
466 ((U && isUInt16(Imm)) || (!U && isInt16(Imm))))
467 return CurDAG->getTargetNode(U ? PPC::CMPLWI : PPC::CMPWI, MVT::i32,
468 LHS, getI32Imm(Imm & 0xFFFF));
469 return CurDAG->getTargetNode(U ? PPC::CMPLW : PPC::CMPW, MVT::i32,
471 } else if (LHS.getValueType() == MVT::f32) {
472 return CurDAG->getTargetNode(PPC::FCMPUS, MVT::i32, LHS, Select(RHS));
474 return CurDAG->getTargetNode(PPC::FCMPUD, MVT::i32, LHS, Select(RHS));
478 /// getBCCForSetCC - Returns the PowerPC condition branch mnemonic corresponding
480 static unsigned getBCCForSetCC(ISD::CondCode CC) {
482 default: assert(0 && "Unknown condition!"); abort();
483 case ISD::SETOEQ: // FIXME: This is incorrect see PR642.
484 case ISD::SETEQ: return PPC::BEQ;
485 case ISD::SETONE: // FIXME: This is incorrect see PR642.
486 case ISD::SETNE: return PPC::BNE;
487 case ISD::SETOLT: // FIXME: This is incorrect see PR642.
489 case ISD::SETLT: return PPC::BLT;
490 case ISD::SETOLE: // FIXME: This is incorrect see PR642.
492 case ISD::SETLE: return PPC::BLE;
493 case ISD::SETOGT: // FIXME: This is incorrect see PR642.
495 case ISD::SETGT: return PPC::BGT;
496 case ISD::SETOGE: // FIXME: This is incorrect see PR642.
498 case ISD::SETGE: return PPC::BGE;
500 case ISD::SETO: return PPC::BUN;
501 case ISD::SETUO: return PPC::BNU;
506 /// getCRIdxForSetCC - Return the index of the condition register field
507 /// associated with the SetCC condition, and whether or not the field is
508 /// treated as inverted. That is, lt = 0; ge = 0 inverted.
509 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool& Inv) {
511 default: assert(0 && "Unknown condition!"); abort();
512 case ISD::SETOLT: // FIXME: This is incorrect see PR642.
514 case ISD::SETLT: Inv = false; return 0;
515 case ISD::SETOGE: // FIXME: This is incorrect see PR642.
517 case ISD::SETGE: Inv = true; return 0;
518 case ISD::SETOGT: // FIXME: This is incorrect see PR642.
520 case ISD::SETGT: Inv = false; return 1;
521 case ISD::SETOLE: // FIXME: This is incorrect see PR642.
523 case ISD::SETLE: Inv = true; return 1;
524 case ISD::SETOEQ: // FIXME: This is incorrect see PR642.
525 case ISD::SETEQ: Inv = false; return 2;
526 case ISD::SETONE: // FIXME: This is incorrect see PR642.
527 case ISD::SETNE: Inv = true; return 2;
528 case ISD::SETO: Inv = true; return 3;
529 case ISD::SETUO: Inv = false; return 3;
535 SDOperand PPCDAGToDAGISel::SelectADD_PARTS(SDOperand Op) {
537 SDOperand LHSL = Select(N->getOperand(0));
538 SDOperand LHSH = Select(N->getOperand(1));
541 bool ME = false, ZE = false;
542 if (isIntImmediate(N->getOperand(3), Imm)) {
543 ME = (signed)Imm == -1;
547 std::vector<SDOperand> Result;
548 SDOperand CarryFromLo;
549 if (isIntImmediate(N->getOperand(2), Imm) &&
550 ((signed)Imm >= -32768 || (signed)Imm < 32768)) {
551 // Codegen the low 32 bits of the add. Interestingly, there is no
552 // shifted form of add immediate carrying.
553 CarryFromLo = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
554 LHSL, getI32Imm(Imm));
556 CarryFromLo = CurDAG->getTargetNode(PPC::ADDC, MVT::i32, MVT::Flag,
557 LHSL, Select(N->getOperand(2)));
559 CarryFromLo = CarryFromLo.getValue(1);
561 // Codegen the high 32 bits, adding zero, minus one, or the full value
562 // along with the carry flag produced by addc/addic.
565 ResultHi = CurDAG->getTargetNode(PPC::ADDZE, MVT::i32, LHSH, CarryFromLo);
567 ResultHi = CurDAG->getTargetNode(PPC::ADDME, MVT::i32, LHSH, CarryFromLo);
569 ResultHi = CurDAG->getTargetNode(PPC::ADDE, MVT::i32, LHSH,
570 Select(N->getOperand(3)), CarryFromLo);
571 Result.push_back(CarryFromLo.getValue(0));
572 Result.push_back(ResultHi);
574 CodeGenMap[Op.getValue(0)] = Result[0];
575 CodeGenMap[Op.getValue(1)] = Result[1];
576 return Result[Op.ResNo];
578 SDOperand PPCDAGToDAGISel::SelectSUB_PARTS(SDOperand Op) {
580 SDOperand LHSL = Select(N->getOperand(0));
581 SDOperand LHSH = Select(N->getOperand(1));
582 SDOperand RHSL = Select(N->getOperand(2));
583 SDOperand RHSH = Select(N->getOperand(3));
585 std::vector<SDOperand> Result;
586 Result.push_back(CurDAG->getTargetNode(PPC::SUBFC, MVT::i32, MVT::Flag,
588 Result.push_back(CurDAG->getTargetNode(PPC::SUBFE, MVT::i32, RHSH, LHSH,
589 Result[0].getValue(1)));
590 CodeGenMap[Op.getValue(0)] = Result[0];
591 CodeGenMap[Op.getValue(1)] = Result[1];
592 return Result[Op.ResNo];
595 SDOperand PPCDAGToDAGISel::SelectSETCC(SDOperand Op) {
598 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
599 if (isIntImmediate(N->getOperand(1), Imm)) {
600 // We can codegen setcc op, imm very efficiently compared to a brcond.
601 // Check for those cases here.
604 SDOperand Op = Select(N->getOperand(0));
608 Op = CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op);
609 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(27),
610 getI32Imm(5), getI32Imm(31));
612 SDOperand AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
614 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
618 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(1),
619 getI32Imm(31), getI32Imm(31));
621 SDOperand T = CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op);
622 T = CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op);;
623 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, T, getI32Imm(1),
624 getI32Imm(31), getI32Imm(31));
627 } else if (Imm == ~0U) { // setcc op, -1
628 SDOperand Op = Select(N->getOperand(0));
632 Op = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
634 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
635 CurDAG->getTargetNode(PPC::LI, MVT::i32,
639 Op = CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op);
640 SDOperand AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
642 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
646 SDOperand AD = CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op,
648 SDOperand AN = CurDAG->getTargetNode(PPC::AND, MVT::i32, AD, Op);
649 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, AN, getI32Imm(1),
650 getI32Imm(31), getI32Imm(31));
653 Op = CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Op, getI32Imm(1),
654 getI32Imm(31), getI32Imm(31));
655 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, getI32Imm(1));
661 unsigned Idx = getCRIdxForSetCC(CC, Inv);
662 SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
665 // Force the ccreg into CR7.
666 SDOperand CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
668 SDOperand InFlag(0, 0); // Null incoming flag value.
669 CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), CR7Reg, CCReg,
672 if (TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor())
673 IntCR = CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg, CCReg);
675 IntCR = CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg);
678 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, IntCR,
679 getI32Imm((32-(3-Idx)) & 31),
680 getI32Imm(31), getI32Imm(31));
683 CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, IntCR,
684 getI32Imm((32-(3-Idx)) & 31),
685 getI32Imm(31),getI32Imm(31));
686 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
690 /// isCallCompatibleAddress - Return true if the specified 32-bit value is
691 /// representable in the immediate field of a Bx instruction.
692 static bool isCallCompatibleAddress(ConstantSDNode *C) {
693 int Addr = C->getValue();
694 if (Addr & 3) return false; // Low 2 bits are implicitly zero.
695 return (Addr << 6 >> 6) == Addr; // Top 6 bits have to be sext of immediate.
698 SDOperand PPCDAGToDAGISel::SelectCALL(SDOperand Op) {
700 SDOperand Chain = Select(N->getOperand(0));
703 std::vector<SDOperand> CallOperands;
705 if (GlobalAddressSDNode *GASD =
706 dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) {
707 CallOpcode = PPC::BL;
708 CallOperands.push_back(N->getOperand(1));
709 } else if (ExternalSymbolSDNode *ESSDN =
710 dyn_cast<ExternalSymbolSDNode>(N->getOperand(1))) {
711 CallOpcode = PPC::BL;
712 CallOperands.push_back(N->getOperand(1));
713 } else if (isa<ConstantSDNode>(N->getOperand(1)) &&
714 isCallCompatibleAddress(cast<ConstantSDNode>(N->getOperand(1)))) {
715 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(1));
716 CallOpcode = PPC::BLA;
717 CallOperands.push_back(getI32Imm((int)C->getValue() >> 2));
719 // Copy the callee address into the CTR register.
720 SDOperand Callee = Select(N->getOperand(1));
721 Chain = CurDAG->getTargetNode(PPC::MTCTR, MVT::Other, Callee, Chain);
723 // Copy the callee address into R12 on darwin.
724 SDOperand R12 = CurDAG->getRegister(PPC::R12, MVT::i32);
725 Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, Chain, R12, Callee);
727 CallOperands.push_back(R12);
728 CallOpcode = PPC::BCTRL;
731 unsigned GPR_idx = 0, FPR_idx = 0;
732 static const unsigned GPR[] = {
733 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
734 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
736 static const unsigned FPR[] = {
737 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
738 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
741 SDOperand InFlag; // Null incoming flag value.
743 for (unsigned i = 2, e = N->getNumOperands(); i != e; ++i) {
744 unsigned DestReg = 0;
745 MVT::ValueType RegTy = N->getOperand(i).getValueType();
746 if (RegTy == MVT::i32) {
747 assert(GPR_idx < 8 && "Too many int args");
748 DestReg = GPR[GPR_idx++];
750 assert(MVT::isFloatingPoint(N->getOperand(i).getValueType()) &&
751 "Unpromoted integer arg?");
752 assert(FPR_idx < 13 && "Too many fp args");
753 DestReg = FPR[FPR_idx++];
756 if (N->getOperand(i).getOpcode() != ISD::UNDEF) {
757 SDOperand Val = Select(N->getOperand(i));
758 Chain = CurDAG->getCopyToReg(Chain, DestReg, Val, InFlag);
759 InFlag = Chain.getValue(1);
760 CallOperands.push_back(CurDAG->getRegister(DestReg, RegTy));
764 // Finally, once everything is in registers to pass to the call, emit the
767 CallOperands.push_back(InFlag); // Strong dep on register copies.
769 CallOperands.push_back(Chain); // Weak dep on whatever occurs before
770 Chain = CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
773 std::vector<SDOperand> CallResults;
775 // If the call has results, copy the values out of the ret val registers.
776 switch (N->getValueType(0)) {
777 default: assert(0 && "Unexpected ret value!");
778 case MVT::Other: break;
780 if (N->getValueType(1) == MVT::i32) {
781 Chain = CurDAG->getCopyFromReg(Chain, PPC::R4, MVT::i32,
782 Chain.getValue(1)).getValue(1);
783 CallResults.push_back(Chain.getValue(0));
784 Chain = CurDAG->getCopyFromReg(Chain, PPC::R3, MVT::i32,
785 Chain.getValue(2)).getValue(1);
786 CallResults.push_back(Chain.getValue(0));
788 Chain = CurDAG->getCopyFromReg(Chain, PPC::R3, MVT::i32,
789 Chain.getValue(1)).getValue(1);
790 CallResults.push_back(Chain.getValue(0));
795 Chain = CurDAG->getCopyFromReg(Chain, PPC::F1, N->getValueType(0),
796 Chain.getValue(1)).getValue(1);
797 CallResults.push_back(Chain.getValue(0));
801 CallResults.push_back(Chain);
802 for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
803 CodeGenMap[Op.getValue(i)] = CallResults[i];
804 return CallResults[Op.ResNo];
807 // Select - Convert the specified operand from a target-independent to a
808 // target-specific node if it hasn't already been changed.
809 SDOperand PPCDAGToDAGISel::Select(SDOperand Op) {
811 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
812 N->getOpcode() < PPCISD::FIRST_NUMBER)
813 return Op; // Already selected.
815 // If this has already been converted, use it.
816 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
817 if (CGMI != CodeGenMap.end()) return CGMI->second;
819 switch (N->getOpcode()) {
821 case ISD::ADD_PARTS: return SelectADD_PARTS(Op);
822 case ISD::SUB_PARTS: return SelectSUB_PARTS(Op);
823 case ISD::SETCC: return SelectSETCC(Op);
824 case PPCISD::CALL: return SelectCALL(Op);
825 case PPCISD::GlobalBaseReg: return getGlobalBaseReg();
827 case ISD::FrameIndex: {
828 int FI = cast<FrameIndexSDNode>(N)->getIndex();
830 return CurDAG->SelectNodeTo(N, PPC::ADDI, MVT::i32,
831 CurDAG->getTargetFrameIndex(FI, MVT::i32),
833 return CodeGenMap[Op] =
834 CurDAG->getTargetNode(PPC::ADDI, MVT::i32,
835 CurDAG->getTargetFrameIndex(FI, MVT::i32),
839 // FIXME: since this depends on the setting of the carry flag from the srawi
840 // we should really be making notes about that for the scheduler.
841 // FIXME: It sure would be nice if we could cheaply recognize the
842 // srl/add/sra pattern the dag combiner will generate for this as
843 // sra/addze rather than having to handle sdiv ourselves. oh well.
845 if (isIntImmediate(N->getOperand(1), Imm)) {
846 if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
848 CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
849 Select(N->getOperand(0)),
850 getI32Imm(Log2_32(Imm)));
851 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
852 Op.getValue(0), Op.getValue(1));
853 } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
855 CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
856 Select(N->getOperand(0)),
857 getI32Imm(Log2_32(-Imm)));
859 CurDAG->getTargetNode(PPC::ADDZE, MVT::i32, Op.getValue(0),
861 return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
865 // Other cases are autogenerated.
870 // If this is an and of a value rotated between 0 and 31 bits and then and'd
871 // with a mask, emit rlwinm
872 if (isIntImmediate(N->getOperand(1), Imm) && (isShiftedMask_32(Imm) ||
873 isShiftedMask_32(~Imm))) {
876 if (isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB, ME)) {
877 Val = Select(N->getOperand(0).getOperand(0));
878 } else if (Imm == 0) {
879 // AND X, 0 -> 0, not "rlwinm 32".
880 return Select(N->getOperand(1));
882 Val = Select(N->getOperand(0));
883 isRunOfOnes(Imm, MB, ME);
886 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Val, getI32Imm(SH),
887 getI32Imm(MB), getI32Imm(ME));
889 // ISD::OR doesn't get all the bitfield insertion fun.
890 // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert
891 if (isIntImmediate(N->getOperand(1), Imm) &&
892 N->getOperand(0).getOpcode() == ISD::OR &&
893 isIntImmediate(N->getOperand(0).getOperand(1), Imm2)) {
896 if (isRunOfOnes(Imm, MB, ME)) {
897 SDOperand Tmp1 = Select(N->getOperand(0).getOperand(0));
898 SDOperand Tmp2 = Select(N->getOperand(0).getOperand(1));
899 return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Tmp1, Tmp2,
900 getI32Imm(0), getI32Imm(MB), getI32Imm(ME));
904 // Other cases are autogenerated.
908 if (SDNode *I = SelectBitfieldInsert(N))
909 return CodeGenMap[Op] = SDOperand(I, 0);
911 // Other cases are autogenerated.
914 unsigned Imm, SH, MB, ME;
915 if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
916 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
917 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32,
918 Select(N->getOperand(0).getOperand(0)),
919 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
922 // Other cases are autogenerated.
926 unsigned Imm, SH, MB, ME;
927 if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
928 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
929 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32,
930 Select(N->getOperand(0).getOperand(0)),
931 getI32Imm(SH & 0x1F), getI32Imm(MB),
935 // Other cases are autogenerated.
938 case ISD::SELECT_CC: {
939 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
941 // handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
942 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
943 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
944 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
945 if (N1C->isNullValue() && N3C->isNullValue() &&
946 N2C->getValue() == 1ULL && CC == ISD::SETNE) {
947 SDOperand LHS = Select(N->getOperand(0));
949 CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
950 LHS, getI32Imm(~0U));
951 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, Tmp, LHS,
955 SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
956 unsigned BROpc = getBCCForSetCC(CC);
958 bool isFP = MVT::isFloatingPoint(N->getValueType(0));
960 if (MVT::isInteger(N->getValueType(0)))
961 SelectCCOp = PPC::SELECT_CC_Int;
962 else if (N->getValueType(0) == MVT::f32)
963 SelectCCOp = PPC::SELECT_CC_F4;
965 SelectCCOp = PPC::SELECT_CC_F8;
966 return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), CCReg,
967 Select(N->getOperand(2)),
968 Select(N->getOperand(3)),
972 case ISD::BRTWOWAY_CC: {
973 SDOperand Chain = Select(N->getOperand(0));
974 MachineBasicBlock *Dest =
975 cast<BasicBlockSDNode>(N->getOperand(4))->getBasicBlock();
976 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
977 SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC);
979 // If this is a two way branch, then grab the fallthrough basic block
980 // argument and build a PowerPC branch pseudo-op, suitable for long branch
981 // conversion if necessary by the branch selection pass. Otherwise, emit a
982 // standard conditional branch.
983 if (N->getOpcode() == ISD::BRTWOWAY_CC) {
984 SDOperand CondTrueBlock = N->getOperand(4);
985 SDOperand CondFalseBlock = N->getOperand(5);
987 // If the false case is the current basic block, then this is a self loop.
988 // We do not want to emit "Loop: ... brcond Out; br Loop", as it adds an
989 // extra dispatch group to the loop. Instead, invert the condition and
990 // emit "Loop: ... br!cond Loop; br Out
991 if (cast<BasicBlockSDNode>(CondFalseBlock)->getBasicBlock() == BB) {
992 std::swap(CondTrueBlock, CondFalseBlock);
993 CC = getSetCCInverse(CC,
994 MVT::isInteger(N->getOperand(2).getValueType()));
997 unsigned Opc = getBCCForSetCC(CC);
998 SDOperand CB = CurDAG->getTargetNode(PPC::COND_BRANCH, MVT::Other,
999 CondCode, getI32Imm(Opc),
1000 CondTrueBlock, CondFalseBlock,
1002 return CurDAG->SelectNodeTo(N, PPC::B, MVT::Other, CondFalseBlock, CB);
1004 // Iterate to the next basic block
1005 ilist<MachineBasicBlock>::iterator It = BB;
1008 // If the fallthrough path is off the end of the function, which would be
1009 // undefined behavior, set it to be the same as the current block because
1010 // we have nothing better to set it to, and leaving it alone will cause
1011 // the PowerPC Branch Selection pass to crash.
1012 if (It == BB->getParent()->end()) It = Dest;
1013 return CurDAG->SelectNodeTo(N, PPC::COND_BRANCH, MVT::Other, CondCode,
1014 getI32Imm(getBCCForSetCC(CC)),
1015 N->getOperand(4), CurDAG->getBasicBlock(It),
1021 return SelectCode(Op);
1025 /// createPPCISelDag - This pass converts a legalized DAG into a
1026 /// PowerPC-specific DAG, ready for instruction scheduling.
1028 FunctionPass *llvm::createPPCISelDag(TargetMachine &TM) {
1029 return new PPCDAGToDAGISel(TM);