1 //===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for PowerPC,
11 // converting from a legalized dag to a PPC dag.
13 //===----------------------------------------------------------------------===//
16 #include "PPCTargetMachine.h"
17 #include "PPCISelLowering.h"
18 #include "PPCHazardRecognizers.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/SSARegMap.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/Constants.h"
27 #include "llvm/GlobalValue.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/MathExtras.h"
35 Statistic<> FrameOff("ppc-codegen", "Number of frame idx offsets collapsed");
37 //===--------------------------------------------------------------------===//
38 /// PPCDAGToDAGISel - PPC specific code to select PPC machine
39 /// instructions for SelectionDAG operations.
41 class PPCDAGToDAGISel : public SelectionDAGISel {
43 PPCTargetLowering PPCLowering;
44 unsigned GlobalBaseReg;
46 PPCDAGToDAGISel(PPCTargetMachine &tm)
47 : SelectionDAGISel(PPCLowering), TM(tm),
48 PPCLowering(*TM.getTargetLowering()) {}
50 virtual bool runOnFunction(Function &Fn) {
51 // Make sure we re-emit a set of the global base reg if necessary
53 SelectionDAGISel::runOnFunction(Fn);
59 /// getI32Imm - Return a target constant with the specified value, of type
61 inline SDOperand getI32Imm(unsigned Imm) {
62 return CurDAG->getTargetConstant(Imm, MVT::i32);
65 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
66 /// base register. Return the virtual register that holds this value.
67 SDOperand getGlobalBaseReg();
69 // Select - Convert the specified operand from a target-independent to a
70 // target-specific node if it hasn't already been changed.
71 void Select(SDOperand &Result, SDOperand Op);
73 SDNode *SelectBitfieldInsert(SDNode *N);
75 /// SelectCC - Select a comparison of the specified values with the
76 /// specified condition code, returning the CR# of the expression.
77 SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
79 /// SelectAddrImm - Returns true if the address N can be represented by
80 /// a base register plus a signed 16-bit displacement [r+imm].
81 bool SelectAddrImm(SDOperand N, SDOperand &Disp, SDOperand &Base);
83 /// SelectAddrIdx - Given the specified addressed, check to see if it can be
84 /// represented as an indexed [r+r] operation. Returns false if it can
85 /// be represented by [r+imm], which are preferred.
86 bool SelectAddrIdx(SDOperand N, SDOperand &Base, SDOperand &Index);
88 /// SelectAddrIdxOnly - Given the specified addressed, force it to be
89 /// represented as an indexed [r+r] operation.
90 bool SelectAddrIdxOnly(SDOperand N, SDOperand &Base, SDOperand &Index);
92 /// SelectAddrImmShift - Returns true if the address N can be represented by
93 /// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable
94 /// for use by STD and friends.
95 bool SelectAddrImmShift(SDOperand N, SDOperand &Disp, SDOperand &Base);
97 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
98 /// inline asm expressions.
99 virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
101 std::vector<SDOperand> &OutOps,
104 switch (ConstraintCode) {
105 default: return true;
107 if (!SelectAddrIdx(Op, Op0, Op1))
108 SelectAddrImm(Op, Op0, Op1);
110 case 'o': // offsetable
111 if (!SelectAddrImm(Op, Op0, Op1)) {
112 Select(Op0, Op); // r+0.
116 case 'v': // not offsetable
117 SelectAddrIdxOnly(Op, Op0, Op1);
121 OutOps.push_back(Op0);
122 OutOps.push_back(Op1);
126 SDOperand BuildSDIVSequence(SDNode *N);
127 SDOperand BuildUDIVSequence(SDNode *N);
129 /// InstructionSelectBasicBlock - This callback is invoked by
130 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
131 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
133 void InsertVRSaveCode(Function &Fn);
135 virtual const char *getPassName() const {
136 return "PowerPC DAG->DAG Pattern Instruction Selection";
139 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for this
140 /// target when scheduling the DAG.
141 virtual HazardRecognizer *CreateTargetHazardRecognizer() {
142 // Should use subtarget info to pick the right hazard recognizer. For
143 // now, always return a PPC970 recognizer.
144 const TargetInstrInfo *II = PPCLowering.getTargetMachine().getInstrInfo();
145 assert(II && "No InstrInfo?");
146 return new PPCHazardRecognizer970(*II);
149 // Include the pieces autogenerated from the target description.
150 #include "PPCGenDAGISel.inc"
153 SDOperand SelectSETCC(SDOperand Op);
154 SDOperand SelectCALL(SDOperand Op);
158 /// InstructionSelectBasicBlock - This callback is invoked by
159 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
160 void PPCDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
163 // The selection process is inherently a bottom-up recursive process (users
164 // select their uses before themselves). Given infinite stack space, we
165 // could just start selecting on the root and traverse the whole graph. In
166 // practice however, this causes us to run out of stack space on large basic
167 // blocks. To avoid this problem, select the entry node, then all its uses,
168 // iteratively instead of recursively.
169 std::vector<SDOperand> Worklist;
170 Worklist.push_back(DAG.getEntryNode());
172 // Note that we can do this in the PPC target (scanning forward across token
173 // chain edges) because no nodes ever get folded across these edges. On a
174 // target like X86 which supports load/modify/store operations, this would
175 // have to be more careful.
176 while (!Worklist.empty()) {
177 SDOperand Node = Worklist.back();
180 // Chose from the least deep of the top two nodes.
181 if (!Worklist.empty() &&
182 Worklist.back().Val->getNodeDepth() < Node.Val->getNodeDepth())
183 std::swap(Worklist.back(), Node);
185 if ((Node.Val->getOpcode() >= ISD::BUILTIN_OP_END &&
186 Node.Val->getOpcode() < PPCISD::FIRST_NUMBER) ||
187 CodeGenMap.count(Node)) continue;
189 for (SDNode::use_iterator UI = Node.Val->use_begin(),
190 E = Node.Val->use_end(); UI != E; ++UI) {
191 // Scan the values. If this use has a value that is a token chain, add it
194 for (unsigned i = 0, e = User->getNumValues(); i != e; ++i)
195 if (User->getValueType(i) == MVT::Other) {
196 Worklist.push_back(SDOperand(User, i));
201 // Finally, legalize this node.
206 // Select target instructions for the DAG.
207 DAG.setRoot(SelectRoot(DAG.getRoot()));
209 DAG.RemoveDeadNodes();
211 // Emit machine code to BB.
212 ScheduleAndEmitDAG(DAG);
215 /// InsertVRSaveCode - Once the entire function has been instruction selected,
216 /// all virtual registers are created and all machine instructions are built,
217 /// check to see if we need to save/restore VRSAVE. If so, do it.
218 void PPCDAGToDAGISel::InsertVRSaveCode(Function &F) {
219 // Check to see if this function uses vector registers, which means we have to
220 // save and restore the VRSAVE register and update it with the regs we use.
222 // In this case, there will be virtual registers of vector type type created
223 // by the scheduler. Detect them now.
224 MachineFunction &Fn = MachineFunction::get(&F);
225 SSARegMap *RegMap = Fn.getSSARegMap();
226 bool HasVectorVReg = false;
227 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
228 e = RegMap->getLastVirtReg()+1; i != e; ++i)
229 if (RegMap->getRegClass(i) == &PPC::VRRCRegClass) {
230 HasVectorVReg = true;
233 if (!HasVectorVReg) return; // nothing to do.
235 // If we have a vector register, we want to emit code into the entry and exit
236 // blocks to save and restore the VRSAVE register. We do this here (instead
237 // of marking all vector instructions as clobbering VRSAVE) for two reasons:
239 // 1. This (trivially) reduces the load on the register allocator, by not
240 // having to represent the live range of the VRSAVE register.
241 // 2. This (more significantly) allows us to create a temporary virtual
242 // register to hold the saved VRSAVE value, allowing this temporary to be
243 // register allocated, instead of forcing it to be spilled to the stack.
245 // Create two vregs - one to hold the VRSAVE register that is live-in to the
246 // function and one for the value after having bits or'd into it.
247 unsigned InVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
248 unsigned UpdatedVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
250 MachineBasicBlock &EntryBB = *Fn.begin();
251 // Emit the following code into the entry block:
252 // InVRSAVE = MFVRSAVE
253 // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
254 // MTVRSAVE UpdatedVRSAVE
255 MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
256 BuildMI(EntryBB, IP, PPC::MFVRSAVE, 0, InVRSAVE);
257 BuildMI(EntryBB, IP, PPC::UPDATE_VRSAVE, 1, UpdatedVRSAVE).addReg(InVRSAVE);
258 BuildMI(EntryBB, IP, PPC::MTVRSAVE, 1).addReg(UpdatedVRSAVE);
260 // Find all return blocks, outputting a restore in each epilog.
261 const TargetInstrInfo &TII = *TM.getInstrInfo();
262 for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
263 if (!BB->empty() && TII.isReturn(BB->back().getOpcode())) {
264 IP = BB->end(); --IP;
266 // Skip over all terminator instructions, which are part of the return
268 MachineBasicBlock::iterator I2 = IP;
269 while (I2 != BB->begin() && TII.isTerminatorInstr((--I2)->getOpcode()))
272 // Emit: MTVRSAVE InVRSave
273 BuildMI(*BB, IP, PPC::MTVRSAVE, 1).addReg(InVRSAVE);
279 /// getGlobalBaseReg - Output the instructions required to put the
280 /// base address to use for accessing globals into a register.
282 SDOperand PPCDAGToDAGISel::getGlobalBaseReg() {
283 if (!GlobalBaseReg) {
284 // Insert the set of GlobalBaseReg into the first MBB of the function
285 MachineBasicBlock &FirstMBB = BB->getParent()->front();
286 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
287 SSARegMap *RegMap = BB->getParent()->getSSARegMap();
288 // FIXME: when we get to LP64, we will need to create the appropriate
289 // type of register here.
290 GlobalBaseReg = RegMap->createVirtualRegister(PPC::GPRCRegisterClass);
291 BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
292 BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg);
294 return CurDAG->getRegister(GlobalBaseReg, MVT::i32);
298 // isIntImmediate - This method tests to see if a constant operand.
299 // If so Imm will receive the 32 bit value.
300 static bool isIntImmediate(SDNode *N, unsigned& Imm) {
301 if (N->getOpcode() == ISD::Constant) {
302 Imm = cast<ConstantSDNode>(N)->getValue();
308 // isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s with
309 // any number of 0s on either side. The 1s are allowed to wrap from LSB to
310 // MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 0x0F0F0000 is
311 // not, since all 1s are not contiguous.
312 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
313 if (isShiftedMask_32(Val)) {
314 // look for the first non-zero bit
315 MB = CountLeadingZeros_32(Val);
316 // look for the first zero bit after the run of ones
317 ME = CountLeadingZeros_32((Val - 1) ^ Val);
320 Val = ~Val; // invert mask
321 if (isShiftedMask_32(Val)) {
322 // effectively look for the first zero bit
323 ME = CountLeadingZeros_32(Val) - 1;
324 // effectively look for the first one bit after the run of zeros
325 MB = CountLeadingZeros_32((Val - 1) ^ Val) + 1;
333 // isRotateAndMask - Returns true if Mask and Shift can be folded into a rotate
334 // and mask opcode and mask operation.
335 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask,
336 unsigned &SH, unsigned &MB, unsigned &ME) {
337 // Don't even go down this path for i64, since different logic will be
338 // necessary for rldicl/rldicr/rldimi.
339 if (N->getValueType(0) != MVT::i32)
343 unsigned Indeterminant = ~0; // bit mask marking indeterminant results
344 unsigned Opcode = N->getOpcode();
345 if (N->getNumOperands() != 2 ||
346 !isIntImmediate(N->getOperand(1).Val, Shift) || (Shift > 31))
349 if (Opcode == ISD::SHL) {
350 // apply shift left to mask if it comes first
351 if (IsShiftMask) Mask = Mask << Shift;
352 // determine which bits are made indeterminant by shift
353 Indeterminant = ~(0xFFFFFFFFu << Shift);
354 } else if (Opcode == ISD::SRL) {
355 // apply shift right to mask if it comes first
356 if (IsShiftMask) Mask = Mask >> Shift;
357 // determine which bits are made indeterminant by shift
358 Indeterminant = ~(0xFFFFFFFFu >> Shift);
359 // adjust for the left rotate
365 // if the mask doesn't intersect any Indeterminant bits
366 if (Mask && !(Mask & Indeterminant)) {
368 // make sure the mask is still a mask (wrap arounds may not be)
369 return isRunOfOnes(Mask, MB, ME);
374 // isOpcWithIntImmediate - This method tests to see if the node is a specific
375 // opcode and that it has a immediate integer right operand.
376 // If so Imm will receive the 32 bit value.
377 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
378 return N->getOpcode() == Opc && isIntImmediate(N->getOperand(1).Val, Imm);
381 // isIntImmediate - This method tests to see if a constant operand.
382 // If so Imm will receive the 32 bit value.
383 static bool isIntImmediate(SDOperand N, unsigned& Imm) {
384 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
385 Imm = (unsigned)CN->getSignExtended();
391 /// SelectBitfieldInsert - turn an or of two masked values into
392 /// the rotate left word immediate then mask insert (rlwimi) instruction.
393 /// Returns true on success, false if the caller still needs to select OR.
395 /// Patterns matched:
396 /// 1. or shl, and 5. or and, and
397 /// 2. or and, shl 6. or shl, shr
398 /// 3. or shr, and 7. or shr, shl
400 SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
401 bool IsRotate = false;
402 unsigned TgtMask = 0xFFFFFFFF, InsMask = 0xFFFFFFFF, SH = 0;
405 SDOperand Op0 = N->getOperand(0);
406 SDOperand Op1 = N->getOperand(1);
408 unsigned Op0Opc = Op0.getOpcode();
409 unsigned Op1Opc = Op1.getOpcode();
411 // Verify that we have the correct opcodes
412 if (ISD::SHL != Op0Opc && ISD::SRL != Op0Opc && ISD::AND != Op0Opc)
414 if (ISD::SHL != Op1Opc && ISD::SRL != Op1Opc && ISD::AND != Op1Opc)
417 // Generate Mask value for Target
418 if (isIntImmediate(Op0.getOperand(1), Value)) {
420 case ISD::SHL: TgtMask <<= Value; break;
421 case ISD::SRL: TgtMask >>= Value; break;
422 case ISD::AND: TgtMask &= Value; break;
428 // Generate Mask value for Insert
429 if (!isIntImmediate(Op1.getOperand(1), Value))
436 if (Op0Opc == ISD::SRL) IsRotate = true;
442 if (Op0Opc == ISD::SHL) IsRotate = true;
449 // If both of the inputs are ANDs and one of them has a logical shift by
450 // constant as its input, make that AND the inserted value so that we can
451 // combine the shift into the rotate part of the rlwimi instruction
452 bool IsAndWithShiftOp = false;
453 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
454 if (Op1.getOperand(0).getOpcode() == ISD::SHL ||
455 Op1.getOperand(0).getOpcode() == ISD::SRL) {
456 if (isIntImmediate(Op1.getOperand(0).getOperand(1), Value)) {
457 SH = Op1.getOperand(0).getOpcode() == ISD::SHL ? Value : 32 - Value;
458 IsAndWithShiftOp = true;
460 } else if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
461 Op0.getOperand(0).getOpcode() == ISD::SRL) {
462 if (isIntImmediate(Op0.getOperand(0).getOperand(1), Value)) {
464 std::swap(TgtMask, InsMask);
465 SH = Op1.getOperand(0).getOpcode() == ISD::SHL ? Value : 32 - Value;
466 IsAndWithShiftOp = true;
471 // Verify that the Target mask and Insert mask together form a full word mask
472 // and that the Insert mask is a run of set bits (which implies both are runs
473 // of set bits). Given that, Select the arguments and generate the rlwimi
476 if (((TgtMask & InsMask) == 0) && isRunOfOnes(InsMask, MB, ME)) {
477 bool fullMask = (TgtMask ^ InsMask) == 0xFFFFFFFF;
478 bool Op0IsAND = Op0Opc == ISD::AND;
479 // Check for rotlwi / rotrwi here, a special case of bitfield insert
480 // where both bitfield halves are sourced from the same value.
481 if (IsRotate && fullMask &&
482 N->getOperand(0).getOperand(0) == N->getOperand(1).getOperand(0)) {
484 Select(Tmp, N->getOperand(0).getOperand(0));
485 return CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Tmp,
486 getI32Imm(SH), getI32Imm(0), getI32Imm(31));
488 SDOperand Tmp1, Tmp2;
489 Select(Tmp1, ((Op0IsAND && fullMask) ? Op0.getOperand(0) : Op0));
490 Select(Tmp2, (IsAndWithShiftOp ? Op1.getOperand(0).getOperand(0)
491 : Op1.getOperand(0)));
492 return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Tmp1, Tmp2,
493 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
498 /// SelectAddrImm - Returns true if the address N can be represented by
499 /// a base register plus a signed 16-bit displacement [r+imm].
500 bool PPCDAGToDAGISel::SelectAddrImm(SDOperand N, SDOperand &Disp,
502 // If this can be more profitably realized as r+r, fail.
503 if (SelectAddrIdx(N, Disp, Base))
506 if (N.getOpcode() == ISD::ADD) {
508 if (isIntImmediate(N.getOperand(1), imm) && isInt16(imm)) {
509 Disp = getI32Imm(imm & 0xFFFF);
510 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
511 Base = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
513 Base = N.getOperand(0);
515 return true; // [r+i]
516 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
517 // Match LOAD (ADD (X, Lo(G))).
518 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
519 && "Cannot handle constant offsets yet!");
520 Disp = N.getOperand(1).getOperand(0); // The global address.
521 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
522 Disp.getOpcode() == ISD::TargetConstantPool);
523 Base = N.getOperand(0);
524 return true; // [&g+r]
526 } else if (N.getOpcode() == ISD::OR) {
528 if (isIntImmediate(N.getOperand(1), imm) && isInt16(imm)) {
529 // If this is an or of disjoint bitfields, we can codegen this as an add
530 // (for better address arithmetic) if the LHS and RHS of the OR are
531 // provably disjoint.
532 uint64_t LHSKnownZero, LHSKnownOne;
533 PPCLowering.ComputeMaskedBits(N.getOperand(0), ~0U,
534 LHSKnownZero, LHSKnownOne);
535 if ((LHSKnownZero|~imm) == ~0U) {
536 // If all of the bits are known zero on the LHS or RHS, the add won't
538 Base = N.getOperand(0);
539 Disp = getI32Imm(imm & 0xFFFF);
543 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
544 // Loading from a constant address.
545 int Addr = (int)CN->getValue();
547 // If this address fits entirely in a 16-bit sext immediate field, codegen
549 if (Addr == (short)Addr) {
550 Disp = getI32Imm(Addr);
551 Base = CurDAG->getRegister(PPC::R0, MVT::i32);
555 // Otherwise, break this down into an LIS + disp.
556 Disp = getI32Imm((short)Addr);
557 Base = CurDAG->getConstant(Addr - (signed short)Addr, MVT::i32);
562 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
563 Base = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
566 return true; // [r+0]
569 /// SelectAddrIdx - Given the specified addressed, check to see if it can be
570 /// represented as an indexed [r+r] operation. Returns false if it can
571 /// be represented by [r+imm], which are preferred.
572 bool PPCDAGToDAGISel::SelectAddrIdx(SDOperand N, SDOperand &Base,
575 if (N.getOpcode() == ISD::ADD) {
576 if (isIntImmediate(N.getOperand(1), imm) && isInt16(imm))
578 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
581 Base = N.getOperand(0);
582 Index = N.getOperand(1);
584 } else if (N.getOpcode() == ISD::OR) {
585 if (isIntImmediate(N.getOperand(1), imm) && isInt16(imm))
586 return false; // r+i can fold it if we can.
588 // If this is an or of disjoint bitfields, we can codegen this as an add
589 // (for better address arithmetic) if the LHS and RHS of the OR are provably
591 uint64_t LHSKnownZero, LHSKnownOne;
592 uint64_t RHSKnownZero, RHSKnownOne;
593 PPCLowering.ComputeMaskedBits(N.getOperand(0), ~0U,
594 LHSKnownZero, LHSKnownOne);
597 PPCLowering.ComputeMaskedBits(N.getOperand(1), ~0U,
598 RHSKnownZero, RHSKnownOne);
599 // If all of the bits are known zero on the LHS or RHS, the add won't
601 if ((LHSKnownZero | RHSKnownZero) == ~0U) {
602 Base = N.getOperand(0);
603 Index = N.getOperand(1);
612 /// SelectAddrIdxOnly - Given the specified addressed, force it to be
613 /// represented as an indexed [r+r] operation.
614 bool PPCDAGToDAGISel::SelectAddrIdxOnly(SDOperand N, SDOperand &Base,
616 // Check to see if we can easily represent this as an [r+r] address. This
617 // will fail if it thinks that the address is more profitably represented as
618 // reg+imm, e.g. where imm = 0.
619 if (SelectAddrIdx(N, Base, Index))
622 // If the operand is an addition, always emit this as [r+r], since this is
623 // better (for code size, and execution, as the memop does the add for free)
624 // than emitting an explicit add.
625 if (N.getOpcode() == ISD::ADD) {
626 Base = N.getOperand(0);
627 Index = N.getOperand(1);
631 // Otherwise, do it the hard way, using R0 as the base register.
632 Base = CurDAG->getRegister(PPC::R0, MVT::i32);
637 /// SelectAddrImmShift - Returns true if the address N can be represented by
638 /// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable
639 /// for use by STD and friends.
640 bool PPCDAGToDAGISel::SelectAddrImmShift(SDOperand N, SDOperand &Disp,
642 // If this can be more profitably realized as r+r, fail.
643 if (SelectAddrIdx(N, Disp, Base))
646 if (N.getOpcode() == ISD::ADD) {
648 if (isIntImmediate(N.getOperand(1), imm) && isInt16(imm) &&
650 Disp = getI32Imm((imm & 0xFFFF) >> 2);
651 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
652 Base = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
654 Base = N.getOperand(0);
656 return true; // [r+i]
657 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
658 // Match LOAD (ADD (X, Lo(G))).
659 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
660 && "Cannot handle constant offsets yet!");
661 Disp = N.getOperand(1).getOperand(0); // The global address.
662 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
663 Disp.getOpcode() == ISD::TargetConstantPool);
664 Base = N.getOperand(0);
665 return true; // [&g+r]
667 } else if (N.getOpcode() == ISD::OR) {
669 if (isIntImmediate(N.getOperand(1), imm) && isInt16(imm) &&
671 // If this is an or of disjoint bitfields, we can codegen this as an add
672 // (for better address arithmetic) if the LHS and RHS of the OR are
673 // provably disjoint.
674 uint64_t LHSKnownZero, LHSKnownOne;
675 PPCLowering.ComputeMaskedBits(N.getOperand(0), ~0U,
676 LHSKnownZero, LHSKnownOne);
677 if ((LHSKnownZero|~imm) == ~0U) {
678 // If all of the bits are known zero on the LHS or RHS, the add won't
680 Base = N.getOperand(0);
681 Disp = getI32Imm((imm & 0xFFFF) >> 2);
685 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
686 // Loading from a constant address.
687 int Addr = (int)CN->getValue();
688 if ((Addr & 3) == 0) {
689 // If this address fits entirely in a 16-bit sext immediate field, codegen
691 if (Addr == (short)Addr) {
692 Disp = getI32Imm(Addr >> 2);
693 Base = CurDAG->getRegister(PPC::R0, MVT::i32);
697 // Otherwise, break this down into an LIS + disp.
698 Disp = getI32Imm((short)Addr >> 2);
699 Base = CurDAG->getConstant(Addr - (signed short)Addr, MVT::i32);
705 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
706 Base = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
709 return true; // [r+0]
713 /// SelectCC - Select a comparison of the specified values with the specified
714 /// condition code, returning the CR# of the expression.
715 SDOperand PPCDAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS,
717 // Always select the LHS.
720 // Use U to determine whether the SETCC immediate range is signed or not.
721 if (MVT::isInteger(LHS.getValueType())) {
722 bool U = ISD::isUnsignedIntSetCC(CC);
724 if (isIntImmediate(RHS, Imm) &&
725 ((U && isUInt16(Imm)) || (!U && isInt16(Imm))))
726 return SDOperand(CurDAG->getTargetNode(U ? PPC::CMPLWI : PPC::CMPWI,
727 MVT::i32, LHS, getI32Imm(Imm & 0xFFFF)), 0);
729 return SDOperand(CurDAG->getTargetNode(U ? PPC::CMPLW : PPC::CMPW, MVT::i32,
731 } else if (LHS.getValueType() == MVT::f32) {
733 return SDOperand(CurDAG->getTargetNode(PPC::FCMPUS, MVT::i32, LHS, RHS), 0);
736 return SDOperand(CurDAG->getTargetNode(PPC::FCMPUD, MVT::i32, LHS, RHS), 0);
740 /// getBCCForSetCC - Returns the PowerPC condition branch mnemonic corresponding
742 static unsigned getBCCForSetCC(ISD::CondCode CC) {
744 default: assert(0 && "Unknown condition!"); abort();
745 case ISD::SETOEQ: // FIXME: This is incorrect see PR642.
746 case ISD::SETEQ: return PPC::BEQ;
747 case ISD::SETONE: // FIXME: This is incorrect see PR642.
748 case ISD::SETNE: return PPC::BNE;
749 case ISD::SETOLT: // FIXME: This is incorrect see PR642.
751 case ISD::SETLT: return PPC::BLT;
752 case ISD::SETOLE: // FIXME: This is incorrect see PR642.
754 case ISD::SETLE: return PPC::BLE;
755 case ISD::SETOGT: // FIXME: This is incorrect see PR642.
757 case ISD::SETGT: return PPC::BGT;
758 case ISD::SETOGE: // FIXME: This is incorrect see PR642.
760 case ISD::SETGE: return PPC::BGE;
762 case ISD::SETO: return PPC::BUN;
763 case ISD::SETUO: return PPC::BNU;
768 /// getCRIdxForSetCC - Return the index of the condition register field
769 /// associated with the SetCC condition, and whether or not the field is
770 /// treated as inverted. That is, lt = 0; ge = 0 inverted.
771 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool& Inv) {
773 default: assert(0 && "Unknown condition!"); abort();
774 case ISD::SETOLT: // FIXME: This is incorrect see PR642.
776 case ISD::SETLT: Inv = false; return 0;
777 case ISD::SETOGE: // FIXME: This is incorrect see PR642.
779 case ISD::SETGE: Inv = true; return 0;
780 case ISD::SETOGT: // FIXME: This is incorrect see PR642.
782 case ISD::SETGT: Inv = false; return 1;
783 case ISD::SETOLE: // FIXME: This is incorrect see PR642.
785 case ISD::SETLE: Inv = true; return 1;
786 case ISD::SETOEQ: // FIXME: This is incorrect see PR642.
787 case ISD::SETEQ: Inv = false; return 2;
788 case ISD::SETONE: // FIXME: This is incorrect see PR642.
789 case ISD::SETNE: Inv = true; return 2;
790 case ISD::SETO: Inv = true; return 3;
791 case ISD::SETUO: Inv = false; return 3;
796 SDOperand PPCDAGToDAGISel::SelectSETCC(SDOperand Op) {
799 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
800 if (isIntImmediate(N->getOperand(1), Imm)) {
801 // We can codegen setcc op, imm very efficiently compared to a brcond.
802 // Check for those cases here.
806 Select(Op, N->getOperand(0));
810 Op = SDOperand(CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op), 0);
811 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(27),
812 getI32Imm(5), getI32Imm(31));
815 SDOperand(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
816 Op, getI32Imm(~0U)), 0);
817 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
821 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(1),
822 getI32Imm(31), getI32Imm(31));
825 SDOperand(CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op), 0);
826 T = SDOperand(CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op), 0);
827 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, T, getI32Imm(1),
828 getI32Imm(31), getI32Imm(31));
831 } else if (Imm == ~0U) { // setcc op, -1
833 Select(Op, N->getOperand(0));
837 Op = SDOperand(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
838 Op, getI32Imm(1)), 0);
839 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
840 SDOperand(CurDAG->getTargetNode(PPC::LI, MVT::i32,
844 Op = SDOperand(CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op), 0);
845 SDNode *AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
847 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDOperand(AD, 0), Op,
851 SDOperand AD = SDOperand(CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op,
853 SDOperand AN = SDOperand(CurDAG->getTargetNode(PPC::AND, MVT::i32, AD,
855 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, AN, getI32Imm(1),
856 getI32Imm(31), getI32Imm(31));
859 Op = SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Op,
860 getI32Imm(1), getI32Imm(31),
862 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, getI32Imm(1));
868 unsigned Idx = getCRIdxForSetCC(CC, Inv);
869 SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
872 // Force the ccreg into CR7.
873 SDOperand CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
875 SDOperand InFlag(0, 0); // Null incoming flag value.
876 CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), CR7Reg, CCReg,
879 if (TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor())
880 IntCR = SDOperand(CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg,
883 IntCR = SDOperand(CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg), 0);
886 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, IntCR,
887 getI32Imm((32-(3-Idx)) & 31),
888 getI32Imm(31), getI32Imm(31));
891 SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, IntCR,
892 getI32Imm((32-(3-Idx)) & 31),
893 getI32Imm(31),getI32Imm(31)), 0);
894 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
898 /// isCallCompatibleAddress - Return true if the specified 32-bit value is
899 /// representable in the immediate field of a Bx instruction.
900 static bool isCallCompatibleAddress(ConstantSDNode *C) {
901 int Addr = C->getValue();
902 if (Addr & 3) return false; // Low 2 bits are implicitly zero.
903 return (Addr << 6 >> 6) == Addr; // Top 6 bits have to be sext of immediate.
906 SDOperand PPCDAGToDAGISel::SelectCALL(SDOperand Op) {
909 Select(Chain, N->getOperand(0));
912 std::vector<SDOperand> CallOperands;
914 if (GlobalAddressSDNode *GASD =
915 dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) {
916 CallOpcode = PPC::BL;
917 CallOperands.push_back(N->getOperand(1));
918 } else if (ExternalSymbolSDNode *ESSDN =
919 dyn_cast<ExternalSymbolSDNode>(N->getOperand(1))) {
920 CallOpcode = PPC::BL;
921 CallOperands.push_back(N->getOperand(1));
922 } else if (isa<ConstantSDNode>(N->getOperand(1)) &&
923 isCallCompatibleAddress(cast<ConstantSDNode>(N->getOperand(1)))) {
924 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(1));
925 CallOpcode = PPC::BLA;
926 CallOperands.push_back(getI32Imm((int)C->getValue() >> 2));
928 // Copy the callee address into the CTR register.
930 Select(Callee, N->getOperand(1));
931 Chain = SDOperand(CurDAG->getTargetNode(PPC::MTCTR, MVT::Other, Callee,
934 // Copy the callee address into R12 on darwin.
935 SDOperand R12 = CurDAG->getRegister(PPC::R12, MVT::i32);
936 Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, Chain, R12, Callee);
938 CallOperands.push_back(R12);
939 CallOpcode = PPC::BCTRL;
942 unsigned GPR_idx = 0, FPR_idx = 0;
943 static const unsigned GPR[] = {
944 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
945 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
947 static const unsigned FPR[] = {
948 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
949 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
952 SDOperand InFlag; // Null incoming flag value.
954 for (unsigned i = 2, e = N->getNumOperands(); i != e; ++i) {
955 unsigned DestReg = 0;
956 MVT::ValueType RegTy = N->getOperand(i).getValueType();
957 if (RegTy == MVT::i32) {
958 assert(GPR_idx < 8 && "Too many int args");
959 DestReg = GPR[GPR_idx++];
961 assert(MVT::isFloatingPoint(N->getOperand(i).getValueType()) &&
962 "Unpromoted integer arg?");
963 assert(FPR_idx < 13 && "Too many fp args");
964 DestReg = FPR[FPR_idx++];
967 if (N->getOperand(i).getOpcode() != ISD::UNDEF) {
969 Select(Val, N->getOperand(i));
970 Chain = CurDAG->getCopyToReg(Chain, DestReg, Val, InFlag);
971 InFlag = Chain.getValue(1);
972 CallOperands.push_back(CurDAG->getRegister(DestReg, RegTy));
976 // Finally, once everything is in registers to pass to the call, emit the
979 CallOperands.push_back(InFlag); // Strong dep on register copies.
981 CallOperands.push_back(Chain); // Weak dep on whatever occurs before
982 Chain = SDOperand(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
985 std::vector<SDOperand> CallResults;
987 // If the call has results, copy the values out of the ret val registers.
988 switch (N->getValueType(0)) {
989 default: assert(0 && "Unexpected ret value!");
990 case MVT::Other: break;
992 if (N->getValueType(1) == MVT::i32) {
993 Chain = CurDAG->getCopyFromReg(Chain, PPC::R4, MVT::i32,
994 Chain.getValue(1)).getValue(1);
995 CallResults.push_back(Chain.getValue(0));
996 Chain = CurDAG->getCopyFromReg(Chain, PPC::R3, MVT::i32,
997 Chain.getValue(2)).getValue(1);
998 CallResults.push_back(Chain.getValue(0));
1000 Chain = CurDAG->getCopyFromReg(Chain, PPC::R3, MVT::i32,
1001 Chain.getValue(1)).getValue(1);
1002 CallResults.push_back(Chain.getValue(0));
1007 Chain = CurDAG->getCopyFromReg(Chain, PPC::F1, N->getValueType(0),
1008 Chain.getValue(1)).getValue(1);
1009 CallResults.push_back(Chain.getValue(0));
1013 CallResults.push_back(Chain);
1014 for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
1015 CodeGenMap[Op.getValue(i)] = CallResults[i];
1016 return CallResults[Op.ResNo];
1019 // Select - Convert the specified operand from a target-independent to a
1020 // target-specific node if it hasn't already been changed.
1021 void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
1023 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
1024 N->getOpcode() < PPCISD::FIRST_NUMBER) {
1026 return; // Already selected.
1029 // If this has already been converted, use it.
1030 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
1031 if (CGMI != CodeGenMap.end()) {
1032 Result = CGMI->second;
1036 switch (N->getOpcode()) {
1039 Result = SelectSETCC(Op);
1042 Result = SelectCALL(Op);
1044 case PPCISD::GlobalBaseReg:
1045 Result = getGlobalBaseReg();
1048 case ISD::FrameIndex: {
1049 int FI = cast<FrameIndexSDNode>(N)->getIndex();
1050 if (N->hasOneUse()) {
1051 Result = CurDAG->SelectNodeTo(N, PPC::ADDI, MVT::i32,
1052 CurDAG->getTargetFrameIndex(FI, MVT::i32),
1056 Result = CodeGenMap[Op] =
1057 SDOperand(CurDAG->getTargetNode(PPC::ADDI, MVT::i32,
1058 CurDAG->getTargetFrameIndex(FI, MVT::i32),
1063 // FIXME: since this depends on the setting of the carry flag from the srawi
1064 // we should really be making notes about that for the scheduler.
1065 // FIXME: It sure would be nice if we could cheaply recognize the
1066 // srl/add/sra pattern the dag combiner will generate for this as
1067 // sra/addze rather than having to handle sdiv ourselves. oh well.
1069 if (isIntImmediate(N->getOperand(1), Imm)) {
1071 Select(N0, N->getOperand(0));
1072 if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
1074 CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
1075 N0, getI32Imm(Log2_32(Imm)));
1076 Result = CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
1077 SDOperand(Op, 0), SDOperand(Op, 1));
1078 } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
1080 CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
1081 N0, getI32Imm(Log2_32(-Imm)));
1083 SDOperand(CurDAG->getTargetNode(PPC::ADDZE, MVT::i32,
1084 SDOperand(Op, 0), SDOperand(Op, 1)),
1086 Result = CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
1091 // Other cases are autogenerated.
1096 // If this is an and of a value rotated between 0 and 31 bits and then and'd
1097 // with a mask, emit rlwinm
1098 if (isIntImmediate(N->getOperand(1), Imm) && (isShiftedMask_32(Imm) ||
1099 isShiftedMask_32(~Imm))) {
1101 unsigned SH, MB, ME;
1102 if (isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB, ME)) {
1103 Select(Val, N->getOperand(0).getOperand(0));
1104 } else if (Imm == 0) {
1105 // AND X, 0 -> 0, not "rlwinm 32".
1106 Select(Result, N->getOperand(1));
1109 Select(Val, N->getOperand(0));
1110 isRunOfOnes(Imm, MB, ME);
1113 Result = CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Val,
1114 getI32Imm(SH), getI32Imm(MB),
1118 // ISD::OR doesn't get all the bitfield insertion fun.
1119 // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert
1120 if (isIntImmediate(N->getOperand(1), Imm) &&
1121 N->getOperand(0).getOpcode() == ISD::OR &&
1122 isIntImmediate(N->getOperand(0).getOperand(1), Imm2)) {
1125 if (isRunOfOnes(Imm, MB, ME)) {
1126 SDOperand Tmp1, Tmp2;
1127 Select(Tmp1, N->getOperand(0).getOperand(0));
1128 Select(Tmp2, N->getOperand(0).getOperand(1));
1129 Result = SDOperand(CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32,
1131 getI32Imm(0), getI32Imm(MB),
1137 // Other cases are autogenerated.
1141 if (SDNode *I = SelectBitfieldInsert(N)) {
1142 Result = CodeGenMap[Op] = SDOperand(I, 0);
1146 // Other cases are autogenerated.
1149 unsigned Imm, SH, MB, ME;
1150 if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
1151 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
1153 Select(Val, N->getOperand(0).getOperand(0));
1154 Result = CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32,
1155 Val, getI32Imm(SH), getI32Imm(MB),
1160 // Other cases are autogenerated.
1164 unsigned Imm, SH, MB, ME;
1165 if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
1166 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
1168 Select(Val, N->getOperand(0).getOperand(0));
1169 Result = CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32,
1170 Val, getI32Imm(SH & 0x1F), getI32Imm(MB),
1175 // Other cases are autogenerated.
1178 case ISD::SELECT_CC: {
1179 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1181 // handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
1182 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1183 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
1184 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
1185 if (N1C->isNullValue() && N3C->isNullValue() &&
1186 N2C->getValue() == 1ULL && CC == ISD::SETNE) {
1188 Select(LHS, N->getOperand(0));
1190 CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
1191 LHS, getI32Imm(~0U));
1192 Result = CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
1193 SDOperand(Tmp, 0), LHS,
1198 SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
1199 unsigned BROpc = getBCCForSetCC(CC);
1201 bool isFP = MVT::isFloatingPoint(N->getValueType(0));
1202 unsigned SelectCCOp;
1203 if (MVT::isInteger(N->getValueType(0)))
1204 SelectCCOp = PPC::SELECT_CC_Int;
1205 else if (N->getValueType(0) == MVT::f32)
1206 SelectCCOp = PPC::SELECT_CC_F4;
1208 SelectCCOp = PPC::SELECT_CC_F8;
1210 Select(N2, N->getOperand(2));
1211 Select(N3, N->getOperand(3));
1212 Result = CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), CCReg,
1213 N2, N3, getI32Imm(BROpc));
1218 Select(Chain, N->getOperand(0));
1219 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
1220 SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC);
1221 Result = CurDAG->SelectNodeTo(N, PPC::COND_BRANCH, MVT::Other,
1222 CondCode, getI32Imm(getBCCForSetCC(CC)),
1223 N->getOperand(4), Chain);
1228 SelectCode(Result, Op);
1232 /// createPPCISelDag - This pass converts a legalized DAG into a
1233 /// PowerPC-specific DAG, ready for instruction scheduling.
1235 FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) {
1236 return new PPCDAGToDAGISel(TM);