1 //===-- PPC32ISelDAGToDAG.cpp - PPC32 pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for 32 bit PowerPC,
11 // converting from a legalized dag to a PPC dag.
13 //===----------------------------------------------------------------------===//
16 #include "PPC32TargetMachine.h"
17 #include "PPC32ISelLowering.h"
18 #include "llvm/CodeGen/MachineConstantPool.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/SSARegMap.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/Constants.h"
27 #include "llvm/GlobalValue.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/MathExtras.h"
33 Statistic<> FusedFP ("ppc-codegen", "Number of fused fp operations");
34 Statistic<> FrameOff("ppc-codegen", "Number of frame idx offsets collapsed");
36 //===--------------------------------------------------------------------===//
37 /// PPC32DAGToDAGISel - PPC32 specific code to select PPC32 machine
38 /// instructions for SelectionDAG operations.
40 class PPC32DAGToDAGISel : public SelectionDAGISel {
41 PPC32TargetLowering PPC32Lowering;
42 unsigned GlobalBaseReg;
44 PPC32DAGToDAGISel(TargetMachine &TM)
45 : SelectionDAGISel(PPC32Lowering), PPC32Lowering(TM) {}
47 virtual bool runOnFunction(Function &Fn) {
48 // Make sure we re-emit a set of the global base reg if necessary
50 return SelectionDAGISel::runOnFunction(Fn);
53 /// getI32Imm - Return a target constant with the specified value, of type
55 inline SDOperand getI32Imm(unsigned Imm) {
56 return CurDAG->getTargetConstant(Imm, MVT::i32);
59 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
60 /// base register. Return the virtual register that holds this value.
61 SDOperand getGlobalBaseReg();
63 // Select - Convert the specified operand from a target-independent to a
64 // target-specific node if it hasn't already been changed.
65 SDOperand Select(SDOperand Op);
67 SDNode *SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
68 unsigned OCHi, unsigned OCLo,
69 bool IsArithmetic = false,
71 SDNode *SelectBitfieldInsert(SDNode *N);
73 /// SelectCC - Select a comparison of the specified values with the
74 /// specified condition code, returning the CR# of the expression.
75 SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
77 /// SelectAddr - Given the specified address, return the two operands for a
78 /// load/store instruction, and return true if it should be an indexed [r+r]
80 bool SelectAddr(SDOperand Addr, SDOperand &Op1, SDOperand &Op2);
82 /// InstructionSelectBasicBlock - This callback is invoked by
83 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
84 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) {
86 // Select target instructions for the DAG.
87 Select(DAG.getRoot());
88 DAG.RemoveDeadNodes();
90 // Emit machine code to BB.
91 ScheduleAndEmitDAG(DAG);
94 virtual const char *getPassName() const {
95 return "PowerPC DAG->DAG Pattern Instruction Selection";
100 /// getGlobalBaseReg - Output the instructions required to put the
101 /// base address to use for accessing globals into a register.
103 SDOperand PPC32DAGToDAGISel::getGlobalBaseReg() {
104 if (!GlobalBaseReg) {
105 // Insert the set of GlobalBaseReg into the first MBB of the function
106 MachineBasicBlock &FirstMBB = BB->getParent()->front();
107 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
108 SSARegMap *RegMap = BB->getParent()->getSSARegMap();
109 GlobalBaseReg = RegMap->createVirtualRegister(PPC32::GPRCRegisterClass);
110 BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
111 BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg);
113 return CurDAG->getRegister(GlobalBaseReg, MVT::i32);
117 // isIntImmediate - This method tests to see if a constant operand.
118 // If so Imm will receive the 32 bit value.
119 static bool isIntImmediate(SDNode *N, unsigned& Imm) {
120 if (N->getOpcode() == ISD::Constant) {
121 Imm = cast<ConstantSDNode>(N)->getValue();
127 // isOprShiftImm - Returns true if the specified operand is a shift opcode with
128 // a immediate shift count less than 32.
129 static bool isOprShiftImm(SDNode *N, unsigned& Opc, unsigned& SH) {
130 Opc = N->getOpcode();
131 return (Opc == ISD::SHL || Opc == ISD::SRL || Opc == ISD::SRA) &&
132 isIntImmediate(N->getOperand(1).Val, SH) && SH < 32;
135 // isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s with
136 // any number of 0s on either side. The 1s are allowed to wrap from LSB to
137 // MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 0x0F0F0000 is
138 // not, since all 1s are not contiguous.
139 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
140 if (isShiftedMask_32(Val)) {
141 // look for the first non-zero bit
142 MB = CountLeadingZeros_32(Val);
143 // look for the first zero bit after the run of ones
144 ME = CountLeadingZeros_32((Val - 1) ^ Val);
147 Val = ~Val; // invert mask
148 if (isShiftedMask_32(Val)) {
149 // effectively look for the first zero bit
150 ME = CountLeadingZeros_32(Val) - 1;
151 // effectively look for the first one bit after the run of zeros
152 MB = CountLeadingZeros_32((Val - 1) ^ Val) + 1;
160 // isRotateAndMask - Returns true if Mask and Shift can be folded in to a rotate
161 // and mask opcode and mask operation.
162 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask,
163 unsigned &SH, unsigned &MB, unsigned &ME) {
165 unsigned Indeterminant = ~0; // bit mask marking indeterminant results
166 unsigned Opcode = N->getOpcode();
167 if (!isIntImmediate(N->getOperand(1).Val, Shift) || (Shift > 31))
170 if (Opcode == ISD::SHL) {
171 // apply shift left to mask if it comes first
172 if (IsShiftMask) Mask = Mask << Shift;
173 // determine which bits are made indeterminant by shift
174 Indeterminant = ~(0xFFFFFFFFu << Shift);
175 } else if (Opcode == ISD::SRA || Opcode == ISD::SRL) {
176 // apply shift right to mask if it comes first
177 if (IsShiftMask) Mask = Mask >> Shift;
178 // determine which bits are made indeterminant by shift
179 Indeterminant = ~(0xFFFFFFFFu >> Shift);
180 // adjust for the left rotate
186 // if the mask doesn't intersect any Indeterminant bits
187 if (Mask && !(Mask & Indeterminant)) {
189 // make sure the mask is still a mask (wrap arounds may not be)
190 return isRunOfOnes(Mask, MB, ME);
195 // isOpcWithIntImmediate - This method tests to see if the node is a specific
196 // opcode and that it has a immediate integer right operand.
197 // If so Imm will receive the 32 bit value.
198 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
199 return N->getOpcode() == Opc && isIntImmediate(N->getOperand(1).Val, Imm);
202 // isOprNot - Returns true if the specified operand is an xor with immediate -1.
203 static bool isOprNot(SDNode *N) {
205 return isOpcWithIntImmediate(N, ISD::XOR, Imm) && (signed)Imm == -1;
208 // Immediate constant composers.
209 // Lo16 - grabs the lo 16 bits from a 32 bit constant.
210 // Hi16 - grabs the hi 16 bits from a 32 bit constant.
211 // HA16 - computes the hi bits required if the lo bits are add/subtracted in
213 static unsigned Lo16(unsigned x) { return x & 0x0000FFFF; }
214 static unsigned Hi16(unsigned x) { return Lo16(x >> 16); }
215 static unsigned HA16(unsigned x) { return Hi16((signed)x - (signed short)x); }
217 // isIntImmediate - This method tests to see if a constant operand.
218 // If so Imm will receive the 32 bit value.
219 static bool isIntImmediate(SDOperand N, unsigned& Imm) {
220 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
221 Imm = (unsigned)CN->getSignExtended();
227 /// SelectBitfieldInsert - turn an or of two masked values into
228 /// the rotate left word immediate then mask insert (rlwimi) instruction.
229 /// Returns true on success, false if the caller still needs to select OR.
231 /// Patterns matched:
232 /// 1. or shl, and 5. or and, and
233 /// 2. or and, shl 6. or shl, shr
234 /// 3. or shr, and 7. or shr, shl
236 SDNode *PPC32DAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
237 bool IsRotate = false;
238 unsigned TgtMask = 0xFFFFFFFF, InsMask = 0xFFFFFFFF, SH = 0;
241 SDOperand Op0 = N->getOperand(0);
242 SDOperand Op1 = N->getOperand(1);
244 unsigned Op0Opc = Op0.getOpcode();
245 unsigned Op1Opc = Op1.getOpcode();
247 // Verify that we have the correct opcodes
248 if (ISD::SHL != Op0Opc && ISD::SRL != Op0Opc && ISD::AND != Op0Opc)
250 if (ISD::SHL != Op1Opc && ISD::SRL != Op1Opc && ISD::AND != Op1Opc)
253 // Generate Mask value for Target
254 if (isIntImmediate(Op0.getOperand(1), Value)) {
256 case ISD::SHL: TgtMask <<= Value; break;
257 case ISD::SRL: TgtMask >>= Value; break;
258 case ISD::AND: TgtMask &= Value; break;
264 // Generate Mask value for Insert
265 if (isIntImmediate(Op1.getOperand(1), Value)) {
270 if (Op0Opc == ISD::SRL) IsRotate = true;
276 if (Op0Opc == ISD::SHL) IsRotate = true;
286 // If both of the inputs are ANDs and one of them has a logical shift by
287 // constant as its input, make that AND the inserted value so that we can
288 // combine the shift into the rotate part of the rlwimi instruction
289 bool IsAndWithShiftOp = false;
290 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
291 if (Op1.getOperand(0).getOpcode() == ISD::SHL ||
292 Op1.getOperand(0).getOpcode() == ISD::SRL) {
293 if (isIntImmediate(Op1.getOperand(0).getOperand(1), Value)) {
294 SH = Op1.getOperand(0).getOpcode() == ISD::SHL ? Value : 32 - Value;
295 IsAndWithShiftOp = true;
297 } else if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
298 Op0.getOperand(0).getOpcode() == ISD::SRL) {
299 if (isIntImmediate(Op0.getOperand(0).getOperand(1), Value)) {
301 std::swap(TgtMask, InsMask);
302 SH = Op1.getOperand(0).getOpcode() == ISD::SHL ? Value : 32 - Value;
303 IsAndWithShiftOp = true;
308 // Verify that the Target mask and Insert mask together form a full word mask
309 // and that the Insert mask is a run of set bits (which implies both are runs
310 // of set bits). Given that, Select the arguments and generate the rlwimi
313 if (((TgtMask & InsMask) == 0) && isRunOfOnes(InsMask, MB, ME)) {
314 bool fullMask = (TgtMask ^ InsMask) == 0xFFFFFFFF;
315 bool Op0IsAND = Op0Opc == ISD::AND;
316 // Check for rotlwi / rotrwi here, a special case of bitfield insert
317 // where both bitfield halves are sourced from the same value.
318 if (IsRotate && fullMask &&
319 N->getOperand(0).getOperand(0) == N->getOperand(1).getOperand(0)) {
320 Op0 = CurDAG->getTargetNode(PPC::RLWINM, MVT::i32,
321 Select(N->getOperand(0).getOperand(0)),
322 getI32Imm(SH), getI32Imm(0), getI32Imm(31));
325 SDOperand Tmp1 = (Op0IsAND && fullMask) ? Select(Op0.getOperand(0))
327 SDOperand Tmp2 = IsAndWithShiftOp ? Select(Op1.getOperand(0).getOperand(0))
328 : Select(Op1.getOperand(0));
329 Op0 = CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Tmp1, Tmp2,
330 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
336 // SelectIntImmediateExpr - Choose code for integer operations with an immediate
338 SDNode *PPC32DAGToDAGISel::SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
339 unsigned OCHi, unsigned OCLo,
342 // Check to make sure this is a constant.
343 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(RHS);
344 // Exit if not a constant.
346 // Extract immediate.
347 unsigned C = (unsigned)CN->getValue();
348 // Negate if required (ISD::SUB).
350 // Get the hi and lo portions of constant.
351 unsigned Hi = IsArithmetic ? HA16(C) : Hi16(C);
352 unsigned Lo = Lo16(C);
354 // If two instructions are needed and usage indicates it would be better to
355 // load immediate into a register, bail out.
356 if (Hi && Lo && CN->use_size() > 2) return false;
358 // Select the first operand.
359 SDOperand Opr0 = Select(LHS);
361 if (Lo) // Add in the lo-part.
362 Opr0 = CurDAG->getTargetNode(OCLo, MVT::i32, Opr0, getI32Imm(Lo));
363 if (Hi) // Add in the hi-part.
364 Opr0 = CurDAG->getTargetNode(OCHi, MVT::i32, Opr0, getI32Imm(Hi));
368 /// SelectAddr - Given the specified address, return the two operands for a
369 /// load/store instruction, and return true if it should be an indexed [r+r]
371 bool PPC32DAGToDAGISel::SelectAddr(SDOperand Addr, SDOperand &Op1,
374 if (Addr.getOpcode() == ISD::ADD) {
375 if (isIntImmediate(Addr.getOperand(1), imm) && isInt16(imm)) {
376 Op1 = getI32Imm(Lo16(imm));
377 if (FrameIndexSDNode *FI =
378 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
380 Op2 = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
382 Op2 = Select(Addr.getOperand(0));
386 Op1 = Select(Addr.getOperand(0));
387 Op2 = Select(Addr.getOperand(1));
388 return true; // [r+r]
392 // Now check if we're dealing with a global, and whether or not we should emit
393 // an optimized load or store for statics.
394 if (GlobalAddressSDNode *GN = dyn_cast<GlobalAddressSDNode>(Addr)) {
395 GlobalValue *GV = GN->getGlobal();
396 if (!GV->hasWeakLinkage() && !GV->isExternal()) {
397 Op1 = CurDAG->getTargetGlobalAddress(GV, MVT::i32);
399 Op2 = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(),
402 Op2 = CurDAG->getTargetNode(PPC::LIS, MVT::i32, Op1);
405 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Addr)) {
407 Op2 = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
409 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Addr)) {
412 Op2 = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(),Op1);
414 Op2 = CurDAG->getTargetNode(PPC::LIS, MVT::i32, Op1);
422 /// SelectCC - Select a comparison of the specified values with the specified
423 /// condition code, returning the CR# of the expression.
424 SDOperand PPC32DAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS,
426 // Always select the LHS.
429 // Use U to determine whether the SETCC immediate range is signed or not.
430 if (MVT::isInteger(LHS.getValueType())) {
431 bool U = ISD::isUnsignedIntSetCC(CC);
433 if (isIntImmediate(RHS, Imm) &&
434 ((U && isUInt16(Imm)) || (!U && isInt16(Imm))))
435 return CurDAG->getTargetNode(U ? PPC::CMPLWI : PPC::CMPWI, MVT::i32,
436 LHS, getI32Imm(Lo16(Imm)));
437 return CurDAG->getTargetNode(U ? PPC::CMPLW : PPC::CMPW, MVT::i32,
440 return CurDAG->getTargetNode(PPC::FCMPU, MVT::i32, LHS, Select(RHS));
444 /// getBCCForSetCC - Returns the PowerPC condition branch mnemonic corresponding
446 static unsigned getBCCForSetCC(ISD::CondCode CC) {
448 default: assert(0 && "Unknown condition!"); abort();
449 case ISD::SETEQ: return PPC::BEQ;
450 case ISD::SETNE: return PPC::BNE;
452 case ISD::SETLT: return PPC::BLT;
454 case ISD::SETLE: return PPC::BLE;
456 case ISD::SETGT: return PPC::BGT;
458 case ISD::SETGE: return PPC::BGE;
463 /// getCRIdxForSetCC - Return the index of the condition register field
464 /// associated with the SetCC condition, and whether or not the field is
465 /// treated as inverted. That is, lt = 0; ge = 0 inverted.
466 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool& Inv) {
468 default: assert(0 && "Unknown condition!"); abort();
470 case ISD::SETLT: Inv = false; return 0;
472 case ISD::SETGE: Inv = true; return 0;
474 case ISD::SETGT: Inv = false; return 1;
476 case ISD::SETLE: Inv = true; return 1;
477 case ISD::SETEQ: Inv = false; return 2;
478 case ISD::SETNE: Inv = true; return 2;
483 // Select - Convert the specified operand from a target-independent to a
484 // target-specific node if it hasn't already been changed.
485 SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
487 if (N->getOpcode() >= ISD::BUILTIN_OP_END)
488 return Op; // Already selected.
490 switch (N->getOpcode()) {
492 std::cerr << "Cannot yet select: ";
496 case ISD::EntryToken: // These leaves remain the same.
498 case ISD::TokenFactor: {
500 if (N->getNumOperands() == 2) {
501 SDOperand Op0 = Select(N->getOperand(0));
502 SDOperand Op1 = Select(N->getOperand(1));
503 New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Op0, Op1);
505 std::vector<SDOperand> Ops;
506 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
507 Ops.push_back(Select(N->getOperand(i)));
508 New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Ops);
512 CurDAG->ReplaceAllUsesWith(N, New.Val);
517 case ISD::CopyFromReg: {
518 SDOperand Chain = Select(N->getOperand(0));
519 if (Chain == N->getOperand(0)) return Op; // No change
520 SDOperand New = CurDAG->getCopyFromReg(Chain,
521 cast<RegisterSDNode>(N->getOperand(1))->getReg(), N->getValueType(0));
522 return New.getValue(Op.ResNo);
524 case ISD::CopyToReg: {
525 SDOperand Chain = Select(N->getOperand(0));
526 SDOperand Reg = N->getOperand(1);
527 SDOperand Val = Select(N->getOperand(2));
528 if (Chain != N->getOperand(0) || Val != N->getOperand(2)) {
529 SDOperand New = CurDAG->getNode(ISD::CopyToReg, MVT::Other,
531 CurDAG->ReplaceAllUsesWith(N, New.Val);
536 case ISD::Constant: {
537 assert(N->getValueType(0) == MVT::i32);
538 unsigned v = (unsigned)cast<ConstantSDNode>(N)->getValue();
539 unsigned Hi = HA16(v);
540 unsigned Lo = Lo16(v);
542 SDOperand Top = CurDAG->getTargetNode(PPC::LIS, MVT::i32,
544 CurDAG->SelectNodeTo(N, MVT::i32, PPC::ORI, Top, getI32Imm(v & 0xFFFF));
546 CurDAG->SelectNodeTo(N, MVT::i32, PPC::LI, getI32Imm(v));
548 CurDAG->SelectNodeTo(N, MVT::i32, PPC::LIS, getI32Imm(v >> 16));
552 case ISD::ConstantFP: { // FIXME: this should get sucked into the legalizer
553 MachineConstantPool *CP = CurDAG->getMachineFunction().getConstantPool();
554 Constant *CFP = ConstantFP::get(Type::FloatTy,
555 cast<ConstantFPSDNode>(N)->getValue());
556 SDOperand CPN = CurDAG->getConstantPool(CP->getConstantPoolIndex(CFP),
560 Tmp = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(),CPN);
562 Tmp = CurDAG->getTargetNode(PPC::LIS, MVT::i32, CPN);
563 CurDAG->SelectNodeTo(N, N->getValueType(0), PPC::LFS, CPN, Tmp);
567 if (N->getValueType(0) == MVT::i32)
568 CurDAG->SelectNodeTo(N, MVT::i32, PPC::IMPLICIT_DEF_GPR);
570 CurDAG->SelectNodeTo(N, N->getValueType(0), PPC::IMPLICIT_DEF_FP);
572 case ISD::FrameIndex: {
573 int FI = cast<FrameIndexSDNode>(N)->getIndex();
574 CurDAG->SelectNodeTo(N, MVT::i32, PPC::ADDI,
575 CurDAG->getTargetFrameIndex(FI, MVT::i32),
579 case ISD::ConstantPool: {
580 unsigned CPIIdx = cast<ConstantPoolSDNode>(N)->getIndex();
581 SDOperand Tmp, CPI = CurDAG->getTargetConstantPool(CPIIdx, MVT::i32);
583 Tmp = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(),CPI);
585 Tmp = CurDAG->getTargetNode(PPC::LIS, MVT::i32, CPI);
586 CurDAG->SelectNodeTo(N, MVT::i32, PPC::LA, Tmp, CPI);
589 case ISD::GlobalAddress: {
590 GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
592 SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i32);
594 Tmp = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(), GA);
596 Tmp = CurDAG->getTargetNode(PPC::LIS, MVT::i32, GA);
598 if (GV->hasWeakLinkage() || GV->isExternal())
599 CurDAG->SelectNodeTo(N, MVT::i32, PPC::LWZ, GA, Tmp);
601 CurDAG->SelectNodeTo(N, MVT::i32, PPC::LA, Tmp, GA);
604 case ISD::SIGN_EXTEND_INREG:
605 switch(cast<VTSDNode>(N->getOperand(1))->getVT()) {
606 default: assert(0 && "Illegal type in SIGN_EXTEND_INREG"); break;
608 CurDAG->SelectNodeTo(N, MVT::i32, PPC::EXTSH, Select(N->getOperand(0)));
611 CurDAG->SelectNodeTo(N, MVT::i32, PPC::EXTSB, Select(N->getOperand(0)));
616 assert(N->getValueType(0) == MVT::i32);
617 CurDAG->SelectNodeTo(N, MVT::i32, PPC::CNTLZW, Select(N->getOperand(0)));
620 MVT::ValueType Ty = N->getValueType(0);
621 if (Ty == MVT::i32) {
622 if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0), N->getOperand(1),
623 PPC::ADDIS, PPC::ADDI, true)) {
624 CurDAG->ReplaceAllUsesWith(N, I);
627 CurDAG->SelectNodeTo(N, Ty, PPC::ADD, Select(N->getOperand(0)),
628 Select(N->getOperand(1)));
633 if (!NoExcessFPPrecision) { // Match FMA ops
634 if (N->getOperand(0).getOpcode() == ISD::MUL &&
635 N->getOperand(0).Val->hasOneUse()) {
636 ++FusedFP; // Statistic
637 CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FMADD : PPC::FMADDS,
638 Select(N->getOperand(0).getOperand(0)),
639 Select(N->getOperand(0).getOperand(1)),
640 Select(N->getOperand(1)));
642 } else if (N->getOperand(1).getOpcode() == ISD::MUL &&
643 N->getOperand(1).hasOneUse()) {
644 ++FusedFP; // Statistic
645 CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FMADD : PPC::FMADDS,
646 Select(N->getOperand(1).getOperand(0)),
647 Select(N->getOperand(1).getOperand(1)),
648 Select(N->getOperand(0)));
653 CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FADD : PPC::FADDS,
654 Select(N->getOperand(0)), Select(N->getOperand(1)));
658 MVT::ValueType Ty = N->getValueType(0);
659 if (Ty == MVT::i32) {
661 if (isIntImmediate(N->getOperand(0), Imm) && isInt16(Imm)) {
663 CurDAG->SelectNodeTo(N, Ty, PPC::NEG, Select(N->getOperand(1)));
665 CurDAG->SelectNodeTo(N, Ty, PPC::SUBFIC, Select(N->getOperand(1)),
666 getI32Imm(Lo16(Imm)));
669 if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0), N->getOperand(1),
670 PPC::ADDIS, PPC::ADDI, true, true)) {
671 CurDAG->ReplaceAllUsesWith(N, I);
674 CurDAG->SelectNodeTo(N, Ty, PPC::SUBF, Select(N->getOperand(1)),
675 Select(N->getOperand(0)));
680 if (!NoExcessFPPrecision) { // Match FMA ops
681 if (N->getOperand(0).getOpcode() == ISD::MUL &&
682 N->getOperand(0).Val->hasOneUse()) {
683 ++FusedFP; // Statistic
684 CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FMSUB : PPC::FMSUBS,
685 Select(N->getOperand(0).getOperand(0)),
686 Select(N->getOperand(0).getOperand(1)),
687 Select(N->getOperand(1)));
689 } else if (N->getOperand(1).getOpcode() == ISD::MUL &&
690 N->getOperand(1).Val->hasOneUse()) {
691 ++FusedFP; // Statistic
692 CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FNMSUB : PPC::FNMSUBS,
693 Select(N->getOperand(1).getOperand(0)),
694 Select(N->getOperand(1).getOperand(1)),
695 Select(N->getOperand(0)));
699 CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FSUB : PPC::FSUBS,
700 Select(N->getOperand(0)),
701 Select(N->getOperand(1)));
706 if (isIntImmediate(N->getOperand(1), Imm) && isInt16(Imm)) {
707 CurDAG->SelectNodeTo(N, N->getValueType(0), PPC::MULLI,
708 Select(N->getOperand(0)), getI32Imm(Lo16(Imm)));
711 switch (N->getValueType(0)) {
712 default: assert(0 && "Unhandled multiply type!");
713 case MVT::i32: Opc = PPC::MULLW; break;
714 case MVT::f32: Opc = PPC::FMULS; break;
715 case MVT::f64: Opc = PPC::FMUL; break;
717 CurDAG->SelectNodeTo(N, MVT::i32, Opc, Select(N->getOperand(0)),
718 Select(N->getOperand(1)));
723 if (isIntImmediate(N->getOperand(1), Imm)) {
724 if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
726 CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
727 Select(N->getOperand(0)),
728 getI32Imm(Log2_32(Imm)));
729 CurDAG->SelectNodeTo(N, MVT::i32, PPC::ADDZE,
730 Op.getValue(0), Op.getValue(1));
732 } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
734 CurDAG->getTargetNode(PPC::SRAWI, MVT::Flag, MVT::i32,
735 Select(N->getOperand(0)),
736 getI32Imm(Log2_32(-Imm)));
738 CurDAG->getTargetNode(PPC::ADDZE, MVT::i32, Op.getValue(1),
740 CurDAG->SelectNodeTo(N, MVT::i32, PPC::NEG, PT);
744 assert(0 && "SDIV not implemented yet!");
748 assert(N->getValueType(0) == MVT::i32);
749 CurDAG->SelectNodeTo(N, MVT::i32, PPC::MULHW, Select(N->getOperand(0)),
750 Select(N->getOperand(1)));
753 assert(N->getValueType(0) == MVT::i32);
754 CurDAG->SelectNodeTo(N, MVT::i32, PPC::MULHWU, Select(N->getOperand(0)),
755 Select(N->getOperand(1)));
759 // If this is an and of a value rotated between 0 and 31 bits and then and'd
760 // with a mask, emit rlwinm
761 if (isIntImmediate(N->getOperand(1), Imm) && (isShiftedMask_32(Imm) ||
762 isShiftedMask_32(~Imm))) {
765 if (isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB, ME)) {
766 Val = Select(N->getOperand(0).getOperand(0));
768 Val = Select(N->getOperand(0));
769 isRunOfOnes(Imm, MB, ME);
772 CurDAG->SelectNodeTo(N, MVT::i32, PPC::RLWINM, Val, getI32Imm(SH),
773 getI32Imm(MB), getI32Imm(ME));
776 // If this is an and with an immediate that isn't a mask, then codegen it as
777 // high and low 16 bit immediate ands.
778 if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0),
780 PPC::ANDISo, PPC::ANDIo)) {
781 CurDAG->ReplaceAllUsesWith(N, I);
785 // Finally, check for the case where we are being asked to select
786 // and (not(a), b) or and (a, not(b)) which can be selected as andc.
787 if (isOprNot(N->getOperand(0).Val))
788 CurDAG->SelectNodeTo(N, MVT::i32, PPC::ANDC, Select(N->getOperand(1)),
789 Select(N->getOperand(0).getOperand(0)));
790 else if (isOprNot(N->getOperand(1).Val))
791 CurDAG->SelectNodeTo(N, MVT::i32, PPC::ANDC, Select(N->getOperand(0)),
792 Select(N->getOperand(1).getOperand(0)));
794 CurDAG->SelectNodeTo(N, MVT::i32, PPC::AND, Select(N->getOperand(0)),
795 Select(N->getOperand(1)));
799 if (SDNode *I = SelectBitfieldInsert(N)) {
800 CurDAG->ReplaceAllUsesWith(N, I);
804 if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0),
806 PPC::ORIS, PPC::ORI)) {
807 CurDAG->ReplaceAllUsesWith(N, I);
811 // Finally, check for the case where we are being asked to select
812 // 'or (not(a), b)' or 'or (a, not(b))' which can be selected as orc.
813 if (isOprNot(N->getOperand(0).Val))
814 CurDAG->SelectNodeTo(N, MVT::i32, PPC::ORC, Select(N->getOperand(1)),
815 Select(N->getOperand(0).getOperand(0)));
816 else if (isOprNot(N->getOperand(1).Val))
817 CurDAG->SelectNodeTo(N, MVT::i32, PPC::ORC, Select(N->getOperand(0)),
818 Select(N->getOperand(1).getOperand(0)));
820 CurDAG->SelectNodeTo(N, MVT::i32, PPC::OR, Select(N->getOperand(0)),
821 Select(N->getOperand(1)));
824 // Check whether or not this node is a logical 'not'. This is represented
825 // by llvm as a xor with the constant value -1 (all bits set). If this is a
826 // 'not', then fold 'or' into 'nor', and so forth for the supported ops.
829 SDOperand Val = Select(N->getOperand(0));
830 switch (Val.getTargetOpcode()) {
831 default: Opc = 0; break;
832 case PPC::OR: Opc = PPC::NOR; break;
833 case PPC::AND: Opc = PPC::NAND; break;
834 case PPC::XOR: Opc = PPC::EQV; break;
837 CurDAG->SelectNodeTo(N, MVT::i32, Opc, Val.getOperand(0),
840 CurDAG->SelectNodeTo(N, MVT::i32, PPC::NOR, Val, Val);
843 // If this is a xor with an immediate other than -1, then codegen it as high
844 // and low 16 bit immediate xors.
845 if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0),
847 PPC::XORIS, PPC::XORI)) {
848 CurDAG->ReplaceAllUsesWith(N, I);
852 // Finally, check for the case where we are being asked to select
853 // xor (not(a), b) which is equivalent to not(xor a, b), which is eqv
854 if (isOprNot(N->getOperand(0).Val))
855 CurDAG->SelectNodeTo(N, MVT::i32, PPC::EQV,
856 Select(N->getOperand(0).getOperand(0)),
857 Select(N->getOperand(1)));
859 CurDAG->SelectNodeTo(N, MVT::i32, PPC::XOR, Select(N->getOperand(0)),
860 Select(N->getOperand(1)));
863 unsigned Imm, SH, MB, ME;
864 if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
865 isRotateAndMask(N, Imm, true, SH, MB, ME))
866 CurDAG->SelectNodeTo(N, MVT::i32, PPC::RLWINM,
867 Select(N->getOperand(0).getOperand(0)),
868 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
869 else if (isIntImmediate(N->getOperand(1), Imm))
870 CurDAG->SelectNodeTo(N, MVT::i32, PPC::RLWINM, Select(N->getOperand(0)),
871 getI32Imm(Imm), getI32Imm(0), getI32Imm(31-Imm));
873 CurDAG->SelectNodeTo(N, MVT::i32, PPC::SLW, Select(N->getOperand(0)),
874 Select(N->getOperand(1)));
878 unsigned Imm, SH, MB, ME;
879 if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
880 isRotateAndMask(N, Imm, true, SH, MB, ME))
881 CurDAG->SelectNodeTo(N, MVT::i32, PPC::RLWINM,
882 Select(N->getOperand(0).getOperand(0)),
883 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
884 else if (isIntImmediate(N->getOperand(1), Imm))
885 CurDAG->SelectNodeTo(N, MVT::i32, PPC::RLWINM, Select(N->getOperand(0)),
886 getI32Imm(32-Imm), getI32Imm(Imm), getI32Imm(31));
888 CurDAG->SelectNodeTo(N, MVT::i32, PPC::SRW, Select(N->getOperand(0)),
889 Select(N->getOperand(1)));
893 unsigned Imm, SH, MB, ME;
894 if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
895 isRotateAndMask(N, Imm, true, SH, MB, ME))
896 CurDAG->SelectNodeTo(N, MVT::i32, PPC::RLWINM,
897 Select(N->getOperand(0).getOperand(0)),
898 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
899 else if (isIntImmediate(N->getOperand(1), Imm))
900 CurDAG->SelectNodeTo(N, MVT::i32, PPC::SRAWI, Select(N->getOperand(0)),
903 CurDAG->SelectNodeTo(N, MVT::i32, PPC::SRAW, Select(N->getOperand(0)),
904 Select(N->getOperand(1)));
908 CurDAG->SelectNodeTo(N, N->getValueType(0), PPC::FABS,
909 Select(N->getOperand(0)));
912 assert(MVT::f64 == N->getValueType(0) &&
913 MVT::f32 == N->getOperand(0).getValueType() && "Illegal FP_EXTEND");
914 CurDAG->SelectNodeTo(N, MVT::f64, PPC::FMR, Select(N->getOperand(0)));
917 assert(MVT::f32 == N->getValueType(0) &&
918 MVT::f64 == N->getOperand(0).getValueType() && "Illegal FP_ROUND");
919 CurDAG->SelectNodeTo(N, MVT::f32, PPC::FRSP, Select(N->getOperand(0)));
922 SDOperand Val = Select(N->getOperand(0));
923 MVT::ValueType Ty = N->getValueType(0);
924 if (Val.Val->hasOneUse()) {
926 switch (Val.getTargetOpcode()) {
927 default: Opc = 0; break;
928 case PPC::FABS: Opc = PPC::FNABS; break;
929 case PPC::FMADD: Opc = PPC::FNMADD; break;
930 case PPC::FMADDS: Opc = PPC::FNMADDS; break;
931 case PPC::FMSUB: Opc = PPC::FNMSUB; break;
932 case PPC::FMSUBS: Opc = PPC::FNMSUBS; break;
934 // If we inverted the opcode, then emit the new instruction with the
935 // inverted opcode and the original instruction's operands. Otherwise,
936 // fall through and generate a fneg instruction.
938 if (PPC::FNABS == Opc)
939 CurDAG->SelectNodeTo(N, Ty, Opc, Val.getOperand(0));
941 CurDAG->SelectNodeTo(N, Ty, Opc, Val.getOperand(0),
942 Val.getOperand(1), Val.getOperand(2));
946 CurDAG->SelectNodeTo(N, Ty, PPC::FNEG, Val);
950 MVT::ValueType Ty = N->getValueType(0);
951 CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FSQRT : PPC::FSQRTS,
952 Select(N->getOperand(0)));
958 case ISD::SEXTLOAD: {
960 bool isIdx = SelectAddr(N->getOperand(1), Op1, Op2);
962 MVT::ValueType TypeBeingLoaded = (N->getOpcode() == ISD::LOAD) ?
963 N->getValueType(0) : cast<VTSDNode>(N->getOperand(3))->getVT();
965 switch (TypeBeingLoaded) {
966 default: N->dump(); assert(0 && "Cannot load this type!");
968 case MVT::i8: Opc = isIdx ? PPC::LBZX : PPC::LBZ; break;
970 if (N->getOpcode() == ISD::SEXTLOAD) { // SEXT load?
971 Opc = isIdx ? PPC::LHAX : PPC::LHA;
973 Opc = isIdx ? PPC::LHZX : PPC::LHZ;
976 case MVT::i32: Opc = isIdx ? PPC::LWZX : PPC::LWZ; break;
977 case MVT::f32: Opc = isIdx ? PPC::LFSX : PPC::LFS; break;
978 case MVT::f64: Opc = isIdx ? PPC::LFDX : PPC::LFD; break;
981 CurDAG->SelectNodeTo(N, N->getValueType(0), MVT::Other, Opc,
982 Op1, Op2, Select(N->getOperand(0)));
986 case ISD::TRUNCSTORE:
988 SDOperand AddrOp1, AddrOp2;
989 bool isIdx = SelectAddr(N->getOperand(2), AddrOp1, AddrOp2);
992 if (N->getOpcode() == ISD::STORE) {
993 switch (N->getOperand(1).getValueType()) {
994 default: assert(0 && "unknown Type in store");
995 case MVT::i32: Opc = isIdx ? PPC::STWX : PPC::STW; break;
996 case MVT::f64: Opc = isIdx ? PPC::STFDX : PPC::STFD; break;
997 case MVT::f32: Opc = isIdx ? PPC::STFSX : PPC::STFS; break;
999 } else { //ISD::TRUNCSTORE
1000 switch(cast<VTSDNode>(N->getOperand(4))->getVT()) {
1001 default: assert(0 && "unknown Type in store");
1003 case MVT::i8: Opc = isIdx ? PPC::STBX : PPC::STB; break;
1004 case MVT::i16: Opc = isIdx ? PPC::STHX : PPC::STH; break;
1008 CurDAG->SelectNodeTo(N, MVT::Other, Opc, Select(N->getOperand(1)),
1009 AddrOp1, AddrOp2, Select(N->getOperand(0)));
1015 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
1016 if (isIntImmediate(N->getOperand(1), Imm)) {
1017 // We can codegen setcc op, imm very efficiently compared to a brcond.
1018 // Check for those cases here.
1021 SDOperand Op = Select(N->getOperand(0));
1023 default: assert(0 && "Unhandled SetCC condition"); abort();
1025 Op = CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op);
1026 CurDAG->SelectNodeTo(N, MVT::i32, PPC::RLWINM, Op, getI32Imm(27),
1027 getI32Imm(5), getI32Imm(31));
1030 SDOperand AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
1031 Op, getI32Imm(~0U));
1032 CurDAG->SelectNodeTo(N, MVT::i32, PPC::SUBFE, AD, Op, AD.getValue(1));
1036 CurDAG->SelectNodeTo(N, MVT::i32, PPC::RLWINM, Op, getI32Imm(1),
1037 getI32Imm(31), getI32Imm(31));
1040 SDOperand T = CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op);
1041 T = CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op);;
1042 CurDAG->SelectNodeTo(N, MVT::i32, PPC::RLWINM, T, getI32Imm(1),
1043 getI32Imm(31), getI32Imm(31));
1048 } else if (Imm == ~0U) { // setcc op, -1
1049 SDOperand Op = Select(N->getOperand(0));
1051 default: assert(0 && "Unhandled SetCC condition"); abort();
1053 Op = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
1055 CurDAG->SelectNodeTo(N, MVT::i32, PPC::ADDZE,
1056 CurDAG->getTargetNode(PPC::LI, MVT::i32,
1061 Op = CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op);
1062 SDOperand AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, Op,
1064 CurDAG->SelectNodeTo(N, MVT::i32, PPC::SUBFE, AD, Op, AD.getValue(1));
1068 SDOperand AD = CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op,
1070 SDOperand AN = CurDAG->getTargetNode(PPC::AND, MVT::i32, AD, Op);
1071 CurDAG->SelectNodeTo(N, MVT::i32, PPC::RLWINM, AN, getI32Imm(1),
1072 getI32Imm(31), getI32Imm(31));
1076 Op = CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Op, getI32Imm(1),
1077 getI32Imm(31), getI32Imm(31));
1078 CurDAG->SelectNodeTo(N, MVT::i32, PPC::XORI, Op, getI32Imm(1));
1086 unsigned Idx = getCRIdxForSetCC(CC, Inv);
1088 SelectCC(Select(N->getOperand(0)), Select(N->getOperand(1)), CC);
1090 if (TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor()) {
1091 IntCR = CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CCReg);
1093 assert(0 && "Not imp yet!");
1094 // FIXME: HOW DO WE DO THIS??
1096 //SDOperand CR7Op = CurDAG->getCopyToReg();
1097 BuildMI(BB, PPC::MCRF, 1, PPC::CR7).addReg(CCReg);
1098 BuildMI(BB, PPC::MFCR, 0, IntCR);
1103 CurDAG->SelectNodeTo(N, MVT::i32, PPC::RLWINM, IntCR,
1104 getI32Imm(32-(3-Idx)), getI32Imm(31), getI32Imm(31));
1107 CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, IntCR,
1108 getI32Imm(32-(3-Idx)), getI32Imm(31),getI32Imm(31));
1109 CurDAG->SelectNodeTo(N, MVT::i32, PPC::XORI, Tmp, getI32Imm(1));
1115 case ISD::CALLSEQ_START:
1116 case ISD::CALLSEQ_END: {
1117 unsigned Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
1118 unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
1119 PPC::ADJCALLSTACKDOWN : PPC::ADJCALLSTACKUP;
1120 CurDAG->SelectNodeTo(N, MVT::Other, Opc,
1121 getI32Imm(Amt), Select(N->getOperand(0)));
1125 case ISD::TAILCALL: {
1126 SDOperand Chain = Select(N->getOperand(0));
1128 unsigned CallOpcode;
1129 std::vector<SDOperand> CallOperands;
1131 if (GlobalAddressSDNode *GASD =
1132 dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) {
1133 CallOpcode = PPC::CALLpcrel;
1134 CallOperands.push_back(CurDAG->getTargetGlobalAddress(GASD->getGlobal(),
1136 } else if (ExternalSymbolSDNode *ESSDN =
1137 dyn_cast<ExternalSymbolSDNode>(N->getOperand(1))) {
1138 CallOpcode = PPC::CALLpcrel;
1139 CallOperands.push_back(N->getOperand(1));
1141 // Copy the callee address into the CTR register.
1142 SDOperand Callee = Select(N->getOperand(1));
1143 Chain = CurDAG->getTargetNode(PPC::MTCTR, MVT::Other, Callee, Chain);
1145 // Copy the callee address into R12 on darwin.
1146 SDOperand R12 = CurDAG->getRegister(PPC::R12, MVT::i32);
1147 Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, R12, Callee, Chain);
1149 CallOperands.push_back(getI32Imm(20)); // Information to encode indcall
1150 CallOperands.push_back(getI32Imm(0)); // Information to encode indcall
1151 CallOperands.push_back(R12);
1152 CallOpcode = PPC::CALLindirect;
1155 unsigned GPR_idx = 0, FPR_idx = 0;
1156 static const unsigned GPR[] = {
1157 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1158 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1160 static const unsigned FPR[] = {
1161 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1162 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1165 for (unsigned i = 2, e = N->getNumOperands(); i != e; ++i)
1166 if (N->getOperand(i).getOpcode() != ISD::UNDEF) {
1167 unsigned DestReg = 0;
1168 MVT::ValueType RegTy;
1169 if (N->getOperand(i).getValueType() == MVT::i32) {
1170 assert(GPR_idx < 8 && "Too many int args");
1171 DestReg = GPR[GPR_idx++];
1174 assert(MVT::isFloatingPoint(N->getOperand(i).getValueType()) &&
1175 "Unpromoted integer arg?");
1176 assert(FPR_idx < 13 && "Too many fp args");
1177 DestReg = FPR[FPR_idx++];
1178 RegTy = MVT::f64; // Even if this is really f32!
1181 SDOperand Reg = CurDAG->getRegister(DestReg, RegTy);
1182 Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, Chain, Reg,
1183 Select(N->getOperand(i)));
1184 CallOperands.push_back(Reg);
1187 // Finally, once everything is in registers to pass to the call, emit the
1189 CallOperands.push_back(Chain);
1190 Chain = CurDAG->getTargetNode(CallOpcode, MVT::Other, CallOperands);
1192 std::vector<SDOperand> CallResults;
1194 // If the call has results, copy the values out of the ret val registers.
1195 switch (N->getValueType(0)) {
1196 default: assert(0 && "Unexpected ret value!");
1197 case MVT::Other: break;
1199 if (N->getValueType(1) == MVT::i32) {
1200 Chain = CurDAG->getCopyFromReg(Chain, PPC::R4, MVT::i32).getValue(1);
1201 CallResults.push_back(Chain.getValue(0));
1202 Chain = CurDAG->getCopyFromReg(Chain, PPC::R3, MVT::i32).getValue(1);
1203 CallResults.push_back(Chain.getValue(0));
1205 Chain = CurDAG->getCopyFromReg(Chain, PPC::R3, MVT::i32).getValue(1);
1206 CallResults.push_back(Chain.getValue(0));
1211 Chain = CurDAG->getCopyFromReg(Chain, PPC::F1, MVT::f64).getValue(1);
1212 CallResults.push_back(Chain.getValue(0));
1216 CallResults.push_back(Chain);
1217 CurDAG->ReplaceAllUsesWith(N, CallResults);
1218 return CallResults[Op.ResNo];
1221 SDOperand Chain = Select(N->getOperand(0)); // Token chain.
1223 if (N->getNumOperands() > 1) {
1224 SDOperand Val = Select(N->getOperand(1));
1225 switch (N->getOperand(1).getValueType()) {
1226 default: assert(0 && "Unknown return type!");
1229 Chain = CurDAG->getCopyToReg(Chain, PPC::F1, Val);
1232 Chain = CurDAG->getCopyToReg(Chain, PPC::R3, Val);
1236 if (N->getNumOperands() > 2) {
1237 assert(N->getOperand(1).getValueType() == MVT::i32 &&
1238 N->getOperand(2).getValueType() == MVT::i32 &&
1239 N->getNumOperands() == 2 && "Unknown two-register ret value!");
1240 Val = Select(N->getOperand(2));
1241 Chain = CurDAG->getCopyToReg(Chain, PPC::R4, Val);
1245 // Finally, select this to a blr (return) instruction.
1246 CurDAG->SelectNodeTo(N, MVT::Other, PPC::BLR, Chain);
1250 CurDAG->SelectNodeTo(N, MVT::Other, PPC::B, N->getOperand(1),
1251 Select(N->getOperand(0)));
1254 case ISD::BRTWOWAY_CC: {
1255 SDOperand Chain = Select(N->getOperand(0));
1256 MachineBasicBlock *Dest =
1257 cast<BasicBlockSDNode>(N->getOperand(4))->getBasicBlock();
1258 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
1259 SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC);
1260 unsigned Opc = getBCCForSetCC(CC);
1262 // If this is a two way branch, then grab the fallthrough basic block
1263 // argument and build a PowerPC branch pseudo-op, suitable for long branch
1264 // conversion if necessary by the branch selection pass. Otherwise, emit a
1265 // standard conditional branch.
1266 if (N->getOpcode() == ISD::BRTWOWAY_CC) {
1267 MachineBasicBlock *Fallthrough =
1268 cast<BasicBlockSDNode>(N->getOperand(5))->getBasicBlock();
1269 SDOperand CB = CurDAG->getTargetNode(PPC::COND_BRANCH, MVT::Other,
1270 CondCode, getI32Imm(Opc),
1271 N->getOperand(4), N->getOperand(5),
1273 CurDAG->SelectNodeTo(N, MVT::Other, PPC::B, N->getOperand(5), CB);
1275 // Iterate to the next basic block
1276 ilist<MachineBasicBlock>::iterator It = BB;
1279 // If the fallthrough path is off the end of the function, which would be
1280 // undefined behavior, set it to be the same as the current block because
1281 // we have nothing better to set it to, and leaving it alone will cause
1282 // the PowerPC Branch Selection pass to crash.
1283 if (It == BB->getParent()->end()) It = Dest;
1284 CurDAG->SelectNodeTo(N, MVT::Other, PPC::COND_BRANCH, CondCode,
1285 getI32Imm(Opc), N->getOperand(4),
1286 CurDAG->getBasicBlock(It), Chain);
1291 return SDOperand(N, Op.ResNo);
1295 /// createPPC32ISelDag - This pass converts a legalized DAG into a
1296 /// PowerPC-specific DAG, ready for instruction scheduling.
1298 FunctionPass *llvm::createPPC32ISelDag(TargetMachine &TM) {
1299 return new PPC32DAGToDAGISel(TM);