1 //===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for PowerPC,
11 // converting from a legalized dag to a PPC dag.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "ppc-codegen"
17 #include "PPCPredicates.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCHazardRecognizers.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/SelectionDAGISel.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Constants.h"
28 #include "llvm/Function.h"
29 #include "llvm/GlobalValue.h"
30 #include "llvm/Intrinsics.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
38 //===--------------------------------------------------------------------===//
39 /// PPCDAGToDAGISel - PPC specific code to select PPC machine
40 /// instructions for SelectionDAG operations.
42 class PPCDAGToDAGISel : public SelectionDAGISel {
43 const PPCTargetMachine &TM;
44 const PPCTargetLowering &PPCLowering;
45 const PPCSubtarget &PPCSubTarget;
46 unsigned GlobalBaseReg;
48 explicit PPCDAGToDAGISel(PPCTargetMachine &tm)
49 : SelectionDAGISel(tm), TM(tm),
50 PPCLowering(*TM.getTargetLowering()),
51 PPCSubTarget(*TM.getSubtargetImpl()) {}
53 virtual bool runOnMachineFunction(MachineFunction &MF) {
54 // Make sure we re-emit a set of the global base reg if necessary
56 SelectionDAGISel::runOnMachineFunction(MF);
62 /// getI32Imm - Return a target constant with the specified value, of type
64 inline SDValue getI32Imm(unsigned Imm) {
65 return CurDAG->getTargetConstant(Imm, MVT::i32);
68 /// getI64Imm - Return a target constant with the specified value, of type
70 inline SDValue getI64Imm(uint64_t Imm) {
71 return CurDAG->getTargetConstant(Imm, MVT::i64);
74 /// getSmallIPtrImm - Return a target constant of pointer type.
75 inline SDValue getSmallIPtrImm(unsigned Imm) {
76 return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy());
79 /// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s
80 /// with any number of 0s on either side. The 1s are allowed to wrap from
81 /// LSB to MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs.
82 /// 0x0F0F0000 is not, since all 1s are not contiguous.
83 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME);
86 /// isRotateAndMask - Returns true if Mask and Shift can be folded into a
87 /// rotate and mask opcode and mask operation.
88 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool isShiftMask,
89 unsigned &SH, unsigned &MB, unsigned &ME);
91 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
92 /// base register. Return the virtual register that holds this value.
93 SDNode *getGlobalBaseReg();
95 // Select - Convert the specified operand from a target-independent to a
96 // target-specific node if it hasn't already been changed.
97 SDNode *Select(SDNode *N);
99 SDNode *SelectBitfieldInsert(SDNode *N);
101 /// SelectCC - Select a comparison of the specified values with the
102 /// specified condition code, returning the CR# of the expression.
103 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, DebugLoc dl);
105 /// SelectAddrImm - Returns true if the address N can be represented by
106 /// a base register plus a signed 16-bit displacement [r+imm].
107 bool SelectAddrImm(SDValue N, SDValue &Disp,
109 return PPCLowering.SelectAddressRegImm(N, Disp, Base, *CurDAG);
112 /// SelectAddrImmOffs - Return true if the operand is valid for a preinc
113 /// immediate field. Because preinc imms have already been validated, just
115 bool SelectAddrImmOffs(SDValue N, SDValue &Out) const {
120 /// SelectAddrIdx - Given the specified addressed, check to see if it can be
121 /// represented as an indexed [r+r] operation. Returns false if it can
122 /// be represented by [r+imm], which are preferred.
123 bool SelectAddrIdx(SDValue N, SDValue &Base, SDValue &Index) {
124 return PPCLowering.SelectAddressRegReg(N, Base, Index, *CurDAG);
127 /// SelectAddrIdxOnly - Given the specified addressed, force it to be
128 /// represented as an indexed [r+r] operation.
129 bool SelectAddrIdxOnly(SDValue N, SDValue &Base, SDValue &Index) {
130 return PPCLowering.SelectAddressRegRegOnly(N, Base, Index, *CurDAG);
133 /// SelectAddrImmShift - Returns true if the address N can be represented by
134 /// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable
135 /// for use by STD and friends.
136 bool SelectAddrImmShift(SDValue N, SDValue &Disp, SDValue &Base) {
137 return PPCLowering.SelectAddressRegImmShift(N, Disp, Base, *CurDAG);
140 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
141 /// inline asm expressions. It is always correct to compute the value into
142 /// a register. The case of adding a (possibly relocatable) constant to a
143 /// register can be improved, but it is wrong to substitute Reg+Reg for
144 /// Reg in an asm, because the load or store opcode would have to change.
145 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
147 std::vector<SDValue> &OutOps) {
148 OutOps.push_back(Op);
152 void InsertVRSaveCode(MachineFunction &MF);
154 virtual const char *getPassName() const {
155 return "PowerPC DAG->DAG Pattern Instruction Selection";
158 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
159 /// this target when scheduling the DAG.
160 virtual ScheduleHazardRecognizer *CreateTargetHazardRecognizer() {
161 // Should use subtarget info to pick the right hazard recognizer. For
162 // now, always return a PPC970 recognizer.
163 const TargetInstrInfo *II = TM.getInstrInfo();
164 assert(II && "No InstrInfo?");
165 return new PPCHazardRecognizer970(*II);
168 // Include the pieces autogenerated from the target description.
169 #include "PPCGenDAGISel.inc"
172 SDNode *SelectSETCC(SDNode *N);
176 /// InsertVRSaveCode - Once the entire function has been instruction selected,
177 /// all virtual registers are created and all machine instructions are built,
178 /// check to see if we need to save/restore VRSAVE. If so, do it.
179 void PPCDAGToDAGISel::InsertVRSaveCode(MachineFunction &Fn) {
180 // Check to see if this function uses vector registers, which means we have to
181 // save and restore the VRSAVE register and update it with the regs we use.
183 // In this case, there will be virtual registers of vector type created
184 // by the scheduler. Detect them now.
185 bool HasVectorVReg = false;
186 for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
187 e = RegInfo->getLastVirtReg()+1; i != e; ++i)
188 if (RegInfo->getRegClass(i) == &PPC::VRRCRegClass) {
189 HasVectorVReg = true;
192 if (!HasVectorVReg) return; // nothing to do.
194 // If we have a vector register, we want to emit code into the entry and exit
195 // blocks to save and restore the VRSAVE register. We do this here (instead
196 // of marking all vector instructions as clobbering VRSAVE) for two reasons:
198 // 1. This (trivially) reduces the load on the register allocator, by not
199 // having to represent the live range of the VRSAVE register.
200 // 2. This (more significantly) allows us to create a temporary virtual
201 // register to hold the saved VRSAVE value, allowing this temporary to be
202 // register allocated, instead of forcing it to be spilled to the stack.
204 // Create two vregs - one to hold the VRSAVE register that is live-in to the
205 // function and one for the value after having bits or'd into it.
206 unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
207 unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
209 const TargetInstrInfo &TII = *TM.getInstrInfo();
210 MachineBasicBlock &EntryBB = *Fn.begin();
212 // Emit the following code into the entry block:
213 // InVRSAVE = MFVRSAVE
214 // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
215 // MTVRSAVE UpdatedVRSAVE
216 MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
217 BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE);
218 BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE),
219 UpdatedVRSAVE).addReg(InVRSAVE);
220 BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
222 // Find all return blocks, outputting a restore in each epilog.
223 for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
224 if (!BB->empty() && BB->back().getDesc().isReturn()) {
225 IP = BB->end(); --IP;
227 // Skip over all terminator instructions, which are part of the return
229 MachineBasicBlock::iterator I2 = IP;
230 while (I2 != BB->begin() && (--I2)->getDesc().isTerminator())
233 // Emit: MTVRSAVE InVRSave
234 BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
240 /// getGlobalBaseReg - Output the instructions required to put the
241 /// base address to use for accessing globals into a register.
243 SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
244 if (!GlobalBaseReg) {
245 const TargetInstrInfo &TII = *TM.getInstrInfo();
246 // Insert the set of GlobalBaseReg into the first MBB of the function
247 MachineBasicBlock &FirstMBB = MF->front();
248 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
251 if (PPCLowering.getPointerTy() == MVT::i32) {
252 GlobalBaseReg = RegInfo->createVirtualRegister(PPC::GPRCRegisterClass);
253 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR), PPC::LR);
254 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
256 GlobalBaseReg = RegInfo->createVirtualRegister(PPC::G8RCRegisterClass);
257 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8), PPC::LR8);
258 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg);
261 return CurDAG->getRegister(GlobalBaseReg,
262 PPCLowering.getPointerTy()).getNode();
265 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
266 /// or 64-bit immediate, and if the value can be accurately represented as a
267 /// sign extension from a 16-bit value. If so, this returns true and the
269 static bool isIntS16Immediate(SDNode *N, short &Imm) {
270 if (N->getOpcode() != ISD::Constant)
273 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
274 if (N->getValueType(0) == MVT::i32)
275 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
277 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
280 static bool isIntS16Immediate(SDValue Op, short &Imm) {
281 return isIntS16Immediate(Op.getNode(), Imm);
285 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
286 /// operand. If so Imm will receive the 32-bit value.
287 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
288 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
289 Imm = cast<ConstantSDNode>(N)->getZExtValue();
295 /// isInt64Immediate - This method tests to see if the node is a 64-bit constant
296 /// operand. If so Imm will receive the 64-bit value.
297 static bool isInt64Immediate(SDNode *N, uint64_t &Imm) {
298 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
299 Imm = cast<ConstantSDNode>(N)->getZExtValue();
305 // isInt32Immediate - This method tests to see if a constant operand.
306 // If so Imm will receive the 32 bit value.
307 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
308 return isInt32Immediate(N.getNode(), Imm);
312 // isOpcWithIntImmediate - This method tests to see if the node is a specific
313 // opcode and that it has a immediate integer right operand.
314 // If so Imm will receive the 32 bit value.
315 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
316 return N->getOpcode() == Opc
317 && isInt32Immediate(N->getOperand(1).getNode(), Imm);
320 bool PPCDAGToDAGISel::isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
321 if (isShiftedMask_32(Val)) {
322 // look for the first non-zero bit
323 MB = CountLeadingZeros_32(Val);
324 // look for the first zero bit after the run of ones
325 ME = CountLeadingZeros_32((Val - 1) ^ Val);
328 Val = ~Val; // invert mask
329 if (isShiftedMask_32(Val)) {
330 // effectively look for the first zero bit
331 ME = CountLeadingZeros_32(Val) - 1;
332 // effectively look for the first one bit after the run of zeros
333 MB = CountLeadingZeros_32((Val - 1) ^ Val) + 1;
341 bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask,
342 bool isShiftMask, unsigned &SH,
343 unsigned &MB, unsigned &ME) {
344 // Don't even go down this path for i64, since different logic will be
345 // necessary for rldicl/rldicr/rldimi.
346 if (N->getValueType(0) != MVT::i32)
350 unsigned Indeterminant = ~0; // bit mask marking indeterminant results
351 unsigned Opcode = N->getOpcode();
352 if (N->getNumOperands() != 2 ||
353 !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31))
356 if (Opcode == ISD::SHL) {
357 // apply shift left to mask if it comes first
358 if (isShiftMask) Mask = Mask << Shift;
359 // determine which bits are made indeterminant by shift
360 Indeterminant = ~(0xFFFFFFFFu << Shift);
361 } else if (Opcode == ISD::SRL) {
362 // apply shift right to mask if it comes first
363 if (isShiftMask) Mask = Mask >> Shift;
364 // determine which bits are made indeterminant by shift
365 Indeterminant = ~(0xFFFFFFFFu >> Shift);
366 // adjust for the left rotate
368 } else if (Opcode == ISD::ROTL) {
374 // if the mask doesn't intersect any Indeterminant bits
375 if (Mask && !(Mask & Indeterminant)) {
377 // make sure the mask is still a mask (wrap arounds may not be)
378 return isRunOfOnes(Mask, MB, ME);
383 /// SelectBitfieldInsert - turn an or of two masked values into
384 /// the rotate left word immediate then mask insert (rlwimi) instruction.
385 SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
386 SDValue Op0 = N->getOperand(0);
387 SDValue Op1 = N->getOperand(1);
388 DebugLoc dl = N->getDebugLoc();
390 APInt LKZ, LKO, RKZ, RKO;
391 CurDAG->ComputeMaskedBits(Op0, APInt::getAllOnesValue(32), LKZ, LKO);
392 CurDAG->ComputeMaskedBits(Op1, APInt::getAllOnesValue(32), RKZ, RKO);
394 unsigned TargetMask = LKZ.getZExtValue();
395 unsigned InsertMask = RKZ.getZExtValue();
397 if ((TargetMask | InsertMask) == 0xFFFFFFFF) {
398 unsigned Op0Opc = Op0.getOpcode();
399 unsigned Op1Opc = Op1.getOpcode();
400 unsigned Value, SH = 0;
401 TargetMask = ~TargetMask;
402 InsertMask = ~InsertMask;
404 // If the LHS has a foldable shift and the RHS does not, then swap it to the
405 // RHS so that we can fold the shift into the insert.
406 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
407 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
408 Op0.getOperand(0).getOpcode() == ISD::SRL) {
409 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
410 Op1.getOperand(0).getOpcode() != ISD::SRL) {
412 std::swap(Op0Opc, Op1Opc);
413 std::swap(TargetMask, InsertMask);
416 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
417 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
418 Op1.getOperand(0).getOpcode() != ISD::SRL) {
420 std::swap(Op0Opc, Op1Opc);
421 std::swap(TargetMask, InsertMask);
426 if (InsertMask && isRunOfOnes(InsertMask, MB, ME)) {
429 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
430 isInt32Immediate(Op1.getOperand(1), Value)) {
431 Op1 = Op1.getOperand(0);
432 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value;
434 if (Op1Opc == ISD::AND) {
435 unsigned SHOpc = Op1.getOperand(0).getOpcode();
436 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) &&
437 isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) {
438 Op1 = Op1.getOperand(0).getOperand(0);
439 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value;
441 Op1 = Op1.getOperand(0);
446 SDValue Ops[] = { Op0, Op1, getI32Imm(SH), getI32Imm(MB),
448 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5);
454 /// SelectCC - Select a comparison of the specified values with the specified
455 /// condition code, returning the CR# of the expression.
456 SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS,
457 ISD::CondCode CC, DebugLoc dl) {
458 // Always select the LHS.
461 if (LHS.getValueType() == MVT::i32) {
463 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
464 if (isInt32Immediate(RHS, Imm)) {
465 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
467 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
468 getI32Imm(Imm & 0xFFFF)), 0);
469 // If this is a 16-bit signed immediate, fold it.
470 if (isInt<16>((int)Imm))
471 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
472 getI32Imm(Imm & 0xFFFF)), 0);
474 // For non-equality comparisons, the default code would materialize the
475 // constant, then compare against it, like this:
479 // Since we are just comparing for equality, we can emit this instead:
480 // xoris r0,r3,0x1234
481 // cmplwi cr0,r0,0x5678
483 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS, dl, MVT::i32, LHS,
484 getI32Imm(Imm >> 16)), 0);
485 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, Xor,
486 getI32Imm(Imm & 0xFFFF)), 0);
489 } else if (ISD::isUnsignedIntSetCC(CC)) {
490 if (isInt32Immediate(RHS, Imm) && isUInt<16>(Imm))
491 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
492 getI32Imm(Imm & 0xFFFF)), 0);
496 if (isIntS16Immediate(RHS, SImm))
497 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
498 getI32Imm((int)SImm & 0xFFFF)),
502 } else if (LHS.getValueType() == MVT::i64) {
504 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
505 if (isInt64Immediate(RHS.getNode(), Imm)) {
506 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
508 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
509 getI32Imm(Imm & 0xFFFF)), 0);
510 // If this is a 16-bit signed immediate, fold it.
512 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
513 getI32Imm(Imm & 0xFFFF)), 0);
515 // For non-equality comparisons, the default code would materialize the
516 // constant, then compare against it, like this:
520 // Since we are just comparing for equality, we can emit this instead:
521 // xoris r0,r3,0x1234
522 // cmpldi cr0,r0,0x5678
524 if (isUInt<32>(Imm)) {
525 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS8, dl, MVT::i64, LHS,
526 getI64Imm(Imm >> 16)), 0);
527 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, Xor,
528 getI64Imm(Imm & 0xFFFF)), 0);
532 } else if (ISD::isUnsignedIntSetCC(CC)) {
533 if (isInt64Immediate(RHS.getNode(), Imm) && isUInt<16>(Imm))
534 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
535 getI64Imm(Imm & 0xFFFF)), 0);
539 if (isIntS16Immediate(RHS, SImm))
540 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
541 getI64Imm(SImm & 0xFFFF)),
545 } else if (LHS.getValueType() == MVT::f32) {
548 assert(LHS.getValueType() == MVT::f64 && "Unknown vt!");
551 return SDValue(CurDAG->getMachineNode(Opc, dl, MVT::i32, LHS, RHS), 0);
554 static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {
560 llvm_unreachable("Should be lowered by legalize!");
561 default: llvm_unreachable("Unknown condition!");
563 case ISD::SETEQ: return PPC::PRED_EQ;
565 case ISD::SETNE: return PPC::PRED_NE;
567 case ISD::SETLT: return PPC::PRED_LT;
569 case ISD::SETLE: return PPC::PRED_LE;
571 case ISD::SETGT: return PPC::PRED_GT;
573 case ISD::SETGE: return PPC::PRED_GE;
574 case ISD::SETO: return PPC::PRED_NU;
575 case ISD::SETUO: return PPC::PRED_UN;
576 // These two are invalid for floating point. Assume we have int.
577 case ISD::SETULT: return PPC::PRED_LT;
578 case ISD::SETUGT: return PPC::PRED_GT;
582 /// getCRIdxForSetCC - Return the index of the condition register field
583 /// associated with the SetCC condition, and whether or not the field is
584 /// treated as inverted. That is, lt = 0; ge = 0 inverted.
586 /// If this returns with Other != -1, then the returned comparison is an or of
587 /// two simpler comparisons. In this case, Invert is guaranteed to be false.
588 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert, int &Other) {
592 default: llvm_unreachable("Unknown condition!");
594 case ISD::SETLT: return 0; // Bit #0 = SETOLT
596 case ISD::SETGT: return 1; // Bit #1 = SETOGT
598 case ISD::SETEQ: return 2; // Bit #2 = SETOEQ
599 case ISD::SETUO: return 3; // Bit #3 = SETUO
601 case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE
603 case ISD::SETLE: Invert = true; return 1; // !Bit #1 = SETULE
605 case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE
606 case ISD::SETO: Invert = true; return 3; // !Bit #3 = SETO
611 llvm_unreachable("Invalid branch code: should be expanded by legalize");
612 // These are invalid for floating point. Assume integer.
613 case ISD::SETULT: return 0;
614 case ISD::SETUGT: return 1;
619 SDNode *PPCDAGToDAGISel::SelectSETCC(SDNode *N) {
620 DebugLoc dl = N->getDebugLoc();
622 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
623 if (isInt32Immediate(N->getOperand(1), Imm)) {
624 // We can codegen setcc op, imm very efficiently compared to a brcond.
625 // Check for those cases here.
628 SDValue Op = N->getOperand(0);
632 Op = SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Op), 0);
633 SDValue Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) };
634 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
638 SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
639 Op, getI32Imm(~0U)), 0);
640 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
644 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
645 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
649 SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Op), 0);
650 T = SDValue(CurDAG->getMachineNode(PPC::ANDC, dl, MVT::i32, T, Op), 0);
651 SDValue Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
652 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
655 } else if (Imm == ~0U) { // setcc op, -1
656 SDValue Op = N->getOperand(0);
660 Op = SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
661 Op, getI32Imm(1)), 0);
662 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
663 SDValue(CurDAG->getMachineNode(PPC::LI, dl,
668 Op = SDValue(CurDAG->getMachineNode(PPC::NOR, dl, MVT::i32, Op, Op), 0);
669 SDNode *AD = CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
671 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0),
675 SDValue AD = SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Op,
677 SDValue AN = SDValue(CurDAG->getMachineNode(PPC::AND, dl, MVT::i32, AD,
679 SDValue Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
680 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
683 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
684 Op = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops, 4),
686 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op,
695 unsigned Idx = getCRIdxForSetCC(CC, Inv, OtherCondIdx);
696 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl);
699 // Force the ccreg into CR7.
700 SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
702 SDValue InFlag(0, 0); // Null incoming flag value.
703 CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, CR7Reg, CCReg,
706 if (PPCSubTarget.isGigaProcessor() && OtherCondIdx == -1)
707 IntCR = SDValue(CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg,
710 IntCR = SDValue(CurDAG->getMachineNode(PPC::MFCRpseud, dl, MVT::i32,
713 SDValue Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31),
714 getI32Imm(31), getI32Imm(31) };
715 if (OtherCondIdx == -1 && !Inv)
716 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
718 // Get the specified bit.
720 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0);
722 assert(OtherCondIdx == -1 && "Can't have split plus negation");
723 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
726 // Otherwise, we have to turn an operation like SETONE -> SETOLT | SETOGT.
727 // We already got the bit for the first part of the comparison (e.g. SETULE).
729 // Get the other bit of the comparison.
730 Ops[1] = getI32Imm((32-(3-OtherCondIdx)) & 31);
732 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0);
734 return CurDAG->SelectNodeTo(N, PPC::OR, MVT::i32, Tmp, OtherCond);
738 // Select - Convert the specified operand from a target-independent to a
739 // target-specific node if it hasn't already been changed.
740 SDNode *PPCDAGToDAGISel::Select(SDNode *N) {
741 DebugLoc dl = N->getDebugLoc();
742 if (N->isMachineOpcode())
743 return NULL; // Already selected.
745 switch (N->getOpcode()) {
748 case ISD::Constant: {
749 if (N->getValueType(0) == MVT::i64) {
751 int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue();
752 // Assume no remaining bits.
753 unsigned Remainder = 0;
754 // Assume no shift required.
757 // If it can't be represented as a 32 bit value.
758 if (!isInt<32>(Imm)) {
759 Shift = CountTrailingZeros_64(Imm);
760 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
762 // If the shifted value fits 32 bits.
763 if (isInt<32>(ImmSh)) {
764 // Go with the shifted value.
767 // Still stuck with a 64 bit value.
774 // Intermediate operand.
777 // Handle first 32 bits.
778 unsigned Lo = Imm & 0xFFFF;
779 unsigned Hi = (Imm >> 16) & 0xFFFF;
782 if (isInt<16>(Imm)) {
784 Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo));
786 // Handle the Hi bits.
787 unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8;
788 Result = CurDAG->getMachineNode(OpC, dl, MVT::i64, getI32Imm(Hi));
790 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
791 SDValue(Result, 0), getI32Imm(Lo));
794 Result = CurDAG->getMachineNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi));
797 // If no shift, we're done.
798 if (!Shift) return Result;
800 // Shift for next step if the upper 32-bits were not zero.
802 Result = CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64,
805 getI32Imm(63 - Shift));
808 // Add in the last bits as required.
809 if ((Hi = (Remainder >> 16) & 0xFFFF)) {
810 Result = CurDAG->getMachineNode(PPC::ORIS8, dl, MVT::i64,
811 SDValue(Result, 0), getI32Imm(Hi));
813 if ((Lo = Remainder & 0xFFFF)) {
814 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
815 SDValue(Result, 0), getI32Imm(Lo));
824 return SelectSETCC(N);
825 case PPCISD::GlobalBaseReg:
826 return getGlobalBaseReg();
828 case ISD::FrameIndex: {
829 int FI = cast<FrameIndexSDNode>(N)->getIndex();
830 SDValue TFI = CurDAG->getTargetFrameIndex(FI, N->getValueType(0));
831 unsigned Opc = N->getValueType(0) == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
833 return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), TFI,
835 return CurDAG->getMachineNode(Opc, dl, N->getValueType(0), TFI,
840 SDValue InFlag = N->getOperand(1);
841 // Use MFOCRF if supported.
842 if (PPCSubTarget.isGigaProcessor())
843 return CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32,
844 N->getOperand(0), InFlag);
846 return CurDAG->getMachineNode(PPC::MFCRpseud, dl, MVT::i32,
847 N->getOperand(0), InFlag);
851 // FIXME: since this depends on the setting of the carry flag from the srawi
852 // we should really be making notes about that for the scheduler.
853 // FIXME: It sure would be nice if we could cheaply recognize the
854 // srl/add/sra pattern the dag combiner will generate for this as
855 // sra/addze rather than having to handle sdiv ourselves. oh well.
857 if (isInt32Immediate(N->getOperand(1), Imm)) {
858 SDValue N0 = N->getOperand(0);
859 if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
861 CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Glue,
862 N0, getI32Imm(Log2_32(Imm)));
863 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
864 SDValue(Op, 0), SDValue(Op, 1));
865 } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
867 CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Glue,
868 N0, getI32Imm(Log2_32(-Imm)));
870 SDValue(CurDAG->getMachineNode(PPC::ADDZE, dl, MVT::i32,
871 SDValue(Op, 0), SDValue(Op, 1)),
873 return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
877 // Other cases are autogenerated.
882 // Handle preincrement loads.
883 LoadSDNode *LD = cast<LoadSDNode>(N);
884 EVT LoadedVT = LD->getMemoryVT();
886 // Normal loads are handled by code generated from the .td file.
887 if (LD->getAddressingMode() != ISD::PRE_INC)
890 SDValue Offset = LD->getOffset();
891 if (isa<ConstantSDNode>(Offset) ||
892 Offset.getOpcode() == ISD::TargetGlobalAddress) {
895 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
896 if (LD->getValueType(0) != MVT::i64) {
897 // Handle PPC32 integer and normal FP loads.
898 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
899 switch (LoadedVT.getSimpleVT().SimpleTy) {
900 default: llvm_unreachable("Invalid PPC load type!");
901 case MVT::f64: Opcode = PPC::LFDU; break;
902 case MVT::f32: Opcode = PPC::LFSU; break;
903 case MVT::i32: Opcode = PPC::LWZU; break;
904 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
906 case MVT::i8: Opcode = PPC::LBZU; break;
909 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
910 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
911 switch (LoadedVT.getSimpleVT().SimpleTy) {
912 default: llvm_unreachable("Invalid PPC load type!");
913 case MVT::i64: Opcode = PPC::LDU; break;
914 case MVT::i32: Opcode = PPC::LWZU8; break;
915 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
917 case MVT::i8: Opcode = PPC::LBZU8; break;
921 SDValue Chain = LD->getChain();
922 SDValue Base = LD->getBasePtr();
923 SDValue Ops[] = { Offset, Base, Chain };
925 return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0),
926 PPCLowering.getPointerTy(),
929 llvm_unreachable("R+R preindex loads not supported yet!");
934 unsigned Imm, Imm2, SH, MB, ME;
936 // If this is an and of a value rotated between 0 and 31 bits and then and'd
937 // with a mask, emit rlwinm
938 if (isInt32Immediate(N->getOperand(1), Imm) &&
939 isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH, MB, ME)) {
940 SDValue Val = N->getOperand(0).getOperand(0);
941 SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
942 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
944 // If this is just a masked value where the input is not handled above, and
945 // is not a rotate-left (handled by a pattern in the .td file), emit rlwinm
946 if (isInt32Immediate(N->getOperand(1), Imm) &&
947 isRunOfOnes(Imm, MB, ME) &&
948 N->getOperand(0).getOpcode() != ISD::ROTL) {
949 SDValue Val = N->getOperand(0);
950 SDValue Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) };
951 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
953 // AND X, 0 -> 0, not "rlwinm 32".
954 if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) {
955 ReplaceUses(SDValue(N, 0), N->getOperand(1));
958 // ISD::OR doesn't get all the bitfield insertion fun.
959 // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert
960 if (isInt32Immediate(N->getOperand(1), Imm) &&
961 N->getOperand(0).getOpcode() == ISD::OR &&
962 isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) {
965 if (isRunOfOnes(Imm, MB, ME)) {
966 SDValue Ops[] = { N->getOperand(0).getOperand(0),
967 N->getOperand(0).getOperand(1),
968 getI32Imm(0), getI32Imm(MB),getI32Imm(ME) };
969 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5);
973 // Other cases are autogenerated.
977 if (N->getValueType(0) == MVT::i32)
978 if (SDNode *I = SelectBitfieldInsert(N))
981 // Other cases are autogenerated.
984 unsigned Imm, SH, MB, ME;
985 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
986 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
987 SDValue Ops[] = { N->getOperand(0).getOperand(0),
988 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
989 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
992 // Other cases are autogenerated.
996 unsigned Imm, SH, MB, ME;
997 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
998 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
999 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1000 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
1001 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
1004 // Other cases are autogenerated.
1007 case ISD::SELECT_CC: {
1008 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1010 // Handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
1011 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1012 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
1013 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
1014 if (N1C->isNullValue() && N3C->isNullValue() &&
1015 N2C->getZExtValue() == 1ULL && CC == ISD::SETNE &&
1016 // FIXME: Implement this optzn for PPC64.
1017 N->getValueType(0) == MVT::i32) {
1019 CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
1020 N->getOperand(0), getI32Imm(~0U));
1021 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
1022 SDValue(Tmp, 0), N->getOperand(0),
1026 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl);
1027 unsigned BROpc = getPredicateForSetCC(CC);
1029 unsigned SelectCCOp;
1030 if (N->getValueType(0) == MVT::i32)
1031 SelectCCOp = PPC::SELECT_CC_I4;
1032 else if (N->getValueType(0) == MVT::i64)
1033 SelectCCOp = PPC::SELECT_CC_I8;
1034 else if (N->getValueType(0) == MVT::f32)
1035 SelectCCOp = PPC::SELECT_CC_F4;
1036 else if (N->getValueType(0) == MVT::f64)
1037 SelectCCOp = PPC::SELECT_CC_F8;
1039 SelectCCOp = PPC::SELECT_CC_VRRC;
1041 SDValue Ops[] = { CCReg, N->getOperand(2), N->getOperand(3),
1043 return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops, 4);
1045 case PPCISD::COND_BRANCH: {
1046 // Op #0 is the Chain.
1047 // Op #1 is the PPC::PRED_* number.
1049 // Op #3 is the Dest MBB
1050 // Op #4 is the Flag.
1051 // Prevent PPC::PRED_* from being selected into LI.
1053 getI32Imm(cast<ConstantSDNode>(N->getOperand(1))->getZExtValue());
1054 SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3),
1055 N->getOperand(0), N->getOperand(4) };
1056 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 5);
1059 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
1060 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl);
1061 SDValue Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode,
1062 N->getOperand(4), N->getOperand(0) };
1063 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 4);
1066 // FIXME: Should custom lower this.
1067 SDValue Chain = N->getOperand(0);
1068 SDValue Target = N->getOperand(1);
1069 unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
1070 Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Target,
1072 return CurDAG->SelectNodeTo(N, PPC::BCTR, MVT::Other, Chain);
1076 return SelectCode(N);
1081 /// createPPCISelDag - This pass converts a legalized DAG into a
1082 /// PowerPC-specific DAG, ready for instruction scheduling.
1084 FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) {
1085 return new PPCDAGToDAGISel(TM);