1 //===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for PowerPC,
11 // converting from a legalized dag to a PPC dag.
13 //===----------------------------------------------------------------------===//
16 #include "PPCTargetMachine.h"
17 #include "PPCISelLowering.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/SSARegMap.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/SelectionDAGISel.h"
23 #include "llvm/Target/TargetOptions.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/Constants.h"
26 #include "llvm/GlobalValue.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/MathExtras.h"
32 Statistic<> FrameOff("ppc-codegen", "Number of frame idx offsets collapsed");
34 //===--------------------------------------------------------------------===//
35 /// PPCDAGToDAGISel - PPC specific code to select PPC machine
36 /// instructions for SelectionDAG operations.
38 class PPCDAGToDAGISel : public SelectionDAGISel {
39 PPCTargetLowering PPCLowering;
40 unsigned GlobalBaseReg;
42 PPCDAGToDAGISel(TargetMachine &TM)
43 : SelectionDAGISel(PPCLowering), PPCLowering(TM) {}
45 virtual bool runOnFunction(Function &Fn) {
46 // Make sure we re-emit a set of the global base reg if necessary
48 return SelectionDAGISel::runOnFunction(Fn);
51 /// getI32Imm - Return a target constant with the specified value, of type
53 inline SDOperand getI32Imm(unsigned Imm) {
54 return CurDAG->getTargetConstant(Imm, MVT::i32);
57 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
58 /// base register. Return the virtual register that holds this value.
59 SDOperand getGlobalBaseReg();
61 // Select - Convert the specified operand from a target-independent to a
62 // target-specific node if it hasn't already been changed.
63 SDOperand Select(SDOperand Op);
65 SDNode *SelectBitfieldInsert(SDNode *N);
67 /// SelectCC - Select a comparison of the specified values with the
68 /// specified condition code, returning the CR# of the expression.
69 SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
71 /// SelectAddrImm - Returns true if the address N can be represented by
72 /// a base register plus a signed 16-bit displacement [r+imm].
73 bool SelectAddrImm(SDOperand N, SDOperand &Disp, SDOperand &Base);
75 /// SelectAddrIdx - Given the specified addressed, check to see if it can be
76 /// represented as an indexed [r+r] operation. Returns false if it can
77 /// be represented by [r+imm], which are preferred.
78 bool SelectAddrIdx(SDOperand N, SDOperand &Base, SDOperand &Index);
80 /// SelectAddrIdxOnly - Given the specified addressed, force it to be
81 /// represented as an indexed [r+r] operation.
82 bool SelectAddrIdxOnly(SDOperand N, SDOperand &Base, SDOperand &Index);
84 SDOperand BuildSDIVSequence(SDNode *N);
85 SDOperand BuildUDIVSequence(SDNode *N);
87 /// InstructionSelectBasicBlock - This callback is invoked by
88 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
89 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
91 virtual const char *getPassName() const {
92 return "PowerPC DAG->DAG Pattern Instruction Selection";
95 // Include the pieces autogenerated from the target description.
96 #include "PPCGenDAGISel.inc"
99 SDOperand SelectDYNAMIC_STACKALLOC(SDOperand Op);
100 SDOperand SelectADD_PARTS(SDOperand Op);
101 SDOperand SelectSUB_PARTS(SDOperand Op);
102 SDOperand SelectSETCC(SDOperand Op);
103 SDOperand SelectCALL(SDOperand Op);
107 /// InstructionSelectBasicBlock - This callback is invoked by
108 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
109 void PPCDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
112 // The selection process is inherently a bottom-up recursive process (users
113 // select their uses before themselves). Given infinite stack space, we
114 // could just start selecting on the root and traverse the whole graph. In
115 // practice however, this causes us to run out of stack space on large basic
116 // blocks. To avoid this problem, select the entry node, then all its uses,
117 // iteratively instead of recursively.
118 std::vector<SDOperand> Worklist;
119 Worklist.push_back(DAG.getEntryNode());
121 // Note that we can do this in the PPC target (scanning forward across token
122 // chain edges) because no nodes ever get folded across these edges. On a
123 // target like X86 which supports load/modify/store operations, this would
124 // have to be more careful.
125 while (!Worklist.empty()) {
126 SDOperand Node = Worklist.back();
129 // Chose from the least deep of the top two nodes.
130 if (!Worklist.empty() &&
131 Worklist.back().Val->getNodeDepth() < Node.Val->getNodeDepth())
132 std::swap(Worklist.back(), Node);
134 if ((Node.Val->getOpcode() >= ISD::BUILTIN_OP_END &&
135 Node.Val->getOpcode() < PPCISD::FIRST_NUMBER) ||
136 CodeGenMap.count(Node)) continue;
138 for (SDNode::use_iterator UI = Node.Val->use_begin(),
139 E = Node.Val->use_end(); UI != E; ++UI) {
140 // Scan the values. If this use has a value that is a token chain, add it
143 for (unsigned i = 0, e = User->getNumValues(); i != e; ++i)
144 if (User->getValueType(i) == MVT::Other) {
145 Worklist.push_back(SDOperand(User, i));
150 // Finally, legalize this node.
154 // Select target instructions for the DAG.
155 DAG.setRoot(Select(DAG.getRoot()));
157 DAG.RemoveDeadNodes();
159 // Emit machine code to BB.
160 ScheduleAndEmitDAG(DAG);
163 /// getGlobalBaseReg - Output the instructions required to put the
164 /// base address to use for accessing globals into a register.
166 SDOperand PPCDAGToDAGISel::getGlobalBaseReg() {
167 if (!GlobalBaseReg) {
168 // Insert the set of GlobalBaseReg into the first MBB of the function
169 MachineBasicBlock &FirstMBB = BB->getParent()->front();
170 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
171 SSARegMap *RegMap = BB->getParent()->getSSARegMap();
172 // FIXME: when we get to LP64, we will need to create the appropriate
173 // type of register here.
174 GlobalBaseReg = RegMap->createVirtualRegister(PPC::GPRCRegisterClass);
175 BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
176 BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg);
178 return CurDAG->getRegister(GlobalBaseReg, MVT::i32);
182 // isIntImmediate - This method tests to see if a constant operand.
183 // If so Imm will receive the 32 bit value.
184 static bool isIntImmediate(SDNode *N, unsigned& Imm) {
185 if (N->getOpcode() == ISD::Constant) {
186 Imm = cast<ConstantSDNode>(N)->getValue();
192 // isOprShiftImm - Returns true if the specified operand is a shift opcode with
193 // a immediate shift count less than 32.
194 static bool isOprShiftImm(SDNode *N, unsigned& Opc, unsigned& SH) {
195 Opc = N->getOpcode();
196 return (Opc == ISD::SHL || Opc == ISD::SRL || Opc == ISD::SRA) &&
197 isIntImmediate(N->getOperand(1).Val, SH) && SH < 32;
200 // isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s with
201 // any number of 0s on either side. The 1s are allowed to wrap from LSB to
202 // MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 0x0F0F0000 is
203 // not, since all 1s are not contiguous.
204 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
205 if (isShiftedMask_32(Val)) {
206 // look for the first non-zero bit
207 MB = CountLeadingZeros_32(Val);
208 // look for the first zero bit after the run of ones
209 ME = CountLeadingZeros_32((Val - 1) ^ Val);
212 Val = ~Val; // invert mask
213 if (isShiftedMask_32(Val)) {
214 // effectively look for the first zero bit
215 ME = CountLeadingZeros_32(Val) - 1;
216 // effectively look for the first one bit after the run of zeros
217 MB = CountLeadingZeros_32((Val - 1) ^ Val) + 1;
225 // isRotateAndMask - Returns true if Mask and Shift can be folded into a rotate
226 // and mask opcode and mask operation.
227 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask,
228 unsigned &SH, unsigned &MB, unsigned &ME) {
229 // Don't even go down this path for i64, since different logic will be
230 // necessary for rldicl/rldicr/rldimi.
231 if (N->getValueType(0) != MVT::i32)
235 unsigned Indeterminant = ~0; // bit mask marking indeterminant results
236 unsigned Opcode = N->getOpcode();
237 if (N->getNumOperands() != 2 ||
238 !isIntImmediate(N->getOperand(1).Val, Shift) || (Shift > 31))
241 if (Opcode == ISD::SHL) {
242 // apply shift left to mask if it comes first
243 if (IsShiftMask) Mask = Mask << Shift;
244 // determine which bits are made indeterminant by shift
245 Indeterminant = ~(0xFFFFFFFFu << Shift);
246 } else if (Opcode == ISD::SRL) {
247 // apply shift right to mask if it comes first
248 if (IsShiftMask) Mask = Mask >> Shift;
249 // determine which bits are made indeterminant by shift
250 Indeterminant = ~(0xFFFFFFFFu >> Shift);
251 // adjust for the left rotate
257 // if the mask doesn't intersect any Indeterminant bits
258 if (Mask && !(Mask & Indeterminant)) {
260 // make sure the mask is still a mask (wrap arounds may not be)
261 return isRunOfOnes(Mask, MB, ME);
266 // isOpcWithIntImmediate - This method tests to see if the node is a specific
267 // opcode and that it has a immediate integer right operand.
268 // If so Imm will receive the 32 bit value.
269 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
270 return N->getOpcode() == Opc && isIntImmediate(N->getOperand(1).Val, Imm);
273 // isOprNot - Returns true if the specified operand is an xor with immediate -1.
274 static bool isOprNot(SDNode *N) {
276 return isOpcWithIntImmediate(N, ISD::XOR, Imm) && (signed)Imm == -1;
279 // Immediate constant composers.
280 // Lo16 - grabs the lo 16 bits from a 32 bit constant.
281 // Hi16 - grabs the hi 16 bits from a 32 bit constant.
282 // HA16 - computes the hi bits required if the lo bits are add/subtracted in
284 static unsigned Lo16(unsigned x) { return x & 0x0000FFFF; }
285 static unsigned Hi16(unsigned x) { return Lo16(x >> 16); }
286 static unsigned HA16(unsigned x) { return Hi16((signed)x - (signed short)x); }
288 // isIntImmediate - This method tests to see if a constant operand.
289 // If so Imm will receive the 32 bit value.
290 static bool isIntImmediate(SDOperand N, unsigned& Imm) {
291 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
292 Imm = (unsigned)CN->getSignExtended();
298 /// SelectBitfieldInsert - turn an or of two masked values into
299 /// the rotate left word immediate then mask insert (rlwimi) instruction.
300 /// Returns true on success, false if the caller still needs to select OR.
302 /// Patterns matched:
303 /// 1. or shl, and 5. or and, and
304 /// 2. or and, shl 6. or shl, shr
305 /// 3. or shr, and 7. or shr, shl
307 SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
308 bool IsRotate = false;
309 unsigned TgtMask = 0xFFFFFFFF, InsMask = 0xFFFFFFFF, SH = 0;
312 SDOperand Op0 = N->getOperand(0);
313 SDOperand Op1 = N->getOperand(1);
315 unsigned Op0Opc = Op0.getOpcode();
316 unsigned Op1Opc = Op1.getOpcode();
318 // Verify that we have the correct opcodes
319 if (ISD::SHL != Op0Opc && ISD::SRL != Op0Opc && ISD::AND != Op0Opc)
321 if (ISD::SHL != Op1Opc && ISD::SRL != Op1Opc && ISD::AND != Op1Opc)
324 // Generate Mask value for Target
325 if (isIntImmediate(Op0.getOperand(1), Value)) {
327 case ISD::SHL: TgtMask <<= Value; break;
328 case ISD::SRL: TgtMask >>= Value; break;
329 case ISD::AND: TgtMask &= Value; break;
335 // Generate Mask value for Insert
336 if (!isIntImmediate(Op1.getOperand(1), Value))
343 if (Op0Opc == ISD::SRL) IsRotate = true;
349 if (Op0Opc == ISD::SHL) IsRotate = true;
356 // If both of the inputs are ANDs and one of them has a logical shift by
357 // constant as its input, make that AND the inserted value so that we can
358 // combine the shift into the rotate part of the rlwimi instruction
359 bool IsAndWithShiftOp = false;
360 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
361 if (Op1.getOperand(0).getOpcode() == ISD::SHL ||
362 Op1.getOperand(0).getOpcode() == ISD::SRL) {
363 if (isIntImmediate(Op1.getOperand(0).getOperand(1), Value)) {
364 SH = Op1.getOperand(0).getOpcode() == ISD::SHL ? Value : 32 - Value;
365 IsAndWithShiftOp = true;
367 } else if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
368 Op0.getOperand(0).getOpcode() == ISD::SRL) {
369 if (isIntImmediate(Op0.getOperand(0).getOperand(1), Value)) {
371 std::swap(TgtMask, InsMask);
372 SH = Op1.getOperand(0).getOpcode() == ISD::SHL ? Value : 32 - Value;
373 IsAndWithShiftOp = true;
378 // Verify that the Target mask and Insert mask together form a full word mask
379 // and that the Insert mask is a run of set bits (which implies both are runs
380 // of set bits). Given that, Select the arguments and generate the rlwimi
383 if (((TgtMask & InsMask) == 0) && isRunOfOnes(InsMask, MB, ME)) {
384 bool fullMask = (TgtMask ^ InsMask) == 0xFFFFFFFF;
385 bool Op0IsAND = Op0Opc == ISD::AND;
386 // Check for rotlwi / rotrwi here, a special case of bitfield insert
387 // where both bitfield halves are sourced from the same value.
388 if (IsRotate && fullMask &&
389 N->getOperand(0).getOperand(0) == N->getOperand(1).getOperand(0)) {
390 Op0 = CurDAG->getTargetNode(PPC::RLWINM, MVT::i32,
391 Select(N->getOperand(0).getOperand(0)),
392 getI32Imm(SH), getI32Imm(0), getI32Imm(31));
395 SDOperand Tmp1 = (Op0IsAND && fullMask) ? Select(Op0.getOperand(0))
397 SDOperand Tmp2 = IsAndWithShiftOp ? Select(Op1.getOperand(0).getOperand(0))
398 : Select(Op1.getOperand(0));
399 Op0 = CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Tmp1, Tmp2,
400 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
406 /// SelectAddrImm - Returns true if the address N can be represented by
407 /// a base register plus a signed 16-bit displacement [r+imm].
408 bool PPCDAGToDAGISel::SelectAddrImm(SDOperand N, SDOperand &Disp,
410 if (N.getOpcode() == ISD::ADD) {
412 if (isIntImmediate(N.getOperand(1), imm) && isInt16(imm)) {
413 Disp = getI32Imm(Lo16(imm));
414 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
415 Base = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
417 Base = Select(N.getOperand(0));
419 return true; // [r+i]
420 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
421 // Match LOAD (ADD (X, Lo(G))).
422 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
423 && "Cannot handle constant offsets yet!");
424 Disp = N.getOperand(1).getOperand(0); // The global address.
425 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
426 Disp.getOpcode() == ISD::TargetConstantPool);
427 Base = Select(N.getOperand(0));
428 return true; // [&g+r]
430 return false; // [r+r]
433 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
434 Base = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
437 return true; // [r+0]
440 /// SelectAddrIdx - Given the specified addressed, check to see if it can be
441 /// represented as an indexed [r+r] operation. Returns false if it can
442 /// be represented by [r+imm], which are preferred.
443 bool PPCDAGToDAGISel::SelectAddrIdx(SDOperand N, SDOperand &Base,
445 // Check to see if we can represent this as an [r+imm] address instead,
446 // which will fail if the address is more profitably represented as an
448 if (SelectAddrImm(N, Base, Index))
451 if (N.getOpcode() == ISD::ADD) {
452 Base = Select(N.getOperand(0));
453 Index = Select(N.getOperand(1));
457 Base = CurDAG->getRegister(PPC::R0, MVT::i32);
462 /// SelectAddrIdxOnly - Given the specified addressed, force it to be
463 /// represented as an indexed [r+r] operation.
464 bool PPCDAGToDAGISel::SelectAddrIdxOnly(SDOperand N, SDOperand &Base,
466 if (N.getOpcode() == ISD::ADD) {
467 Base = Select(N.getOperand(0));
468 Index = Select(N.getOperand(1));
472 Base = CurDAG->getRegister(PPC::R0, MVT::i32);
477 /// SelectCC - Select a comparison of the specified values with the specified
478 /// condition code, returning the CR# of the expression.
479 SDOperand PPCDAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS,
481 // Always select the LHS.
484 // Use U to determine whether the SETCC immediate range is signed or not.
485 if (MVT::isInteger(LHS.getValueType())) {
486 bool U = ISD::isUnsignedIntSetCC(CC);
488 if (isIntImmediate(RHS, Imm) &&
489 ((U && isUInt16(Imm)) || (!U && isInt16(Imm))))
490 return CurDAG->getTargetNode(U ? PPC::CMPLWI : PPC::CMPWI, MVT::i32,
491 LHS, getI32Imm(Lo16(Imm)));
492 return CurDAG->getTargetNode(U ? PPC::CMPLW : PPC::CMPW, MVT::i32,
494 } else if (LHS.getValueType() == MVT::f32) {
495 return CurDAG->getTargetNode(PPC::FCMPUS, MVT::i32, LHS, Select(RHS));
497 return CurDAG->getTargetNode(PPC::FCMPUD, MVT::i32, LHS, Select(RHS));
501 /// getBCCForSetCC - Returns the PowerPC condition branch mnemonic corresponding
503 static unsigned getBCCForSetCC(ISD::CondCode CC) {
505 default: assert(0 && "Unknown condition!"); abort();
506 case ISD::SETOEQ: // FIXME: This is incorrect see PR642.
507 case ISD::SETEQ: return PPC::BEQ;
508 case ISD::SETONE: // FIXME: This is incorrect see PR642.
509 case ISD::SETNE: return PPC::BNE;
510 case ISD::SETOLT: // FIXME: This is incorrect see PR642.
512 case ISD::SETLT: return PPC::BLT;
513 case ISD::SETOLE: // FIXME: This is incorrect see PR642.
515 case ISD::SETLE: return PPC::BLE;
516 case ISD::SETOGT: // FIXME: This is incorrect see PR642.
518 case ISD::SETGT: return PPC::BGT;
519 case ISD::SETOGE: // FIXME: This is incorrect see PR642.
521 case ISD::SETGE: return PPC::BGE;
523 case ISD::SETO: return PPC::BUN;
524 case ISD::SETUO: return PPC::BNU;
529 /// getCRIdxForSetCC - Return the index of the condition register field
530 /// associated with the SetCC condition, and whether or not the field is
531 /// treated as inverted. That is, lt = 0; ge = 0 inverted.
532 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool& Inv) {
534 default: assert(0 && "Unknown condition!"); abort();
535 case ISD::SETOLT: // FIXME: This is incorrect see PR642.
537 case ISD::SETLT: Inv = false; return 0;
538 case ISD::SETOGE: // FIXME: This is incorrect see PR642.
540 case ISD::SETGE: Inv = true; return 0;
541 case ISD::SETOGT: // FIXME: This is incorrect see PR642.
543 case ISD::SETGT: Inv = false; return 1;
544 case ISD::SETOLE: // FIXME: This is incorrect see PR642.
546 case ISD::SETLE: Inv = true; return 1;
547 case ISD::SETOEQ: // FIXME: This is incorrect see PR642.
548 case ISD::SETEQ: Inv = false; return 2;
549 case ISD::SETONE: // FIXME: This is incorrect see PR642.
550 case ISD::SETNE: Inv = true; return 2;
551 case ISD::SETO: Inv = true; return 3;
552 case ISD::SETUO: Inv = false; return 3;
557 SDOperand PPCDAGToDAGISel::SelectDYNAMIC_STACKALLOC(SDOperand Op) {
560 // FIXME: We are currently ignoring the requested alignment for handling
561 // greater than the stack alignment. This will need to be revisited at some
562 // point. Align = N.getOperand(2);
563 if (!isa<ConstantSDNode>(N->getOperand(2)) ||
564 cast<ConstantSDNode>(N->getOperand(2))->getValue() != 0) {
565 std::cerr << "Cannot allocate stack object with greater alignment than"
566 << " the stack alignment yet!";
569 SDOperand Chain = Select(N->getOperand(0));
570 SDOperand Amt = Select(N->getOperand(1));
572 SDOperand R1Reg = CurDAG->getRegister(PPC::R1, MVT::i32);
574 SDOperand R1Val = CurDAG->getCopyFromReg(Chain, PPC::R1, MVT::i32);
575 Chain = R1Val.getValue(1);
577 // Subtract the amount (guaranteed to be a multiple of the stack alignment)
578 // from the stack pointer, giving us the result pointer.
579 SDOperand Result = CurDAG->getTargetNode(PPC::SUBF, MVT::i32, Amt, R1Val);
581 // Copy this result back into R1.
582 Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, Chain, R1Reg, Result);
584 // Copy this result back out of R1 to make sure we're not using the stack
585 // space without decrementing the stack pointer.
586 Result = CurDAG->getCopyFromReg(Chain, PPC::R1, MVT::i32);
588 // Finally, replace the DYNAMIC_STACKALLOC with the copyfromreg.
589 CodeGenMap[Op.getValue(0)] = Result;
590 CodeGenMap[Op.getValue(1)] = Result.getValue(1);
591 return SDOperand(Result.Val, Op.ResNo);
594 SDOperand PPCDAGToDAGISel::SelectADD_PARTS(SDOperand Op) {
596 SDOperand LHSL = Select(N->getOperand(0));
597 SDOperand LHSH = Select(N->getOperand(1));
600 bool ME = false, ZE = false;
601 if (isIntImmediate(N->getOperand(3), Imm)) {
602 ME = (signed)Imm == -1;
606 std::vector<SDOperand> Result;
607 SDOperand CarryFromLo;
608 if (isIntImmediate(N->getOperand(2), Imm) &&
609 ((signed)Imm >= -32768 || (signed)Imm < 32768)) {
610 // Codegen the low 32 bits of the add. Interestingly, there is no
611 // shifted form of add immediate carrying.
612 CarryFromLo = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
613 LHSL, getI32Imm(Imm));
615 CarryFromLo = CurDAG->getTargetNode(PPC::ADDC, MVT::i32, MVT::Flag,
616 LHSL, Select(N->getOperand(2)));
618 CarryFromLo = CarryFromLo.getValue(1);
620 // Codegen the high 32 bits, adding zero, minus one, or the full value
621 // along with the carry flag produced by addc/addic.
624 ResultHi = CurDAG->getTargetNode(PPC::ADDZE, MVT::i32, LHSH, CarryFromLo);
626 ResultHi = CurDAG->getTargetNode(PPC::ADDME, MVT::i32, LHSH, CarryFromLo);
628 ResultHi = CurDAG->getTargetNode(PPC::ADDE, MVT::i32, LHSH,
629 Select(N->getOperand(3)), CarryFromLo);
630 Result.push_back(CarryFromLo.getValue(0));
631 Result.push_back(ResultHi);
633 CodeGenMap[Op.getValue(0)] = Result[0];
634 CodeGenMap[Op.getValue(1)] = Result[1];
635 return Result[Op.ResNo];
637 SDOperand PPCDAGToDAGISel::SelectSUB_PARTS(SDOperand Op) {
639 SDOperand LHSL = Select(N->getOperand(0));
640 SDOperand LHSH = Select(N->getOperand(1));
641 SDOperand RHSL = Select(N->getOperand(2));
642 SDOperand RHSH = Select(N->getOperand(3));
644 std::vector<SDOperand> Result;
645 Result.push_back(CurDAG->getTargetNode(PPC::SUBFC, MVT::i32, MVT::Flag,
647 Result.push_back(CurDAG->getTargetNode(PPC::SUBFE, MVT::i32, RHSH, LHSH,
648 Result[0].getValue(1)));
649 CodeGenMap[Op.getValue(0)] = Result[0];
650 CodeGenMap[Op.getValue(1)] = Result[1];
651 return Result[Op.ResNo];
654 SDOperand PPCDAGToDAGISel::SelectSETCC(SDOperand Op) {
657 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
658 if (isIntImmediate(N->getOperand(1), Imm)) {
659 // We can codegen setcc op, imm very efficiently compared to a brcond.
660 // Check for those cases here.
663 SDOperand Op = Select(N->getOperand(0));
667 Op = CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op);
668 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(27),
669 getI32Imm(5), getI32Imm(31));
671 SDOperand AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
673 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
677 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(1),
678 getI32Imm(31), getI32Imm(31));
680 SDOperand T = CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op);
681 T = CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op);;
682 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, T, getI32Imm(1),
683 getI32Imm(31), getI32Imm(31));
686 } else if (Imm == ~0U) { // setcc op, -1
687 SDOperand Op = Select(N->getOperand(0));
691 Op = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
693 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
694 CurDAG->getTargetNode(PPC::LI, MVT::i32,
698 Op = CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op);
699 SDOperand AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
701 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
705 SDOperand AD = CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op,
707 SDOperand AN = CurDAG->getTargetNode(PPC::AND, MVT::i32, AD, Op);
708 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, AN, getI32Imm(1),
709 getI32Imm(31), getI32Imm(31));
712 Op = CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Op, getI32Imm(1),
713 getI32Imm(31), getI32Imm(31));
714 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, getI32Imm(1));
720 unsigned Idx = getCRIdxForSetCC(CC, Inv);
721 SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
724 // Force the ccreg into CR7.
725 SDOperand CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
727 SDOperand InFlag(0, 0); // Null incoming flag value.
728 CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), CR7Reg, CCReg,
731 if (TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor())
732 IntCR = CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg, CCReg);
734 IntCR = CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg);
737 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, IntCR,
738 getI32Imm((32-(3-Idx)) & 31),
739 getI32Imm(31), getI32Imm(31));
742 CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, IntCR,
743 getI32Imm((32-(3-Idx)) & 31),
744 getI32Imm(31),getI32Imm(31));
745 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
749 /// isCallCompatibleAddress - Return true if the specified 32-bit value is
750 /// representable in the immediate field of a Bx instruction.
751 static bool isCallCompatibleAddress(ConstantSDNode *C) {
752 int Addr = C->getValue();
753 if (Addr & 3) return false; // Low 2 bits are implicitly zero.
754 return (Addr << 6 >> 6) == Addr; // Top 6 bits have to be sext of immediate.
757 SDOperand PPCDAGToDAGISel::SelectCALL(SDOperand Op) {
759 SDOperand Chain = Select(N->getOperand(0));
762 std::vector<SDOperand> CallOperands;
764 if (GlobalAddressSDNode *GASD =
765 dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) {
766 CallOpcode = PPC::BL;
767 CallOperands.push_back(N->getOperand(1));
768 } else if (ExternalSymbolSDNode *ESSDN =
769 dyn_cast<ExternalSymbolSDNode>(N->getOperand(1))) {
770 CallOpcode = PPC::BL;
771 CallOperands.push_back(N->getOperand(1));
772 } else if (isa<ConstantSDNode>(N->getOperand(1)) &&
773 isCallCompatibleAddress(cast<ConstantSDNode>(N->getOperand(1)))) {
774 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(1));
775 CallOpcode = PPC::BLA;
776 CallOperands.push_back(getI32Imm((int)C->getValue() >> 2));
778 // Copy the callee address into the CTR register.
779 SDOperand Callee = Select(N->getOperand(1));
780 Chain = CurDAG->getTargetNode(PPC::MTCTR, MVT::Other, Callee, Chain);
782 // Copy the callee address into R12 on darwin.
783 SDOperand R12 = CurDAG->getRegister(PPC::R12, MVT::i32);
784 Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, Chain, R12, Callee);
786 CallOperands.push_back(R12);
787 CallOpcode = PPC::BCTRL;
790 unsigned GPR_idx = 0, FPR_idx = 0;
791 static const unsigned GPR[] = {
792 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
793 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
795 static const unsigned FPR[] = {
796 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
797 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
800 SDOperand InFlag; // Null incoming flag value.
802 for (unsigned i = 2, e = N->getNumOperands(); i != e; ++i) {
803 unsigned DestReg = 0;
804 MVT::ValueType RegTy = N->getOperand(i).getValueType();
805 if (RegTy == MVT::i32) {
806 assert(GPR_idx < 8 && "Too many int args");
807 DestReg = GPR[GPR_idx++];
809 assert(MVT::isFloatingPoint(N->getOperand(i).getValueType()) &&
810 "Unpromoted integer arg?");
811 assert(FPR_idx < 13 && "Too many fp args");
812 DestReg = FPR[FPR_idx++];
815 if (N->getOperand(i).getOpcode() != ISD::UNDEF) {
816 SDOperand Val = Select(N->getOperand(i));
817 Chain = CurDAG->getCopyToReg(Chain, DestReg, Val, InFlag);
818 InFlag = Chain.getValue(1);
819 CallOperands.push_back(CurDAG->getRegister(DestReg, RegTy));
823 // Finally, once everything is in registers to pass to the call, emit the
826 CallOperands.push_back(InFlag); // Strong dep on register copies.
828 CallOperands.push_back(Chain); // Weak dep on whatever occurs before
829 Chain = CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
832 std::vector<SDOperand> CallResults;
834 // If the call has results, copy the values out of the ret val registers.
835 switch (N->getValueType(0)) {
836 default: assert(0 && "Unexpected ret value!");
837 case MVT::Other: break;
839 if (N->getValueType(1) == MVT::i32) {
840 Chain = CurDAG->getCopyFromReg(Chain, PPC::R4, MVT::i32,
841 Chain.getValue(1)).getValue(1);
842 CallResults.push_back(Chain.getValue(0));
843 Chain = CurDAG->getCopyFromReg(Chain, PPC::R3, MVT::i32,
844 Chain.getValue(2)).getValue(1);
845 CallResults.push_back(Chain.getValue(0));
847 Chain = CurDAG->getCopyFromReg(Chain, PPC::R3, MVT::i32,
848 Chain.getValue(1)).getValue(1);
849 CallResults.push_back(Chain.getValue(0));
854 Chain = CurDAG->getCopyFromReg(Chain, PPC::F1, N->getValueType(0),
855 Chain.getValue(1)).getValue(1);
856 CallResults.push_back(Chain.getValue(0));
860 CallResults.push_back(Chain);
861 for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
862 CodeGenMap[Op.getValue(i)] = CallResults[i];
863 return CallResults[Op.ResNo];
866 // Select - Convert the specified operand from a target-independent to a
867 // target-specific node if it hasn't already been changed.
868 SDOperand PPCDAGToDAGISel::Select(SDOperand Op) {
870 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
871 N->getOpcode() < PPCISD::FIRST_NUMBER)
872 return Op; // Already selected.
874 // If this has already been converted, use it.
875 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
876 if (CGMI != CodeGenMap.end()) return CGMI->second;
878 switch (N->getOpcode()) {
880 case ISD::DYNAMIC_STACKALLOC: return SelectDYNAMIC_STACKALLOC(Op);
881 case ISD::ADD_PARTS: return SelectADD_PARTS(Op);
882 case ISD::SUB_PARTS: return SelectSUB_PARTS(Op);
883 case ISD::SETCC: return SelectSETCC(Op);
884 case ISD::CALL: return SelectCALL(Op);
885 case ISD::TAILCALL: return SelectCALL(Op);
886 case PPCISD::GlobalBaseReg: return getGlobalBaseReg();
888 case ISD::FrameIndex: {
889 int FI = cast<FrameIndexSDNode>(N)->getIndex();
891 return CurDAG->SelectNodeTo(N, PPC::ADDI, MVT::i32,
892 CurDAG->getTargetFrameIndex(FI, MVT::i32),
894 return CodeGenMap[Op] =
895 CurDAG->getTargetNode(PPC::ADDI, MVT::i32,
896 CurDAG->getTargetFrameIndex(FI, MVT::i32),
900 // FIXME: since this depends on the setting of the carry flag from the srawi
901 // we should really be making notes about that for the scheduler.
902 // FIXME: It sure would be nice if we could cheaply recognize the
903 // srl/add/sra pattern the dag combiner will generate for this as
904 // sra/addze rather than having to handle sdiv ourselves. oh well.
906 if (isIntImmediate(N->getOperand(1), Imm)) {
907 if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
909 CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
910 Select(N->getOperand(0)),
911 getI32Imm(Log2_32(Imm)));
912 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
913 Op.getValue(0), Op.getValue(1));
914 } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
916 CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
917 Select(N->getOperand(0)),
918 getI32Imm(Log2_32(-Imm)));
920 CurDAG->getTargetNode(PPC::ADDZE, MVT::i32, Op.getValue(0),
922 return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
926 // Other cases are autogenerated.
931 // If this is an and of a value rotated between 0 and 31 bits and then and'd
932 // with a mask, emit rlwinm
933 if (isIntImmediate(N->getOperand(1), Imm) && (isShiftedMask_32(Imm) ||
934 isShiftedMask_32(~Imm))) {
937 if (isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB, ME)) {
938 Val = Select(N->getOperand(0).getOperand(0));
939 } else if (Imm == 0) {
940 // AND X, 0 -> 0, not "rlwinm 32".
941 return Select(N->getOperand(1));
943 Val = Select(N->getOperand(0));
944 isRunOfOnes(Imm, MB, ME);
947 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Val, getI32Imm(SH),
948 getI32Imm(MB), getI32Imm(ME));
951 // Other cases are autogenerated.
955 if (SDNode *I = SelectBitfieldInsert(N))
956 return CodeGenMap[Op] = SDOperand(I, 0);
958 // Other cases are autogenerated.
961 unsigned Imm, SH, MB, ME;
962 if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
963 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
964 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32,
965 Select(N->getOperand(0).getOperand(0)),
966 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
969 // Other cases are autogenerated.
973 unsigned Imm, SH, MB, ME;
974 if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
975 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
976 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32,
977 Select(N->getOperand(0).getOperand(0)),
978 getI32Imm(SH & 0x1F), getI32Imm(MB),
982 // Other cases are autogenerated.
986 SDOperand Val = Select(N->getOperand(0));
987 MVT::ValueType Ty = N->getValueType(0);
988 if (N->getOperand(0).Val->hasOneUse()) {
990 switch (Val.isTargetOpcode() ? Val.getTargetOpcode() : 0) {
991 default: Opc = 0; break;
992 case PPC::FABSS: Opc = PPC::FNABSS; break;
993 case PPC::FABSD: Opc = PPC::FNABSD; break;
994 case PPC::FMADD: Opc = PPC::FNMADD; break;
995 case PPC::FMADDS: Opc = PPC::FNMADDS; break;
996 case PPC::FMSUB: Opc = PPC::FNMSUB; break;
997 case PPC::FMSUBS: Opc = PPC::FNMSUBS; break;
999 // If we inverted the opcode, then emit the new instruction with the
1000 // inverted opcode and the original instruction's operands. Otherwise,
1001 // fall through and generate a fneg instruction.
1003 if (Opc == PPC::FNABSS || Opc == PPC::FNABSD)
1004 return CurDAG->SelectNodeTo(N, Opc, Ty, Val.getOperand(0));
1006 return CurDAG->SelectNodeTo(N, Opc, Ty, Val.getOperand(0),
1007 Val.getOperand(1), Val.getOperand(2));
1010 // Other cases are autogenerated.
1013 case ISD::SELECT_CC: {
1014 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1016 // handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
1017 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1018 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
1019 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
1020 if (N1C->isNullValue() && N3C->isNullValue() &&
1021 N2C->getValue() == 1ULL && CC == ISD::SETNE) {
1022 SDOperand LHS = Select(N->getOperand(0));
1024 CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
1025 LHS, getI32Imm(~0U));
1026 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, Tmp, LHS,
1030 SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
1031 unsigned BROpc = getBCCForSetCC(CC);
1033 bool isFP = MVT::isFloatingPoint(N->getValueType(0));
1034 unsigned SelectCCOp;
1035 if (MVT::isInteger(N->getValueType(0)))
1036 SelectCCOp = PPC::SELECT_CC_Int;
1037 else if (N->getValueType(0) == MVT::f32)
1038 SelectCCOp = PPC::SELECT_CC_F4;
1040 SelectCCOp = PPC::SELECT_CC_F8;
1041 return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), CCReg,
1042 Select(N->getOperand(2)),
1043 Select(N->getOperand(3)),
1048 SDOperand Chain = Select(N->getOperand(0)); // Token chain.
1050 if (N->getNumOperands() == 2) {
1051 SDOperand Val = Select(N->getOperand(1));
1052 if (N->getOperand(1).getValueType() == MVT::i32) {
1053 Chain = CurDAG->getCopyToReg(Chain, PPC::R3, Val);
1055 assert(MVT::isFloatingPoint(N->getOperand(1).getValueType()));
1056 Chain = CurDAG->getCopyToReg(Chain, PPC::F1, Val);
1058 } else if (N->getNumOperands() > 1) {
1059 assert(N->getOperand(1).getValueType() == MVT::i32 &&
1060 N->getOperand(2).getValueType() == MVT::i32 &&
1061 N->getNumOperands() == 3 && "Unknown two-register ret value!");
1062 Chain = CurDAG->getCopyToReg(Chain, PPC::R4, Select(N->getOperand(1)));
1063 Chain = CurDAG->getCopyToReg(Chain, PPC::R3, Select(N->getOperand(2)));
1066 // Finally, select this to a blr (return) instruction.
1067 return CurDAG->SelectNodeTo(N, PPC::BLR, MVT::Other, Chain);
1070 case ISD::BRTWOWAY_CC: {
1071 SDOperand Chain = Select(N->getOperand(0));
1072 MachineBasicBlock *Dest =
1073 cast<BasicBlockSDNode>(N->getOperand(4))->getBasicBlock();
1074 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
1075 SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC);
1077 // If this is a two way branch, then grab the fallthrough basic block
1078 // argument and build a PowerPC branch pseudo-op, suitable for long branch
1079 // conversion if necessary by the branch selection pass. Otherwise, emit a
1080 // standard conditional branch.
1081 if (N->getOpcode() == ISD::BRTWOWAY_CC) {
1082 SDOperand CondTrueBlock = N->getOperand(4);
1083 SDOperand CondFalseBlock = N->getOperand(5);
1085 // If the false case is the current basic block, then this is a self loop.
1086 // We do not want to emit "Loop: ... brcond Out; br Loop", as it adds an
1087 // extra dispatch group to the loop. Instead, invert the condition and
1088 // emit "Loop: ... br!cond Loop; br Out
1089 if (cast<BasicBlockSDNode>(CondFalseBlock)->getBasicBlock() == BB) {
1090 std::swap(CondTrueBlock, CondFalseBlock);
1091 CC = getSetCCInverse(CC,
1092 MVT::isInteger(N->getOperand(2).getValueType()));
1095 unsigned Opc = getBCCForSetCC(CC);
1096 SDOperand CB = CurDAG->getTargetNode(PPC::COND_BRANCH, MVT::Other,
1097 CondCode, getI32Imm(Opc),
1098 CondTrueBlock, CondFalseBlock,
1100 return CurDAG->SelectNodeTo(N, PPC::B, MVT::Other, CondFalseBlock, CB);
1102 // Iterate to the next basic block
1103 ilist<MachineBasicBlock>::iterator It = BB;
1106 // If the fallthrough path is off the end of the function, which would be
1107 // undefined behavior, set it to be the same as the current block because
1108 // we have nothing better to set it to, and leaving it alone will cause
1109 // the PowerPC Branch Selection pass to crash.
1110 if (It == BB->getParent()->end()) It = Dest;
1111 return CurDAG->SelectNodeTo(N, PPC::COND_BRANCH, MVT::Other, CondCode,
1112 getI32Imm(getBCCForSetCC(CC)),
1113 N->getOperand(4), CurDAG->getBasicBlock(It),
1119 return SelectCode(Op);
1123 /// createPPCISelDag - This pass converts a legalized DAG into a
1124 /// PowerPC-specific DAG, ready for instruction scheduling.
1126 FunctionPass *llvm::createPPCISelDag(TargetMachine &TM) {
1127 return new PPCDAGToDAGISel(TM);