1 //===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for PowerPC,
11 // converting from a legalized dag to a PPC dag.
13 //===----------------------------------------------------------------------===//
16 #include "PPCTargetMachine.h"
17 #include "PPCISelLowering.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/SSARegMap.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/SelectionDAGISel.h"
23 #include "llvm/Target/TargetOptions.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/Constants.h"
26 #include "llvm/GlobalValue.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/MathExtras.h"
32 Statistic<> FusedFP ("ppc-codegen", "Number of fused fp operations");
33 Statistic<> FrameOff("ppc-codegen", "Number of frame idx offsets collapsed");
35 //===--------------------------------------------------------------------===//
36 /// PPCDAGToDAGISel - PPC specific code to select PPC machine
37 /// instructions for SelectionDAG operations.
39 class PPCDAGToDAGISel : public SelectionDAGISel {
40 PPCTargetLowering PPCLowering;
41 unsigned GlobalBaseReg;
43 PPCDAGToDAGISel(TargetMachine &TM)
44 : SelectionDAGISel(PPCLowering), PPCLowering(TM) {}
46 virtual bool runOnFunction(Function &Fn) {
47 // Make sure we re-emit a set of the global base reg if necessary
49 return SelectionDAGISel::runOnFunction(Fn);
52 /// getI32Imm - Return a target constant with the specified value, of type
54 inline SDOperand getI32Imm(unsigned Imm) {
55 return CurDAG->getTargetConstant(Imm, MVT::i32);
58 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
59 /// base register. Return the virtual register that holds this value.
60 SDOperand getGlobalBaseReg();
62 // Select - Convert the specified operand from a target-independent to a
63 // target-specific node if it hasn't already been changed.
64 SDOperand Select(SDOperand Op);
66 SDNode *SelectBitfieldInsert(SDNode *N);
68 /// SelectCC - Select a comparison of the specified values with the
69 /// specified condition code, returning the CR# of the expression.
70 SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
72 /// SelectAddr - Given the specified address, return the two operands for a
73 /// load/store instruction, and return true if it should be an indexed [r+r]
75 bool SelectAddr(SDOperand Addr, SDOperand &Op1, SDOperand &Op2);
77 /// SelectAddrIndexed - Given the specified addressed, force it to be
78 /// represented as an indexed [r+r] operation, rather than possibly
79 /// returning [r+imm] as SelectAddr may.
80 void SelectAddrIndexed(SDOperand Addr, SDOperand &Op1, SDOperand &Op2);
82 SDOperand BuildSDIVSequence(SDNode *N);
83 SDOperand BuildUDIVSequence(SDNode *N);
85 /// InstructionSelectBasicBlock - This callback is invoked by
86 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
87 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
89 virtual const char *getPassName() const {
90 return "PowerPC DAG->DAG Pattern Instruction Selection";
93 // Include the pieces autogenerated from the target description.
94 #include "PPCGenDAGISel.inc"
97 SDOperand SelectDYNAMIC_STACKALLOC(SDOperand Op);
98 SDOperand SelectADD_PARTS(SDOperand Op);
99 SDOperand SelectSUB_PARTS(SDOperand Op);
100 SDOperand SelectSETCC(SDOperand Op);
101 SDOperand SelectCALL(SDOperand Op);
105 /// InstructionSelectBasicBlock - This callback is invoked by
106 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
107 void PPCDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
110 // The selection process is inherently a bottom-up recursive process (users
111 // select their uses before themselves). Given infinite stack space, we
112 // could just start selecting on the root and traverse the whole graph. In
113 // practice however, this causes us to run out of stack space on large basic
114 // blocks. To avoid this problem, select the entry node, then all its uses,
115 // iteratively instead of recursively.
116 std::vector<SDOperand> Worklist;
117 Worklist.push_back(DAG.getEntryNode());
119 // Note that we can do this in the PPC target (scanning forward across token
120 // chain edges) because no nodes ever get folded across these edges. On a
121 // target like X86 which supports load/modify/store operations, this would
122 // have to be more careful.
123 while (!Worklist.empty()) {
124 SDOperand Node = Worklist.back();
127 // Chose from the least deep of the top two nodes.
128 if (!Worklist.empty() &&
129 Worklist.back().Val->getNodeDepth() < Node.Val->getNodeDepth())
130 std::swap(Worklist.back(), Node);
132 if ((Node.Val->getOpcode() >= ISD::BUILTIN_OP_END &&
133 Node.Val->getOpcode() < PPCISD::FIRST_NUMBER) ||
134 CodeGenMap.count(Node)) continue;
136 for (SDNode::use_iterator UI = Node.Val->use_begin(),
137 E = Node.Val->use_end(); UI != E; ++UI) {
138 // Scan the values. If this use has a value that is a token chain, add it
141 for (unsigned i = 0, e = User->getNumValues(); i != e; ++i)
142 if (User->getValueType(i) == MVT::Other) {
143 Worklist.push_back(SDOperand(User, i));
148 // Finally, legalize this node.
152 // Select target instructions for the DAG.
153 DAG.setRoot(Select(DAG.getRoot()));
155 DAG.RemoveDeadNodes();
157 // Emit machine code to BB.
158 ScheduleAndEmitDAG(DAG);
161 /// getGlobalBaseReg - Output the instructions required to put the
162 /// base address to use for accessing globals into a register.
164 SDOperand PPCDAGToDAGISel::getGlobalBaseReg() {
165 if (!GlobalBaseReg) {
166 // Insert the set of GlobalBaseReg into the first MBB of the function
167 MachineBasicBlock &FirstMBB = BB->getParent()->front();
168 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
169 SSARegMap *RegMap = BB->getParent()->getSSARegMap();
170 // FIXME: when we get to LP64, we will need to create the appropriate
171 // type of register here.
172 GlobalBaseReg = RegMap->createVirtualRegister(PPC::GPRCRegisterClass);
173 BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
174 BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg);
176 return CurDAG->getRegister(GlobalBaseReg, MVT::i32);
180 // isIntImmediate - This method tests to see if a constant operand.
181 // If so Imm will receive the 32 bit value.
182 static bool isIntImmediate(SDNode *N, unsigned& Imm) {
183 if (N->getOpcode() == ISD::Constant) {
184 Imm = cast<ConstantSDNode>(N)->getValue();
190 // isOprShiftImm - Returns true if the specified operand is a shift opcode with
191 // a immediate shift count less than 32.
192 static bool isOprShiftImm(SDNode *N, unsigned& Opc, unsigned& SH) {
193 Opc = N->getOpcode();
194 return (Opc == ISD::SHL || Opc == ISD::SRL || Opc == ISD::SRA) &&
195 isIntImmediate(N->getOperand(1).Val, SH) && SH < 32;
198 // isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s with
199 // any number of 0s on either side. The 1s are allowed to wrap from LSB to
200 // MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 0x0F0F0000 is
201 // not, since all 1s are not contiguous.
202 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
203 if (isShiftedMask_32(Val)) {
204 // look for the first non-zero bit
205 MB = CountLeadingZeros_32(Val);
206 // look for the first zero bit after the run of ones
207 ME = CountLeadingZeros_32((Val - 1) ^ Val);
210 Val = ~Val; // invert mask
211 if (isShiftedMask_32(Val)) {
212 // effectively look for the first zero bit
213 ME = CountLeadingZeros_32(Val) - 1;
214 // effectively look for the first one bit after the run of zeros
215 MB = CountLeadingZeros_32((Val - 1) ^ Val) + 1;
223 // isRotateAndMask - Returns true if Mask and Shift can be folded into a rotate
224 // and mask opcode and mask operation.
225 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask,
226 unsigned &SH, unsigned &MB, unsigned &ME) {
227 // Don't even go down this path for i64, since different logic will be
228 // necessary for rldicl/rldicr/rldimi.
229 if (N->getValueType(0) != MVT::i32)
233 unsigned Indeterminant = ~0; // bit mask marking indeterminant results
234 unsigned Opcode = N->getOpcode();
235 if (N->getNumOperands() != 2 ||
236 !isIntImmediate(N->getOperand(1).Val, Shift) || (Shift > 31))
239 if (Opcode == ISD::SHL) {
240 // apply shift left to mask if it comes first
241 if (IsShiftMask) Mask = Mask << Shift;
242 // determine which bits are made indeterminant by shift
243 Indeterminant = ~(0xFFFFFFFFu << Shift);
244 } else if (Opcode == ISD::SRL) {
245 // apply shift right to mask if it comes first
246 if (IsShiftMask) Mask = Mask >> Shift;
247 // determine which bits are made indeterminant by shift
248 Indeterminant = ~(0xFFFFFFFFu >> Shift);
249 // adjust for the left rotate
255 // if the mask doesn't intersect any Indeterminant bits
256 if (Mask && !(Mask & Indeterminant)) {
258 // make sure the mask is still a mask (wrap arounds may not be)
259 return isRunOfOnes(Mask, MB, ME);
264 // isOpcWithIntImmediate - This method tests to see if the node is a specific
265 // opcode and that it has a immediate integer right operand.
266 // If so Imm will receive the 32 bit value.
267 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
268 return N->getOpcode() == Opc && isIntImmediate(N->getOperand(1).Val, Imm);
271 // isOprNot - Returns true if the specified operand is an xor with immediate -1.
272 static bool isOprNot(SDNode *N) {
274 return isOpcWithIntImmediate(N, ISD::XOR, Imm) && (signed)Imm == -1;
277 // Immediate constant composers.
278 // Lo16 - grabs the lo 16 bits from a 32 bit constant.
279 // Hi16 - grabs the hi 16 bits from a 32 bit constant.
280 // HA16 - computes the hi bits required if the lo bits are add/subtracted in
282 static unsigned Lo16(unsigned x) { return x & 0x0000FFFF; }
283 static unsigned Hi16(unsigned x) { return Lo16(x >> 16); }
284 static unsigned HA16(unsigned x) { return Hi16((signed)x - (signed short)x); }
286 // isIntImmediate - This method tests to see if a constant operand.
287 // If so Imm will receive the 32 bit value.
288 static bool isIntImmediate(SDOperand N, unsigned& Imm) {
289 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
290 Imm = (unsigned)CN->getSignExtended();
296 /// SelectBitfieldInsert - turn an or of two masked values into
297 /// the rotate left word immediate then mask insert (rlwimi) instruction.
298 /// Returns true on success, false if the caller still needs to select OR.
300 /// Patterns matched:
301 /// 1. or shl, and 5. or and, and
302 /// 2. or and, shl 6. or shl, shr
303 /// 3. or shr, and 7. or shr, shl
305 SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
306 bool IsRotate = false;
307 unsigned TgtMask = 0xFFFFFFFF, InsMask = 0xFFFFFFFF, SH = 0;
310 SDOperand Op0 = N->getOperand(0);
311 SDOperand Op1 = N->getOperand(1);
313 unsigned Op0Opc = Op0.getOpcode();
314 unsigned Op1Opc = Op1.getOpcode();
316 // Verify that we have the correct opcodes
317 if (ISD::SHL != Op0Opc && ISD::SRL != Op0Opc && ISD::AND != Op0Opc)
319 if (ISD::SHL != Op1Opc && ISD::SRL != Op1Opc && ISD::AND != Op1Opc)
322 // Generate Mask value for Target
323 if (isIntImmediate(Op0.getOperand(1), Value)) {
325 case ISD::SHL: TgtMask <<= Value; break;
326 case ISD::SRL: TgtMask >>= Value; break;
327 case ISD::AND: TgtMask &= Value; break;
333 // Generate Mask value for Insert
334 if (!isIntImmediate(Op1.getOperand(1), Value))
341 if (Op0Opc == ISD::SRL) IsRotate = true;
347 if (Op0Opc == ISD::SHL) IsRotate = true;
354 // If both of the inputs are ANDs and one of them has a logical shift by
355 // constant as its input, make that AND the inserted value so that we can
356 // combine the shift into the rotate part of the rlwimi instruction
357 bool IsAndWithShiftOp = false;
358 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
359 if (Op1.getOperand(0).getOpcode() == ISD::SHL ||
360 Op1.getOperand(0).getOpcode() == ISD::SRL) {
361 if (isIntImmediate(Op1.getOperand(0).getOperand(1), Value)) {
362 SH = Op1.getOperand(0).getOpcode() == ISD::SHL ? Value : 32 - Value;
363 IsAndWithShiftOp = true;
365 } else if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
366 Op0.getOperand(0).getOpcode() == ISD::SRL) {
367 if (isIntImmediate(Op0.getOperand(0).getOperand(1), Value)) {
369 std::swap(TgtMask, InsMask);
370 SH = Op1.getOperand(0).getOpcode() == ISD::SHL ? Value : 32 - Value;
371 IsAndWithShiftOp = true;
376 // Verify that the Target mask and Insert mask together form a full word mask
377 // and that the Insert mask is a run of set bits (which implies both are runs
378 // of set bits). Given that, Select the arguments and generate the rlwimi
381 if (((TgtMask & InsMask) == 0) && isRunOfOnes(InsMask, MB, ME)) {
382 bool fullMask = (TgtMask ^ InsMask) == 0xFFFFFFFF;
383 bool Op0IsAND = Op0Opc == ISD::AND;
384 // Check for rotlwi / rotrwi here, a special case of bitfield insert
385 // where both bitfield halves are sourced from the same value.
386 if (IsRotate && fullMask &&
387 N->getOperand(0).getOperand(0) == N->getOperand(1).getOperand(0)) {
388 Op0 = CurDAG->getTargetNode(PPC::RLWINM, MVT::i32,
389 Select(N->getOperand(0).getOperand(0)),
390 getI32Imm(SH), getI32Imm(0), getI32Imm(31));
393 SDOperand Tmp1 = (Op0IsAND && fullMask) ? Select(Op0.getOperand(0))
395 SDOperand Tmp2 = IsAndWithShiftOp ? Select(Op1.getOperand(0).getOperand(0))
396 : Select(Op1.getOperand(0));
397 Op0 = CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Tmp1, Tmp2,
398 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
404 /// SelectAddr - Given the specified address, return the two operands for a
405 /// load/store instruction, and return true if it should be an indexed [r+r]
407 bool PPCDAGToDAGISel::SelectAddr(SDOperand Addr, SDOperand &Op1,
410 if (Addr.getOpcode() == ISD::ADD) {
411 if (isIntImmediate(Addr.getOperand(1), imm) && isInt16(imm)) {
412 Op1 = getI32Imm(Lo16(imm));
413 if (FrameIndexSDNode *FI =
414 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
416 Op2 = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
418 Op2 = Select(Addr.getOperand(0));
421 } else if (Addr.getOperand(1).getOpcode() == PPCISD::Lo) {
422 // Match LOAD (ADD (X, Lo(G))).
423 assert(!cast<ConstantSDNode>(Addr.getOperand(1).getOperand(1))->getValue()
424 && "Cannot handle constant offsets yet!");
425 Op1 = Addr.getOperand(1).getOperand(0); // The global address.
426 assert(Op1.getOpcode() == ISD::TargetGlobalAddress);
427 Op2 = Select(Addr.getOperand(0));
428 return false; // [&g+r]
430 Op1 = Select(Addr.getOperand(0));
431 Op2 = Select(Addr.getOperand(1));
432 return true; // [r+r]
436 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Addr)) {
438 Op2 = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
440 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Addr)) {
443 Op2 = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(),Op1);
445 Op2 = CurDAG->getTargetNode(PPC::LIS, MVT::i32, Op1);
453 /// SelectAddrIndexed - Given the specified addressed, force it to be
454 /// represented as an indexed [r+r] operation, rather than possibly
455 /// returning [r+imm] as SelectAddr may.
456 void PPCDAGToDAGISel::SelectAddrIndexed(SDOperand Addr, SDOperand &Op1,
458 if (Addr.getOpcode() == ISD::ADD) {
459 Op1 = Select(Addr.getOperand(0));
460 Op2 = Select(Addr.getOperand(1));
464 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Addr)) {
465 Op1 = CurDAG->getTargetNode(PPC::LI, MVT::i32, getI32Imm(0));
466 Op2 = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
469 Op1 = CurDAG->getTargetNode(PPC::LI, MVT::i32, getI32Imm(0));
473 /// SelectCC - Select a comparison of the specified values with the specified
474 /// condition code, returning the CR# of the expression.
475 SDOperand PPCDAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS,
477 // Always select the LHS.
480 // Use U to determine whether the SETCC immediate range is signed or not.
481 if (MVT::isInteger(LHS.getValueType())) {
482 bool U = ISD::isUnsignedIntSetCC(CC);
484 if (isIntImmediate(RHS, Imm) &&
485 ((U && isUInt16(Imm)) || (!U && isInt16(Imm))))
486 return CurDAG->getTargetNode(U ? PPC::CMPLWI : PPC::CMPWI, MVT::i32,
487 LHS, getI32Imm(Lo16(Imm)));
488 return CurDAG->getTargetNode(U ? PPC::CMPLW : PPC::CMPW, MVT::i32,
490 } else if (LHS.getValueType() == MVT::f32) {
491 return CurDAG->getTargetNode(PPC::FCMPUS, MVT::i32, LHS, Select(RHS));
493 return CurDAG->getTargetNode(PPC::FCMPUD, MVT::i32, LHS, Select(RHS));
497 /// getBCCForSetCC - Returns the PowerPC condition branch mnemonic corresponding
499 static unsigned getBCCForSetCC(ISD::CondCode CC) {
501 default: assert(0 && "Unknown condition!"); abort();
502 case ISD::SETOEQ: // FIXME: This is incorrect see PR642.
503 case ISD::SETEQ: return PPC::BEQ;
504 case ISD::SETONE: // FIXME: This is incorrect see PR642.
505 case ISD::SETNE: return PPC::BNE;
506 case ISD::SETOLT: // FIXME: This is incorrect see PR642.
508 case ISD::SETLT: return PPC::BLT;
509 case ISD::SETOLE: // FIXME: This is incorrect see PR642.
511 case ISD::SETLE: return PPC::BLE;
512 case ISD::SETOGT: // FIXME: This is incorrect see PR642.
514 case ISD::SETGT: return PPC::BGT;
515 case ISD::SETOGE: // FIXME: This is incorrect see PR642.
517 case ISD::SETGE: return PPC::BGE;
519 case ISD::SETO: return PPC::BUN;
520 case ISD::SETUO: return PPC::BNU;
525 /// getCRIdxForSetCC - Return the index of the condition register field
526 /// associated with the SetCC condition, and whether or not the field is
527 /// treated as inverted. That is, lt = 0; ge = 0 inverted.
528 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool& Inv) {
530 default: assert(0 && "Unknown condition!"); abort();
531 case ISD::SETOLT: // FIXME: This is incorrect see PR642.
533 case ISD::SETLT: Inv = false; return 0;
534 case ISD::SETOGE: // FIXME: This is incorrect see PR642.
536 case ISD::SETGE: Inv = true; return 0;
537 case ISD::SETOGT: // FIXME: This is incorrect see PR642.
539 case ISD::SETGT: Inv = false; return 1;
540 case ISD::SETOLE: // FIXME: This is incorrect see PR642.
542 case ISD::SETLE: Inv = true; return 1;
543 case ISD::SETOEQ: // FIXME: This is incorrect see PR642.
544 case ISD::SETEQ: Inv = false; return 2;
545 case ISD::SETONE: // FIXME: This is incorrect see PR642.
546 case ISD::SETNE: Inv = true; return 2;
547 case ISD::SETO: Inv = true; return 3;
548 case ISD::SETUO: Inv = false; return 3;
553 SDOperand PPCDAGToDAGISel::SelectDYNAMIC_STACKALLOC(SDOperand Op) {
556 // FIXME: We are currently ignoring the requested alignment for handling
557 // greater than the stack alignment. This will need to be revisited at some
558 // point. Align = N.getOperand(2);
559 if (!isa<ConstantSDNode>(N->getOperand(2)) ||
560 cast<ConstantSDNode>(N->getOperand(2))->getValue() != 0) {
561 std::cerr << "Cannot allocate stack object with greater alignment than"
562 << " the stack alignment yet!";
565 SDOperand Chain = Select(N->getOperand(0));
566 SDOperand Amt = Select(N->getOperand(1));
568 SDOperand R1Reg = CurDAG->getRegister(PPC::R1, MVT::i32);
570 SDOperand R1Val = CurDAG->getCopyFromReg(Chain, PPC::R1, MVT::i32);
571 Chain = R1Val.getValue(1);
573 // Subtract the amount (guaranteed to be a multiple of the stack alignment)
574 // from the stack pointer, giving us the result pointer.
575 SDOperand Result = CurDAG->getTargetNode(PPC::SUBF, MVT::i32, Amt, R1Val);
577 // Copy this result back into R1.
578 Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, Chain, R1Reg, Result);
580 // Copy this result back out of R1 to make sure we're not using the stack
581 // space without decrementing the stack pointer.
582 Result = CurDAG->getCopyFromReg(Chain, PPC::R1, MVT::i32);
584 // Finally, replace the DYNAMIC_STACKALLOC with the copyfromreg.
585 CodeGenMap[Op.getValue(0)] = Result;
586 CodeGenMap[Op.getValue(1)] = Result.getValue(1);
587 return SDOperand(Result.Val, Op.ResNo);
590 SDOperand PPCDAGToDAGISel::SelectADD_PARTS(SDOperand Op) {
592 SDOperand LHSL = Select(N->getOperand(0));
593 SDOperand LHSH = Select(N->getOperand(1));
596 bool ME = false, ZE = false;
597 if (isIntImmediate(N->getOperand(3), Imm)) {
598 ME = (signed)Imm == -1;
602 std::vector<SDOperand> Result;
603 SDOperand CarryFromLo;
604 if (isIntImmediate(N->getOperand(2), Imm) &&
605 ((signed)Imm >= -32768 || (signed)Imm < 32768)) {
606 // Codegen the low 32 bits of the add. Interestingly, there is no
607 // shifted form of add immediate carrying.
608 CarryFromLo = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
609 LHSL, getI32Imm(Imm));
611 CarryFromLo = CurDAG->getTargetNode(PPC::ADDC, MVT::i32, MVT::Flag,
612 LHSL, Select(N->getOperand(2)));
614 CarryFromLo = CarryFromLo.getValue(1);
616 // Codegen the high 32 bits, adding zero, minus one, or the full value
617 // along with the carry flag produced by addc/addic.
620 ResultHi = CurDAG->getTargetNode(PPC::ADDZE, MVT::i32, LHSH, CarryFromLo);
622 ResultHi = CurDAG->getTargetNode(PPC::ADDME, MVT::i32, LHSH, CarryFromLo);
624 ResultHi = CurDAG->getTargetNode(PPC::ADDE, MVT::i32, LHSH,
625 Select(N->getOperand(3)), CarryFromLo);
626 Result.push_back(CarryFromLo.getValue(0));
627 Result.push_back(ResultHi);
629 CodeGenMap[Op.getValue(0)] = Result[0];
630 CodeGenMap[Op.getValue(1)] = Result[1];
631 return Result[Op.ResNo];
633 SDOperand PPCDAGToDAGISel::SelectSUB_PARTS(SDOperand Op) {
635 SDOperand LHSL = Select(N->getOperand(0));
636 SDOperand LHSH = Select(N->getOperand(1));
637 SDOperand RHSL = Select(N->getOperand(2));
638 SDOperand RHSH = Select(N->getOperand(3));
640 std::vector<SDOperand> Result;
641 Result.push_back(CurDAG->getTargetNode(PPC::SUBFC, MVT::i32, MVT::Flag,
643 Result.push_back(CurDAG->getTargetNode(PPC::SUBFE, MVT::i32, RHSH, LHSH,
644 Result[0].getValue(1)));
645 CodeGenMap[Op.getValue(0)] = Result[0];
646 CodeGenMap[Op.getValue(1)] = Result[1];
647 return Result[Op.ResNo];
650 SDOperand PPCDAGToDAGISel::SelectSETCC(SDOperand Op) {
653 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
654 if (isIntImmediate(N->getOperand(1), Imm)) {
655 // We can codegen setcc op, imm very efficiently compared to a brcond.
656 // Check for those cases here.
659 SDOperand Op = Select(N->getOperand(0));
663 Op = CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op);
664 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(27),
665 getI32Imm(5), getI32Imm(31));
667 SDOperand AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
669 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
673 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(1),
674 getI32Imm(31), getI32Imm(31));
676 SDOperand T = CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op);
677 T = CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op);;
678 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, T, getI32Imm(1),
679 getI32Imm(31), getI32Imm(31));
682 } else if (Imm == ~0U) { // setcc op, -1
683 SDOperand Op = Select(N->getOperand(0));
687 Op = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
689 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
690 CurDAG->getTargetNode(PPC::LI, MVT::i32,
694 Op = CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op);
695 SDOperand AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
697 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
701 SDOperand AD = CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op,
703 SDOperand AN = CurDAG->getTargetNode(PPC::AND, MVT::i32, AD, Op);
704 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, AN, getI32Imm(1),
705 getI32Imm(31), getI32Imm(31));
708 Op = CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Op, getI32Imm(1),
709 getI32Imm(31), getI32Imm(31));
710 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, getI32Imm(1));
716 unsigned Idx = getCRIdxForSetCC(CC, Inv);
717 SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
720 // Force the ccreg into CR7.
721 SDOperand CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
723 SDOperand InFlag; // Null incoming flag value.
724 CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), CR7Reg, CCReg,
727 if (TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor())
728 IntCR = CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg, CCReg);
730 IntCR = CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg);
733 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, IntCR,
734 getI32Imm((32-(3-Idx)) & 31),
735 getI32Imm(31), getI32Imm(31));
738 CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, IntCR,
739 getI32Imm((32-(3-Idx)) & 31),
740 getI32Imm(31),getI32Imm(31));
741 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
745 /// isCallCompatibleAddress - Return true if the specified 32-bit value is
746 /// representable in the immediate field of a Bx instruction.
747 static bool isCallCompatibleAddress(ConstantSDNode *C) {
748 int Addr = C->getValue();
749 if (Addr & 3) return false; // Low 2 bits are implicitly zero.
750 return (Addr << 6 >> 6) == Addr; // Top 6 bits have to be sext of immediate.
753 SDOperand PPCDAGToDAGISel::SelectCALL(SDOperand Op) {
755 SDOperand Chain = Select(N->getOperand(0));
758 std::vector<SDOperand> CallOperands;
760 if (GlobalAddressSDNode *GASD =
761 dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) {
762 CallOpcode = PPC::BL;
763 CallOperands.push_back(N->getOperand(1));
764 } else if (ExternalSymbolSDNode *ESSDN =
765 dyn_cast<ExternalSymbolSDNode>(N->getOperand(1))) {
766 CallOpcode = PPC::BL;
767 CallOperands.push_back(N->getOperand(1));
768 } else if (isa<ConstantSDNode>(N->getOperand(1)) &&
769 isCallCompatibleAddress(cast<ConstantSDNode>(N->getOperand(1)))) {
770 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(1));
771 CallOpcode = PPC::BLA;
772 CallOperands.push_back(getI32Imm((int)C->getValue() >> 2));
774 // Copy the callee address into the CTR register.
775 SDOperand Callee = Select(N->getOperand(1));
776 Chain = CurDAG->getTargetNode(PPC::MTCTR, MVT::Other, Callee, Chain);
778 // Copy the callee address into R12 on darwin.
779 SDOperand R12 = CurDAG->getRegister(PPC::R12, MVT::i32);
780 Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, Chain, R12, Callee);
782 CallOperands.push_back(R12);
783 CallOpcode = PPC::BCTRL;
786 unsigned GPR_idx = 0, FPR_idx = 0;
787 static const unsigned GPR[] = {
788 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
789 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
791 static const unsigned FPR[] = {
792 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
793 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
796 SDOperand InFlag; // Null incoming flag value.
798 for (unsigned i = 2, e = N->getNumOperands(); i != e; ++i) {
799 unsigned DestReg = 0;
800 MVT::ValueType RegTy = N->getOperand(i).getValueType();
801 if (RegTy == MVT::i32) {
802 assert(GPR_idx < 8 && "Too many int args");
803 DestReg = GPR[GPR_idx++];
805 assert(MVT::isFloatingPoint(N->getOperand(i).getValueType()) &&
806 "Unpromoted integer arg?");
807 assert(FPR_idx < 13 && "Too many fp args");
808 DestReg = FPR[FPR_idx++];
811 if (N->getOperand(i).getOpcode() != ISD::UNDEF) {
812 SDOperand Val = Select(N->getOperand(i));
813 Chain = CurDAG->getCopyToReg(Chain, DestReg, Val, InFlag);
814 InFlag = Chain.getValue(1);
815 CallOperands.push_back(CurDAG->getRegister(DestReg, RegTy));
819 // Finally, once everything is in registers to pass to the call, emit the
822 CallOperands.push_back(InFlag); // Strong dep on register copies.
824 CallOperands.push_back(Chain); // Weak dep on whatever occurs before
825 Chain = CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
828 std::vector<SDOperand> CallResults;
830 // If the call has results, copy the values out of the ret val registers.
831 switch (N->getValueType(0)) {
832 default: assert(0 && "Unexpected ret value!");
833 case MVT::Other: break;
835 if (N->getValueType(1) == MVT::i32) {
836 Chain = CurDAG->getCopyFromReg(Chain, PPC::R4, MVT::i32,
837 Chain.getValue(1)).getValue(1);
838 CallResults.push_back(Chain.getValue(0));
839 Chain = CurDAG->getCopyFromReg(Chain, PPC::R3, MVT::i32,
840 Chain.getValue(2)).getValue(1);
841 CallResults.push_back(Chain.getValue(0));
843 Chain = CurDAG->getCopyFromReg(Chain, PPC::R3, MVT::i32,
844 Chain.getValue(1)).getValue(1);
845 CallResults.push_back(Chain.getValue(0));
850 Chain = CurDAG->getCopyFromReg(Chain, PPC::F1, N->getValueType(0),
851 Chain.getValue(1)).getValue(1);
852 CallResults.push_back(Chain.getValue(0));
856 CallResults.push_back(Chain);
857 for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
858 CodeGenMap[Op.getValue(i)] = CallResults[i];
859 return CallResults[Op.ResNo];
862 // Select - Convert the specified operand from a target-independent to a
863 // target-specific node if it hasn't already been changed.
864 SDOperand PPCDAGToDAGISel::Select(SDOperand Op) {
866 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
867 N->getOpcode() < PPCISD::FIRST_NUMBER)
868 return Op; // Already selected.
870 // If this has already been converted, use it.
871 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
872 if (CGMI != CodeGenMap.end()) return CGMI->second;
874 switch (N->getOpcode()) {
876 case ISD::BasicBlock: return CodeGenMap[Op] = Op;
877 case ISD::DYNAMIC_STACKALLOC: return SelectDYNAMIC_STACKALLOC(Op);
878 case ISD::ADD_PARTS: return SelectADD_PARTS(Op);
879 case ISD::SUB_PARTS: return SelectSUB_PARTS(Op);
880 case ISD::SETCC: return SelectSETCC(Op);
881 case ISD::CALL: return SelectCALL(Op);
882 case ISD::TAILCALL: return SelectCALL(Op);
883 case PPCISD::GlobalBaseReg: return getGlobalBaseReg();
885 case ISD::FrameIndex: {
886 int FI = cast<FrameIndexSDNode>(N)->getIndex();
888 return CurDAG->SelectNodeTo(N, PPC::ADDI, MVT::i32,
889 CurDAG->getTargetFrameIndex(FI, MVT::i32),
891 return CodeGenMap[Op] =
892 CurDAG->getTargetNode(PPC::ADDI, MVT::i32,
893 CurDAG->getTargetFrameIndex(FI, MVT::i32),
896 case ISD::ConstantPool: {
897 Constant *C = cast<ConstantPoolSDNode>(N)->get();
898 SDOperand Tmp, CPI = CurDAG->getTargetConstantPool(C, MVT::i32);
900 Tmp = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(),CPI);
902 Tmp = CurDAG->getTargetNode(PPC::LIS, MVT::i32, CPI);
904 return CurDAG->SelectNodeTo(N, PPC::LA, MVT::i32, Tmp, CPI);
905 return CodeGenMap[Op] = CurDAG->getTargetNode(PPC::LA, MVT::i32, Tmp, CPI);
908 MVT::ValueType Ty = N->getValueType(0);
909 if (!NoExcessFPPrecision) { // Match FMA ops
910 if (N->getOperand(0).getOpcode() == ISD::FMUL &&
911 N->getOperand(0).Val->hasOneUse()) {
912 ++FusedFP; // Statistic
913 return CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FMADD :PPC::FMADDS,
914 Ty, Select(N->getOperand(0).getOperand(0)),
915 Select(N->getOperand(0).getOperand(1)),
916 Select(N->getOperand(1)));
917 } else if (N->getOperand(1).getOpcode() == ISD::FMUL &&
918 N->getOperand(1).hasOneUse()) {
919 ++FusedFP; // Statistic
920 return CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FMADD :PPC::FMADDS,
921 Ty, Select(N->getOperand(1).getOperand(0)),
922 Select(N->getOperand(1).getOperand(1)),
923 Select(N->getOperand(0)));
927 // Other cases are autogenerated.
931 MVT::ValueType Ty = N->getValueType(0);
933 if (!NoExcessFPPrecision) { // Match FMA ops
934 if (N->getOperand(0).getOpcode() == ISD::FMUL &&
935 N->getOperand(0).Val->hasOneUse()) {
936 ++FusedFP; // Statistic
937 return CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FMSUB:PPC::FMSUBS,
938 Ty, Select(N->getOperand(0).getOperand(0)),
939 Select(N->getOperand(0).getOperand(1)),
940 Select(N->getOperand(1)));
941 } else if (N->getOperand(1).getOpcode() == ISD::FMUL &&
942 N->getOperand(1).Val->hasOneUse()) {
943 ++FusedFP; // Statistic
944 return CurDAG->SelectNodeTo(N, Ty == MVT::f64 ?PPC::FNMSUB:PPC::FNMSUBS,
945 Ty, Select(N->getOperand(1).getOperand(0)),
946 Select(N->getOperand(1).getOperand(1)),
947 Select(N->getOperand(0)));
951 // Other cases are autogenerated.
955 // FIXME: since this depends on the setting of the carry flag from the srawi
956 // we should really be making notes about that for the scheduler.
957 // FIXME: It sure would be nice if we could cheaply recognize the
958 // srl/add/sra pattern the dag combiner will generate for this as
959 // sra/addze rather than having to handle sdiv ourselves. oh well.
961 if (isIntImmediate(N->getOperand(1), Imm)) {
962 if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
964 CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
965 Select(N->getOperand(0)),
966 getI32Imm(Log2_32(Imm)));
967 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
968 Op.getValue(0), Op.getValue(1));
969 } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
971 CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
972 Select(N->getOperand(0)),
973 getI32Imm(Log2_32(-Imm)));
975 CurDAG->getTargetNode(PPC::ADDZE, MVT::i32, Op.getValue(0),
977 return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
981 // Other cases are autogenerated.
986 // If this is an and of a value rotated between 0 and 31 bits and then and'd
987 // with a mask, emit rlwinm
988 if (isIntImmediate(N->getOperand(1), Imm) && (isShiftedMask_32(Imm) ||
989 isShiftedMask_32(~Imm))) {
992 if (isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB, ME)) {
993 Val = Select(N->getOperand(0).getOperand(0));
994 } else if (Imm == 0) {
995 // AND X, 0 -> 0, not "rlwinm 32".
996 return Select(N->getOperand(1));
998 Val = Select(N->getOperand(0));
999 isRunOfOnes(Imm, MB, ME);
1002 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Val, getI32Imm(SH),
1003 getI32Imm(MB), getI32Imm(ME));
1006 // Other cases are autogenerated.
1010 if (SDNode *I = SelectBitfieldInsert(N))
1011 return CodeGenMap[Op] = SDOperand(I, 0);
1013 // Other cases are autogenerated.
1016 unsigned Imm, SH, MB, ME;
1017 if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
1018 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
1019 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32,
1020 Select(N->getOperand(0).getOperand(0)),
1021 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
1024 // Other cases are autogenerated.
1028 unsigned Imm, SH, MB, ME;
1029 if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
1030 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
1031 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32,
1032 Select(N->getOperand(0).getOperand(0)),
1033 getI32Imm(SH & 0x1F), getI32Imm(MB),
1037 // Other cases are autogenerated.
1041 SDOperand Val = Select(N->getOperand(0));
1042 MVT::ValueType Ty = N->getValueType(0);
1043 if (N->getOperand(0).Val->hasOneUse()) {
1045 switch (Val.isTargetOpcode() ? Val.getTargetOpcode() : 0) {
1046 default: Opc = 0; break;
1047 case PPC::FABSS: Opc = PPC::FNABSS; break;
1048 case PPC::FABSD: Opc = PPC::FNABSD; break;
1049 case PPC::FMADD: Opc = PPC::FNMADD; break;
1050 case PPC::FMADDS: Opc = PPC::FNMADDS; break;
1051 case PPC::FMSUB: Opc = PPC::FNMSUB; break;
1052 case PPC::FMSUBS: Opc = PPC::FNMSUBS; break;
1054 // If we inverted the opcode, then emit the new instruction with the
1055 // inverted opcode and the original instruction's operands. Otherwise,
1056 // fall through and generate a fneg instruction.
1058 if (Opc == PPC::FNABSS || Opc == PPC::FNABSD)
1059 return CurDAG->SelectNodeTo(N, Opc, Ty, Val.getOperand(0));
1061 return CurDAG->SelectNodeTo(N, Opc, Ty, Val.getOperand(0),
1062 Val.getOperand(1), Val.getOperand(2));
1066 return CurDAG->SelectNodeTo(N, PPC::FNEGS, MVT::f32, Val);
1068 return CurDAG->SelectNodeTo(N, PPC::FNEGD, MVT::f64, Val);
1073 case ISD::SEXTLOAD: {
1075 // If this is a vector load, then force this to be indexed addressing, since
1076 // altivec does not have immediate offsets for loads.
1078 if (N->getOpcode() == ISD::LOAD && MVT::isVector(N->getValueType(0))) {
1079 SelectAddrIndexed(N->getOperand(1), Op1, Op2);
1081 isIdx = SelectAddr(N->getOperand(1), Op1, Op2);
1083 MVT::ValueType TypeBeingLoaded = (N->getOpcode() == ISD::LOAD) ?
1084 N->getValueType(0) : cast<VTSDNode>(N->getOperand(3))->getVT();
1087 switch (TypeBeingLoaded) {
1088 default: N->dump(); assert(0 && "Cannot load this type!");
1090 case MVT::i8: Opc = isIdx ? PPC::LBZX : PPC::LBZ; break;
1092 if (N->getOpcode() == ISD::SEXTLOAD) { // SEXT load?
1093 Opc = isIdx ? PPC::LHAX : PPC::LHA;
1095 Opc = isIdx ? PPC::LHZX : PPC::LHZ;
1098 case MVT::i32: Opc = isIdx ? PPC::LWZX : PPC::LWZ; break;
1099 case MVT::f32: Opc = isIdx ? PPC::LFSX : PPC::LFS; break;
1100 case MVT::f64: Opc = isIdx ? PPC::LFDX : PPC::LFD; break;
1101 case MVT::v4f32: Opc = PPC::LVX; break;
1104 // If this is an f32 -> f64 load, emit the f32 load, then use an 'extending
1106 if (TypeBeingLoaded != MVT::f32 || N->getOpcode() == ISD::LOAD) {
1107 return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
1108 Op1, Op2, Select(N->getOperand(0))).
1111 std::vector<SDOperand> Ops;
1114 Ops.push_back(Select(N->getOperand(0)));
1115 SDOperand Res = CurDAG->getTargetNode(Opc, MVT::f32, MVT::Other, Ops);
1116 SDOperand Ext = CurDAG->getTargetNode(PPC::FMRSD, MVT::f64, Res);
1117 CodeGenMap[Op.getValue(0)] = Ext;
1118 CodeGenMap[Op.getValue(1)] = Res.getValue(1);
1120 return Res.getValue(1);
1125 case ISD::TRUNCSTORE:
1127 SDOperand AddrOp1, AddrOp2;
1128 // If this is a vector store, then force this to be indexed addressing,
1129 // since altivec does not have immediate offsets for stores.
1131 if (N->getOpcode() == ISD::STORE &&
1132 MVT::isVector(N->getOperand(1).getValueType())) {
1133 SelectAddrIndexed(N->getOperand(2), AddrOp1, AddrOp2);
1135 isIdx = SelectAddr(N->getOperand(2), AddrOp1, AddrOp2);
1139 if (N->getOpcode() == ISD::STORE) {
1140 switch (N->getOperand(1).getValueType()) {
1141 default: assert(0 && "unknown Type in store");
1142 case MVT::i32: Opc = isIdx ? PPC::STWX : PPC::STW; break;
1143 case MVT::f64: Opc = isIdx ? PPC::STFDX : PPC::STFD; break;
1144 case MVT::f32: Opc = isIdx ? PPC::STFSX : PPC::STFS; break;
1145 case MVT::v4f32: Opc = PPC::STVX;
1147 } else { //ISD::TRUNCSTORE
1148 switch(cast<VTSDNode>(N->getOperand(4))->getVT()) {
1149 default: assert(0 && "unknown Type in store");
1150 case MVT::i8: Opc = isIdx ? PPC::STBX : PPC::STB; break;
1151 case MVT::i16: Opc = isIdx ? PPC::STHX : PPC::STH; break;
1155 return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Select(N->getOperand(1)),
1156 AddrOp1, AddrOp2, Select(N->getOperand(0)));
1159 case ISD::SELECT_CC: {
1160 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1162 // handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
1163 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1164 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
1165 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
1166 if (N1C->isNullValue() && N3C->isNullValue() &&
1167 N2C->getValue() == 1ULL && CC == ISD::SETNE) {
1168 SDOperand LHS = Select(N->getOperand(0));
1170 CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
1171 LHS, getI32Imm(~0U));
1172 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, Tmp, LHS,
1176 SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
1177 unsigned BROpc = getBCCForSetCC(CC);
1179 bool isFP = MVT::isFloatingPoint(N->getValueType(0));
1180 unsigned SelectCCOp;
1181 if (MVT::isInteger(N->getValueType(0)))
1182 SelectCCOp = PPC::SELECT_CC_Int;
1183 else if (N->getValueType(0) == MVT::f32)
1184 SelectCCOp = PPC::SELECT_CC_F4;
1186 SelectCCOp = PPC::SELECT_CC_F8;
1187 return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), CCReg,
1188 Select(N->getOperand(2)),
1189 Select(N->getOperand(3)),
1194 SDOperand Chain = Select(N->getOperand(0)); // Token chain.
1196 if (N->getNumOperands() == 2) {
1197 SDOperand Val = Select(N->getOperand(1));
1198 if (N->getOperand(1).getValueType() == MVT::i32) {
1199 Chain = CurDAG->getCopyToReg(Chain, PPC::R3, Val);
1201 assert(MVT::isFloatingPoint(N->getOperand(1).getValueType()));
1202 Chain = CurDAG->getCopyToReg(Chain, PPC::F1, Val);
1204 } else if (N->getNumOperands() > 1) {
1205 assert(N->getOperand(1).getValueType() == MVT::i32 &&
1206 N->getOperand(2).getValueType() == MVT::i32 &&
1207 N->getNumOperands() == 3 && "Unknown two-register ret value!");
1208 Chain = CurDAG->getCopyToReg(Chain, PPC::R4, Select(N->getOperand(1)));
1209 Chain = CurDAG->getCopyToReg(Chain, PPC::R3, Select(N->getOperand(2)));
1212 // Finally, select this to a blr (return) instruction.
1213 return CurDAG->SelectNodeTo(N, PPC::BLR, MVT::Other, Chain);
1216 case ISD::BRTWOWAY_CC: {
1217 SDOperand Chain = Select(N->getOperand(0));
1218 MachineBasicBlock *Dest =
1219 cast<BasicBlockSDNode>(N->getOperand(4))->getBasicBlock();
1220 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
1221 SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC);
1223 // If this is a two way branch, then grab the fallthrough basic block
1224 // argument and build a PowerPC branch pseudo-op, suitable for long branch
1225 // conversion if necessary by the branch selection pass. Otherwise, emit a
1226 // standard conditional branch.
1227 if (N->getOpcode() == ISD::BRTWOWAY_CC) {
1228 SDOperand CondTrueBlock = N->getOperand(4);
1229 SDOperand CondFalseBlock = N->getOperand(5);
1231 // If the false case is the current basic block, then this is a self loop.
1232 // We do not want to emit "Loop: ... brcond Out; br Loop", as it adds an
1233 // extra dispatch group to the loop. Instead, invert the condition and
1234 // emit "Loop: ... br!cond Loop; br Out
1235 if (cast<BasicBlockSDNode>(CondFalseBlock)->getBasicBlock() == BB) {
1236 std::swap(CondTrueBlock, CondFalseBlock);
1237 CC = getSetCCInverse(CC,
1238 MVT::isInteger(N->getOperand(2).getValueType()));
1241 unsigned Opc = getBCCForSetCC(CC);
1242 SDOperand CB = CurDAG->getTargetNode(PPC::COND_BRANCH, MVT::Other,
1243 CondCode, getI32Imm(Opc),
1244 CondTrueBlock, CondFalseBlock,
1246 return CurDAG->SelectNodeTo(N, PPC::B, MVT::Other, CondFalseBlock, CB);
1248 // Iterate to the next basic block
1249 ilist<MachineBasicBlock>::iterator It = BB;
1252 // If the fallthrough path is off the end of the function, which would be
1253 // undefined behavior, set it to be the same as the current block because
1254 // we have nothing better to set it to, and leaving it alone will cause
1255 // the PowerPC Branch Selection pass to crash.
1256 if (It == BB->getParent()->end()) It = Dest;
1257 return CurDAG->SelectNodeTo(N, PPC::COND_BRANCH, MVT::Other, CondCode,
1258 getI32Imm(getBCCForSetCC(CC)),
1259 N->getOperand(4), CurDAG->getBasicBlock(It),
1265 return SelectCode(Op);
1269 /// createPPCISelDag - This pass converts a legalized DAG into a
1270 /// PowerPC-specific DAG, ready for instruction scheduling.
1272 FunctionPass *llvm::createPPCISelDag(TargetMachine &TM) {
1273 return new PPCDAGToDAGISel(TM);