1 //===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for PowerPC,
11 // converting from a legalized dag to a PPC dag.
13 //===----------------------------------------------------------------------===//
16 #include "PPCTargetMachine.h"
17 #include "PPCISelLowering.h"
18 #include "PPCHazardRecognizers.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/SSARegMap.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/Constants.h"
27 #include "llvm/GlobalValue.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/MathExtras.h"
36 Statistic<> FrameOff("ppc-codegen", "Number of frame idx offsets collapsed");
38 //===--------------------------------------------------------------------===//
39 /// PPCDAGToDAGISel - PPC specific code to select PPC machine
40 /// instructions for SelectionDAG operations.
42 class PPCDAGToDAGISel : public SelectionDAGISel {
44 PPCTargetLowering PPCLowering;
45 unsigned GlobalBaseReg;
47 PPCDAGToDAGISel(PPCTargetMachine &tm)
48 : SelectionDAGISel(PPCLowering), TM(tm),
49 PPCLowering(*TM.getTargetLowering()) {}
51 virtual bool runOnFunction(Function &Fn) {
52 // Make sure we re-emit a set of the global base reg if necessary
54 SelectionDAGISel::runOnFunction(Fn);
60 /// getI32Imm - Return a target constant with the specified value, of type
62 inline SDOperand getI32Imm(unsigned Imm) {
63 return CurDAG->getTargetConstant(Imm, MVT::i32);
66 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
67 /// base register. Return the virtual register that holds this value.
68 SDOperand getGlobalBaseReg();
70 // Select - Convert the specified operand from a target-independent to a
71 // target-specific node if it hasn't already been changed.
72 void Select(SDOperand &Result, SDOperand Op);
74 SDNode *SelectBitfieldInsert(SDNode *N);
76 /// SelectCC - Select a comparison of the specified values with the
77 /// specified condition code, returning the CR# of the expression.
78 SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
80 /// SelectAddrImm - Returns true if the address N can be represented by
81 /// a base register plus a signed 16-bit displacement [r+imm].
82 bool SelectAddrImm(SDOperand N, SDOperand &Disp, SDOperand &Base);
84 /// SelectAddrIdx - Given the specified addressed, check to see if it can be
85 /// represented as an indexed [r+r] operation. Returns false if it can
86 /// be represented by [r+imm], which are preferred.
87 bool SelectAddrIdx(SDOperand N, SDOperand &Base, SDOperand &Index);
89 /// SelectAddrIdxOnly - Given the specified addressed, force it to be
90 /// represented as an indexed [r+r] operation.
91 bool SelectAddrIdxOnly(SDOperand N, SDOperand &Base, SDOperand &Index);
93 /// SelectAddrImmShift - Returns true if the address N can be represented by
94 /// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable
95 /// for use by STD and friends.
96 bool SelectAddrImmShift(SDOperand N, SDOperand &Disp, SDOperand &Base);
98 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
99 /// inline asm expressions.
100 virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
102 std::vector<SDOperand> &OutOps,
105 switch (ConstraintCode) {
106 default: return true;
108 if (!SelectAddrIdx(Op, Op0, Op1))
109 SelectAddrImm(Op, Op0, Op1);
111 case 'o': // offsetable
112 if (!SelectAddrImm(Op, Op0, Op1)) {
113 Select(Op0, Op); // r+0.
117 case 'v': // not offsetable
118 SelectAddrIdxOnly(Op, Op0, Op1);
122 OutOps.push_back(Op0);
123 OutOps.push_back(Op1);
127 SDOperand BuildSDIVSequence(SDNode *N);
128 SDOperand BuildUDIVSequence(SDNode *N);
130 /// InstructionSelectBasicBlock - This callback is invoked by
131 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
132 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
134 void InsertVRSaveCode(Function &Fn);
136 virtual const char *getPassName() const {
137 return "PowerPC DAG->DAG Pattern Instruction Selection";
140 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
141 /// this target when scheduling the DAG.
142 virtual HazardRecognizer *CreateTargetHazardRecognizer() {
143 // Should use subtarget info to pick the right hazard recognizer. For
144 // now, always return a PPC970 recognizer.
145 const TargetInstrInfo *II = PPCLowering.getTargetMachine().getInstrInfo();
146 assert(II && "No InstrInfo?");
147 return new PPCHazardRecognizer970(*II);
150 // Include the pieces autogenerated from the target description.
151 #include "PPCGenDAGISel.inc"
154 SDOperand SelectSETCC(SDOperand Op);
155 SDOperand SelectCALL(SDOperand Op);
159 /// InstructionSelectBasicBlock - This callback is invoked by
160 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
161 void PPCDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
164 // The selection process is inherently a bottom-up recursive process (users
165 // select their uses before themselves). Given infinite stack space, we
166 // could just start selecting on the root and traverse the whole graph. In
167 // practice however, this causes us to run out of stack space on large basic
168 // blocks. To avoid this problem, select the entry node, then all its uses,
169 // iteratively instead of recursively.
170 std::vector<SDOperand> Worklist;
171 Worklist.push_back(DAG.getEntryNode());
173 // Note that we can do this in the PPC target (scanning forward across token
174 // chain edges) because no nodes ever get folded across these edges. On a
175 // target like X86 which supports load/modify/store operations, this would
176 // have to be more careful.
177 while (!Worklist.empty()) {
178 SDOperand Node = Worklist.back();
181 // Chose from the least deep of the top two nodes.
182 if (!Worklist.empty() &&
183 Worklist.back().Val->getNodeDepth() < Node.Val->getNodeDepth())
184 std::swap(Worklist.back(), Node);
186 if ((Node.Val->getOpcode() >= ISD::BUILTIN_OP_END &&
187 Node.Val->getOpcode() < PPCISD::FIRST_NUMBER) ||
188 CodeGenMap.count(Node)) continue;
190 for (SDNode::use_iterator UI = Node.Val->use_begin(),
191 E = Node.Val->use_end(); UI != E; ++UI) {
192 // Scan the values. If this use has a value that is a token chain, add it
195 for (unsigned i = 0, e = User->getNumValues(); i != e; ++i)
196 if (User->getValueType(i) == MVT::Other) {
197 Worklist.push_back(SDOperand(User, i));
202 // Finally, legalize this node.
207 // Select target instructions for the DAG.
208 DAG.setRoot(SelectRoot(DAG.getRoot()));
210 DAG.RemoveDeadNodes();
212 // Emit machine code to BB.
213 ScheduleAndEmitDAG(DAG);
216 /// InsertVRSaveCode - Once the entire function has been instruction selected,
217 /// all virtual registers are created and all machine instructions are built,
218 /// check to see if we need to save/restore VRSAVE. If so, do it.
219 void PPCDAGToDAGISel::InsertVRSaveCode(Function &F) {
220 // Check to see if this function uses vector registers, which means we have to
221 // save and restore the VRSAVE register and update it with the regs we use.
223 // In this case, there will be virtual registers of vector type type created
224 // by the scheduler. Detect them now.
225 MachineFunction &Fn = MachineFunction::get(&F);
226 SSARegMap *RegMap = Fn.getSSARegMap();
227 bool HasVectorVReg = false;
228 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
229 e = RegMap->getLastVirtReg()+1; i != e; ++i)
230 if (RegMap->getRegClass(i) == &PPC::VRRCRegClass) {
231 HasVectorVReg = true;
234 if (!HasVectorVReg) return; // nothing to do.
236 // If we have a vector register, we want to emit code into the entry and exit
237 // blocks to save and restore the VRSAVE register. We do this here (instead
238 // of marking all vector instructions as clobbering VRSAVE) for two reasons:
240 // 1. This (trivially) reduces the load on the register allocator, by not
241 // having to represent the live range of the VRSAVE register.
242 // 2. This (more significantly) allows us to create a temporary virtual
243 // register to hold the saved VRSAVE value, allowing this temporary to be
244 // register allocated, instead of forcing it to be spilled to the stack.
246 // Create two vregs - one to hold the VRSAVE register that is live-in to the
247 // function and one for the value after having bits or'd into it.
248 unsigned InVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
249 unsigned UpdatedVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
251 MachineBasicBlock &EntryBB = *Fn.begin();
252 // Emit the following code into the entry block:
253 // InVRSAVE = MFVRSAVE
254 // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
255 // MTVRSAVE UpdatedVRSAVE
256 MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
257 BuildMI(EntryBB, IP, PPC::MFVRSAVE, 0, InVRSAVE);
258 BuildMI(EntryBB, IP, PPC::UPDATE_VRSAVE, 1, UpdatedVRSAVE).addReg(InVRSAVE);
259 BuildMI(EntryBB, IP, PPC::MTVRSAVE, 1).addReg(UpdatedVRSAVE);
261 // Find all return blocks, outputting a restore in each epilog.
262 const TargetInstrInfo &TII = *TM.getInstrInfo();
263 for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
264 if (!BB->empty() && TII.isReturn(BB->back().getOpcode())) {
265 IP = BB->end(); --IP;
267 // Skip over all terminator instructions, which are part of the return
269 MachineBasicBlock::iterator I2 = IP;
270 while (I2 != BB->begin() && TII.isTerminatorInstr((--I2)->getOpcode()))
273 // Emit: MTVRSAVE InVRSave
274 BuildMI(*BB, IP, PPC::MTVRSAVE, 1).addReg(InVRSAVE);
280 /// getGlobalBaseReg - Output the instructions required to put the
281 /// base address to use for accessing globals into a register.
283 SDOperand PPCDAGToDAGISel::getGlobalBaseReg() {
284 if (!GlobalBaseReg) {
285 // Insert the set of GlobalBaseReg into the first MBB of the function
286 MachineBasicBlock &FirstMBB = BB->getParent()->front();
287 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
288 SSARegMap *RegMap = BB->getParent()->getSSARegMap();
289 // FIXME: when we get to LP64, we will need to create the appropriate
290 // type of register here.
291 GlobalBaseReg = RegMap->createVirtualRegister(PPC::GPRCRegisterClass);
292 BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
293 BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg);
295 return CurDAG->getRegister(GlobalBaseReg, MVT::i32);
299 // isIntImmediate - This method tests to see if a constant operand.
300 // If so Imm will receive the 32 bit value.
301 static bool isIntImmediate(SDNode *N, unsigned& Imm) {
302 if (N->getOpcode() == ISD::Constant) {
303 Imm = cast<ConstantSDNode>(N)->getValue();
309 // isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s with
310 // any number of 0s on either side. The 1s are allowed to wrap from LSB to
311 // MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 0x0F0F0000 is
312 // not, since all 1s are not contiguous.
313 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
314 if (isShiftedMask_32(Val)) {
315 // look for the first non-zero bit
316 MB = CountLeadingZeros_32(Val);
317 // look for the first zero bit after the run of ones
318 ME = CountLeadingZeros_32((Val - 1) ^ Val);
321 Val = ~Val; // invert mask
322 if (isShiftedMask_32(Val)) {
323 // effectively look for the first zero bit
324 ME = CountLeadingZeros_32(Val) - 1;
325 // effectively look for the first one bit after the run of zeros
326 MB = CountLeadingZeros_32((Val - 1) ^ Val) + 1;
334 // isRotateAndMask - Returns true if Mask and Shift can be folded into a rotate
335 // and mask opcode and mask operation.
336 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask,
337 unsigned &SH, unsigned &MB, unsigned &ME) {
338 // Don't even go down this path for i64, since different logic will be
339 // necessary for rldicl/rldicr/rldimi.
340 if (N->getValueType(0) != MVT::i32)
344 unsigned Indeterminant = ~0; // bit mask marking indeterminant results
345 unsigned Opcode = N->getOpcode();
346 if (N->getNumOperands() != 2 ||
347 !isIntImmediate(N->getOperand(1).Val, Shift) || (Shift > 31))
350 if (Opcode == ISD::SHL) {
351 // apply shift left to mask if it comes first
352 if (IsShiftMask) Mask = Mask << Shift;
353 // determine which bits are made indeterminant by shift
354 Indeterminant = ~(0xFFFFFFFFu << Shift);
355 } else if (Opcode == ISD::SRL) {
356 // apply shift right to mask if it comes first
357 if (IsShiftMask) Mask = Mask >> Shift;
358 // determine which bits are made indeterminant by shift
359 Indeterminant = ~(0xFFFFFFFFu >> Shift);
360 // adjust for the left rotate
366 // if the mask doesn't intersect any Indeterminant bits
367 if (Mask && !(Mask & Indeterminant)) {
369 // make sure the mask is still a mask (wrap arounds may not be)
370 return isRunOfOnes(Mask, MB, ME);
375 // isOpcWithIntImmediate - This method tests to see if the node is a specific
376 // opcode and that it has a immediate integer right operand.
377 // If so Imm will receive the 32 bit value.
378 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
379 return N->getOpcode() == Opc && isIntImmediate(N->getOperand(1).Val, Imm);
382 // isIntImmediate - This method tests to see if a constant operand.
383 // If so Imm will receive the 32 bit value.
384 static bool isIntImmediate(SDOperand N, unsigned& Imm) {
385 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
386 Imm = (unsigned)CN->getSignExtended();
392 /// SelectBitfieldInsert - turn an or of two masked values into
393 /// the rotate left word immediate then mask insert (rlwimi) instruction.
394 SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
395 SDOperand Op0 = N->getOperand(0);
396 SDOperand Op1 = N->getOperand(1);
398 uint64_t LKZ, LKO, RKZ, RKO;
399 TLI.ComputeMaskedBits(Op0, 0xFFFFFFFFULL, LKZ, LKO);
400 TLI.ComputeMaskedBits(Op1, 0xFFFFFFFFULL, RKZ, RKO);
402 unsigned TargetMask = LKZ;
403 unsigned InsertMask = RKZ;
405 if ((TargetMask | InsertMask) == 0xFFFFFFFF) {
406 unsigned Op0Opc = Op0.getOpcode();
407 unsigned Op1Opc = Op1.getOpcode();
408 unsigned Value, SH = 0;
409 TargetMask = ~TargetMask;
410 InsertMask = ~InsertMask;
412 // If the LHS has a foldable shift and the RHS does not, then swap it to the
413 // RHS so that we can fold the shift into the insert.
414 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
415 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
416 Op0.getOperand(0).getOpcode() == ISD::SRL) {
417 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
418 Op1.getOperand(0).getOpcode() != ISD::SRL) {
420 std::swap(Op0Opc, Op1Opc);
421 std::swap(TargetMask, InsertMask);
424 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
425 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
426 Op1.getOperand(0).getOpcode() != ISD::SRL) {
428 std::swap(Op0Opc, Op1Opc);
429 std::swap(TargetMask, InsertMask);
434 if (InsertMask && isRunOfOnes(InsertMask, MB, ME)) {
435 SDOperand Tmp1, Tmp2, Tmp3;
436 bool DisjointMask = (TargetMask ^ InsertMask) == 0xFFFFFFFF;
438 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
439 isIntImmediate(Op1.getOperand(1), Value)) {
440 Op1 = Op1.getOperand(0);
441 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value;
443 if (Op1Opc == ISD::AND) {
444 unsigned SHOpc = Op1.getOperand(0).getOpcode();
445 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) &&
446 isIntImmediate(Op1.getOperand(0).getOperand(1), Value)) {
447 Op1 = Op1.getOperand(0).getOperand(0);
448 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value;
450 Op1 = Op1.getOperand(0);
454 Tmp3 = (Op0Opc == ISD::AND && DisjointMask) ? Op0.getOperand(0) : Op0;
458 return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Tmp1, Tmp2,
459 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
465 /// SelectAddrImm - Returns true if the address N can be represented by
466 /// a base register plus a signed 16-bit displacement [r+imm].
467 bool PPCDAGToDAGISel::SelectAddrImm(SDOperand N, SDOperand &Disp,
469 // If this can be more profitably realized as r+r, fail.
470 if (SelectAddrIdx(N, Disp, Base))
473 if (N.getOpcode() == ISD::ADD) {
475 if (isIntImmediate(N.getOperand(1), imm) && isInt16(imm)) {
476 Disp = getI32Imm(imm & 0xFFFF);
477 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
478 Base = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
480 Base = N.getOperand(0);
482 return true; // [r+i]
483 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
484 // Match LOAD (ADD (X, Lo(G))).
485 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
486 && "Cannot handle constant offsets yet!");
487 Disp = N.getOperand(1).getOperand(0); // The global address.
488 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
489 Disp.getOpcode() == ISD::TargetConstantPool ||
490 Disp.getOpcode() == ISD::TargetJumpTable);
491 Base = N.getOperand(0);
492 return true; // [&g+r]
494 } else if (N.getOpcode() == ISD::OR) {
496 if (isIntImmediate(N.getOperand(1), imm) && isInt16(imm)) {
497 // If this is an or of disjoint bitfields, we can codegen this as an add
498 // (for better address arithmetic) if the LHS and RHS of the OR are
499 // provably disjoint.
500 uint64_t LHSKnownZero, LHSKnownOne;
501 PPCLowering.ComputeMaskedBits(N.getOperand(0), ~0U,
502 LHSKnownZero, LHSKnownOne);
503 if ((LHSKnownZero|~imm) == ~0U) {
504 // If all of the bits are known zero on the LHS or RHS, the add won't
506 Base = N.getOperand(0);
507 Disp = getI32Imm(imm & 0xFFFF);
511 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
512 // Loading from a constant address.
513 int Addr = (int)CN->getValue();
515 // If this address fits entirely in a 16-bit sext immediate field, codegen
517 if (Addr == (short)Addr) {
518 Disp = getI32Imm(Addr);
519 Base = CurDAG->getRegister(PPC::R0, MVT::i32);
523 // Otherwise, break this down into an LIS + disp.
524 Disp = getI32Imm((short)Addr);
525 Base = CurDAG->getConstant(Addr - (signed short)Addr, MVT::i32);
530 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
531 Base = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
534 return true; // [r+0]
537 /// SelectAddrIdx - Given the specified addressed, check to see if it can be
538 /// represented as an indexed [r+r] operation. Returns false if it can
539 /// be represented by [r+imm], which are preferred.
540 bool PPCDAGToDAGISel::SelectAddrIdx(SDOperand N, SDOperand &Base,
543 if (N.getOpcode() == ISD::ADD) {
544 if (isIntImmediate(N.getOperand(1), imm) && isInt16(imm))
546 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
549 Base = N.getOperand(0);
550 Index = N.getOperand(1);
552 } else if (N.getOpcode() == ISD::OR) {
553 if (isIntImmediate(N.getOperand(1), imm) && isInt16(imm))
554 return false; // r+i can fold it if we can.
556 // If this is an or of disjoint bitfields, we can codegen this as an add
557 // (for better address arithmetic) if the LHS and RHS of the OR are provably
559 uint64_t LHSKnownZero, LHSKnownOne;
560 uint64_t RHSKnownZero, RHSKnownOne;
561 PPCLowering.ComputeMaskedBits(N.getOperand(0), ~0U,
562 LHSKnownZero, LHSKnownOne);
565 PPCLowering.ComputeMaskedBits(N.getOperand(1), ~0U,
566 RHSKnownZero, RHSKnownOne);
567 // If all of the bits are known zero on the LHS or RHS, the add won't
569 if ((LHSKnownZero | RHSKnownZero) == ~0U) {
570 Base = N.getOperand(0);
571 Index = N.getOperand(1);
580 /// SelectAddrIdxOnly - Given the specified addressed, force it to be
581 /// represented as an indexed [r+r] operation.
582 bool PPCDAGToDAGISel::SelectAddrIdxOnly(SDOperand N, SDOperand &Base,
584 // Check to see if we can easily represent this as an [r+r] address. This
585 // will fail if it thinks that the address is more profitably represented as
586 // reg+imm, e.g. where imm = 0.
587 if (SelectAddrIdx(N, Base, Index))
590 // If the operand is an addition, always emit this as [r+r], since this is
591 // better (for code size, and execution, as the memop does the add for free)
592 // than emitting an explicit add.
593 if (N.getOpcode() == ISD::ADD) {
594 Base = N.getOperand(0);
595 Index = N.getOperand(1);
599 // Otherwise, do it the hard way, using R0 as the base register.
600 Base = CurDAG->getRegister(PPC::R0, MVT::i32);
605 /// SelectAddrImmShift - Returns true if the address N can be represented by
606 /// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable
607 /// for use by STD and friends.
608 bool PPCDAGToDAGISel::SelectAddrImmShift(SDOperand N, SDOperand &Disp,
610 // If this can be more profitably realized as r+r, fail.
611 if (SelectAddrIdx(N, Disp, Base))
614 if (N.getOpcode() == ISD::ADD) {
616 if (isIntImmediate(N.getOperand(1), imm) && isInt16(imm) &&
618 Disp = getI32Imm((imm & 0xFFFF) >> 2);
619 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
620 Base = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
622 Base = N.getOperand(0);
624 return true; // [r+i]
625 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
626 // Match LOAD (ADD (X, Lo(G))).
627 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
628 && "Cannot handle constant offsets yet!");
629 Disp = N.getOperand(1).getOperand(0); // The global address.
630 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
631 Disp.getOpcode() == ISD::TargetConstantPool ||
632 Disp.getOpcode() == ISD::TargetJumpTable);
633 Base = N.getOperand(0);
634 return true; // [&g+r]
636 } else if (N.getOpcode() == ISD::OR) {
638 if (isIntImmediate(N.getOperand(1), imm) && isInt16(imm) &&
640 // If this is an or of disjoint bitfields, we can codegen this as an add
641 // (for better address arithmetic) if the LHS and RHS of the OR are
642 // provably disjoint.
643 uint64_t LHSKnownZero, LHSKnownOne;
644 PPCLowering.ComputeMaskedBits(N.getOperand(0), ~0U,
645 LHSKnownZero, LHSKnownOne);
646 if ((LHSKnownZero|~imm) == ~0U) {
647 // If all of the bits are known zero on the LHS or RHS, the add won't
649 Base = N.getOperand(0);
650 Disp = getI32Imm((imm & 0xFFFF) >> 2);
654 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
655 // Loading from a constant address.
656 int Addr = (int)CN->getValue();
657 if ((Addr & 3) == 0) {
658 // If this address fits entirely in a 16-bit sext immediate field, codegen
660 if (Addr == (short)Addr) {
661 Disp = getI32Imm(Addr >> 2);
662 Base = CurDAG->getRegister(PPC::R0, MVT::i32);
666 // Otherwise, break this down into an LIS + disp.
667 Disp = getI32Imm((short)Addr >> 2);
668 Base = CurDAG->getConstant(Addr - (signed short)Addr, MVT::i32);
674 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
675 Base = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
678 return true; // [r+0]
682 /// SelectCC - Select a comparison of the specified values with the specified
683 /// condition code, returning the CR# of the expression.
684 SDOperand PPCDAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS,
686 // Always select the LHS.
689 // Use U to determine whether the SETCC immediate range is signed or not.
690 if (MVT::isInteger(LHS.getValueType())) {
691 bool U = ISD::isUnsignedIntSetCC(CC);
693 if (isIntImmediate(RHS, Imm) &&
694 ((U && isUInt16(Imm)) || (!U && isInt16(Imm))))
695 return SDOperand(CurDAG->getTargetNode(U ? PPC::CMPLWI : PPC::CMPWI,
696 MVT::i32, LHS, getI32Imm(Imm & 0xFFFF)), 0);
698 return SDOperand(CurDAG->getTargetNode(U ? PPC::CMPLW : PPC::CMPW, MVT::i32,
700 } else if (LHS.getValueType() == MVT::f32) {
702 return SDOperand(CurDAG->getTargetNode(PPC::FCMPUS, MVT::i32, LHS, RHS), 0);
705 return SDOperand(CurDAG->getTargetNode(PPC::FCMPUD, MVT::i32, LHS, RHS), 0);
709 /// getBCCForSetCC - Returns the PowerPC condition branch mnemonic corresponding
711 static unsigned getBCCForSetCC(ISD::CondCode CC) {
713 default: assert(0 && "Unknown condition!"); abort();
714 case ISD::SETOEQ: // FIXME: This is incorrect see PR642.
715 case ISD::SETEQ: return PPC::BEQ;
716 case ISD::SETONE: // FIXME: This is incorrect see PR642.
717 case ISD::SETNE: return PPC::BNE;
718 case ISD::SETOLT: // FIXME: This is incorrect see PR642.
720 case ISD::SETLT: return PPC::BLT;
721 case ISD::SETOLE: // FIXME: This is incorrect see PR642.
723 case ISD::SETLE: return PPC::BLE;
724 case ISD::SETOGT: // FIXME: This is incorrect see PR642.
726 case ISD::SETGT: return PPC::BGT;
727 case ISD::SETOGE: // FIXME: This is incorrect see PR642.
729 case ISD::SETGE: return PPC::BGE;
731 case ISD::SETO: return PPC::BUN;
732 case ISD::SETUO: return PPC::BNU;
737 /// getCRIdxForSetCC - Return the index of the condition register field
738 /// associated with the SetCC condition, and whether or not the field is
739 /// treated as inverted. That is, lt = 0; ge = 0 inverted.
740 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool& Inv) {
742 default: assert(0 && "Unknown condition!"); abort();
743 case ISD::SETOLT: // FIXME: This is incorrect see PR642.
745 case ISD::SETLT: Inv = false; return 0;
746 case ISD::SETOGE: // FIXME: This is incorrect see PR642.
748 case ISD::SETGE: Inv = true; return 0;
749 case ISD::SETOGT: // FIXME: This is incorrect see PR642.
751 case ISD::SETGT: Inv = false; return 1;
752 case ISD::SETOLE: // FIXME: This is incorrect see PR642.
754 case ISD::SETLE: Inv = true; return 1;
755 case ISD::SETOEQ: // FIXME: This is incorrect see PR642.
756 case ISD::SETEQ: Inv = false; return 2;
757 case ISD::SETONE: // FIXME: This is incorrect see PR642.
758 case ISD::SETNE: Inv = true; return 2;
759 case ISD::SETO: Inv = true; return 3;
760 case ISD::SETUO: Inv = false; return 3;
765 SDOperand PPCDAGToDAGISel::SelectSETCC(SDOperand Op) {
768 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
769 if (isIntImmediate(N->getOperand(1), Imm)) {
770 // We can codegen setcc op, imm very efficiently compared to a brcond.
771 // Check for those cases here.
775 Select(Op, N->getOperand(0));
779 Op = SDOperand(CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op), 0);
780 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(27),
781 getI32Imm(5), getI32Imm(31));
784 SDOperand(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
785 Op, getI32Imm(~0U)), 0);
786 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
790 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(1),
791 getI32Imm(31), getI32Imm(31));
794 SDOperand(CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op), 0);
795 T = SDOperand(CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op), 0);
796 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, T, getI32Imm(1),
797 getI32Imm(31), getI32Imm(31));
800 } else if (Imm == ~0U) { // setcc op, -1
802 Select(Op, N->getOperand(0));
806 Op = SDOperand(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
807 Op, getI32Imm(1)), 0);
808 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
809 SDOperand(CurDAG->getTargetNode(PPC::LI, MVT::i32,
813 Op = SDOperand(CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op), 0);
814 SDNode *AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
816 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDOperand(AD, 0),
817 Op, SDOperand(AD, 1));
820 SDOperand AD = SDOperand(CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op,
822 SDOperand AN = SDOperand(CurDAG->getTargetNode(PPC::AND, MVT::i32, AD,
824 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, AN, getI32Imm(1),
825 getI32Imm(31), getI32Imm(31));
828 Op = SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Op,
829 getI32Imm(1), getI32Imm(31),
831 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, getI32Imm(1));
837 unsigned Idx = getCRIdxForSetCC(CC, Inv);
838 SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
841 // Force the ccreg into CR7.
842 SDOperand CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
844 SDOperand InFlag(0, 0); // Null incoming flag value.
845 CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), CR7Reg, CCReg,
848 if (TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor())
849 IntCR = SDOperand(CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg,
852 IntCR = SDOperand(CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg), 0);
855 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, IntCR,
856 getI32Imm((32-(3-Idx)) & 31),
857 getI32Imm(31), getI32Imm(31));
860 SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, IntCR,
861 getI32Imm((32-(3-Idx)) & 31),
862 getI32Imm(31),getI32Imm(31)), 0);
863 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
867 /// isCallCompatibleAddress - Return true if the specified 32-bit value is
868 /// representable in the immediate field of a Bx instruction.
869 static bool isCallCompatibleAddress(ConstantSDNode *C) {
870 int Addr = C->getValue();
871 if (Addr & 3) return false; // Low 2 bits are implicitly zero.
872 return (Addr << 6 >> 6) == Addr; // Top 6 bits have to be sext of immediate.
875 SDOperand PPCDAGToDAGISel::SelectCALL(SDOperand Op) {
877 SDOperand Chain, Flag;
878 Select(Chain, N->getOperand(0));
879 if (N->getNumOperands() == 3) // input flag
880 Select(Flag, N->getOperand(2));
884 std::vector<SDOperand> CallArgs;
885 if (GlobalAddressSDNode *GASD =
886 dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) {
887 CallOpcode = PPC::BL;
888 CallArgs.push_back(N->getOperand(1));
889 } else if (ExternalSymbolSDNode *ESSDN =
890 dyn_cast<ExternalSymbolSDNode>(N->getOperand(1))) {
891 CallOpcode = PPC::BL;
892 CallArgs.push_back(N->getOperand(1));
893 } else if (isa<ConstantSDNode>(N->getOperand(1)) &&
894 isCallCompatibleAddress(cast<ConstantSDNode>(N->getOperand(1)))) {
895 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(1));
896 CallOpcode = PPC::BLA;
897 CallArgs.push_back(getI32Imm((int)C->getValue() >> 2));
899 // Copy the callee address into the CTR register.
901 Select(Callee, N->getOperand(1));
903 Chain = SDOperand(CurDAG->getTargetNode(PPC::MTCTR, MVT::Other, MVT::Flag,
904 Callee, Chain, Flag), 0);
906 Chain = SDOperand(CurDAG->getTargetNode(PPC::MTCTR, MVT::Other, MVT::Flag,
908 Flag = Chain.getValue(1);
910 // Copy the callee address into R12 on darwin.
911 Chain = CurDAG->getCopyToReg(Chain, PPC::R12, Callee, Flag);
912 Flag = Chain.getValue(1);
914 CallOpcode = PPC::BCTRL;
917 // Emit the call itself.
918 CallArgs.push_back(Chain);
920 CallArgs.push_back(Flag);
921 Chain = SDOperand(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
923 CodeGenMap[Op.getValue(0)] = Chain;
924 CodeGenMap[Op.getValue(1)] = Chain.getValue(1);
925 return Chain.getValue(Op.ResNo);
928 // Select - Convert the specified operand from a target-independent to a
929 // target-specific node if it hasn't already been changed.
930 void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
932 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
933 N->getOpcode() < PPCISD::FIRST_NUMBER) {
935 return; // Already selected.
938 // If this has already been converted, use it.
939 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
940 if (CGMI != CodeGenMap.end()) {
941 Result = CGMI->second;
945 switch (N->getOpcode()) {
948 Result = SelectSETCC(Op);
951 Result = SelectCALL(Op);
953 case PPCISD::GlobalBaseReg:
954 Result = getGlobalBaseReg();
957 case ISD::FrameIndex: {
958 int FI = cast<FrameIndexSDNode>(N)->getIndex();
959 if (N->hasOneUse()) {
960 Result = CurDAG->SelectNodeTo(N, PPC::ADDI, MVT::i32,
961 CurDAG->getTargetFrameIndex(FI, MVT::i32),
965 Result = CodeGenMap[Op] =
966 SDOperand(CurDAG->getTargetNode(PPC::ADDI, MVT::i32,
967 CurDAG->getTargetFrameIndex(FI, MVT::i32),
974 Select(InFlag, N->getOperand(1));
975 // Use MFOCRF if supported.
976 if (TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor())
977 Result = SDOperand(CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32,
978 N->getOperand(0), InFlag), 0);
980 Result = SDOperand(CurDAG->getTargetNode(PPC::MFCR, MVT::i32, InFlag), 0);
981 CodeGenMap[Op] = Result;
986 // FIXME: since this depends on the setting of the carry flag from the srawi
987 // we should really be making notes about that for the scheduler.
988 // FIXME: It sure would be nice if we could cheaply recognize the
989 // srl/add/sra pattern the dag combiner will generate for this as
990 // sra/addze rather than having to handle sdiv ourselves. oh well.
992 if (isIntImmediate(N->getOperand(1), Imm)) {
994 Select(N0, N->getOperand(0));
995 if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
997 CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
998 N0, getI32Imm(Log2_32(Imm)));
999 Result = CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
1000 SDOperand(Op, 0), SDOperand(Op, 1));
1001 } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
1003 CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
1004 N0, getI32Imm(Log2_32(-Imm)));
1006 SDOperand(CurDAG->getTargetNode(PPC::ADDZE, MVT::i32,
1007 SDOperand(Op, 0), SDOperand(Op, 1)),
1009 Result = CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
1014 // Other cases are autogenerated.
1019 // If this is an and of a value rotated between 0 and 31 bits and then and'd
1020 // with a mask, emit rlwinm
1021 if (isIntImmediate(N->getOperand(1), Imm) && (isShiftedMask_32(Imm) ||
1022 isShiftedMask_32(~Imm))) {
1024 unsigned SH, MB, ME;
1025 if (isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB, ME)) {
1026 Select(Val, N->getOperand(0).getOperand(0));
1027 } else if (Imm == 0) {
1028 // AND X, 0 -> 0, not "rlwinm 32".
1029 Select(Result, N->getOperand(1));
1032 Select(Val, N->getOperand(0));
1033 isRunOfOnes(Imm, MB, ME);
1036 Result = CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Val,
1037 getI32Imm(SH), getI32Imm(MB),
1041 // ISD::OR doesn't get all the bitfield insertion fun.
1042 // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert
1043 if (isIntImmediate(N->getOperand(1), Imm) &&
1044 N->getOperand(0).getOpcode() == ISD::OR &&
1045 isIntImmediate(N->getOperand(0).getOperand(1), Imm2)) {
1048 if (isRunOfOnes(Imm, MB, ME)) {
1049 SDOperand Tmp1, Tmp2;
1050 Select(Tmp1, N->getOperand(0).getOperand(0));
1051 Select(Tmp2, N->getOperand(0).getOperand(1));
1052 Result = SDOperand(CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32,
1054 getI32Imm(0), getI32Imm(MB),
1060 // Other cases are autogenerated.
1064 if (SDNode *I = SelectBitfieldInsert(N)) {
1065 Result = CodeGenMap[Op] = SDOperand(I, 0);
1069 // Other cases are autogenerated.
1072 unsigned Imm, SH, MB, ME;
1073 if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
1074 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
1076 Select(Val, N->getOperand(0).getOperand(0));
1077 Result = CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32,
1078 Val, getI32Imm(SH), getI32Imm(MB),
1083 // Other cases are autogenerated.
1087 unsigned Imm, SH, MB, ME;
1088 if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
1089 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
1091 Select(Val, N->getOperand(0).getOperand(0));
1092 Result = CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32,
1093 Val, getI32Imm(SH), getI32Imm(MB),
1098 // Other cases are autogenerated.
1101 case ISD::SELECT_CC: {
1102 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1104 // handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
1105 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1106 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
1107 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
1108 if (N1C->isNullValue() && N3C->isNullValue() &&
1109 N2C->getValue() == 1ULL && CC == ISD::SETNE) {
1111 Select(LHS, N->getOperand(0));
1113 CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
1114 LHS, getI32Imm(~0U));
1115 Result = CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
1116 SDOperand(Tmp, 0), LHS,
1121 SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
1122 unsigned BROpc = getBCCForSetCC(CC);
1124 bool isFP = MVT::isFloatingPoint(N->getValueType(0));
1125 unsigned SelectCCOp;
1126 if (MVT::isInteger(N->getValueType(0)))
1127 SelectCCOp = PPC::SELECT_CC_Int;
1128 else if (N->getValueType(0) == MVT::f32)
1129 SelectCCOp = PPC::SELECT_CC_F4;
1130 else if (N->getValueType(0) == MVT::f64)
1131 SelectCCOp = PPC::SELECT_CC_F8;
1133 SelectCCOp = PPC::SELECT_CC_VRRC;
1136 Select(N2, N->getOperand(2));
1137 Select(N3, N->getOperand(3));
1138 Result = CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), CCReg,
1139 N2, N3, getI32Imm(BROpc));
1144 Select(Chain, N->getOperand(0));
1145 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
1146 SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC);
1147 Result = CurDAG->SelectNodeTo(N, PPC::COND_BRANCH, MVT::Other,
1148 CondCode, getI32Imm(getBCCForSetCC(CC)),
1149 N->getOperand(4), Chain);
1153 SDOperand Chain, Target;
1154 Select(Chain, N->getOperand(0));
1155 Select(Target,N->getOperand(1));
1156 Chain = SDOperand(CurDAG->getTargetNode(PPC::MTCTR, MVT::Other, Target,
1158 Result = CurDAG->SelectNodeTo(N, PPC::BCTR, MVT::Other, Chain);
1163 SelectCode(Result, Op);
1167 /// createPPCISelDag - This pass converts a legalized DAG into a
1168 /// PowerPC-specific DAG, ready for instruction scheduling.
1170 FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) {
1171 return new PPCDAGToDAGISel(TM);