1 //===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for PowerPC,
11 // converting from a legalized dag to a PPC dag.
13 //===----------------------------------------------------------------------===//
16 #include "MCTargetDesc/PPCPredicates.h"
17 #include "PPCTargetMachine.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/SelectionDAGISel.h"
23 #include "llvm/IR/Constants.h"
24 #include "llvm/IR/Function.h"
25 #include "llvm/IR/GlobalAlias.h"
26 #include "llvm/IR/GlobalValue.h"
27 #include "llvm/IR/GlobalVariable.h"
28 #include "llvm/IR/Intrinsics.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetOptions.h"
37 #define DEBUG_TYPE "ppc-codegen"
39 // FIXME: Remove this once the bug has been fixed!
40 cl::opt<bool> ANDIGlueBug("expose-ppc-andi-glue-bug",
41 cl::desc("expose the ANDI glue bug on PPC"), cl::Hidden);
44 void initializePPCDAGToDAGISelPass(PassRegistry&);
48 //===--------------------------------------------------------------------===//
49 /// PPCDAGToDAGISel - PPC specific code to select PPC machine
50 /// instructions for SelectionDAG operations.
52 class PPCDAGToDAGISel : public SelectionDAGISel {
53 const PPCTargetMachine &TM;
54 const PPCTargetLowering &PPCLowering;
55 const PPCSubtarget &PPCSubTarget;
56 unsigned GlobalBaseReg;
58 explicit PPCDAGToDAGISel(PPCTargetMachine &tm)
59 : SelectionDAGISel(tm), TM(tm),
60 PPCLowering(*TM.getTargetLowering()),
61 PPCSubTarget(*TM.getSubtargetImpl()) {
62 initializePPCDAGToDAGISelPass(*PassRegistry::getPassRegistry());
65 bool runOnMachineFunction(MachineFunction &MF) override {
66 // Make sure we re-emit a set of the global base reg if necessary
68 SelectionDAGISel::runOnMachineFunction(MF);
70 if (!PPCSubTarget.isSVR4ABI())
76 void PostprocessISelDAG() override;
78 /// getI32Imm - Return a target constant with the specified value, of type
80 inline SDValue getI32Imm(unsigned Imm) {
81 return CurDAG->getTargetConstant(Imm, MVT::i32);
84 /// getI64Imm - Return a target constant with the specified value, of type
86 inline SDValue getI64Imm(uint64_t Imm) {
87 return CurDAG->getTargetConstant(Imm, MVT::i64);
90 /// getSmallIPtrImm - Return a target constant of pointer type.
91 inline SDValue getSmallIPtrImm(unsigned Imm) {
92 return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy());
95 /// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s
96 /// with any number of 0s on either side. The 1s are allowed to wrap from
97 /// LSB to MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs.
98 /// 0x0F0F0000 is not, since all 1s are not contiguous.
99 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME);
102 /// isRotateAndMask - Returns true if Mask and Shift can be folded into a
103 /// rotate and mask opcode and mask operation.
104 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool isShiftMask,
105 unsigned &SH, unsigned &MB, unsigned &ME);
107 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
108 /// base register. Return the virtual register that holds this value.
109 SDNode *getGlobalBaseReg();
111 // Select - Convert the specified operand from a target-independent to a
112 // target-specific node if it hasn't already been changed.
113 SDNode *Select(SDNode *N) override;
115 SDNode *SelectBitfieldInsert(SDNode *N);
117 /// SelectCC - Select a comparison of the specified values with the
118 /// specified condition code, returning the CR# of the expression.
119 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDLoc dl);
121 /// SelectAddrImm - Returns true if the address N can be represented by
122 /// a base register plus a signed 16-bit displacement [r+imm].
123 bool SelectAddrImm(SDValue N, SDValue &Disp,
125 return PPCLowering.SelectAddressRegImm(N, Disp, Base, *CurDAG, false);
128 /// SelectAddrImmOffs - Return true if the operand is valid for a preinc
129 /// immediate field. Note that the operand at this point is already the
130 /// result of a prior SelectAddressRegImm call.
131 bool SelectAddrImmOffs(SDValue N, SDValue &Out) const {
132 if (N.getOpcode() == ISD::TargetConstant ||
133 N.getOpcode() == ISD::TargetGlobalAddress) {
141 /// SelectAddrIdx - Given the specified addressed, check to see if it can be
142 /// represented as an indexed [r+r] operation. Returns false if it can
143 /// be represented by [r+imm], which are preferred.
144 bool SelectAddrIdx(SDValue N, SDValue &Base, SDValue &Index) {
145 return PPCLowering.SelectAddressRegReg(N, Base, Index, *CurDAG);
148 /// SelectAddrIdxOnly - Given the specified addressed, force it to be
149 /// represented as an indexed [r+r] operation.
150 bool SelectAddrIdxOnly(SDValue N, SDValue &Base, SDValue &Index) {
151 return PPCLowering.SelectAddressRegRegOnly(N, Base, Index, *CurDAG);
154 /// SelectAddrImmX4 - Returns true if the address N can be represented by
155 /// a base register plus a signed 16-bit displacement that is a multiple of 4.
156 /// Suitable for use by STD and friends.
157 bool SelectAddrImmX4(SDValue N, SDValue &Disp, SDValue &Base) {
158 return PPCLowering.SelectAddressRegImm(N, Disp, Base, *CurDAG, true);
161 // Select an address into a single register.
162 bool SelectAddr(SDValue N, SDValue &Base) {
167 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
168 /// inline asm expressions. It is always correct to compute the value into
169 /// a register. The case of adding a (possibly relocatable) constant to a
170 /// register can be improved, but it is wrong to substitute Reg+Reg for
171 /// Reg in an asm, because the load or store opcode would have to change.
172 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
174 std::vector<SDValue> &OutOps) override {
175 OutOps.push_back(Op);
179 void InsertVRSaveCode(MachineFunction &MF);
181 const char *getPassName() const override {
182 return "PowerPC DAG->DAG Pattern Instruction Selection";
185 // Include the pieces autogenerated from the target description.
186 #include "PPCGenDAGISel.inc"
189 SDNode *SelectSETCC(SDNode *N);
191 void PeepholePPC64();
192 void PeepholeCROps();
194 bool AllUsersSelectZero(SDNode *N);
195 void SwapAllSelectUsers(SDNode *N);
199 /// InsertVRSaveCode - Once the entire function has been instruction selected,
200 /// all virtual registers are created and all machine instructions are built,
201 /// check to see if we need to save/restore VRSAVE. If so, do it.
202 void PPCDAGToDAGISel::InsertVRSaveCode(MachineFunction &Fn) {
203 // Check to see if this function uses vector registers, which means we have to
204 // save and restore the VRSAVE register and update it with the regs we use.
206 // In this case, there will be virtual registers of vector type created
207 // by the scheduler. Detect them now.
208 bool HasVectorVReg = false;
209 for (unsigned i = 0, e = RegInfo->getNumVirtRegs(); i != e; ++i) {
210 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
211 if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) {
212 HasVectorVReg = true;
216 if (!HasVectorVReg) return; // nothing to do.
218 // If we have a vector register, we want to emit code into the entry and exit
219 // blocks to save and restore the VRSAVE register. We do this here (instead
220 // of marking all vector instructions as clobbering VRSAVE) for two reasons:
222 // 1. This (trivially) reduces the load on the register allocator, by not
223 // having to represent the live range of the VRSAVE register.
224 // 2. This (more significantly) allows us to create a temporary virtual
225 // register to hold the saved VRSAVE value, allowing this temporary to be
226 // register allocated, instead of forcing it to be spilled to the stack.
228 // Create two vregs - one to hold the VRSAVE register that is live-in to the
229 // function and one for the value after having bits or'd into it.
230 unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
231 unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
233 const TargetInstrInfo &TII = *TM.getInstrInfo();
234 MachineBasicBlock &EntryBB = *Fn.begin();
236 // Emit the following code into the entry block:
237 // InVRSAVE = MFVRSAVE
238 // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
239 // MTVRSAVE UpdatedVRSAVE
240 MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
241 BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE);
242 BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE),
243 UpdatedVRSAVE).addReg(InVRSAVE);
244 BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
246 // Find all return blocks, outputting a restore in each epilog.
247 for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
248 if (!BB->empty() && BB->back().isReturn()) {
249 IP = BB->end(); --IP;
251 // Skip over all terminator instructions, which are part of the return
253 MachineBasicBlock::iterator I2 = IP;
254 while (I2 != BB->begin() && (--I2)->isTerminator())
257 // Emit: MTVRSAVE InVRSave
258 BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
264 /// getGlobalBaseReg - Output the instructions required to put the
265 /// base address to use for accessing globals into a register.
267 SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
268 if (!GlobalBaseReg) {
269 const TargetInstrInfo &TII = *TM.getInstrInfo();
270 // Insert the set of GlobalBaseReg into the first MBB of the function
271 MachineBasicBlock &FirstMBB = MF->front();
272 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
275 if (PPCLowering.getPointerTy() == MVT::i32) {
276 GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::GPRC_NOR0RegClass);
277 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));
278 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
280 GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::G8RC_NOX0RegClass);
281 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8));
282 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg);
285 return CurDAG->getRegister(GlobalBaseReg,
286 PPCLowering.getPointerTy()).getNode();
289 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
290 /// or 64-bit immediate, and if the value can be accurately represented as a
291 /// sign extension from a 16-bit value. If so, this returns true and the
293 static bool isIntS16Immediate(SDNode *N, short &Imm) {
294 if (N->getOpcode() != ISD::Constant)
297 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
298 if (N->getValueType(0) == MVT::i32)
299 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
301 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
304 static bool isIntS16Immediate(SDValue Op, short &Imm) {
305 return isIntS16Immediate(Op.getNode(), Imm);
309 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
310 /// operand. If so Imm will receive the 32-bit value.
311 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
312 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
313 Imm = cast<ConstantSDNode>(N)->getZExtValue();
319 /// isInt64Immediate - This method tests to see if the node is a 64-bit constant
320 /// operand. If so Imm will receive the 64-bit value.
321 static bool isInt64Immediate(SDNode *N, uint64_t &Imm) {
322 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
323 Imm = cast<ConstantSDNode>(N)->getZExtValue();
329 // isInt32Immediate - This method tests to see if a constant operand.
330 // If so Imm will receive the 32 bit value.
331 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
332 return isInt32Immediate(N.getNode(), Imm);
336 // isOpcWithIntImmediate - This method tests to see if the node is a specific
337 // opcode and that it has a immediate integer right operand.
338 // If so Imm will receive the 32 bit value.
339 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
340 return N->getOpcode() == Opc
341 && isInt32Immediate(N->getOperand(1).getNode(), Imm);
344 bool PPCDAGToDAGISel::isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
348 if (isShiftedMask_32(Val)) {
349 // look for the first non-zero bit
350 MB = countLeadingZeros(Val);
351 // look for the first zero bit after the run of ones
352 ME = countLeadingZeros((Val - 1) ^ Val);
355 Val = ~Val; // invert mask
356 if (isShiftedMask_32(Val)) {
357 // effectively look for the first zero bit
358 ME = countLeadingZeros(Val) - 1;
359 // effectively look for the first one bit after the run of zeros
360 MB = countLeadingZeros((Val - 1) ^ Val) + 1;
368 bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask,
369 bool isShiftMask, unsigned &SH,
370 unsigned &MB, unsigned &ME) {
371 // Don't even go down this path for i64, since different logic will be
372 // necessary for rldicl/rldicr/rldimi.
373 if (N->getValueType(0) != MVT::i32)
377 unsigned Indeterminant = ~0; // bit mask marking indeterminant results
378 unsigned Opcode = N->getOpcode();
379 if (N->getNumOperands() != 2 ||
380 !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31))
383 if (Opcode == ISD::SHL) {
384 // apply shift left to mask if it comes first
385 if (isShiftMask) Mask = Mask << Shift;
386 // determine which bits are made indeterminant by shift
387 Indeterminant = ~(0xFFFFFFFFu << Shift);
388 } else if (Opcode == ISD::SRL) {
389 // apply shift right to mask if it comes first
390 if (isShiftMask) Mask = Mask >> Shift;
391 // determine which bits are made indeterminant by shift
392 Indeterminant = ~(0xFFFFFFFFu >> Shift);
393 // adjust for the left rotate
395 } else if (Opcode == ISD::ROTL) {
401 // if the mask doesn't intersect any Indeterminant bits
402 if (Mask && !(Mask & Indeterminant)) {
404 // make sure the mask is still a mask (wrap arounds may not be)
405 return isRunOfOnes(Mask, MB, ME);
410 /// SelectBitfieldInsert - turn an or of two masked values into
411 /// the rotate left word immediate then mask insert (rlwimi) instruction.
412 SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
413 SDValue Op0 = N->getOperand(0);
414 SDValue Op1 = N->getOperand(1);
417 APInt LKZ, LKO, RKZ, RKO;
418 CurDAG->computeKnownBits(Op0, LKZ, LKO);
419 CurDAG->computeKnownBits(Op1, RKZ, RKO);
421 unsigned TargetMask = LKZ.getZExtValue();
422 unsigned InsertMask = RKZ.getZExtValue();
424 if ((TargetMask | InsertMask) == 0xFFFFFFFF) {
425 unsigned Op0Opc = Op0.getOpcode();
426 unsigned Op1Opc = Op1.getOpcode();
427 unsigned Value, SH = 0;
428 TargetMask = ~TargetMask;
429 InsertMask = ~InsertMask;
431 // If the LHS has a foldable shift and the RHS does not, then swap it to the
432 // RHS so that we can fold the shift into the insert.
433 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
434 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
435 Op0.getOperand(0).getOpcode() == ISD::SRL) {
436 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
437 Op1.getOperand(0).getOpcode() != ISD::SRL) {
439 std::swap(Op0Opc, Op1Opc);
440 std::swap(TargetMask, InsertMask);
443 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
444 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
445 Op1.getOperand(0).getOpcode() != ISD::SRL) {
447 std::swap(Op0Opc, Op1Opc);
448 std::swap(TargetMask, InsertMask);
453 if (isRunOfOnes(InsertMask, MB, ME)) {
456 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
457 isInt32Immediate(Op1.getOperand(1), Value)) {
458 Op1 = Op1.getOperand(0);
459 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value;
461 if (Op1Opc == ISD::AND) {
462 // The AND mask might not be a constant, and we need to make sure that
463 // if we're going to fold the masking with the insert, all bits not
464 // know to be zero in the mask are known to be one.
466 CurDAG->computeKnownBits(Op1.getOperand(1), MKZ, MKO);
467 bool CanFoldMask = InsertMask == MKO.getZExtValue();
469 unsigned SHOpc = Op1.getOperand(0).getOpcode();
470 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && CanFoldMask &&
471 isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) {
472 // Note that Value must be in range here (less than 32) because
473 // otherwise there would not be any bits set in InsertMask.
474 Op1 = Op1.getOperand(0).getOperand(0);
475 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value;
480 SDValue Ops[] = { Op0, Op1, getI32Imm(SH), getI32Imm(MB),
482 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops);
488 /// SelectCC - Select a comparison of the specified values with the specified
489 /// condition code, returning the CR# of the expression.
490 SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS,
491 ISD::CondCode CC, SDLoc dl) {
492 // Always select the LHS.
495 if (LHS.getValueType() == MVT::i32) {
497 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
498 if (isInt32Immediate(RHS, Imm)) {
499 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
501 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
502 getI32Imm(Imm & 0xFFFF)), 0);
503 // If this is a 16-bit signed immediate, fold it.
504 if (isInt<16>((int)Imm))
505 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
506 getI32Imm(Imm & 0xFFFF)), 0);
508 // For non-equality comparisons, the default code would materialize the
509 // constant, then compare against it, like this:
513 // Since we are just comparing for equality, we can emit this instead:
514 // xoris r0,r3,0x1234
515 // cmplwi cr0,r0,0x5678
517 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS, dl, MVT::i32, LHS,
518 getI32Imm(Imm >> 16)), 0);
519 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, Xor,
520 getI32Imm(Imm & 0xFFFF)), 0);
523 } else if (ISD::isUnsignedIntSetCC(CC)) {
524 if (isInt32Immediate(RHS, Imm) && isUInt<16>(Imm))
525 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
526 getI32Imm(Imm & 0xFFFF)), 0);
530 if (isIntS16Immediate(RHS, SImm))
531 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
532 getI32Imm((int)SImm & 0xFFFF)),
536 } else if (LHS.getValueType() == MVT::i64) {
538 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
539 if (isInt64Immediate(RHS.getNode(), Imm)) {
540 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
542 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
543 getI32Imm(Imm & 0xFFFF)), 0);
544 // If this is a 16-bit signed immediate, fold it.
546 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
547 getI32Imm(Imm & 0xFFFF)), 0);
549 // For non-equality comparisons, the default code would materialize the
550 // constant, then compare against it, like this:
554 // Since we are just comparing for equality, we can emit this instead:
555 // xoris r0,r3,0x1234
556 // cmpldi cr0,r0,0x5678
558 if (isUInt<32>(Imm)) {
559 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS8, dl, MVT::i64, LHS,
560 getI64Imm(Imm >> 16)), 0);
561 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, Xor,
562 getI64Imm(Imm & 0xFFFF)), 0);
566 } else if (ISD::isUnsignedIntSetCC(CC)) {
567 if (isInt64Immediate(RHS.getNode(), Imm) && isUInt<16>(Imm))
568 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
569 getI64Imm(Imm & 0xFFFF)), 0);
573 if (isIntS16Immediate(RHS, SImm))
574 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
575 getI64Imm(SImm & 0xFFFF)),
579 } else if (LHS.getValueType() == MVT::f32) {
582 assert(LHS.getValueType() == MVT::f64 && "Unknown vt!");
583 Opc = PPCSubTarget.hasVSX() ? PPC::XSCMPUDP : PPC::FCMPUD;
585 return SDValue(CurDAG->getMachineNode(Opc, dl, MVT::i32, LHS, RHS), 0);
588 static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {
594 llvm_unreachable("Should be lowered by legalize!");
595 default: llvm_unreachable("Unknown condition!");
597 case ISD::SETEQ: return PPC::PRED_EQ;
599 case ISD::SETNE: return PPC::PRED_NE;
601 case ISD::SETLT: return PPC::PRED_LT;
603 case ISD::SETLE: return PPC::PRED_LE;
605 case ISD::SETGT: return PPC::PRED_GT;
607 case ISD::SETGE: return PPC::PRED_GE;
608 case ISD::SETO: return PPC::PRED_NU;
609 case ISD::SETUO: return PPC::PRED_UN;
610 // These two are invalid for floating point. Assume we have int.
611 case ISD::SETULT: return PPC::PRED_LT;
612 case ISD::SETUGT: return PPC::PRED_GT;
616 /// getCRIdxForSetCC - Return the index of the condition register field
617 /// associated with the SetCC condition, and whether or not the field is
618 /// treated as inverted. That is, lt = 0; ge = 0 inverted.
619 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert) {
622 default: llvm_unreachable("Unknown condition!");
624 case ISD::SETLT: return 0; // Bit #0 = SETOLT
626 case ISD::SETGT: return 1; // Bit #1 = SETOGT
628 case ISD::SETEQ: return 2; // Bit #2 = SETOEQ
629 case ISD::SETUO: return 3; // Bit #3 = SETUO
631 case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE
633 case ISD::SETLE: Invert = true; return 1; // !Bit #1 = SETULE
635 case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE
636 case ISD::SETO: Invert = true; return 3; // !Bit #3 = SETO
641 llvm_unreachable("Invalid branch code: should be expanded by legalize");
642 // These are invalid for floating point. Assume integer.
643 case ISD::SETULT: return 0;
644 case ISD::SETUGT: return 1;
648 // getVCmpInst: return the vector compare instruction for the specified
649 // vector type and condition code. Since this is for altivec specific code,
650 // only support the altivec types (v16i8, v8i16, v4i32, and v4f32).
651 static unsigned int getVCmpInst(MVT::SimpleValueType VecVT, ISD::CondCode CC,
658 if (VecVT == MVT::v16i8)
659 return PPC::VCMPEQUB;
660 else if (VecVT == MVT::v8i16)
661 return PPC::VCMPEQUH;
662 else if (VecVT == MVT::v4i32)
663 return PPC::VCMPEQUW;
664 // v4f32 != v4f32 could be translate to unordered not equal
665 else if (VecVT == MVT::v4f32)
666 return HasVSX ? PPC::XVCMPEQSP : PPC::VCMPEQFP;
667 else if (VecVT == MVT::v2f64)
668 return PPC::XVCMPEQDP;
674 if (VecVT == MVT::v16i8)
675 return PPC::VCMPGTSB;
676 else if (VecVT == MVT::v8i16)
677 return PPC::VCMPGTSH;
678 else if (VecVT == MVT::v4i32)
679 return PPC::VCMPGTSW;
680 else if (VecVT == MVT::v4f32)
681 return HasVSX ? PPC::XVCMPGTSP : PPC::VCMPGTFP;
682 else if (VecVT == MVT::v2f64)
683 return PPC::XVCMPGTDP;
689 if (VecVT == MVT::v16i8)
690 return PPC::VCMPGTUB;
691 else if (VecVT == MVT::v8i16)
692 return PPC::VCMPGTUH;
693 else if (VecVT == MVT::v4i32)
694 return PPC::VCMPGTUW;
697 if (VecVT == MVT::v4f32)
698 return HasVSX ? PPC::XVCMPEQSP : PPC::VCMPEQFP;
699 else if (VecVT == MVT::v2f64)
700 return PPC::XVCMPEQDP;
705 if (VecVT == MVT::v4f32)
706 return HasVSX ? PPC::XVCMPGTSP : PPC::VCMPGTFP;
707 else if (VecVT == MVT::v2f64)
708 return PPC::XVCMPGTDP;
711 if (VecVT == MVT::v4f32)
712 return HasVSX ? PPC::XVCMPGESP : PPC::VCMPGEFP;
713 else if (VecVT == MVT::v2f64)
714 return PPC::XVCMPGEDP;
719 llvm_unreachable("Invalid integer vector compare condition");
722 // getVCmpEQInst: return the equal compare instruction for the specified vector
723 // type. Since this is for altivec specific code, only support the altivec
724 // types (v16i8, v8i16, v4i32, and v4f32).
725 static unsigned int getVCmpEQInst(MVT::SimpleValueType VecVT, bool HasVSX) {
728 return PPC::VCMPEQUB;
730 return PPC::VCMPEQUH;
732 return PPC::VCMPEQUW;
734 return HasVSX ? PPC::XVCMPEQSP : PPC::VCMPEQFP;
736 return PPC::XVCMPEQDP;
738 llvm_unreachable("Invalid integer vector compare condition");
742 SDNode *PPCDAGToDAGISel::SelectSETCC(SDNode *N) {
745 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
746 EVT PtrVT = CurDAG->getTargetLoweringInfo().getPointerTy();
747 bool isPPC64 = (PtrVT == MVT::i64);
749 if (!PPCSubTarget.useCRBits() &&
750 isInt32Immediate(N->getOperand(1), Imm)) {
751 // We can codegen setcc op, imm very efficiently compared to a brcond.
752 // Check for those cases here.
755 SDValue Op = N->getOperand(0);
759 Op = SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Op), 0);
760 SDValue Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) };
761 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
766 SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
767 Op, getI32Imm(~0U)), 0);
768 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
772 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
773 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
777 SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Op), 0);
778 T = SDValue(CurDAG->getMachineNode(PPC::ANDC, dl, MVT::i32, T, Op), 0);
779 SDValue Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
780 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
783 } else if (Imm == ~0U) { // setcc op, -1
784 SDValue Op = N->getOperand(0);
789 Op = SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
790 Op, getI32Imm(1)), 0);
791 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
792 SDValue(CurDAG->getMachineNode(PPC::LI, dl,
798 Op = SDValue(CurDAG->getMachineNode(PPC::NOR, dl, MVT::i32, Op, Op), 0);
799 SDNode *AD = CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
801 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0),
805 SDValue AD = SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Op,
807 SDValue AN = SDValue(CurDAG->getMachineNode(PPC::AND, dl, MVT::i32, AD,
809 SDValue Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
810 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
813 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
814 Op = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops),
816 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op,
823 SDValue LHS = N->getOperand(0);
824 SDValue RHS = N->getOperand(1);
826 // Altivec Vector compare instructions do not set any CR register by default and
827 // vector compare operations return the same type as the operands.
828 if (LHS.getValueType().isVector()) {
829 EVT VecVT = LHS.getValueType();
830 MVT::SimpleValueType VT = VecVT.getSimpleVT().SimpleTy;
831 unsigned int VCmpInst = getVCmpInst(VT, CC, PPCSubTarget.hasVSX());
837 return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS);
841 SDValue VCmp(CurDAG->getMachineNode(VCmpInst, dl, VecVT, LHS, RHS), 0);
842 return CurDAG->SelectNodeTo(N, PPCSubTarget.hasVSX() ? PPC::XXLNOR :
849 return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, RHS, LHS);
853 return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS);
857 // Small optimization: Altivec provides a 'Vector Compare Greater Than
858 // or Equal To' instruction (vcmpgefp), so in this case there is no
859 // need for extra logic for the equal compare.
860 if (VecVT.getSimpleVT().isFloatingPoint()) {
861 return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS);
863 SDValue VCmpGT(CurDAG->getMachineNode(VCmpInst, dl, VecVT, LHS, RHS), 0);
864 unsigned int VCmpEQInst = getVCmpEQInst(VT, PPCSubTarget.hasVSX());
865 SDValue VCmpEQ(CurDAG->getMachineNode(VCmpEQInst, dl, VecVT, LHS, RHS), 0);
866 return CurDAG->SelectNodeTo(N, PPCSubTarget.hasVSX() ? PPC::XXLOR :
868 VecVT, VCmpGT, VCmpEQ);
874 SDValue VCmpLE(CurDAG->getMachineNode(VCmpInst, dl, VecVT, RHS, LHS), 0);
875 unsigned int VCmpEQInst = getVCmpEQInst(VT, PPCSubTarget.hasVSX());
876 SDValue VCmpEQ(CurDAG->getMachineNode(VCmpEQInst, dl, VecVT, LHS, RHS), 0);
877 return CurDAG->SelectNodeTo(N, PPCSubTarget.hasVSX() ? PPC::XXLOR :
879 VecVT, VCmpLE, VCmpEQ);
882 llvm_unreachable("Invalid vector compare type: should be expanded by legalize");
886 if (PPCSubTarget.useCRBits())
890 unsigned Idx = getCRIdxForSetCC(CC, Inv);
891 SDValue CCReg = SelectCC(LHS, RHS, CC, dl);
894 // Force the ccreg into CR7.
895 SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
897 SDValue InFlag(nullptr, 0); // Null incoming flag value.
898 CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, CR7Reg, CCReg,
901 IntCR = SDValue(CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg,
904 SDValue Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31),
905 getI32Imm(31), getI32Imm(31) };
907 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
909 // Get the specified bit.
911 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0);
912 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
916 // Select - Convert the specified operand from a target-independent to a
917 // target-specific node if it hasn't already been changed.
918 SDNode *PPCDAGToDAGISel::Select(SDNode *N) {
920 if (N->isMachineOpcode()) {
922 return nullptr; // Already selected.
925 switch (N->getOpcode()) {
928 case ISD::Constant: {
929 if (N->getValueType(0) == MVT::i64) {
931 int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue();
932 // Assume no remaining bits.
933 unsigned Remainder = 0;
934 // Assume no shift required.
937 // If it can't be represented as a 32 bit value.
938 if (!isInt<32>(Imm)) {
939 Shift = countTrailingZeros<uint64_t>(Imm);
940 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
942 // If the shifted value fits 32 bits.
943 if (isInt<32>(ImmSh)) {
944 // Go with the shifted value.
947 // Still stuck with a 64 bit value.
954 // Intermediate operand.
957 // Handle first 32 bits.
958 unsigned Lo = Imm & 0xFFFF;
959 unsigned Hi = (Imm >> 16) & 0xFFFF;
962 if (isInt<16>(Imm)) {
964 Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo));
966 // Handle the Hi bits.
967 unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8;
968 Result = CurDAG->getMachineNode(OpC, dl, MVT::i64, getI32Imm(Hi));
970 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
971 SDValue(Result, 0), getI32Imm(Lo));
974 Result = CurDAG->getMachineNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi));
977 // If no shift, we're done.
978 if (!Shift) return Result;
980 // Shift for next step if the upper 32-bits were not zero.
982 Result = CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64,
985 getI32Imm(63 - Shift));
988 // Add in the last bits as required.
989 if ((Hi = (Remainder >> 16) & 0xFFFF)) {
990 Result = CurDAG->getMachineNode(PPC::ORIS8, dl, MVT::i64,
991 SDValue(Result, 0), getI32Imm(Hi));
993 if ((Lo = Remainder & 0xFFFF)) {
994 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
995 SDValue(Result, 0), getI32Imm(Lo));
1004 SDNode *SN = SelectSETCC(N);
1009 case PPCISD::GlobalBaseReg:
1010 return getGlobalBaseReg();
1012 case ISD::FrameIndex: {
1013 int FI = cast<FrameIndexSDNode>(N)->getIndex();
1014 SDValue TFI = CurDAG->getTargetFrameIndex(FI, N->getValueType(0));
1015 unsigned Opc = N->getValueType(0) == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
1017 return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), TFI,
1018 getSmallIPtrImm(0));
1019 return CurDAG->getMachineNode(Opc, dl, N->getValueType(0), TFI,
1020 getSmallIPtrImm(0));
1023 case PPCISD::MFOCRF: {
1024 SDValue InFlag = N->getOperand(1);
1025 return CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32,
1026 N->getOperand(0), InFlag);
1030 // FIXME: since this depends on the setting of the carry flag from the srawi
1031 // we should really be making notes about that for the scheduler.
1032 // FIXME: It sure would be nice if we could cheaply recognize the
1033 // srl/add/sra pattern the dag combiner will generate for this as
1034 // sra/addze rather than having to handle sdiv ourselves. oh well.
1036 if (isInt32Immediate(N->getOperand(1), Imm)) {
1037 SDValue N0 = N->getOperand(0);
1038 if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
1040 CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Glue,
1041 N0, getI32Imm(Log2_32(Imm)));
1042 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
1043 SDValue(Op, 0), SDValue(Op, 1));
1044 } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
1046 CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Glue,
1047 N0, getI32Imm(Log2_32(-Imm)));
1049 SDValue(CurDAG->getMachineNode(PPC::ADDZE, dl, MVT::i32,
1050 SDValue(Op, 0), SDValue(Op, 1)),
1052 return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
1056 // Other cases are autogenerated.
1061 // Handle preincrement loads.
1062 LoadSDNode *LD = cast<LoadSDNode>(N);
1063 EVT LoadedVT = LD->getMemoryVT();
1065 // Normal loads are handled by code generated from the .td file.
1066 if (LD->getAddressingMode() != ISD::PRE_INC)
1069 SDValue Offset = LD->getOffset();
1070 if (Offset.getOpcode() == ISD::TargetConstant ||
1071 Offset.getOpcode() == ISD::TargetGlobalAddress) {
1074 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
1075 if (LD->getValueType(0) != MVT::i64) {
1076 // Handle PPC32 integer and normal FP loads.
1077 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
1078 switch (LoadedVT.getSimpleVT().SimpleTy) {
1079 default: llvm_unreachable("Invalid PPC load type!");
1080 case MVT::f64: Opcode = PPC::LFDU; break;
1081 case MVT::f32: Opcode = PPC::LFSU; break;
1082 case MVT::i32: Opcode = PPC::LWZU; break;
1083 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
1085 case MVT::i8: Opcode = PPC::LBZU; break;
1088 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
1089 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
1090 switch (LoadedVT.getSimpleVT().SimpleTy) {
1091 default: llvm_unreachable("Invalid PPC load type!");
1092 case MVT::i64: Opcode = PPC::LDU; break;
1093 case MVT::i32: Opcode = PPC::LWZU8; break;
1094 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
1096 case MVT::i8: Opcode = PPC::LBZU8; break;
1100 SDValue Chain = LD->getChain();
1101 SDValue Base = LD->getBasePtr();
1102 SDValue Ops[] = { Offset, Base, Chain };
1103 return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0),
1104 PPCLowering.getPointerTy(),
1108 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
1109 if (LD->getValueType(0) != MVT::i64) {
1110 // Handle PPC32 integer and normal FP loads.
1111 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
1112 switch (LoadedVT.getSimpleVT().SimpleTy) {
1113 default: llvm_unreachable("Invalid PPC load type!");
1114 case MVT::f64: Opcode = PPC::LFDUX; break;
1115 case MVT::f32: Opcode = PPC::LFSUX; break;
1116 case MVT::i32: Opcode = PPC::LWZUX; break;
1117 case MVT::i16: Opcode = isSExt ? PPC::LHAUX : PPC::LHZUX; break;
1119 case MVT::i8: Opcode = PPC::LBZUX; break;
1122 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
1123 assert((!isSExt || LoadedVT == MVT::i16 || LoadedVT == MVT::i32) &&
1124 "Invalid sext update load");
1125 switch (LoadedVT.getSimpleVT().SimpleTy) {
1126 default: llvm_unreachable("Invalid PPC load type!");
1127 case MVT::i64: Opcode = PPC::LDUX; break;
1128 case MVT::i32: Opcode = isSExt ? PPC::LWAUX : PPC::LWZUX8; break;
1129 case MVT::i16: Opcode = isSExt ? PPC::LHAUX8 : PPC::LHZUX8; break;
1131 case MVT::i8: Opcode = PPC::LBZUX8; break;
1135 SDValue Chain = LD->getChain();
1136 SDValue Base = LD->getBasePtr();
1137 SDValue Ops[] = { Base, Offset, Chain };
1138 return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0),
1139 PPCLowering.getPointerTy(),
1145 unsigned Imm, Imm2, SH, MB, ME;
1148 // If this is an and of a value rotated between 0 and 31 bits and then and'd
1149 // with a mask, emit rlwinm
1150 if (isInt32Immediate(N->getOperand(1), Imm) &&
1151 isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH, MB, ME)) {
1152 SDValue Val = N->getOperand(0).getOperand(0);
1153 SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
1154 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
1156 // If this is just a masked value where the input is not handled above, and
1157 // is not a rotate-left (handled by a pattern in the .td file), emit rlwinm
1158 if (isInt32Immediate(N->getOperand(1), Imm) &&
1159 isRunOfOnes(Imm, MB, ME) &&
1160 N->getOperand(0).getOpcode() != ISD::ROTL) {
1161 SDValue Val = N->getOperand(0);
1162 SDValue Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) };
1163 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
1165 // If this is a 64-bit zero-extension mask, emit rldicl.
1166 if (isInt64Immediate(N->getOperand(1).getNode(), Imm64) &&
1168 SDValue Val = N->getOperand(0);
1169 MB = 64 - CountTrailingOnes_64(Imm64);
1172 // If the operand is a logical right shift, we can fold it into this
1173 // instruction: rldicl(rldicl(x, 64-n, n), 0, mb) -> rldicl(x, 64-n, mb)
1174 // for n <= mb. The right shift is really a left rotate followed by a
1175 // mask, and this mask is a more-restrictive sub-mask of the mask implied
1177 if (Val.getOpcode() == ISD::SRL &&
1178 isInt32Immediate(Val.getOperand(1).getNode(), Imm) && Imm <= MB) {
1179 assert(Imm < 64 && "Illegal shift amount");
1180 Val = Val.getOperand(0);
1184 SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB) };
1185 return CurDAG->SelectNodeTo(N, PPC::RLDICL, MVT::i64, Ops);
1187 // AND X, 0 -> 0, not "rlwinm 32".
1188 if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) {
1189 ReplaceUses(SDValue(N, 0), N->getOperand(1));
1192 // ISD::OR doesn't get all the bitfield insertion fun.
1193 // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert
1194 if (isInt32Immediate(N->getOperand(1), Imm) &&
1195 N->getOperand(0).getOpcode() == ISD::OR &&
1196 isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) {
1199 if (isRunOfOnes(Imm, MB, ME)) {
1200 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1201 N->getOperand(0).getOperand(1),
1202 getI32Imm(0), getI32Imm(MB),getI32Imm(ME) };
1203 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops);
1207 // Other cases are autogenerated.
1211 if (N->getValueType(0) == MVT::i32)
1212 if (SDNode *I = SelectBitfieldInsert(N))
1215 // Other cases are autogenerated.
1218 unsigned Imm, SH, MB, ME;
1219 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
1220 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
1221 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1222 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
1223 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
1226 // Other cases are autogenerated.
1230 unsigned Imm, SH, MB, ME;
1231 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
1232 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
1233 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1234 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
1235 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
1238 // Other cases are autogenerated.
1241 // FIXME: Remove this once the ANDI glue bug is fixed:
1242 case PPCISD::ANDIo_1_EQ_BIT:
1243 case PPCISD::ANDIo_1_GT_BIT: {
1247 EVT InVT = N->getOperand(0).getValueType();
1248 assert((InVT == MVT::i64 || InVT == MVT::i32) &&
1249 "Invalid input type for ANDIo_1_EQ_BIT");
1251 unsigned Opcode = (InVT == MVT::i64) ? PPC::ANDIo8 : PPC::ANDIo;
1252 SDValue AndI(CurDAG->getMachineNode(Opcode, dl, InVT, MVT::Glue,
1254 CurDAG->getTargetConstant(1, InVT)), 0);
1255 SDValue CR0Reg = CurDAG->getRegister(PPC::CR0, MVT::i32);
1257 CurDAG->getTargetConstant(N->getOpcode() == PPCISD::ANDIo_1_EQ_BIT ?
1258 PPC::sub_eq : PPC::sub_gt, MVT::i32);
1260 return CurDAG->SelectNodeTo(N, TargetOpcode::EXTRACT_SUBREG, MVT::i1,
1262 SDValue(AndI.getNode(), 1) /* glue */);
1264 case ISD::SELECT_CC: {
1265 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1266 EVT PtrVT = CurDAG->getTargetLoweringInfo().getPointerTy();
1267 bool isPPC64 = (PtrVT == MVT::i64);
1269 // If this is a select of i1 operands, we'll pattern match it.
1270 if (PPCSubTarget.useCRBits() &&
1271 N->getOperand(0).getValueType() == MVT::i1)
1274 // Handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
1276 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1277 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
1278 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
1279 if (N1C->isNullValue() && N3C->isNullValue() &&
1280 N2C->getZExtValue() == 1ULL && CC == ISD::SETNE &&
1281 // FIXME: Implement this optzn for PPC64.
1282 N->getValueType(0) == MVT::i32) {
1284 CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
1285 N->getOperand(0), getI32Imm(~0U));
1286 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
1287 SDValue(Tmp, 0), N->getOperand(0),
1291 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl);
1293 if (N->getValueType(0) == MVT::i1) {
1294 // An i1 select is: (c & t) | (!c & f).
1296 unsigned Idx = getCRIdxForSetCC(CC, Inv);
1300 default: llvm_unreachable("Invalid CC index");
1301 case 0: SRI = PPC::sub_lt; break;
1302 case 1: SRI = PPC::sub_gt; break;
1303 case 2: SRI = PPC::sub_eq; break;
1304 case 3: SRI = PPC::sub_un; break;
1307 SDValue CCBit = CurDAG->getTargetExtractSubreg(SRI, dl, MVT::i1, CCReg);
1309 SDValue NotCCBit(CurDAG->getMachineNode(PPC::CRNOR, dl, MVT::i1,
1311 SDValue C = Inv ? NotCCBit : CCBit,
1312 NotC = Inv ? CCBit : NotCCBit;
1314 SDValue CAndT(CurDAG->getMachineNode(PPC::CRAND, dl, MVT::i1,
1315 C, N->getOperand(2)), 0);
1316 SDValue NotCAndF(CurDAG->getMachineNode(PPC::CRAND, dl, MVT::i1,
1317 NotC, N->getOperand(3)), 0);
1319 return CurDAG->SelectNodeTo(N, PPC::CROR, MVT::i1, CAndT, NotCAndF);
1322 unsigned BROpc = getPredicateForSetCC(CC);
1324 unsigned SelectCCOp;
1325 if (N->getValueType(0) == MVT::i32)
1326 SelectCCOp = PPC::SELECT_CC_I4;
1327 else if (N->getValueType(0) == MVT::i64)
1328 SelectCCOp = PPC::SELECT_CC_I8;
1329 else if (N->getValueType(0) == MVT::f32)
1330 SelectCCOp = PPC::SELECT_CC_F4;
1331 else if (N->getValueType(0) == MVT::f64)
1332 SelectCCOp = PPC::SELECT_CC_F8;
1334 SelectCCOp = PPC::SELECT_CC_VRRC;
1336 SDValue Ops[] = { CCReg, N->getOperand(2), N->getOperand(3),
1338 return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops);
1341 if (PPCSubTarget.hasVSX()) {
1342 SDValue Ops[] = { N->getOperand(2), N->getOperand(1), N->getOperand(0) };
1343 return CurDAG->SelectNodeTo(N, PPC::XXSEL, N->getValueType(0), Ops);
1347 case ISD::VECTOR_SHUFFLE:
1348 if (PPCSubTarget.hasVSX() && (N->getValueType(0) == MVT::v2f64 ||
1349 N->getValueType(0) == MVT::v2i64)) {
1350 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
1352 SDValue Op1 = N->getOperand(SVN->getMaskElt(0) < 2 ? 0 : 1),
1353 Op2 = N->getOperand(SVN->getMaskElt(1) < 2 ? 0 : 1);
1356 for (int i = 0; i < 2; ++i)
1357 if (SVN->getMaskElt(i) <= 0 || SVN->getMaskElt(i) == 2)
1362 SDValue DMV = CurDAG->getTargetConstant(DM[1] | (DM[0] << 1), MVT::i32);
1364 if (Op1 == Op2 && DM[0] == 0 && DM[1] == 0 &&
1365 Op1.getOpcode() == ISD::SCALAR_TO_VECTOR &&
1366 isa<LoadSDNode>(Op1.getOperand(0))) {
1367 LoadSDNode *LD = cast<LoadSDNode>(Op1.getOperand(0));
1368 SDValue Base, Offset;
1370 if (LD->isUnindexed() &&
1371 SelectAddrIdxOnly(LD->getBasePtr(), Base, Offset)) {
1372 SDValue Chain = LD->getChain();
1373 SDValue Ops[] = { Base, Offset, Chain };
1374 return CurDAG->SelectNodeTo(N, PPC::LXVDSX,
1375 N->getValueType(0), Ops);
1379 SDValue Ops[] = { Op1, Op2, DMV };
1380 return CurDAG->SelectNodeTo(N, PPC::XXPERMDI, N->getValueType(0), Ops);
1386 bool IsPPC64 = PPCSubTarget.isPPC64();
1387 SDValue Ops[] = { N->getOperand(1), N->getOperand(0) };
1388 return CurDAG->SelectNodeTo(N, N->getOpcode() == PPCISD::BDNZ ?
1389 (IsPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
1390 (IsPPC64 ? PPC::BDZ8 : PPC::BDZ),
1393 case PPCISD::COND_BRANCH: {
1394 // Op #0 is the Chain.
1395 // Op #1 is the PPC::PRED_* number.
1397 // Op #3 is the Dest MBB
1398 // Op #4 is the Flag.
1399 // Prevent PPC::PRED_* from being selected into LI.
1401 getI32Imm(cast<ConstantSDNode>(N->getOperand(1))->getZExtValue());
1402 SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3),
1403 N->getOperand(0), N->getOperand(4) };
1404 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops);
1407 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
1408 unsigned PCC = getPredicateForSetCC(CC);
1410 if (N->getOperand(2).getValueType() == MVT::i1) {
1414 default: llvm_unreachable("Unexpected Boolean-operand predicate");
1415 case PPC::PRED_LT: Opc = PPC::CRANDC; Swap = true; break;
1416 case PPC::PRED_LE: Opc = PPC::CRORC; Swap = true; break;
1417 case PPC::PRED_EQ: Opc = PPC::CREQV; Swap = false; break;
1418 case PPC::PRED_GE: Opc = PPC::CRORC; Swap = false; break;
1419 case PPC::PRED_GT: Opc = PPC::CRANDC; Swap = false; break;
1420 case PPC::PRED_NE: Opc = PPC::CRXOR; Swap = false; break;
1423 SDValue BitComp(CurDAG->getMachineNode(Opc, dl, MVT::i1,
1424 N->getOperand(Swap ? 3 : 2),
1425 N->getOperand(Swap ? 2 : 3)), 0);
1426 return CurDAG->SelectNodeTo(N, PPC::BC, MVT::Other,
1427 BitComp, N->getOperand(4), N->getOperand(0));
1430 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl);
1431 SDValue Ops[] = { getI32Imm(PCC), CondCode,
1432 N->getOperand(4), N->getOperand(0) };
1433 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops);
1436 // FIXME: Should custom lower this.
1437 SDValue Chain = N->getOperand(0);
1438 SDValue Target = N->getOperand(1);
1439 unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
1440 unsigned Reg = Target.getValueType() == MVT::i32 ? PPC::BCTR : PPC::BCTR8;
1441 Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, Target,
1443 return CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain);
1445 case PPCISD::TOC_ENTRY: {
1446 assert (PPCSubTarget.isPPC64() && "Only supported for 64-bit ABI");
1448 // For medium and large code model, we generate two instructions as
1449 // described below. Otherwise we allow SelectCodeCommon to handle this,
1450 // selecting one of LDtoc, LDtocJTI, and LDtocCPT.
1451 CodeModel::Model CModel = TM.getCodeModel();
1452 if (CModel != CodeModel::Medium && CModel != CodeModel::Large)
1455 // The first source operand is a TargetGlobalAddress or a
1456 // TargetJumpTable. If it is an externally defined symbol, a symbol
1457 // with common linkage, a function address, or a jump table address,
1458 // or if we are generating code for large code model, we generate:
1459 // LDtocL(<ga:@sym>, ADDIStocHA(%X2, <ga:@sym>))
1460 // Otherwise we generate:
1461 // ADDItocL(ADDIStocHA(%X2, <ga:@sym>), <ga:@sym>)
1462 SDValue GA = N->getOperand(0);
1463 SDValue TOCbase = N->getOperand(1);
1464 SDNode *Tmp = CurDAG->getMachineNode(PPC::ADDIStocHA, dl, MVT::i64,
1467 if (isa<JumpTableSDNode>(GA) || CModel == CodeModel::Large)
1468 return CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA,
1471 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(GA)) {
1472 const GlobalValue *GValue = G->getGlobal();
1473 const GlobalAlias *GAlias = dyn_cast<GlobalAlias>(GValue);
1474 const GlobalValue *RealGValue = GAlias ? GAlias->getAliasee() : GValue;
1475 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(RealGValue);
1476 assert((GVar || isa<Function>(RealGValue)) &&
1477 "Unexpected global value subclass!");
1479 // An external variable is one without an initializer. For these,
1480 // for variables with common linkage, and for Functions, generate
1482 if (!GVar || !GVar->hasInitializer() || RealGValue->hasCommonLinkage() ||
1483 RealGValue->hasAvailableExternallyLinkage())
1484 return CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA,
1488 return CurDAG->getMachineNode(PPC::ADDItocL, dl, MVT::i64,
1489 SDValue(Tmp, 0), GA);
1491 case PPCISD::VADD_SPLAT: {
1492 // This expands into one of three sequences, depending on whether
1493 // the first operand is odd or even, positive or negative.
1494 assert(isa<ConstantSDNode>(N->getOperand(0)) &&
1495 isa<ConstantSDNode>(N->getOperand(1)) &&
1496 "Invalid operand on VADD_SPLAT!");
1498 int Elt = N->getConstantOperandVal(0);
1499 int EltSize = N->getConstantOperandVal(1);
1500 unsigned Opc1, Opc2, Opc3;
1504 Opc1 = PPC::VSPLTISB;
1505 Opc2 = PPC::VADDUBM;
1506 Opc3 = PPC::VSUBUBM;
1508 } else if (EltSize == 2) {
1509 Opc1 = PPC::VSPLTISH;
1510 Opc2 = PPC::VADDUHM;
1511 Opc3 = PPC::VSUBUHM;
1514 assert(EltSize == 4 && "Invalid element size on VADD_SPLAT!");
1515 Opc1 = PPC::VSPLTISW;
1516 Opc2 = PPC::VADDUWM;
1517 Opc3 = PPC::VSUBUWM;
1521 if ((Elt & 1) == 0) {
1522 // Elt is even, in the range [-32,-18] + [16,30].
1524 // Convert: VADD_SPLAT elt, size
1525 // Into: tmp = VSPLTIS[BHW] elt
1526 // VADDU[BHW]M tmp, tmp
1527 // Where: [BHW] = B for size = 1, H for size = 2, W for size = 4
1528 SDValue EltVal = getI32Imm(Elt >> 1);
1529 SDNode *Tmp = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
1530 SDValue TmpVal = SDValue(Tmp, 0);
1531 return CurDAG->getMachineNode(Opc2, dl, VT, TmpVal, TmpVal);
1533 } else if (Elt > 0) {
1534 // Elt is odd and positive, in the range [17,31].
1536 // Convert: VADD_SPLAT elt, size
1537 // Into: tmp1 = VSPLTIS[BHW] elt-16
1538 // tmp2 = VSPLTIS[BHW] -16
1539 // VSUBU[BHW]M tmp1, tmp2
1540 SDValue EltVal = getI32Imm(Elt - 16);
1541 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
1542 EltVal = getI32Imm(-16);
1543 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
1544 return CurDAG->getMachineNode(Opc3, dl, VT, SDValue(Tmp1, 0),
1548 // Elt is odd and negative, in the range [-31,-17].
1550 // Convert: VADD_SPLAT elt, size
1551 // Into: tmp1 = VSPLTIS[BHW] elt+16
1552 // tmp2 = VSPLTIS[BHW] -16
1553 // VADDU[BHW]M tmp1, tmp2
1554 SDValue EltVal = getI32Imm(Elt + 16);
1555 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
1556 EltVal = getI32Imm(-16);
1557 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
1558 return CurDAG->getMachineNode(Opc2, dl, VT, SDValue(Tmp1, 0),
1564 return SelectCode(N);
1567 /// PostprocessISelDAG - Perform some late peephole optimizations
1568 /// on the DAG representation.
1569 void PPCDAGToDAGISel::PostprocessISelDAG() {
1571 // Skip peepholes at -O0.
1572 if (TM.getOptLevel() == CodeGenOpt::None)
1579 // Check if all users of this node will become isel where the second operand
1580 // is the constant zero. If this is so, and if we can negate the condition,
1581 // then we can flip the true and false operands. This will allow the zero to
1582 // be folded with the isel so that we don't need to materialize a register
1584 bool PPCDAGToDAGISel::AllUsersSelectZero(SDNode *N) {
1585 // If we're not using isel, then this does not matter.
1586 if (!PPCSubTarget.hasISEL())
1589 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
1592 if (!User->isMachineOpcode())
1594 if (User->getMachineOpcode() != PPC::SELECT_I4 &&
1595 User->getMachineOpcode() != PPC::SELECT_I8)
1598 SDNode *Op2 = User->getOperand(2).getNode();
1599 if (!Op2->isMachineOpcode())
1602 if (Op2->getMachineOpcode() != PPC::LI &&
1603 Op2->getMachineOpcode() != PPC::LI8)
1606 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op2->getOperand(0));
1610 if (!C->isNullValue())
1617 void PPCDAGToDAGISel::SwapAllSelectUsers(SDNode *N) {
1618 SmallVector<SDNode *, 4> ToReplace;
1619 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
1622 assert((User->getMachineOpcode() == PPC::SELECT_I4 ||
1623 User->getMachineOpcode() == PPC::SELECT_I8) &&
1624 "Must have all select users");
1625 ToReplace.push_back(User);
1628 for (SmallVector<SDNode *, 4>::iterator UI = ToReplace.begin(),
1629 UE = ToReplace.end(); UI != UE; ++UI) {
1632 CurDAG->getMachineNode(User->getMachineOpcode(), SDLoc(User),
1633 User->getValueType(0), User->getOperand(0),
1634 User->getOperand(2),
1635 User->getOperand(1));
1637 DEBUG(dbgs() << "CR Peephole replacing:\nOld: ");
1638 DEBUG(User->dump(CurDAG));
1639 DEBUG(dbgs() << "\nNew: ");
1640 DEBUG(ResNode->dump(CurDAG));
1641 DEBUG(dbgs() << "\n");
1643 ReplaceUses(User, ResNode);
1647 void PPCDAGToDAGISel::PeepholeCROps() {
1651 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
1652 E = CurDAG->allnodes_end(); I != E; ++I) {
1653 MachineSDNode *MachineNode = dyn_cast<MachineSDNode>(I);
1654 if (!MachineNode || MachineNode->use_empty())
1656 SDNode *ResNode = MachineNode;
1658 bool Op1Set = false, Op1Unset = false,
1660 Op2Set = false, Op2Unset = false,
1663 unsigned Opcode = MachineNode->getMachineOpcode();
1674 SDValue Op = MachineNode->getOperand(1);
1675 if (Op.isMachineOpcode()) {
1676 if (Op.getMachineOpcode() == PPC::CRSET)
1678 else if (Op.getMachineOpcode() == PPC::CRUNSET)
1680 else if (Op.getMachineOpcode() == PPC::CRNOR &&
1681 Op.getOperand(0) == Op.getOperand(1))
1687 case PPC::SELECT_I4:
1688 case PPC::SELECT_I8:
1689 case PPC::SELECT_F4:
1690 case PPC::SELECT_F8:
1691 case PPC::SELECT_VRRC: {
1692 SDValue Op = MachineNode->getOperand(0);
1693 if (Op.isMachineOpcode()) {
1694 if (Op.getMachineOpcode() == PPC::CRSET)
1696 else if (Op.getMachineOpcode() == PPC::CRUNSET)
1698 else if (Op.getMachineOpcode() == PPC::CRNOR &&
1699 Op.getOperand(0) == Op.getOperand(1))
1706 bool SelectSwap = false;
1710 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
1712 ResNode = MachineNode->getOperand(0).getNode();
1715 ResNode = MachineNode->getOperand(1).getNode();
1718 ResNode = MachineNode->getOperand(0).getNode();
1719 else if (Op1Unset || Op2Unset)
1720 // x & 0 = 0 & y = 0
1721 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
1724 // ~x & y = andc(y, x)
1725 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
1726 MVT::i1, MachineNode->getOperand(1),
1727 MachineNode->getOperand(0).
1730 // x & ~y = andc(x, y)
1731 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
1732 MVT::i1, MachineNode->getOperand(0),
1733 MachineNode->getOperand(1).
1735 else if (AllUsersSelectZero(MachineNode))
1736 ResNode = CurDAG->getMachineNode(PPC::CRNAND, SDLoc(MachineNode),
1737 MVT::i1, MachineNode->getOperand(0),
1738 MachineNode->getOperand(1)),
1742 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
1743 // nand(x, x) -> nor(x, x)
1744 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1745 MVT::i1, MachineNode->getOperand(0),
1746 MachineNode->getOperand(0));
1748 // nand(1, y) -> nor(y, y)
1749 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1750 MVT::i1, MachineNode->getOperand(1),
1751 MachineNode->getOperand(1));
1753 // nand(x, 1) -> nor(x, x)
1754 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1755 MVT::i1, MachineNode->getOperand(0),
1756 MachineNode->getOperand(0));
1757 else if (Op1Unset || Op2Unset)
1758 // nand(x, 0) = nand(0, y) = 1
1759 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
1762 // nand(~x, y) = ~(~x & y) = x | ~y = orc(x, y)
1763 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
1764 MVT::i1, MachineNode->getOperand(0).
1766 MachineNode->getOperand(1));
1768 // nand(x, ~y) = ~x | y = orc(y, x)
1769 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
1770 MVT::i1, MachineNode->getOperand(1).
1772 MachineNode->getOperand(0));
1773 else if (AllUsersSelectZero(MachineNode))
1774 ResNode = CurDAG->getMachineNode(PPC::CRAND, SDLoc(MachineNode),
1775 MVT::i1, MachineNode->getOperand(0),
1776 MachineNode->getOperand(1)),
1780 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
1782 ResNode = MachineNode->getOperand(0).getNode();
1783 else if (Op1Set || Op2Set)
1784 // x | 1 = 1 | y = 1
1785 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
1789 ResNode = MachineNode->getOperand(1).getNode();
1792 ResNode = MachineNode->getOperand(0).getNode();
1794 // ~x | y = orc(y, x)
1795 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
1796 MVT::i1, MachineNode->getOperand(1),
1797 MachineNode->getOperand(0).
1800 // x | ~y = orc(x, y)
1801 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
1802 MVT::i1, MachineNode->getOperand(0),
1803 MachineNode->getOperand(1).
1805 else if (AllUsersSelectZero(MachineNode))
1806 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1807 MVT::i1, MachineNode->getOperand(0),
1808 MachineNode->getOperand(1)),
1812 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
1814 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
1817 // xor(1, y) -> nor(y, y)
1818 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1819 MVT::i1, MachineNode->getOperand(1),
1820 MachineNode->getOperand(1));
1822 // xor(x, 1) -> nor(x, x)
1823 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1824 MVT::i1, MachineNode->getOperand(0),
1825 MachineNode->getOperand(0));
1828 ResNode = MachineNode->getOperand(1).getNode();
1831 ResNode = MachineNode->getOperand(0).getNode();
1833 // xor(~x, y) = eqv(x, y)
1834 ResNode = CurDAG->getMachineNode(PPC::CREQV, SDLoc(MachineNode),
1835 MVT::i1, MachineNode->getOperand(0).
1837 MachineNode->getOperand(1));
1839 // xor(x, ~y) = eqv(x, y)
1840 ResNode = CurDAG->getMachineNode(PPC::CREQV, SDLoc(MachineNode),
1841 MVT::i1, MachineNode->getOperand(0),
1842 MachineNode->getOperand(1).
1844 else if (AllUsersSelectZero(MachineNode))
1845 ResNode = CurDAG->getMachineNode(PPC::CREQV, SDLoc(MachineNode),
1846 MVT::i1, MachineNode->getOperand(0),
1847 MachineNode->getOperand(1)),
1851 if (Op1Set || Op2Set)
1853 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
1856 // nor(0, y) = ~y -> nor(y, y)
1857 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1858 MVT::i1, MachineNode->getOperand(1),
1859 MachineNode->getOperand(1));
1862 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1863 MVT::i1, MachineNode->getOperand(0),
1864 MachineNode->getOperand(0));
1866 // nor(~x, y) = andc(x, y)
1867 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
1868 MVT::i1, MachineNode->getOperand(0).
1870 MachineNode->getOperand(1));
1872 // nor(x, ~y) = andc(y, x)
1873 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
1874 MVT::i1, MachineNode->getOperand(1).
1876 MachineNode->getOperand(0));
1877 else if (AllUsersSelectZero(MachineNode))
1878 ResNode = CurDAG->getMachineNode(PPC::CROR, SDLoc(MachineNode),
1879 MVT::i1, MachineNode->getOperand(0),
1880 MachineNode->getOperand(1)),
1884 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
1886 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
1890 ResNode = MachineNode->getOperand(1).getNode();
1893 ResNode = MachineNode->getOperand(0).getNode();
1895 // eqv(0, y) = ~y -> nor(y, y)
1896 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1897 MVT::i1, MachineNode->getOperand(1),
1898 MachineNode->getOperand(1));
1901 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1902 MVT::i1, MachineNode->getOperand(0),
1903 MachineNode->getOperand(0));
1905 // eqv(~x, y) = xor(x, y)
1906 ResNode = CurDAG->getMachineNode(PPC::CRXOR, SDLoc(MachineNode),
1907 MVT::i1, MachineNode->getOperand(0).
1909 MachineNode->getOperand(1));
1911 // eqv(x, ~y) = xor(x, y)
1912 ResNode = CurDAG->getMachineNode(PPC::CRXOR, SDLoc(MachineNode),
1913 MVT::i1, MachineNode->getOperand(0),
1914 MachineNode->getOperand(1).
1916 else if (AllUsersSelectZero(MachineNode))
1917 ResNode = CurDAG->getMachineNode(PPC::CRXOR, SDLoc(MachineNode),
1918 MVT::i1, MachineNode->getOperand(0),
1919 MachineNode->getOperand(1)),
1923 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
1925 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
1929 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1930 MVT::i1, MachineNode->getOperand(1),
1931 MachineNode->getOperand(1));
1932 else if (Op1Unset || Op2Set)
1933 // andc(0, y) = andc(x, 1) = 0
1934 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
1938 ResNode = MachineNode->getOperand(0).getNode();
1940 // andc(~x, y) = ~(x | y) = nor(x, y)
1941 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1942 MVT::i1, MachineNode->getOperand(0).
1944 MachineNode->getOperand(1));
1946 // andc(x, ~y) = x & y
1947 ResNode = CurDAG->getMachineNode(PPC::CRAND, SDLoc(MachineNode),
1948 MVT::i1, MachineNode->getOperand(0),
1949 MachineNode->getOperand(1).
1951 else if (AllUsersSelectZero(MachineNode))
1952 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
1953 MVT::i1, MachineNode->getOperand(1),
1954 MachineNode->getOperand(0)),
1958 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
1960 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
1962 else if (Op1Set || Op2Unset)
1963 // orc(1, y) = orc(x, 0) = 1
1964 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
1968 ResNode = MachineNode->getOperand(0).getNode();
1971 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1972 MVT::i1, MachineNode->getOperand(1),
1973 MachineNode->getOperand(1));
1975 // orc(~x, y) = ~(x & y) = nand(x, y)
1976 ResNode = CurDAG->getMachineNode(PPC::CRNAND, SDLoc(MachineNode),
1977 MVT::i1, MachineNode->getOperand(0).
1979 MachineNode->getOperand(1));
1981 // orc(x, ~y) = x | y
1982 ResNode = CurDAG->getMachineNode(PPC::CROR, SDLoc(MachineNode),
1983 MVT::i1, MachineNode->getOperand(0),
1984 MachineNode->getOperand(1).
1986 else if (AllUsersSelectZero(MachineNode))
1987 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
1988 MVT::i1, MachineNode->getOperand(1),
1989 MachineNode->getOperand(0)),
1992 case PPC::SELECT_I4:
1993 case PPC::SELECT_I8:
1994 case PPC::SELECT_F4:
1995 case PPC::SELECT_F8:
1996 case PPC::SELECT_VRRC:
1998 ResNode = MachineNode->getOperand(1).getNode();
2000 ResNode = MachineNode->getOperand(2).getNode();
2002 ResNode = CurDAG->getMachineNode(MachineNode->getMachineOpcode(),
2004 MachineNode->getValueType(0),
2005 MachineNode->getOperand(0).
2007 MachineNode->getOperand(2),
2008 MachineNode->getOperand(1));
2013 ResNode = CurDAG->getMachineNode(Opcode == PPC::BC ? PPC::BCn :
2017 MachineNode->getOperand(0).
2019 MachineNode->getOperand(1),
2020 MachineNode->getOperand(2));
2021 // FIXME: Handle Op1Set, Op1Unset here too.
2025 // If we're inverting this node because it is used only by selects that
2026 // we'd like to swap, then swap the selects before the node replacement.
2028 SwapAllSelectUsers(MachineNode);
2030 if (ResNode != MachineNode) {
2031 DEBUG(dbgs() << "CR Peephole replacing:\nOld: ");
2032 DEBUG(MachineNode->dump(CurDAG));
2033 DEBUG(dbgs() << "\nNew: ");
2034 DEBUG(ResNode->dump(CurDAG));
2035 DEBUG(dbgs() << "\n");
2037 ReplaceUses(MachineNode, ResNode);
2042 CurDAG->RemoveDeadNodes();
2043 } while (IsModified);
2046 void PPCDAGToDAGISel::PeepholePPC64() {
2047 // These optimizations are currently supported only for 64-bit SVR4.
2048 if (PPCSubTarget.isDarwin() || !PPCSubTarget.isPPC64())
2051 SelectionDAG::allnodes_iterator Position(CurDAG->getRoot().getNode());
2054 while (Position != CurDAG->allnodes_begin()) {
2055 SDNode *N = --Position;
2056 // Skip dead nodes and any non-machine opcodes.
2057 if (N->use_empty() || !N->isMachineOpcode())
2061 unsigned StorageOpcode = N->getMachineOpcode();
2063 switch (StorageOpcode) {
2094 // If this is a load or store with a zero offset, we may be able to
2095 // fold an add-immediate into the memory operation.
2096 if (!isa<ConstantSDNode>(N->getOperand(FirstOp)) ||
2097 N->getConstantOperandVal(FirstOp) != 0)
2100 SDValue Base = N->getOperand(FirstOp + 1);
2101 if (!Base.isMachineOpcode())
2105 bool ReplaceFlags = true;
2107 // When the feeding operation is an add-immediate of some sort,
2108 // determine whether we need to add relocation information to the
2109 // target flags on the immediate operand when we fold it into the
2110 // load instruction.
2112 // For something like ADDItocL, the relocation information is
2113 // inferred from the opcode; when we process it in the AsmPrinter,
2114 // we add the necessary relocation there. A load, though, can receive
2115 // relocation from various flavors of ADDIxxx, so we need to carry
2116 // the relocation information in the target flags.
2117 switch (Base.getMachineOpcode()) {
2122 // In some cases (such as TLS) the relocation information
2123 // is already in place on the operand, so copying the operand
2125 ReplaceFlags = false;
2126 // For these cases, the immediate may not be divisible by 4, in
2127 // which case the fold is illegal for DS-form instructions. (The
2128 // other cases provide aligned addresses and are always safe.)
2129 if ((StorageOpcode == PPC::LWA ||
2130 StorageOpcode == PPC::LD ||
2131 StorageOpcode == PPC::STD) &&
2132 (!isa<ConstantSDNode>(Base.getOperand(1)) ||
2133 Base.getConstantOperandVal(1) % 4 != 0))
2136 case PPC::ADDIdtprelL:
2137 Flags = PPCII::MO_DTPREL_LO;
2139 case PPC::ADDItlsldL:
2140 Flags = PPCII::MO_TLSLD_LO;
2143 Flags = PPCII::MO_TOC_LO;
2147 // We found an opportunity. Reverse the operands from the add
2148 // immediate and substitute them into the load or store. If
2149 // needed, update the target flags for the immediate operand to
2150 // reflect the necessary relocation information.
2151 DEBUG(dbgs() << "Folding add-immediate into mem-op:\nBase: ");
2152 DEBUG(Base->dump(CurDAG));
2153 DEBUG(dbgs() << "\nN: ");
2154 DEBUG(N->dump(CurDAG));
2155 DEBUG(dbgs() << "\n");
2157 SDValue ImmOpnd = Base.getOperand(1);
2159 // If the relocation information isn't already present on the
2160 // immediate operand, add it now.
2162 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(ImmOpnd)) {
2164 const GlobalValue *GV = GA->getGlobal();
2165 // We can't perform this optimization for data whose alignment
2166 // is insufficient for the instruction encoding.
2167 if (GV->getAlignment() < 4 &&
2168 (StorageOpcode == PPC::LD || StorageOpcode == PPC::STD ||
2169 StorageOpcode == PPC::LWA)) {
2170 DEBUG(dbgs() << "Rejected this candidate for alignment.\n\n");
2173 ImmOpnd = CurDAG->getTargetGlobalAddress(GV, dl, MVT::i64, 0, Flags);
2174 } else if (ConstantPoolSDNode *CP =
2175 dyn_cast<ConstantPoolSDNode>(ImmOpnd)) {
2176 const Constant *C = CP->getConstVal();
2177 ImmOpnd = CurDAG->getTargetConstantPool(C, MVT::i64,
2183 if (FirstOp == 1) // Store
2184 (void)CurDAG->UpdateNodeOperands(N, N->getOperand(0), ImmOpnd,
2185 Base.getOperand(0), N->getOperand(3));
2187 (void)CurDAG->UpdateNodeOperands(N, ImmOpnd, Base.getOperand(0),
2190 // The add-immediate may now be dead, in which case remove it.
2191 if (Base.getNode()->use_empty())
2192 CurDAG->RemoveDeadNode(Base.getNode());
2197 /// createPPCISelDag - This pass converts a legalized DAG into a
2198 /// PowerPC-specific DAG, ready for instruction scheduling.
2200 FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) {
2201 return new PPCDAGToDAGISel(TM);
2204 static void initializePassOnce(PassRegistry &Registry) {
2205 const char *Name = "PowerPC DAG->DAG Pattern Instruction Selection";
2206 PassInfo *PI = new PassInfo(Name, "ppc-codegen", &SelectionDAGISel::ID,
2207 nullptr, false, false);
2208 Registry.registerPass(*PI, true);
2211 void llvm::initializePPCDAGToDAGISelPass(PassRegistry &Registry) {
2212 CALL_ONCE_INITIALIZATION(initializePassOnce);