1 //===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for PowerPC,
11 // converting from a legalized dag to a PPC dag.
13 //===----------------------------------------------------------------------===//
16 #include "PPCTargetMachine.h"
17 #include "PPCISelLowering.h"
18 #include "PPCHazardRecognizers.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/SSARegMap.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/Constants.h"
27 #include "llvm/GlobalValue.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/MathExtras.h"
36 Statistic<> FrameOff("ppc-codegen", "Number of frame idx offsets collapsed");
38 //===--------------------------------------------------------------------===//
39 /// PPCDAGToDAGISel - PPC specific code to select PPC machine
40 /// instructions for SelectionDAG operations.
42 class PPCDAGToDAGISel : public SelectionDAGISel {
44 PPCTargetLowering PPCLowering;
45 unsigned GlobalBaseReg;
47 PPCDAGToDAGISel(PPCTargetMachine &tm)
48 : SelectionDAGISel(PPCLowering), TM(tm),
49 PPCLowering(*TM.getTargetLowering()) {}
51 virtual bool runOnFunction(Function &Fn) {
52 // Make sure we re-emit a set of the global base reg if necessary
54 SelectionDAGISel::runOnFunction(Fn);
60 /// getI32Imm - Return a target constant with the specified value, of type
62 inline SDOperand getI32Imm(unsigned Imm) {
63 return CurDAG->getTargetConstant(Imm, MVT::i32);
66 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
67 /// base register. Return the virtual register that holds this value.
68 SDOperand getGlobalBaseReg();
70 // Select - Convert the specified operand from a target-independent to a
71 // target-specific node if it hasn't already been changed.
72 void Select(SDOperand &Result, SDOperand Op);
74 SDNode *SelectBitfieldInsert(SDNode *N);
76 /// SelectCC - Select a comparison of the specified values with the
77 /// specified condition code, returning the CR# of the expression.
78 SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
80 /// SelectAddrImm - Returns true if the address N can be represented by
81 /// a base register plus a signed 16-bit displacement [r+imm].
82 bool SelectAddrImm(SDOperand N, SDOperand &Disp, SDOperand &Base);
84 /// SelectAddrIdx - Given the specified addressed, check to see if it can be
85 /// represented as an indexed [r+r] operation. Returns false if it can
86 /// be represented by [r+imm], which are preferred.
87 bool SelectAddrIdx(SDOperand N, SDOperand &Base, SDOperand &Index);
89 /// SelectAddrIdxOnly - Given the specified addressed, force it to be
90 /// represented as an indexed [r+r] operation.
91 bool SelectAddrIdxOnly(SDOperand N, SDOperand &Base, SDOperand &Index);
93 /// SelectAddrImmShift - Returns true if the address N can be represented by
94 /// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable
95 /// for use by STD and friends.
96 bool SelectAddrImmShift(SDOperand N, SDOperand &Disp, SDOperand &Base);
98 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
99 /// inline asm expressions.
100 virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
102 std::vector<SDOperand> &OutOps,
105 switch (ConstraintCode) {
106 default: return true;
108 if (!SelectAddrIdx(Op, Op0, Op1))
109 SelectAddrImm(Op, Op0, Op1);
111 case 'o': // offsetable
112 if (!SelectAddrImm(Op, Op0, Op1)) {
113 Select(Op0, Op); // r+0.
117 case 'v': // not offsetable
118 SelectAddrIdxOnly(Op, Op0, Op1);
122 OutOps.push_back(Op0);
123 OutOps.push_back(Op1);
127 SDOperand BuildSDIVSequence(SDNode *N);
128 SDOperand BuildUDIVSequence(SDNode *N);
130 /// InstructionSelectBasicBlock - This callback is invoked by
131 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
132 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
134 void InsertVRSaveCode(Function &Fn);
136 virtual const char *getPassName() const {
137 return "PowerPC DAG->DAG Pattern Instruction Selection";
140 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
141 /// this target when scheduling the DAG.
142 virtual HazardRecognizer *CreateTargetHazardRecognizer() {
143 // Should use subtarget info to pick the right hazard recognizer. For
144 // now, always return a PPC970 recognizer.
145 const TargetInstrInfo *II = PPCLowering.getTargetMachine().getInstrInfo();
146 assert(II && "No InstrInfo?");
147 return new PPCHazardRecognizer970(*II);
150 // Include the pieces autogenerated from the target description.
151 #include "PPCGenDAGISel.inc"
154 SDOperand SelectSETCC(SDOperand Op);
158 /// InstructionSelectBasicBlock - This callback is invoked by
159 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
160 void PPCDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
163 // The selection process is inherently a bottom-up recursive process (users
164 // select their uses before themselves). Given infinite stack space, we
165 // could just start selecting on the root and traverse the whole graph. In
166 // practice however, this causes us to run out of stack space on large basic
167 // blocks. To avoid this problem, select the entry node, then all its uses,
168 // iteratively instead of recursively.
169 std::vector<SDOperand> Worklist;
170 Worklist.push_back(DAG.getEntryNode());
172 // Note that we can do this in the PPC target (scanning forward across token
173 // chain edges) because no nodes ever get folded across these edges. On a
174 // target like X86 which supports load/modify/store operations, this would
175 // have to be more careful.
176 while (!Worklist.empty()) {
177 SDOperand Node = Worklist.back();
180 // Chose from the least deep of the top two nodes.
181 if (!Worklist.empty() &&
182 Worklist.back().Val->getNodeDepth() < Node.Val->getNodeDepth())
183 std::swap(Worklist.back(), Node);
185 if ((Node.Val->getOpcode() >= ISD::BUILTIN_OP_END &&
186 Node.Val->getOpcode() < PPCISD::FIRST_NUMBER) ||
187 CodeGenMap.count(Node)) continue;
189 for (SDNode::use_iterator UI = Node.Val->use_begin(),
190 E = Node.Val->use_end(); UI != E; ++UI) {
191 // Scan the values. If this use has a value that is a token chain, add it
194 for (unsigned i = 0, e = User->getNumValues(); i != e; ++i)
195 if (User->getValueType(i) == MVT::Other) {
196 Worklist.push_back(SDOperand(User, i));
201 // Finally, legalize this node.
206 // Select target instructions for the DAG.
207 DAG.setRoot(SelectRoot(DAG.getRoot()));
209 DAG.RemoveDeadNodes();
211 // Emit machine code to BB.
212 ScheduleAndEmitDAG(DAG);
215 /// InsertVRSaveCode - Once the entire function has been instruction selected,
216 /// all virtual registers are created and all machine instructions are built,
217 /// check to see if we need to save/restore VRSAVE. If so, do it.
218 void PPCDAGToDAGISel::InsertVRSaveCode(Function &F) {
219 // Check to see if this function uses vector registers, which means we have to
220 // save and restore the VRSAVE register and update it with the regs we use.
222 // In this case, there will be virtual registers of vector type type created
223 // by the scheduler. Detect them now.
224 MachineFunction &Fn = MachineFunction::get(&F);
225 SSARegMap *RegMap = Fn.getSSARegMap();
226 bool HasVectorVReg = false;
227 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
228 e = RegMap->getLastVirtReg()+1; i != e; ++i)
229 if (RegMap->getRegClass(i) == &PPC::VRRCRegClass) {
230 HasVectorVReg = true;
233 if (!HasVectorVReg) return; // nothing to do.
235 // If we have a vector register, we want to emit code into the entry and exit
236 // blocks to save and restore the VRSAVE register. We do this here (instead
237 // of marking all vector instructions as clobbering VRSAVE) for two reasons:
239 // 1. This (trivially) reduces the load on the register allocator, by not
240 // having to represent the live range of the VRSAVE register.
241 // 2. This (more significantly) allows us to create a temporary virtual
242 // register to hold the saved VRSAVE value, allowing this temporary to be
243 // register allocated, instead of forcing it to be spilled to the stack.
245 // Create two vregs - one to hold the VRSAVE register that is live-in to the
246 // function and one for the value after having bits or'd into it.
247 unsigned InVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
248 unsigned UpdatedVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
250 MachineBasicBlock &EntryBB = *Fn.begin();
251 // Emit the following code into the entry block:
252 // InVRSAVE = MFVRSAVE
253 // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
254 // MTVRSAVE UpdatedVRSAVE
255 MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
256 BuildMI(EntryBB, IP, PPC::MFVRSAVE, 0, InVRSAVE);
257 BuildMI(EntryBB, IP, PPC::UPDATE_VRSAVE, 1, UpdatedVRSAVE).addReg(InVRSAVE);
258 BuildMI(EntryBB, IP, PPC::MTVRSAVE, 1).addReg(UpdatedVRSAVE);
260 // Find all return blocks, outputting a restore in each epilog.
261 const TargetInstrInfo &TII = *TM.getInstrInfo();
262 for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
263 if (!BB->empty() && TII.isReturn(BB->back().getOpcode())) {
264 IP = BB->end(); --IP;
266 // Skip over all terminator instructions, which are part of the return
268 MachineBasicBlock::iterator I2 = IP;
269 while (I2 != BB->begin() && TII.isTerminatorInstr((--I2)->getOpcode()))
272 // Emit: MTVRSAVE InVRSave
273 BuildMI(*BB, IP, PPC::MTVRSAVE, 1).addReg(InVRSAVE);
279 /// getGlobalBaseReg - Output the instructions required to put the
280 /// base address to use for accessing globals into a register.
282 SDOperand PPCDAGToDAGISel::getGlobalBaseReg() {
283 if (!GlobalBaseReg) {
284 // Insert the set of GlobalBaseReg into the first MBB of the function
285 MachineBasicBlock &FirstMBB = BB->getParent()->front();
286 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
287 SSARegMap *RegMap = BB->getParent()->getSSARegMap();
288 // FIXME: when we get to LP64, we will need to create the appropriate
289 // type of register here.
290 GlobalBaseReg = RegMap->createVirtualRegister(PPC::GPRCRegisterClass);
291 BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
292 BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg);
294 return CurDAG->getRegister(GlobalBaseReg, MVT::i32);
298 // isIntImmediate - This method tests to see if a constant operand.
299 // If so Imm will receive the 32 bit value.
300 static bool isIntImmediate(SDNode *N, unsigned& Imm) {
301 if (N->getOpcode() == ISD::Constant) {
302 Imm = cast<ConstantSDNode>(N)->getValue();
308 // isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s with
309 // any number of 0s on either side. The 1s are allowed to wrap from LSB to
310 // MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 0x0F0F0000 is
311 // not, since all 1s are not contiguous.
312 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
313 if (isShiftedMask_32(Val)) {
314 // look for the first non-zero bit
315 MB = CountLeadingZeros_32(Val);
316 // look for the first zero bit after the run of ones
317 ME = CountLeadingZeros_32((Val - 1) ^ Val);
320 Val = ~Val; // invert mask
321 if (isShiftedMask_32(Val)) {
322 // effectively look for the first zero bit
323 ME = CountLeadingZeros_32(Val) - 1;
324 // effectively look for the first one bit after the run of zeros
325 MB = CountLeadingZeros_32((Val - 1) ^ Val) + 1;
333 // isRotateAndMask - Returns true if Mask and Shift can be folded into a rotate
334 // and mask opcode and mask operation.
335 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask,
336 unsigned &SH, unsigned &MB, unsigned &ME) {
337 // Don't even go down this path for i64, since different logic will be
338 // necessary for rldicl/rldicr/rldimi.
339 if (N->getValueType(0) != MVT::i32)
343 unsigned Indeterminant = ~0; // bit mask marking indeterminant results
344 unsigned Opcode = N->getOpcode();
345 if (N->getNumOperands() != 2 ||
346 !isIntImmediate(N->getOperand(1).Val, Shift) || (Shift > 31))
349 if (Opcode == ISD::SHL) {
350 // apply shift left to mask if it comes first
351 if (IsShiftMask) Mask = Mask << Shift;
352 // determine which bits are made indeterminant by shift
353 Indeterminant = ~(0xFFFFFFFFu << Shift);
354 } else if (Opcode == ISD::SRL) {
355 // apply shift right to mask if it comes first
356 if (IsShiftMask) Mask = Mask >> Shift;
357 // determine which bits are made indeterminant by shift
358 Indeterminant = ~(0xFFFFFFFFu >> Shift);
359 // adjust for the left rotate
365 // if the mask doesn't intersect any Indeterminant bits
366 if (Mask && !(Mask & Indeterminant)) {
368 // make sure the mask is still a mask (wrap arounds may not be)
369 return isRunOfOnes(Mask, MB, ME);
374 // isOpcWithIntImmediate - This method tests to see if the node is a specific
375 // opcode and that it has a immediate integer right operand.
376 // If so Imm will receive the 32 bit value.
377 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
378 return N->getOpcode() == Opc && isIntImmediate(N->getOperand(1).Val, Imm);
381 // isIntImmediate - This method tests to see if a constant operand.
382 // If so Imm will receive the 32 bit value.
383 static bool isIntImmediate(SDOperand N, unsigned& Imm) {
384 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
385 Imm = (unsigned)CN->getSignExtended();
391 /// SelectBitfieldInsert - turn an or of two masked values into
392 /// the rotate left word immediate then mask insert (rlwimi) instruction.
393 SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
394 SDOperand Op0 = N->getOperand(0);
395 SDOperand Op1 = N->getOperand(1);
397 uint64_t LKZ, LKO, RKZ, RKO;
398 TLI.ComputeMaskedBits(Op0, 0xFFFFFFFFULL, LKZ, LKO);
399 TLI.ComputeMaskedBits(Op1, 0xFFFFFFFFULL, RKZ, RKO);
401 unsigned TargetMask = LKZ;
402 unsigned InsertMask = RKZ;
404 if ((TargetMask | InsertMask) == 0xFFFFFFFF) {
405 unsigned Op0Opc = Op0.getOpcode();
406 unsigned Op1Opc = Op1.getOpcode();
407 unsigned Value, SH = 0;
408 TargetMask = ~TargetMask;
409 InsertMask = ~InsertMask;
411 // If the LHS has a foldable shift and the RHS does not, then swap it to the
412 // RHS so that we can fold the shift into the insert.
413 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
414 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
415 Op0.getOperand(0).getOpcode() == ISD::SRL) {
416 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
417 Op1.getOperand(0).getOpcode() != ISD::SRL) {
419 std::swap(Op0Opc, Op1Opc);
420 std::swap(TargetMask, InsertMask);
423 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
424 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
425 Op1.getOperand(0).getOpcode() != ISD::SRL) {
427 std::swap(Op0Opc, Op1Opc);
428 std::swap(TargetMask, InsertMask);
433 if (InsertMask && isRunOfOnes(InsertMask, MB, ME)) {
434 SDOperand Tmp1, Tmp2, Tmp3;
435 bool DisjointMask = (TargetMask ^ InsertMask) == 0xFFFFFFFF;
437 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
438 isIntImmediate(Op1.getOperand(1), Value)) {
439 Op1 = Op1.getOperand(0);
440 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value;
442 if (Op1Opc == ISD::AND) {
443 unsigned SHOpc = Op1.getOperand(0).getOpcode();
444 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) &&
445 isIntImmediate(Op1.getOperand(0).getOperand(1), Value)) {
446 Op1 = Op1.getOperand(0).getOperand(0);
447 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value;
449 Op1 = Op1.getOperand(0);
453 Tmp3 = (Op0Opc == ISD::AND && DisjointMask) ? Op0.getOperand(0) : Op0;
457 return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Tmp1, Tmp2,
458 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
464 /// SelectAddrImm - Returns true if the address N can be represented by
465 /// a base register plus a signed 16-bit displacement [r+imm].
466 bool PPCDAGToDAGISel::SelectAddrImm(SDOperand N, SDOperand &Disp,
468 // If this can be more profitably realized as r+r, fail.
469 if (SelectAddrIdx(N, Disp, Base))
472 if (N.getOpcode() == ISD::ADD) {
474 if (isIntImmediate(N.getOperand(1), imm) && isInt16(imm)) {
475 Disp = getI32Imm(imm & 0xFFFF);
476 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
477 Base = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
479 Base = N.getOperand(0);
481 return true; // [r+i]
482 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
483 // Match LOAD (ADD (X, Lo(G))).
484 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
485 && "Cannot handle constant offsets yet!");
486 Disp = N.getOperand(1).getOperand(0); // The global address.
487 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
488 Disp.getOpcode() == ISD::TargetConstantPool ||
489 Disp.getOpcode() == ISD::TargetJumpTable);
490 Base = N.getOperand(0);
491 return true; // [&g+r]
493 } else if (N.getOpcode() == ISD::OR) {
495 if (isIntImmediate(N.getOperand(1), imm) && isInt16(imm)) {
496 // If this is an or of disjoint bitfields, we can codegen this as an add
497 // (for better address arithmetic) if the LHS and RHS of the OR are
498 // provably disjoint.
499 uint64_t LHSKnownZero, LHSKnownOne;
500 PPCLowering.ComputeMaskedBits(N.getOperand(0), ~0U,
501 LHSKnownZero, LHSKnownOne);
502 if ((LHSKnownZero|~imm) == ~0U) {
503 // If all of the bits are known zero on the LHS or RHS, the add won't
505 Base = N.getOperand(0);
506 Disp = getI32Imm(imm & 0xFFFF);
510 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
511 // Loading from a constant address.
512 int Addr = (int)CN->getValue();
514 // If this address fits entirely in a 16-bit sext immediate field, codegen
516 if (Addr == (short)Addr) {
517 Disp = getI32Imm(Addr);
518 Base = CurDAG->getRegister(PPC::R0, MVT::i32);
522 // Otherwise, break this down into an LIS + disp.
523 Disp = getI32Imm((short)Addr);
524 Base = CurDAG->getConstant(Addr - (signed short)Addr, MVT::i32);
529 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
530 Base = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
533 return true; // [r+0]
536 /// SelectAddrIdx - Given the specified addressed, check to see if it can be
537 /// represented as an indexed [r+r] operation. Returns false if it can
538 /// be represented by [r+imm], which are preferred.
539 bool PPCDAGToDAGISel::SelectAddrIdx(SDOperand N, SDOperand &Base,
542 if (N.getOpcode() == ISD::ADD) {
543 if (isIntImmediate(N.getOperand(1), imm) && isInt16(imm))
545 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
548 Base = N.getOperand(0);
549 Index = N.getOperand(1);
551 } else if (N.getOpcode() == ISD::OR) {
552 if (isIntImmediate(N.getOperand(1), imm) && isInt16(imm))
553 return false; // r+i can fold it if we can.
555 // If this is an or of disjoint bitfields, we can codegen this as an add
556 // (for better address arithmetic) if the LHS and RHS of the OR are provably
558 uint64_t LHSKnownZero, LHSKnownOne;
559 uint64_t RHSKnownZero, RHSKnownOne;
560 PPCLowering.ComputeMaskedBits(N.getOperand(0), ~0U,
561 LHSKnownZero, LHSKnownOne);
564 PPCLowering.ComputeMaskedBits(N.getOperand(1), ~0U,
565 RHSKnownZero, RHSKnownOne);
566 // If all of the bits are known zero on the LHS or RHS, the add won't
568 if ((LHSKnownZero | RHSKnownZero) == ~0U) {
569 Base = N.getOperand(0);
570 Index = N.getOperand(1);
579 /// SelectAddrIdxOnly - Given the specified addressed, force it to be
580 /// represented as an indexed [r+r] operation.
581 bool PPCDAGToDAGISel::SelectAddrIdxOnly(SDOperand N, SDOperand &Base,
583 // Check to see if we can easily represent this as an [r+r] address. This
584 // will fail if it thinks that the address is more profitably represented as
585 // reg+imm, e.g. where imm = 0.
586 if (SelectAddrIdx(N, Base, Index))
589 // If the operand is an addition, always emit this as [r+r], since this is
590 // better (for code size, and execution, as the memop does the add for free)
591 // than emitting an explicit add.
592 if (N.getOpcode() == ISD::ADD) {
593 Base = N.getOperand(0);
594 Index = N.getOperand(1);
598 // Otherwise, do it the hard way, using R0 as the base register.
599 Base = CurDAG->getRegister(PPC::R0, MVT::i32);
604 /// SelectAddrImmShift - Returns true if the address N can be represented by
605 /// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable
606 /// for use by STD and friends.
607 bool PPCDAGToDAGISel::SelectAddrImmShift(SDOperand N, SDOperand &Disp,
609 // If this can be more profitably realized as r+r, fail.
610 if (SelectAddrIdx(N, Disp, Base))
613 if (N.getOpcode() == ISD::ADD) {
615 if (isIntImmediate(N.getOperand(1), imm) && isInt16(imm) &&
617 Disp = getI32Imm((imm & 0xFFFF) >> 2);
618 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
619 Base = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
621 Base = N.getOperand(0);
623 return true; // [r+i]
624 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
625 // Match LOAD (ADD (X, Lo(G))).
626 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
627 && "Cannot handle constant offsets yet!");
628 Disp = N.getOperand(1).getOperand(0); // The global address.
629 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
630 Disp.getOpcode() == ISD::TargetConstantPool ||
631 Disp.getOpcode() == ISD::TargetJumpTable);
632 Base = N.getOperand(0);
633 return true; // [&g+r]
635 } else if (N.getOpcode() == ISD::OR) {
637 if (isIntImmediate(N.getOperand(1), imm) && isInt16(imm) &&
639 // If this is an or of disjoint bitfields, we can codegen this as an add
640 // (for better address arithmetic) if the LHS and RHS of the OR are
641 // provably disjoint.
642 uint64_t LHSKnownZero, LHSKnownOne;
643 PPCLowering.ComputeMaskedBits(N.getOperand(0), ~0U,
644 LHSKnownZero, LHSKnownOne);
645 if ((LHSKnownZero|~imm) == ~0U) {
646 // If all of the bits are known zero on the LHS or RHS, the add won't
648 Base = N.getOperand(0);
649 Disp = getI32Imm((imm & 0xFFFF) >> 2);
653 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
654 // Loading from a constant address.
655 int Addr = (int)CN->getValue();
656 if ((Addr & 3) == 0) {
657 // If this address fits entirely in a 16-bit sext immediate field, codegen
659 if (Addr == (short)Addr) {
660 Disp = getI32Imm(Addr >> 2);
661 Base = CurDAG->getRegister(PPC::R0, MVT::i32);
665 // Otherwise, break this down into an LIS + disp.
666 Disp = getI32Imm((short)Addr >> 2);
667 Base = CurDAG->getConstant(Addr - (signed short)Addr, MVT::i32);
673 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
674 Base = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
677 return true; // [r+0]
681 /// SelectCC - Select a comparison of the specified values with the specified
682 /// condition code, returning the CR# of the expression.
683 SDOperand PPCDAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS,
685 // Always select the LHS.
688 // Use U to determine whether the SETCC immediate range is signed or not.
689 if (MVT::isInteger(LHS.getValueType())) {
690 bool U = ISD::isUnsignedIntSetCC(CC);
692 if (isIntImmediate(RHS, Imm) &&
693 ((U && isUInt16(Imm)) || (!U && isInt16(Imm))))
694 return SDOperand(CurDAG->getTargetNode(U ? PPC::CMPLWI : PPC::CMPWI,
695 MVT::i32, LHS, getI32Imm(Imm & 0xFFFF)), 0);
697 return SDOperand(CurDAG->getTargetNode(U ? PPC::CMPLW : PPC::CMPW, MVT::i32,
699 } else if (LHS.getValueType() == MVT::f32) {
701 return SDOperand(CurDAG->getTargetNode(PPC::FCMPUS, MVT::i32, LHS, RHS), 0);
704 return SDOperand(CurDAG->getTargetNode(PPC::FCMPUD, MVT::i32, LHS, RHS), 0);
708 /// getBCCForSetCC - Returns the PowerPC condition branch mnemonic corresponding
710 static unsigned getBCCForSetCC(ISD::CondCode CC) {
712 default: assert(0 && "Unknown condition!"); abort();
713 case ISD::SETOEQ: // FIXME: This is incorrect see PR642.
714 case ISD::SETEQ: return PPC::BEQ;
715 case ISD::SETONE: // FIXME: This is incorrect see PR642.
716 case ISD::SETNE: return PPC::BNE;
717 case ISD::SETOLT: // FIXME: This is incorrect see PR642.
719 case ISD::SETLT: return PPC::BLT;
720 case ISD::SETOLE: // FIXME: This is incorrect see PR642.
722 case ISD::SETLE: return PPC::BLE;
723 case ISD::SETOGT: // FIXME: This is incorrect see PR642.
725 case ISD::SETGT: return PPC::BGT;
726 case ISD::SETOGE: // FIXME: This is incorrect see PR642.
728 case ISD::SETGE: return PPC::BGE;
730 case ISD::SETO: return PPC::BUN;
731 case ISD::SETUO: return PPC::BNU;
736 /// getCRIdxForSetCC - Return the index of the condition register field
737 /// associated with the SetCC condition, and whether or not the field is
738 /// treated as inverted. That is, lt = 0; ge = 0 inverted.
739 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool& Inv) {
741 default: assert(0 && "Unknown condition!"); abort();
742 case ISD::SETOLT: // FIXME: This is incorrect see PR642.
744 case ISD::SETLT: Inv = false; return 0;
745 case ISD::SETOGE: // FIXME: This is incorrect see PR642.
747 case ISD::SETGE: Inv = true; return 0;
748 case ISD::SETOGT: // FIXME: This is incorrect see PR642.
750 case ISD::SETGT: Inv = false; return 1;
751 case ISD::SETOLE: // FIXME: This is incorrect see PR642.
753 case ISD::SETLE: Inv = true; return 1;
754 case ISD::SETOEQ: // FIXME: This is incorrect see PR642.
755 case ISD::SETEQ: Inv = false; return 2;
756 case ISD::SETONE: // FIXME: This is incorrect see PR642.
757 case ISD::SETNE: Inv = true; return 2;
758 case ISD::SETO: Inv = true; return 3;
759 case ISD::SETUO: Inv = false; return 3;
764 SDOperand PPCDAGToDAGISel::SelectSETCC(SDOperand Op) {
767 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
768 if (isIntImmediate(N->getOperand(1), Imm)) {
769 // We can codegen setcc op, imm very efficiently compared to a brcond.
770 // Check for those cases here.
774 Select(Op, N->getOperand(0));
778 Op = SDOperand(CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op), 0);
779 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(27),
780 getI32Imm(5), getI32Imm(31));
783 SDOperand(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
784 Op, getI32Imm(~0U)), 0);
785 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
789 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(1),
790 getI32Imm(31), getI32Imm(31));
793 SDOperand(CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op), 0);
794 T = SDOperand(CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op), 0);
795 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, T, getI32Imm(1),
796 getI32Imm(31), getI32Imm(31));
799 } else if (Imm == ~0U) { // setcc op, -1
801 Select(Op, N->getOperand(0));
805 Op = SDOperand(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
806 Op, getI32Imm(1)), 0);
807 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
808 SDOperand(CurDAG->getTargetNode(PPC::LI, MVT::i32,
812 Op = SDOperand(CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op), 0);
813 SDNode *AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
815 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDOperand(AD, 0),
816 Op, SDOperand(AD, 1));
819 SDOperand AD = SDOperand(CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op,
821 SDOperand AN = SDOperand(CurDAG->getTargetNode(PPC::AND, MVT::i32, AD,
823 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, AN, getI32Imm(1),
824 getI32Imm(31), getI32Imm(31));
827 Op = SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Op,
828 getI32Imm(1), getI32Imm(31),
830 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, getI32Imm(1));
836 unsigned Idx = getCRIdxForSetCC(CC, Inv);
837 SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
840 // Force the ccreg into CR7.
841 SDOperand CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
843 SDOperand InFlag(0, 0); // Null incoming flag value.
844 CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), CR7Reg, CCReg,
847 if (TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor())
848 IntCR = SDOperand(CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg,
851 IntCR = SDOperand(CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg), 0);
854 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, IntCR,
855 getI32Imm((32-(3-Idx)) & 31),
856 getI32Imm(31), getI32Imm(31));
859 SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, IntCR,
860 getI32Imm((32-(3-Idx)) & 31),
861 getI32Imm(31),getI32Imm(31)), 0);
862 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
867 // Select - Convert the specified operand from a target-independent to a
868 // target-specific node if it hasn't already been changed.
869 void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
871 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
872 N->getOpcode() < PPCISD::FIRST_NUMBER) {
874 return; // Already selected.
877 // If this has already been converted, use it.
878 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
879 if (CGMI != CodeGenMap.end()) {
880 Result = CGMI->second;
884 switch (N->getOpcode()) {
887 Result = SelectSETCC(Op);
889 case PPCISD::GlobalBaseReg:
890 Result = getGlobalBaseReg();
893 case ISD::FrameIndex: {
894 int FI = cast<FrameIndexSDNode>(N)->getIndex();
895 if (N->hasOneUse()) {
896 Result = CurDAG->SelectNodeTo(N, PPC::ADDI, MVT::i32,
897 CurDAG->getTargetFrameIndex(FI, MVT::i32),
901 Result = CodeGenMap[Op] =
902 SDOperand(CurDAG->getTargetNode(PPC::ADDI, MVT::i32,
903 CurDAG->getTargetFrameIndex(FI, MVT::i32),
910 Select(InFlag, N->getOperand(1));
911 // Use MFOCRF if supported.
912 if (TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor())
913 Result = SDOperand(CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32,
914 N->getOperand(0), InFlag), 0);
916 Result = SDOperand(CurDAG->getTargetNode(PPC::MFCR, MVT::i32, InFlag), 0);
917 CodeGenMap[Op] = Result;
922 // FIXME: since this depends on the setting of the carry flag from the srawi
923 // we should really be making notes about that for the scheduler.
924 // FIXME: It sure would be nice if we could cheaply recognize the
925 // srl/add/sra pattern the dag combiner will generate for this as
926 // sra/addze rather than having to handle sdiv ourselves. oh well.
928 if (isIntImmediate(N->getOperand(1), Imm)) {
930 Select(N0, N->getOperand(0));
931 if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
933 CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
934 N0, getI32Imm(Log2_32(Imm)));
935 Result = CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
936 SDOperand(Op, 0), SDOperand(Op, 1));
937 } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
939 CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
940 N0, getI32Imm(Log2_32(-Imm)));
942 SDOperand(CurDAG->getTargetNode(PPC::ADDZE, MVT::i32,
943 SDOperand(Op, 0), SDOperand(Op, 1)),
945 Result = CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
950 // Other cases are autogenerated.
955 // If this is an and of a value rotated between 0 and 31 bits and then and'd
956 // with a mask, emit rlwinm
957 if (isIntImmediate(N->getOperand(1), Imm) && (isShiftedMask_32(Imm) ||
958 isShiftedMask_32(~Imm))) {
961 if (isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB, ME)) {
962 Select(Val, N->getOperand(0).getOperand(0));
963 } else if (Imm == 0) {
964 // AND X, 0 -> 0, not "rlwinm 32".
965 Select(Result, N->getOperand(1));
968 Select(Val, N->getOperand(0));
969 isRunOfOnes(Imm, MB, ME);
972 Result = CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Val,
973 getI32Imm(SH), getI32Imm(MB),
977 // ISD::OR doesn't get all the bitfield insertion fun.
978 // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert
979 if (isIntImmediate(N->getOperand(1), Imm) &&
980 N->getOperand(0).getOpcode() == ISD::OR &&
981 isIntImmediate(N->getOperand(0).getOperand(1), Imm2)) {
984 if (isRunOfOnes(Imm, MB, ME)) {
985 SDOperand Tmp1, Tmp2;
986 Select(Tmp1, N->getOperand(0).getOperand(0));
987 Select(Tmp2, N->getOperand(0).getOperand(1));
988 Result = SDOperand(CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32,
990 getI32Imm(0), getI32Imm(MB),
996 // Other cases are autogenerated.
1000 if (SDNode *I = SelectBitfieldInsert(N)) {
1001 Result = CodeGenMap[Op] = SDOperand(I, 0);
1005 // Other cases are autogenerated.
1008 unsigned Imm, SH, MB, ME;
1009 if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
1010 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
1012 Select(Val, N->getOperand(0).getOperand(0));
1013 Result = CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32,
1014 Val, getI32Imm(SH), getI32Imm(MB),
1019 // Other cases are autogenerated.
1023 unsigned Imm, SH, MB, ME;
1024 if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
1025 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
1027 Select(Val, N->getOperand(0).getOperand(0));
1028 Result = CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32,
1029 Val, getI32Imm(SH), getI32Imm(MB),
1034 // Other cases are autogenerated.
1037 case ISD::SELECT_CC: {
1038 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1040 // handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
1041 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1042 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
1043 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
1044 if (N1C->isNullValue() && N3C->isNullValue() &&
1045 N2C->getValue() == 1ULL && CC == ISD::SETNE) {
1047 Select(LHS, N->getOperand(0));
1049 CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
1050 LHS, getI32Imm(~0U));
1051 Result = CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
1052 SDOperand(Tmp, 0), LHS,
1057 SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
1058 unsigned BROpc = getBCCForSetCC(CC);
1060 bool isFP = MVT::isFloatingPoint(N->getValueType(0));
1061 unsigned SelectCCOp;
1062 if (MVT::isInteger(N->getValueType(0)))
1063 SelectCCOp = PPC::SELECT_CC_Int;
1064 else if (N->getValueType(0) == MVT::f32)
1065 SelectCCOp = PPC::SELECT_CC_F4;
1066 else if (N->getValueType(0) == MVT::f64)
1067 SelectCCOp = PPC::SELECT_CC_F8;
1069 SelectCCOp = PPC::SELECT_CC_VRRC;
1072 Select(N2, N->getOperand(2));
1073 Select(N3, N->getOperand(3));
1074 Result = CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), CCReg,
1075 N2, N3, getI32Imm(BROpc));
1080 Select(Chain, N->getOperand(0));
1081 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
1082 SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC);
1083 Result = CurDAG->SelectNodeTo(N, PPC::COND_BRANCH, MVT::Other,
1084 CondCode, getI32Imm(getBCCForSetCC(CC)),
1085 N->getOperand(4), Chain);
1089 SDOperand Chain, Target;
1090 Select(Chain, N->getOperand(0));
1091 Select(Target,N->getOperand(1));
1092 Chain = SDOperand(CurDAG->getTargetNode(PPC::MTCTR, MVT::Other, Target,
1094 Result = CurDAG->SelectNodeTo(N, PPC::BCTR, MVT::Other, Chain);
1099 SelectCode(Result, Op);
1103 /// createPPCISelDag - This pass converts a legalized DAG into a
1104 /// PowerPC-specific DAG, ready for instruction scheduling.
1106 FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) {
1107 return new PPCDAGToDAGISel(TM);