1 //===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for PowerPC,
11 // converting from a legalized dag to a PPC dag.
13 //===----------------------------------------------------------------------===//
16 #include "PPCTargetMachine.h"
17 #include "PPCISelLowering.h"
18 #include "PPCHazardRecognizers.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/SSARegMap.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/Constants.h"
27 #include "llvm/GlobalValue.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/MathExtras.h"
31 #include "llvm/Support/Visibility.h"
38 Statistic<> FrameOff("ppc-codegen", "Number of frame idx offsets collapsed");
40 //===--------------------------------------------------------------------===//
41 /// PPCDAGToDAGISel - PPC specific code to select PPC machine
42 /// instructions for SelectionDAG operations.
44 class VISIBILITY_HIDDEN PPCDAGToDAGISel : public SelectionDAGISel {
46 PPCTargetLowering PPCLowering;
47 unsigned GlobalBaseReg;
49 PPCDAGToDAGISel(PPCTargetMachine &tm)
50 : SelectionDAGISel(PPCLowering), TM(tm),
51 PPCLowering(*TM.getTargetLowering()) {}
53 virtual bool runOnFunction(Function &Fn) {
54 // Make sure we re-emit a set of the global base reg if necessary
56 SelectionDAGISel::runOnFunction(Fn);
62 /// getI32Imm - Return a target constant with the specified value, of type
64 inline SDOperand getI32Imm(unsigned Imm) {
65 return CurDAG->getTargetConstant(Imm, MVT::i32);
68 /// getI64Imm - Return a target constant with the specified value, of type
70 inline SDOperand getI64Imm(uint64_t Imm) {
71 return CurDAG->getTargetConstant(Imm, MVT::i64);
74 /// getSmallIPtrImm - Return a target constant of pointer type.
75 inline SDOperand getSmallIPtrImm(unsigned Imm) {
76 return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy());
80 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
81 /// base register. Return the virtual register that holds this value.
82 SDOperand getGlobalBaseReg();
84 // Select - Convert the specified operand from a target-independent to a
85 // target-specific node if it hasn't already been changed.
86 SDNode *Select(SDOperand &Result, SDOperand Op);
88 SDNode *SelectBitfieldInsert(SDNode *N);
90 /// SelectCC - Select a comparison of the specified values with the
91 /// specified condition code, returning the CR# of the expression.
92 SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
94 /// SelectAddrImm - Returns true if the address N can be represented by
95 /// a base register plus a signed 16-bit displacement [r+imm].
96 bool SelectAddrImm(SDOperand N, SDOperand &Disp, SDOperand &Base);
98 /// SelectAddrIdx - Given the specified addressed, check to see if it can be
99 /// represented as an indexed [r+r] operation. Returns false if it can
100 /// be represented by [r+imm], which are preferred.
101 bool SelectAddrIdx(SDOperand N, SDOperand &Base, SDOperand &Index);
103 /// SelectAddrIdxOnly - Given the specified addressed, force it to be
104 /// represented as an indexed [r+r] operation.
105 bool SelectAddrIdxOnly(SDOperand N, SDOperand &Base, SDOperand &Index);
107 /// SelectAddrImmShift - Returns true if the address N can be represented by
108 /// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable
109 /// for use by STD and friends.
110 bool SelectAddrImmShift(SDOperand N, SDOperand &Disp, SDOperand &Base);
112 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
113 /// inline asm expressions.
114 virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
116 std::vector<SDOperand> &OutOps,
119 switch (ConstraintCode) {
120 default: return true;
122 if (!SelectAddrIdx(Op, Op0, Op1))
123 SelectAddrImm(Op, Op0, Op1);
125 case 'o': // offsetable
126 if (!SelectAddrImm(Op, Op0, Op1)) {
127 AddToQueue(Op0, Op); // r+0.
128 Op1 = getSmallIPtrImm(0);
131 case 'v': // not offsetable
132 SelectAddrIdxOnly(Op, Op0, Op1);
136 OutOps.push_back(Op0);
137 OutOps.push_back(Op1);
141 SDOperand BuildSDIVSequence(SDNode *N);
142 SDOperand BuildUDIVSequence(SDNode *N);
144 /// InstructionSelectBasicBlock - This callback is invoked by
145 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
146 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
148 void InsertVRSaveCode(Function &Fn);
150 virtual const char *getPassName() const {
151 return "PowerPC DAG->DAG Pattern Instruction Selection";
154 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
155 /// this target when scheduling the DAG.
156 virtual HazardRecognizer *CreateTargetHazardRecognizer() {
157 // Should use subtarget info to pick the right hazard recognizer. For
158 // now, always return a PPC970 recognizer.
159 const TargetInstrInfo *II = PPCLowering.getTargetMachine().getInstrInfo();
160 assert(II && "No InstrInfo?");
161 return new PPCHazardRecognizer970(*II);
164 // Include the pieces autogenerated from the target description.
165 #include "PPCGenDAGISel.inc"
168 SDNode *SelectSETCC(SDOperand Op);
169 SDNode *MySelect_PPCbctrl(SDOperand N);
170 SDNode *MySelect_PPCcall(SDOperand N);
174 /// InstructionSelectBasicBlock - This callback is invoked by
175 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
176 void PPCDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
179 // Select target instructions for the DAG.
180 DAG.setRoot(SelectRoot(DAG.getRoot()));
181 DAG.RemoveDeadNodes();
183 // Emit machine code to BB.
184 ScheduleAndEmitDAG(DAG);
187 /// InsertVRSaveCode - Once the entire function has been instruction selected,
188 /// all virtual registers are created and all machine instructions are built,
189 /// check to see if we need to save/restore VRSAVE. If so, do it.
190 void PPCDAGToDAGISel::InsertVRSaveCode(Function &F) {
191 // Check to see if this function uses vector registers, which means we have to
192 // save and restore the VRSAVE register and update it with the regs we use.
194 // In this case, there will be virtual registers of vector type type created
195 // by the scheduler. Detect them now.
196 MachineFunction &Fn = MachineFunction::get(&F);
197 SSARegMap *RegMap = Fn.getSSARegMap();
198 bool HasVectorVReg = false;
199 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
200 e = RegMap->getLastVirtReg()+1; i != e; ++i)
201 if (RegMap->getRegClass(i) == &PPC::VRRCRegClass) {
202 HasVectorVReg = true;
205 if (!HasVectorVReg) return; // nothing to do.
207 // If we have a vector register, we want to emit code into the entry and exit
208 // blocks to save and restore the VRSAVE register. We do this here (instead
209 // of marking all vector instructions as clobbering VRSAVE) for two reasons:
211 // 1. This (trivially) reduces the load on the register allocator, by not
212 // having to represent the live range of the VRSAVE register.
213 // 2. This (more significantly) allows us to create a temporary virtual
214 // register to hold the saved VRSAVE value, allowing this temporary to be
215 // register allocated, instead of forcing it to be spilled to the stack.
217 // Create two vregs - one to hold the VRSAVE register that is live-in to the
218 // function and one for the value after having bits or'd into it.
219 unsigned InVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
220 unsigned UpdatedVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
222 MachineBasicBlock &EntryBB = *Fn.begin();
223 // Emit the following code into the entry block:
224 // InVRSAVE = MFVRSAVE
225 // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
226 // MTVRSAVE UpdatedVRSAVE
227 MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
228 BuildMI(EntryBB, IP, PPC::MFVRSAVE, 0, InVRSAVE);
229 BuildMI(EntryBB, IP, PPC::UPDATE_VRSAVE, 1, UpdatedVRSAVE).addReg(InVRSAVE);
230 BuildMI(EntryBB, IP, PPC::MTVRSAVE, 1).addReg(UpdatedVRSAVE);
232 // Find all return blocks, outputting a restore in each epilog.
233 const TargetInstrInfo &TII = *TM.getInstrInfo();
234 for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
235 if (!BB->empty() && TII.isReturn(BB->back().getOpcode())) {
236 IP = BB->end(); --IP;
238 // Skip over all terminator instructions, which are part of the return
240 MachineBasicBlock::iterator I2 = IP;
241 while (I2 != BB->begin() && TII.isTerminatorInstr((--I2)->getOpcode()))
244 // Emit: MTVRSAVE InVRSave
245 BuildMI(*BB, IP, PPC::MTVRSAVE, 1).addReg(InVRSAVE);
251 /// getGlobalBaseReg - Output the instructions required to put the
252 /// base address to use for accessing globals into a register.
254 SDOperand PPCDAGToDAGISel::getGlobalBaseReg() {
255 if (!GlobalBaseReg) {
256 // Insert the set of GlobalBaseReg into the first MBB of the function
257 MachineBasicBlock &FirstMBB = BB->getParent()->front();
258 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
259 SSARegMap *RegMap = BB->getParent()->getSSARegMap();
261 if (PPCLowering.getPointerTy() == MVT::i32)
262 GlobalBaseReg = RegMap->createVirtualRegister(PPC::GPRCRegisterClass);
264 GlobalBaseReg = RegMap->createVirtualRegister(PPC::G8RCRegisterClass);
266 BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
267 BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg);
269 return CurDAG->getRegister(GlobalBaseReg, PPCLowering.getPointerTy());
272 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
273 /// or 64-bit immediate, and if the value can be accurately represented as a
274 /// sign extension from a 16-bit value. If so, this returns true and the
276 static bool isIntS16Immediate(SDNode *N, short &Imm) {
277 if (N->getOpcode() != ISD::Constant)
280 Imm = (short)cast<ConstantSDNode>(N)->getValue();
281 if (N->getValueType(0) == MVT::i32)
282 return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue();
284 return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue();
287 static bool isIntS16Immediate(SDOperand Op, short &Imm) {
288 return isIntS16Immediate(Op.Val, Imm);
292 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
293 /// operand. If so Imm will receive the 32-bit value.
294 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
295 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
296 Imm = cast<ConstantSDNode>(N)->getValue();
302 /// isInt64Immediate - This method tests to see if the node is a 64-bit constant
303 /// operand. If so Imm will receive the 64-bit value.
304 static bool isInt64Immediate(SDNode *N, uint64_t &Imm) {
305 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
306 Imm = cast<ConstantSDNode>(N)->getValue();
312 // isInt32Immediate - This method tests to see if a constant operand.
313 // If so Imm will receive the 32 bit value.
314 static bool isInt32Immediate(SDOperand N, unsigned &Imm) {
315 return isInt32Immediate(N.Val, Imm);
319 // isOpcWithIntImmediate - This method tests to see if the node is a specific
320 // opcode and that it has a immediate integer right operand.
321 // If so Imm will receive the 32 bit value.
322 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
323 return N->getOpcode() == Opc && isInt32Immediate(N->getOperand(1).Val, Imm);
327 // isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s with
328 // any number of 0s on either side. The 1s are allowed to wrap from LSB to
329 // MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 0x0F0F0000 is
330 // not, since all 1s are not contiguous.
331 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
332 if (isShiftedMask_32(Val)) {
333 // look for the first non-zero bit
334 MB = CountLeadingZeros_32(Val);
335 // look for the first zero bit after the run of ones
336 ME = CountLeadingZeros_32((Val - 1) ^ Val);
339 Val = ~Val; // invert mask
340 if (isShiftedMask_32(Val)) {
341 // effectively look for the first zero bit
342 ME = CountLeadingZeros_32(Val) - 1;
343 // effectively look for the first one bit after the run of zeros
344 MB = CountLeadingZeros_32((Val - 1) ^ Val) + 1;
352 // isRotateAndMask - Returns true if Mask and Shift can be folded into a rotate
353 // and mask opcode and mask operation.
354 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask,
355 unsigned &SH, unsigned &MB, unsigned &ME) {
356 // Don't even go down this path for i64, since different logic will be
357 // necessary for rldicl/rldicr/rldimi.
358 if (N->getValueType(0) != MVT::i32)
362 unsigned Indeterminant = ~0; // bit mask marking indeterminant results
363 unsigned Opcode = N->getOpcode();
364 if (N->getNumOperands() != 2 ||
365 !isInt32Immediate(N->getOperand(1).Val, Shift) || (Shift > 31))
368 if (Opcode == ISD::SHL) {
369 // apply shift left to mask if it comes first
370 if (IsShiftMask) Mask = Mask << Shift;
371 // determine which bits are made indeterminant by shift
372 Indeterminant = ~(0xFFFFFFFFu << Shift);
373 } else if (Opcode == ISD::SRL) {
374 // apply shift right to mask if it comes first
375 if (IsShiftMask) Mask = Mask >> Shift;
376 // determine which bits are made indeterminant by shift
377 Indeterminant = ~(0xFFFFFFFFu >> Shift);
378 // adjust for the left rotate
384 // if the mask doesn't intersect any Indeterminant bits
385 if (Mask && !(Mask & Indeterminant)) {
387 // make sure the mask is still a mask (wrap arounds may not be)
388 return isRunOfOnes(Mask, MB, ME);
393 /// SelectBitfieldInsert - turn an or of two masked values into
394 /// the rotate left word immediate then mask insert (rlwimi) instruction.
395 SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
396 SDOperand Op0 = N->getOperand(0);
397 SDOperand Op1 = N->getOperand(1);
399 uint64_t LKZ, LKO, RKZ, RKO;
400 TLI.ComputeMaskedBits(Op0, 0xFFFFFFFFULL, LKZ, LKO);
401 TLI.ComputeMaskedBits(Op1, 0xFFFFFFFFULL, RKZ, RKO);
403 unsigned TargetMask = LKZ;
404 unsigned InsertMask = RKZ;
406 if ((TargetMask | InsertMask) == 0xFFFFFFFF) {
407 unsigned Op0Opc = Op0.getOpcode();
408 unsigned Op1Opc = Op1.getOpcode();
409 unsigned Value, SH = 0;
410 TargetMask = ~TargetMask;
411 InsertMask = ~InsertMask;
413 // If the LHS has a foldable shift and the RHS does not, then swap it to the
414 // RHS so that we can fold the shift into the insert.
415 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
416 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
417 Op0.getOperand(0).getOpcode() == ISD::SRL) {
418 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
419 Op1.getOperand(0).getOpcode() != ISD::SRL) {
421 std::swap(Op0Opc, Op1Opc);
422 std::swap(TargetMask, InsertMask);
425 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
426 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
427 Op1.getOperand(0).getOpcode() != ISD::SRL) {
429 std::swap(Op0Opc, Op1Opc);
430 std::swap(TargetMask, InsertMask);
435 if (InsertMask && isRunOfOnes(InsertMask, MB, ME)) {
436 SDOperand Tmp1, Tmp2, Tmp3;
437 bool DisjointMask = (TargetMask ^ InsertMask) == 0xFFFFFFFF;
439 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
440 isInt32Immediate(Op1.getOperand(1), Value)) {
441 Op1 = Op1.getOperand(0);
442 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value;
444 if (Op1Opc == ISD::AND) {
445 unsigned SHOpc = Op1.getOperand(0).getOpcode();
446 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) &&
447 isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) {
448 Op1 = Op1.getOperand(0).getOperand(0);
449 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value;
451 Op1 = Op1.getOperand(0);
455 Tmp3 = (Op0Opc == ISD::AND && DisjointMask) ? Op0.getOperand(0) : Op0;
456 AddToQueue(Tmp1, Tmp3);
457 AddToQueue(Tmp2, Op1);
459 return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Tmp1, Tmp2,
460 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
466 /// SelectAddrImm - Returns true if the address N can be represented by
467 /// a base register plus a signed 16-bit displacement [r+imm].
468 bool PPCDAGToDAGISel::SelectAddrImm(SDOperand N, SDOperand &Disp,
470 // If this can be more profitably realized as r+r, fail.
471 if (SelectAddrIdx(N, Disp, Base))
474 if (N.getOpcode() == ISD::ADD) {
476 if (isIntS16Immediate(N.getOperand(1), imm)) {
477 Disp = getI32Imm((int)imm & 0xFFFF);
478 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
479 Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType());
481 Base = N.getOperand(0);
483 return true; // [r+i]
484 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
485 // Match LOAD (ADD (X, Lo(G))).
486 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
487 && "Cannot handle constant offsets yet!");
488 Disp = N.getOperand(1).getOperand(0); // The global address.
489 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
490 Disp.getOpcode() == ISD::TargetConstantPool ||
491 Disp.getOpcode() == ISD::TargetJumpTable);
492 Base = N.getOperand(0);
493 return true; // [&g+r]
495 } else if (N.getOpcode() == ISD::OR) {
497 if (isIntS16Immediate(N.getOperand(1), imm)) {
498 // If this is an or of disjoint bitfields, we can codegen this as an add
499 // (for better address arithmetic) if the LHS and RHS of the OR are
500 // provably disjoint.
501 uint64_t LHSKnownZero, LHSKnownOne;
502 PPCLowering.ComputeMaskedBits(N.getOperand(0), ~0U,
503 LHSKnownZero, LHSKnownOne);
504 if ((LHSKnownZero|~(unsigned)imm) == ~0U) {
505 // If all of the bits are known zero on the LHS or RHS, the add won't
507 Base = N.getOperand(0);
508 Disp = getI32Imm((int)imm & 0xFFFF);
512 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
513 // Loading from a constant address.
515 // If this address fits entirely in a 16-bit sext immediate field, codegen
518 if (isIntS16Immediate(CN, Imm)) {
519 Disp = CurDAG->getTargetConstant(Imm, CN->getValueType(0));
520 Base = CurDAG->getRegister(PPC::R0, CN->getValueType(0));
524 // FIXME: Handle small sext constant offsets in PPC64 mode also!
525 if (CN->getValueType(0) == MVT::i32) {
526 int Addr = (int)CN->getValue();
528 // Otherwise, break this down into an LIS + disp.
529 Disp = getI32Imm((short)Addr);
530 Base = CurDAG->getConstant(Addr - (signed short)Addr, MVT::i32);
535 Disp = getSmallIPtrImm(0);
536 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
537 Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType());
540 return true; // [r+0]
543 /// SelectAddrIdx - Given the specified addressed, check to see if it can be
544 /// represented as an indexed [r+r] operation. Returns false if it can
545 /// be represented by [r+imm], which are preferred.
546 bool PPCDAGToDAGISel::SelectAddrIdx(SDOperand N, SDOperand &Base,
549 if (N.getOpcode() == ISD::ADD) {
550 if (isIntS16Immediate(N.getOperand(1), imm))
552 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
555 Base = N.getOperand(0);
556 Index = N.getOperand(1);
558 } else if (N.getOpcode() == ISD::OR) {
559 if (isIntS16Immediate(N.getOperand(1), imm))
560 return false; // r+i can fold it if we can.
562 // If this is an or of disjoint bitfields, we can codegen this as an add
563 // (for better address arithmetic) if the LHS and RHS of the OR are provably
565 uint64_t LHSKnownZero, LHSKnownOne;
566 uint64_t RHSKnownZero, RHSKnownOne;
567 PPCLowering.ComputeMaskedBits(N.getOperand(0), ~0U,
568 LHSKnownZero, LHSKnownOne);
571 PPCLowering.ComputeMaskedBits(N.getOperand(1), ~0U,
572 RHSKnownZero, RHSKnownOne);
573 // If all of the bits are known zero on the LHS or RHS, the add won't
575 if ((LHSKnownZero | RHSKnownZero) == ~0U) {
576 Base = N.getOperand(0);
577 Index = N.getOperand(1);
586 /// SelectAddrIdxOnly - Given the specified addressed, force it to be
587 /// represented as an indexed [r+r] operation.
588 bool PPCDAGToDAGISel::SelectAddrIdxOnly(SDOperand N, SDOperand &Base,
590 // Check to see if we can easily represent this as an [r+r] address. This
591 // will fail if it thinks that the address is more profitably represented as
592 // reg+imm, e.g. where imm = 0.
593 if (SelectAddrIdx(N, Base, Index))
596 // If the operand is an addition, always emit this as [r+r], since this is
597 // better (for code size, and execution, as the memop does the add for free)
598 // than emitting an explicit add.
599 if (N.getOpcode() == ISD::ADD) {
600 Base = N.getOperand(0);
601 Index = N.getOperand(1);
605 // Otherwise, do it the hard way, using R0 as the base register.
606 Base = CurDAG->getRegister(PPC::R0, N.getValueType());
611 /// SelectAddrImmShift - Returns true if the address N can be represented by
612 /// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable
613 /// for use by STD and friends.
614 bool PPCDAGToDAGISel::SelectAddrImmShift(SDOperand N, SDOperand &Disp,
616 // If this can be more profitably realized as r+r, fail.
617 if (SelectAddrIdx(N, Disp, Base))
620 if (N.getOpcode() == ISD::ADD) {
622 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
623 Disp = getI32Imm(((int)imm & 0xFFFF) >> 2);
624 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
625 Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType());
627 Base = N.getOperand(0);
629 return true; // [r+i]
630 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
631 // Match LOAD (ADD (X, Lo(G))).
632 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
633 && "Cannot handle constant offsets yet!");
634 Disp = N.getOperand(1).getOperand(0); // The global address.
635 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
636 Disp.getOpcode() == ISD::TargetConstantPool ||
637 Disp.getOpcode() == ISD::TargetJumpTable);
638 Base = N.getOperand(0);
639 return true; // [&g+r]
641 } else if (N.getOpcode() == ISD::OR) {
643 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
644 // If this is an or of disjoint bitfields, we can codegen this as an add
645 // (for better address arithmetic) if the LHS and RHS of the OR are
646 // provably disjoint.
647 uint64_t LHSKnownZero, LHSKnownOne;
648 PPCLowering.ComputeMaskedBits(N.getOperand(0), ~0U,
649 LHSKnownZero, LHSKnownOne);
650 if ((LHSKnownZero|~(unsigned)imm) == ~0U) {
651 // If all of the bits are known zero on the LHS or RHS, the add won't
653 Base = N.getOperand(0);
654 Disp = getI32Imm(((int)imm & 0xFFFF) >> 2);
658 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
659 // Loading from a constant address.
661 // If this address fits entirely in a 14-bit sext immediate field, codegen
664 if (isIntS16Immediate(CN, Imm)) {
665 Disp = getSmallIPtrImm((unsigned short)Imm >> 2);
666 Base = CurDAG->getRegister(PPC::R0, CN->getValueType(0));
670 // FIXME: Handle small sext constant offsets in PPC64 mode also!
671 if (CN->getValueType(0) == MVT::i32) {
672 int Addr = (int)CN->getValue();
674 // Otherwise, break this down into an LIS + disp.
675 Disp = getI32Imm((short)Addr >> 2);
676 Base = CurDAG->getConstant(Addr - (signed short)Addr, MVT::i32);
681 Disp = getSmallIPtrImm(0);
682 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
683 Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType());
686 return true; // [r+0]
690 /// SelectCC - Select a comparison of the specified values with the specified
691 /// condition code, returning the CR# of the expression.
692 SDOperand PPCDAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS,
694 // Always select the LHS.
695 AddToQueue(LHS, LHS);
698 if (LHS.getValueType() == MVT::i32) {
700 if (ISD::isUnsignedIntSetCC(CC)) {
701 if (isInt32Immediate(RHS, Imm) && isUInt16(Imm))
702 return SDOperand(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, LHS,
703 getI32Imm(Imm & 0xFFFF)), 0);
707 if (isIntS16Immediate(RHS, SImm))
708 return SDOperand(CurDAG->getTargetNode(PPC::CMPWI, MVT::i32, LHS,
709 getI32Imm((int)SImm & 0xFFFF)),
713 } else if (LHS.getValueType() == MVT::i64) {
715 if (ISD::isUnsignedIntSetCC(CC)) {
716 if (isInt64Immediate(RHS.Val, Imm) && isUInt16(Imm))
717 return SDOperand(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, LHS,
718 getI64Imm(Imm & 0xFFFF)), 0);
722 if (isIntS16Immediate(RHS, SImm))
723 return SDOperand(CurDAG->getTargetNode(PPC::CMPDI, MVT::i64, LHS,
724 getI64Imm((int)SImm & 0xFFFF)),
728 } else if (LHS.getValueType() == MVT::f32) {
731 assert(LHS.getValueType() == MVT::f64 && "Unknown vt!");
734 AddToQueue(RHS, RHS);
735 return SDOperand(CurDAG->getTargetNode(Opc, MVT::i32, LHS, RHS), 0);
738 /// getBCCForSetCC - Returns the PowerPC condition branch mnemonic corresponding
740 static unsigned getBCCForSetCC(ISD::CondCode CC) {
742 default: assert(0 && "Unknown condition!"); abort();
743 case ISD::SETOEQ: // FIXME: This is incorrect see PR642.
745 case ISD::SETEQ: return PPC::BEQ;
746 case ISD::SETONE: // FIXME: This is incorrect see PR642.
748 case ISD::SETNE: return PPC::BNE;
749 case ISD::SETOLT: // FIXME: This is incorrect see PR642.
751 case ISD::SETLT: return PPC::BLT;
752 case ISD::SETOLE: // FIXME: This is incorrect see PR642.
754 case ISD::SETLE: return PPC::BLE;
755 case ISD::SETOGT: // FIXME: This is incorrect see PR642.
757 case ISD::SETGT: return PPC::BGT;
758 case ISD::SETOGE: // FIXME: This is incorrect see PR642.
760 case ISD::SETGE: return PPC::BGE;
762 case ISD::SETO: return PPC::BUN;
763 case ISD::SETUO: return PPC::BNU;
768 /// getCRIdxForSetCC - Return the index of the condition register field
769 /// associated with the SetCC condition, and whether or not the field is
770 /// treated as inverted. That is, lt = 0; ge = 0 inverted.
771 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool& Inv) {
773 default: assert(0 && "Unknown condition!"); abort();
774 case ISD::SETOLT: // FIXME: This is incorrect see PR642.
776 case ISD::SETLT: Inv = false; return 0;
777 case ISD::SETOGE: // FIXME: This is incorrect see PR642.
779 case ISD::SETGE: Inv = true; return 0;
780 case ISD::SETOGT: // FIXME: This is incorrect see PR642.
782 case ISD::SETGT: Inv = false; return 1;
783 case ISD::SETOLE: // FIXME: This is incorrect see PR642.
785 case ISD::SETLE: Inv = true; return 1;
786 case ISD::SETOEQ: // FIXME: This is incorrect see PR642.
788 case ISD::SETEQ: Inv = false; return 2;
789 case ISD::SETONE: // FIXME: This is incorrect see PR642.
791 case ISD::SETNE: Inv = true; return 2;
792 case ISD::SETO: Inv = true; return 3;
793 case ISD::SETUO: Inv = false; return 3;
798 SDNode *PPCDAGToDAGISel::SelectSETCC(SDOperand Op) {
801 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
802 if (isInt32Immediate(N->getOperand(1), Imm)) {
803 // We can codegen setcc op, imm very efficiently compared to a brcond.
804 // Check for those cases here.
808 AddToQueue(Op, N->getOperand(0));
812 Op = SDOperand(CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op), 0);
813 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(27),
814 getI32Imm(5), getI32Imm(31)).Val;
817 SDOperand(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
818 Op, getI32Imm(~0U)), 0);
819 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
823 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(1),
824 getI32Imm(31), getI32Imm(31)).Val;
827 SDOperand(CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op), 0);
828 T = SDOperand(CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op), 0);
829 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, T, getI32Imm(1),
830 getI32Imm(31), getI32Imm(31)).Val;
833 } else if (Imm == ~0U) { // setcc op, -1
835 AddToQueue(Op, N->getOperand(0));
839 Op = SDOperand(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
840 Op, getI32Imm(1)), 0);
841 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
842 SDOperand(CurDAG->getTargetNode(PPC::LI, MVT::i32,
846 Op = SDOperand(CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op), 0);
847 SDNode *AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
849 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDOperand(AD, 0),
850 Op, SDOperand(AD, 1)).Val;
853 SDOperand AD = SDOperand(CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op,
855 SDOperand AN = SDOperand(CurDAG->getTargetNode(PPC::AND, MVT::i32, AD,
857 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, AN, getI32Imm(1),
858 getI32Imm(31), getI32Imm(31)).Val;
861 Op = SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Op,
862 getI32Imm(1), getI32Imm(31),
864 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op,
871 unsigned Idx = getCRIdxForSetCC(CC, Inv);
872 SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
875 // Force the ccreg into CR7.
876 SDOperand CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
878 SDOperand InFlag(0, 0); // Null incoming flag value.
879 CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), CR7Reg, CCReg,
882 if (TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor())
883 IntCR = SDOperand(CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg,
886 IntCR = SDOperand(CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg), 0);
889 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, IntCR,
890 getI32Imm((32-(3-Idx)) & 31),
891 getI32Imm(31), getI32Imm(31)).Val;
894 SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, IntCR,
895 getI32Imm((32-(3-Idx)) & 31),
896 getI32Imm(31),getI32Imm(31)), 0);
897 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1)).Val;
902 // Select - Convert the specified operand from a target-independent to a
903 // target-specific node if it hasn't already been changed.
904 SDNode *PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
906 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
907 N->getOpcode() < PPCISD::FIRST_NUMBER) {
909 return NULL; // Already selected.
912 switch (N->getOpcode()) {
915 return SelectSETCC(Op);
916 case PPCISD::GlobalBaseReg:
917 return getGlobalBaseReg().Val;
919 case ISD::FrameIndex: {
920 int FI = cast<FrameIndexSDNode>(N)->getIndex();
921 SDOperand TFI = CurDAG->getTargetFrameIndex(FI, Op.getValueType());
922 unsigned Opc = Op.getValueType() == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
924 return CurDAG->SelectNodeTo(N, Opc, Op.getValueType(), TFI,
925 getSmallIPtrImm(0)).Val;
926 return CurDAG->getTargetNode(Opc, Op.getValueType(), TFI,
932 AddToQueue(InFlag, N->getOperand(1));
933 // Use MFOCRF if supported.
934 if (TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor())
935 return CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32,
936 N->getOperand(0), InFlag);
938 return CurDAG->getTargetNode(PPC::MFCR, MVT::i32, InFlag);
942 // FIXME: since this depends on the setting of the carry flag from the srawi
943 // we should really be making notes about that for the scheduler.
944 // FIXME: It sure would be nice if we could cheaply recognize the
945 // srl/add/sra pattern the dag combiner will generate for this as
946 // sra/addze rather than having to handle sdiv ourselves. oh well.
948 if (isInt32Immediate(N->getOperand(1), Imm)) {
950 AddToQueue(N0, N->getOperand(0));
951 if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
953 CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
954 N0, getI32Imm(Log2_32(Imm)));
955 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
956 SDOperand(Op, 0), SDOperand(Op, 1)).Val;
957 } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
959 CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
960 N0, getI32Imm(Log2_32(-Imm)));
962 SDOperand(CurDAG->getTargetNode(PPC::ADDZE, MVT::i32,
963 SDOperand(Op, 0), SDOperand(Op, 1)),
965 return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT).Val;
969 // Other cases are autogenerated.
974 // If this is an and of a value rotated between 0 and 31 bits and then and'd
975 // with a mask, emit rlwinm
976 if (isInt32Immediate(N->getOperand(1), Imm) &&
977 (isShiftedMask_32(Imm) || isShiftedMask_32(~Imm))) {
980 if (isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB, ME)) {
981 AddToQueue(Val, N->getOperand(0).getOperand(0));
982 } else if (Imm == 0) {
983 // AND X, 0 -> 0, not "rlwinm 32".
984 AddToQueue(Result, N->getOperand(1));
985 ReplaceUses(SDOperand(N, 0), N->getOperand(1));
988 AddToQueue(Val, N->getOperand(0));
989 isRunOfOnes(Imm, MB, ME);
992 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Val,
993 getI32Imm(SH), getI32Imm(MB),
996 // ISD::OR doesn't get all the bitfield insertion fun.
997 // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert
998 if (isInt32Immediate(N->getOperand(1), Imm) &&
999 N->getOperand(0).getOpcode() == ISD::OR &&
1000 isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) {
1003 if (isRunOfOnes(Imm, MB, ME)) {
1004 SDOperand Tmp1, Tmp2;
1005 AddToQueue(Tmp1, N->getOperand(0).getOperand(0));
1006 AddToQueue(Tmp2, N->getOperand(0).getOperand(1));
1007 return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Tmp1, Tmp2,
1008 getI32Imm(0), getI32Imm(MB),getI32Imm(ME));
1012 // Other cases are autogenerated.
1016 if (N->getValueType(0) == MVT::i32)
1017 if (SDNode *I = SelectBitfieldInsert(N))
1020 // Other cases are autogenerated.
1023 unsigned Imm, SH, MB, ME;
1024 if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
1025 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
1027 AddToQueue(Val, N->getOperand(0).getOperand(0));
1028 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32,
1029 Val, getI32Imm(SH), getI32Imm(MB),
1033 // Other cases are autogenerated.
1037 unsigned Imm, SH, MB, ME;
1038 if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
1039 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
1041 AddToQueue(Val, N->getOperand(0).getOperand(0));
1042 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32,
1043 Val, getI32Imm(SH), getI32Imm(MB),
1047 // Other cases are autogenerated.
1050 case ISD::SELECT_CC: {
1051 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1053 // Handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
1054 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1055 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
1056 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
1057 if (N1C->isNullValue() && N3C->isNullValue() &&
1058 N2C->getValue() == 1ULL && CC == ISD::SETNE &&
1059 // FIXME: Implement this optzn for PPC64.
1060 N->getValueType(0) == MVT::i32) {
1062 AddToQueue(LHS, N->getOperand(0));
1064 CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
1065 LHS, getI32Imm(~0U));
1066 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
1067 SDOperand(Tmp, 0), LHS,
1068 SDOperand(Tmp, 1)).Val;
1071 SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
1072 unsigned BROpc = getBCCForSetCC(CC);
1074 bool isFP = MVT::isFloatingPoint(N->getValueType(0));
1075 unsigned SelectCCOp;
1076 if (N->getValueType(0) == MVT::i32)
1077 SelectCCOp = PPC::SELECT_CC_I4;
1078 else if (N->getValueType(0) == MVT::i64)
1079 SelectCCOp = PPC::SELECT_CC_I8;
1080 else if (N->getValueType(0) == MVT::f32)
1081 SelectCCOp = PPC::SELECT_CC_F4;
1082 else if (N->getValueType(0) == MVT::f64)
1083 SelectCCOp = PPC::SELECT_CC_F8;
1085 SelectCCOp = PPC::SELECT_CC_VRRC;
1088 AddToQueue(N2, N->getOperand(2));
1089 AddToQueue(N3, N->getOperand(3));
1090 return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), CCReg,
1091 N2, N3, getI32Imm(BROpc)).Val;
1095 AddToQueue(Chain, N->getOperand(0));
1096 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
1097 SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC);
1098 return CurDAG->SelectNodeTo(N, PPC::COND_BRANCH, MVT::Other,
1099 CondCode, getI32Imm(getBCCForSetCC(CC)),
1100 N->getOperand(4), Chain).Val;
1103 // FIXME: Should custom lower this.
1104 SDOperand Chain, Target;
1105 AddToQueue(Chain, N->getOperand(0));
1106 AddToQueue(Target,N->getOperand(1));
1107 unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
1108 Chain = SDOperand(CurDAG->getTargetNode(Opc, MVT::Other, Target,
1110 return CurDAG->SelectNodeTo(N, PPC::BCTR, MVT::Other, Chain).Val;
1112 // FIXME: These are manually selected because tblgen isn't handling varargs
1114 case PPCISD::BCTRL: return MySelect_PPCbctrl(Op);
1115 case PPCISD::CALL: return MySelect_PPCcall(Op);
1118 return SelectCode(Result, Op);
1122 // FIXME: This is manually selected because tblgen isn't handling varargs nodes
1124 SDNode *PPCDAGToDAGISel::MySelect_PPCbctrl(SDOperand N) {
1125 SDOperand Chain(0, 0);
1128 N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag;
1130 SmallVector<SDOperand, 8> Ops;
1131 // Push varargs arguments, including optional flag.
1132 for (unsigned i = 1, e = N.getNumOperands()-hasFlag; i != e; ++i) {
1133 AddToQueue(Chain, N.getOperand(i));
1134 Ops.push_back(Chain);
1137 AddToQueue(Chain, N.getOperand(0));
1138 Ops.push_back(Chain);
1141 AddToQueue(Chain, N.getOperand(N.getNumOperands()-1));
1142 Ops.push_back(Chain);
1145 return CurDAG->getTargetNode(PPC::BCTRL, MVT::Other, MVT::Flag,
1146 &Ops[0], Ops.size());
1149 // FIXME: This is manually selected because tblgen isn't handling varargs nodes
1151 SDNode *PPCDAGToDAGISel::MySelect_PPCcall(SDOperand N) {
1152 SDOperand Chain(0, 0);
1154 SDOperand Tmp0(0, 0);
1156 Chain = N.getOperand(0);
1157 N1 = N.getOperand(1);
1159 // Pattern: (PPCcall:void (imm:i32):$func)
1160 // Emits: (BLA:void (imm:i32):$func)
1161 // Pattern complexity = 4 cost = 1
1162 if (N1.getOpcode() == ISD::Constant) {
1163 unsigned Tmp0C = (unsigned)cast<ConstantSDNode>(N1)->getValue();
1165 SmallVector<SDOperand, 8> Ops;
1166 Ops.push_back(CurDAG->getTargetConstant(Tmp0C, MVT::i32));
1169 N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag;
1171 // Push varargs arguments, not including optional flag.
1172 for (unsigned i = 2, e = N.getNumOperands()-hasFlag; i != e; ++i) {
1173 AddToQueue(Chain, N.getOperand(i));
1174 Ops.push_back(Chain);
1176 AddToQueue(Chain, N.getOperand(0));
1177 Ops.push_back(Chain);
1179 AddToQueue(Chain, N.getOperand(N.getNumOperands()-1));
1180 Ops.push_back(Chain);
1182 return CurDAG->getTargetNode(PPC::BLA, MVT::Other, MVT::Flag,
1183 &Ops[0], Ops.size());
1186 // Pattern: (PPCcall:void (tglobaladdr:i32):$dst)
1187 // Emits: (BL:void (tglobaladdr:i32):$dst)
1188 // Pattern complexity = 4 cost = 1
1189 if (N1.getOpcode() == ISD::TargetGlobalAddress) {
1190 SmallVector<SDOperand, 8> Ops;
1194 N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag;
1196 // Push varargs arguments, not including optional flag.
1197 for (unsigned i = 2, e = N.getNumOperands()-hasFlag; i != e; ++i) {
1198 AddToQueue(Chain, N.getOperand(i));
1199 Ops.push_back(Chain);
1201 AddToQueue(Chain, N.getOperand(0));
1202 Ops.push_back(Chain);
1204 AddToQueue(Chain, N.getOperand(N.getNumOperands()-1));
1205 Ops.push_back(Chain);
1208 return CurDAG->getTargetNode(PPC::BL, MVT::Other, MVT::Flag,
1209 &Ops[0], Ops.size());
1212 // Pattern: (PPCcall:void (texternalsym:i32):$dst)
1213 // Emits: (BL:void (texternalsym:i32):$dst)
1214 // Pattern complexity = 4 cost = 1
1215 if (N1.getOpcode() == ISD::TargetExternalSymbol) {
1216 std::vector<SDOperand> Ops;
1220 N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag;
1222 // Push varargs arguments, not including optional flag.
1223 for (unsigned i = 2, e = N.getNumOperands()-hasFlag; i != e; ++i) {
1224 AddToQueue(Chain, N.getOperand(i));
1225 Ops.push_back(Chain);
1227 AddToQueue(Chain, N.getOperand(0));
1228 Ops.push_back(Chain);
1230 AddToQueue(Chain, N.getOperand(N.getNumOperands()-1));
1231 Ops.push_back(Chain);
1234 return CurDAG->getTargetNode(PPC::BL, MVT::Other, MVT::Flag,
1235 &Ops[0], Ops.size());
1237 std::cerr << "Cannot yet select: ";
1238 N.Val->dump(CurDAG);
1246 /// createPPCISelDag - This pass converts a legalized DAG into a
1247 /// PowerPC-specific DAG, ready for instruction scheduling.
1249 FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) {
1250 return new PPCDAGToDAGISel(TM);