1 //===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for PowerPC,
11 // converting from a legalized dag to a PPC dag.
13 //===----------------------------------------------------------------------===//
16 #include "MCTargetDesc/PPCPredicates.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCTargetMachine.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/IR/GlobalAlias.h"
27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/IR/GlobalVariable.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Module.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetOptions.h"
39 #define DEBUG_TYPE "ppc-codegen"
41 // FIXME: Remove this once the bug has been fixed!
42 cl::opt<bool> ANDIGlueBug("expose-ppc-andi-glue-bug",
43 cl::desc("expose the ANDI glue bug on PPC"), cl::Hidden);
45 cl::opt<bool> UseBitPermRewriter("ppc-use-bit-perm-rewriter", cl::init(true),
46 cl::desc("use aggressive ppc isel for bit permutations"), cl::Hidden);
47 cl::opt<bool> BPermRewriterNoMasking("ppc-bit-perm-rewriter-stress-rotates",
48 cl::desc("stress rotate selection in aggressive ppc isel for "
49 "bit permutations"), cl::Hidden);
52 void initializePPCDAGToDAGISelPass(PassRegistry&);
56 //===--------------------------------------------------------------------===//
57 /// PPCDAGToDAGISel - PPC specific code to select PPC machine
58 /// instructions for SelectionDAG operations.
60 class PPCDAGToDAGISel : public SelectionDAGISel {
61 const PPCTargetMachine &TM;
62 const PPCTargetLowering *PPCLowering;
63 const PPCSubtarget *PPCSubTarget;
64 unsigned GlobalBaseReg;
66 explicit PPCDAGToDAGISel(PPCTargetMachine &tm)
67 : SelectionDAGISel(tm), TM(tm),
68 PPCLowering(TM.getSubtargetImpl()->getTargetLowering()),
69 PPCSubTarget(TM.getSubtargetImpl()) {
70 initializePPCDAGToDAGISelPass(*PassRegistry::getPassRegistry());
73 bool runOnMachineFunction(MachineFunction &MF) override {
74 // Make sure we re-emit a set of the global base reg if necessary
76 PPCLowering = TM.getSubtargetImpl()->getTargetLowering();
77 PPCSubTarget = TM.getSubtargetImpl();
78 SelectionDAGISel::runOnMachineFunction(MF);
80 if (!PPCSubTarget->isSVR4ABI())
86 void PreprocessISelDAG() override;
87 void PostprocessISelDAG() override;
89 /// getI32Imm - Return a target constant with the specified value, of type
91 inline SDValue getI32Imm(unsigned Imm) {
92 return CurDAG->getTargetConstant(Imm, MVT::i32);
95 /// getI64Imm - Return a target constant with the specified value, of type
97 inline SDValue getI64Imm(uint64_t Imm) {
98 return CurDAG->getTargetConstant(Imm, MVT::i64);
101 /// getSmallIPtrImm - Return a target constant of pointer type.
102 inline SDValue getSmallIPtrImm(unsigned Imm) {
103 return CurDAG->getTargetConstant(Imm, PPCLowering->getPointerTy());
106 /// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s
107 /// with any number of 0s on either side. The 1s are allowed to wrap from
108 /// LSB to MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs.
109 /// 0x0F0F0000 is not, since all 1s are not contiguous.
110 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME);
113 /// isRotateAndMask - Returns true if Mask and Shift can be folded into a
114 /// rotate and mask opcode and mask operation.
115 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool isShiftMask,
116 unsigned &SH, unsigned &MB, unsigned &ME);
118 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
119 /// base register. Return the virtual register that holds this value.
120 SDNode *getGlobalBaseReg();
122 SDNode *getFrameIndex(SDNode *SN, SDNode *N, unsigned Offset = 0);
124 // Select - Convert the specified operand from a target-independent to a
125 // target-specific node if it hasn't already been changed.
126 SDNode *Select(SDNode *N) override;
128 SDNode *SelectBitfieldInsert(SDNode *N);
129 SDNode *SelectBitPermutation(SDNode *N);
131 /// SelectCC - Select a comparison of the specified values with the
132 /// specified condition code, returning the CR# of the expression.
133 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDLoc dl);
135 /// SelectAddrImm - Returns true if the address N can be represented by
136 /// a base register plus a signed 16-bit displacement [r+imm].
137 bool SelectAddrImm(SDValue N, SDValue &Disp,
139 return PPCLowering->SelectAddressRegImm(N, Disp, Base, *CurDAG, false);
142 /// SelectAddrImmOffs - Return true if the operand is valid for a preinc
143 /// immediate field. Note that the operand at this point is already the
144 /// result of a prior SelectAddressRegImm call.
145 bool SelectAddrImmOffs(SDValue N, SDValue &Out) const {
146 if (N.getOpcode() == ISD::TargetConstant ||
147 N.getOpcode() == ISD::TargetGlobalAddress) {
155 /// SelectAddrIdx - Given the specified addressed, check to see if it can be
156 /// represented as an indexed [r+r] operation. Returns false if it can
157 /// be represented by [r+imm], which are preferred.
158 bool SelectAddrIdx(SDValue N, SDValue &Base, SDValue &Index) {
159 return PPCLowering->SelectAddressRegReg(N, Base, Index, *CurDAG);
162 /// SelectAddrIdxOnly - Given the specified addressed, force it to be
163 /// represented as an indexed [r+r] operation.
164 bool SelectAddrIdxOnly(SDValue N, SDValue &Base, SDValue &Index) {
165 return PPCLowering->SelectAddressRegRegOnly(N, Base, Index, *CurDAG);
168 /// SelectAddrImmX4 - Returns true if the address N can be represented by
169 /// a base register plus a signed 16-bit displacement that is a multiple of 4.
170 /// Suitable for use by STD and friends.
171 bool SelectAddrImmX4(SDValue N, SDValue &Disp, SDValue &Base) {
172 return PPCLowering->SelectAddressRegImm(N, Disp, Base, *CurDAG, true);
175 // Select an address into a single register.
176 bool SelectAddr(SDValue N, SDValue &Base) {
181 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
182 /// inline asm expressions. It is always correct to compute the value into
183 /// a register. The case of adding a (possibly relocatable) constant to a
184 /// register can be improved, but it is wrong to substitute Reg+Reg for
185 /// Reg in an asm, because the load or store opcode would have to change.
186 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
188 std::vector<SDValue> &OutOps) override {
189 // We need to make sure that this one operand does not end up in r0
190 // (because we might end up lowering this as 0(%op)).
191 const TargetRegisterInfo *TRI = TM.getSubtargetImpl()->getRegisterInfo();
192 const TargetRegisterClass *TRC = TRI->getPointerRegClass(*MF, /*Kind=*/1);
193 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
195 SDValue(CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
196 SDLoc(Op), Op.getValueType(),
199 OutOps.push_back(NewOp);
203 void InsertVRSaveCode(MachineFunction &MF);
205 const char *getPassName() const override {
206 return "PowerPC DAG->DAG Pattern Instruction Selection";
209 // Include the pieces autogenerated from the target description.
210 #include "PPCGenDAGISel.inc"
213 SDNode *SelectSETCC(SDNode *N);
215 void PeepholePPC64();
216 void PeepholePPC64ZExt();
217 void PeepholeCROps();
219 SDValue combineToCMPB(SDNode *N);
220 void foldBoolExts(SDValue &Res, SDNode *&N);
222 bool AllUsersSelectZero(SDNode *N);
223 void SwapAllSelectUsers(SDNode *N);
227 /// InsertVRSaveCode - Once the entire function has been instruction selected,
228 /// all virtual registers are created and all machine instructions are built,
229 /// check to see if we need to save/restore VRSAVE. If so, do it.
230 void PPCDAGToDAGISel::InsertVRSaveCode(MachineFunction &Fn) {
231 // Check to see if this function uses vector registers, which means we have to
232 // save and restore the VRSAVE register and update it with the regs we use.
234 // In this case, there will be virtual registers of vector type created
235 // by the scheduler. Detect them now.
236 bool HasVectorVReg = false;
237 for (unsigned i = 0, e = RegInfo->getNumVirtRegs(); i != e; ++i) {
238 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
239 if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) {
240 HasVectorVReg = true;
244 if (!HasVectorVReg) return; // nothing to do.
246 // If we have a vector register, we want to emit code into the entry and exit
247 // blocks to save and restore the VRSAVE register. We do this here (instead
248 // of marking all vector instructions as clobbering VRSAVE) for two reasons:
250 // 1. This (trivially) reduces the load on the register allocator, by not
251 // having to represent the live range of the VRSAVE register.
252 // 2. This (more significantly) allows us to create a temporary virtual
253 // register to hold the saved VRSAVE value, allowing this temporary to be
254 // register allocated, instead of forcing it to be spilled to the stack.
256 // Create two vregs - one to hold the VRSAVE register that is live-in to the
257 // function and one for the value after having bits or'd into it.
258 unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
259 unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
261 const TargetInstrInfo &TII = *TM.getSubtargetImpl()->getInstrInfo();
262 MachineBasicBlock &EntryBB = *Fn.begin();
264 // Emit the following code into the entry block:
265 // InVRSAVE = MFVRSAVE
266 // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
267 // MTVRSAVE UpdatedVRSAVE
268 MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
269 BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE);
270 BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE),
271 UpdatedVRSAVE).addReg(InVRSAVE);
272 BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
274 // Find all return blocks, outputting a restore in each epilog.
275 for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
276 if (!BB->empty() && BB->back().isReturn()) {
277 IP = BB->end(); --IP;
279 // Skip over all terminator instructions, which are part of the return
281 MachineBasicBlock::iterator I2 = IP;
282 while (I2 != BB->begin() && (--I2)->isTerminator())
285 // Emit: MTVRSAVE InVRSave
286 BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
292 /// getGlobalBaseReg - Output the instructions required to put the
293 /// base address to use for accessing globals into a register.
295 SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
296 if (!GlobalBaseReg) {
297 const TargetInstrInfo &TII = *TM.getSubtargetImpl()->getInstrInfo();
298 // Insert the set of GlobalBaseReg into the first MBB of the function
299 MachineBasicBlock &FirstMBB = MF->front();
300 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
301 const Module *M = MF->getFunction()->getParent();
304 if (PPCLowering->getPointerTy() == MVT::i32) {
305 if (PPCSubTarget->isTargetELF()) {
306 GlobalBaseReg = PPC::R30;
307 if (M->getPICLevel() == PICLevel::Small) {
308 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MoveGOTtoLR));
309 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
311 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));
312 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
313 unsigned TempReg = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
314 BuildMI(FirstMBB, MBBI, dl,
315 TII.get(PPC::UpdateGBR)).addReg(GlobalBaseReg)
316 .addReg(TempReg, RegState::Define).addReg(GlobalBaseReg);
317 MF->getInfo<PPCFunctionInfo>()->setUsesPICBase(true);
321 RegInfo->createVirtualRegister(&PPC::GPRC_NOR0RegClass);
322 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));
323 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
326 GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::G8RC_NOX0RegClass);
327 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8));
328 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg);
331 return CurDAG->getRegister(GlobalBaseReg,
332 PPCLowering->getPointerTy()).getNode();
335 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
336 /// or 64-bit immediate, and if the value can be accurately represented as a
337 /// sign extension from a 16-bit value. If so, this returns true and the
339 static bool isIntS16Immediate(SDNode *N, short &Imm) {
340 if (N->getOpcode() != ISD::Constant)
343 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
344 if (N->getValueType(0) == MVT::i32)
345 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
347 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
350 static bool isIntS16Immediate(SDValue Op, short &Imm) {
351 return isIntS16Immediate(Op.getNode(), Imm);
355 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
356 /// operand. If so Imm will receive the 32-bit value.
357 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
358 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
359 Imm = cast<ConstantSDNode>(N)->getZExtValue();
365 /// isInt64Immediate - This method tests to see if the node is a 64-bit constant
366 /// operand. If so Imm will receive the 64-bit value.
367 static bool isInt64Immediate(SDNode *N, uint64_t &Imm) {
368 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
369 Imm = cast<ConstantSDNode>(N)->getZExtValue();
375 // isInt32Immediate - This method tests to see if a constant operand.
376 // If so Imm will receive the 32 bit value.
377 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
378 return isInt32Immediate(N.getNode(), Imm);
382 // isOpcWithIntImmediate - This method tests to see if the node is a specific
383 // opcode and that it has a immediate integer right operand.
384 // If so Imm will receive the 32 bit value.
385 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
386 return N->getOpcode() == Opc
387 && isInt32Immediate(N->getOperand(1).getNode(), Imm);
390 SDNode *PPCDAGToDAGISel::getFrameIndex(SDNode *SN, SDNode *N, unsigned Offset) {
392 int FI = cast<FrameIndexSDNode>(N)->getIndex();
393 SDValue TFI = CurDAG->getTargetFrameIndex(FI, N->getValueType(0));
394 unsigned Opc = N->getValueType(0) == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
396 return CurDAG->SelectNodeTo(SN, Opc, N->getValueType(0), TFI,
397 getSmallIPtrImm(Offset));
398 return CurDAG->getMachineNode(Opc, dl, N->getValueType(0), TFI,
399 getSmallIPtrImm(Offset));
402 bool PPCDAGToDAGISel::isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
406 if (isShiftedMask_32(Val)) {
407 // look for the first non-zero bit
408 MB = countLeadingZeros(Val);
409 // look for the first zero bit after the run of ones
410 ME = countLeadingZeros((Val - 1) ^ Val);
413 Val = ~Val; // invert mask
414 if (isShiftedMask_32(Val)) {
415 // effectively look for the first zero bit
416 ME = countLeadingZeros(Val) - 1;
417 // effectively look for the first one bit after the run of zeros
418 MB = countLeadingZeros((Val - 1) ^ Val) + 1;
426 bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask,
427 bool isShiftMask, unsigned &SH,
428 unsigned &MB, unsigned &ME) {
429 // Don't even go down this path for i64, since different logic will be
430 // necessary for rldicl/rldicr/rldimi.
431 if (N->getValueType(0) != MVT::i32)
435 unsigned Indeterminant = ~0; // bit mask marking indeterminant results
436 unsigned Opcode = N->getOpcode();
437 if (N->getNumOperands() != 2 ||
438 !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31))
441 if (Opcode == ISD::SHL) {
442 // apply shift left to mask if it comes first
443 if (isShiftMask) Mask = Mask << Shift;
444 // determine which bits are made indeterminant by shift
445 Indeterminant = ~(0xFFFFFFFFu << Shift);
446 } else if (Opcode == ISD::SRL) {
447 // apply shift right to mask if it comes first
448 if (isShiftMask) Mask = Mask >> Shift;
449 // determine which bits are made indeterminant by shift
450 Indeterminant = ~(0xFFFFFFFFu >> Shift);
451 // adjust for the left rotate
453 } else if (Opcode == ISD::ROTL) {
459 // if the mask doesn't intersect any Indeterminant bits
460 if (Mask && !(Mask & Indeterminant)) {
462 // make sure the mask is still a mask (wrap arounds may not be)
463 return isRunOfOnes(Mask, MB, ME);
468 /// SelectBitfieldInsert - turn an or of two masked values into
469 /// the rotate left word immediate then mask insert (rlwimi) instruction.
470 SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
471 SDValue Op0 = N->getOperand(0);
472 SDValue Op1 = N->getOperand(1);
475 APInt LKZ, LKO, RKZ, RKO;
476 CurDAG->computeKnownBits(Op0, LKZ, LKO);
477 CurDAG->computeKnownBits(Op1, RKZ, RKO);
479 unsigned TargetMask = LKZ.getZExtValue();
480 unsigned InsertMask = RKZ.getZExtValue();
482 if ((TargetMask | InsertMask) == 0xFFFFFFFF) {
483 unsigned Op0Opc = Op0.getOpcode();
484 unsigned Op1Opc = Op1.getOpcode();
485 unsigned Value, SH = 0;
486 TargetMask = ~TargetMask;
487 InsertMask = ~InsertMask;
489 // If the LHS has a foldable shift and the RHS does not, then swap it to the
490 // RHS so that we can fold the shift into the insert.
491 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
492 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
493 Op0.getOperand(0).getOpcode() == ISD::SRL) {
494 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
495 Op1.getOperand(0).getOpcode() != ISD::SRL) {
497 std::swap(Op0Opc, Op1Opc);
498 std::swap(TargetMask, InsertMask);
501 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
502 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
503 Op1.getOperand(0).getOpcode() != ISD::SRL) {
505 std::swap(Op0Opc, Op1Opc);
506 std::swap(TargetMask, InsertMask);
511 if (isRunOfOnes(InsertMask, MB, ME)) {
514 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
515 isInt32Immediate(Op1.getOperand(1), Value)) {
516 Op1 = Op1.getOperand(0);
517 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value;
519 if (Op1Opc == ISD::AND) {
520 // The AND mask might not be a constant, and we need to make sure that
521 // if we're going to fold the masking with the insert, all bits not
522 // know to be zero in the mask are known to be one.
524 CurDAG->computeKnownBits(Op1.getOperand(1), MKZ, MKO);
525 bool CanFoldMask = InsertMask == MKO.getZExtValue();
527 unsigned SHOpc = Op1.getOperand(0).getOpcode();
528 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && CanFoldMask &&
529 isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) {
530 // Note that Value must be in range here (less than 32) because
531 // otherwise there would not be any bits set in InsertMask.
532 Op1 = Op1.getOperand(0).getOperand(0);
533 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value;
538 SDValue Ops[] = { Op0, Op1, getI32Imm(SH), getI32Imm(MB),
540 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops);
546 // Predict the number of instructions that would be generated by calling
548 static unsigned SelectInt64CountDirect(int64_t Imm) {
549 // Assume no remaining bits.
550 unsigned Remainder = 0;
551 // Assume no shift required.
554 // If it can't be represented as a 32 bit value.
555 if (!isInt<32>(Imm)) {
556 Shift = countTrailingZeros<uint64_t>(Imm);
557 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
559 // If the shifted value fits 32 bits.
560 if (isInt<32>(ImmSh)) {
561 // Go with the shifted value.
564 // Still stuck with a 64 bit value.
571 // Intermediate operand.
574 // Handle first 32 bits.
575 unsigned Lo = Imm & 0xFFFF;
576 unsigned Hi = (Imm >> 16) & 0xFFFF;
579 if (isInt<16>(Imm)) {
583 // Handle the Hi bits and Lo bits.
590 // If no shift, we're done.
591 if (!Shift) return Result;
593 // Shift for next step if the upper 32-bits were not zero.
597 // Add in the last bits as required.
598 if ((Hi = (Remainder >> 16) & 0xFFFF))
600 if ((Lo = Remainder & 0xFFFF))
606 static uint64_t Rot64(uint64_t Imm, unsigned R) {
607 return (Imm << R) | (Imm >> (64 - R));
610 static unsigned SelectInt64Count(int64_t Imm) {
611 unsigned Count = SelectInt64CountDirect(Imm);
615 for (unsigned r = 1; r < 63; ++r) {
616 uint64_t RImm = Rot64(Imm, r);
617 unsigned RCount = SelectInt64CountDirect(RImm) + 1;
618 Count = std::min(Count, RCount);
620 // See comments in SelectInt64 for an explanation of the logic below.
621 unsigned LS = findLastSet(RImm);
625 uint64_t OnesMask = -(int64_t) (UINT64_C(1) << (LS+1));
626 uint64_t RImmWithOnes = RImm | OnesMask;
628 RCount = SelectInt64CountDirect(RImmWithOnes) + 1;
629 Count = std::min(Count, RCount);
635 // Select a 64-bit constant. For cost-modeling purposes, SelectInt64Count
636 // (above) needs to be kept in sync with this function.
637 static SDNode *SelectInt64Direct(SelectionDAG *CurDAG, SDLoc dl, int64_t Imm) {
638 // Assume no remaining bits.
639 unsigned Remainder = 0;
640 // Assume no shift required.
643 // If it can't be represented as a 32 bit value.
644 if (!isInt<32>(Imm)) {
645 Shift = countTrailingZeros<uint64_t>(Imm);
646 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
648 // If the shifted value fits 32 bits.
649 if (isInt<32>(ImmSh)) {
650 // Go with the shifted value.
653 // Still stuck with a 64 bit value.
660 // Intermediate operand.
663 // Handle first 32 bits.
664 unsigned Lo = Imm & 0xFFFF;
665 unsigned Hi = (Imm >> 16) & 0xFFFF;
667 auto getI32Imm = [CurDAG](unsigned Imm) {
668 return CurDAG->getTargetConstant(Imm, MVT::i32);
672 if (isInt<16>(Imm)) {
674 Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo));
676 // Handle the Hi bits.
677 unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8;
678 Result = CurDAG->getMachineNode(OpC, dl, MVT::i64, getI32Imm(Hi));
680 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
681 SDValue(Result, 0), getI32Imm(Lo));
684 Result = CurDAG->getMachineNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi));
687 // If no shift, we're done.
688 if (!Shift) return Result;
690 // Shift for next step if the upper 32-bits were not zero.
692 Result = CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64,
695 getI32Imm(63 - Shift));
698 // Add in the last bits as required.
699 if ((Hi = (Remainder >> 16) & 0xFFFF)) {
700 Result = CurDAG->getMachineNode(PPC::ORIS8, dl, MVT::i64,
701 SDValue(Result, 0), getI32Imm(Hi));
703 if ((Lo = Remainder & 0xFFFF)) {
704 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
705 SDValue(Result, 0), getI32Imm(Lo));
711 static SDNode *SelectInt64(SelectionDAG *CurDAG, SDLoc dl, int64_t Imm) {
712 unsigned Count = SelectInt64CountDirect(Imm);
714 return SelectInt64Direct(CurDAG, dl, Imm);
721 for (unsigned r = 1; r < 63; ++r) {
722 uint64_t RImm = Rot64(Imm, r);
723 unsigned RCount = SelectInt64CountDirect(RImm) + 1;
724 if (RCount < Count) {
731 // If the immediate to generate has many trailing zeros, it might be
732 // worthwhile to generate a rotated value with too many leading ones
733 // (because that's free with li/lis's sign-extension semantics), and then
734 // mask them off after rotation.
736 unsigned LS = findLastSet(RImm);
737 // We're adding (63-LS) higher-order ones, and we expect to mask them off
738 // after performing the inverse rotation by (64-r). So we need that:
739 // 63-LS == 64-r => LS == r-1
743 uint64_t OnesMask = -(int64_t) (UINT64_C(1) << (LS+1));
744 uint64_t RImmWithOnes = RImm | OnesMask;
746 RCount = SelectInt64CountDirect(RImmWithOnes) + 1;
747 if (RCount < Count) {
750 MatImm = RImmWithOnes;
756 return SelectInt64Direct(CurDAG, dl, Imm);
758 auto getI32Imm = [CurDAG](unsigned Imm) {
759 return CurDAG->getTargetConstant(Imm, MVT::i32);
762 SDValue Val = SDValue(SelectInt64Direct(CurDAG, dl, MatImm), 0);
763 return CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64, Val,
764 getI32Imm(64 - RMin), getI32Imm(MaskEnd));
767 // Select a 64-bit constant.
768 static SDNode *SelectInt64(SelectionDAG *CurDAG, SDNode *N) {
772 int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue();
773 return SelectInt64(CurDAG, dl, Imm);
777 class BitPermutationSelector {
781 // The bit number in the value, using a convention where bit 0 is the
790 ValueBit(SDValue V, unsigned I, Kind K = Variable)
791 : V(V), Idx(I), K(K) {}
792 ValueBit(Kind K = Variable)
793 : V(SDValue(nullptr, 0)), Idx(UINT32_MAX), K(K) {}
795 bool isZero() const {
796 return K == ConstZero;
799 bool hasValue() const {
800 return K == Variable;
803 SDValue getValue() const {
804 assert(hasValue() && "Cannot get the value of a constant bit");
808 unsigned getValueBitIndex() const {
809 assert(hasValue() && "Cannot get the value bit index of a constant bit");
814 // A bit group has the same underlying value and the same rotate factor.
818 unsigned StartIdx, EndIdx;
820 // This rotation amount assumes that the lower 32 bits of the quantity are
821 // replicated in the high 32 bits by the rotation operator (which is done
822 // by rlwinm and friends in 64-bit mode).
824 // Did converting to Repl32 == true change the rotation factor? If it did,
825 // it decreased it by 32.
827 // Was this group coalesced after setting Repl32 to true?
828 bool Repl32Coalesced;
830 BitGroup(SDValue V, unsigned R, unsigned S, unsigned E)
831 : V(V), RLAmt(R), StartIdx(S), EndIdx(E), Repl32(false), Repl32CR(false),
832 Repl32Coalesced(false) {
833 DEBUG(dbgs() << "\tbit group for " << V.getNode() << " RLAmt = " << R <<
834 " [" << S << ", " << E << "]\n");
838 // Information on each (Value, RLAmt) pair (like the number of groups
839 // associated with each) used to choose the lowering method.
840 struct ValueRotInfo {
844 unsigned FirstGroupStartIdx;
848 : RLAmt(UINT32_MAX), NumGroups(0), FirstGroupStartIdx(UINT32_MAX),
851 // For sorting (in reverse order) by NumGroups, and then by
852 // FirstGroupStartIdx.
853 bool operator < (const ValueRotInfo &Other) const {
854 // We need to sort so that the non-Repl32 come first because, when we're
855 // doing masking, the Repl32 bit groups might be subsumed into the 64-bit
856 // masking operation.
857 if (Repl32 < Other.Repl32)
859 else if (Repl32 > Other.Repl32)
861 else if (NumGroups > Other.NumGroups)
863 else if (NumGroups < Other.NumGroups)
865 else if (FirstGroupStartIdx < Other.FirstGroupStartIdx)
871 // Return true if something interesting was deduced, return false if we're
872 // providing only a generic representation of V (or something else likewise
873 // uninteresting for instruction selection).
874 bool getValueBits(SDValue V, SmallVector<ValueBit, 64> &Bits) {
875 switch (V.getOpcode()) {
878 if (isa<ConstantSDNode>(V.getOperand(1))) {
879 unsigned RotAmt = V.getConstantOperandVal(1);
881 SmallVector<ValueBit, 64> LHSBits(Bits.size());
882 getValueBits(V.getOperand(0), LHSBits);
884 for (unsigned i = 0; i < Bits.size(); ++i)
885 Bits[i] = LHSBits[i < RotAmt ? i + (Bits.size() - RotAmt) : i - RotAmt];
891 if (isa<ConstantSDNode>(V.getOperand(1))) {
892 unsigned ShiftAmt = V.getConstantOperandVal(1);
894 SmallVector<ValueBit, 64> LHSBits(Bits.size());
895 getValueBits(V.getOperand(0), LHSBits);
897 for (unsigned i = ShiftAmt; i < Bits.size(); ++i)
898 Bits[i] = LHSBits[i - ShiftAmt];
900 for (unsigned i = 0; i < ShiftAmt; ++i)
901 Bits[i] = ValueBit(ValueBit::ConstZero);
907 if (isa<ConstantSDNode>(V.getOperand(1))) {
908 unsigned ShiftAmt = V.getConstantOperandVal(1);
910 SmallVector<ValueBit, 64> LHSBits(Bits.size());
911 getValueBits(V.getOperand(0), LHSBits);
913 for (unsigned i = 0; i < Bits.size() - ShiftAmt; ++i)
914 Bits[i] = LHSBits[i + ShiftAmt];
916 for (unsigned i = Bits.size() - ShiftAmt; i < Bits.size(); ++i)
917 Bits[i] = ValueBit(ValueBit::ConstZero);
923 if (isa<ConstantSDNode>(V.getOperand(1))) {
924 uint64_t Mask = V.getConstantOperandVal(1);
926 SmallVector<ValueBit, 64> LHSBits(Bits.size());
927 bool LHSTrivial = getValueBits(V.getOperand(0), LHSBits);
929 for (unsigned i = 0; i < Bits.size(); ++i)
930 if (((Mask >> i) & 1) == 1)
931 Bits[i] = LHSBits[i];
933 Bits[i] = ValueBit(ValueBit::ConstZero);
935 // Mark this as interesting, only if the LHS was also interesting. This
936 // prevents the overall procedure from matching a single immediate 'and'
937 // (which is non-optimal because such an and might be folded with other
938 // things if we don't select it here).
943 SmallVector<ValueBit, 64> LHSBits(Bits.size()), RHSBits(Bits.size());
944 getValueBits(V.getOperand(0), LHSBits);
945 getValueBits(V.getOperand(1), RHSBits);
947 bool AllDisjoint = true;
948 for (unsigned i = 0; i < Bits.size(); ++i)
949 if (LHSBits[i].isZero())
950 Bits[i] = RHSBits[i];
951 else if (RHSBits[i].isZero())
952 Bits[i] = LHSBits[i];
965 for (unsigned i = 0; i < Bits.size(); ++i)
966 Bits[i] = ValueBit(V, i);
971 // For each value (except the constant ones), compute the left-rotate amount
972 // to get it from its original to final position.
973 void computeRotationAmounts() {
975 RLAmt.resize(Bits.size());
976 for (unsigned i = 0; i < Bits.size(); ++i)
977 if (Bits[i].hasValue()) {
978 unsigned VBI = Bits[i].getValueBitIndex();
982 RLAmt[i] = Bits.size() - (VBI - i);
983 } else if (Bits[i].isZero()) {
985 RLAmt[i] = UINT32_MAX;
987 llvm_unreachable("Unknown value bit type");
991 // Collect groups of consecutive bits with the same underlying value and
992 // rotation factor. If we're doing late masking, we ignore zeros, otherwise
993 // they break up groups.
994 void collectBitGroups(bool LateMask) {
997 unsigned LastRLAmt = RLAmt[0];
998 SDValue LastValue = Bits[0].hasValue() ? Bits[0].getValue() : SDValue();
999 unsigned LastGroupStartIdx = 0;
1000 for (unsigned i = 1; i < Bits.size(); ++i) {
1001 unsigned ThisRLAmt = RLAmt[i];
1002 SDValue ThisValue = Bits[i].hasValue() ? Bits[i].getValue() : SDValue();
1003 if (LateMask && !ThisValue) {
1004 ThisValue = LastValue;
1005 ThisRLAmt = LastRLAmt;
1006 // If we're doing late masking, then the first bit group always starts
1007 // at zero (even if the first bits were zero).
1008 if (BitGroups.empty())
1009 LastGroupStartIdx = 0;
1012 // If this bit has the same underlying value and the same rotate factor as
1013 // the last one, then they're part of the same group.
1014 if (ThisRLAmt == LastRLAmt && ThisValue == LastValue)
1017 if (LastValue.getNode())
1018 BitGroups.push_back(BitGroup(LastValue, LastRLAmt, LastGroupStartIdx,
1020 LastRLAmt = ThisRLAmt;
1021 LastValue = ThisValue;
1022 LastGroupStartIdx = i;
1024 if (LastValue.getNode())
1025 BitGroups.push_back(BitGroup(LastValue, LastRLAmt, LastGroupStartIdx,
1028 if (BitGroups.empty())
1031 // We might be able to combine the first and last groups.
1032 if (BitGroups.size() > 1) {
1033 // If the first and last groups are the same, then remove the first group
1034 // in favor of the last group, making the ending index of the last group
1035 // equal to the ending index of the to-be-removed first group.
1036 if (BitGroups[0].StartIdx == 0 &&
1037 BitGroups[BitGroups.size()-1].EndIdx == Bits.size()-1 &&
1038 BitGroups[0].V == BitGroups[BitGroups.size()-1].V &&
1039 BitGroups[0].RLAmt == BitGroups[BitGroups.size()-1].RLAmt) {
1040 DEBUG(dbgs() << "\tcombining final bit group with inital one\n");
1041 BitGroups[BitGroups.size()-1].EndIdx = BitGroups[0].EndIdx;
1042 BitGroups.erase(BitGroups.begin());
1047 // Take all (SDValue, RLAmt) pairs and sort them by the number of groups
1048 // associated with each. If there is a degeneracy, pick the one that occurs
1049 // first (in the final value).
1050 void collectValueRotInfo() {
1053 for (auto &BG : BitGroups) {
1054 unsigned RLAmtKey = BG.RLAmt + (BG.Repl32 ? 64 : 0);
1055 ValueRotInfo &VRI = ValueRots[std::make_pair(BG.V, RLAmtKey)];
1057 VRI.RLAmt = BG.RLAmt;
1058 VRI.Repl32 = BG.Repl32;
1060 VRI.FirstGroupStartIdx = std::min(VRI.FirstGroupStartIdx, BG.StartIdx);
1063 // Now that we've collected the various ValueRotInfo instances, we need to
1065 ValueRotsVec.clear();
1066 for (auto &I : ValueRots) {
1067 ValueRotsVec.push_back(I.second);
1069 std::sort(ValueRotsVec.begin(), ValueRotsVec.end());
1072 // In 64-bit mode, rlwinm and friends have a rotation operator that
1073 // replicates the low-order 32 bits into the high-order 32-bits. The mask
1074 // indices of these instructions can only be in the lower 32 bits, so they
1075 // can only represent some 64-bit bit groups. However, when they can be used,
1076 // the 32-bit replication can be used to represent, as a single bit group,
1077 // otherwise separate bit groups. We'll convert to replicated-32-bit bit
1078 // groups when possible. Returns true if any of the bit groups were
1080 void assignRepl32BitGroups() {
1081 // If we have bits like this:
1083 // Indices: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1084 // V bits: ... 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24
1085 // Groups: | RLAmt = 8 | RLAmt = 40 |
1087 // But, making use of a 32-bit operation that replicates the low-order 32
1088 // bits into the high-order 32 bits, this can be one bit group with a RLAmt
1091 auto IsAllLow32 = [this](BitGroup & BG) {
1092 if (BG.StartIdx <= BG.EndIdx) {
1093 for (unsigned i = BG.StartIdx; i <= BG.EndIdx; ++i) {
1094 if (!Bits[i].hasValue())
1096 if (Bits[i].getValueBitIndex() >= 32)
1100 for (unsigned i = BG.StartIdx; i < Bits.size(); ++i) {
1101 if (!Bits[i].hasValue())
1103 if (Bits[i].getValueBitIndex() >= 32)
1106 for (unsigned i = 0; i <= BG.EndIdx; ++i) {
1107 if (!Bits[i].hasValue())
1109 if (Bits[i].getValueBitIndex() >= 32)
1117 for (auto &BG : BitGroups) {
1118 if (BG.StartIdx < 32 && BG.EndIdx < 32) {
1119 if (IsAllLow32(BG)) {
1120 if (BG.RLAmt >= 32) {
1127 DEBUG(dbgs() << "\t32-bit replicated bit group for " <<
1128 BG.V.getNode() << " RLAmt = " << BG.RLAmt <<
1129 " [" << BG.StartIdx << ", " << BG.EndIdx << "]\n");
1134 // Now walk through the bit groups, consolidating where possible.
1135 for (auto I = BitGroups.begin(); I != BitGroups.end();) {
1136 // We might want to remove this bit group by merging it with the previous
1137 // group (which might be the ending group).
1138 auto IP = (I == BitGroups.begin()) ?
1139 std::prev(BitGroups.end()) : std::prev(I);
1140 if (I->Repl32 && IP->Repl32 && I->V == IP->V && I->RLAmt == IP->RLAmt &&
1141 I->StartIdx == (IP->EndIdx + 1) % 64 && I != IP) {
1143 DEBUG(dbgs() << "\tcombining 32-bit replicated bit group for " <<
1144 I->V.getNode() << " RLAmt = " << I->RLAmt <<
1145 " [" << I->StartIdx << ", " << I->EndIdx <<
1146 "] with group with range [" <<
1147 IP->StartIdx << ", " << IP->EndIdx << "]\n");
1149 IP->EndIdx = I->EndIdx;
1150 IP->Repl32CR = IP->Repl32CR || I->Repl32CR;
1151 IP->Repl32Coalesced = true;
1152 I = BitGroups.erase(I);
1155 // There is a special case worth handling: If there is a single group
1156 // covering the entire upper 32 bits, and it can be merged with both
1157 // the next and previous groups (which might be the same group), then
1158 // do so. If it is the same group (so there will be only one group in
1159 // total), then we need to reverse the order of the range so that it
1160 // covers the entire 64 bits.
1161 if (I->StartIdx == 32 && I->EndIdx == 63) {
1162 assert(std::next(I) == BitGroups.end() &&
1163 "bit group ends at index 63 but there is another?");
1164 auto IN = BitGroups.begin();
1166 if (IP->Repl32 && IN->Repl32 && I->V == IP->V && I->V == IN->V &&
1167 (I->RLAmt % 32) == IP->RLAmt && (I->RLAmt % 32) == IN->RLAmt &&
1168 IP->EndIdx == 31 && IN->StartIdx == 0 && I != IP &&
1171 DEBUG(dbgs() << "\tcombining bit group for " <<
1172 I->V.getNode() << " RLAmt = " << I->RLAmt <<
1173 " [" << I->StartIdx << ", " << I->EndIdx <<
1174 "] with 32-bit replicated groups with ranges [" <<
1175 IP->StartIdx << ", " << IP->EndIdx << "] and [" <<
1176 IN->StartIdx << ", " << IN->EndIdx << "]\n");
1179 // There is only one other group; change it to cover the whole
1180 // range (backward, so that it can still be Repl32 but cover the
1181 // whole 64-bit range).
1184 IP->Repl32CR = IP->Repl32CR || I->RLAmt >= 32;
1185 IP->Repl32Coalesced = true;
1186 I = BitGroups.erase(I);
1188 // There are two separate groups, one before this group and one
1189 // after us (at the beginning). We're going to remove this group,
1190 // but also the group at the very beginning.
1191 IP->EndIdx = IN->EndIdx;
1192 IP->Repl32CR = IP->Repl32CR || IN->Repl32CR || I->RLAmt >= 32;
1193 IP->Repl32Coalesced = true;
1194 I = BitGroups.erase(I);
1195 BitGroups.erase(BitGroups.begin());
1198 // This must be the last group in the vector (and we might have
1199 // just invalidated the iterator above), so break here.
1209 SDValue getI32Imm(unsigned Imm) {
1210 return CurDAG->getTargetConstant(Imm, MVT::i32);
1213 uint64_t getZerosMask() {
1215 for (unsigned i = 0; i < Bits.size(); ++i) {
1216 if (Bits[i].hasValue())
1218 Mask |= (UINT64_C(1) << i);
1224 // Depending on the number of groups for a particular value, it might be
1225 // better to rotate, mask explicitly (using andi/andis), and then or the
1226 // result. Select this part of the result first.
1227 void SelectAndParts32(SDLoc dl, SDValue &Res, unsigned *InstCnt) {
1228 if (BPermRewriterNoMasking)
1231 for (ValueRotInfo &VRI : ValueRotsVec) {
1233 for (unsigned i = 0; i < Bits.size(); ++i) {
1234 if (!Bits[i].hasValue() || Bits[i].getValue() != VRI.V)
1236 if (RLAmt[i] != VRI.RLAmt)
1241 // Compute the masks for andi/andis that would be necessary.
1242 unsigned ANDIMask = (Mask & UINT16_MAX), ANDISMask = Mask >> 16;
1243 assert((ANDIMask != 0 || ANDISMask != 0) &&
1244 "No set bits in mask for value bit groups");
1245 bool NeedsRotate = VRI.RLAmt != 0;
1247 // We're trying to minimize the number of instructions. If we have one
1248 // group, using one of andi/andis can break even. If we have three
1249 // groups, we can use both andi and andis and break even (to use both
1250 // andi and andis we also need to or the results together). We need four
1251 // groups if we also need to rotate. To use andi/andis we need to do more
1252 // than break even because rotate-and-mask instructions tend to be easier
1255 // FIXME: We've biased here against using andi/andis, which is right for
1256 // POWER cores, but not optimal everywhere. For example, on the A2,
1257 // andi/andis have single-cycle latency whereas the rotate-and-mask
1258 // instructions take two cycles, and it would be better to bias toward
1259 // andi/andis in break-even cases.
1261 unsigned NumAndInsts = (unsigned) NeedsRotate +
1262 (unsigned) (ANDIMask != 0) +
1263 (unsigned) (ANDISMask != 0) +
1264 (unsigned) (ANDIMask != 0 && ANDISMask != 0) +
1265 (unsigned) (bool) Res;
1267 DEBUG(dbgs() << "\t\trotation groups for " << VRI.V.getNode() <<
1268 " RL: " << VRI.RLAmt << ":" <<
1269 "\n\t\t\tisel using masking: " << NumAndInsts <<
1270 " using rotates: " << VRI.NumGroups << "\n");
1272 if (NumAndInsts >= VRI.NumGroups)
1275 DEBUG(dbgs() << "\t\t\t\tusing masking\n");
1277 if (InstCnt) *InstCnt += NumAndInsts;
1282 { VRI.V, getI32Imm(VRI.RLAmt), getI32Imm(0), getI32Imm(31) };
1283 VRot = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32,
1289 SDValue ANDIVal, ANDISVal;
1291 ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo, dl, MVT::i32,
1292 VRot, getI32Imm(ANDIMask)), 0);
1294 ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo, dl, MVT::i32,
1295 VRot, getI32Imm(ANDISMask)), 0);
1299 TotalVal = ANDISVal;
1303 TotalVal = SDValue(CurDAG->getMachineNode(PPC::OR, dl, MVT::i32,
1304 ANDIVal, ANDISVal), 0);
1309 Res = SDValue(CurDAG->getMachineNode(PPC::OR, dl, MVT::i32,
1312 // Now, remove all groups with this underlying value and rotation
1314 for (auto I = BitGroups.begin(); I != BitGroups.end();) {
1315 if (I->V == VRI.V && I->RLAmt == VRI.RLAmt)
1316 I = BitGroups.erase(I);
1323 // Instruction selection for the 32-bit case.
1324 SDNode *Select32(SDNode *N, bool LateMask, unsigned *InstCnt) {
1328 if (InstCnt) *InstCnt = 0;
1330 // Take care of cases that should use andi/andis first.
1331 SelectAndParts32(dl, Res, InstCnt);
1333 // If we've not yet selected a 'starting' instruction, and we have no zeros
1334 // to fill in, select the (Value, RLAmt) with the highest priority (largest
1335 // number of groups), and start with this rotated value.
1336 if ((!HasZeros || LateMask) && !Res) {
1337 ValueRotInfo &VRI = ValueRotsVec[0];
1339 if (InstCnt) *InstCnt += 1;
1341 { VRI.V, getI32Imm(VRI.RLAmt), getI32Imm(0), getI32Imm(31) };
1342 Res = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0);
1347 // Now, remove all groups with this underlying value and rotation factor.
1348 for (auto I = BitGroups.begin(); I != BitGroups.end();) {
1349 if (I->V == VRI.V && I->RLAmt == VRI.RLAmt)
1350 I = BitGroups.erase(I);
1356 if (InstCnt) *InstCnt += BitGroups.size();
1358 // Insert the other groups (one at a time).
1359 for (auto &BG : BitGroups) {
1362 { BG.V, getI32Imm(BG.RLAmt), getI32Imm(Bits.size() - BG.EndIdx - 1),
1363 getI32Imm(Bits.size() - BG.StartIdx - 1) };
1364 Res = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0);
1367 { Res, BG.V, getI32Imm(BG.RLAmt), getI32Imm(Bits.size() - BG.EndIdx - 1),
1368 getI32Imm(Bits.size() - BG.StartIdx - 1) };
1369 Res = SDValue(CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops), 0);
1374 unsigned Mask = (unsigned) getZerosMask();
1376 unsigned ANDIMask = (Mask & UINT16_MAX), ANDISMask = Mask >> 16;
1377 assert((ANDIMask != 0 || ANDISMask != 0) &&
1378 "No set bits in zeros mask?");
1380 if (InstCnt) *InstCnt += (unsigned) (ANDIMask != 0) +
1381 (unsigned) (ANDISMask != 0) +
1382 (unsigned) (ANDIMask != 0 && ANDISMask != 0);
1384 SDValue ANDIVal, ANDISVal;
1386 ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo, dl, MVT::i32,
1387 Res, getI32Imm(ANDIMask)), 0);
1389 ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo, dl, MVT::i32,
1390 Res, getI32Imm(ANDISMask)), 0);
1397 Res = SDValue(CurDAG->getMachineNode(PPC::OR, dl, MVT::i32,
1398 ANDIVal, ANDISVal), 0);
1401 return Res.getNode();
1404 unsigned SelectRotMask64Count(unsigned RLAmt, bool Repl32,
1405 unsigned MaskStart, unsigned MaskEnd,
1407 // In the notation used by the instructions, 'start' and 'end' are reversed
1408 // because bits are counted from high to low order.
1409 unsigned InstMaskStart = 64 - MaskEnd - 1,
1410 InstMaskEnd = 64 - MaskStart - 1;
1415 if ((!IsIns && (InstMaskEnd == 63 || InstMaskStart == 0)) ||
1416 InstMaskEnd == 63 - RLAmt)
1422 // For 64-bit values, not all combinations of rotates and masks are
1423 // available. Produce one if it is available.
1424 SDValue SelectRotMask64(SDValue V, SDLoc dl, unsigned RLAmt, bool Repl32,
1425 unsigned MaskStart, unsigned MaskEnd,
1426 unsigned *InstCnt = nullptr) {
1427 // In the notation used by the instructions, 'start' and 'end' are reversed
1428 // because bits are counted from high to low order.
1429 unsigned InstMaskStart = 64 - MaskEnd - 1,
1430 InstMaskEnd = 64 - MaskStart - 1;
1432 if (InstCnt) *InstCnt += 1;
1435 // This rotation amount assumes that the lower 32 bits of the quantity
1436 // are replicated in the high 32 bits by the rotation operator (which is
1437 // done by rlwinm and friends).
1438 assert(InstMaskStart >= 32 && "Mask cannot start out of range");
1439 assert(InstMaskEnd >= 32 && "Mask cannot end out of range");
1441 { V, getI32Imm(RLAmt), getI32Imm(InstMaskStart - 32),
1442 getI32Imm(InstMaskEnd - 32) };
1443 return SDValue(CurDAG->getMachineNode(PPC::RLWINM8, dl, MVT::i64,
1447 if (InstMaskEnd == 63) {
1449 { V, getI32Imm(RLAmt), getI32Imm(InstMaskStart) };
1450 return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Ops), 0);
1453 if (InstMaskStart == 0) {
1455 { V, getI32Imm(RLAmt), getI32Imm(InstMaskEnd) };
1456 return SDValue(CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64, Ops), 0);
1459 if (InstMaskEnd == 63 - RLAmt) {
1461 { V, getI32Imm(RLAmt), getI32Imm(InstMaskStart) };
1462 return SDValue(CurDAG->getMachineNode(PPC::RLDIC, dl, MVT::i64, Ops), 0);
1465 // We cannot do this with a single instruction, so we'll use two. The
1466 // problem is that we're not free to choose both a rotation amount and mask
1467 // start and end independently. We can choose an arbitrary mask start and
1468 // end, but then the rotation amount is fixed. Rotation, however, can be
1469 // inverted, and so by applying an "inverse" rotation first, we can get the
1471 if (InstCnt) *InstCnt += 1;
1473 // The rotation mask for the second instruction must be MaskStart.
1474 unsigned RLAmt2 = MaskStart;
1475 // The first instruction must rotate V so that the overall rotation amount
1477 unsigned RLAmt1 = (64 + RLAmt - RLAmt2) % 64;
1479 V = SelectRotMask64(V, dl, RLAmt1, false, 0, 63);
1480 return SelectRotMask64(V, dl, RLAmt2, false, MaskStart, MaskEnd);
1483 // For 64-bit values, not all combinations of rotates and masks are
1484 // available. Produce a rotate-mask-and-insert if one is available.
1485 SDValue SelectRotMaskIns64(SDValue Base, SDValue V, SDLoc dl, unsigned RLAmt,
1486 bool Repl32, unsigned MaskStart,
1487 unsigned MaskEnd, unsigned *InstCnt = nullptr) {
1488 // In the notation used by the instructions, 'start' and 'end' are reversed
1489 // because bits are counted from high to low order.
1490 unsigned InstMaskStart = 64 - MaskEnd - 1,
1491 InstMaskEnd = 64 - MaskStart - 1;
1493 if (InstCnt) *InstCnt += 1;
1496 // This rotation amount assumes that the lower 32 bits of the quantity
1497 // are replicated in the high 32 bits by the rotation operator (which is
1498 // done by rlwinm and friends).
1499 assert(InstMaskStart >= 32 && "Mask cannot start out of range");
1500 assert(InstMaskEnd >= 32 && "Mask cannot end out of range");
1502 { Base, V, getI32Imm(RLAmt), getI32Imm(InstMaskStart - 32),
1503 getI32Imm(InstMaskEnd - 32) };
1504 return SDValue(CurDAG->getMachineNode(PPC::RLWIMI8, dl, MVT::i64,
1508 if (InstMaskEnd == 63 - RLAmt) {
1510 { Base, V, getI32Imm(RLAmt), getI32Imm(InstMaskStart) };
1511 return SDValue(CurDAG->getMachineNode(PPC::RLDIMI, dl, MVT::i64, Ops), 0);
1514 // We cannot do this with a single instruction, so we'll use two. The
1515 // problem is that we're not free to choose both a rotation amount and mask
1516 // start and end independently. We can choose an arbitrary mask start and
1517 // end, but then the rotation amount is fixed. Rotation, however, can be
1518 // inverted, and so by applying an "inverse" rotation first, we can get the
1520 if (InstCnt) *InstCnt += 1;
1522 // The rotation mask for the second instruction must be MaskStart.
1523 unsigned RLAmt2 = MaskStart;
1524 // The first instruction must rotate V so that the overall rotation amount
1526 unsigned RLAmt1 = (64 + RLAmt - RLAmt2) % 64;
1528 V = SelectRotMask64(V, dl, RLAmt1, false, 0, 63);
1529 return SelectRotMaskIns64(Base, V, dl, RLAmt2, false, MaskStart, MaskEnd);
1532 void SelectAndParts64(SDLoc dl, SDValue &Res, unsigned *InstCnt) {
1533 if (BPermRewriterNoMasking)
1536 // The idea here is the same as in the 32-bit version, but with additional
1537 // complications from the fact that Repl32 might be true. Because we
1538 // aggressively convert bit groups to Repl32 form (which, for small
1539 // rotation factors, involves no other change), and then coalesce, it might
1540 // be the case that a single 64-bit masking operation could handle both
1541 // some Repl32 groups and some non-Repl32 groups. If converting to Repl32
1542 // form allowed coalescing, then we must use a 32-bit rotaton in order to
1543 // completely capture the new combined bit group.
1545 for (ValueRotInfo &VRI : ValueRotsVec) {
1548 // We need to add to the mask all bits from the associated bit groups.
1549 // If Repl32 is false, we need to add bits from bit groups that have
1550 // Repl32 true, but are trivially convertable to Repl32 false. Such a
1551 // group is trivially convertable if it overlaps only with the lower 32
1552 // bits, and the group has not been coalesced.
1553 auto MatchingBG = [VRI](BitGroup &BG) {
1557 unsigned EffRLAmt = BG.RLAmt;
1558 if (!VRI.Repl32 && BG.Repl32) {
1559 if (BG.StartIdx < 32 && BG.EndIdx < 32 && BG.StartIdx <= BG.EndIdx &&
1560 !BG.Repl32Coalesced) {
1566 } else if (VRI.Repl32 != BG.Repl32) {
1570 if (VRI.RLAmt != EffRLAmt)
1576 for (auto &BG : BitGroups) {
1577 if (!MatchingBG(BG))
1580 if (BG.StartIdx <= BG.EndIdx) {
1581 for (unsigned i = BG.StartIdx; i <= BG.EndIdx; ++i)
1582 Mask |= (UINT64_C(1) << i);
1584 for (unsigned i = BG.StartIdx; i < Bits.size(); ++i)
1585 Mask |= (UINT64_C(1) << i);
1586 for (unsigned i = 0; i <= BG.EndIdx; ++i)
1587 Mask |= (UINT64_C(1) << i);
1591 // We can use the 32-bit andi/andis technique if the mask does not
1592 // require any higher-order bits. This can save an instruction compared
1593 // to always using the general 64-bit technique.
1594 bool Use32BitInsts = isUInt<32>(Mask);
1595 // Compute the masks for andi/andis that would be necessary.
1596 unsigned ANDIMask = (Mask & UINT16_MAX),
1597 ANDISMask = (Mask >> 16) & UINT16_MAX;
1599 bool NeedsRotate = VRI.RLAmt || (VRI.Repl32 && !isUInt<32>(Mask));
1601 unsigned NumAndInsts = (unsigned) NeedsRotate +
1602 (unsigned) (bool) Res;
1604 NumAndInsts += (unsigned) (ANDIMask != 0) + (unsigned) (ANDISMask != 0) +
1605 (unsigned) (ANDIMask != 0 && ANDISMask != 0);
1607 NumAndInsts += SelectInt64Count(Mask) + /* and */ 1;
1609 unsigned NumRLInsts = 0;
1610 bool FirstBG = true;
1611 for (auto &BG : BitGroups) {
1612 if (!MatchingBG(BG))
1615 SelectRotMask64Count(BG.RLAmt, BG.Repl32, BG.StartIdx, BG.EndIdx,
1620 DEBUG(dbgs() << "\t\trotation groups for " << VRI.V.getNode() <<
1621 " RL: " << VRI.RLAmt << (VRI.Repl32 ? " (32):" : ":") <<
1622 "\n\t\t\tisel using masking: " << NumAndInsts <<
1623 " using rotates: " << NumRLInsts << "\n");
1625 // When we'd use andi/andis, we bias toward using the rotates (andi only
1626 // has a record form, and is cracked on POWER cores). However, when using
1627 // general 64-bit constant formation, bias toward the constant form,
1628 // because that exposes more opportunities for CSE.
1629 if (NumAndInsts > NumRLInsts)
1631 if (Use32BitInsts && NumAndInsts == NumRLInsts)
1634 DEBUG(dbgs() << "\t\t\t\tusing masking\n");
1636 if (InstCnt) *InstCnt += NumAndInsts;
1639 // We actually need to generate a rotation if we have a non-zero rotation
1640 // factor or, in the Repl32 case, if we care about any of the
1641 // higher-order replicated bits. In the latter case, we generate a mask
1642 // backward so that it actually includes the entire 64 bits.
1643 if (VRI.RLAmt || (VRI.Repl32 && !isUInt<32>(Mask)))
1644 VRot = SelectRotMask64(VRI.V, dl, VRI.RLAmt, VRI.Repl32,
1645 VRI.Repl32 ? 31 : 0, VRI.Repl32 ? 30 : 63);
1650 if (Use32BitInsts) {
1651 assert((ANDIMask != 0 || ANDISMask != 0) &&
1652 "No set bits in mask when using 32-bit ands for 64-bit value");
1654 SDValue ANDIVal, ANDISVal;
1656 ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo8, dl, MVT::i64,
1657 VRot, getI32Imm(ANDIMask)), 0);
1659 ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo8, dl, MVT::i64,
1660 VRot, getI32Imm(ANDISMask)), 0);
1663 TotalVal = ANDISVal;
1667 TotalVal = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
1668 ANDIVal, ANDISVal), 0);
1670 TotalVal = SDValue(SelectInt64(CurDAG, dl, Mask), 0);
1672 SDValue(CurDAG->getMachineNode(PPC::AND8, dl, MVT::i64,
1673 VRot, TotalVal), 0);
1679 Res = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
1682 // Now, remove all groups with this underlying value and rotation
1684 for (auto I = BitGroups.begin(); I != BitGroups.end();) {
1686 I = BitGroups.erase(I);
1693 // Instruction selection for the 64-bit case.
1694 SDNode *Select64(SDNode *N, bool LateMask, unsigned *InstCnt) {
1698 if (InstCnt) *InstCnt = 0;
1700 // Take care of cases that should use andi/andis first.
1701 SelectAndParts64(dl, Res, InstCnt);
1703 // If we've not yet selected a 'starting' instruction, and we have no zeros
1704 // to fill in, select the (Value, RLAmt) with the highest priority (largest
1705 // number of groups), and start with this rotated value.
1706 if ((!HasZeros || LateMask) && !Res) {
1707 // If we have both Repl32 groups and non-Repl32 groups, the non-Repl32
1708 // groups will come first, and so the VRI representing the largest number
1709 // of groups might not be first (it might be the first Repl32 groups).
1710 unsigned MaxGroupsIdx = 0;
1711 if (!ValueRotsVec[0].Repl32) {
1712 for (unsigned i = 0, ie = ValueRotsVec.size(); i < ie; ++i)
1713 if (ValueRotsVec[i].Repl32) {
1714 if (ValueRotsVec[i].NumGroups > ValueRotsVec[0].NumGroups)
1720 ValueRotInfo &VRI = ValueRotsVec[MaxGroupsIdx];
1721 bool NeedsRotate = false;
1724 } else if (VRI.Repl32) {
1725 for (auto &BG : BitGroups) {
1726 if (BG.V != VRI.V || BG.RLAmt != VRI.RLAmt ||
1727 BG.Repl32 != VRI.Repl32)
1730 // We don't need a rotate if the bit group is confined to the lower
1732 if (BG.StartIdx < 32 && BG.EndIdx < 32 && BG.StartIdx < BG.EndIdx)
1741 Res = SelectRotMask64(VRI.V, dl, VRI.RLAmt, VRI.Repl32,
1742 VRI.Repl32 ? 31 : 0, VRI.Repl32 ? 30 : 63,
1747 // Now, remove all groups with this underlying value and rotation factor.
1749 for (auto I = BitGroups.begin(); I != BitGroups.end();) {
1750 if (I->V == VRI.V && I->RLAmt == VRI.RLAmt && I->Repl32 == VRI.Repl32)
1751 I = BitGroups.erase(I);
1757 // Because 64-bit rotates are more flexible than inserts, we might have a
1758 // preference regarding which one we do first (to save one instruction).
1760 for (auto I = BitGroups.begin(), IE = BitGroups.end(); I != IE; ++I) {
1761 if (SelectRotMask64Count(I->RLAmt, I->Repl32, I->StartIdx, I->EndIdx,
1763 SelectRotMask64Count(I->RLAmt, I->Repl32, I->StartIdx, I->EndIdx,
1765 if (I != BitGroups.begin()) {
1768 BitGroups.insert(BitGroups.begin(), BG);
1775 // Insert the other groups (one at a time).
1776 for (auto &BG : BitGroups) {
1778 Res = SelectRotMask64(BG.V, dl, BG.RLAmt, BG.Repl32, BG.StartIdx,
1779 BG.EndIdx, InstCnt);
1781 Res = SelectRotMaskIns64(Res, BG.V, dl, BG.RLAmt, BG.Repl32,
1782 BG.StartIdx, BG.EndIdx, InstCnt);
1786 uint64_t Mask = getZerosMask();
1788 // We can use the 32-bit andi/andis technique if the mask does not
1789 // require any higher-order bits. This can save an instruction compared
1790 // to always using the general 64-bit technique.
1791 bool Use32BitInsts = isUInt<32>(Mask);
1792 // Compute the masks for andi/andis that would be necessary.
1793 unsigned ANDIMask = (Mask & UINT16_MAX),
1794 ANDISMask = (Mask >> 16) & UINT16_MAX;
1796 if (Use32BitInsts) {
1797 assert((ANDIMask != 0 || ANDISMask != 0) &&
1798 "No set bits in mask when using 32-bit ands for 64-bit value");
1800 if (InstCnt) *InstCnt += (unsigned) (ANDIMask != 0) +
1801 (unsigned) (ANDISMask != 0) +
1802 (unsigned) (ANDIMask != 0 && ANDISMask != 0);
1804 SDValue ANDIVal, ANDISVal;
1806 ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo8, dl, MVT::i64,
1807 Res, getI32Imm(ANDIMask)), 0);
1809 ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo8, dl, MVT::i64,
1810 Res, getI32Imm(ANDISMask)), 0);
1817 Res = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
1818 ANDIVal, ANDISVal), 0);
1820 if (InstCnt) *InstCnt += SelectInt64Count(Mask) + /* and */ 1;
1822 SDValue MaskVal = SDValue(SelectInt64(CurDAG, dl, Mask), 0);
1824 SDValue(CurDAG->getMachineNode(PPC::AND8, dl, MVT::i64,
1829 return Res.getNode();
1832 SDNode *Select(SDNode *N, bool LateMask, unsigned *InstCnt = nullptr) {
1833 // Fill in BitGroups.
1834 collectBitGroups(LateMask);
1835 if (BitGroups.empty())
1838 // For 64-bit values, figure out when we can use 32-bit instructions.
1839 if (Bits.size() == 64)
1840 assignRepl32BitGroups();
1842 // Fill in ValueRotsVec.
1843 collectValueRotInfo();
1845 if (Bits.size() == 32) {
1846 return Select32(N, LateMask, InstCnt);
1848 assert(Bits.size() == 64 && "Not 64 bits here?");
1849 return Select64(N, LateMask, InstCnt);
1855 SmallVector<ValueBit, 64> Bits;
1858 SmallVector<unsigned, 64> RLAmt;
1860 SmallVector<BitGroup, 16> BitGroups;
1862 DenseMap<std::pair<SDValue, unsigned>, ValueRotInfo> ValueRots;
1863 SmallVector<ValueRotInfo, 16> ValueRotsVec;
1865 SelectionDAG *CurDAG;
1868 BitPermutationSelector(SelectionDAG *DAG)
1871 // Here we try to match complex bit permutations into a set of
1872 // rotate-and-shift/shift/and/or instructions, using a set of heuristics
1873 // known to produce optimial code for common cases (like i32 byte swapping).
1874 SDNode *Select(SDNode *N) {
1875 Bits.resize(N->getValueType(0).getSizeInBits());
1876 if (!getValueBits(SDValue(N, 0), Bits))
1879 DEBUG(dbgs() << "Considering bit-permutation-based instruction"
1880 " selection for: ");
1881 DEBUG(N->dump(CurDAG));
1883 // Fill it RLAmt and set HasZeros.
1884 computeRotationAmounts();
1887 return Select(N, false);
1889 // We currently have two techniques for handling results with zeros: early
1890 // masking (the default) and late masking. Late masking is sometimes more
1891 // efficient, but because the structure of the bit groups is different, it
1892 // is hard to tell without generating both and comparing the results. With
1893 // late masking, we ignore zeros in the resulting value when inserting each
1894 // set of bit groups, and then mask in the zeros at the end. With early
1895 // masking, we only insert the non-zero parts of the result at every step.
1897 unsigned InstCnt, InstCntLateMask;
1898 DEBUG(dbgs() << "\tEarly masking:\n");
1899 SDNode *RN = Select(N, false, &InstCnt);
1900 DEBUG(dbgs() << "\t\tisel would use " << InstCnt << " instructions\n");
1902 DEBUG(dbgs() << "\tLate masking:\n");
1903 SDNode *RNLM = Select(N, true, &InstCntLateMask);
1904 DEBUG(dbgs() << "\t\tisel would use " << InstCntLateMask <<
1907 if (InstCnt <= InstCntLateMask) {
1908 DEBUG(dbgs() << "\tUsing early-masking for isel\n");
1912 DEBUG(dbgs() << "\tUsing late-masking for isel\n");
1916 } // anonymous namespace
1918 SDNode *PPCDAGToDAGISel::SelectBitPermutation(SDNode *N) {
1919 if (N->getValueType(0) != MVT::i32 &&
1920 N->getValueType(0) != MVT::i64)
1923 if (!UseBitPermRewriter)
1926 switch (N->getOpcode()) {
1933 BitPermutationSelector BPS(CurDAG);
1934 return BPS.Select(N);
1941 /// SelectCC - Select a comparison of the specified values with the specified
1942 /// condition code, returning the CR# of the expression.
1943 SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS,
1944 ISD::CondCode CC, SDLoc dl) {
1945 // Always select the LHS.
1948 if (LHS.getValueType() == MVT::i32) {
1950 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1951 if (isInt32Immediate(RHS, Imm)) {
1952 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
1953 if (isUInt<16>(Imm))
1954 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
1955 getI32Imm(Imm & 0xFFFF)), 0);
1956 // If this is a 16-bit signed immediate, fold it.
1957 if (isInt<16>((int)Imm))
1958 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
1959 getI32Imm(Imm & 0xFFFF)), 0);
1961 // For non-equality comparisons, the default code would materialize the
1962 // constant, then compare against it, like this:
1964 // ori r2, r2, 22136
1966 // Since we are just comparing for equality, we can emit this instead:
1967 // xoris r0,r3,0x1234
1968 // cmplwi cr0,r0,0x5678
1970 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS, dl, MVT::i32, LHS,
1971 getI32Imm(Imm >> 16)), 0);
1972 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, Xor,
1973 getI32Imm(Imm & 0xFFFF)), 0);
1976 } else if (ISD::isUnsignedIntSetCC(CC)) {
1977 if (isInt32Immediate(RHS, Imm) && isUInt<16>(Imm))
1978 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
1979 getI32Imm(Imm & 0xFFFF)), 0);
1983 if (isIntS16Immediate(RHS, SImm))
1984 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
1985 getI32Imm((int)SImm & 0xFFFF)),
1989 } else if (LHS.getValueType() == MVT::i64) {
1991 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1992 if (isInt64Immediate(RHS.getNode(), Imm)) {
1993 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
1994 if (isUInt<16>(Imm))
1995 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
1996 getI32Imm(Imm & 0xFFFF)), 0);
1997 // If this is a 16-bit signed immediate, fold it.
1999 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
2000 getI32Imm(Imm & 0xFFFF)), 0);
2002 // For non-equality comparisons, the default code would materialize the
2003 // constant, then compare against it, like this:
2005 // ori r2, r2, 22136
2007 // Since we are just comparing for equality, we can emit this instead:
2008 // xoris r0,r3,0x1234
2009 // cmpldi cr0,r0,0x5678
2011 if (isUInt<32>(Imm)) {
2012 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS8, dl, MVT::i64, LHS,
2013 getI64Imm(Imm >> 16)), 0);
2014 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, Xor,
2015 getI64Imm(Imm & 0xFFFF)), 0);
2019 } else if (ISD::isUnsignedIntSetCC(CC)) {
2020 if (isInt64Immediate(RHS.getNode(), Imm) && isUInt<16>(Imm))
2021 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
2022 getI64Imm(Imm & 0xFFFF)), 0);
2026 if (isIntS16Immediate(RHS, SImm))
2027 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
2028 getI64Imm(SImm & 0xFFFF)),
2032 } else if (LHS.getValueType() == MVT::f32) {
2035 assert(LHS.getValueType() == MVT::f64 && "Unknown vt!");
2036 Opc = PPCSubTarget->hasVSX() ? PPC::XSCMPUDP : PPC::FCMPUD;
2038 return SDValue(CurDAG->getMachineNode(Opc, dl, MVT::i32, LHS, RHS), 0);
2041 static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {
2047 llvm_unreachable("Should be lowered by legalize!");
2048 default: llvm_unreachable("Unknown condition!");
2050 case ISD::SETEQ: return PPC::PRED_EQ;
2052 case ISD::SETNE: return PPC::PRED_NE;
2054 case ISD::SETLT: return PPC::PRED_LT;
2056 case ISD::SETLE: return PPC::PRED_LE;
2058 case ISD::SETGT: return PPC::PRED_GT;
2060 case ISD::SETGE: return PPC::PRED_GE;
2061 case ISD::SETO: return PPC::PRED_NU;
2062 case ISD::SETUO: return PPC::PRED_UN;
2063 // These two are invalid for floating point. Assume we have int.
2064 case ISD::SETULT: return PPC::PRED_LT;
2065 case ISD::SETUGT: return PPC::PRED_GT;
2069 /// getCRIdxForSetCC - Return the index of the condition register field
2070 /// associated with the SetCC condition, and whether or not the field is
2071 /// treated as inverted. That is, lt = 0; ge = 0 inverted.
2072 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert) {
2075 default: llvm_unreachable("Unknown condition!");
2077 case ISD::SETLT: return 0; // Bit #0 = SETOLT
2079 case ISD::SETGT: return 1; // Bit #1 = SETOGT
2081 case ISD::SETEQ: return 2; // Bit #2 = SETOEQ
2082 case ISD::SETUO: return 3; // Bit #3 = SETUO
2084 case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE
2086 case ISD::SETLE: Invert = true; return 1; // !Bit #1 = SETULE
2088 case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE
2089 case ISD::SETO: Invert = true; return 3; // !Bit #3 = SETO
2094 llvm_unreachable("Invalid branch code: should be expanded by legalize");
2095 // These are invalid for floating point. Assume integer.
2096 case ISD::SETULT: return 0;
2097 case ISD::SETUGT: return 1;
2101 // getVCmpInst: return the vector compare instruction for the specified
2102 // vector type and condition code. Since this is for altivec specific code,
2103 // only support the altivec types (v16i8, v8i16, v4i32, and v4f32).
2104 static unsigned int getVCmpInst(MVT VecVT, ISD::CondCode CC,
2105 bool HasVSX, bool &Swap, bool &Negate) {
2109 if (VecVT.isFloatingPoint()) {
2110 /* Handle some cases by swapping input operands. */
2112 case ISD::SETLE: CC = ISD::SETGE; Swap = true; break;
2113 case ISD::SETLT: CC = ISD::SETGT; Swap = true; break;
2114 case ISD::SETOLE: CC = ISD::SETOGE; Swap = true; break;
2115 case ISD::SETOLT: CC = ISD::SETOGT; Swap = true; break;
2116 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break;
2117 case ISD::SETUGT: CC = ISD::SETULT; Swap = true; break;
2120 /* Handle some cases by negating the result. */
2122 case ISD::SETNE: CC = ISD::SETEQ; Negate = true; break;
2123 case ISD::SETUNE: CC = ISD::SETOEQ; Negate = true; break;
2124 case ISD::SETULE: CC = ISD::SETOGT; Negate = true; break;
2125 case ISD::SETULT: CC = ISD::SETOGE; Negate = true; break;
2128 /* We have instructions implementing the remaining cases. */
2132 if (VecVT == MVT::v4f32)
2133 return HasVSX ? PPC::XVCMPEQSP : PPC::VCMPEQFP;
2134 else if (VecVT == MVT::v2f64)
2135 return PPC::XVCMPEQDP;
2139 if (VecVT == MVT::v4f32)
2140 return HasVSX ? PPC::XVCMPGTSP : PPC::VCMPGTFP;
2141 else if (VecVT == MVT::v2f64)
2142 return PPC::XVCMPGTDP;
2146 if (VecVT == MVT::v4f32)
2147 return HasVSX ? PPC::XVCMPGESP : PPC::VCMPGEFP;
2148 else if (VecVT == MVT::v2f64)
2149 return PPC::XVCMPGEDP;
2154 llvm_unreachable("Invalid floating-point vector compare condition");
2156 /* Handle some cases by swapping input operands. */
2158 case ISD::SETGE: CC = ISD::SETLE; Swap = true; break;
2159 case ISD::SETLT: CC = ISD::SETGT; Swap = true; break;
2160 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break;
2161 case ISD::SETULT: CC = ISD::SETUGT; Swap = true; break;
2164 /* Handle some cases by negating the result. */
2166 case ISD::SETNE: CC = ISD::SETEQ; Negate = true; break;
2167 case ISD::SETUNE: CC = ISD::SETUEQ; Negate = true; break;
2168 case ISD::SETLE: CC = ISD::SETGT; Negate = true; break;
2169 case ISD::SETULE: CC = ISD::SETUGT; Negate = true; break;
2172 /* We have instructions implementing the remaining cases. */
2176 if (VecVT == MVT::v16i8)
2177 return PPC::VCMPEQUB;
2178 else if (VecVT == MVT::v8i16)
2179 return PPC::VCMPEQUH;
2180 else if (VecVT == MVT::v4i32)
2181 return PPC::VCMPEQUW;
2184 if (VecVT == MVT::v16i8)
2185 return PPC::VCMPGTSB;
2186 else if (VecVT == MVT::v8i16)
2187 return PPC::VCMPGTSH;
2188 else if (VecVT == MVT::v4i32)
2189 return PPC::VCMPGTSW;
2192 if (VecVT == MVT::v16i8)
2193 return PPC::VCMPGTUB;
2194 else if (VecVT == MVT::v8i16)
2195 return PPC::VCMPGTUH;
2196 else if (VecVT == MVT::v4i32)
2197 return PPC::VCMPGTUW;
2202 llvm_unreachable("Invalid integer vector compare condition");
2206 SDNode *PPCDAGToDAGISel::SelectSETCC(SDNode *N) {
2209 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
2210 EVT PtrVT = CurDAG->getTargetLoweringInfo().getPointerTy();
2211 bool isPPC64 = (PtrVT == MVT::i64);
2213 if (!PPCSubTarget->useCRBits() &&
2214 isInt32Immediate(N->getOperand(1), Imm)) {
2215 // We can codegen setcc op, imm very efficiently compared to a brcond.
2216 // Check for those cases here.
2219 SDValue Op = N->getOperand(0);
2223 Op = SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Op), 0);
2224 SDValue Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) };
2225 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2230 SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
2231 Op, getI32Imm(~0U)), 0);
2232 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
2236 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
2237 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2241 SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Op), 0);
2242 T = SDValue(CurDAG->getMachineNode(PPC::ANDC, dl, MVT::i32, T, Op), 0);
2243 SDValue Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
2244 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2247 } else if (Imm == ~0U) { // setcc op, -1
2248 SDValue Op = N->getOperand(0);
2253 Op = SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
2254 Op, getI32Imm(1)), 0);
2255 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
2256 SDValue(CurDAG->getMachineNode(PPC::LI, dl,
2262 Op = SDValue(CurDAG->getMachineNode(PPC::NOR, dl, MVT::i32, Op, Op), 0);
2263 SDNode *AD = CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
2264 Op, getI32Imm(~0U));
2265 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0),
2266 Op, SDValue(AD, 1));
2269 SDValue AD = SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Op,
2271 SDValue AN = SDValue(CurDAG->getMachineNode(PPC::AND, dl, MVT::i32, AD,
2273 SDValue Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
2274 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2277 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
2278 Op = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops),
2280 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op,
2287 SDValue LHS = N->getOperand(0);
2288 SDValue RHS = N->getOperand(1);
2290 // Altivec Vector compare instructions do not set any CR register by default and
2291 // vector compare operations return the same type as the operands.
2292 if (LHS.getValueType().isVector()) {
2293 EVT VecVT = LHS.getValueType();
2295 unsigned int VCmpInst = getVCmpInst(VecVT.getSimpleVT(), CC,
2296 PPCSubTarget->hasVSX(), Swap, Negate);
2298 std::swap(LHS, RHS);
2301 SDValue VCmp(CurDAG->getMachineNode(VCmpInst, dl, VecVT, LHS, RHS), 0);
2302 return CurDAG->SelectNodeTo(N, PPCSubTarget->hasVSX() ? PPC::XXLNOR :
2307 return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS);
2310 if (PPCSubTarget->useCRBits())
2314 unsigned Idx = getCRIdxForSetCC(CC, Inv);
2315 SDValue CCReg = SelectCC(LHS, RHS, CC, dl);
2318 // Force the ccreg into CR7.
2319 SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
2321 SDValue InFlag(nullptr, 0); // Null incoming flag value.
2322 CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, CR7Reg, CCReg,
2323 InFlag).getValue(1);
2325 IntCR = SDValue(CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg,
2328 SDValue Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31),
2329 getI32Imm(31), getI32Imm(31) };
2331 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2333 // Get the specified bit.
2335 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0);
2336 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
2340 // Select - Convert the specified operand from a target-independent to a
2341 // target-specific node if it hasn't already been changed.
2342 SDNode *PPCDAGToDAGISel::Select(SDNode *N) {
2344 if (N->isMachineOpcode()) {
2346 return nullptr; // Already selected.
2349 // In case any misguided DAG-level optimizations form an ADD with a
2350 // TargetConstant operand, crash here instead of miscompiling (by selecting
2351 // an r+r add instead of some kind of r+i add).
2352 if (N->getOpcode() == ISD::ADD &&
2353 N->getOperand(1).getOpcode() == ISD::TargetConstant)
2354 llvm_unreachable("Invalid ADD with TargetConstant operand");
2356 // Try matching complex bit permutations before doing anything else.
2357 if (SDNode *NN = SelectBitPermutation(N))
2360 switch (N->getOpcode()) {
2363 case ISD::Constant: {
2364 if (N->getValueType(0) == MVT::i64)
2365 return SelectInt64(CurDAG, N);
2370 SDNode *SN = SelectSETCC(N);
2375 case PPCISD::GlobalBaseReg:
2376 return getGlobalBaseReg();
2378 case ISD::FrameIndex:
2379 return getFrameIndex(N, N);
2381 case PPCISD::MFOCRF: {
2382 SDValue InFlag = N->getOperand(1);
2383 return CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32,
2384 N->getOperand(0), InFlag);
2387 case PPCISD::READ_TIME_BASE: {
2388 return CurDAG->getMachineNode(PPC::ReadTB, dl, MVT::i32, MVT::i32,
2389 MVT::Other, N->getOperand(0));
2392 case PPCISD::SRA_ADDZE: {
2393 SDValue N0 = N->getOperand(0);
2395 CurDAG->getTargetConstant(*cast<ConstantSDNode>(N->getOperand(1))->
2396 getConstantIntValue(), N->getValueType(0));
2397 if (N->getValueType(0) == MVT::i64) {
2399 CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, MVT::Glue,
2401 return CurDAG->SelectNodeTo(N, PPC::ADDZE8, MVT::i64,
2402 SDValue(Op, 0), SDValue(Op, 1));
2404 assert(N->getValueType(0) == MVT::i32 &&
2405 "Expecting i64 or i32 in PPCISD::SRA_ADDZE");
2407 CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Glue,
2409 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
2410 SDValue(Op, 0), SDValue(Op, 1));
2415 // Handle preincrement loads.
2416 LoadSDNode *LD = cast<LoadSDNode>(N);
2417 EVT LoadedVT = LD->getMemoryVT();
2419 // Normal loads are handled by code generated from the .td file.
2420 if (LD->getAddressingMode() != ISD::PRE_INC)
2423 SDValue Offset = LD->getOffset();
2424 if (Offset.getOpcode() == ISD::TargetConstant ||
2425 Offset.getOpcode() == ISD::TargetGlobalAddress) {
2428 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
2429 if (LD->getValueType(0) != MVT::i64) {
2430 // Handle PPC32 integer and normal FP loads.
2431 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
2432 switch (LoadedVT.getSimpleVT().SimpleTy) {
2433 default: llvm_unreachable("Invalid PPC load type!");
2434 case MVT::f64: Opcode = PPC::LFDU; break;
2435 case MVT::f32: Opcode = PPC::LFSU; break;
2436 case MVT::i32: Opcode = PPC::LWZU; break;
2437 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
2439 case MVT::i8: Opcode = PPC::LBZU; break;
2442 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
2443 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
2444 switch (LoadedVT.getSimpleVT().SimpleTy) {
2445 default: llvm_unreachable("Invalid PPC load type!");
2446 case MVT::i64: Opcode = PPC::LDU; break;
2447 case MVT::i32: Opcode = PPC::LWZU8; break;
2448 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
2450 case MVT::i8: Opcode = PPC::LBZU8; break;
2454 SDValue Chain = LD->getChain();
2455 SDValue Base = LD->getBasePtr();
2456 SDValue Ops[] = { Offset, Base, Chain };
2457 return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0),
2458 PPCLowering->getPointerTy(),
2462 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
2463 if (LD->getValueType(0) != MVT::i64) {
2464 // Handle PPC32 integer and normal FP loads.
2465 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
2466 switch (LoadedVT.getSimpleVT().SimpleTy) {
2467 default: llvm_unreachable("Invalid PPC load type!");
2468 case MVT::f64: Opcode = PPC::LFDUX; break;
2469 case MVT::f32: Opcode = PPC::LFSUX; break;
2470 case MVT::i32: Opcode = PPC::LWZUX; break;
2471 case MVT::i16: Opcode = isSExt ? PPC::LHAUX : PPC::LHZUX; break;
2473 case MVT::i8: Opcode = PPC::LBZUX; break;
2476 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
2477 assert((!isSExt || LoadedVT == MVT::i16 || LoadedVT == MVT::i32) &&
2478 "Invalid sext update load");
2479 switch (LoadedVT.getSimpleVT().SimpleTy) {
2480 default: llvm_unreachable("Invalid PPC load type!");
2481 case MVT::i64: Opcode = PPC::LDUX; break;
2482 case MVT::i32: Opcode = isSExt ? PPC::LWAUX : PPC::LWZUX8; break;
2483 case MVT::i16: Opcode = isSExt ? PPC::LHAUX8 : PPC::LHZUX8; break;
2485 case MVT::i8: Opcode = PPC::LBZUX8; break;
2489 SDValue Chain = LD->getChain();
2490 SDValue Base = LD->getBasePtr();
2491 SDValue Ops[] = { Base, Offset, Chain };
2492 return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0),
2493 PPCLowering->getPointerTy(),
2499 unsigned Imm, Imm2, SH, MB, ME;
2502 // If this is an and of a value rotated between 0 and 31 bits and then and'd
2503 // with a mask, emit rlwinm
2504 if (isInt32Immediate(N->getOperand(1), Imm) &&
2505 isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH, MB, ME)) {
2506 SDValue Val = N->getOperand(0).getOperand(0);
2507 SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
2508 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2510 // If this is just a masked value where the input is not handled above, and
2511 // is not a rotate-left (handled by a pattern in the .td file), emit rlwinm
2512 if (isInt32Immediate(N->getOperand(1), Imm) &&
2513 isRunOfOnes(Imm, MB, ME) &&
2514 N->getOperand(0).getOpcode() != ISD::ROTL) {
2515 SDValue Val = N->getOperand(0);
2516 SDValue Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) };
2517 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2519 // If this is a 64-bit zero-extension mask, emit rldicl.
2520 if (isInt64Immediate(N->getOperand(1).getNode(), Imm64) &&
2522 SDValue Val = N->getOperand(0);
2523 MB = 64 - CountTrailingOnes_64(Imm64);
2526 // If the operand is a logical right shift, we can fold it into this
2527 // instruction: rldicl(rldicl(x, 64-n, n), 0, mb) -> rldicl(x, 64-n, mb)
2528 // for n <= mb. The right shift is really a left rotate followed by a
2529 // mask, and this mask is a more-restrictive sub-mask of the mask implied
2531 if (Val.getOpcode() == ISD::SRL &&
2532 isInt32Immediate(Val.getOperand(1).getNode(), Imm) && Imm <= MB) {
2533 assert(Imm < 64 && "Illegal shift amount");
2534 Val = Val.getOperand(0);
2538 SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB) };
2539 return CurDAG->SelectNodeTo(N, PPC::RLDICL, MVT::i64, Ops);
2541 // AND X, 0 -> 0, not "rlwinm 32".
2542 if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) {
2543 ReplaceUses(SDValue(N, 0), N->getOperand(1));
2546 // ISD::OR doesn't get all the bitfield insertion fun.
2547 // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert
2548 if (isInt32Immediate(N->getOperand(1), Imm) &&
2549 N->getOperand(0).getOpcode() == ISD::OR &&
2550 isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) {
2553 if (isRunOfOnes(Imm, MB, ME)) {
2554 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2555 N->getOperand(0).getOperand(1),
2556 getI32Imm(0), getI32Imm(MB),getI32Imm(ME) };
2557 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops);
2561 // Other cases are autogenerated.
2565 if (N->getValueType(0) == MVT::i32)
2566 if (SDNode *I = SelectBitfieldInsert(N))
2570 if (N->getOperand(0)->getOpcode() == ISD::FrameIndex &&
2571 isIntS16Immediate(N->getOperand(1), Imm)) {
2572 APInt LHSKnownZero, LHSKnownOne;
2573 CurDAG->computeKnownBits(N->getOperand(0), LHSKnownZero, LHSKnownOne);
2575 // If this is equivalent to an add, then we can fold it with the
2576 // FrameIndex calculation.
2577 if ((LHSKnownZero.getZExtValue()|~(uint64_t)Imm) == ~0ULL)
2578 return getFrameIndex(N, N->getOperand(0).getNode(), (int)Imm);
2581 // Other cases are autogenerated.
2586 if (N->getOperand(0)->getOpcode() == ISD::FrameIndex &&
2587 isIntS16Immediate(N->getOperand(1), Imm))
2588 return getFrameIndex(N, N->getOperand(0).getNode(), (int)Imm);
2593 unsigned Imm, SH, MB, ME;
2594 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
2595 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
2596 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2597 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
2598 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2601 // Other cases are autogenerated.
2605 unsigned Imm, SH, MB, ME;
2606 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
2607 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
2608 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2609 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
2610 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2613 // Other cases are autogenerated.
2616 // FIXME: Remove this once the ANDI glue bug is fixed:
2617 case PPCISD::ANDIo_1_EQ_BIT:
2618 case PPCISD::ANDIo_1_GT_BIT: {
2622 EVT InVT = N->getOperand(0).getValueType();
2623 assert((InVT == MVT::i64 || InVT == MVT::i32) &&
2624 "Invalid input type for ANDIo_1_EQ_BIT");
2626 unsigned Opcode = (InVT == MVT::i64) ? PPC::ANDIo8 : PPC::ANDIo;
2627 SDValue AndI(CurDAG->getMachineNode(Opcode, dl, InVT, MVT::Glue,
2629 CurDAG->getTargetConstant(1, InVT)), 0);
2630 SDValue CR0Reg = CurDAG->getRegister(PPC::CR0, MVT::i32);
2632 CurDAG->getTargetConstant(N->getOpcode() == PPCISD::ANDIo_1_EQ_BIT ?
2633 PPC::sub_eq : PPC::sub_gt, MVT::i32);
2635 return CurDAG->SelectNodeTo(N, TargetOpcode::EXTRACT_SUBREG, MVT::i1,
2637 SDValue(AndI.getNode(), 1) /* glue */);
2639 case ISD::SELECT_CC: {
2640 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
2641 EVT PtrVT = CurDAG->getTargetLoweringInfo().getPointerTy();
2642 bool isPPC64 = (PtrVT == MVT::i64);
2644 // If this is a select of i1 operands, we'll pattern match it.
2645 if (PPCSubTarget->useCRBits() &&
2646 N->getOperand(0).getValueType() == MVT::i1)
2649 // Handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
2651 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2652 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
2653 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
2654 if (N1C->isNullValue() && N3C->isNullValue() &&
2655 N2C->getZExtValue() == 1ULL && CC == ISD::SETNE &&
2656 // FIXME: Implement this optzn for PPC64.
2657 N->getValueType(0) == MVT::i32) {
2659 CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
2660 N->getOperand(0), getI32Imm(~0U));
2661 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
2662 SDValue(Tmp, 0), N->getOperand(0),
2666 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl);
2668 if (N->getValueType(0) == MVT::i1) {
2669 // An i1 select is: (c & t) | (!c & f).
2671 unsigned Idx = getCRIdxForSetCC(CC, Inv);
2675 default: llvm_unreachable("Invalid CC index");
2676 case 0: SRI = PPC::sub_lt; break;
2677 case 1: SRI = PPC::sub_gt; break;
2678 case 2: SRI = PPC::sub_eq; break;
2679 case 3: SRI = PPC::sub_un; break;
2682 SDValue CCBit = CurDAG->getTargetExtractSubreg(SRI, dl, MVT::i1, CCReg);
2684 SDValue NotCCBit(CurDAG->getMachineNode(PPC::CRNOR, dl, MVT::i1,
2686 SDValue C = Inv ? NotCCBit : CCBit,
2687 NotC = Inv ? CCBit : NotCCBit;
2689 SDValue CAndT(CurDAG->getMachineNode(PPC::CRAND, dl, MVT::i1,
2690 C, N->getOperand(2)), 0);
2691 SDValue NotCAndF(CurDAG->getMachineNode(PPC::CRAND, dl, MVT::i1,
2692 NotC, N->getOperand(3)), 0);
2694 return CurDAG->SelectNodeTo(N, PPC::CROR, MVT::i1, CAndT, NotCAndF);
2697 unsigned BROpc = getPredicateForSetCC(CC);
2699 unsigned SelectCCOp;
2700 if (N->getValueType(0) == MVT::i32)
2701 SelectCCOp = PPC::SELECT_CC_I4;
2702 else if (N->getValueType(0) == MVT::i64)
2703 SelectCCOp = PPC::SELECT_CC_I8;
2704 else if (N->getValueType(0) == MVT::f32)
2705 SelectCCOp = PPC::SELECT_CC_F4;
2706 else if (N->getValueType(0) == MVT::f64)
2707 if (PPCSubTarget->hasVSX())
2708 SelectCCOp = PPC::SELECT_CC_VSFRC;
2710 SelectCCOp = PPC::SELECT_CC_F8;
2711 else if (N->getValueType(0) == MVT::v2f64 ||
2712 N->getValueType(0) == MVT::v2i64)
2713 SelectCCOp = PPC::SELECT_CC_VSRC;
2715 SelectCCOp = PPC::SELECT_CC_VRRC;
2717 SDValue Ops[] = { CCReg, N->getOperand(2), N->getOperand(3),
2719 return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops);
2722 if (PPCSubTarget->hasVSX()) {
2723 SDValue Ops[] = { N->getOperand(2), N->getOperand(1), N->getOperand(0) };
2724 return CurDAG->SelectNodeTo(N, PPC::XXSEL, N->getValueType(0), Ops);
2728 case ISD::VECTOR_SHUFFLE:
2729 if (PPCSubTarget->hasVSX() && (N->getValueType(0) == MVT::v2f64 ||
2730 N->getValueType(0) == MVT::v2i64)) {
2731 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
2733 SDValue Op1 = N->getOperand(SVN->getMaskElt(0) < 2 ? 0 : 1),
2734 Op2 = N->getOperand(SVN->getMaskElt(1) < 2 ? 0 : 1);
2737 for (int i = 0; i < 2; ++i)
2738 if (SVN->getMaskElt(i) <= 0 || SVN->getMaskElt(i) == 2)
2743 // For little endian, we must swap the input operands and adjust
2744 // the mask elements (reverse and invert them).
2745 if (PPCSubTarget->isLittleEndian()) {
2746 std::swap(Op1, Op2);
2747 unsigned tmp = DM[0];
2752 SDValue DMV = CurDAG->getTargetConstant(DM[1] | (DM[0] << 1), MVT::i32);
2754 if (Op1 == Op2 && DM[0] == 0 && DM[1] == 0 &&
2755 Op1.getOpcode() == ISD::SCALAR_TO_VECTOR &&
2756 isa<LoadSDNode>(Op1.getOperand(0))) {
2757 LoadSDNode *LD = cast<LoadSDNode>(Op1.getOperand(0));
2758 SDValue Base, Offset;
2760 if (LD->isUnindexed() &&
2761 SelectAddrIdxOnly(LD->getBasePtr(), Base, Offset)) {
2762 SDValue Chain = LD->getChain();
2763 SDValue Ops[] = { Base, Offset, Chain };
2764 return CurDAG->SelectNodeTo(N, PPC::LXVDSX,
2765 N->getValueType(0), Ops);
2769 SDValue Ops[] = { Op1, Op2, DMV };
2770 return CurDAG->SelectNodeTo(N, PPC::XXPERMDI, N->getValueType(0), Ops);
2776 bool IsPPC64 = PPCSubTarget->isPPC64();
2777 SDValue Ops[] = { N->getOperand(1), N->getOperand(0) };
2778 return CurDAG->SelectNodeTo(N, N->getOpcode() == PPCISD::BDNZ ?
2779 (IsPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
2780 (IsPPC64 ? PPC::BDZ8 : PPC::BDZ),
2783 case PPCISD::COND_BRANCH: {
2784 // Op #0 is the Chain.
2785 // Op #1 is the PPC::PRED_* number.
2787 // Op #3 is the Dest MBB
2788 // Op #4 is the Flag.
2789 // Prevent PPC::PRED_* from being selected into LI.
2791 getI32Imm(cast<ConstantSDNode>(N->getOperand(1))->getZExtValue());
2792 SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3),
2793 N->getOperand(0), N->getOperand(4) };
2794 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops);
2797 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
2798 unsigned PCC = getPredicateForSetCC(CC);
2800 if (N->getOperand(2).getValueType() == MVT::i1) {
2804 default: llvm_unreachable("Unexpected Boolean-operand predicate");
2805 case PPC::PRED_LT: Opc = PPC::CRANDC; Swap = true; break;
2806 case PPC::PRED_LE: Opc = PPC::CRORC; Swap = true; break;
2807 case PPC::PRED_EQ: Opc = PPC::CREQV; Swap = false; break;
2808 case PPC::PRED_GE: Opc = PPC::CRORC; Swap = false; break;
2809 case PPC::PRED_GT: Opc = PPC::CRANDC; Swap = false; break;
2810 case PPC::PRED_NE: Opc = PPC::CRXOR; Swap = false; break;
2813 SDValue BitComp(CurDAG->getMachineNode(Opc, dl, MVT::i1,
2814 N->getOperand(Swap ? 3 : 2),
2815 N->getOperand(Swap ? 2 : 3)), 0);
2816 return CurDAG->SelectNodeTo(N, PPC::BC, MVT::Other,
2817 BitComp, N->getOperand(4), N->getOperand(0));
2820 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl);
2821 SDValue Ops[] = { getI32Imm(PCC), CondCode,
2822 N->getOperand(4), N->getOperand(0) };
2823 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops);
2826 // FIXME: Should custom lower this.
2827 SDValue Chain = N->getOperand(0);
2828 SDValue Target = N->getOperand(1);
2829 unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
2830 unsigned Reg = Target.getValueType() == MVT::i32 ? PPC::BCTR : PPC::BCTR8;
2831 Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, Target,
2833 return CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain);
2835 case PPCISD::TOC_ENTRY: {
2836 assert ((PPCSubTarget->isPPC64() || PPCSubTarget->isSVR4ABI()) &&
2837 "Only supported for 64-bit ABI and 32-bit SVR4");
2838 if (PPCSubTarget->isSVR4ABI() && !PPCSubTarget->isPPC64()) {
2839 SDValue GA = N->getOperand(0);
2840 return CurDAG->getMachineNode(PPC::LWZtoc, dl, MVT::i32, GA,
2844 // For medium and large code model, we generate two instructions as
2845 // described below. Otherwise we allow SelectCodeCommon to handle this,
2846 // selecting one of LDtoc, LDtocJTI, LDtocCPT, and LDtocBA.
2847 CodeModel::Model CModel = TM.getCodeModel();
2848 if (CModel != CodeModel::Medium && CModel != CodeModel::Large)
2851 // The first source operand is a TargetGlobalAddress or a TargetJumpTable.
2852 // If it is an externally defined symbol, a symbol with common linkage,
2853 // a non-local function address, or a jump table address, or if we are
2854 // generating code for large code model, we generate:
2855 // LDtocL(<ga:@sym>, ADDIStocHA(%X2, <ga:@sym>))
2856 // Otherwise we generate:
2857 // ADDItocL(ADDIStocHA(%X2, <ga:@sym>), <ga:@sym>)
2858 SDValue GA = N->getOperand(0);
2859 SDValue TOCbase = N->getOperand(1);
2860 SDNode *Tmp = CurDAG->getMachineNode(PPC::ADDIStocHA, dl, MVT::i64,
2863 if (isa<JumpTableSDNode>(GA) || isa<BlockAddressSDNode>(GA) ||
2864 CModel == CodeModel::Large)
2865 return CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA,
2868 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(GA)) {
2869 const GlobalValue *GValue = G->getGlobal();
2870 if ((GValue->getType()->getElementType()->isFunctionTy() &&
2871 (GValue->isDeclaration() || GValue->isWeakForLinker())) ||
2872 GValue->isDeclaration() || GValue->hasCommonLinkage() ||
2873 GValue->hasAvailableExternallyLinkage())
2874 return CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA,
2878 return CurDAG->getMachineNode(PPC::ADDItocL, dl, MVT::i64,
2879 SDValue(Tmp, 0), GA);
2881 case PPCISD::PPC32_PICGOT: {
2882 // Generate a PIC-safe GOT reference.
2883 assert(!PPCSubTarget->isPPC64() && PPCSubTarget->isSVR4ABI() &&
2884 "PPCISD::PPC32_PICGOT is only supported for 32-bit SVR4");
2885 return CurDAG->SelectNodeTo(N, PPC::PPC32PICGOT, PPCLowering->getPointerTy(), MVT::i32);
2887 case PPCISD::VADD_SPLAT: {
2888 // This expands into one of three sequences, depending on whether
2889 // the first operand is odd or even, positive or negative.
2890 assert(isa<ConstantSDNode>(N->getOperand(0)) &&
2891 isa<ConstantSDNode>(N->getOperand(1)) &&
2892 "Invalid operand on VADD_SPLAT!");
2894 int Elt = N->getConstantOperandVal(0);
2895 int EltSize = N->getConstantOperandVal(1);
2896 unsigned Opc1, Opc2, Opc3;
2900 Opc1 = PPC::VSPLTISB;
2901 Opc2 = PPC::VADDUBM;
2902 Opc3 = PPC::VSUBUBM;
2904 } else if (EltSize == 2) {
2905 Opc1 = PPC::VSPLTISH;
2906 Opc2 = PPC::VADDUHM;
2907 Opc3 = PPC::VSUBUHM;
2910 assert(EltSize == 4 && "Invalid element size on VADD_SPLAT!");
2911 Opc1 = PPC::VSPLTISW;
2912 Opc2 = PPC::VADDUWM;
2913 Opc3 = PPC::VSUBUWM;
2917 if ((Elt & 1) == 0) {
2918 // Elt is even, in the range [-32,-18] + [16,30].
2920 // Convert: VADD_SPLAT elt, size
2921 // Into: tmp = VSPLTIS[BHW] elt
2922 // VADDU[BHW]M tmp, tmp
2923 // Where: [BHW] = B for size = 1, H for size = 2, W for size = 4
2924 SDValue EltVal = getI32Imm(Elt >> 1);
2925 SDNode *Tmp = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
2926 SDValue TmpVal = SDValue(Tmp, 0);
2927 return CurDAG->getMachineNode(Opc2, dl, VT, TmpVal, TmpVal);
2929 } else if (Elt > 0) {
2930 // Elt is odd and positive, in the range [17,31].
2932 // Convert: VADD_SPLAT elt, size
2933 // Into: tmp1 = VSPLTIS[BHW] elt-16
2934 // tmp2 = VSPLTIS[BHW] -16
2935 // VSUBU[BHW]M tmp1, tmp2
2936 SDValue EltVal = getI32Imm(Elt - 16);
2937 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
2938 EltVal = getI32Imm(-16);
2939 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
2940 return CurDAG->getMachineNode(Opc3, dl, VT, SDValue(Tmp1, 0),
2944 // Elt is odd and negative, in the range [-31,-17].
2946 // Convert: VADD_SPLAT elt, size
2947 // Into: tmp1 = VSPLTIS[BHW] elt+16
2948 // tmp2 = VSPLTIS[BHW] -16
2949 // VADDU[BHW]M tmp1, tmp2
2950 SDValue EltVal = getI32Imm(Elt + 16);
2951 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
2952 EltVal = getI32Imm(-16);
2953 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
2954 return CurDAG->getMachineNode(Opc2, dl, VT, SDValue(Tmp1, 0),
2960 return SelectCode(N);
2963 // If the target supports the cmpb instruction, do the idiom recognition here.
2964 // We don't do this as a DAG combine because we don't want to do it as nodes
2965 // are being combined (because we might miss part of the eventual idiom). We
2966 // don't want to do it during instruction selection because we want to reuse
2967 // the logic for lowering the masking operations already part of the
2968 // instruction selector.
2969 SDValue PPCDAGToDAGISel::combineToCMPB(SDNode *N) {
2972 assert(N->getOpcode() == ISD::OR &&
2973 "Only OR nodes are supported for CMPB");
2976 if (!PPCSubTarget->hasCMPB())
2979 if (N->getValueType(0) != MVT::i32 &&
2980 N->getValueType(0) != MVT::i64)
2983 EVT VT = N->getValueType(0);
2986 bool BytesFound[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
2987 uint64_t Mask = 0, Alt = 0;
2989 auto IsByteSelectCC = [this](SDValue O, unsigned &b,
2990 uint64_t &Mask, uint64_t &Alt,
2991 SDValue &LHS, SDValue &RHS) {
2992 if (O.getOpcode() != ISD::SELECT_CC)
2994 ISD::CondCode CC = cast<CondCodeSDNode>(O.getOperand(4))->get();
2996 if (!isa<ConstantSDNode>(O.getOperand(2)) ||
2997 !isa<ConstantSDNode>(O.getOperand(3)))
3000 uint64_t PM = O.getConstantOperandVal(2);
3001 uint64_t PAlt = O.getConstantOperandVal(3);
3002 for (b = 0; b < 8; ++b) {
3003 uint64_t Mask = UINT64_C(0xFF) << (8*b);
3004 if (PM && (PM & Mask) == PM && (PAlt & Mask) == PAlt)
3013 if (!isa<ConstantSDNode>(O.getOperand(1)) ||
3014 O.getConstantOperandVal(1) != 0) {
3015 SDValue Op0 = O.getOperand(0), Op1 = O.getOperand(1);
3016 if (Op0.getOpcode() == ISD::TRUNCATE)
3017 Op0 = Op0.getOperand(0);
3018 if (Op1.getOpcode() == ISD::TRUNCATE)
3019 Op1 = Op1.getOperand(0);
3021 if (Op0.getOpcode() == ISD::SRL && Op1.getOpcode() == ISD::SRL &&
3022 Op0.getOperand(1) == Op1.getOperand(1) && CC == ISD::SETEQ &&
3023 isa<ConstantSDNode>(Op0.getOperand(1))) {
3025 unsigned Bits = Op0.getValueType().getSizeInBits();
3028 if (Op0.getConstantOperandVal(1) != Bits-8)
3031 LHS = Op0.getOperand(0);
3032 RHS = Op1.getOperand(0);
3036 // When we have small integers (i16 to be specific), the form present
3037 // post-legalization uses SETULT in the SELECT_CC for the
3038 // higher-order byte, depending on the fact that the
3039 // even-higher-order bytes are known to all be zero, for example:
3040 // select_cc (xor $lhs, $rhs), 256, 65280, 0, setult
3041 // (so when the second byte is the same, because all higher-order
3042 // bits from bytes 3 and 4 are known to be zero, the result of the
3043 // xor can be at most 255)
3044 if (Op0.getOpcode() == ISD::XOR && CC == ISD::SETULT &&
3045 isa<ConstantSDNode>(O.getOperand(1))) {
3047 uint64_t ULim = O.getConstantOperandVal(1);
3048 if (ULim != (UINT64_C(1) << b*8))
3051 // Now we need to make sure that the upper bytes are known to be
3053 unsigned Bits = Op0.getValueType().getSizeInBits();
3054 if (!CurDAG->MaskedValueIsZero(Op0,
3055 APInt::getHighBitsSet(Bits, Bits - (b+1)*8)))
3058 LHS = Op0.getOperand(0);
3059 RHS = Op0.getOperand(1);
3066 if (CC != ISD::SETEQ)
3069 SDValue Op = O.getOperand(0);
3070 if (Op.getOpcode() == ISD::AND) {
3071 if (!isa<ConstantSDNode>(Op.getOperand(1)))
3073 if (Op.getConstantOperandVal(1) != (UINT64_C(0xFF) << (8*b)))
3076 SDValue XOR = Op.getOperand(0);
3077 if (XOR.getOpcode() == ISD::TRUNCATE)
3078 XOR = XOR.getOperand(0);
3079 if (XOR.getOpcode() != ISD::XOR)
3082 LHS = XOR.getOperand(0);
3083 RHS = XOR.getOperand(1);
3085 } else if (Op.getOpcode() == ISD::SRL) {
3086 if (!isa<ConstantSDNode>(Op.getOperand(1)))
3088 unsigned Bits = Op.getValueType().getSizeInBits();
3091 if (Op.getConstantOperandVal(1) != Bits-8)
3094 SDValue XOR = Op.getOperand(0);
3095 if (XOR.getOpcode() == ISD::TRUNCATE)
3096 XOR = XOR.getOperand(0);
3097 if (XOR.getOpcode() != ISD::XOR)
3100 LHS = XOR.getOperand(0);
3101 RHS = XOR.getOperand(1);
3108 SmallVector<SDValue, 8> Queue(1, SDValue(N, 0));
3109 while (!Queue.empty()) {
3110 SDValue V = Queue.pop_back_val();
3112 for (const SDValue &O : V.getNode()->ops()) {
3114 uint64_t M = 0, A = 0;
3116 if (O.getOpcode() == ISD::OR) {
3118 } else if (IsByteSelectCC(O, b, M, A, OLHS, ORHS)) {
3122 BytesFound[b] = true;
3125 } else if ((LHS == ORHS && RHS == OLHS) ||
3126 (RHS == ORHS && LHS == OLHS)) {
3127 BytesFound[b] = true;
3139 unsigned LastB = 0, BCnt = 0;
3140 for (unsigned i = 0; i < 8; ++i)
3141 if (BytesFound[LastB]) {
3146 if (!LastB || BCnt < 2)
3149 // Because we'll be zero-extending the output anyway if don't have a specific
3150 // value for each input byte (via the Mask), we can 'anyext' the inputs.
3151 if (LHS.getValueType() != VT) {
3152 LHS = CurDAG->getAnyExtOrTrunc(LHS, dl, VT);
3153 RHS = CurDAG->getAnyExtOrTrunc(RHS, dl, VT);
3156 Res = CurDAG->getNode(PPCISD::CMPB, dl, VT, LHS, RHS);
3158 bool NonTrivialMask = ((int64_t) Mask) != INT64_C(-1);
3159 if (NonTrivialMask && !Alt) {
3160 // Res = Mask & CMPB
3161 Res = CurDAG->getNode(ISD::AND, dl, VT, Res, CurDAG->getConstant(Mask, VT));
3163 // Res = (CMPB & Mask) | (~CMPB & Alt)
3164 // Which, as suggested here:
3165 // https://graphics.stanford.edu/~seander/bithacks.html#MaskedMerge
3166 // can be written as:
3167 // Res = Alt ^ ((Alt ^ Mask) & CMPB)
3168 // useful because the (Alt ^ Mask) can be pre-computed.
3169 Res = CurDAG->getNode(ISD::AND, dl, VT, Res,
3170 CurDAG->getConstant(Mask ^ Alt, VT));
3171 Res = CurDAG->getNode(ISD::XOR, dl, VT, Res, CurDAG->getConstant(Alt, VT));
3177 // When CR bit registers are enabled, an extension of an i1 variable to a i32
3178 // or i64 value is lowered in terms of a SELECT_I[48] operation, and thus
3179 // involves constant materialization of a 0 or a 1 or both. If the result of
3180 // the extension is then operated upon by some operator that can be constant
3181 // folded with a constant 0 or 1, and that constant can be materialized using
3182 // only one instruction (like a zero or one), then we should fold in those
3183 // operations with the select.
3184 void PPCDAGToDAGISel::foldBoolExts(SDValue &Res, SDNode *&N) {
3185 if (!PPCSubTarget->useCRBits())
3188 if (N->getOpcode() != ISD::ZERO_EXTEND &&
3189 N->getOpcode() != ISD::SIGN_EXTEND &&
3190 N->getOpcode() != ISD::ANY_EXTEND)
3193 if (N->getOperand(0).getValueType() != MVT::i1)
3196 if (!N->hasOneUse())
3200 EVT VT = N->getValueType(0);
3201 SDValue Cond = N->getOperand(0);
3203 CurDAG->getConstant(N->getOpcode() == ISD::SIGN_EXTEND ? -1 : 1, VT);
3204 SDValue ConstFalse = CurDAG->getConstant(0, VT);
3207 SDNode *User = *N->use_begin();
3208 if (User->getNumOperands() != 2)
3211 auto TryFold = [this, N, User](SDValue Val) {
3212 SDValue UserO0 = User->getOperand(0), UserO1 = User->getOperand(1);
3213 SDValue O0 = UserO0.getNode() == N ? Val : UserO0;
3214 SDValue O1 = UserO1.getNode() == N ? Val : UserO1;
3216 return CurDAG->FoldConstantArithmetic(User->getOpcode(),
3217 User->getValueType(0),
3218 O0.getNode(), O1.getNode());
3221 SDValue TrueRes = TryFold(ConstTrue);
3224 SDValue FalseRes = TryFold(ConstFalse);
3228 // For us to materialize these using one instruction, we must be able to
3229 // represent them as signed 16-bit integers.
3230 uint64_t True = cast<ConstantSDNode>(TrueRes)->getZExtValue(),
3231 False = cast<ConstantSDNode>(FalseRes)->getZExtValue();
3232 if (!isInt<16>(True) || !isInt<16>(False))
3235 // We can replace User with a new SELECT node, and try again to see if we
3236 // can fold the select with its user.
3237 Res = CurDAG->getSelect(dl, User->getValueType(0), Cond, TrueRes, FalseRes);
3239 ConstTrue = TrueRes;
3240 ConstFalse = FalseRes;
3241 } while (N->hasOneUse());
3244 void PPCDAGToDAGISel::PreprocessISelDAG() {
3245 SelectionDAG::allnodes_iterator Position(CurDAG->getRoot().getNode());
3248 bool MadeChange = false;
3249 while (Position != CurDAG->allnodes_begin()) {
3250 SDNode *N = --Position;
3255 switch (N->getOpcode()) {
3258 Res = combineToCMPB(N);
3263 foldBoolExts(Res, N);
3266 DEBUG(dbgs() << "PPC DAG preprocessing replacing:\nOld: ");
3267 DEBUG(N->dump(CurDAG));
3268 DEBUG(dbgs() << "\nNew: ");
3269 DEBUG(Res.getNode()->dump(CurDAG));
3270 DEBUG(dbgs() << "\n");
3272 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Res);
3278 CurDAG->RemoveDeadNodes();
3281 /// PostprocessISelDAG - Perform some late peephole optimizations
3282 /// on the DAG representation.
3283 void PPCDAGToDAGISel::PostprocessISelDAG() {
3285 // Skip peepholes at -O0.
3286 if (TM.getOptLevel() == CodeGenOpt::None)
3291 PeepholePPC64ZExt();
3294 // Check if all users of this node will become isel where the second operand
3295 // is the constant zero. If this is so, and if we can negate the condition,
3296 // then we can flip the true and false operands. This will allow the zero to
3297 // be folded with the isel so that we don't need to materialize a register
3299 bool PPCDAGToDAGISel::AllUsersSelectZero(SDNode *N) {
3300 // If we're not using isel, then this does not matter.
3301 if (!PPCSubTarget->hasISEL())
3304 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
3307 if (!User->isMachineOpcode())
3309 if (User->getMachineOpcode() != PPC::SELECT_I4 &&
3310 User->getMachineOpcode() != PPC::SELECT_I8)
3313 SDNode *Op2 = User->getOperand(2).getNode();
3314 if (!Op2->isMachineOpcode())
3317 if (Op2->getMachineOpcode() != PPC::LI &&
3318 Op2->getMachineOpcode() != PPC::LI8)
3321 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op2->getOperand(0));
3325 if (!C->isNullValue())
3332 void PPCDAGToDAGISel::SwapAllSelectUsers(SDNode *N) {
3333 SmallVector<SDNode *, 4> ToReplace;
3334 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
3337 assert((User->getMachineOpcode() == PPC::SELECT_I4 ||
3338 User->getMachineOpcode() == PPC::SELECT_I8) &&
3339 "Must have all select users");
3340 ToReplace.push_back(User);
3343 for (SmallVector<SDNode *, 4>::iterator UI = ToReplace.begin(),
3344 UE = ToReplace.end(); UI != UE; ++UI) {
3347 CurDAG->getMachineNode(User->getMachineOpcode(), SDLoc(User),
3348 User->getValueType(0), User->getOperand(0),
3349 User->getOperand(2),
3350 User->getOperand(1));
3352 DEBUG(dbgs() << "CR Peephole replacing:\nOld: ");
3353 DEBUG(User->dump(CurDAG));
3354 DEBUG(dbgs() << "\nNew: ");
3355 DEBUG(ResNode->dump(CurDAG));
3356 DEBUG(dbgs() << "\n");
3358 ReplaceUses(User, ResNode);
3362 void PPCDAGToDAGISel::PeepholeCROps() {
3366 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
3367 E = CurDAG->allnodes_end(); I != E; ++I) {
3368 MachineSDNode *MachineNode = dyn_cast<MachineSDNode>(I);
3369 if (!MachineNode || MachineNode->use_empty())
3371 SDNode *ResNode = MachineNode;
3373 bool Op1Set = false, Op1Unset = false,
3375 Op2Set = false, Op2Unset = false,
3378 unsigned Opcode = MachineNode->getMachineOpcode();
3389 SDValue Op = MachineNode->getOperand(1);
3390 if (Op.isMachineOpcode()) {
3391 if (Op.getMachineOpcode() == PPC::CRSET)
3393 else if (Op.getMachineOpcode() == PPC::CRUNSET)
3395 else if (Op.getMachineOpcode() == PPC::CRNOR &&
3396 Op.getOperand(0) == Op.getOperand(1))
3402 case PPC::SELECT_I4:
3403 case PPC::SELECT_I8:
3404 case PPC::SELECT_F4:
3405 case PPC::SELECT_F8:
3406 case PPC::SELECT_VRRC:
3407 case PPC::SELECT_VSFRC:
3408 case PPC::SELECT_VSRC: {
3409 SDValue Op = MachineNode->getOperand(0);
3410 if (Op.isMachineOpcode()) {
3411 if (Op.getMachineOpcode() == PPC::CRSET)
3413 else if (Op.getMachineOpcode() == PPC::CRUNSET)
3415 else if (Op.getMachineOpcode() == PPC::CRNOR &&
3416 Op.getOperand(0) == Op.getOperand(1))
3423 bool SelectSwap = false;
3427 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
3429 ResNode = MachineNode->getOperand(0).getNode();
3432 ResNode = MachineNode->getOperand(1).getNode();
3435 ResNode = MachineNode->getOperand(0).getNode();
3436 else if (Op1Unset || Op2Unset)
3437 // x & 0 = 0 & y = 0
3438 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
3441 // ~x & y = andc(y, x)
3442 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
3443 MVT::i1, MachineNode->getOperand(1),
3444 MachineNode->getOperand(0).
3447 // x & ~y = andc(x, y)
3448 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
3449 MVT::i1, MachineNode->getOperand(0),
3450 MachineNode->getOperand(1).
3452 else if (AllUsersSelectZero(MachineNode))
3453 ResNode = CurDAG->getMachineNode(PPC::CRNAND, SDLoc(MachineNode),
3454 MVT::i1, MachineNode->getOperand(0),
3455 MachineNode->getOperand(1)),
3459 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
3460 // nand(x, x) -> nor(x, x)
3461 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3462 MVT::i1, MachineNode->getOperand(0),
3463 MachineNode->getOperand(0));
3465 // nand(1, y) -> nor(y, y)
3466 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3467 MVT::i1, MachineNode->getOperand(1),
3468 MachineNode->getOperand(1));
3470 // nand(x, 1) -> nor(x, x)
3471 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3472 MVT::i1, MachineNode->getOperand(0),
3473 MachineNode->getOperand(0));
3474 else if (Op1Unset || Op2Unset)
3475 // nand(x, 0) = nand(0, y) = 1
3476 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
3479 // nand(~x, y) = ~(~x & y) = x | ~y = orc(x, y)
3480 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
3481 MVT::i1, MachineNode->getOperand(0).
3483 MachineNode->getOperand(1));
3485 // nand(x, ~y) = ~x | y = orc(y, x)
3486 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
3487 MVT::i1, MachineNode->getOperand(1).
3489 MachineNode->getOperand(0));
3490 else if (AllUsersSelectZero(MachineNode))
3491 ResNode = CurDAG->getMachineNode(PPC::CRAND, SDLoc(MachineNode),
3492 MVT::i1, MachineNode->getOperand(0),
3493 MachineNode->getOperand(1)),
3497 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
3499 ResNode = MachineNode->getOperand(0).getNode();
3500 else if (Op1Set || Op2Set)
3501 // x | 1 = 1 | y = 1
3502 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
3506 ResNode = MachineNode->getOperand(1).getNode();
3509 ResNode = MachineNode->getOperand(0).getNode();
3511 // ~x | y = orc(y, x)
3512 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
3513 MVT::i1, MachineNode->getOperand(1),
3514 MachineNode->getOperand(0).
3517 // x | ~y = orc(x, y)
3518 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
3519 MVT::i1, MachineNode->getOperand(0),
3520 MachineNode->getOperand(1).
3522 else if (AllUsersSelectZero(MachineNode))
3523 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3524 MVT::i1, MachineNode->getOperand(0),
3525 MachineNode->getOperand(1)),
3529 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
3531 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
3534 // xor(1, y) -> nor(y, y)
3535 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3536 MVT::i1, MachineNode->getOperand(1),
3537 MachineNode->getOperand(1));
3539 // xor(x, 1) -> nor(x, x)
3540 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3541 MVT::i1, MachineNode->getOperand(0),
3542 MachineNode->getOperand(0));
3545 ResNode = MachineNode->getOperand(1).getNode();
3548 ResNode = MachineNode->getOperand(0).getNode();
3550 // xor(~x, y) = eqv(x, y)
3551 ResNode = CurDAG->getMachineNode(PPC::CREQV, SDLoc(MachineNode),
3552 MVT::i1, MachineNode->getOperand(0).
3554 MachineNode->getOperand(1));
3556 // xor(x, ~y) = eqv(x, y)
3557 ResNode = CurDAG->getMachineNode(PPC::CREQV, SDLoc(MachineNode),
3558 MVT::i1, MachineNode->getOperand(0),
3559 MachineNode->getOperand(1).
3561 else if (AllUsersSelectZero(MachineNode))
3562 ResNode = CurDAG->getMachineNode(PPC::CREQV, SDLoc(MachineNode),
3563 MVT::i1, MachineNode->getOperand(0),
3564 MachineNode->getOperand(1)),
3568 if (Op1Set || Op2Set)
3570 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
3573 // nor(0, y) = ~y -> nor(y, y)
3574 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3575 MVT::i1, MachineNode->getOperand(1),
3576 MachineNode->getOperand(1));
3579 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3580 MVT::i1, MachineNode->getOperand(0),
3581 MachineNode->getOperand(0));
3583 // nor(~x, y) = andc(x, y)
3584 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
3585 MVT::i1, MachineNode->getOperand(0).
3587 MachineNode->getOperand(1));
3589 // nor(x, ~y) = andc(y, x)
3590 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
3591 MVT::i1, MachineNode->getOperand(1).
3593 MachineNode->getOperand(0));
3594 else if (AllUsersSelectZero(MachineNode))
3595 ResNode = CurDAG->getMachineNode(PPC::CROR, SDLoc(MachineNode),
3596 MVT::i1, MachineNode->getOperand(0),
3597 MachineNode->getOperand(1)),
3601 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
3603 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
3607 ResNode = MachineNode->getOperand(1).getNode();
3610 ResNode = MachineNode->getOperand(0).getNode();
3612 // eqv(0, y) = ~y -> nor(y, y)
3613 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3614 MVT::i1, MachineNode->getOperand(1),
3615 MachineNode->getOperand(1));
3618 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3619 MVT::i1, MachineNode->getOperand(0),
3620 MachineNode->getOperand(0));
3622 // eqv(~x, y) = xor(x, y)
3623 ResNode = CurDAG->getMachineNode(PPC::CRXOR, SDLoc(MachineNode),
3624 MVT::i1, MachineNode->getOperand(0).
3626 MachineNode->getOperand(1));
3628 // eqv(x, ~y) = xor(x, y)
3629 ResNode = CurDAG->getMachineNode(PPC::CRXOR, SDLoc(MachineNode),
3630 MVT::i1, MachineNode->getOperand(0),
3631 MachineNode->getOperand(1).
3633 else if (AllUsersSelectZero(MachineNode))
3634 ResNode = CurDAG->getMachineNode(PPC::CRXOR, SDLoc(MachineNode),
3635 MVT::i1, MachineNode->getOperand(0),
3636 MachineNode->getOperand(1)),
3640 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
3642 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
3646 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3647 MVT::i1, MachineNode->getOperand(1),
3648 MachineNode->getOperand(1));
3649 else if (Op1Unset || Op2Set)
3650 // andc(0, y) = andc(x, 1) = 0
3651 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
3655 ResNode = MachineNode->getOperand(0).getNode();
3657 // andc(~x, y) = ~(x | y) = nor(x, y)
3658 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3659 MVT::i1, MachineNode->getOperand(0).
3661 MachineNode->getOperand(1));
3663 // andc(x, ~y) = x & y
3664 ResNode = CurDAG->getMachineNode(PPC::CRAND, SDLoc(MachineNode),
3665 MVT::i1, MachineNode->getOperand(0),
3666 MachineNode->getOperand(1).
3668 else if (AllUsersSelectZero(MachineNode))
3669 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
3670 MVT::i1, MachineNode->getOperand(1),
3671 MachineNode->getOperand(0)),
3675 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
3677 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
3679 else if (Op1Set || Op2Unset)
3680 // orc(1, y) = orc(x, 0) = 1
3681 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
3685 ResNode = MachineNode->getOperand(0).getNode();
3688 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3689 MVT::i1, MachineNode->getOperand(1),
3690 MachineNode->getOperand(1));
3692 // orc(~x, y) = ~(x & y) = nand(x, y)
3693 ResNode = CurDAG->getMachineNode(PPC::CRNAND, SDLoc(MachineNode),
3694 MVT::i1, MachineNode->getOperand(0).
3696 MachineNode->getOperand(1));
3698 // orc(x, ~y) = x | y
3699 ResNode = CurDAG->getMachineNode(PPC::CROR, SDLoc(MachineNode),
3700 MVT::i1, MachineNode->getOperand(0),
3701 MachineNode->getOperand(1).
3703 else if (AllUsersSelectZero(MachineNode))
3704 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
3705 MVT::i1, MachineNode->getOperand(1),
3706 MachineNode->getOperand(0)),
3709 case PPC::SELECT_I4:
3710 case PPC::SELECT_I8:
3711 case PPC::SELECT_F4:
3712 case PPC::SELECT_F8:
3713 case PPC::SELECT_VRRC:
3714 case PPC::SELECT_VSFRC:
3715 case PPC::SELECT_VSRC:
3717 ResNode = MachineNode->getOperand(1).getNode();
3719 ResNode = MachineNode->getOperand(2).getNode();
3721 ResNode = CurDAG->getMachineNode(MachineNode->getMachineOpcode(),
3723 MachineNode->getValueType(0),
3724 MachineNode->getOperand(0).
3726 MachineNode->getOperand(2),
3727 MachineNode->getOperand(1));
3732 ResNode = CurDAG->getMachineNode(Opcode == PPC::BC ? PPC::BCn :
3736 MachineNode->getOperand(0).
3738 MachineNode->getOperand(1),
3739 MachineNode->getOperand(2));
3740 // FIXME: Handle Op1Set, Op1Unset here too.
3744 // If we're inverting this node because it is used only by selects that
3745 // we'd like to swap, then swap the selects before the node replacement.
3747 SwapAllSelectUsers(MachineNode);
3749 if (ResNode != MachineNode) {
3750 DEBUG(dbgs() << "CR Peephole replacing:\nOld: ");
3751 DEBUG(MachineNode->dump(CurDAG));
3752 DEBUG(dbgs() << "\nNew: ");
3753 DEBUG(ResNode->dump(CurDAG));
3754 DEBUG(dbgs() << "\n");
3756 ReplaceUses(MachineNode, ResNode);
3761 CurDAG->RemoveDeadNodes();
3762 } while (IsModified);
3765 // Gather the set of 32-bit operations that are known to have their
3766 // higher-order 32 bits zero, where ToPromote contains all such operations.
3767 static bool PeepholePPC64ZExtGather(SDValue Op32,
3768 SmallPtrSetImpl<SDNode *> &ToPromote) {
3769 if (!Op32.isMachineOpcode())
3772 // First, check for the "frontier" instructions (those that will clear the
3773 // higher-order 32 bits.
3775 // For RLWINM and RLWNM, we need to make sure that the mask does not wrap
3776 // around. If it does not, then these instructions will clear the
3777 // higher-order bits.
3778 if ((Op32.getMachineOpcode() == PPC::RLWINM ||
3779 Op32.getMachineOpcode() == PPC::RLWNM) &&
3780 Op32.getConstantOperandVal(2) <= Op32.getConstantOperandVal(3)) {
3781 ToPromote.insert(Op32.getNode());
3785 // SLW and SRW always clear the higher-order bits.
3786 if (Op32.getMachineOpcode() == PPC::SLW ||
3787 Op32.getMachineOpcode() == PPC::SRW) {
3788 ToPromote.insert(Op32.getNode());
3792 // For LI and LIS, we need the immediate to be positive (so that it is not
3794 if (Op32.getMachineOpcode() == PPC::LI ||
3795 Op32.getMachineOpcode() == PPC::LIS) {
3796 if (!isUInt<15>(Op32.getConstantOperandVal(0)))
3799 ToPromote.insert(Op32.getNode());
3803 // LHBRX and LWBRX always clear the higher-order bits.
3804 if (Op32.getMachineOpcode() == PPC::LHBRX ||
3805 Op32.getMachineOpcode() == PPC::LWBRX) {
3806 ToPromote.insert(Op32.getNode());
3810 // CNTLZW always produces a 64-bit value in [0,32], and so is zero extended.
3811 if (Op32.getMachineOpcode() == PPC::CNTLZW) {
3812 ToPromote.insert(Op32.getNode());
3816 // Next, check for those instructions we can look through.
3818 // Assuming the mask does not wrap around, then the higher-order bits are
3819 // taken directly from the first operand.
3820 if (Op32.getMachineOpcode() == PPC::RLWIMI &&
3821 Op32.getConstantOperandVal(3) <= Op32.getConstantOperandVal(4)) {
3822 SmallPtrSet<SDNode *, 16> ToPromote1;
3823 if (!PeepholePPC64ZExtGather(Op32.getOperand(0), ToPromote1))
3826 ToPromote.insert(Op32.getNode());
3827 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
3831 // For OR, the higher-order bits are zero if that is true for both operands.
3832 // For SELECT_I4, the same is true (but the relevant operand numbers are
3834 if (Op32.getMachineOpcode() == PPC::OR ||
3835 Op32.getMachineOpcode() == PPC::SELECT_I4) {
3836 unsigned B = Op32.getMachineOpcode() == PPC::SELECT_I4 ? 1 : 0;
3837 SmallPtrSet<SDNode *, 16> ToPromote1;
3838 if (!PeepholePPC64ZExtGather(Op32.getOperand(B+0), ToPromote1))
3840 if (!PeepholePPC64ZExtGather(Op32.getOperand(B+1), ToPromote1))
3843 ToPromote.insert(Op32.getNode());
3844 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
3848 // For ORI and ORIS, we need the higher-order bits of the first operand to be
3849 // zero, and also for the constant to be positive (so that it is not sign
3851 if (Op32.getMachineOpcode() == PPC::ORI ||
3852 Op32.getMachineOpcode() == PPC::ORIS) {
3853 SmallPtrSet<SDNode *, 16> ToPromote1;
3854 if (!PeepholePPC64ZExtGather(Op32.getOperand(0), ToPromote1))
3856 if (!isUInt<15>(Op32.getConstantOperandVal(1)))
3859 ToPromote.insert(Op32.getNode());
3860 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
3864 // The higher-order bits of AND are zero if that is true for at least one of
3866 if (Op32.getMachineOpcode() == PPC::AND) {
3867 SmallPtrSet<SDNode *, 16> ToPromote1, ToPromote2;
3869 PeepholePPC64ZExtGather(Op32.getOperand(0), ToPromote1);
3871 PeepholePPC64ZExtGather(Op32.getOperand(1), ToPromote2);
3872 if (!Op0OK && !Op1OK)
3875 ToPromote.insert(Op32.getNode());
3878 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
3881 ToPromote.insert(ToPromote2.begin(), ToPromote2.end());
3886 // For ANDI and ANDIS, the higher-order bits are zero if either that is true
3887 // of the first operand, or if the second operand is positive (so that it is
3888 // not sign extended).
3889 if (Op32.getMachineOpcode() == PPC::ANDIo ||
3890 Op32.getMachineOpcode() == PPC::ANDISo) {
3891 SmallPtrSet<SDNode *, 16> ToPromote1;
3893 PeepholePPC64ZExtGather(Op32.getOperand(0), ToPromote1);
3894 bool Op1OK = isUInt<15>(Op32.getConstantOperandVal(1));
3895 if (!Op0OK && !Op1OK)
3898 ToPromote.insert(Op32.getNode());
3901 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
3909 void PPCDAGToDAGISel::PeepholePPC64ZExt() {
3910 if (!PPCSubTarget->isPPC64())
3913 // When we zero-extend from i32 to i64, we use a pattern like this:
3914 // def : Pat<(i64 (zext i32:$in)),
3915 // (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32),
3917 // There are several 32-bit shift/rotate instructions, however, that will
3918 // clear the higher-order bits of their output, rendering the RLDICL
3919 // unnecessary. When that happens, we remove it here, and redefine the
3920 // relevant 32-bit operation to be a 64-bit operation.
3922 SelectionDAG::allnodes_iterator Position(CurDAG->getRoot().getNode());
3925 bool MadeChange = false;
3926 while (Position != CurDAG->allnodes_begin()) {
3927 SDNode *N = --Position;
3928 // Skip dead nodes and any non-machine opcodes.
3929 if (N->use_empty() || !N->isMachineOpcode())
3932 if (N->getMachineOpcode() != PPC::RLDICL)
3935 if (N->getConstantOperandVal(1) != 0 ||
3936 N->getConstantOperandVal(2) != 32)
3939 SDValue ISR = N->getOperand(0);
3940 if (!ISR.isMachineOpcode() ||
3941 ISR.getMachineOpcode() != TargetOpcode::INSERT_SUBREG)
3944 if (!ISR.hasOneUse())
3947 if (ISR.getConstantOperandVal(2) != PPC::sub_32)
3950 SDValue IDef = ISR.getOperand(0);
3951 if (!IDef.isMachineOpcode() ||
3952 IDef.getMachineOpcode() != TargetOpcode::IMPLICIT_DEF)
3955 // We now know that we're looking at a canonical i32 -> i64 zext. See if we
3956 // can get rid of it.
3958 SDValue Op32 = ISR->getOperand(1);
3959 if (!Op32.isMachineOpcode())
3962 // There are some 32-bit instructions that always clear the high-order 32
3963 // bits, there are also some instructions (like AND) that we can look
3965 SmallPtrSet<SDNode *, 16> ToPromote;
3966 if (!PeepholePPC64ZExtGather(Op32, ToPromote))
3969 // If the ToPromote set contains nodes that have uses outside of the set
3970 // (except for the original INSERT_SUBREG), then abort the transformation.
3971 bool OutsideUse = false;
3972 for (SDNode *PN : ToPromote) {
3973 for (SDNode *UN : PN->uses()) {
3974 if (!ToPromote.count(UN) && UN != ISR.getNode()) {
3988 // We now know that this zero extension can be removed by promoting to
3989 // nodes in ToPromote to 64-bit operations, where for operations in the
3990 // frontier of the set, we need to insert INSERT_SUBREGs for their
3992 for (SDNode *PN : ToPromote) {
3994 switch (PN->getMachineOpcode()) {
3996 llvm_unreachable("Don't know the 64-bit variant of this instruction");
3997 case PPC::RLWINM: NewOpcode = PPC::RLWINM8; break;
3998 case PPC::RLWNM: NewOpcode = PPC::RLWNM8; break;
3999 case PPC::SLW: NewOpcode = PPC::SLW8; break;
4000 case PPC::SRW: NewOpcode = PPC::SRW8; break;
4001 case PPC::LI: NewOpcode = PPC::LI8; break;
4002 case PPC::LIS: NewOpcode = PPC::LIS8; break;
4003 case PPC::LHBRX: NewOpcode = PPC::LHBRX8; break;
4004 case PPC::LWBRX: NewOpcode = PPC::LWBRX8; break;
4005 case PPC::CNTLZW: NewOpcode = PPC::CNTLZW8; break;
4006 case PPC::RLWIMI: NewOpcode = PPC::RLWIMI8; break;
4007 case PPC::OR: NewOpcode = PPC::OR8; break;
4008 case PPC::SELECT_I4: NewOpcode = PPC::SELECT_I8; break;
4009 case PPC::ORI: NewOpcode = PPC::ORI8; break;
4010 case PPC::ORIS: NewOpcode = PPC::ORIS8; break;
4011 case PPC::AND: NewOpcode = PPC::AND8; break;
4012 case PPC::ANDIo: NewOpcode = PPC::ANDIo8; break;
4013 case PPC::ANDISo: NewOpcode = PPC::ANDISo8; break;
4016 // Note: During the replacement process, the nodes will be in an
4017 // inconsistent state (some instructions will have operands with values
4018 // of the wrong type). Once done, however, everything should be right
4021 SmallVector<SDValue, 4> Ops;
4022 for (const SDValue &V : PN->ops()) {
4023 if (!ToPromote.count(V.getNode()) && V.getValueType() == MVT::i32 &&
4024 !isa<ConstantSDNode>(V)) {
4025 SDValue ReplOpOps[] = { ISR.getOperand(0), V, ISR.getOperand(2) };
4027 CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, SDLoc(V),
4028 ISR.getNode()->getVTList(), ReplOpOps);
4029 Ops.push_back(SDValue(ReplOp, 0));
4035 // Because all to-be-promoted nodes only have users that are other
4036 // promoted nodes (or the original INSERT_SUBREG), we can safely replace
4037 // the i32 result value type with i64.
4039 SmallVector<EVT, 2> NewVTs;
4040 SDVTList VTs = PN->getVTList();
4041 for (unsigned i = 0, ie = VTs.NumVTs; i != ie; ++i)
4042 if (VTs.VTs[i] == MVT::i32)
4043 NewVTs.push_back(MVT::i64);
4045 NewVTs.push_back(VTs.VTs[i]);
4047 DEBUG(dbgs() << "PPC64 ZExt Peephole morphing:\nOld: ");
4048 DEBUG(PN->dump(CurDAG));
4050 CurDAG->SelectNodeTo(PN, NewOpcode, CurDAG->getVTList(NewVTs), Ops);
4052 DEBUG(dbgs() << "\nNew: ");
4053 DEBUG(PN->dump(CurDAG));
4054 DEBUG(dbgs() << "\n");
4057 // Now we replace the original zero extend and its associated INSERT_SUBREG
4058 // with the value feeding the INSERT_SUBREG (which has now been promoted to
4061 DEBUG(dbgs() << "PPC64 ZExt Peephole replacing:\nOld: ");
4062 DEBUG(N->dump(CurDAG));
4063 DEBUG(dbgs() << "\nNew: ");
4064 DEBUG(Op32.getNode()->dump(CurDAG));
4065 DEBUG(dbgs() << "\n");
4067 ReplaceUses(N, Op32.getNode());
4071 CurDAG->RemoveDeadNodes();
4074 void PPCDAGToDAGISel::PeepholePPC64() {
4075 // These optimizations are currently supported only for 64-bit SVR4.
4076 if (PPCSubTarget->isDarwin() || !PPCSubTarget->isPPC64())
4079 SelectionDAG::allnodes_iterator Position(CurDAG->getRoot().getNode());
4082 while (Position != CurDAG->allnodes_begin()) {
4083 SDNode *N = --Position;
4084 // Skip dead nodes and any non-machine opcodes.
4085 if (N->use_empty() || !N->isMachineOpcode())
4089 unsigned StorageOpcode = N->getMachineOpcode();
4091 switch (StorageOpcode) {
4122 // If this is a load or store with a zero offset, we may be able to
4123 // fold an add-immediate into the memory operation.
4124 if (!isa<ConstantSDNode>(N->getOperand(FirstOp)) ||
4125 N->getConstantOperandVal(FirstOp) != 0)
4128 SDValue Base = N->getOperand(FirstOp + 1);
4129 if (!Base.isMachineOpcode())
4133 bool ReplaceFlags = true;
4135 // When the feeding operation is an add-immediate of some sort,
4136 // determine whether we need to add relocation information to the
4137 // target flags on the immediate operand when we fold it into the
4138 // load instruction.
4140 // For something like ADDItocL, the relocation information is
4141 // inferred from the opcode; when we process it in the AsmPrinter,
4142 // we add the necessary relocation there. A load, though, can receive
4143 // relocation from various flavors of ADDIxxx, so we need to carry
4144 // the relocation information in the target flags.
4145 switch (Base.getMachineOpcode()) {
4150 // In some cases (such as TLS) the relocation information
4151 // is already in place on the operand, so copying the operand
4153 ReplaceFlags = false;
4154 // For these cases, the immediate may not be divisible by 4, in
4155 // which case the fold is illegal for DS-form instructions. (The
4156 // other cases provide aligned addresses and are always safe.)
4157 if ((StorageOpcode == PPC::LWA ||
4158 StorageOpcode == PPC::LD ||
4159 StorageOpcode == PPC::STD) &&
4160 (!isa<ConstantSDNode>(Base.getOperand(1)) ||
4161 Base.getConstantOperandVal(1) % 4 != 0))
4164 case PPC::ADDIdtprelL:
4165 Flags = PPCII::MO_DTPREL_LO;
4167 case PPC::ADDItlsldL:
4168 Flags = PPCII::MO_TLSLD_LO;
4171 Flags = PPCII::MO_TOC_LO;
4175 // We found an opportunity. Reverse the operands from the add
4176 // immediate and substitute them into the load or store. If
4177 // needed, update the target flags for the immediate operand to
4178 // reflect the necessary relocation information.
4179 DEBUG(dbgs() << "Folding add-immediate into mem-op:\nBase: ");
4180 DEBUG(Base->dump(CurDAG));
4181 DEBUG(dbgs() << "\nN: ");
4182 DEBUG(N->dump(CurDAG));
4183 DEBUG(dbgs() << "\n");
4185 SDValue ImmOpnd = Base.getOperand(1);
4187 // If the relocation information isn't already present on the
4188 // immediate operand, add it now.
4190 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(ImmOpnd)) {
4192 const GlobalValue *GV = GA->getGlobal();
4193 // We can't perform this optimization for data whose alignment
4194 // is insufficient for the instruction encoding.
4195 if (GV->getAlignment() < 4 &&
4196 (StorageOpcode == PPC::LD || StorageOpcode == PPC::STD ||
4197 StorageOpcode == PPC::LWA)) {
4198 DEBUG(dbgs() << "Rejected this candidate for alignment.\n\n");
4201 ImmOpnd = CurDAG->getTargetGlobalAddress(GV, dl, MVT::i64, 0, Flags);
4202 } else if (ConstantPoolSDNode *CP =
4203 dyn_cast<ConstantPoolSDNode>(ImmOpnd)) {
4204 const Constant *C = CP->getConstVal();
4205 ImmOpnd = CurDAG->getTargetConstantPool(C, MVT::i64,
4211 if (FirstOp == 1) // Store
4212 (void)CurDAG->UpdateNodeOperands(N, N->getOperand(0), ImmOpnd,
4213 Base.getOperand(0), N->getOperand(3));
4215 (void)CurDAG->UpdateNodeOperands(N, ImmOpnd, Base.getOperand(0),
4218 // The add-immediate may now be dead, in which case remove it.
4219 if (Base.getNode()->use_empty())
4220 CurDAG->RemoveDeadNode(Base.getNode());
4225 /// createPPCISelDag - This pass converts a legalized DAG into a
4226 /// PowerPC-specific DAG, ready for instruction scheduling.
4228 FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) {
4229 return new PPCDAGToDAGISel(TM);
4232 static void initializePassOnce(PassRegistry &Registry) {
4233 const char *Name = "PowerPC DAG->DAG Pattern Instruction Selection";
4234 PassInfo *PI = new PassInfo(Name, "ppc-codegen", &SelectionDAGISel::ID,
4235 nullptr, false, false);
4236 Registry.registerPass(*PI, true);
4239 void llvm::initializePPCDAGToDAGISelPass(PassRegistry &Registry) {
4240 CALL_ONCE_INITIALIZATION(initializePassOnce);