1 //===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for PowerPC,
11 // converting from a legalized dag to a PPC dag.
13 //===----------------------------------------------------------------------===//
16 #include "MCTargetDesc/PPCPredicates.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCTargetMachine.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/IR/GlobalAlias.h"
27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/IR/GlobalVariable.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Module.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetOptions.h"
39 #define DEBUG_TYPE "ppc-codegen"
41 // FIXME: Remove this once the bug has been fixed!
42 cl::opt<bool> ANDIGlueBug("expose-ppc-andi-glue-bug",
43 cl::desc("expose the ANDI glue bug on PPC"), cl::Hidden);
46 UseBitPermRewriter("ppc-use-bit-perm-rewriter", cl::init(true),
47 cl::desc("use aggressive ppc isel for bit permutations"),
49 static cl::opt<bool> BPermRewriterNoMasking(
50 "ppc-bit-perm-rewriter-stress-rotates",
51 cl::desc("stress rotate selection in aggressive ppc isel for "
56 void initializePPCDAGToDAGISelPass(PassRegistry&);
60 //===--------------------------------------------------------------------===//
61 /// PPCDAGToDAGISel - PPC specific code to select PPC machine
62 /// instructions for SelectionDAG operations.
64 class PPCDAGToDAGISel : public SelectionDAGISel {
65 const PPCTargetMachine &TM;
66 const PPCSubtarget *PPCSubTarget;
67 const PPCTargetLowering *PPCLowering;
68 unsigned GlobalBaseReg;
70 explicit PPCDAGToDAGISel(PPCTargetMachine &tm)
71 : SelectionDAGISel(tm), TM(tm) {
72 initializePPCDAGToDAGISelPass(*PassRegistry::getPassRegistry());
75 bool runOnMachineFunction(MachineFunction &MF) override {
76 // Make sure we re-emit a set of the global base reg if necessary
78 PPCSubTarget = &MF.getSubtarget<PPCSubtarget>();
79 PPCLowering = PPCSubTarget->getTargetLowering();
80 SelectionDAGISel::runOnMachineFunction(MF);
82 if (!PPCSubTarget->isSVR4ABI())
88 void PreprocessISelDAG() override;
89 void PostprocessISelDAG() override;
91 /// getI32Imm - Return a target constant with the specified value, of type
93 inline SDValue getI32Imm(unsigned Imm, SDLoc dl) {
94 return CurDAG->getTargetConstant(Imm, dl, MVT::i32);
97 /// getI64Imm - Return a target constant with the specified value, of type
99 inline SDValue getI64Imm(uint64_t Imm, SDLoc dl) {
100 return CurDAG->getTargetConstant(Imm, dl, MVT::i64);
103 /// getSmallIPtrImm - Return a target constant of pointer type.
104 inline SDValue getSmallIPtrImm(unsigned Imm, SDLoc dl) {
105 return CurDAG->getTargetConstant(
106 Imm, dl, PPCLowering->getPointerTy(CurDAG->getDataLayout()));
109 /// isRotateAndMask - Returns true if Mask and Shift can be folded into a
110 /// rotate and mask opcode and mask operation.
111 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool isShiftMask,
112 unsigned &SH, unsigned &MB, unsigned &ME);
114 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
115 /// base register. Return the virtual register that holds this value.
116 SDNode *getGlobalBaseReg();
118 SDNode *getFrameIndex(SDNode *SN, SDNode *N, unsigned Offset = 0);
120 // Select - Convert the specified operand from a target-independent to a
121 // target-specific node if it hasn't already been changed.
122 SDNode *Select(SDNode *N) override;
124 SDNode *SelectBitfieldInsert(SDNode *N);
125 SDNode *SelectBitPermutation(SDNode *N);
127 /// SelectCC - Select a comparison of the specified values with the
128 /// specified condition code, returning the CR# of the expression.
129 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDLoc dl);
131 /// SelectAddrImm - Returns true if the address N can be represented by
132 /// a base register plus a signed 16-bit displacement [r+imm].
133 bool SelectAddrImm(SDValue N, SDValue &Disp,
135 return PPCLowering->SelectAddressRegImm(N, Disp, Base, *CurDAG, false);
138 /// SelectAddrImmOffs - Return true if the operand is valid for a preinc
139 /// immediate field. Note that the operand at this point is already the
140 /// result of a prior SelectAddressRegImm call.
141 bool SelectAddrImmOffs(SDValue N, SDValue &Out) const {
142 if (N.getOpcode() == ISD::TargetConstant ||
143 N.getOpcode() == ISD::TargetGlobalAddress) {
151 /// SelectAddrIdx - Given the specified addressed, check to see if it can be
152 /// represented as an indexed [r+r] operation. Returns false if it can
153 /// be represented by [r+imm], which are preferred.
154 bool SelectAddrIdx(SDValue N, SDValue &Base, SDValue &Index) {
155 return PPCLowering->SelectAddressRegReg(N, Base, Index, *CurDAG);
158 /// SelectAddrIdxOnly - Given the specified addressed, force it to be
159 /// represented as an indexed [r+r] operation.
160 bool SelectAddrIdxOnly(SDValue N, SDValue &Base, SDValue &Index) {
161 return PPCLowering->SelectAddressRegRegOnly(N, Base, Index, *CurDAG);
164 /// SelectAddrImmX4 - Returns true if the address N can be represented by
165 /// a base register plus a signed 16-bit displacement that is a multiple of 4.
166 /// Suitable for use by STD and friends.
167 bool SelectAddrImmX4(SDValue N, SDValue &Disp, SDValue &Base) {
168 return PPCLowering->SelectAddressRegImm(N, Disp, Base, *CurDAG, true);
171 // Select an address into a single register.
172 bool SelectAddr(SDValue N, SDValue &Base) {
177 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
178 /// inline asm expressions. It is always correct to compute the value into
179 /// a register. The case of adding a (possibly relocatable) constant to a
180 /// register can be improved, but it is wrong to substitute Reg+Reg for
181 /// Reg in an asm, because the load or store opcode would have to change.
182 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
183 unsigned ConstraintID,
184 std::vector<SDValue> &OutOps) override {
186 switch(ConstraintID) {
188 errs() << "ConstraintID: " << ConstraintID << "\n";
189 llvm_unreachable("Unexpected asm memory constraint");
190 case InlineAsm::Constraint_es:
191 case InlineAsm::Constraint_i:
192 case InlineAsm::Constraint_m:
193 case InlineAsm::Constraint_o:
194 case InlineAsm::Constraint_Q:
195 case InlineAsm::Constraint_Z:
196 case InlineAsm::Constraint_Zy:
197 // We need to make sure that this one operand does not end up in r0
198 // (because we might end up lowering this as 0(%op)).
199 const TargetRegisterInfo *TRI = PPCSubTarget->getRegisterInfo();
200 const TargetRegisterClass *TRC = TRI->getPointerRegClass(*MF, /*Kind=*/1);
202 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i32);
204 SDValue(CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
205 dl, Op.getValueType(),
208 OutOps.push_back(NewOp);
214 void InsertVRSaveCode(MachineFunction &MF);
216 const char *getPassName() const override {
217 return "PowerPC DAG->DAG Pattern Instruction Selection";
220 // Include the pieces autogenerated from the target description.
221 #include "PPCGenDAGISel.inc"
224 SDNode *SelectSETCC(SDNode *N);
226 void PeepholePPC64();
227 void PeepholePPC64ZExt();
228 void PeepholeCROps();
230 SDValue combineToCMPB(SDNode *N);
231 void foldBoolExts(SDValue &Res, SDNode *&N);
233 bool AllUsersSelectZero(SDNode *N);
234 void SwapAllSelectUsers(SDNode *N);
236 SDNode *transferMemOperands(SDNode *N, SDNode *Result);
240 /// InsertVRSaveCode - Once the entire function has been instruction selected,
241 /// all virtual registers are created and all machine instructions are built,
242 /// check to see if we need to save/restore VRSAVE. If so, do it.
243 void PPCDAGToDAGISel::InsertVRSaveCode(MachineFunction &Fn) {
244 // Check to see if this function uses vector registers, which means we have to
245 // save and restore the VRSAVE register and update it with the regs we use.
247 // In this case, there will be virtual registers of vector type created
248 // by the scheduler. Detect them now.
249 bool HasVectorVReg = false;
250 for (unsigned i = 0, e = RegInfo->getNumVirtRegs(); i != e; ++i) {
251 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
252 if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) {
253 HasVectorVReg = true;
257 if (!HasVectorVReg) return; // nothing to do.
259 // If we have a vector register, we want to emit code into the entry and exit
260 // blocks to save and restore the VRSAVE register. We do this here (instead
261 // of marking all vector instructions as clobbering VRSAVE) for two reasons:
263 // 1. This (trivially) reduces the load on the register allocator, by not
264 // having to represent the live range of the VRSAVE register.
265 // 2. This (more significantly) allows us to create a temporary virtual
266 // register to hold the saved VRSAVE value, allowing this temporary to be
267 // register allocated, instead of forcing it to be spilled to the stack.
269 // Create two vregs - one to hold the VRSAVE register that is live-in to the
270 // function and one for the value after having bits or'd into it.
271 unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
272 unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
274 const TargetInstrInfo &TII = *PPCSubTarget->getInstrInfo();
275 MachineBasicBlock &EntryBB = *Fn.begin();
277 // Emit the following code into the entry block:
278 // InVRSAVE = MFVRSAVE
279 // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
280 // MTVRSAVE UpdatedVRSAVE
281 MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
282 BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE);
283 BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE),
284 UpdatedVRSAVE).addReg(InVRSAVE);
285 BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
287 // Find all return blocks, outputting a restore in each epilog.
288 for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
289 if (!BB->empty() && BB->back().isReturn()) {
290 IP = BB->end(); --IP;
292 // Skip over all terminator instructions, which are part of the return
294 MachineBasicBlock::iterator I2 = IP;
295 while (I2 != BB->begin() && (--I2)->isTerminator())
298 // Emit: MTVRSAVE InVRSave
299 BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
305 /// getGlobalBaseReg - Output the instructions required to put the
306 /// base address to use for accessing globals into a register.
308 SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
309 if (!GlobalBaseReg) {
310 const TargetInstrInfo &TII = *PPCSubTarget->getInstrInfo();
311 // Insert the set of GlobalBaseReg into the first MBB of the function
312 MachineBasicBlock &FirstMBB = MF->front();
313 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
314 const Module *M = MF->getFunction()->getParent();
317 if (PPCLowering->getPointerTy(CurDAG->getDataLayout()) == MVT::i32) {
318 if (PPCSubTarget->isTargetELF()) {
319 GlobalBaseReg = PPC::R30;
320 if (M->getPICLevel() == PICLevel::Small) {
321 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MoveGOTtoLR));
322 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
323 MF->getInfo<PPCFunctionInfo>()->setUsesPICBase(true);
325 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));
326 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
327 unsigned TempReg = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
328 BuildMI(FirstMBB, MBBI, dl,
329 TII.get(PPC::UpdateGBR), GlobalBaseReg)
330 .addReg(TempReg, RegState::Define).addReg(GlobalBaseReg);
331 MF->getInfo<PPCFunctionInfo>()->setUsesPICBase(true);
335 RegInfo->createVirtualRegister(&PPC::GPRC_NOR0RegClass);
336 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));
337 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
340 GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::G8RC_NOX0RegClass);
341 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8));
342 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg);
345 return CurDAG->getRegister(GlobalBaseReg,
346 PPCLowering->getPointerTy(CurDAG->getDataLayout()))
350 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
351 /// or 64-bit immediate, and if the value can be accurately represented as a
352 /// sign extension from a 16-bit value. If so, this returns true and the
354 static bool isIntS16Immediate(SDNode *N, short &Imm) {
355 if (N->getOpcode() != ISD::Constant)
358 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
359 if (N->getValueType(0) == MVT::i32)
360 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
362 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
365 static bool isIntS16Immediate(SDValue Op, short &Imm) {
366 return isIntS16Immediate(Op.getNode(), Imm);
370 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
371 /// operand. If so Imm will receive the 32-bit value.
372 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
373 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
374 Imm = cast<ConstantSDNode>(N)->getZExtValue();
380 /// isInt64Immediate - This method tests to see if the node is a 64-bit constant
381 /// operand. If so Imm will receive the 64-bit value.
382 static bool isInt64Immediate(SDNode *N, uint64_t &Imm) {
383 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
384 Imm = cast<ConstantSDNode>(N)->getZExtValue();
390 // isInt32Immediate - This method tests to see if a constant operand.
391 // If so Imm will receive the 32 bit value.
392 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
393 return isInt32Immediate(N.getNode(), Imm);
397 // isOpcWithIntImmediate - This method tests to see if the node is a specific
398 // opcode and that it has a immediate integer right operand.
399 // If so Imm will receive the 32 bit value.
400 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
401 return N->getOpcode() == Opc
402 && isInt32Immediate(N->getOperand(1).getNode(), Imm);
405 SDNode *PPCDAGToDAGISel::getFrameIndex(SDNode *SN, SDNode *N, unsigned Offset) {
407 int FI = cast<FrameIndexSDNode>(N)->getIndex();
408 SDValue TFI = CurDAG->getTargetFrameIndex(FI, N->getValueType(0));
409 unsigned Opc = N->getValueType(0) == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
411 return CurDAG->SelectNodeTo(SN, Opc, N->getValueType(0), TFI,
412 getSmallIPtrImm(Offset, dl));
413 return CurDAG->getMachineNode(Opc, dl, N->getValueType(0), TFI,
414 getSmallIPtrImm(Offset, dl));
417 bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask,
418 bool isShiftMask, unsigned &SH,
419 unsigned &MB, unsigned &ME) {
420 // Don't even go down this path for i64, since different logic will be
421 // necessary for rldicl/rldicr/rldimi.
422 if (N->getValueType(0) != MVT::i32)
426 unsigned Indeterminant = ~0; // bit mask marking indeterminant results
427 unsigned Opcode = N->getOpcode();
428 if (N->getNumOperands() != 2 ||
429 !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31))
432 if (Opcode == ISD::SHL) {
433 // apply shift left to mask if it comes first
434 if (isShiftMask) Mask = Mask << Shift;
435 // determine which bits are made indeterminant by shift
436 Indeterminant = ~(0xFFFFFFFFu << Shift);
437 } else if (Opcode == ISD::SRL) {
438 // apply shift right to mask if it comes first
439 if (isShiftMask) Mask = Mask >> Shift;
440 // determine which bits are made indeterminant by shift
441 Indeterminant = ~(0xFFFFFFFFu >> Shift);
442 // adjust for the left rotate
444 } else if (Opcode == ISD::ROTL) {
450 // if the mask doesn't intersect any Indeterminant bits
451 if (Mask && !(Mask & Indeterminant)) {
453 // make sure the mask is still a mask (wrap arounds may not be)
454 return isRunOfOnes(Mask, MB, ME);
459 /// SelectBitfieldInsert - turn an or of two masked values into
460 /// the rotate left word immediate then mask insert (rlwimi) instruction.
461 SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
462 SDValue Op0 = N->getOperand(0);
463 SDValue Op1 = N->getOperand(1);
466 APInt LKZ, LKO, RKZ, RKO;
467 CurDAG->computeKnownBits(Op0, LKZ, LKO);
468 CurDAG->computeKnownBits(Op1, RKZ, RKO);
470 unsigned TargetMask = LKZ.getZExtValue();
471 unsigned InsertMask = RKZ.getZExtValue();
473 if ((TargetMask | InsertMask) == 0xFFFFFFFF) {
474 unsigned Op0Opc = Op0.getOpcode();
475 unsigned Op1Opc = Op1.getOpcode();
476 unsigned Value, SH = 0;
477 TargetMask = ~TargetMask;
478 InsertMask = ~InsertMask;
480 // If the LHS has a foldable shift and the RHS does not, then swap it to the
481 // RHS so that we can fold the shift into the insert.
482 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
483 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
484 Op0.getOperand(0).getOpcode() == ISD::SRL) {
485 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
486 Op1.getOperand(0).getOpcode() != ISD::SRL) {
488 std::swap(Op0Opc, Op1Opc);
489 std::swap(TargetMask, InsertMask);
492 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
493 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
494 Op1.getOperand(0).getOpcode() != ISD::SRL) {
496 std::swap(Op0Opc, Op1Opc);
497 std::swap(TargetMask, InsertMask);
502 if (isRunOfOnes(InsertMask, MB, ME)) {
505 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
506 isInt32Immediate(Op1.getOperand(1), Value)) {
507 Op1 = Op1.getOperand(0);
508 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value;
510 if (Op1Opc == ISD::AND) {
511 // The AND mask might not be a constant, and we need to make sure that
512 // if we're going to fold the masking with the insert, all bits not
513 // know to be zero in the mask are known to be one.
515 CurDAG->computeKnownBits(Op1.getOperand(1), MKZ, MKO);
516 bool CanFoldMask = InsertMask == MKO.getZExtValue();
518 unsigned SHOpc = Op1.getOperand(0).getOpcode();
519 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && CanFoldMask &&
520 isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) {
521 // Note that Value must be in range here (less than 32) because
522 // otherwise there would not be any bits set in InsertMask.
523 Op1 = Op1.getOperand(0).getOperand(0);
524 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value;
529 SDValue Ops[] = { Op0, Op1, getI32Imm(SH, dl), getI32Imm(MB, dl),
531 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops);
537 // Predict the number of instructions that would be generated by calling
539 static unsigned SelectInt64CountDirect(int64_t Imm) {
540 // Assume no remaining bits.
541 unsigned Remainder = 0;
542 // Assume no shift required.
545 // If it can't be represented as a 32 bit value.
546 if (!isInt<32>(Imm)) {
547 Shift = countTrailingZeros<uint64_t>(Imm);
548 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
550 // If the shifted value fits 32 bits.
551 if (isInt<32>(ImmSh)) {
552 // Go with the shifted value.
555 // Still stuck with a 64 bit value.
562 // Intermediate operand.
565 // Handle first 32 bits.
566 unsigned Lo = Imm & 0xFFFF;
567 unsigned Hi = (Imm >> 16) & 0xFFFF;
570 if (isInt<16>(Imm)) {
574 // Handle the Hi bits and Lo bits.
581 // If no shift, we're done.
582 if (!Shift) return Result;
584 // Shift for next step if the upper 32-bits were not zero.
588 // Add in the last bits as required.
589 if ((Hi = (Remainder >> 16) & 0xFFFF))
591 if ((Lo = Remainder & 0xFFFF))
597 static uint64_t Rot64(uint64_t Imm, unsigned R) {
598 return (Imm << R) | (Imm >> (64 - R));
601 static unsigned SelectInt64Count(int64_t Imm) {
602 unsigned Count = SelectInt64CountDirect(Imm);
606 for (unsigned r = 1; r < 63; ++r) {
607 uint64_t RImm = Rot64(Imm, r);
608 unsigned RCount = SelectInt64CountDirect(RImm) + 1;
609 Count = std::min(Count, RCount);
611 // See comments in SelectInt64 for an explanation of the logic below.
612 unsigned LS = findLastSet(RImm);
616 uint64_t OnesMask = -(int64_t) (UINT64_C(1) << (LS+1));
617 uint64_t RImmWithOnes = RImm | OnesMask;
619 RCount = SelectInt64CountDirect(RImmWithOnes) + 1;
620 Count = std::min(Count, RCount);
626 // Select a 64-bit constant. For cost-modeling purposes, SelectInt64Count
627 // (above) needs to be kept in sync with this function.
628 static SDNode *SelectInt64Direct(SelectionDAG *CurDAG, SDLoc dl, int64_t Imm) {
629 // Assume no remaining bits.
630 unsigned Remainder = 0;
631 // Assume no shift required.
634 // If it can't be represented as a 32 bit value.
635 if (!isInt<32>(Imm)) {
636 Shift = countTrailingZeros<uint64_t>(Imm);
637 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
639 // If the shifted value fits 32 bits.
640 if (isInt<32>(ImmSh)) {
641 // Go with the shifted value.
644 // Still stuck with a 64 bit value.
651 // Intermediate operand.
654 // Handle first 32 bits.
655 unsigned Lo = Imm & 0xFFFF;
656 unsigned Hi = (Imm >> 16) & 0xFFFF;
658 auto getI32Imm = [CurDAG, dl](unsigned Imm) {
659 return CurDAG->getTargetConstant(Imm, dl, MVT::i32);
663 if (isInt<16>(Imm)) {
665 Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo));
667 // Handle the Hi bits.
668 unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8;
669 Result = CurDAG->getMachineNode(OpC, dl, MVT::i64, getI32Imm(Hi));
671 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
672 SDValue(Result, 0), getI32Imm(Lo));
675 Result = CurDAG->getMachineNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi));
678 // If no shift, we're done.
679 if (!Shift) return Result;
681 // Shift for next step if the upper 32-bits were not zero.
683 Result = CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64,
686 getI32Imm(63 - Shift));
689 // Add in the last bits as required.
690 if ((Hi = (Remainder >> 16) & 0xFFFF)) {
691 Result = CurDAG->getMachineNode(PPC::ORIS8, dl, MVT::i64,
692 SDValue(Result, 0), getI32Imm(Hi));
694 if ((Lo = Remainder & 0xFFFF)) {
695 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
696 SDValue(Result, 0), getI32Imm(Lo));
702 static SDNode *SelectInt64(SelectionDAG *CurDAG, SDLoc dl, int64_t Imm) {
703 unsigned Count = SelectInt64CountDirect(Imm);
705 return SelectInt64Direct(CurDAG, dl, Imm);
712 for (unsigned r = 1; r < 63; ++r) {
713 uint64_t RImm = Rot64(Imm, r);
714 unsigned RCount = SelectInt64CountDirect(RImm) + 1;
715 if (RCount < Count) {
722 // If the immediate to generate has many trailing zeros, it might be
723 // worthwhile to generate a rotated value with too many leading ones
724 // (because that's free with li/lis's sign-extension semantics), and then
725 // mask them off after rotation.
727 unsigned LS = findLastSet(RImm);
728 // We're adding (63-LS) higher-order ones, and we expect to mask them off
729 // after performing the inverse rotation by (64-r). So we need that:
730 // 63-LS == 64-r => LS == r-1
734 uint64_t OnesMask = -(int64_t) (UINT64_C(1) << (LS+1));
735 uint64_t RImmWithOnes = RImm | OnesMask;
737 RCount = SelectInt64CountDirect(RImmWithOnes) + 1;
738 if (RCount < Count) {
741 MatImm = RImmWithOnes;
747 return SelectInt64Direct(CurDAG, dl, Imm);
749 auto getI32Imm = [CurDAG, dl](unsigned Imm) {
750 return CurDAG->getTargetConstant(Imm, dl, MVT::i32);
753 SDValue Val = SDValue(SelectInt64Direct(CurDAG, dl, MatImm), 0);
754 return CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64, Val,
755 getI32Imm(64 - RMin), getI32Imm(MaskEnd));
758 // Select a 64-bit constant.
759 static SDNode *SelectInt64(SelectionDAG *CurDAG, SDNode *N) {
763 int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue();
764 return SelectInt64(CurDAG, dl, Imm);
768 class BitPermutationSelector {
772 // The bit number in the value, using a convention where bit 0 is the
781 ValueBit(SDValue V, unsigned I, Kind K = Variable)
782 : V(V), Idx(I), K(K) {}
783 ValueBit(Kind K = Variable)
784 : V(SDValue(nullptr, 0)), Idx(UINT32_MAX), K(K) {}
786 bool isZero() const {
787 return K == ConstZero;
790 bool hasValue() const {
791 return K == Variable;
794 SDValue getValue() const {
795 assert(hasValue() && "Cannot get the value of a constant bit");
799 unsigned getValueBitIndex() const {
800 assert(hasValue() && "Cannot get the value bit index of a constant bit");
805 // A bit group has the same underlying value and the same rotate factor.
809 unsigned StartIdx, EndIdx;
811 // This rotation amount assumes that the lower 32 bits of the quantity are
812 // replicated in the high 32 bits by the rotation operator (which is done
813 // by rlwinm and friends in 64-bit mode).
815 // Did converting to Repl32 == true change the rotation factor? If it did,
816 // it decreased it by 32.
818 // Was this group coalesced after setting Repl32 to true?
819 bool Repl32Coalesced;
821 BitGroup(SDValue V, unsigned R, unsigned S, unsigned E)
822 : V(V), RLAmt(R), StartIdx(S), EndIdx(E), Repl32(false), Repl32CR(false),
823 Repl32Coalesced(false) {
824 DEBUG(dbgs() << "\tbit group for " << V.getNode() << " RLAmt = " << R <<
825 " [" << S << ", " << E << "]\n");
829 // Information on each (Value, RLAmt) pair (like the number of groups
830 // associated with each) used to choose the lowering method.
831 struct ValueRotInfo {
835 unsigned FirstGroupStartIdx;
839 : RLAmt(UINT32_MAX), NumGroups(0), FirstGroupStartIdx(UINT32_MAX),
842 // For sorting (in reverse order) by NumGroups, and then by
843 // FirstGroupStartIdx.
844 bool operator < (const ValueRotInfo &Other) const {
845 // We need to sort so that the non-Repl32 come first because, when we're
846 // doing masking, the Repl32 bit groups might be subsumed into the 64-bit
847 // masking operation.
848 if (Repl32 < Other.Repl32)
850 else if (Repl32 > Other.Repl32)
852 else if (NumGroups > Other.NumGroups)
854 else if (NumGroups < Other.NumGroups)
856 else if (FirstGroupStartIdx < Other.FirstGroupStartIdx)
862 // Return true if something interesting was deduced, return false if we're
863 // providing only a generic representation of V (or something else likewise
864 // uninteresting for instruction selection).
865 bool getValueBits(SDValue V, SmallVector<ValueBit, 64> &Bits) {
866 switch (V.getOpcode()) {
869 if (isa<ConstantSDNode>(V.getOperand(1))) {
870 unsigned RotAmt = V.getConstantOperandVal(1);
872 SmallVector<ValueBit, 64> LHSBits(Bits.size());
873 getValueBits(V.getOperand(0), LHSBits);
875 for (unsigned i = 0; i < Bits.size(); ++i)
876 Bits[i] = LHSBits[i < RotAmt ? i + (Bits.size() - RotAmt) : i - RotAmt];
882 if (isa<ConstantSDNode>(V.getOperand(1))) {
883 unsigned ShiftAmt = V.getConstantOperandVal(1);
885 SmallVector<ValueBit, 64> LHSBits(Bits.size());
886 getValueBits(V.getOperand(0), LHSBits);
888 for (unsigned i = ShiftAmt; i < Bits.size(); ++i)
889 Bits[i] = LHSBits[i - ShiftAmt];
891 for (unsigned i = 0; i < ShiftAmt; ++i)
892 Bits[i] = ValueBit(ValueBit::ConstZero);
898 if (isa<ConstantSDNode>(V.getOperand(1))) {
899 unsigned ShiftAmt = V.getConstantOperandVal(1);
901 SmallVector<ValueBit, 64> LHSBits(Bits.size());
902 getValueBits(V.getOperand(0), LHSBits);
904 for (unsigned i = 0; i < Bits.size() - ShiftAmt; ++i)
905 Bits[i] = LHSBits[i + ShiftAmt];
907 for (unsigned i = Bits.size() - ShiftAmt; i < Bits.size(); ++i)
908 Bits[i] = ValueBit(ValueBit::ConstZero);
914 if (isa<ConstantSDNode>(V.getOperand(1))) {
915 uint64_t Mask = V.getConstantOperandVal(1);
917 SmallVector<ValueBit, 64> LHSBits(Bits.size());
918 bool LHSTrivial = getValueBits(V.getOperand(0), LHSBits);
920 for (unsigned i = 0; i < Bits.size(); ++i)
921 if (((Mask >> i) & 1) == 1)
922 Bits[i] = LHSBits[i];
924 Bits[i] = ValueBit(ValueBit::ConstZero);
926 // Mark this as interesting, only if the LHS was also interesting. This
927 // prevents the overall procedure from matching a single immediate 'and'
928 // (which is non-optimal because such an and might be folded with other
929 // things if we don't select it here).
934 SmallVector<ValueBit, 64> LHSBits(Bits.size()), RHSBits(Bits.size());
935 getValueBits(V.getOperand(0), LHSBits);
936 getValueBits(V.getOperand(1), RHSBits);
938 bool AllDisjoint = true;
939 for (unsigned i = 0; i < Bits.size(); ++i)
940 if (LHSBits[i].isZero())
941 Bits[i] = RHSBits[i];
942 else if (RHSBits[i].isZero())
943 Bits[i] = LHSBits[i];
956 for (unsigned i = 0; i < Bits.size(); ++i)
957 Bits[i] = ValueBit(V, i);
962 // For each value (except the constant ones), compute the left-rotate amount
963 // to get it from its original to final position.
964 void computeRotationAmounts() {
966 RLAmt.resize(Bits.size());
967 for (unsigned i = 0; i < Bits.size(); ++i)
968 if (Bits[i].hasValue()) {
969 unsigned VBI = Bits[i].getValueBitIndex();
973 RLAmt[i] = Bits.size() - (VBI - i);
974 } else if (Bits[i].isZero()) {
976 RLAmt[i] = UINT32_MAX;
978 llvm_unreachable("Unknown value bit type");
982 // Collect groups of consecutive bits with the same underlying value and
983 // rotation factor. If we're doing late masking, we ignore zeros, otherwise
984 // they break up groups.
985 void collectBitGroups(bool LateMask) {
988 unsigned LastRLAmt = RLAmt[0];
989 SDValue LastValue = Bits[0].hasValue() ? Bits[0].getValue() : SDValue();
990 unsigned LastGroupStartIdx = 0;
991 for (unsigned i = 1; i < Bits.size(); ++i) {
992 unsigned ThisRLAmt = RLAmt[i];
993 SDValue ThisValue = Bits[i].hasValue() ? Bits[i].getValue() : SDValue();
994 if (LateMask && !ThisValue) {
995 ThisValue = LastValue;
996 ThisRLAmt = LastRLAmt;
997 // If we're doing late masking, then the first bit group always starts
998 // at zero (even if the first bits were zero).
999 if (BitGroups.empty())
1000 LastGroupStartIdx = 0;
1003 // If this bit has the same underlying value and the same rotate factor as
1004 // the last one, then they're part of the same group.
1005 if (ThisRLAmt == LastRLAmt && ThisValue == LastValue)
1008 if (LastValue.getNode())
1009 BitGroups.push_back(BitGroup(LastValue, LastRLAmt, LastGroupStartIdx,
1011 LastRLAmt = ThisRLAmt;
1012 LastValue = ThisValue;
1013 LastGroupStartIdx = i;
1015 if (LastValue.getNode())
1016 BitGroups.push_back(BitGroup(LastValue, LastRLAmt, LastGroupStartIdx,
1019 if (BitGroups.empty())
1022 // We might be able to combine the first and last groups.
1023 if (BitGroups.size() > 1) {
1024 // If the first and last groups are the same, then remove the first group
1025 // in favor of the last group, making the ending index of the last group
1026 // equal to the ending index of the to-be-removed first group.
1027 if (BitGroups[0].StartIdx == 0 &&
1028 BitGroups[BitGroups.size()-1].EndIdx == Bits.size()-1 &&
1029 BitGroups[0].V == BitGroups[BitGroups.size()-1].V &&
1030 BitGroups[0].RLAmt == BitGroups[BitGroups.size()-1].RLAmt) {
1031 DEBUG(dbgs() << "\tcombining final bit group with initial one\n");
1032 BitGroups[BitGroups.size()-1].EndIdx = BitGroups[0].EndIdx;
1033 BitGroups.erase(BitGroups.begin());
1038 // Take all (SDValue, RLAmt) pairs and sort them by the number of groups
1039 // associated with each. If there is a degeneracy, pick the one that occurs
1040 // first (in the final value).
1041 void collectValueRotInfo() {
1044 for (auto &BG : BitGroups) {
1045 unsigned RLAmtKey = BG.RLAmt + (BG.Repl32 ? 64 : 0);
1046 ValueRotInfo &VRI = ValueRots[std::make_pair(BG.V, RLAmtKey)];
1048 VRI.RLAmt = BG.RLAmt;
1049 VRI.Repl32 = BG.Repl32;
1051 VRI.FirstGroupStartIdx = std::min(VRI.FirstGroupStartIdx, BG.StartIdx);
1054 // Now that we've collected the various ValueRotInfo instances, we need to
1056 ValueRotsVec.clear();
1057 for (auto &I : ValueRots) {
1058 ValueRotsVec.push_back(I.second);
1060 std::sort(ValueRotsVec.begin(), ValueRotsVec.end());
1063 // In 64-bit mode, rlwinm and friends have a rotation operator that
1064 // replicates the low-order 32 bits into the high-order 32-bits. The mask
1065 // indices of these instructions can only be in the lower 32 bits, so they
1066 // can only represent some 64-bit bit groups. However, when they can be used,
1067 // the 32-bit replication can be used to represent, as a single bit group,
1068 // otherwise separate bit groups. We'll convert to replicated-32-bit bit
1069 // groups when possible. Returns true if any of the bit groups were
1071 void assignRepl32BitGroups() {
1072 // If we have bits like this:
1074 // Indices: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1075 // V bits: ... 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24
1076 // Groups: | RLAmt = 8 | RLAmt = 40 |
1078 // But, making use of a 32-bit operation that replicates the low-order 32
1079 // bits into the high-order 32 bits, this can be one bit group with a RLAmt
1082 auto IsAllLow32 = [this](BitGroup & BG) {
1083 if (BG.StartIdx <= BG.EndIdx) {
1084 for (unsigned i = BG.StartIdx; i <= BG.EndIdx; ++i) {
1085 if (!Bits[i].hasValue())
1087 if (Bits[i].getValueBitIndex() >= 32)
1091 for (unsigned i = BG.StartIdx; i < Bits.size(); ++i) {
1092 if (!Bits[i].hasValue())
1094 if (Bits[i].getValueBitIndex() >= 32)
1097 for (unsigned i = 0; i <= BG.EndIdx; ++i) {
1098 if (!Bits[i].hasValue())
1100 if (Bits[i].getValueBitIndex() >= 32)
1108 for (auto &BG : BitGroups) {
1109 if (BG.StartIdx < 32 && BG.EndIdx < 32) {
1110 if (IsAllLow32(BG)) {
1111 if (BG.RLAmt >= 32) {
1118 DEBUG(dbgs() << "\t32-bit replicated bit group for " <<
1119 BG.V.getNode() << " RLAmt = " << BG.RLAmt <<
1120 " [" << BG.StartIdx << ", " << BG.EndIdx << "]\n");
1125 // Now walk through the bit groups, consolidating where possible.
1126 for (auto I = BitGroups.begin(); I != BitGroups.end();) {
1127 // We might want to remove this bit group by merging it with the previous
1128 // group (which might be the ending group).
1129 auto IP = (I == BitGroups.begin()) ?
1130 std::prev(BitGroups.end()) : std::prev(I);
1131 if (I->Repl32 && IP->Repl32 && I->V == IP->V && I->RLAmt == IP->RLAmt &&
1132 I->StartIdx == (IP->EndIdx + 1) % 64 && I != IP) {
1134 DEBUG(dbgs() << "\tcombining 32-bit replicated bit group for " <<
1135 I->V.getNode() << " RLAmt = " << I->RLAmt <<
1136 " [" << I->StartIdx << ", " << I->EndIdx <<
1137 "] with group with range [" <<
1138 IP->StartIdx << ", " << IP->EndIdx << "]\n");
1140 IP->EndIdx = I->EndIdx;
1141 IP->Repl32CR = IP->Repl32CR || I->Repl32CR;
1142 IP->Repl32Coalesced = true;
1143 I = BitGroups.erase(I);
1146 // There is a special case worth handling: If there is a single group
1147 // covering the entire upper 32 bits, and it can be merged with both
1148 // the next and previous groups (which might be the same group), then
1149 // do so. If it is the same group (so there will be only one group in
1150 // total), then we need to reverse the order of the range so that it
1151 // covers the entire 64 bits.
1152 if (I->StartIdx == 32 && I->EndIdx == 63) {
1153 assert(std::next(I) == BitGroups.end() &&
1154 "bit group ends at index 63 but there is another?");
1155 auto IN = BitGroups.begin();
1157 if (IP->Repl32 && IN->Repl32 && I->V == IP->V && I->V == IN->V &&
1158 (I->RLAmt % 32) == IP->RLAmt && (I->RLAmt % 32) == IN->RLAmt &&
1159 IP->EndIdx == 31 && IN->StartIdx == 0 && I != IP &&
1162 DEBUG(dbgs() << "\tcombining bit group for " <<
1163 I->V.getNode() << " RLAmt = " << I->RLAmt <<
1164 " [" << I->StartIdx << ", " << I->EndIdx <<
1165 "] with 32-bit replicated groups with ranges [" <<
1166 IP->StartIdx << ", " << IP->EndIdx << "] and [" <<
1167 IN->StartIdx << ", " << IN->EndIdx << "]\n");
1170 // There is only one other group; change it to cover the whole
1171 // range (backward, so that it can still be Repl32 but cover the
1172 // whole 64-bit range).
1175 IP->Repl32CR = IP->Repl32CR || I->RLAmt >= 32;
1176 IP->Repl32Coalesced = true;
1177 I = BitGroups.erase(I);
1179 // There are two separate groups, one before this group and one
1180 // after us (at the beginning). We're going to remove this group,
1181 // but also the group at the very beginning.
1182 IP->EndIdx = IN->EndIdx;
1183 IP->Repl32CR = IP->Repl32CR || IN->Repl32CR || I->RLAmt >= 32;
1184 IP->Repl32Coalesced = true;
1185 I = BitGroups.erase(I);
1186 BitGroups.erase(BitGroups.begin());
1189 // This must be the last group in the vector (and we might have
1190 // just invalidated the iterator above), so break here.
1200 SDValue getI32Imm(unsigned Imm, SDLoc dl) {
1201 return CurDAG->getTargetConstant(Imm, dl, MVT::i32);
1204 uint64_t getZerosMask() {
1206 for (unsigned i = 0; i < Bits.size(); ++i) {
1207 if (Bits[i].hasValue())
1209 Mask |= (UINT64_C(1) << i);
1215 // Depending on the number of groups for a particular value, it might be
1216 // better to rotate, mask explicitly (using andi/andis), and then or the
1217 // result. Select this part of the result first.
1218 void SelectAndParts32(SDLoc dl, SDValue &Res, unsigned *InstCnt) {
1219 if (BPermRewriterNoMasking)
1222 for (ValueRotInfo &VRI : ValueRotsVec) {
1224 for (unsigned i = 0; i < Bits.size(); ++i) {
1225 if (!Bits[i].hasValue() || Bits[i].getValue() != VRI.V)
1227 if (RLAmt[i] != VRI.RLAmt)
1232 // Compute the masks for andi/andis that would be necessary.
1233 unsigned ANDIMask = (Mask & UINT16_MAX), ANDISMask = Mask >> 16;
1234 assert((ANDIMask != 0 || ANDISMask != 0) &&
1235 "No set bits in mask for value bit groups");
1236 bool NeedsRotate = VRI.RLAmt != 0;
1238 // We're trying to minimize the number of instructions. If we have one
1239 // group, using one of andi/andis can break even. If we have three
1240 // groups, we can use both andi and andis and break even (to use both
1241 // andi and andis we also need to or the results together). We need four
1242 // groups if we also need to rotate. To use andi/andis we need to do more
1243 // than break even because rotate-and-mask instructions tend to be easier
1246 // FIXME: We've biased here against using andi/andis, which is right for
1247 // POWER cores, but not optimal everywhere. For example, on the A2,
1248 // andi/andis have single-cycle latency whereas the rotate-and-mask
1249 // instructions take two cycles, and it would be better to bias toward
1250 // andi/andis in break-even cases.
1252 unsigned NumAndInsts = (unsigned) NeedsRotate +
1253 (unsigned) (ANDIMask != 0) +
1254 (unsigned) (ANDISMask != 0) +
1255 (unsigned) (ANDIMask != 0 && ANDISMask != 0) +
1256 (unsigned) (bool) Res;
1258 DEBUG(dbgs() << "\t\trotation groups for " << VRI.V.getNode() <<
1259 " RL: " << VRI.RLAmt << ":" <<
1260 "\n\t\t\tisel using masking: " << NumAndInsts <<
1261 " using rotates: " << VRI.NumGroups << "\n");
1263 if (NumAndInsts >= VRI.NumGroups)
1266 DEBUG(dbgs() << "\t\t\t\tusing masking\n");
1268 if (InstCnt) *InstCnt += NumAndInsts;
1273 { VRI.V, getI32Imm(VRI.RLAmt, dl), getI32Imm(0, dl),
1274 getI32Imm(31, dl) };
1275 VRot = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32,
1281 SDValue ANDIVal, ANDISVal;
1283 ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo, dl, MVT::i32,
1284 VRot, getI32Imm(ANDIMask, dl)), 0);
1286 ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo, dl, MVT::i32,
1287 VRot, getI32Imm(ANDISMask, dl)), 0);
1291 TotalVal = ANDISVal;
1295 TotalVal = SDValue(CurDAG->getMachineNode(PPC::OR, dl, MVT::i32,
1296 ANDIVal, ANDISVal), 0);
1301 Res = SDValue(CurDAG->getMachineNode(PPC::OR, dl, MVT::i32,
1304 // Now, remove all groups with this underlying value and rotation
1306 eraseMatchingBitGroups([VRI](const BitGroup &BG) {
1307 return BG.V == VRI.V && BG.RLAmt == VRI.RLAmt;
1312 // Instruction selection for the 32-bit case.
1313 SDNode *Select32(SDNode *N, bool LateMask, unsigned *InstCnt) {
1317 if (InstCnt) *InstCnt = 0;
1319 // Take care of cases that should use andi/andis first.
1320 SelectAndParts32(dl, Res, InstCnt);
1322 // If we've not yet selected a 'starting' instruction, and we have no zeros
1323 // to fill in, select the (Value, RLAmt) with the highest priority (largest
1324 // number of groups), and start with this rotated value.
1325 if ((!HasZeros || LateMask) && !Res) {
1326 ValueRotInfo &VRI = ValueRotsVec[0];
1328 if (InstCnt) *InstCnt += 1;
1330 { VRI.V, getI32Imm(VRI.RLAmt, dl), getI32Imm(0, dl),
1331 getI32Imm(31, dl) };
1332 Res = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops),
1338 // Now, remove all groups with this underlying value and rotation factor.
1339 eraseMatchingBitGroups([VRI](const BitGroup &BG) {
1340 return BG.V == VRI.V && BG.RLAmt == VRI.RLAmt;
1344 if (InstCnt) *InstCnt += BitGroups.size();
1346 // Insert the other groups (one at a time).
1347 for (auto &BG : BitGroups) {
1350 { BG.V, getI32Imm(BG.RLAmt, dl),
1351 getI32Imm(Bits.size() - BG.EndIdx - 1, dl),
1352 getI32Imm(Bits.size() - BG.StartIdx - 1, dl) };
1353 Res = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0);
1356 { Res, BG.V, getI32Imm(BG.RLAmt, dl),
1357 getI32Imm(Bits.size() - BG.EndIdx - 1, dl),
1358 getI32Imm(Bits.size() - BG.StartIdx - 1, dl) };
1359 Res = SDValue(CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops), 0);
1364 unsigned Mask = (unsigned) getZerosMask();
1366 unsigned ANDIMask = (Mask & UINT16_MAX), ANDISMask = Mask >> 16;
1367 assert((ANDIMask != 0 || ANDISMask != 0) &&
1368 "No set bits in zeros mask?");
1370 if (InstCnt) *InstCnt += (unsigned) (ANDIMask != 0) +
1371 (unsigned) (ANDISMask != 0) +
1372 (unsigned) (ANDIMask != 0 && ANDISMask != 0);
1374 SDValue ANDIVal, ANDISVal;
1376 ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo, dl, MVT::i32,
1377 Res, getI32Imm(ANDIMask, dl)), 0);
1379 ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo, dl, MVT::i32,
1380 Res, getI32Imm(ANDISMask, dl)), 0);
1387 Res = SDValue(CurDAG->getMachineNode(PPC::OR, dl, MVT::i32,
1388 ANDIVal, ANDISVal), 0);
1391 return Res.getNode();
1394 unsigned SelectRotMask64Count(unsigned RLAmt, bool Repl32,
1395 unsigned MaskStart, unsigned MaskEnd,
1397 // In the notation used by the instructions, 'start' and 'end' are reversed
1398 // because bits are counted from high to low order.
1399 unsigned InstMaskStart = 64 - MaskEnd - 1,
1400 InstMaskEnd = 64 - MaskStart - 1;
1405 if ((!IsIns && (InstMaskEnd == 63 || InstMaskStart == 0)) ||
1406 InstMaskEnd == 63 - RLAmt)
1412 // For 64-bit values, not all combinations of rotates and masks are
1413 // available. Produce one if it is available.
1414 SDValue SelectRotMask64(SDValue V, SDLoc dl, unsigned RLAmt, bool Repl32,
1415 unsigned MaskStart, unsigned MaskEnd,
1416 unsigned *InstCnt = nullptr) {
1417 // In the notation used by the instructions, 'start' and 'end' are reversed
1418 // because bits are counted from high to low order.
1419 unsigned InstMaskStart = 64 - MaskEnd - 1,
1420 InstMaskEnd = 64 - MaskStart - 1;
1422 if (InstCnt) *InstCnt += 1;
1425 // This rotation amount assumes that the lower 32 bits of the quantity
1426 // are replicated in the high 32 bits by the rotation operator (which is
1427 // done by rlwinm and friends).
1428 assert(InstMaskStart >= 32 && "Mask cannot start out of range");
1429 assert(InstMaskEnd >= 32 && "Mask cannot end out of range");
1431 { V, getI32Imm(RLAmt, dl), getI32Imm(InstMaskStart - 32, dl),
1432 getI32Imm(InstMaskEnd - 32, dl) };
1433 return SDValue(CurDAG->getMachineNode(PPC::RLWINM8, dl, MVT::i64,
1437 if (InstMaskEnd == 63) {
1439 { V, getI32Imm(RLAmt, dl), getI32Imm(InstMaskStart, dl) };
1440 return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Ops), 0);
1443 if (InstMaskStart == 0) {
1445 { V, getI32Imm(RLAmt, dl), getI32Imm(InstMaskEnd, dl) };
1446 return SDValue(CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64, Ops), 0);
1449 if (InstMaskEnd == 63 - RLAmt) {
1451 { V, getI32Imm(RLAmt, dl), getI32Imm(InstMaskStart, dl) };
1452 return SDValue(CurDAG->getMachineNode(PPC::RLDIC, dl, MVT::i64, Ops), 0);
1455 // We cannot do this with a single instruction, so we'll use two. The
1456 // problem is that we're not free to choose both a rotation amount and mask
1457 // start and end independently. We can choose an arbitrary mask start and
1458 // end, but then the rotation amount is fixed. Rotation, however, can be
1459 // inverted, and so by applying an "inverse" rotation first, we can get the
1461 if (InstCnt) *InstCnt += 1;
1463 // The rotation mask for the second instruction must be MaskStart.
1464 unsigned RLAmt2 = MaskStart;
1465 // The first instruction must rotate V so that the overall rotation amount
1467 unsigned RLAmt1 = (64 + RLAmt - RLAmt2) % 64;
1469 V = SelectRotMask64(V, dl, RLAmt1, false, 0, 63);
1470 return SelectRotMask64(V, dl, RLAmt2, false, MaskStart, MaskEnd);
1473 // For 64-bit values, not all combinations of rotates and masks are
1474 // available. Produce a rotate-mask-and-insert if one is available.
1475 SDValue SelectRotMaskIns64(SDValue Base, SDValue V, SDLoc dl, unsigned RLAmt,
1476 bool Repl32, unsigned MaskStart,
1477 unsigned MaskEnd, unsigned *InstCnt = nullptr) {
1478 // In the notation used by the instructions, 'start' and 'end' are reversed
1479 // because bits are counted from high to low order.
1480 unsigned InstMaskStart = 64 - MaskEnd - 1,
1481 InstMaskEnd = 64 - MaskStart - 1;
1483 if (InstCnt) *InstCnt += 1;
1486 // This rotation amount assumes that the lower 32 bits of the quantity
1487 // are replicated in the high 32 bits by the rotation operator (which is
1488 // done by rlwinm and friends).
1489 assert(InstMaskStart >= 32 && "Mask cannot start out of range");
1490 assert(InstMaskEnd >= 32 && "Mask cannot end out of range");
1492 { Base, V, getI32Imm(RLAmt, dl), getI32Imm(InstMaskStart - 32, dl),
1493 getI32Imm(InstMaskEnd - 32, dl) };
1494 return SDValue(CurDAG->getMachineNode(PPC::RLWIMI8, dl, MVT::i64,
1498 if (InstMaskEnd == 63 - RLAmt) {
1500 { Base, V, getI32Imm(RLAmt, dl), getI32Imm(InstMaskStart, dl) };
1501 return SDValue(CurDAG->getMachineNode(PPC::RLDIMI, dl, MVT::i64, Ops), 0);
1504 // We cannot do this with a single instruction, so we'll use two. The
1505 // problem is that we're not free to choose both a rotation amount and mask
1506 // start and end independently. We can choose an arbitrary mask start and
1507 // end, but then the rotation amount is fixed. Rotation, however, can be
1508 // inverted, and so by applying an "inverse" rotation first, we can get the
1510 if (InstCnt) *InstCnt += 1;
1512 // The rotation mask for the second instruction must be MaskStart.
1513 unsigned RLAmt2 = MaskStart;
1514 // The first instruction must rotate V so that the overall rotation amount
1516 unsigned RLAmt1 = (64 + RLAmt - RLAmt2) % 64;
1518 V = SelectRotMask64(V, dl, RLAmt1, false, 0, 63);
1519 return SelectRotMaskIns64(Base, V, dl, RLAmt2, false, MaskStart, MaskEnd);
1522 void SelectAndParts64(SDLoc dl, SDValue &Res, unsigned *InstCnt) {
1523 if (BPermRewriterNoMasking)
1526 // The idea here is the same as in the 32-bit version, but with additional
1527 // complications from the fact that Repl32 might be true. Because we
1528 // aggressively convert bit groups to Repl32 form (which, for small
1529 // rotation factors, involves no other change), and then coalesce, it might
1530 // be the case that a single 64-bit masking operation could handle both
1531 // some Repl32 groups and some non-Repl32 groups. If converting to Repl32
1532 // form allowed coalescing, then we must use a 32-bit rotaton in order to
1533 // completely capture the new combined bit group.
1535 for (ValueRotInfo &VRI : ValueRotsVec) {
1538 // We need to add to the mask all bits from the associated bit groups.
1539 // If Repl32 is false, we need to add bits from bit groups that have
1540 // Repl32 true, but are trivially convertable to Repl32 false. Such a
1541 // group is trivially convertable if it overlaps only with the lower 32
1542 // bits, and the group has not been coalesced.
1543 auto MatchingBG = [VRI](const BitGroup &BG) {
1547 unsigned EffRLAmt = BG.RLAmt;
1548 if (!VRI.Repl32 && BG.Repl32) {
1549 if (BG.StartIdx < 32 && BG.EndIdx < 32 && BG.StartIdx <= BG.EndIdx &&
1550 !BG.Repl32Coalesced) {
1556 } else if (VRI.Repl32 != BG.Repl32) {
1560 if (VRI.RLAmt != EffRLAmt)
1566 for (auto &BG : BitGroups) {
1567 if (!MatchingBG(BG))
1570 if (BG.StartIdx <= BG.EndIdx) {
1571 for (unsigned i = BG.StartIdx; i <= BG.EndIdx; ++i)
1572 Mask |= (UINT64_C(1) << i);
1574 for (unsigned i = BG.StartIdx; i < Bits.size(); ++i)
1575 Mask |= (UINT64_C(1) << i);
1576 for (unsigned i = 0; i <= BG.EndIdx; ++i)
1577 Mask |= (UINT64_C(1) << i);
1581 // We can use the 32-bit andi/andis technique if the mask does not
1582 // require any higher-order bits. This can save an instruction compared
1583 // to always using the general 64-bit technique.
1584 bool Use32BitInsts = isUInt<32>(Mask);
1585 // Compute the masks for andi/andis that would be necessary.
1586 unsigned ANDIMask = (Mask & UINT16_MAX),
1587 ANDISMask = (Mask >> 16) & UINT16_MAX;
1589 bool NeedsRotate = VRI.RLAmt || (VRI.Repl32 && !isUInt<32>(Mask));
1591 unsigned NumAndInsts = (unsigned) NeedsRotate +
1592 (unsigned) (bool) Res;
1594 NumAndInsts += (unsigned) (ANDIMask != 0) + (unsigned) (ANDISMask != 0) +
1595 (unsigned) (ANDIMask != 0 && ANDISMask != 0);
1597 NumAndInsts += SelectInt64Count(Mask) + /* and */ 1;
1599 unsigned NumRLInsts = 0;
1600 bool FirstBG = true;
1601 for (auto &BG : BitGroups) {
1602 if (!MatchingBG(BG))
1605 SelectRotMask64Count(BG.RLAmt, BG.Repl32, BG.StartIdx, BG.EndIdx,
1610 DEBUG(dbgs() << "\t\trotation groups for " << VRI.V.getNode() <<
1611 " RL: " << VRI.RLAmt << (VRI.Repl32 ? " (32):" : ":") <<
1612 "\n\t\t\tisel using masking: " << NumAndInsts <<
1613 " using rotates: " << NumRLInsts << "\n");
1615 // When we'd use andi/andis, we bias toward using the rotates (andi only
1616 // has a record form, and is cracked on POWER cores). However, when using
1617 // general 64-bit constant formation, bias toward the constant form,
1618 // because that exposes more opportunities for CSE.
1619 if (NumAndInsts > NumRLInsts)
1621 if (Use32BitInsts && NumAndInsts == NumRLInsts)
1624 DEBUG(dbgs() << "\t\t\t\tusing masking\n");
1626 if (InstCnt) *InstCnt += NumAndInsts;
1629 // We actually need to generate a rotation if we have a non-zero rotation
1630 // factor or, in the Repl32 case, if we care about any of the
1631 // higher-order replicated bits. In the latter case, we generate a mask
1632 // backward so that it actually includes the entire 64 bits.
1633 if (VRI.RLAmt || (VRI.Repl32 && !isUInt<32>(Mask)))
1634 VRot = SelectRotMask64(VRI.V, dl, VRI.RLAmt, VRI.Repl32,
1635 VRI.Repl32 ? 31 : 0, VRI.Repl32 ? 30 : 63);
1640 if (Use32BitInsts) {
1641 assert((ANDIMask != 0 || ANDISMask != 0) &&
1642 "No set bits in mask when using 32-bit ands for 64-bit value");
1644 SDValue ANDIVal, ANDISVal;
1646 ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo8, dl, MVT::i64,
1647 VRot, getI32Imm(ANDIMask, dl)), 0);
1649 ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo8, dl, MVT::i64,
1650 VRot, getI32Imm(ANDISMask, dl)), 0);
1653 TotalVal = ANDISVal;
1657 TotalVal = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
1658 ANDIVal, ANDISVal), 0);
1660 TotalVal = SDValue(SelectInt64(CurDAG, dl, Mask), 0);
1662 SDValue(CurDAG->getMachineNode(PPC::AND8, dl, MVT::i64,
1663 VRot, TotalVal), 0);
1669 Res = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
1672 // Now, remove all groups with this underlying value and rotation
1674 eraseMatchingBitGroups(MatchingBG);
1678 // Instruction selection for the 64-bit case.
1679 SDNode *Select64(SDNode *N, bool LateMask, unsigned *InstCnt) {
1683 if (InstCnt) *InstCnt = 0;
1685 // Take care of cases that should use andi/andis first.
1686 SelectAndParts64(dl, Res, InstCnt);
1688 // If we've not yet selected a 'starting' instruction, and we have no zeros
1689 // to fill in, select the (Value, RLAmt) with the highest priority (largest
1690 // number of groups), and start with this rotated value.
1691 if ((!HasZeros || LateMask) && !Res) {
1692 // If we have both Repl32 groups and non-Repl32 groups, the non-Repl32
1693 // groups will come first, and so the VRI representing the largest number
1694 // of groups might not be first (it might be the first Repl32 groups).
1695 unsigned MaxGroupsIdx = 0;
1696 if (!ValueRotsVec[0].Repl32) {
1697 for (unsigned i = 0, ie = ValueRotsVec.size(); i < ie; ++i)
1698 if (ValueRotsVec[i].Repl32) {
1699 if (ValueRotsVec[i].NumGroups > ValueRotsVec[0].NumGroups)
1705 ValueRotInfo &VRI = ValueRotsVec[MaxGroupsIdx];
1706 bool NeedsRotate = false;
1709 } else if (VRI.Repl32) {
1710 for (auto &BG : BitGroups) {
1711 if (BG.V != VRI.V || BG.RLAmt != VRI.RLAmt ||
1712 BG.Repl32 != VRI.Repl32)
1715 // We don't need a rotate if the bit group is confined to the lower
1717 if (BG.StartIdx < 32 && BG.EndIdx < 32 && BG.StartIdx < BG.EndIdx)
1726 Res = SelectRotMask64(VRI.V, dl, VRI.RLAmt, VRI.Repl32,
1727 VRI.Repl32 ? 31 : 0, VRI.Repl32 ? 30 : 63,
1732 // Now, remove all groups with this underlying value and rotation factor.
1734 eraseMatchingBitGroups([VRI](const BitGroup &BG) {
1735 return BG.V == VRI.V && BG.RLAmt == VRI.RLAmt &&
1736 BG.Repl32 == VRI.Repl32;
1740 // Because 64-bit rotates are more flexible than inserts, we might have a
1741 // preference regarding which one we do first (to save one instruction).
1743 for (auto I = BitGroups.begin(), IE = BitGroups.end(); I != IE; ++I) {
1744 if (SelectRotMask64Count(I->RLAmt, I->Repl32, I->StartIdx, I->EndIdx,
1746 SelectRotMask64Count(I->RLAmt, I->Repl32, I->StartIdx, I->EndIdx,
1748 if (I != BitGroups.begin()) {
1751 BitGroups.insert(BitGroups.begin(), BG);
1758 // Insert the other groups (one at a time).
1759 for (auto &BG : BitGroups) {
1761 Res = SelectRotMask64(BG.V, dl, BG.RLAmt, BG.Repl32, BG.StartIdx,
1762 BG.EndIdx, InstCnt);
1764 Res = SelectRotMaskIns64(Res, BG.V, dl, BG.RLAmt, BG.Repl32,
1765 BG.StartIdx, BG.EndIdx, InstCnt);
1769 uint64_t Mask = getZerosMask();
1771 // We can use the 32-bit andi/andis technique if the mask does not
1772 // require any higher-order bits. This can save an instruction compared
1773 // to always using the general 64-bit technique.
1774 bool Use32BitInsts = isUInt<32>(Mask);
1775 // Compute the masks for andi/andis that would be necessary.
1776 unsigned ANDIMask = (Mask & UINT16_MAX),
1777 ANDISMask = (Mask >> 16) & UINT16_MAX;
1779 if (Use32BitInsts) {
1780 assert((ANDIMask != 0 || ANDISMask != 0) &&
1781 "No set bits in mask when using 32-bit ands for 64-bit value");
1783 if (InstCnt) *InstCnt += (unsigned) (ANDIMask != 0) +
1784 (unsigned) (ANDISMask != 0) +
1785 (unsigned) (ANDIMask != 0 && ANDISMask != 0);
1787 SDValue ANDIVal, ANDISVal;
1789 ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo8, dl, MVT::i64,
1790 Res, getI32Imm(ANDIMask, dl)), 0);
1792 ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo8, dl, MVT::i64,
1793 Res, getI32Imm(ANDISMask, dl)), 0);
1800 Res = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
1801 ANDIVal, ANDISVal), 0);
1803 if (InstCnt) *InstCnt += SelectInt64Count(Mask) + /* and */ 1;
1805 SDValue MaskVal = SDValue(SelectInt64(CurDAG, dl, Mask), 0);
1807 SDValue(CurDAG->getMachineNode(PPC::AND8, dl, MVT::i64,
1812 return Res.getNode();
1815 SDNode *Select(SDNode *N, bool LateMask, unsigned *InstCnt = nullptr) {
1816 // Fill in BitGroups.
1817 collectBitGroups(LateMask);
1818 if (BitGroups.empty())
1821 // For 64-bit values, figure out when we can use 32-bit instructions.
1822 if (Bits.size() == 64)
1823 assignRepl32BitGroups();
1825 // Fill in ValueRotsVec.
1826 collectValueRotInfo();
1828 if (Bits.size() == 32) {
1829 return Select32(N, LateMask, InstCnt);
1831 assert(Bits.size() == 64 && "Not 64 bits here?");
1832 return Select64(N, LateMask, InstCnt);
1838 void eraseMatchingBitGroups(function_ref<bool(const BitGroup &)> F) {
1839 BitGroups.erase(std::remove_if(BitGroups.begin(), BitGroups.end(), F),
1843 SmallVector<ValueBit, 64> Bits;
1846 SmallVector<unsigned, 64> RLAmt;
1848 SmallVector<BitGroup, 16> BitGroups;
1850 DenseMap<std::pair<SDValue, unsigned>, ValueRotInfo> ValueRots;
1851 SmallVector<ValueRotInfo, 16> ValueRotsVec;
1853 SelectionDAG *CurDAG;
1856 BitPermutationSelector(SelectionDAG *DAG)
1859 // Here we try to match complex bit permutations into a set of
1860 // rotate-and-shift/shift/and/or instructions, using a set of heuristics
1861 // known to produce optimial code for common cases (like i32 byte swapping).
1862 SDNode *Select(SDNode *N) {
1863 Bits.resize(N->getValueType(0).getSizeInBits());
1864 if (!getValueBits(SDValue(N, 0), Bits))
1867 DEBUG(dbgs() << "Considering bit-permutation-based instruction"
1868 " selection for: ");
1869 DEBUG(N->dump(CurDAG));
1871 // Fill it RLAmt and set HasZeros.
1872 computeRotationAmounts();
1875 return Select(N, false);
1877 // We currently have two techniques for handling results with zeros: early
1878 // masking (the default) and late masking. Late masking is sometimes more
1879 // efficient, but because the structure of the bit groups is different, it
1880 // is hard to tell without generating both and comparing the results. With
1881 // late masking, we ignore zeros in the resulting value when inserting each
1882 // set of bit groups, and then mask in the zeros at the end. With early
1883 // masking, we only insert the non-zero parts of the result at every step.
1885 unsigned InstCnt, InstCntLateMask;
1886 DEBUG(dbgs() << "\tEarly masking:\n");
1887 SDNode *RN = Select(N, false, &InstCnt);
1888 DEBUG(dbgs() << "\t\tisel would use " << InstCnt << " instructions\n");
1890 DEBUG(dbgs() << "\tLate masking:\n");
1891 SDNode *RNLM = Select(N, true, &InstCntLateMask);
1892 DEBUG(dbgs() << "\t\tisel would use " << InstCntLateMask <<
1895 if (InstCnt <= InstCntLateMask) {
1896 DEBUG(dbgs() << "\tUsing early-masking for isel\n");
1900 DEBUG(dbgs() << "\tUsing late-masking for isel\n");
1904 } // anonymous namespace
1906 SDNode *PPCDAGToDAGISel::SelectBitPermutation(SDNode *N) {
1907 if (N->getValueType(0) != MVT::i32 &&
1908 N->getValueType(0) != MVT::i64)
1911 if (!UseBitPermRewriter)
1914 switch (N->getOpcode()) {
1921 BitPermutationSelector BPS(CurDAG);
1922 return BPS.Select(N);
1929 /// SelectCC - Select a comparison of the specified values with the specified
1930 /// condition code, returning the CR# of the expression.
1931 SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS,
1932 ISD::CondCode CC, SDLoc dl) {
1933 // Always select the LHS.
1936 if (LHS.getValueType() == MVT::i32) {
1938 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1939 if (isInt32Immediate(RHS, Imm)) {
1940 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
1941 if (isUInt<16>(Imm))
1942 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
1943 getI32Imm(Imm & 0xFFFF, dl)),
1945 // If this is a 16-bit signed immediate, fold it.
1946 if (isInt<16>((int)Imm))
1947 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
1948 getI32Imm(Imm & 0xFFFF, dl)),
1951 // For non-equality comparisons, the default code would materialize the
1952 // constant, then compare against it, like this:
1954 // ori r2, r2, 22136
1956 // Since we are just comparing for equality, we can emit this instead:
1957 // xoris r0,r3,0x1234
1958 // cmplwi cr0,r0,0x5678
1960 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS, dl, MVT::i32, LHS,
1961 getI32Imm(Imm >> 16, dl)), 0);
1962 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, Xor,
1963 getI32Imm(Imm & 0xFFFF, dl)), 0);
1966 } else if (ISD::isUnsignedIntSetCC(CC)) {
1967 if (isInt32Immediate(RHS, Imm) && isUInt<16>(Imm))
1968 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
1969 getI32Imm(Imm & 0xFFFF, dl)), 0);
1973 if (isIntS16Immediate(RHS, SImm))
1974 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
1975 getI32Imm((int)SImm & 0xFFFF,
1980 } else if (LHS.getValueType() == MVT::i64) {
1982 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1983 if (isInt64Immediate(RHS.getNode(), Imm)) {
1984 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
1985 if (isUInt<16>(Imm))
1986 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
1987 getI32Imm(Imm & 0xFFFF, dl)),
1989 // If this is a 16-bit signed immediate, fold it.
1991 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
1992 getI32Imm(Imm & 0xFFFF, dl)),
1995 // For non-equality comparisons, the default code would materialize the
1996 // constant, then compare against it, like this:
1998 // ori r2, r2, 22136
2000 // Since we are just comparing for equality, we can emit this instead:
2001 // xoris r0,r3,0x1234
2002 // cmpldi cr0,r0,0x5678
2004 if (isUInt<32>(Imm)) {
2005 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS8, dl, MVT::i64, LHS,
2006 getI64Imm(Imm >> 16, dl)), 0);
2007 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, Xor,
2008 getI64Imm(Imm & 0xFFFF, dl)),
2013 } else if (ISD::isUnsignedIntSetCC(CC)) {
2014 if (isInt64Immediate(RHS.getNode(), Imm) && isUInt<16>(Imm))
2015 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
2016 getI64Imm(Imm & 0xFFFF, dl)), 0);
2020 if (isIntS16Immediate(RHS, SImm))
2021 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
2022 getI64Imm(SImm & 0xFFFF, dl)),
2026 } else if (LHS.getValueType() == MVT::f32) {
2029 assert(LHS.getValueType() == MVT::f64 && "Unknown vt!");
2030 Opc = PPCSubTarget->hasVSX() ? PPC::XSCMPUDP : PPC::FCMPUD;
2032 return SDValue(CurDAG->getMachineNode(Opc, dl, MVT::i32, LHS, RHS), 0);
2035 static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {
2041 llvm_unreachable("Should be lowered by legalize!");
2042 default: llvm_unreachable("Unknown condition!");
2044 case ISD::SETEQ: return PPC::PRED_EQ;
2046 case ISD::SETNE: return PPC::PRED_NE;
2048 case ISD::SETLT: return PPC::PRED_LT;
2050 case ISD::SETLE: return PPC::PRED_LE;
2052 case ISD::SETGT: return PPC::PRED_GT;
2054 case ISD::SETGE: return PPC::PRED_GE;
2055 case ISD::SETO: return PPC::PRED_NU;
2056 case ISD::SETUO: return PPC::PRED_UN;
2057 // These two are invalid for floating point. Assume we have int.
2058 case ISD::SETULT: return PPC::PRED_LT;
2059 case ISD::SETUGT: return PPC::PRED_GT;
2063 /// getCRIdxForSetCC - Return the index of the condition register field
2064 /// associated with the SetCC condition, and whether or not the field is
2065 /// treated as inverted. That is, lt = 0; ge = 0 inverted.
2066 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert) {
2069 default: llvm_unreachable("Unknown condition!");
2071 case ISD::SETLT: return 0; // Bit #0 = SETOLT
2073 case ISD::SETGT: return 1; // Bit #1 = SETOGT
2075 case ISD::SETEQ: return 2; // Bit #2 = SETOEQ
2076 case ISD::SETUO: return 3; // Bit #3 = SETUO
2078 case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE
2080 case ISD::SETLE: Invert = true; return 1; // !Bit #1 = SETULE
2082 case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE
2083 case ISD::SETO: Invert = true; return 3; // !Bit #3 = SETO
2088 llvm_unreachable("Invalid branch code: should be expanded by legalize");
2089 // These are invalid for floating point. Assume integer.
2090 case ISD::SETULT: return 0;
2091 case ISD::SETUGT: return 1;
2095 // getVCmpInst: return the vector compare instruction for the specified
2096 // vector type and condition code. Since this is for altivec specific code,
2097 // only support the altivec types (v16i8, v8i16, v4i32, v2i64, and v4f32).
2098 static unsigned int getVCmpInst(MVT VecVT, ISD::CondCode CC,
2099 bool HasVSX, bool &Swap, bool &Negate) {
2103 if (VecVT.isFloatingPoint()) {
2104 /* Handle some cases by swapping input operands. */
2106 case ISD::SETLE: CC = ISD::SETGE; Swap = true; break;
2107 case ISD::SETLT: CC = ISD::SETGT; Swap = true; break;
2108 case ISD::SETOLE: CC = ISD::SETOGE; Swap = true; break;
2109 case ISD::SETOLT: CC = ISD::SETOGT; Swap = true; break;
2110 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break;
2111 case ISD::SETUGT: CC = ISD::SETULT; Swap = true; break;
2114 /* Handle some cases by negating the result. */
2116 case ISD::SETNE: CC = ISD::SETEQ; Negate = true; break;
2117 case ISD::SETUNE: CC = ISD::SETOEQ; Negate = true; break;
2118 case ISD::SETULE: CC = ISD::SETOGT; Negate = true; break;
2119 case ISD::SETULT: CC = ISD::SETOGE; Negate = true; break;
2122 /* We have instructions implementing the remaining cases. */
2126 if (VecVT == MVT::v4f32)
2127 return HasVSX ? PPC::XVCMPEQSP : PPC::VCMPEQFP;
2128 else if (VecVT == MVT::v2f64)
2129 return PPC::XVCMPEQDP;
2133 if (VecVT == MVT::v4f32)
2134 return HasVSX ? PPC::XVCMPGTSP : PPC::VCMPGTFP;
2135 else if (VecVT == MVT::v2f64)
2136 return PPC::XVCMPGTDP;
2140 if (VecVT == MVT::v4f32)
2141 return HasVSX ? PPC::XVCMPGESP : PPC::VCMPGEFP;
2142 else if (VecVT == MVT::v2f64)
2143 return PPC::XVCMPGEDP;
2148 llvm_unreachable("Invalid floating-point vector compare condition");
2150 /* Handle some cases by swapping input operands. */
2152 case ISD::SETGE: CC = ISD::SETLE; Swap = true; break;
2153 case ISD::SETLT: CC = ISD::SETGT; Swap = true; break;
2154 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break;
2155 case ISD::SETULT: CC = ISD::SETUGT; Swap = true; break;
2158 /* Handle some cases by negating the result. */
2160 case ISD::SETNE: CC = ISD::SETEQ; Negate = true; break;
2161 case ISD::SETUNE: CC = ISD::SETUEQ; Negate = true; break;
2162 case ISD::SETLE: CC = ISD::SETGT; Negate = true; break;
2163 case ISD::SETULE: CC = ISD::SETUGT; Negate = true; break;
2166 /* We have instructions implementing the remaining cases. */
2170 if (VecVT == MVT::v16i8)
2171 return PPC::VCMPEQUB;
2172 else if (VecVT == MVT::v8i16)
2173 return PPC::VCMPEQUH;
2174 else if (VecVT == MVT::v4i32)
2175 return PPC::VCMPEQUW;
2176 else if (VecVT == MVT::v2i64)
2177 return PPC::VCMPEQUD;
2180 if (VecVT == MVT::v16i8)
2181 return PPC::VCMPGTSB;
2182 else if (VecVT == MVT::v8i16)
2183 return PPC::VCMPGTSH;
2184 else if (VecVT == MVT::v4i32)
2185 return PPC::VCMPGTSW;
2186 else if (VecVT == MVT::v2i64)
2187 return PPC::VCMPGTSD;
2190 if (VecVT == MVT::v16i8)
2191 return PPC::VCMPGTUB;
2192 else if (VecVT == MVT::v8i16)
2193 return PPC::VCMPGTUH;
2194 else if (VecVT == MVT::v4i32)
2195 return PPC::VCMPGTUW;
2196 else if (VecVT == MVT::v2i64)
2197 return PPC::VCMPGTUD;
2202 llvm_unreachable("Invalid integer vector compare condition");
2206 SDNode *PPCDAGToDAGISel::SelectSETCC(SDNode *N) {
2209 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
2211 CurDAG->getTargetLoweringInfo().getPointerTy(CurDAG->getDataLayout());
2212 bool isPPC64 = (PtrVT == MVT::i64);
2214 if (!PPCSubTarget->useCRBits() &&
2215 isInt32Immediate(N->getOperand(1), Imm)) {
2216 // We can codegen setcc op, imm very efficiently compared to a brcond.
2217 // Check for those cases here.
2220 SDValue Op = N->getOperand(0);
2224 Op = SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Op), 0);
2225 SDValue Ops[] = { Op, getI32Imm(27, dl), getI32Imm(5, dl),
2226 getI32Imm(31, dl) };
2227 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2232 SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
2233 Op, getI32Imm(~0U, dl)), 0);
2234 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
2238 SDValue Ops[] = { Op, getI32Imm(1, dl), getI32Imm(31, dl),
2239 getI32Imm(31, dl) };
2240 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2244 SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Op), 0);
2245 T = SDValue(CurDAG->getMachineNode(PPC::ANDC, dl, MVT::i32, T, Op), 0);
2246 SDValue Ops[] = { T, getI32Imm(1, dl), getI32Imm(31, dl),
2247 getI32Imm(31, dl) };
2248 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2251 } else if (Imm == ~0U) { // setcc op, -1
2252 SDValue Op = N->getOperand(0);
2257 Op = SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
2258 Op, getI32Imm(1, dl)), 0);
2259 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
2260 SDValue(CurDAG->getMachineNode(PPC::LI, dl,
2263 0), Op.getValue(1));
2266 Op = SDValue(CurDAG->getMachineNode(PPC::NOR, dl, MVT::i32, Op, Op), 0);
2267 SDNode *AD = CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
2268 Op, getI32Imm(~0U, dl));
2269 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0),
2270 Op, SDValue(AD, 1));
2273 SDValue AD = SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Op,
2274 getI32Imm(1, dl)), 0);
2275 SDValue AN = SDValue(CurDAG->getMachineNode(PPC::AND, dl, MVT::i32, AD,
2277 SDValue Ops[] = { AN, getI32Imm(1, dl), getI32Imm(31, dl),
2278 getI32Imm(31, dl) };
2279 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2282 SDValue Ops[] = { Op, getI32Imm(1, dl), getI32Imm(31, dl),
2283 getI32Imm(31, dl) };
2284 Op = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0);
2285 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op,
2292 SDValue LHS = N->getOperand(0);
2293 SDValue RHS = N->getOperand(1);
2295 // Altivec Vector compare instructions do not set any CR register by default and
2296 // vector compare operations return the same type as the operands.
2297 if (LHS.getValueType().isVector()) {
2298 if (PPCSubTarget->hasQPX())
2301 EVT VecVT = LHS.getValueType();
2303 unsigned int VCmpInst = getVCmpInst(VecVT.getSimpleVT(), CC,
2304 PPCSubTarget->hasVSX(), Swap, Negate);
2306 std::swap(LHS, RHS);
2308 EVT ResVT = VecVT.changeVectorElementTypeToInteger();
2310 SDValue VCmp(CurDAG->getMachineNode(VCmpInst, dl, ResVT, LHS, RHS), 0);
2311 return CurDAG->SelectNodeTo(N, PPCSubTarget->hasVSX() ? PPC::XXLNOR :
2316 return CurDAG->SelectNodeTo(N, VCmpInst, ResVT, LHS, RHS);
2319 if (PPCSubTarget->useCRBits())
2323 unsigned Idx = getCRIdxForSetCC(CC, Inv);
2324 SDValue CCReg = SelectCC(LHS, RHS, CC, dl);
2327 // Force the ccreg into CR7.
2328 SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
2330 SDValue InFlag(nullptr, 0); // Null incoming flag value.
2331 CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, CR7Reg, CCReg,
2332 InFlag).getValue(1);
2334 IntCR = SDValue(CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg,
2337 SDValue Ops[] = { IntCR, getI32Imm((32 - (3 - Idx)) & 31, dl),
2338 getI32Imm(31, dl), getI32Imm(31, dl) };
2340 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2342 // Get the specified bit.
2344 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0);
2345 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1, dl));
2348 SDNode *PPCDAGToDAGISel::transferMemOperands(SDNode *N, SDNode *Result) {
2349 // Transfer memoperands.
2350 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2351 MemOp[0] = cast<MemSDNode>(N)->getMemOperand();
2352 cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
2357 // Select - Convert the specified operand from a target-independent to a
2358 // target-specific node if it hasn't already been changed.
2359 SDNode *PPCDAGToDAGISel::Select(SDNode *N) {
2361 if (N->isMachineOpcode()) {
2363 return nullptr; // Already selected.
2366 // In case any misguided DAG-level optimizations form an ADD with a
2367 // TargetConstant operand, crash here instead of miscompiling (by selecting
2368 // an r+r add instead of some kind of r+i add).
2369 if (N->getOpcode() == ISD::ADD &&
2370 N->getOperand(1).getOpcode() == ISD::TargetConstant)
2371 llvm_unreachable("Invalid ADD with TargetConstant operand");
2373 // Try matching complex bit permutations before doing anything else.
2374 if (SDNode *NN = SelectBitPermutation(N))
2377 switch (N->getOpcode()) {
2380 case ISD::Constant: {
2381 if (N->getValueType(0) == MVT::i64)
2382 return SelectInt64(CurDAG, N);
2387 SDNode *SN = SelectSETCC(N);
2392 case PPCISD::GlobalBaseReg:
2393 return getGlobalBaseReg();
2395 case ISD::FrameIndex:
2396 return getFrameIndex(N, N);
2398 case PPCISD::MFOCRF: {
2399 SDValue InFlag = N->getOperand(1);
2400 return CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32,
2401 N->getOperand(0), InFlag);
2404 case PPCISD::READ_TIME_BASE: {
2405 return CurDAG->getMachineNode(PPC::ReadTB, dl, MVT::i32, MVT::i32,
2406 MVT::Other, N->getOperand(0));
2409 case PPCISD::SRA_ADDZE: {
2410 SDValue N0 = N->getOperand(0);
2412 CurDAG->getTargetConstant(*cast<ConstantSDNode>(N->getOperand(1))->
2413 getConstantIntValue(), dl,
2414 N->getValueType(0));
2415 if (N->getValueType(0) == MVT::i64) {
2417 CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, MVT::Glue,
2419 return CurDAG->SelectNodeTo(N, PPC::ADDZE8, MVT::i64,
2420 SDValue(Op, 0), SDValue(Op, 1));
2422 assert(N->getValueType(0) == MVT::i32 &&
2423 "Expecting i64 or i32 in PPCISD::SRA_ADDZE");
2425 CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Glue,
2427 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
2428 SDValue(Op, 0), SDValue(Op, 1));
2433 // Handle preincrement loads.
2434 LoadSDNode *LD = cast<LoadSDNode>(N);
2435 EVT LoadedVT = LD->getMemoryVT();
2437 // Normal loads are handled by code generated from the .td file.
2438 if (LD->getAddressingMode() != ISD::PRE_INC)
2441 SDValue Offset = LD->getOffset();
2442 if (Offset.getOpcode() == ISD::TargetConstant ||
2443 Offset.getOpcode() == ISD::TargetGlobalAddress) {
2446 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
2447 if (LD->getValueType(0) != MVT::i64) {
2448 // Handle PPC32 integer and normal FP loads.
2449 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
2450 switch (LoadedVT.getSimpleVT().SimpleTy) {
2451 default: llvm_unreachable("Invalid PPC load type!");
2452 case MVT::f64: Opcode = PPC::LFDU; break;
2453 case MVT::f32: Opcode = PPC::LFSU; break;
2454 case MVT::i32: Opcode = PPC::LWZU; break;
2455 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
2457 case MVT::i8: Opcode = PPC::LBZU; break;
2460 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
2461 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
2462 switch (LoadedVT.getSimpleVT().SimpleTy) {
2463 default: llvm_unreachable("Invalid PPC load type!");
2464 case MVT::i64: Opcode = PPC::LDU; break;
2465 case MVT::i32: Opcode = PPC::LWZU8; break;
2466 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
2468 case MVT::i8: Opcode = PPC::LBZU8; break;
2472 SDValue Chain = LD->getChain();
2473 SDValue Base = LD->getBasePtr();
2474 SDValue Ops[] = { Offset, Base, Chain };
2475 return transferMemOperands(
2476 N, CurDAG->getMachineNode(
2477 Opcode, dl, LD->getValueType(0),
2478 PPCLowering->getPointerTy(CurDAG->getDataLayout()), MVT::Other,
2482 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
2483 if (LD->getValueType(0) != MVT::i64) {
2484 // Handle PPC32 integer and normal FP loads.
2485 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
2486 switch (LoadedVT.getSimpleVT().SimpleTy) {
2487 default: llvm_unreachable("Invalid PPC load type!");
2488 case MVT::v4f64: Opcode = PPC::QVLFDUX; break; // QPX
2489 case MVT::v4f32: Opcode = PPC::QVLFSUX; break; // QPX
2490 case MVT::f64: Opcode = PPC::LFDUX; break;
2491 case MVT::f32: Opcode = PPC::LFSUX; break;
2492 case MVT::i32: Opcode = PPC::LWZUX; break;
2493 case MVT::i16: Opcode = isSExt ? PPC::LHAUX : PPC::LHZUX; break;
2495 case MVT::i8: Opcode = PPC::LBZUX; break;
2498 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
2499 assert((!isSExt || LoadedVT == MVT::i16 || LoadedVT == MVT::i32) &&
2500 "Invalid sext update load");
2501 switch (LoadedVT.getSimpleVT().SimpleTy) {
2502 default: llvm_unreachable("Invalid PPC load type!");
2503 case MVT::i64: Opcode = PPC::LDUX; break;
2504 case MVT::i32: Opcode = isSExt ? PPC::LWAUX : PPC::LWZUX8; break;
2505 case MVT::i16: Opcode = isSExt ? PPC::LHAUX8 : PPC::LHZUX8; break;
2507 case MVT::i8: Opcode = PPC::LBZUX8; break;
2511 SDValue Chain = LD->getChain();
2512 SDValue Base = LD->getBasePtr();
2513 SDValue Ops[] = { Base, Offset, Chain };
2514 return transferMemOperands(
2515 N, CurDAG->getMachineNode(
2516 Opcode, dl, LD->getValueType(0),
2517 PPCLowering->getPointerTy(CurDAG->getDataLayout()), MVT::Other,
2523 unsigned Imm, Imm2, SH, MB, ME;
2526 // If this is an and of a value rotated between 0 and 31 bits and then and'd
2527 // with a mask, emit rlwinm
2528 if (isInt32Immediate(N->getOperand(1), Imm) &&
2529 isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH, MB, ME)) {
2530 SDValue Val = N->getOperand(0).getOperand(0);
2531 SDValue Ops[] = { Val, getI32Imm(SH, dl), getI32Imm(MB, dl),
2532 getI32Imm(ME, dl) };
2533 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2535 // If this is just a masked value where the input is not handled above, and
2536 // is not a rotate-left (handled by a pattern in the .td file), emit rlwinm
2537 if (isInt32Immediate(N->getOperand(1), Imm) &&
2538 isRunOfOnes(Imm, MB, ME) &&
2539 N->getOperand(0).getOpcode() != ISD::ROTL) {
2540 SDValue Val = N->getOperand(0);
2541 SDValue Ops[] = { Val, getI32Imm(0, dl), getI32Imm(MB, dl),
2542 getI32Imm(ME, dl) };
2543 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2545 // If this is a 64-bit zero-extension mask, emit rldicl.
2546 if (isInt64Immediate(N->getOperand(1).getNode(), Imm64) &&
2548 SDValue Val = N->getOperand(0);
2549 MB = 64 - countTrailingOnes(Imm64);
2552 // If the operand is a logical right shift, we can fold it into this
2553 // instruction: rldicl(rldicl(x, 64-n, n), 0, mb) -> rldicl(x, 64-n, mb)
2554 // for n <= mb. The right shift is really a left rotate followed by a
2555 // mask, and this mask is a more-restrictive sub-mask of the mask implied
2557 if (Val.getOpcode() == ISD::SRL &&
2558 isInt32Immediate(Val.getOperand(1).getNode(), Imm) && Imm <= MB) {
2559 assert(Imm < 64 && "Illegal shift amount");
2560 Val = Val.getOperand(0);
2564 SDValue Ops[] = { Val, getI32Imm(SH, dl), getI32Imm(MB, dl) };
2565 return CurDAG->SelectNodeTo(N, PPC::RLDICL, MVT::i64, Ops);
2567 // AND X, 0 -> 0, not "rlwinm 32".
2568 if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) {
2569 ReplaceUses(SDValue(N, 0), N->getOperand(1));
2572 // ISD::OR doesn't get all the bitfield insertion fun.
2573 // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert
2574 if (isInt32Immediate(N->getOperand(1), Imm) &&
2575 N->getOperand(0).getOpcode() == ISD::OR &&
2576 isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) {
2579 if (isRunOfOnes(Imm, MB, ME)) {
2580 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2581 N->getOperand(0).getOperand(1),
2582 getI32Imm(0, dl), getI32Imm(MB, dl),
2583 getI32Imm(ME, dl) };
2584 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops);
2588 // Other cases are autogenerated.
2592 if (N->getValueType(0) == MVT::i32)
2593 if (SDNode *I = SelectBitfieldInsert(N))
2597 if (N->getOperand(0)->getOpcode() == ISD::FrameIndex &&
2598 isIntS16Immediate(N->getOperand(1), Imm)) {
2599 APInt LHSKnownZero, LHSKnownOne;
2600 CurDAG->computeKnownBits(N->getOperand(0), LHSKnownZero, LHSKnownOne);
2602 // If this is equivalent to an add, then we can fold it with the
2603 // FrameIndex calculation.
2604 if ((LHSKnownZero.getZExtValue()|~(uint64_t)Imm) == ~0ULL)
2605 return getFrameIndex(N, N->getOperand(0).getNode(), (int)Imm);
2608 // Other cases are autogenerated.
2613 if (N->getOperand(0)->getOpcode() == ISD::FrameIndex &&
2614 isIntS16Immediate(N->getOperand(1), Imm))
2615 return getFrameIndex(N, N->getOperand(0).getNode(), (int)Imm);
2620 unsigned Imm, SH, MB, ME;
2621 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
2622 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
2623 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2624 getI32Imm(SH, dl), getI32Imm(MB, dl),
2625 getI32Imm(ME, dl) };
2626 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2629 // Other cases are autogenerated.
2633 unsigned Imm, SH, MB, ME;
2634 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
2635 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
2636 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2637 getI32Imm(SH, dl), getI32Imm(MB, dl),
2638 getI32Imm(ME, dl) };
2639 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2642 // Other cases are autogenerated.
2645 // FIXME: Remove this once the ANDI glue bug is fixed:
2646 case PPCISD::ANDIo_1_EQ_BIT:
2647 case PPCISD::ANDIo_1_GT_BIT: {
2651 EVT InVT = N->getOperand(0).getValueType();
2652 assert((InVT == MVT::i64 || InVT == MVT::i32) &&
2653 "Invalid input type for ANDIo_1_EQ_BIT");
2655 unsigned Opcode = (InVT == MVT::i64) ? PPC::ANDIo8 : PPC::ANDIo;
2656 SDValue AndI(CurDAG->getMachineNode(Opcode, dl, InVT, MVT::Glue,
2658 CurDAG->getTargetConstant(1, dl, InVT)),
2660 SDValue CR0Reg = CurDAG->getRegister(PPC::CR0, MVT::i32);
2662 CurDAG->getTargetConstant(N->getOpcode() == PPCISD::ANDIo_1_EQ_BIT ?
2663 PPC::sub_eq : PPC::sub_gt, dl, MVT::i32);
2665 return CurDAG->SelectNodeTo(N, TargetOpcode::EXTRACT_SUBREG, MVT::i1,
2667 SDValue(AndI.getNode(), 1) /* glue */);
2669 case ISD::SELECT_CC: {
2670 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
2672 CurDAG->getTargetLoweringInfo().getPointerTy(CurDAG->getDataLayout());
2673 bool isPPC64 = (PtrVT == MVT::i64);
2675 // If this is a select of i1 operands, we'll pattern match it.
2676 if (PPCSubTarget->useCRBits() &&
2677 N->getOperand(0).getValueType() == MVT::i1)
2680 // Handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
2682 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2683 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
2684 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
2685 if (N1C->isNullValue() && N3C->isNullValue() &&
2686 N2C->getZExtValue() == 1ULL && CC == ISD::SETNE &&
2687 // FIXME: Implement this optzn for PPC64.
2688 N->getValueType(0) == MVT::i32) {
2690 CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
2691 N->getOperand(0), getI32Imm(~0U, dl));
2692 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
2693 SDValue(Tmp, 0), N->getOperand(0),
2697 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl);
2699 if (N->getValueType(0) == MVT::i1) {
2700 // An i1 select is: (c & t) | (!c & f).
2702 unsigned Idx = getCRIdxForSetCC(CC, Inv);
2706 default: llvm_unreachable("Invalid CC index");
2707 case 0: SRI = PPC::sub_lt; break;
2708 case 1: SRI = PPC::sub_gt; break;
2709 case 2: SRI = PPC::sub_eq; break;
2710 case 3: SRI = PPC::sub_un; break;
2713 SDValue CCBit = CurDAG->getTargetExtractSubreg(SRI, dl, MVT::i1, CCReg);
2715 SDValue NotCCBit(CurDAG->getMachineNode(PPC::CRNOR, dl, MVT::i1,
2717 SDValue C = Inv ? NotCCBit : CCBit,
2718 NotC = Inv ? CCBit : NotCCBit;
2720 SDValue CAndT(CurDAG->getMachineNode(PPC::CRAND, dl, MVT::i1,
2721 C, N->getOperand(2)), 0);
2722 SDValue NotCAndF(CurDAG->getMachineNode(PPC::CRAND, dl, MVT::i1,
2723 NotC, N->getOperand(3)), 0);
2725 return CurDAG->SelectNodeTo(N, PPC::CROR, MVT::i1, CAndT, NotCAndF);
2728 unsigned BROpc = getPredicateForSetCC(CC);
2730 unsigned SelectCCOp;
2731 if (N->getValueType(0) == MVT::i32)
2732 SelectCCOp = PPC::SELECT_CC_I4;
2733 else if (N->getValueType(0) == MVT::i64)
2734 SelectCCOp = PPC::SELECT_CC_I8;
2735 else if (N->getValueType(0) == MVT::f32)
2736 if (PPCSubTarget->hasP8Vector())
2737 SelectCCOp = PPC::SELECT_CC_VSSRC;
2739 SelectCCOp = PPC::SELECT_CC_F4;
2740 else if (N->getValueType(0) == MVT::f64)
2741 if (PPCSubTarget->hasVSX())
2742 SelectCCOp = PPC::SELECT_CC_VSFRC;
2744 SelectCCOp = PPC::SELECT_CC_F8;
2745 else if (PPCSubTarget->hasQPX() && N->getValueType(0) == MVT::v4f64)
2746 SelectCCOp = PPC::SELECT_CC_QFRC;
2747 else if (PPCSubTarget->hasQPX() && N->getValueType(0) == MVT::v4f32)
2748 SelectCCOp = PPC::SELECT_CC_QSRC;
2749 else if (PPCSubTarget->hasQPX() && N->getValueType(0) == MVT::v4i1)
2750 SelectCCOp = PPC::SELECT_CC_QBRC;
2751 else if (N->getValueType(0) == MVT::v2f64 ||
2752 N->getValueType(0) == MVT::v2i64)
2753 SelectCCOp = PPC::SELECT_CC_VSRC;
2755 SelectCCOp = PPC::SELECT_CC_VRRC;
2757 SDValue Ops[] = { CCReg, N->getOperand(2), N->getOperand(3),
2758 getI32Imm(BROpc, dl) };
2759 return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops);
2762 if (PPCSubTarget->hasVSX()) {
2763 SDValue Ops[] = { N->getOperand(2), N->getOperand(1), N->getOperand(0) };
2764 return CurDAG->SelectNodeTo(N, PPC::XXSEL, N->getValueType(0), Ops);
2768 case ISD::VECTOR_SHUFFLE:
2769 if (PPCSubTarget->hasVSX() && (N->getValueType(0) == MVT::v2f64 ||
2770 N->getValueType(0) == MVT::v2i64)) {
2771 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
2773 SDValue Op1 = N->getOperand(SVN->getMaskElt(0) < 2 ? 0 : 1),
2774 Op2 = N->getOperand(SVN->getMaskElt(1) < 2 ? 0 : 1);
2777 for (int i = 0; i < 2; ++i)
2778 if (SVN->getMaskElt(i) <= 0 || SVN->getMaskElt(i) == 2)
2783 if (Op1 == Op2 && DM[0] == 0 && DM[1] == 0 &&
2784 Op1.getOpcode() == ISD::SCALAR_TO_VECTOR &&
2785 isa<LoadSDNode>(Op1.getOperand(0))) {
2786 LoadSDNode *LD = cast<LoadSDNode>(Op1.getOperand(0));
2787 SDValue Base, Offset;
2789 if (LD->isUnindexed() &&
2790 SelectAddrIdxOnly(LD->getBasePtr(), Base, Offset)) {
2791 SDValue Chain = LD->getChain();
2792 SDValue Ops[] = { Base, Offset, Chain };
2793 return CurDAG->SelectNodeTo(N, PPC::LXVDSX,
2794 N->getValueType(0), Ops);
2798 // For little endian, we must swap the input operands and adjust
2799 // the mask elements (reverse and invert them).
2800 if (PPCSubTarget->isLittleEndian()) {
2801 std::swap(Op1, Op2);
2802 unsigned tmp = DM[0];
2807 SDValue DMV = CurDAG->getTargetConstant(DM[1] | (DM[0] << 1), dl,
2809 SDValue Ops[] = { Op1, Op2, DMV };
2810 return CurDAG->SelectNodeTo(N, PPC::XXPERMDI, N->getValueType(0), Ops);
2816 bool IsPPC64 = PPCSubTarget->isPPC64();
2817 SDValue Ops[] = { N->getOperand(1), N->getOperand(0) };
2818 return CurDAG->SelectNodeTo(N, N->getOpcode() == PPCISD::BDNZ ?
2819 (IsPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
2820 (IsPPC64 ? PPC::BDZ8 : PPC::BDZ),
2823 case PPCISD::COND_BRANCH: {
2824 // Op #0 is the Chain.
2825 // Op #1 is the PPC::PRED_* number.
2827 // Op #3 is the Dest MBB
2828 // Op #4 is the Flag.
2829 // Prevent PPC::PRED_* from being selected into LI.
2831 getI32Imm(cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(), dl);
2832 SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3),
2833 N->getOperand(0), N->getOperand(4) };
2834 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops);
2837 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
2838 unsigned PCC = getPredicateForSetCC(CC);
2840 if (N->getOperand(2).getValueType() == MVT::i1) {
2844 default: llvm_unreachable("Unexpected Boolean-operand predicate");
2845 case PPC::PRED_LT: Opc = PPC::CRANDC; Swap = true; break;
2846 case PPC::PRED_LE: Opc = PPC::CRORC; Swap = true; break;
2847 case PPC::PRED_EQ: Opc = PPC::CREQV; Swap = false; break;
2848 case PPC::PRED_GE: Opc = PPC::CRORC; Swap = false; break;
2849 case PPC::PRED_GT: Opc = PPC::CRANDC; Swap = false; break;
2850 case PPC::PRED_NE: Opc = PPC::CRXOR; Swap = false; break;
2853 SDValue BitComp(CurDAG->getMachineNode(Opc, dl, MVT::i1,
2854 N->getOperand(Swap ? 3 : 2),
2855 N->getOperand(Swap ? 2 : 3)), 0);
2856 return CurDAG->SelectNodeTo(N, PPC::BC, MVT::Other,
2857 BitComp, N->getOperand(4), N->getOperand(0));
2860 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl);
2861 SDValue Ops[] = { getI32Imm(PCC, dl), CondCode,
2862 N->getOperand(4), N->getOperand(0) };
2863 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops);
2866 // FIXME: Should custom lower this.
2867 SDValue Chain = N->getOperand(0);
2868 SDValue Target = N->getOperand(1);
2869 unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
2870 unsigned Reg = Target.getValueType() == MVT::i32 ? PPC::BCTR : PPC::BCTR8;
2871 Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, Target,
2873 return CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain);
2875 case PPCISD::TOC_ENTRY: {
2876 assert ((PPCSubTarget->isPPC64() || PPCSubTarget->isSVR4ABI()) &&
2877 "Only supported for 64-bit ABI and 32-bit SVR4");
2878 if (PPCSubTarget->isSVR4ABI() && !PPCSubTarget->isPPC64()) {
2879 SDValue GA = N->getOperand(0);
2880 return transferMemOperands(N, CurDAG->getMachineNode(PPC::LWZtoc, dl,
2881 MVT::i32, GA, N->getOperand(1)));
2884 // For medium and large code model, we generate two instructions as
2885 // described below. Otherwise we allow SelectCodeCommon to handle this,
2886 // selecting one of LDtoc, LDtocJTI, LDtocCPT, and LDtocBA.
2887 CodeModel::Model CModel = TM.getCodeModel();
2888 if (CModel != CodeModel::Medium && CModel != CodeModel::Large)
2891 // The first source operand is a TargetGlobalAddress or a TargetJumpTable.
2892 // If it is an externally defined symbol, a symbol with common linkage,
2893 // a non-local function address, or a jump table address, or if we are
2894 // generating code for large code model, we generate:
2895 // LDtocL(<ga:@sym>, ADDIStocHA(%X2, <ga:@sym>))
2896 // Otherwise we generate:
2897 // ADDItocL(ADDIStocHA(%X2, <ga:@sym>), <ga:@sym>)
2898 SDValue GA = N->getOperand(0);
2899 SDValue TOCbase = N->getOperand(1);
2900 SDNode *Tmp = CurDAG->getMachineNode(PPC::ADDIStocHA, dl, MVT::i64,
2903 if (isa<JumpTableSDNode>(GA) || isa<BlockAddressSDNode>(GA) ||
2904 CModel == CodeModel::Large)
2905 return transferMemOperands(N, CurDAG->getMachineNode(PPC::LDtocL, dl,
2906 MVT::i64, GA, SDValue(Tmp, 0)));
2908 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(GA)) {
2909 const GlobalValue *GValue = G->getGlobal();
2910 if ((GValue->getType()->getElementType()->isFunctionTy() &&
2911 !GValue->isStrongDefinitionForLinker()) ||
2912 GValue->isDeclaration() || GValue->hasCommonLinkage() ||
2913 GValue->hasAvailableExternallyLinkage())
2914 return transferMemOperands(N, CurDAG->getMachineNode(PPC::LDtocL, dl,
2915 MVT::i64, GA, SDValue(Tmp, 0)));
2918 return CurDAG->getMachineNode(PPC::ADDItocL, dl, MVT::i64,
2919 SDValue(Tmp, 0), GA);
2921 case PPCISD::PPC32_PICGOT: {
2922 // Generate a PIC-safe GOT reference.
2923 assert(!PPCSubTarget->isPPC64() && PPCSubTarget->isSVR4ABI() &&
2924 "PPCISD::PPC32_PICGOT is only supported for 32-bit SVR4");
2925 return CurDAG->SelectNodeTo(
2926 N, PPC::PPC32PICGOT, PPCLowering->getPointerTy(CurDAG->getDataLayout()),
2929 case PPCISD::VADD_SPLAT: {
2930 // This expands into one of three sequences, depending on whether
2931 // the first operand is odd or even, positive or negative.
2932 assert(isa<ConstantSDNode>(N->getOperand(0)) &&
2933 isa<ConstantSDNode>(N->getOperand(1)) &&
2934 "Invalid operand on VADD_SPLAT!");
2936 int Elt = N->getConstantOperandVal(0);
2937 int EltSize = N->getConstantOperandVal(1);
2938 unsigned Opc1, Opc2, Opc3;
2942 Opc1 = PPC::VSPLTISB;
2943 Opc2 = PPC::VADDUBM;
2944 Opc3 = PPC::VSUBUBM;
2946 } else if (EltSize == 2) {
2947 Opc1 = PPC::VSPLTISH;
2948 Opc2 = PPC::VADDUHM;
2949 Opc3 = PPC::VSUBUHM;
2952 assert(EltSize == 4 && "Invalid element size on VADD_SPLAT!");
2953 Opc1 = PPC::VSPLTISW;
2954 Opc2 = PPC::VADDUWM;
2955 Opc3 = PPC::VSUBUWM;
2959 if ((Elt & 1) == 0) {
2960 // Elt is even, in the range [-32,-18] + [16,30].
2962 // Convert: VADD_SPLAT elt, size
2963 // Into: tmp = VSPLTIS[BHW] elt
2964 // VADDU[BHW]M tmp, tmp
2965 // Where: [BHW] = B for size = 1, H for size = 2, W for size = 4
2966 SDValue EltVal = getI32Imm(Elt >> 1, dl);
2967 SDNode *Tmp = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
2968 SDValue TmpVal = SDValue(Tmp, 0);
2969 return CurDAG->getMachineNode(Opc2, dl, VT, TmpVal, TmpVal);
2971 } else if (Elt > 0) {
2972 // Elt is odd and positive, in the range [17,31].
2974 // Convert: VADD_SPLAT elt, size
2975 // Into: tmp1 = VSPLTIS[BHW] elt-16
2976 // tmp2 = VSPLTIS[BHW] -16
2977 // VSUBU[BHW]M tmp1, tmp2
2978 SDValue EltVal = getI32Imm(Elt - 16, dl);
2979 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
2980 EltVal = getI32Imm(-16, dl);
2981 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
2982 return CurDAG->getMachineNode(Opc3, dl, VT, SDValue(Tmp1, 0),
2986 // Elt is odd and negative, in the range [-31,-17].
2988 // Convert: VADD_SPLAT elt, size
2989 // Into: tmp1 = VSPLTIS[BHW] elt+16
2990 // tmp2 = VSPLTIS[BHW] -16
2991 // VADDU[BHW]M tmp1, tmp2
2992 SDValue EltVal = getI32Imm(Elt + 16, dl);
2993 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
2994 EltVal = getI32Imm(-16, dl);
2995 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
2996 return CurDAG->getMachineNode(Opc2, dl, VT, SDValue(Tmp1, 0),
3002 return SelectCode(N);
3005 // If the target supports the cmpb instruction, do the idiom recognition here.
3006 // We don't do this as a DAG combine because we don't want to do it as nodes
3007 // are being combined (because we might miss part of the eventual idiom). We
3008 // don't want to do it during instruction selection because we want to reuse
3009 // the logic for lowering the masking operations already part of the
3010 // instruction selector.
3011 SDValue PPCDAGToDAGISel::combineToCMPB(SDNode *N) {
3014 assert(N->getOpcode() == ISD::OR &&
3015 "Only OR nodes are supported for CMPB");
3018 if (!PPCSubTarget->hasCMPB())
3021 if (N->getValueType(0) != MVT::i32 &&
3022 N->getValueType(0) != MVT::i64)
3025 EVT VT = N->getValueType(0);
3028 bool BytesFound[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
3029 uint64_t Mask = 0, Alt = 0;
3031 auto IsByteSelectCC = [this](SDValue O, unsigned &b,
3032 uint64_t &Mask, uint64_t &Alt,
3033 SDValue &LHS, SDValue &RHS) {
3034 if (O.getOpcode() != ISD::SELECT_CC)
3036 ISD::CondCode CC = cast<CondCodeSDNode>(O.getOperand(4))->get();
3038 if (!isa<ConstantSDNode>(O.getOperand(2)) ||
3039 !isa<ConstantSDNode>(O.getOperand(3)))
3042 uint64_t PM = O.getConstantOperandVal(2);
3043 uint64_t PAlt = O.getConstantOperandVal(3);
3044 for (b = 0; b < 8; ++b) {
3045 uint64_t Mask = UINT64_C(0xFF) << (8*b);
3046 if (PM && (PM & Mask) == PM && (PAlt & Mask) == PAlt)
3055 if (!isa<ConstantSDNode>(O.getOperand(1)) ||
3056 O.getConstantOperandVal(1) != 0) {
3057 SDValue Op0 = O.getOperand(0), Op1 = O.getOperand(1);
3058 if (Op0.getOpcode() == ISD::TRUNCATE)
3059 Op0 = Op0.getOperand(0);
3060 if (Op1.getOpcode() == ISD::TRUNCATE)
3061 Op1 = Op1.getOperand(0);
3063 if (Op0.getOpcode() == ISD::SRL && Op1.getOpcode() == ISD::SRL &&
3064 Op0.getOperand(1) == Op1.getOperand(1) && CC == ISD::SETEQ &&
3065 isa<ConstantSDNode>(Op0.getOperand(1))) {
3067 unsigned Bits = Op0.getValueType().getSizeInBits();
3070 if (Op0.getConstantOperandVal(1) != Bits-8)
3073 LHS = Op0.getOperand(0);
3074 RHS = Op1.getOperand(0);
3078 // When we have small integers (i16 to be specific), the form present
3079 // post-legalization uses SETULT in the SELECT_CC for the
3080 // higher-order byte, depending on the fact that the
3081 // even-higher-order bytes are known to all be zero, for example:
3082 // select_cc (xor $lhs, $rhs), 256, 65280, 0, setult
3083 // (so when the second byte is the same, because all higher-order
3084 // bits from bytes 3 and 4 are known to be zero, the result of the
3085 // xor can be at most 255)
3086 if (Op0.getOpcode() == ISD::XOR && CC == ISD::SETULT &&
3087 isa<ConstantSDNode>(O.getOperand(1))) {
3089 uint64_t ULim = O.getConstantOperandVal(1);
3090 if (ULim != (UINT64_C(1) << b*8))
3093 // Now we need to make sure that the upper bytes are known to be
3095 unsigned Bits = Op0.getValueType().getSizeInBits();
3096 if (!CurDAG->MaskedValueIsZero(Op0,
3097 APInt::getHighBitsSet(Bits, Bits - (b+1)*8)))
3100 LHS = Op0.getOperand(0);
3101 RHS = Op0.getOperand(1);
3108 if (CC != ISD::SETEQ)
3111 SDValue Op = O.getOperand(0);
3112 if (Op.getOpcode() == ISD::AND) {
3113 if (!isa<ConstantSDNode>(Op.getOperand(1)))
3115 if (Op.getConstantOperandVal(1) != (UINT64_C(0xFF) << (8*b)))
3118 SDValue XOR = Op.getOperand(0);
3119 if (XOR.getOpcode() == ISD::TRUNCATE)
3120 XOR = XOR.getOperand(0);
3121 if (XOR.getOpcode() != ISD::XOR)
3124 LHS = XOR.getOperand(0);
3125 RHS = XOR.getOperand(1);
3127 } else if (Op.getOpcode() == ISD::SRL) {
3128 if (!isa<ConstantSDNode>(Op.getOperand(1)))
3130 unsigned Bits = Op.getValueType().getSizeInBits();
3133 if (Op.getConstantOperandVal(1) != Bits-8)
3136 SDValue XOR = Op.getOperand(0);
3137 if (XOR.getOpcode() == ISD::TRUNCATE)
3138 XOR = XOR.getOperand(0);
3139 if (XOR.getOpcode() != ISD::XOR)
3142 LHS = XOR.getOperand(0);
3143 RHS = XOR.getOperand(1);
3150 SmallVector<SDValue, 8> Queue(1, SDValue(N, 0));
3151 while (!Queue.empty()) {
3152 SDValue V = Queue.pop_back_val();
3154 for (const SDValue &O : V.getNode()->ops()) {
3156 uint64_t M = 0, A = 0;
3158 if (O.getOpcode() == ISD::OR) {
3160 } else if (IsByteSelectCC(O, b, M, A, OLHS, ORHS)) {
3164 BytesFound[b] = true;
3167 } else if ((LHS == ORHS && RHS == OLHS) ||
3168 (RHS == ORHS && LHS == OLHS)) {
3169 BytesFound[b] = true;
3181 unsigned LastB = 0, BCnt = 0;
3182 for (unsigned i = 0; i < 8; ++i)
3183 if (BytesFound[LastB]) {
3188 if (!LastB || BCnt < 2)
3191 // Because we'll be zero-extending the output anyway if don't have a specific
3192 // value for each input byte (via the Mask), we can 'anyext' the inputs.
3193 if (LHS.getValueType() != VT) {
3194 LHS = CurDAG->getAnyExtOrTrunc(LHS, dl, VT);
3195 RHS = CurDAG->getAnyExtOrTrunc(RHS, dl, VT);
3198 Res = CurDAG->getNode(PPCISD::CMPB, dl, VT, LHS, RHS);
3200 bool NonTrivialMask = ((int64_t) Mask) != INT64_C(-1);
3201 if (NonTrivialMask && !Alt) {
3202 // Res = Mask & CMPB
3203 Res = CurDAG->getNode(ISD::AND, dl, VT, Res,
3204 CurDAG->getConstant(Mask, dl, VT));
3206 // Res = (CMPB & Mask) | (~CMPB & Alt)
3207 // Which, as suggested here:
3208 // https://graphics.stanford.edu/~seander/bithacks.html#MaskedMerge
3209 // can be written as:
3210 // Res = Alt ^ ((Alt ^ Mask) & CMPB)
3211 // useful because the (Alt ^ Mask) can be pre-computed.
3212 Res = CurDAG->getNode(ISD::AND, dl, VT, Res,
3213 CurDAG->getConstant(Mask ^ Alt, dl, VT));
3214 Res = CurDAG->getNode(ISD::XOR, dl, VT, Res,
3215 CurDAG->getConstant(Alt, dl, VT));
3221 // When CR bit registers are enabled, an extension of an i1 variable to a i32
3222 // or i64 value is lowered in terms of a SELECT_I[48] operation, and thus
3223 // involves constant materialization of a 0 or a 1 or both. If the result of
3224 // the extension is then operated upon by some operator that can be constant
3225 // folded with a constant 0 or 1, and that constant can be materialized using
3226 // only one instruction (like a zero or one), then we should fold in those
3227 // operations with the select.
3228 void PPCDAGToDAGISel::foldBoolExts(SDValue &Res, SDNode *&N) {
3229 if (!PPCSubTarget->useCRBits())
3232 if (N->getOpcode() != ISD::ZERO_EXTEND &&
3233 N->getOpcode() != ISD::SIGN_EXTEND &&
3234 N->getOpcode() != ISD::ANY_EXTEND)
3237 if (N->getOperand(0).getValueType() != MVT::i1)
3240 if (!N->hasOneUse())
3244 EVT VT = N->getValueType(0);
3245 SDValue Cond = N->getOperand(0);
3247 CurDAG->getConstant(N->getOpcode() == ISD::SIGN_EXTEND ? -1 : 1, dl, VT);
3248 SDValue ConstFalse = CurDAG->getConstant(0, dl, VT);
3251 SDNode *User = *N->use_begin();
3252 if (User->getNumOperands() != 2)
3255 auto TryFold = [this, N, User, dl](SDValue Val) {
3256 SDValue UserO0 = User->getOperand(0), UserO1 = User->getOperand(1);
3257 SDValue O0 = UserO0.getNode() == N ? Val : UserO0;
3258 SDValue O1 = UserO1.getNode() == N ? Val : UserO1;
3260 return CurDAG->FoldConstantArithmetic(User->getOpcode(), dl,
3261 User->getValueType(0),
3262 O0.getNode(), O1.getNode());
3265 SDValue TrueRes = TryFold(ConstTrue);
3268 SDValue FalseRes = TryFold(ConstFalse);
3272 // For us to materialize these using one instruction, we must be able to
3273 // represent them as signed 16-bit integers.
3274 uint64_t True = cast<ConstantSDNode>(TrueRes)->getZExtValue(),
3275 False = cast<ConstantSDNode>(FalseRes)->getZExtValue();
3276 if (!isInt<16>(True) || !isInt<16>(False))
3279 // We can replace User with a new SELECT node, and try again to see if we
3280 // can fold the select with its user.
3281 Res = CurDAG->getSelect(dl, User->getValueType(0), Cond, TrueRes, FalseRes);
3283 ConstTrue = TrueRes;
3284 ConstFalse = FalseRes;
3285 } while (N->hasOneUse());
3288 void PPCDAGToDAGISel::PreprocessISelDAG() {
3289 SelectionDAG::allnodes_iterator Position(CurDAG->getRoot().getNode());
3292 bool MadeChange = false;
3293 while (Position != CurDAG->allnodes_begin()) {
3294 SDNode *N = --Position;
3299 switch (N->getOpcode()) {
3302 Res = combineToCMPB(N);
3307 foldBoolExts(Res, N);
3310 DEBUG(dbgs() << "PPC DAG preprocessing replacing:\nOld: ");
3311 DEBUG(N->dump(CurDAG));
3312 DEBUG(dbgs() << "\nNew: ");
3313 DEBUG(Res.getNode()->dump(CurDAG));
3314 DEBUG(dbgs() << "\n");
3316 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Res);
3322 CurDAG->RemoveDeadNodes();
3325 /// PostprocessISelDAG - Perform some late peephole optimizations
3326 /// on the DAG representation.
3327 void PPCDAGToDAGISel::PostprocessISelDAG() {
3329 // Skip peepholes at -O0.
3330 if (TM.getOptLevel() == CodeGenOpt::None)
3335 PeepholePPC64ZExt();
3338 // Check if all users of this node will become isel where the second operand
3339 // is the constant zero. If this is so, and if we can negate the condition,
3340 // then we can flip the true and false operands. This will allow the zero to
3341 // be folded with the isel so that we don't need to materialize a register
3343 bool PPCDAGToDAGISel::AllUsersSelectZero(SDNode *N) {
3344 // If we're not using isel, then this does not matter.
3345 if (!PPCSubTarget->hasISEL())
3348 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
3351 if (!User->isMachineOpcode())
3353 if (User->getMachineOpcode() != PPC::SELECT_I4 &&
3354 User->getMachineOpcode() != PPC::SELECT_I8)
3357 SDNode *Op2 = User->getOperand(2).getNode();
3358 if (!Op2->isMachineOpcode())
3361 if (Op2->getMachineOpcode() != PPC::LI &&
3362 Op2->getMachineOpcode() != PPC::LI8)
3365 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op2->getOperand(0));
3369 if (!C->isNullValue())
3376 void PPCDAGToDAGISel::SwapAllSelectUsers(SDNode *N) {
3377 SmallVector<SDNode *, 4> ToReplace;
3378 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
3381 assert((User->getMachineOpcode() == PPC::SELECT_I4 ||
3382 User->getMachineOpcode() == PPC::SELECT_I8) &&
3383 "Must have all select users");
3384 ToReplace.push_back(User);
3387 for (SmallVector<SDNode *, 4>::iterator UI = ToReplace.begin(),
3388 UE = ToReplace.end(); UI != UE; ++UI) {
3391 CurDAG->getMachineNode(User->getMachineOpcode(), SDLoc(User),
3392 User->getValueType(0), User->getOperand(0),
3393 User->getOperand(2),
3394 User->getOperand(1));
3396 DEBUG(dbgs() << "CR Peephole replacing:\nOld: ");
3397 DEBUG(User->dump(CurDAG));
3398 DEBUG(dbgs() << "\nNew: ");
3399 DEBUG(ResNode->dump(CurDAG));
3400 DEBUG(dbgs() << "\n");
3402 ReplaceUses(User, ResNode);
3406 void PPCDAGToDAGISel::PeepholeCROps() {
3410 for (SDNode &Node : CurDAG->allnodes()) {
3411 MachineSDNode *MachineNode = dyn_cast<MachineSDNode>(&Node);
3412 if (!MachineNode || MachineNode->use_empty())
3414 SDNode *ResNode = MachineNode;
3416 bool Op1Set = false, Op1Unset = false,
3418 Op2Set = false, Op2Unset = false,
3421 unsigned Opcode = MachineNode->getMachineOpcode();
3432 SDValue Op = MachineNode->getOperand(1);
3433 if (Op.isMachineOpcode()) {
3434 if (Op.getMachineOpcode() == PPC::CRSET)
3436 else if (Op.getMachineOpcode() == PPC::CRUNSET)
3438 else if (Op.getMachineOpcode() == PPC::CRNOR &&
3439 Op.getOperand(0) == Op.getOperand(1))
3445 case PPC::SELECT_I4:
3446 case PPC::SELECT_I8:
3447 case PPC::SELECT_F4:
3448 case PPC::SELECT_F8:
3449 case PPC::SELECT_QFRC:
3450 case PPC::SELECT_QSRC:
3451 case PPC::SELECT_QBRC:
3452 case PPC::SELECT_VRRC:
3453 case PPC::SELECT_VSFRC:
3454 case PPC::SELECT_VSSRC:
3455 case PPC::SELECT_VSRC: {
3456 SDValue Op = MachineNode->getOperand(0);
3457 if (Op.isMachineOpcode()) {
3458 if (Op.getMachineOpcode() == PPC::CRSET)
3460 else if (Op.getMachineOpcode() == PPC::CRUNSET)
3462 else if (Op.getMachineOpcode() == PPC::CRNOR &&
3463 Op.getOperand(0) == Op.getOperand(1))
3470 bool SelectSwap = false;
3474 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
3476 ResNode = MachineNode->getOperand(0).getNode();
3479 ResNode = MachineNode->getOperand(1).getNode();
3482 ResNode = MachineNode->getOperand(0).getNode();
3483 else if (Op1Unset || Op2Unset)
3484 // x & 0 = 0 & y = 0
3485 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
3488 // ~x & y = andc(y, x)
3489 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
3490 MVT::i1, MachineNode->getOperand(1),
3491 MachineNode->getOperand(0).
3494 // x & ~y = andc(x, y)
3495 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
3496 MVT::i1, MachineNode->getOperand(0),
3497 MachineNode->getOperand(1).
3499 else if (AllUsersSelectZero(MachineNode))
3500 ResNode = CurDAG->getMachineNode(PPC::CRNAND, SDLoc(MachineNode),
3501 MVT::i1, MachineNode->getOperand(0),
3502 MachineNode->getOperand(1)),
3506 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
3507 // nand(x, x) -> nor(x, x)
3508 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3509 MVT::i1, MachineNode->getOperand(0),
3510 MachineNode->getOperand(0));
3512 // nand(1, y) -> nor(y, y)
3513 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3514 MVT::i1, MachineNode->getOperand(1),
3515 MachineNode->getOperand(1));
3517 // nand(x, 1) -> nor(x, x)
3518 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3519 MVT::i1, MachineNode->getOperand(0),
3520 MachineNode->getOperand(0));
3521 else if (Op1Unset || Op2Unset)
3522 // nand(x, 0) = nand(0, y) = 1
3523 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
3526 // nand(~x, y) = ~(~x & y) = x | ~y = orc(x, y)
3527 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
3528 MVT::i1, MachineNode->getOperand(0).
3530 MachineNode->getOperand(1));
3532 // nand(x, ~y) = ~x | y = orc(y, x)
3533 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
3534 MVT::i1, MachineNode->getOperand(1).
3536 MachineNode->getOperand(0));
3537 else if (AllUsersSelectZero(MachineNode))
3538 ResNode = CurDAG->getMachineNode(PPC::CRAND, SDLoc(MachineNode),
3539 MVT::i1, MachineNode->getOperand(0),
3540 MachineNode->getOperand(1)),
3544 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
3546 ResNode = MachineNode->getOperand(0).getNode();
3547 else if (Op1Set || Op2Set)
3548 // x | 1 = 1 | y = 1
3549 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
3553 ResNode = MachineNode->getOperand(1).getNode();
3556 ResNode = MachineNode->getOperand(0).getNode();
3558 // ~x | y = orc(y, x)
3559 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
3560 MVT::i1, MachineNode->getOperand(1),
3561 MachineNode->getOperand(0).
3564 // x | ~y = orc(x, y)
3565 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
3566 MVT::i1, MachineNode->getOperand(0),
3567 MachineNode->getOperand(1).
3569 else if (AllUsersSelectZero(MachineNode))
3570 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3571 MVT::i1, MachineNode->getOperand(0),
3572 MachineNode->getOperand(1)),
3576 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
3578 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
3581 // xor(1, y) -> nor(y, y)
3582 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3583 MVT::i1, MachineNode->getOperand(1),
3584 MachineNode->getOperand(1));
3586 // xor(x, 1) -> nor(x, x)
3587 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3588 MVT::i1, MachineNode->getOperand(0),
3589 MachineNode->getOperand(0));
3592 ResNode = MachineNode->getOperand(1).getNode();
3595 ResNode = MachineNode->getOperand(0).getNode();
3597 // xor(~x, y) = eqv(x, y)
3598 ResNode = CurDAG->getMachineNode(PPC::CREQV, SDLoc(MachineNode),
3599 MVT::i1, MachineNode->getOperand(0).
3601 MachineNode->getOperand(1));
3603 // xor(x, ~y) = eqv(x, y)
3604 ResNode = CurDAG->getMachineNode(PPC::CREQV, SDLoc(MachineNode),
3605 MVT::i1, MachineNode->getOperand(0),
3606 MachineNode->getOperand(1).
3608 else if (AllUsersSelectZero(MachineNode))
3609 ResNode = CurDAG->getMachineNode(PPC::CREQV, SDLoc(MachineNode),
3610 MVT::i1, MachineNode->getOperand(0),
3611 MachineNode->getOperand(1)),
3615 if (Op1Set || Op2Set)
3617 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
3620 // nor(0, y) = ~y -> nor(y, y)
3621 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3622 MVT::i1, MachineNode->getOperand(1),
3623 MachineNode->getOperand(1));
3626 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3627 MVT::i1, MachineNode->getOperand(0),
3628 MachineNode->getOperand(0));
3630 // nor(~x, y) = andc(x, y)
3631 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
3632 MVT::i1, MachineNode->getOperand(0).
3634 MachineNode->getOperand(1));
3636 // nor(x, ~y) = andc(y, x)
3637 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
3638 MVT::i1, MachineNode->getOperand(1).
3640 MachineNode->getOperand(0));
3641 else if (AllUsersSelectZero(MachineNode))
3642 ResNode = CurDAG->getMachineNode(PPC::CROR, SDLoc(MachineNode),
3643 MVT::i1, MachineNode->getOperand(0),
3644 MachineNode->getOperand(1)),
3648 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
3650 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
3654 ResNode = MachineNode->getOperand(1).getNode();
3657 ResNode = MachineNode->getOperand(0).getNode();
3659 // eqv(0, y) = ~y -> nor(y, y)
3660 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3661 MVT::i1, MachineNode->getOperand(1),
3662 MachineNode->getOperand(1));
3665 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3666 MVT::i1, MachineNode->getOperand(0),
3667 MachineNode->getOperand(0));
3669 // eqv(~x, y) = xor(x, y)
3670 ResNode = CurDAG->getMachineNode(PPC::CRXOR, SDLoc(MachineNode),
3671 MVT::i1, MachineNode->getOperand(0).
3673 MachineNode->getOperand(1));
3675 // eqv(x, ~y) = xor(x, y)
3676 ResNode = CurDAG->getMachineNode(PPC::CRXOR, SDLoc(MachineNode),
3677 MVT::i1, MachineNode->getOperand(0),
3678 MachineNode->getOperand(1).
3680 else if (AllUsersSelectZero(MachineNode))
3681 ResNode = CurDAG->getMachineNode(PPC::CRXOR, SDLoc(MachineNode),
3682 MVT::i1, MachineNode->getOperand(0),
3683 MachineNode->getOperand(1)),
3687 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
3689 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
3693 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3694 MVT::i1, MachineNode->getOperand(1),
3695 MachineNode->getOperand(1));
3696 else if (Op1Unset || Op2Set)
3697 // andc(0, y) = andc(x, 1) = 0
3698 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
3702 ResNode = MachineNode->getOperand(0).getNode();
3704 // andc(~x, y) = ~(x | y) = nor(x, y)
3705 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3706 MVT::i1, MachineNode->getOperand(0).
3708 MachineNode->getOperand(1));
3710 // andc(x, ~y) = x & y
3711 ResNode = CurDAG->getMachineNode(PPC::CRAND, SDLoc(MachineNode),
3712 MVT::i1, MachineNode->getOperand(0),
3713 MachineNode->getOperand(1).
3715 else if (AllUsersSelectZero(MachineNode))
3716 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
3717 MVT::i1, MachineNode->getOperand(1),
3718 MachineNode->getOperand(0)),
3722 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
3724 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
3726 else if (Op1Set || Op2Unset)
3727 // orc(1, y) = orc(x, 0) = 1
3728 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
3732 ResNode = MachineNode->getOperand(0).getNode();
3735 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3736 MVT::i1, MachineNode->getOperand(1),
3737 MachineNode->getOperand(1));
3739 // orc(~x, y) = ~(x & y) = nand(x, y)
3740 ResNode = CurDAG->getMachineNode(PPC::CRNAND, SDLoc(MachineNode),
3741 MVT::i1, MachineNode->getOperand(0).
3743 MachineNode->getOperand(1));
3745 // orc(x, ~y) = x | y
3746 ResNode = CurDAG->getMachineNode(PPC::CROR, SDLoc(MachineNode),
3747 MVT::i1, MachineNode->getOperand(0),
3748 MachineNode->getOperand(1).
3750 else if (AllUsersSelectZero(MachineNode))
3751 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
3752 MVT::i1, MachineNode->getOperand(1),
3753 MachineNode->getOperand(0)),
3756 case PPC::SELECT_I4:
3757 case PPC::SELECT_I8:
3758 case PPC::SELECT_F4:
3759 case PPC::SELECT_F8:
3760 case PPC::SELECT_QFRC:
3761 case PPC::SELECT_QSRC:
3762 case PPC::SELECT_QBRC:
3763 case PPC::SELECT_VRRC:
3764 case PPC::SELECT_VSFRC:
3765 case PPC::SELECT_VSSRC:
3766 case PPC::SELECT_VSRC:
3768 ResNode = MachineNode->getOperand(1).getNode();
3770 ResNode = MachineNode->getOperand(2).getNode();
3772 ResNode = CurDAG->getMachineNode(MachineNode->getMachineOpcode(),
3774 MachineNode->getValueType(0),
3775 MachineNode->getOperand(0).
3777 MachineNode->getOperand(2),
3778 MachineNode->getOperand(1));
3783 ResNode = CurDAG->getMachineNode(Opcode == PPC::BC ? PPC::BCn :
3787 MachineNode->getOperand(0).
3789 MachineNode->getOperand(1),
3790 MachineNode->getOperand(2));
3791 // FIXME: Handle Op1Set, Op1Unset here too.
3795 // If we're inverting this node because it is used only by selects that
3796 // we'd like to swap, then swap the selects before the node replacement.
3798 SwapAllSelectUsers(MachineNode);
3800 if (ResNode != MachineNode) {
3801 DEBUG(dbgs() << "CR Peephole replacing:\nOld: ");
3802 DEBUG(MachineNode->dump(CurDAG));
3803 DEBUG(dbgs() << "\nNew: ");
3804 DEBUG(ResNode->dump(CurDAG));
3805 DEBUG(dbgs() << "\n");
3807 ReplaceUses(MachineNode, ResNode);
3812 CurDAG->RemoveDeadNodes();
3813 } while (IsModified);
3816 // Gather the set of 32-bit operations that are known to have their
3817 // higher-order 32 bits zero, where ToPromote contains all such operations.
3818 static bool PeepholePPC64ZExtGather(SDValue Op32,
3819 SmallPtrSetImpl<SDNode *> &ToPromote) {
3820 if (!Op32.isMachineOpcode())
3823 // First, check for the "frontier" instructions (those that will clear the
3824 // higher-order 32 bits.
3826 // For RLWINM and RLWNM, we need to make sure that the mask does not wrap
3827 // around. If it does not, then these instructions will clear the
3828 // higher-order bits.
3829 if ((Op32.getMachineOpcode() == PPC::RLWINM ||
3830 Op32.getMachineOpcode() == PPC::RLWNM) &&
3831 Op32.getConstantOperandVal(2) <= Op32.getConstantOperandVal(3)) {
3832 ToPromote.insert(Op32.getNode());
3836 // SLW and SRW always clear the higher-order bits.
3837 if (Op32.getMachineOpcode() == PPC::SLW ||
3838 Op32.getMachineOpcode() == PPC::SRW) {
3839 ToPromote.insert(Op32.getNode());
3843 // For LI and LIS, we need the immediate to be positive (so that it is not
3845 if (Op32.getMachineOpcode() == PPC::LI ||
3846 Op32.getMachineOpcode() == PPC::LIS) {
3847 if (!isUInt<15>(Op32.getConstantOperandVal(0)))
3850 ToPromote.insert(Op32.getNode());
3854 // LHBRX and LWBRX always clear the higher-order bits.
3855 if (Op32.getMachineOpcode() == PPC::LHBRX ||
3856 Op32.getMachineOpcode() == PPC::LWBRX) {
3857 ToPromote.insert(Op32.getNode());
3861 // CNTLZW always produces a 64-bit value in [0,32], and so is zero extended.
3862 if (Op32.getMachineOpcode() == PPC::CNTLZW) {
3863 ToPromote.insert(Op32.getNode());
3867 // Next, check for those instructions we can look through.
3869 // Assuming the mask does not wrap around, then the higher-order bits are
3870 // taken directly from the first operand.
3871 if (Op32.getMachineOpcode() == PPC::RLWIMI &&
3872 Op32.getConstantOperandVal(3) <= Op32.getConstantOperandVal(4)) {
3873 SmallPtrSet<SDNode *, 16> ToPromote1;
3874 if (!PeepholePPC64ZExtGather(Op32.getOperand(0), ToPromote1))
3877 ToPromote.insert(Op32.getNode());
3878 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
3882 // For OR, the higher-order bits are zero if that is true for both operands.
3883 // For SELECT_I4, the same is true (but the relevant operand numbers are
3885 if (Op32.getMachineOpcode() == PPC::OR ||
3886 Op32.getMachineOpcode() == PPC::SELECT_I4) {
3887 unsigned B = Op32.getMachineOpcode() == PPC::SELECT_I4 ? 1 : 0;
3888 SmallPtrSet<SDNode *, 16> ToPromote1;
3889 if (!PeepholePPC64ZExtGather(Op32.getOperand(B+0), ToPromote1))
3891 if (!PeepholePPC64ZExtGather(Op32.getOperand(B+1), ToPromote1))
3894 ToPromote.insert(Op32.getNode());
3895 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
3899 // For ORI and ORIS, we need the higher-order bits of the first operand to be
3900 // zero, and also for the constant to be positive (so that it is not sign
3902 if (Op32.getMachineOpcode() == PPC::ORI ||
3903 Op32.getMachineOpcode() == PPC::ORIS) {
3904 SmallPtrSet<SDNode *, 16> ToPromote1;
3905 if (!PeepholePPC64ZExtGather(Op32.getOperand(0), ToPromote1))
3907 if (!isUInt<15>(Op32.getConstantOperandVal(1)))
3910 ToPromote.insert(Op32.getNode());
3911 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
3915 // The higher-order bits of AND are zero if that is true for at least one of
3917 if (Op32.getMachineOpcode() == PPC::AND) {
3918 SmallPtrSet<SDNode *, 16> ToPromote1, ToPromote2;
3920 PeepholePPC64ZExtGather(Op32.getOperand(0), ToPromote1);
3922 PeepholePPC64ZExtGather(Op32.getOperand(1), ToPromote2);
3923 if (!Op0OK && !Op1OK)
3926 ToPromote.insert(Op32.getNode());
3929 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
3932 ToPromote.insert(ToPromote2.begin(), ToPromote2.end());
3937 // For ANDI and ANDIS, the higher-order bits are zero if either that is true
3938 // of the first operand, or if the second operand is positive (so that it is
3939 // not sign extended).
3940 if (Op32.getMachineOpcode() == PPC::ANDIo ||
3941 Op32.getMachineOpcode() == PPC::ANDISo) {
3942 SmallPtrSet<SDNode *, 16> ToPromote1;
3944 PeepholePPC64ZExtGather(Op32.getOperand(0), ToPromote1);
3945 bool Op1OK = isUInt<15>(Op32.getConstantOperandVal(1));
3946 if (!Op0OK && !Op1OK)
3949 ToPromote.insert(Op32.getNode());
3952 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
3960 void PPCDAGToDAGISel::PeepholePPC64ZExt() {
3961 if (!PPCSubTarget->isPPC64())
3964 // When we zero-extend from i32 to i64, we use a pattern like this:
3965 // def : Pat<(i64 (zext i32:$in)),
3966 // (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32),
3968 // There are several 32-bit shift/rotate instructions, however, that will
3969 // clear the higher-order bits of their output, rendering the RLDICL
3970 // unnecessary. When that happens, we remove it here, and redefine the
3971 // relevant 32-bit operation to be a 64-bit operation.
3973 SelectionDAG::allnodes_iterator Position(CurDAG->getRoot().getNode());
3976 bool MadeChange = false;
3977 while (Position != CurDAG->allnodes_begin()) {
3978 SDNode *N = --Position;
3979 // Skip dead nodes and any non-machine opcodes.
3980 if (N->use_empty() || !N->isMachineOpcode())
3983 if (N->getMachineOpcode() != PPC::RLDICL)
3986 if (N->getConstantOperandVal(1) != 0 ||
3987 N->getConstantOperandVal(2) != 32)
3990 SDValue ISR = N->getOperand(0);
3991 if (!ISR.isMachineOpcode() ||
3992 ISR.getMachineOpcode() != TargetOpcode::INSERT_SUBREG)
3995 if (!ISR.hasOneUse())
3998 if (ISR.getConstantOperandVal(2) != PPC::sub_32)
4001 SDValue IDef = ISR.getOperand(0);
4002 if (!IDef.isMachineOpcode() ||
4003 IDef.getMachineOpcode() != TargetOpcode::IMPLICIT_DEF)
4006 // We now know that we're looking at a canonical i32 -> i64 zext. See if we
4007 // can get rid of it.
4009 SDValue Op32 = ISR->getOperand(1);
4010 if (!Op32.isMachineOpcode())
4013 // There are some 32-bit instructions that always clear the high-order 32
4014 // bits, there are also some instructions (like AND) that we can look
4016 SmallPtrSet<SDNode *, 16> ToPromote;
4017 if (!PeepholePPC64ZExtGather(Op32, ToPromote))
4020 // If the ToPromote set contains nodes that have uses outside of the set
4021 // (except for the original INSERT_SUBREG), then abort the transformation.
4022 bool OutsideUse = false;
4023 for (SDNode *PN : ToPromote) {
4024 for (SDNode *UN : PN->uses()) {
4025 if (!ToPromote.count(UN) && UN != ISR.getNode()) {
4039 // We now know that this zero extension can be removed by promoting to
4040 // nodes in ToPromote to 64-bit operations, where for operations in the
4041 // frontier of the set, we need to insert INSERT_SUBREGs for their
4043 for (SDNode *PN : ToPromote) {
4045 switch (PN->getMachineOpcode()) {
4047 llvm_unreachable("Don't know the 64-bit variant of this instruction");
4048 case PPC::RLWINM: NewOpcode = PPC::RLWINM8; break;
4049 case PPC::RLWNM: NewOpcode = PPC::RLWNM8; break;
4050 case PPC::SLW: NewOpcode = PPC::SLW8; break;
4051 case PPC::SRW: NewOpcode = PPC::SRW8; break;
4052 case PPC::LI: NewOpcode = PPC::LI8; break;
4053 case PPC::LIS: NewOpcode = PPC::LIS8; break;
4054 case PPC::LHBRX: NewOpcode = PPC::LHBRX8; break;
4055 case PPC::LWBRX: NewOpcode = PPC::LWBRX8; break;
4056 case PPC::CNTLZW: NewOpcode = PPC::CNTLZW8; break;
4057 case PPC::RLWIMI: NewOpcode = PPC::RLWIMI8; break;
4058 case PPC::OR: NewOpcode = PPC::OR8; break;
4059 case PPC::SELECT_I4: NewOpcode = PPC::SELECT_I8; break;
4060 case PPC::ORI: NewOpcode = PPC::ORI8; break;
4061 case PPC::ORIS: NewOpcode = PPC::ORIS8; break;
4062 case PPC::AND: NewOpcode = PPC::AND8; break;
4063 case PPC::ANDIo: NewOpcode = PPC::ANDIo8; break;
4064 case PPC::ANDISo: NewOpcode = PPC::ANDISo8; break;
4067 // Note: During the replacement process, the nodes will be in an
4068 // inconsistent state (some instructions will have operands with values
4069 // of the wrong type). Once done, however, everything should be right
4072 SmallVector<SDValue, 4> Ops;
4073 for (const SDValue &V : PN->ops()) {
4074 if (!ToPromote.count(V.getNode()) && V.getValueType() == MVT::i32 &&
4075 !isa<ConstantSDNode>(V)) {
4076 SDValue ReplOpOps[] = { ISR.getOperand(0), V, ISR.getOperand(2) };
4078 CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, SDLoc(V),
4079 ISR.getNode()->getVTList(), ReplOpOps);
4080 Ops.push_back(SDValue(ReplOp, 0));
4086 // Because all to-be-promoted nodes only have users that are other
4087 // promoted nodes (or the original INSERT_SUBREG), we can safely replace
4088 // the i32 result value type with i64.
4090 SmallVector<EVT, 2> NewVTs;
4091 SDVTList VTs = PN->getVTList();
4092 for (unsigned i = 0, ie = VTs.NumVTs; i != ie; ++i)
4093 if (VTs.VTs[i] == MVT::i32)
4094 NewVTs.push_back(MVT::i64);
4096 NewVTs.push_back(VTs.VTs[i]);
4098 DEBUG(dbgs() << "PPC64 ZExt Peephole morphing:\nOld: ");
4099 DEBUG(PN->dump(CurDAG));
4101 CurDAG->SelectNodeTo(PN, NewOpcode, CurDAG->getVTList(NewVTs), Ops);
4103 DEBUG(dbgs() << "\nNew: ");
4104 DEBUG(PN->dump(CurDAG));
4105 DEBUG(dbgs() << "\n");
4108 // Now we replace the original zero extend and its associated INSERT_SUBREG
4109 // with the value feeding the INSERT_SUBREG (which has now been promoted to
4112 DEBUG(dbgs() << "PPC64 ZExt Peephole replacing:\nOld: ");
4113 DEBUG(N->dump(CurDAG));
4114 DEBUG(dbgs() << "\nNew: ");
4115 DEBUG(Op32.getNode()->dump(CurDAG));
4116 DEBUG(dbgs() << "\n");
4118 ReplaceUses(N, Op32.getNode());
4122 CurDAG->RemoveDeadNodes();
4125 void PPCDAGToDAGISel::PeepholePPC64() {
4126 // These optimizations are currently supported only for 64-bit SVR4.
4127 if (PPCSubTarget->isDarwin() || !PPCSubTarget->isPPC64())
4130 SelectionDAG::allnodes_iterator Position(CurDAG->getRoot().getNode());
4133 while (Position != CurDAG->allnodes_begin()) {
4134 SDNode *N = --Position;
4135 // Skip dead nodes and any non-machine opcodes.
4136 if (N->use_empty() || !N->isMachineOpcode())
4140 unsigned StorageOpcode = N->getMachineOpcode();
4142 switch (StorageOpcode) {
4173 // If this is a load or store with a zero offset, we may be able to
4174 // fold an add-immediate into the memory operation.
4175 if (!isa<ConstantSDNode>(N->getOperand(FirstOp)) ||
4176 N->getConstantOperandVal(FirstOp) != 0)
4179 SDValue Base = N->getOperand(FirstOp + 1);
4180 if (!Base.isMachineOpcode())
4184 bool ReplaceFlags = true;
4186 // When the feeding operation is an add-immediate of some sort,
4187 // determine whether we need to add relocation information to the
4188 // target flags on the immediate operand when we fold it into the
4189 // load instruction.
4191 // For something like ADDItocL, the relocation information is
4192 // inferred from the opcode; when we process it in the AsmPrinter,
4193 // we add the necessary relocation there. A load, though, can receive
4194 // relocation from various flavors of ADDIxxx, so we need to carry
4195 // the relocation information in the target flags.
4196 switch (Base.getMachineOpcode()) {
4201 // In some cases (such as TLS) the relocation information
4202 // is already in place on the operand, so copying the operand
4204 ReplaceFlags = false;
4205 // For these cases, the immediate may not be divisible by 4, in
4206 // which case the fold is illegal for DS-form instructions. (The
4207 // other cases provide aligned addresses and are always safe.)
4208 if ((StorageOpcode == PPC::LWA ||
4209 StorageOpcode == PPC::LD ||
4210 StorageOpcode == PPC::STD) &&
4211 (!isa<ConstantSDNode>(Base.getOperand(1)) ||
4212 Base.getConstantOperandVal(1) % 4 != 0))
4215 case PPC::ADDIdtprelL:
4216 Flags = PPCII::MO_DTPREL_LO;
4218 case PPC::ADDItlsldL:
4219 Flags = PPCII::MO_TLSLD_LO;
4222 Flags = PPCII::MO_TOC_LO;
4226 // We found an opportunity. Reverse the operands from the add
4227 // immediate and substitute them into the load or store. If
4228 // needed, update the target flags for the immediate operand to
4229 // reflect the necessary relocation information.
4230 DEBUG(dbgs() << "Folding add-immediate into mem-op:\nBase: ");
4231 DEBUG(Base->dump(CurDAG));
4232 DEBUG(dbgs() << "\nN: ");
4233 DEBUG(N->dump(CurDAG));
4234 DEBUG(dbgs() << "\n");
4236 SDValue ImmOpnd = Base.getOperand(1);
4238 // If the relocation information isn't already present on the
4239 // immediate operand, add it now.
4241 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(ImmOpnd)) {
4243 const GlobalValue *GV = GA->getGlobal();
4244 // We can't perform this optimization for data whose alignment
4245 // is insufficient for the instruction encoding.
4246 if (GV->getAlignment() < 4 &&
4247 (StorageOpcode == PPC::LD || StorageOpcode == PPC::STD ||
4248 StorageOpcode == PPC::LWA)) {
4249 DEBUG(dbgs() << "Rejected this candidate for alignment.\n\n");
4252 ImmOpnd = CurDAG->getTargetGlobalAddress(GV, dl, MVT::i64, 0, Flags);
4253 } else if (ConstantPoolSDNode *CP =
4254 dyn_cast<ConstantPoolSDNode>(ImmOpnd)) {
4255 const Constant *C = CP->getConstVal();
4256 ImmOpnd = CurDAG->getTargetConstantPool(C, MVT::i64,
4262 if (FirstOp == 1) // Store
4263 (void)CurDAG->UpdateNodeOperands(N, N->getOperand(0), ImmOpnd,
4264 Base.getOperand(0), N->getOperand(3));
4266 (void)CurDAG->UpdateNodeOperands(N, ImmOpnd, Base.getOperand(0),
4269 // The add-immediate may now be dead, in which case remove it.
4270 if (Base.getNode()->use_empty())
4271 CurDAG->RemoveDeadNode(Base.getNode());
4276 /// createPPCISelDag - This pass converts a legalized DAG into a
4277 /// PowerPC-specific DAG, ready for instruction scheduling.
4279 FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) {
4280 return new PPCDAGToDAGISel(TM);
4283 static void initializePassOnce(PassRegistry &Registry) {
4284 const char *Name = "PowerPC DAG->DAG Pattern Instruction Selection";
4285 PassInfo *PI = new PassInfo(Name, "ppc-codegen", &SelectionDAGISel::ID,
4286 nullptr, false, false);
4287 Registry.registerPass(*PI, true);
4290 void llvm::initializePPCDAGToDAGISelPass(PassRegistry &Registry) {
4291 CALL_ONCE_INITIALIZATION(initializePassOnce);