1 //===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for PowerPC,
11 // converting from a legalized dag to a PPC dag.
13 //===----------------------------------------------------------------------===//
16 #include "PPCPredicates.h"
17 #include "PPCTargetMachine.h"
18 #include "PPCISelLowering.h"
19 #include "PPCHazardRecognizers.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/SSARegMap.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/CodeGen/SelectionDAGISel.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/ADT/Statistic.h"
27 #include "llvm/Constants.h"
28 #include "llvm/GlobalValue.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/Support/Compiler.h"
38 Statistic FrameOff("ppc-codegen", "Number of frame idx offsets collapsed");
40 //===--------------------------------------------------------------------===//
41 /// PPCDAGToDAGISel - PPC specific code to select PPC machine
42 /// instructions for SelectionDAG operations.
44 class VISIBILITY_HIDDEN PPCDAGToDAGISel : public SelectionDAGISel {
46 PPCTargetLowering PPCLowering;
47 unsigned GlobalBaseReg;
49 PPCDAGToDAGISel(PPCTargetMachine &tm)
50 : SelectionDAGISel(PPCLowering), TM(tm),
51 PPCLowering(*TM.getTargetLowering()) {}
53 virtual bool runOnFunction(Function &Fn) {
54 // Make sure we re-emit a set of the global base reg if necessary
56 SelectionDAGISel::runOnFunction(Fn);
62 /// getI32Imm - Return a target constant with the specified value, of type
64 inline SDOperand getI32Imm(unsigned Imm) {
65 return CurDAG->getTargetConstant(Imm, MVT::i32);
68 /// getI64Imm - Return a target constant with the specified value, of type
70 inline SDOperand getI64Imm(uint64_t Imm) {
71 return CurDAG->getTargetConstant(Imm, MVT::i64);
74 /// getSmallIPtrImm - Return a target constant of pointer type.
75 inline SDOperand getSmallIPtrImm(unsigned Imm) {
76 return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy());
79 /// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s
80 /// with any number of 0s on either side. The 1s are allowed to wrap from
81 /// LSB to MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs.
82 /// 0x0F0F0000 is not, since all 1s are not contiguous.
83 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME);
86 /// isRotateAndMask - Returns true if Mask and Shift can be folded into a
87 /// rotate and mask opcode and mask operation.
88 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask,
89 unsigned &SH, unsigned &MB, unsigned &ME);
91 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
92 /// base register. Return the virtual register that holds this value.
93 SDNode *getGlobalBaseReg();
95 // Select - Convert the specified operand from a target-independent to a
96 // target-specific node if it hasn't already been changed.
97 SDNode *Select(SDOperand Op);
99 SDNode *SelectBitfieldInsert(SDNode *N);
101 /// SelectCC - Select a comparison of the specified values with the
102 /// specified condition code, returning the CR# of the expression.
103 SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
105 /// SelectAddrImm - Returns true if the address N can be represented by
106 /// a base register plus a signed 16-bit displacement [r+imm].
107 bool SelectAddrImm(SDOperand Op, SDOperand N, SDOperand &Disp,
109 return PPCLowering.SelectAddressRegImm(N, Disp, Base, *CurDAG);
112 /// SelectAddrImmOffs - Return true if the operand is valid for a preinc
113 /// immediate field. Because preinc imms have already been validated, just
115 bool SelectAddrImmOffs(SDOperand Op, SDOperand N, SDOperand &Out) const {
120 /// SelectAddrIdx - Given the specified addressed, check to see if it can be
121 /// represented as an indexed [r+r] operation. Returns false if it can
122 /// be represented by [r+imm], which are preferred.
123 bool SelectAddrIdx(SDOperand Op, SDOperand N, SDOperand &Base,
125 return PPCLowering.SelectAddressRegReg(N, Base, Index, *CurDAG);
128 /// SelectAddrIdxOnly - Given the specified addressed, force it to be
129 /// represented as an indexed [r+r] operation.
130 bool SelectAddrIdxOnly(SDOperand Op, SDOperand N, SDOperand &Base,
132 return PPCLowering.SelectAddressRegRegOnly(N, Base, Index, *CurDAG);
135 /// SelectAddrImmShift - Returns true if the address N can be represented by
136 /// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable
137 /// for use by STD and friends.
138 bool SelectAddrImmShift(SDOperand Op, SDOperand N, SDOperand &Disp,
140 return PPCLowering.SelectAddressRegImmShift(N, Disp, Base, *CurDAG);
143 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
144 /// inline asm expressions.
145 virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
147 std::vector<SDOperand> &OutOps,
150 switch (ConstraintCode) {
151 default: return true;
153 if (!SelectAddrIdx(Op, Op, Op0, Op1))
154 SelectAddrImm(Op, Op, Op0, Op1);
156 case 'o': // offsetable
157 if (!SelectAddrImm(Op, Op, Op0, Op1)) {
159 AddToISelQueue(Op0); // r+0.
160 Op1 = getSmallIPtrImm(0);
163 case 'v': // not offsetable
164 SelectAddrIdxOnly(Op, Op, Op0, Op1);
168 OutOps.push_back(Op0);
169 OutOps.push_back(Op1);
173 SDOperand BuildSDIVSequence(SDNode *N);
174 SDOperand BuildUDIVSequence(SDNode *N);
176 /// InstructionSelectBasicBlock - This callback is invoked by
177 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
178 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
180 void InsertVRSaveCode(Function &Fn);
182 virtual const char *getPassName() const {
183 return "PowerPC DAG->DAG Pattern Instruction Selection";
186 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
187 /// this target when scheduling the DAG.
188 virtual HazardRecognizer *CreateTargetHazardRecognizer() {
189 // Should use subtarget info to pick the right hazard recognizer. For
190 // now, always return a PPC970 recognizer.
191 const TargetInstrInfo *II = PPCLowering.getTargetMachine().getInstrInfo();
192 assert(II && "No InstrInfo?");
193 return new PPCHazardRecognizer970(*II);
196 // Include the pieces autogenerated from the target description.
197 #include "PPCGenDAGISel.inc"
200 SDNode *SelectSETCC(SDOperand Op);
204 /// InstructionSelectBasicBlock - This callback is invoked by
205 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
206 void PPCDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
209 // Select target instructions for the DAG.
210 DAG.setRoot(SelectRoot(DAG.getRoot()));
211 DAG.RemoveDeadNodes();
213 // Emit machine code to BB.
214 ScheduleAndEmitDAG(DAG);
217 /// InsertVRSaveCode - Once the entire function has been instruction selected,
218 /// all virtual registers are created and all machine instructions are built,
219 /// check to see if we need to save/restore VRSAVE. If so, do it.
220 void PPCDAGToDAGISel::InsertVRSaveCode(Function &F) {
221 // Check to see if this function uses vector registers, which means we have to
222 // save and restore the VRSAVE register and update it with the regs we use.
224 // In this case, there will be virtual registers of vector type type created
225 // by the scheduler. Detect them now.
226 MachineFunction &Fn = MachineFunction::get(&F);
227 SSARegMap *RegMap = Fn.getSSARegMap();
228 bool HasVectorVReg = false;
229 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
230 e = RegMap->getLastVirtReg()+1; i != e; ++i)
231 if (RegMap->getRegClass(i) == &PPC::VRRCRegClass) {
232 HasVectorVReg = true;
235 if (!HasVectorVReg) return; // nothing to do.
237 // If we have a vector register, we want to emit code into the entry and exit
238 // blocks to save and restore the VRSAVE register. We do this here (instead
239 // of marking all vector instructions as clobbering VRSAVE) for two reasons:
241 // 1. This (trivially) reduces the load on the register allocator, by not
242 // having to represent the live range of the VRSAVE register.
243 // 2. This (more significantly) allows us to create a temporary virtual
244 // register to hold the saved VRSAVE value, allowing this temporary to be
245 // register allocated, instead of forcing it to be spilled to the stack.
247 // Create two vregs - one to hold the VRSAVE register that is live-in to the
248 // function and one for the value after having bits or'd into it.
249 unsigned InVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
250 unsigned UpdatedVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
252 const TargetInstrInfo &TII = *TM.getInstrInfo();
253 MachineBasicBlock &EntryBB = *Fn.begin();
254 // Emit the following code into the entry block:
255 // InVRSAVE = MFVRSAVE
256 // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
257 // MTVRSAVE UpdatedVRSAVE
258 MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
259 BuildMI(EntryBB, IP, TII.get(PPC::MFVRSAVE), InVRSAVE);
260 BuildMI(EntryBB, IP, TII.get(PPC::UPDATE_VRSAVE), UpdatedVRSAVE).addReg(InVRSAVE);
261 BuildMI(EntryBB, IP, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
263 // Find all return blocks, outputting a restore in each epilog.
264 for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
265 if (!BB->empty() && TII.isReturn(BB->back().getOpcode())) {
266 IP = BB->end(); --IP;
268 // Skip over all terminator instructions, which are part of the return
270 MachineBasicBlock::iterator I2 = IP;
271 while (I2 != BB->begin() && TII.isTerminatorInstr((--I2)->getOpcode()))
274 // Emit: MTVRSAVE InVRSave
275 BuildMI(*BB, IP, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
281 /// getGlobalBaseReg - Output the instructions required to put the
282 /// base address to use for accessing globals into a register.
284 SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
285 if (!GlobalBaseReg) {
286 const TargetInstrInfo &TII = *TM.getInstrInfo();
287 // Insert the set of GlobalBaseReg into the first MBB of the function
288 MachineBasicBlock &FirstMBB = BB->getParent()->front();
289 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
290 SSARegMap *RegMap = BB->getParent()->getSSARegMap();
292 if (PPCLowering.getPointerTy() == MVT::i32) {
293 GlobalBaseReg = RegMap->createVirtualRegister(PPC::GPRCRegisterClass);
294 BuildMI(FirstMBB, MBBI, TII.get(PPC::MovePCtoLR), PPC::LR);
295 BuildMI(FirstMBB, MBBI, TII.get(PPC::MFLR), GlobalBaseReg);
297 GlobalBaseReg = RegMap->createVirtualRegister(PPC::G8RCRegisterClass);
298 BuildMI(FirstMBB, MBBI, TII.get(PPC::MovePCtoLR8), PPC::LR8);
299 BuildMI(FirstMBB, MBBI, TII.get(PPC::MFLR8), GlobalBaseReg);
302 return CurDAG->getRegister(GlobalBaseReg, PPCLowering.getPointerTy()).Val;
305 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
306 /// or 64-bit immediate, and if the value can be accurately represented as a
307 /// sign extension from a 16-bit value. If so, this returns true and the
309 static bool isIntS16Immediate(SDNode *N, short &Imm) {
310 if (N->getOpcode() != ISD::Constant)
313 Imm = (short)cast<ConstantSDNode>(N)->getValue();
314 if (N->getValueType(0) == MVT::i32)
315 return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue();
317 return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue();
320 static bool isIntS16Immediate(SDOperand Op, short &Imm) {
321 return isIntS16Immediate(Op.Val, Imm);
325 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
326 /// operand. If so Imm will receive the 32-bit value.
327 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
328 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
329 Imm = cast<ConstantSDNode>(N)->getValue();
335 /// isInt64Immediate - This method tests to see if the node is a 64-bit constant
336 /// operand. If so Imm will receive the 64-bit value.
337 static bool isInt64Immediate(SDNode *N, uint64_t &Imm) {
338 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
339 Imm = cast<ConstantSDNode>(N)->getValue();
345 // isInt32Immediate - This method tests to see if a constant operand.
346 // If so Imm will receive the 32 bit value.
347 static bool isInt32Immediate(SDOperand N, unsigned &Imm) {
348 return isInt32Immediate(N.Val, Imm);
352 // isOpcWithIntImmediate - This method tests to see if the node is a specific
353 // opcode and that it has a immediate integer right operand.
354 // If so Imm will receive the 32 bit value.
355 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
356 return N->getOpcode() == Opc && isInt32Immediate(N->getOperand(1).Val, Imm);
359 bool PPCDAGToDAGISel::isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
360 if (isShiftedMask_32(Val)) {
361 // look for the first non-zero bit
362 MB = CountLeadingZeros_32(Val);
363 // look for the first zero bit after the run of ones
364 ME = CountLeadingZeros_32((Val - 1) ^ Val);
367 Val = ~Val; // invert mask
368 if (isShiftedMask_32(Val)) {
369 // effectively look for the first zero bit
370 ME = CountLeadingZeros_32(Val) - 1;
371 // effectively look for the first one bit after the run of zeros
372 MB = CountLeadingZeros_32((Val - 1) ^ Val) + 1;
380 bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask,
381 bool IsShiftMask, unsigned &SH,
382 unsigned &MB, unsigned &ME) {
383 // Don't even go down this path for i64, since different logic will be
384 // necessary for rldicl/rldicr/rldimi.
385 if (N->getValueType(0) != MVT::i32)
389 unsigned Indeterminant = ~0; // bit mask marking indeterminant results
390 unsigned Opcode = N->getOpcode();
391 if (N->getNumOperands() != 2 ||
392 !isInt32Immediate(N->getOperand(1).Val, Shift) || (Shift > 31))
395 if (Opcode == ISD::SHL) {
396 // apply shift left to mask if it comes first
397 if (IsShiftMask) Mask = Mask << Shift;
398 // determine which bits are made indeterminant by shift
399 Indeterminant = ~(0xFFFFFFFFu << Shift);
400 } else if (Opcode == ISD::SRL) {
401 // apply shift right to mask if it comes first
402 if (IsShiftMask) Mask = Mask >> Shift;
403 // determine which bits are made indeterminant by shift
404 Indeterminant = ~(0xFFFFFFFFu >> Shift);
405 // adjust for the left rotate
407 } else if (Opcode == ISD::ROTL) {
413 // if the mask doesn't intersect any Indeterminant bits
414 if (Mask && !(Mask & Indeterminant)) {
416 // make sure the mask is still a mask (wrap arounds may not be)
417 return isRunOfOnes(Mask, MB, ME);
422 /// SelectBitfieldInsert - turn an or of two masked values into
423 /// the rotate left word immediate then mask insert (rlwimi) instruction.
424 SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
425 SDOperand Op0 = N->getOperand(0);
426 SDOperand Op1 = N->getOperand(1);
428 uint64_t LKZ, LKO, RKZ, RKO;
429 TLI.ComputeMaskedBits(Op0, 0xFFFFFFFFULL, LKZ, LKO);
430 TLI.ComputeMaskedBits(Op1, 0xFFFFFFFFULL, RKZ, RKO);
432 unsigned TargetMask = LKZ;
433 unsigned InsertMask = RKZ;
435 if ((TargetMask | InsertMask) == 0xFFFFFFFF) {
436 unsigned Op0Opc = Op0.getOpcode();
437 unsigned Op1Opc = Op1.getOpcode();
438 unsigned Value, SH = 0;
439 TargetMask = ~TargetMask;
440 InsertMask = ~InsertMask;
442 // If the LHS has a foldable shift and the RHS does not, then swap it to the
443 // RHS so that we can fold the shift into the insert.
444 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
445 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
446 Op0.getOperand(0).getOpcode() == ISD::SRL) {
447 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
448 Op1.getOperand(0).getOpcode() != ISD::SRL) {
450 std::swap(Op0Opc, Op1Opc);
451 std::swap(TargetMask, InsertMask);
454 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
455 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
456 Op1.getOperand(0).getOpcode() != ISD::SRL) {
458 std::swap(Op0Opc, Op1Opc);
459 std::swap(TargetMask, InsertMask);
464 if (InsertMask && isRunOfOnes(InsertMask, MB, ME)) {
465 SDOperand Tmp1, Tmp2, Tmp3;
466 bool DisjointMask = (TargetMask ^ InsertMask) == 0xFFFFFFFF;
468 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
469 isInt32Immediate(Op1.getOperand(1), Value)) {
470 Op1 = Op1.getOperand(0);
471 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value;
473 if (Op1Opc == ISD::AND) {
474 unsigned SHOpc = Op1.getOperand(0).getOpcode();
475 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) &&
476 isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) {
477 Op1 = Op1.getOperand(0).getOperand(0);
478 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value;
480 Op1 = Op1.getOperand(0);
484 Tmp3 = (Op0Opc == ISD::AND && DisjointMask) ? Op0.getOperand(0) : Op0;
485 AddToISelQueue(Tmp3);
488 SDOperand Ops[] = { Tmp3, Op1, getI32Imm(SH), getI32Imm(MB),
490 return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Ops, 5);
496 /// SelectCC - Select a comparison of the specified values with the specified
497 /// condition code, returning the CR# of the expression.
498 SDOperand PPCDAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS,
500 // Always select the LHS.
504 if (LHS.getValueType() == MVT::i32) {
506 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
507 if (isInt32Immediate(RHS, Imm)) {
508 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
510 return SDOperand(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, LHS,
511 getI32Imm(Imm & 0xFFFF)), 0);
512 // If this is a 16-bit signed immediate, fold it.
514 return SDOperand(CurDAG->getTargetNode(PPC::CMPWI, MVT::i32, LHS,
515 getI32Imm(Imm & 0xFFFF)), 0);
517 // For non-equality comparisons, the default code would materialize the
518 // constant, then compare against it, like this:
522 // Since we are just comparing for equality, we can emit this instead:
523 // xoris r0,r3,0x1234
524 // cmplwi cr0,r0,0x5678
526 SDOperand Xor(CurDAG->getTargetNode(PPC::XORIS, MVT::i32, LHS,
527 getI32Imm(Imm >> 16)), 0);
528 return SDOperand(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, Xor,
529 getI32Imm(Imm & 0xFFFF)), 0);
532 } else if (ISD::isUnsignedIntSetCC(CC)) {
533 if (isInt32Immediate(RHS, Imm) && isUInt16(Imm))
534 return SDOperand(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, LHS,
535 getI32Imm(Imm & 0xFFFF)), 0);
539 if (isIntS16Immediate(RHS, SImm))
540 return SDOperand(CurDAG->getTargetNode(PPC::CMPWI, MVT::i32, LHS,
541 getI32Imm((int)SImm & 0xFFFF)),
545 } else if (LHS.getValueType() == MVT::i64) {
547 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
548 if (isInt64Immediate(RHS.Val, Imm)) {
549 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
551 return SDOperand(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, LHS,
552 getI32Imm(Imm & 0xFFFF)), 0);
553 // If this is a 16-bit signed immediate, fold it.
555 return SDOperand(CurDAG->getTargetNode(PPC::CMPDI, MVT::i64, LHS,
556 getI32Imm(Imm & 0xFFFF)), 0);
558 // For non-equality comparisons, the default code would materialize the
559 // constant, then compare against it, like this:
563 // Since we are just comparing for equality, we can emit this instead:
564 // xoris r0,r3,0x1234
565 // cmpldi cr0,r0,0x5678
568 SDOperand Xor(CurDAG->getTargetNode(PPC::XORIS8, MVT::i64, LHS,
569 getI64Imm(Imm >> 16)), 0);
570 return SDOperand(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, Xor,
571 getI64Imm(Imm & 0xFFFF)), 0);
575 } else if (ISD::isUnsignedIntSetCC(CC)) {
576 if (isInt64Immediate(RHS.Val, Imm) && isUInt16(Imm))
577 return SDOperand(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, LHS,
578 getI64Imm(Imm & 0xFFFF)), 0);
582 if (isIntS16Immediate(RHS, SImm))
583 return SDOperand(CurDAG->getTargetNode(PPC::CMPDI, MVT::i64, LHS,
584 getI64Imm(SImm & 0xFFFF)),
588 } else if (LHS.getValueType() == MVT::f32) {
591 assert(LHS.getValueType() == MVT::f64 && "Unknown vt!");
595 return SDOperand(CurDAG->getTargetNode(Opc, MVT::i32, LHS, RHS), 0);
598 static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {
600 default: assert(0 && "Unknown condition!"); abort();
601 case ISD::SETOEQ: // FIXME: This is incorrect see PR642.
603 case ISD::SETEQ: return PPC::PRED_EQ;
604 case ISD::SETONE: // FIXME: This is incorrect see PR642.
606 case ISD::SETNE: return PPC::PRED_NE;
607 case ISD::SETOLT: // FIXME: This is incorrect see PR642.
609 case ISD::SETLT: return PPC::PRED_LT;
610 case ISD::SETOLE: // FIXME: This is incorrect see PR642.
612 case ISD::SETLE: return PPC::PRED_LE;
613 case ISD::SETOGT: // FIXME: This is incorrect see PR642.
615 case ISD::SETGT: return PPC::PRED_GT;
616 case ISD::SETOGE: // FIXME: This is incorrect see PR642.
618 case ISD::SETGE: return PPC::PRED_GE;
620 case ISD::SETO: return PPC::PRED_NU;
621 case ISD::SETUO: return PPC::PRED_UN;
625 /// getCRIdxForSetCC - Return the index of the condition register field
626 /// associated with the SetCC condition, and whether or not the field is
627 /// treated as inverted. That is, lt = 0; ge = 0 inverted.
628 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool& Inv) {
630 default: assert(0 && "Unknown condition!"); abort();
631 case ISD::SETOLT: // FIXME: This is incorrect see PR642.
633 case ISD::SETLT: Inv = false; return 0;
634 case ISD::SETOGE: // FIXME: This is incorrect see PR642.
636 case ISD::SETGE: Inv = true; return 0;
637 case ISD::SETOGT: // FIXME: This is incorrect see PR642.
639 case ISD::SETGT: Inv = false; return 1;
640 case ISD::SETOLE: // FIXME: This is incorrect see PR642.
642 case ISD::SETLE: Inv = true; return 1;
643 case ISD::SETOEQ: // FIXME: This is incorrect see PR642.
645 case ISD::SETEQ: Inv = false; return 2;
646 case ISD::SETONE: // FIXME: This is incorrect see PR642.
648 case ISD::SETNE: Inv = true; return 2;
649 case ISD::SETO: Inv = true; return 3;
650 case ISD::SETUO: Inv = false; return 3;
655 SDNode *PPCDAGToDAGISel::SelectSETCC(SDOperand Op) {
658 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
659 if (isInt32Immediate(N->getOperand(1), Imm)) {
660 // We can codegen setcc op, imm very efficiently compared to a brcond.
661 // Check for those cases here.
664 SDOperand Op = N->getOperand(0);
669 Op = SDOperand(CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op), 0);
670 SDOperand Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) };
671 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
675 SDOperand(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
676 Op, getI32Imm(~0U)), 0);
677 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
681 SDOperand Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
682 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
686 SDOperand(CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op), 0);
687 T = SDOperand(CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op), 0);
688 SDOperand Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
689 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
692 } else if (Imm == ~0U) { // setcc op, -1
693 SDOperand Op = N->getOperand(0);
698 Op = SDOperand(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
699 Op, getI32Imm(1)), 0);
700 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
701 SDOperand(CurDAG->getTargetNode(PPC::LI, MVT::i32,
705 Op = SDOperand(CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op), 0);
706 SDNode *AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
708 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDOperand(AD, 0),
709 Op, SDOperand(AD, 1));
712 SDOperand AD = SDOperand(CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op,
714 SDOperand AN = SDOperand(CurDAG->getTargetNode(PPC::AND, MVT::i32, AD,
716 SDOperand Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
717 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
720 SDOperand Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
721 Op = SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0);
722 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op,
730 unsigned Idx = getCRIdxForSetCC(CC, Inv);
731 SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
734 // Force the ccreg into CR7.
735 SDOperand CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
737 SDOperand InFlag(0, 0); // Null incoming flag value.
738 CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), CR7Reg, CCReg,
741 if (TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor())
742 IntCR = SDOperand(CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg,
745 IntCR = SDOperand(CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg), 0);
747 SDOperand Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31),
748 getI32Imm(31), getI32Imm(31) };
750 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
753 SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0);
754 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
759 // Select - Convert the specified operand from a target-independent to a
760 // target-specific node if it hasn't already been changed.
761 SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
763 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
764 N->getOpcode() < PPCISD::FIRST_NUMBER)
765 return NULL; // Already selected.
767 switch (N->getOpcode()) {
770 return SelectSETCC(Op);
771 case PPCISD::GlobalBaseReg:
772 return getGlobalBaseReg();
774 case ISD::FrameIndex: {
775 int FI = cast<FrameIndexSDNode>(N)->getIndex();
776 SDOperand TFI = CurDAG->getTargetFrameIndex(FI, Op.getValueType());
777 unsigned Opc = Op.getValueType() == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
779 return CurDAG->SelectNodeTo(N, Opc, Op.getValueType(), TFI,
781 return CurDAG->getTargetNode(Opc, Op.getValueType(), TFI,
786 SDOperand InFlag = N->getOperand(1);
787 AddToISelQueue(InFlag);
788 // Use MFOCRF if supported.
789 if (TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor())
790 return CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32,
791 N->getOperand(0), InFlag);
793 return CurDAG->getTargetNode(PPC::MFCR, MVT::i32, InFlag);
797 // FIXME: since this depends on the setting of the carry flag from the srawi
798 // we should really be making notes about that for the scheduler.
799 // FIXME: It sure would be nice if we could cheaply recognize the
800 // srl/add/sra pattern the dag combiner will generate for this as
801 // sra/addze rather than having to handle sdiv ourselves. oh well.
803 if (isInt32Immediate(N->getOperand(1), Imm)) {
804 SDOperand N0 = N->getOperand(0);
806 if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
808 CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
809 N0, getI32Imm(Log2_32(Imm)));
810 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
811 SDOperand(Op, 0), SDOperand(Op, 1));
812 } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
814 CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
815 N0, getI32Imm(Log2_32(-Imm)));
817 SDOperand(CurDAG->getTargetNode(PPC::ADDZE, MVT::i32,
818 SDOperand(Op, 0), SDOperand(Op, 1)),
820 return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
824 // Other cases are autogenerated.
829 // Handle preincrement loads.
830 LoadSDNode *LD = cast<LoadSDNode>(Op);
831 MVT::ValueType LoadedVT = LD->getLoadedVT();
833 // Normal loads are handled by code generated from the .td file.
834 if (LD->getAddressingMode() != ISD::PRE_INC)
837 SDOperand Offset = LD->getOffset();
838 if (isa<ConstantSDNode>(Offset) ||
839 Offset.getOpcode() == ISD::TargetGlobalAddress) {
842 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
843 if (LD->getValueType(0) != MVT::i64) {
844 // Handle PPC32 integer and normal FP loads.
845 assert(!isSExt || LoadedVT == MVT::i16 && "Invalid sext update load");
847 default: assert(0 && "Invalid PPC load type!");
848 case MVT::f64: Opcode = PPC::LFDU; break;
849 case MVT::f32: Opcode = PPC::LFSU; break;
850 case MVT::i32: Opcode = PPC::LWZU; break;
851 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
853 case MVT::i8: Opcode = PPC::LBZU; break;
856 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
857 assert(!isSExt || LoadedVT == MVT::i16 && "Invalid sext update load");
859 default: assert(0 && "Invalid PPC load type!");
860 case MVT::i64: Opcode = PPC::LDU; break;
861 case MVT::i32: Opcode = PPC::LWZU8; break;
862 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
864 case MVT::i8: Opcode = PPC::LBZU8; break;
868 SDOperand Chain = LD->getChain();
869 SDOperand Base = LD->getBasePtr();
870 AddToISelQueue(Chain);
871 AddToISelQueue(Base);
872 AddToISelQueue(Offset);
873 SDOperand Ops[] = { Offset, Base, Chain };
875 return CurDAG->getTargetNode(Opcode, MVT::i32, MVT::i32,
878 assert(0 && "R+R preindex loads not supported yet!");
883 unsigned Imm, Imm2, SH, MB, ME;
885 // If this is an and of a value rotated between 0 and 31 bits and then and'd
886 // with a mask, emit rlwinm
887 if (isInt32Immediate(N->getOperand(1), Imm) &&
888 isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB, ME)) {
889 SDOperand Val = N->getOperand(0).getOperand(0);
891 SDOperand Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
892 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
894 // If this is just a masked value where the input is not handled above, and
895 // is not a rotate-left (handled by a pattern in the .td file), emit rlwinm
896 if (isInt32Immediate(N->getOperand(1), Imm) &&
897 isRunOfOnes(Imm, MB, ME) &&
898 N->getOperand(0).getOpcode() != ISD::ROTL) {
899 SDOperand Val = N->getOperand(0);
901 SDOperand Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) };
902 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
904 // AND X, 0 -> 0, not "rlwinm 32".
905 if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) {
906 AddToISelQueue(N->getOperand(1));
907 ReplaceUses(SDOperand(N, 0), N->getOperand(1));
910 // ISD::OR doesn't get all the bitfield insertion fun.
911 // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert
912 if (isInt32Immediate(N->getOperand(1), Imm) &&
913 N->getOperand(0).getOpcode() == ISD::OR &&
914 isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) {
917 if (isRunOfOnes(Imm, MB, ME)) {
918 AddToISelQueue(N->getOperand(0).getOperand(0));
919 AddToISelQueue(N->getOperand(0).getOperand(1));
920 SDOperand Ops[] = { N->getOperand(0).getOperand(0),
921 N->getOperand(0).getOperand(1),
922 getI32Imm(0), getI32Imm(MB),getI32Imm(ME) };
923 return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Ops, 5);
927 // Other cases are autogenerated.
931 if (N->getValueType(0) == MVT::i32)
932 if (SDNode *I = SelectBitfieldInsert(N))
935 // Other cases are autogenerated.
938 unsigned Imm, SH, MB, ME;
939 if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
940 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
941 AddToISelQueue(N->getOperand(0).getOperand(0));
942 SDOperand Ops[] = { N->getOperand(0).getOperand(0),
943 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
944 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
947 // Other cases are autogenerated.
951 unsigned Imm, SH, MB, ME;
952 if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
953 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
954 AddToISelQueue(N->getOperand(0).getOperand(0));
955 SDOperand Ops[] = { N->getOperand(0).getOperand(0),
956 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
957 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
960 // Other cases are autogenerated.
963 case ISD::SELECT_CC: {
964 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
966 // Handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
967 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
968 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
969 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
970 if (N1C->isNullValue() && N3C->isNullValue() &&
971 N2C->getValue() == 1ULL && CC == ISD::SETNE &&
972 // FIXME: Implement this optzn for PPC64.
973 N->getValueType(0) == MVT::i32) {
974 AddToISelQueue(N->getOperand(0));
976 CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
977 N->getOperand(0), getI32Imm(~0U));
978 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
979 SDOperand(Tmp, 0), N->getOperand(0),
983 SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
984 unsigned BROpc = getPredicateForSetCC(CC);
987 if (N->getValueType(0) == MVT::i32)
988 SelectCCOp = PPC::SELECT_CC_I4;
989 else if (N->getValueType(0) == MVT::i64)
990 SelectCCOp = PPC::SELECT_CC_I8;
991 else if (N->getValueType(0) == MVT::f32)
992 SelectCCOp = PPC::SELECT_CC_F4;
993 else if (N->getValueType(0) == MVT::f64)
994 SelectCCOp = PPC::SELECT_CC_F8;
996 SelectCCOp = PPC::SELECT_CC_VRRC;
998 AddToISelQueue(N->getOperand(2));
999 AddToISelQueue(N->getOperand(3));
1000 SDOperand Ops[] = { CCReg, N->getOperand(2), N->getOperand(3),
1002 return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops, 4);
1004 case PPCISD::COND_BRANCH: {
1005 AddToISelQueue(N->getOperand(0)); // Op #0 is the Chain.
1006 // Op #1 is the PPC::PRED_* number.
1008 // Op #3 is the Dest MBB
1009 AddToISelQueue(N->getOperand(4)); // Op #4 is the Flag.
1010 SDOperand Ops[] = { N->getOperand(1), N->getOperand(2), N->getOperand(3),
1011 N->getOperand(0), N->getOperand(4) };
1012 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 5);
1015 AddToISelQueue(N->getOperand(0));
1016 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
1017 SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC);
1018 SDOperand Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode,
1019 N->getOperand(4), N->getOperand(0) };
1020 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 4);
1023 // FIXME: Should custom lower this.
1024 SDOperand Chain = N->getOperand(0);
1025 SDOperand Target = N->getOperand(1);
1026 AddToISelQueue(Chain);
1027 AddToISelQueue(Target);
1028 unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
1029 Chain = SDOperand(CurDAG->getTargetNode(Opc, MVT::Other, Target,
1031 return CurDAG->SelectNodeTo(N, PPC::BCTR, MVT::Other, Chain);
1035 return SelectCode(Op);
1040 /// createPPCISelDag - This pass converts a legalized DAG into a
1041 /// PowerPC-specific DAG, ready for instruction scheduling.
1043 FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) {
1044 return new PPCDAGToDAGISel(TM);