1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCMachineFunctionInfo.h"
16 #include "PPCPredicates.h"
17 #include "PPCTargetMachine.h"
18 #include "PPCPerfectShuffle.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/VectorExtras.h"
21 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/PseudoSourceValue.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CallingConv.h"
30 #include "llvm/Constants.h"
31 #include "llvm/Function.h"
32 #include "llvm/Intrinsics.h"
33 #include "llvm/ParameterAttributes.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Target/TargetOptions.h"
36 #include "llvm/Support/CommandLine.h"
39 static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc",
40 cl::desc("enable preincrement load/store generation on PPC (experimental)"),
43 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
44 : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()),
45 PPCAtomicLabelIndex(0) {
49 // Use _setjmp/_longjmp instead of setjmp/longjmp.
50 setUseUnderscoreSetJmp(true);
51 setUseUnderscoreLongJmp(true);
53 // Set up the register classes.
54 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
55 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
56 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
58 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
59 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
60 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand);
62 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
64 // PowerPC has pre-inc load and store's.
65 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
66 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
67 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
68 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
69 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
70 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
71 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
72 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
73 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
74 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
76 // Shortening conversions involving ppcf128 get expanded (2 regs -> 1 reg)
77 setConvertAction(MVT::ppcf128, MVT::f64, Expand);
78 setConvertAction(MVT::ppcf128, MVT::f32, Expand);
79 // This is used in the ppcf128->int sequence. Note it has different semantics
80 // from FP_ROUND: that rounds to nearest, this rounds to zero.
81 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
83 // PowerPC has no intrinsics for these particular operations
84 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
86 // PowerPC has no SREM/UREM instructions
87 setOperationAction(ISD::SREM, MVT::i32, Expand);
88 setOperationAction(ISD::UREM, MVT::i32, Expand);
89 setOperationAction(ISD::SREM, MVT::i64, Expand);
90 setOperationAction(ISD::UREM, MVT::i64, Expand);
92 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
93 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
94 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
95 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
96 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
97 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
98 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
99 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
100 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
102 // We don't support sin/cos/sqrt/fmod/pow
103 setOperationAction(ISD::FSIN , MVT::f64, Expand);
104 setOperationAction(ISD::FCOS , MVT::f64, Expand);
105 setOperationAction(ISD::FREM , MVT::f64, Expand);
106 setOperationAction(ISD::FPOW , MVT::f64, Expand);
107 setOperationAction(ISD::FSIN , MVT::f32, Expand);
108 setOperationAction(ISD::FCOS , MVT::f32, Expand);
109 setOperationAction(ISD::FREM , MVT::f32, Expand);
110 setOperationAction(ISD::FPOW , MVT::f32, Expand);
112 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
114 // If we're enabling GP optimizations, use hardware square root
115 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
116 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
117 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
120 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
121 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
123 // PowerPC does not have BSWAP, CTPOP or CTTZ
124 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
125 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
126 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
127 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
128 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
129 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
131 // PowerPC does not have ROTR
132 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
134 // PowerPC does not have Select
135 setOperationAction(ISD::SELECT, MVT::i32, Expand);
136 setOperationAction(ISD::SELECT, MVT::i64, Expand);
137 setOperationAction(ISD::SELECT, MVT::f32, Expand);
138 setOperationAction(ISD::SELECT, MVT::f64, Expand);
140 // PowerPC wants to turn select_cc of FP into fsel when possible.
141 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
142 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
144 // PowerPC wants to optimize integer setcc a bit
145 setOperationAction(ISD::SETCC, MVT::i32, Custom);
147 // PowerPC does not have BRCOND which requires SetCC
148 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
150 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
152 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
153 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
155 // PowerPC does not have [U|S]INT_TO_FP
156 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
157 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
159 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
160 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
161 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
162 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
164 // We cannot sextinreg(i1). Expand to shifts.
165 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
167 // Support label based line numbers.
168 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
169 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
171 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
172 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
173 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
174 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
177 // We want to legalize GlobalAddress and ConstantPool nodes into the
178 // appropriate instructions to materialize the address.
179 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
180 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
181 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
182 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
183 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
184 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
185 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
186 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
188 // RET must be custom lowered, to meet ABI requirements
189 setOperationAction(ISD::RET , MVT::Other, Custom);
191 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
192 setOperationAction(ISD::VASTART , MVT::Other, Custom);
194 // VAARG is custom lowered with ELF 32 ABI
195 if (TM.getSubtarget<PPCSubtarget>().isELF32_ABI())
196 setOperationAction(ISD::VAARG, MVT::Other, Custom);
198 setOperationAction(ISD::VAARG, MVT::Other, Expand);
200 // Use the default implementation.
201 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
202 setOperationAction(ISD::VAEND , MVT::Other, Expand);
203 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
204 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
205 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
206 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
208 setOperationAction(ISD::ATOMIC_LAS , MVT::i32 , Custom);
209 setOperationAction(ISD::ATOMIC_LCS , MVT::i32 , Custom);
210 setOperationAction(ISD::ATOMIC_SWAP , MVT::i32 , Custom);
211 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
212 setOperationAction(ISD::ATOMIC_LAS , MVT::i64 , Custom);
213 setOperationAction(ISD::ATOMIC_LCS , MVT::i64 , Custom);
214 setOperationAction(ISD::ATOMIC_SWAP , MVT::i64 , Custom);
217 // We want to custom lower some of our intrinsics.
218 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
220 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
221 // They also have instructions for converting between i64 and fp.
222 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
223 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
224 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
225 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
226 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
228 // FIXME: disable this lowered code. This generates 64-bit register values,
229 // and we don't model the fact that the top part is clobbered by calls. We
230 // need to flag these together so that the value isn't live across a call.
231 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
233 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
234 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
236 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
237 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
240 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
241 // 64-bit PowerPC implementations can support i64 types directly
242 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
243 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
244 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
245 // 64-bit PowerPC wants to expand i128 shifts itself.
246 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
247 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
248 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
250 // 32-bit PowerPC wants to expand i64 shifts itself.
251 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
252 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
253 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
256 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
257 // First set operation action for all vector types to expand. Then we
258 // will selectively turn on ones that can be effectively codegen'd.
259 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
260 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
261 // add/sub are legal for all supported vector VT's.
262 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal);
263 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal);
265 // We promote all shuffles to v16i8.
266 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote);
267 AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8);
269 // We promote all non-typed operations to v4i32.
270 setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote);
271 AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32);
272 setOperationAction(ISD::OR , (MVT::ValueType)VT, Promote);
273 AddPromotedToType (ISD::OR , (MVT::ValueType)VT, MVT::v4i32);
274 setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote);
275 AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32);
276 setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote);
277 AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32);
278 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
279 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32);
280 setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote);
281 AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32);
283 // No other operations are legal.
284 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
285 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
286 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
287 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
288 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
289 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
290 setOperationAction(ISD::FNEG, (MVT::ValueType)VT, Expand);
291 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
292 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
293 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
294 setOperationAction(ISD::UMUL_LOHI, (MVT::ValueType)VT, Expand);
295 setOperationAction(ISD::SMUL_LOHI, (MVT::ValueType)VT, Expand);
296 setOperationAction(ISD::UDIVREM, (MVT::ValueType)VT, Expand);
297 setOperationAction(ISD::SDIVREM, (MVT::ValueType)VT, Expand);
298 setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand);
299 setOperationAction(ISD::FPOW, (MVT::ValueType)VT, Expand);
300 setOperationAction(ISD::CTPOP, (MVT::ValueType)VT, Expand);
301 setOperationAction(ISD::CTLZ, (MVT::ValueType)VT, Expand);
302 setOperationAction(ISD::CTTZ, (MVT::ValueType)VT, Expand);
305 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
306 // with merges, splats, etc.
307 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
309 setOperationAction(ISD::AND , MVT::v4i32, Legal);
310 setOperationAction(ISD::OR , MVT::v4i32, Legal);
311 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
312 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
313 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
314 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
316 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
317 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
318 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
319 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
321 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
322 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
323 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
324 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
326 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
327 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
329 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
330 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
331 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
332 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
335 setShiftAmountType(MVT::i32);
336 setSetCCResultContents(ZeroOrOneSetCCResult);
338 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
339 setStackPointerRegisterToSaveRestore(PPC::X1);
340 setExceptionPointerRegister(PPC::X3);
341 setExceptionSelectorRegister(PPC::X4);
343 setStackPointerRegisterToSaveRestore(PPC::R1);
344 setExceptionPointerRegister(PPC::R3);
345 setExceptionSelectorRegister(PPC::R4);
348 // We have target-specific dag combine patterns for the following nodes:
349 setTargetDAGCombine(ISD::SINT_TO_FP);
350 setTargetDAGCombine(ISD::STORE);
351 setTargetDAGCombine(ISD::BR_CC);
352 setTargetDAGCombine(ISD::BSWAP);
354 // Darwin long double math library functions have $LDBL128 appended.
355 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) {
356 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
357 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
358 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
359 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
360 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
363 computeRegisterProperties();
366 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
367 /// function arguments in the caller parameter area.
368 unsigned PPCTargetLowering::getByValTypeAlignment(const Type *Ty) const {
369 TargetMachine &TM = getTargetMachine();
370 // Darwin passes everything on 4 byte boundary.
371 if (TM.getSubtarget<PPCSubtarget>().isDarwin())
377 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
380 case PPCISD::FSEL: return "PPCISD::FSEL";
381 case PPCISD::FCFID: return "PPCISD::FCFID";
382 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
383 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
384 case PPCISD::STFIWX: return "PPCISD::STFIWX";
385 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
386 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
387 case PPCISD::VPERM: return "PPCISD::VPERM";
388 case PPCISD::Hi: return "PPCISD::Hi";
389 case PPCISD::Lo: return "PPCISD::Lo";
390 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
391 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
392 case PPCISD::SRL: return "PPCISD::SRL";
393 case PPCISD::SRA: return "PPCISD::SRA";
394 case PPCISD::SHL: return "PPCISD::SHL";
395 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
396 case PPCISD::STD_32: return "PPCISD::STD_32";
397 case PPCISD::CALL_ELF: return "PPCISD::CALL_ELF";
398 case PPCISD::CALL_Macho: return "PPCISD::CALL_Macho";
399 case PPCISD::MTCTR: return "PPCISD::MTCTR";
400 case PPCISD::BCTRL_Macho: return "PPCISD::BCTRL_Macho";
401 case PPCISD::BCTRL_ELF: return "PPCISD::BCTRL_ELF";
402 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
403 case PPCISD::MFCR: return "PPCISD::MFCR";
404 case PPCISD::VCMP: return "PPCISD::VCMP";
405 case PPCISD::VCMPo: return "PPCISD::VCMPo";
406 case PPCISD::LBRX: return "PPCISD::LBRX";
407 case PPCISD::STBRX: return "PPCISD::STBRX";
408 case PPCISD::LARX: return "PPCISD::LARX";
409 case PPCISD::STCX: return "PPCISD::STCX";
410 case PPCISD::CMP_UNRESERVE: return "PPCISD::CMP_UNRESERVE";
411 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
412 case PPCISD::MFFS: return "PPCISD::MFFS";
413 case PPCISD::MTFSB0: return "PPCISD::MTFSB0";
414 case PPCISD::MTFSB1: return "PPCISD::MTFSB1";
415 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
416 case PPCISD::MTFSF: return "PPCISD::MTFSF";
417 case PPCISD::TAILCALL: return "PPCISD::TAILCALL";
418 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
424 PPCTargetLowering::getSetCCResultType(const SDOperand &) const {
429 //===----------------------------------------------------------------------===//
430 // Node matching predicates, for use by the tblgen matching code.
431 //===----------------------------------------------------------------------===//
433 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
434 static bool isFloatingPointZero(SDOperand Op) {
435 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
436 return CFP->getValueAPF().isZero();
437 else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
438 // Maybe this has already been legalized into the constant pool?
439 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
440 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
441 return CFP->getValueAPF().isZero();
446 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
447 /// true if Op is undef or if it matches the specified value.
448 static bool isConstantOrUndef(SDOperand Op, unsigned Val) {
449 return Op.getOpcode() == ISD::UNDEF ||
450 cast<ConstantSDNode>(Op)->getValue() == Val;
453 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
454 /// VPKUHUM instruction.
455 bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) {
457 for (unsigned i = 0; i != 16; ++i)
458 if (!isConstantOrUndef(N->getOperand(i), i*2+1))
461 for (unsigned i = 0; i != 8; ++i)
462 if (!isConstantOrUndef(N->getOperand(i), i*2+1) ||
463 !isConstantOrUndef(N->getOperand(i+8), i*2+1))
469 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
470 /// VPKUWUM instruction.
471 bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) {
473 for (unsigned i = 0; i != 16; i += 2)
474 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
475 !isConstantOrUndef(N->getOperand(i+1), i*2+3))
478 for (unsigned i = 0; i != 8; i += 2)
479 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
480 !isConstantOrUndef(N->getOperand(i+1), i*2+3) ||
481 !isConstantOrUndef(N->getOperand(i+8), i*2+2) ||
482 !isConstantOrUndef(N->getOperand(i+9), i*2+3))
488 /// isVMerge - Common function, used to match vmrg* shuffles.
490 static bool isVMerge(SDNode *N, unsigned UnitSize,
491 unsigned LHSStart, unsigned RHSStart) {
492 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
493 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
494 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
495 "Unsupported merge size!");
497 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
498 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
499 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j),
500 LHSStart+j+i*UnitSize) ||
501 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j),
502 RHSStart+j+i*UnitSize))
508 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
509 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
510 bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
512 return isVMerge(N, UnitSize, 8, 24);
513 return isVMerge(N, UnitSize, 8, 8);
516 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
517 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
518 bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
520 return isVMerge(N, UnitSize, 0, 16);
521 return isVMerge(N, UnitSize, 0, 0);
525 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
526 /// amount, otherwise return -1.
527 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
528 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
529 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
530 // Find the first non-undef value in the shuffle mask.
532 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i)
535 if (i == 16) return -1; // all undef.
537 // Otherwise, check to see if the rest of the elements are consequtively
538 // numbered from this value.
539 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue();
540 if (ShiftAmt < i) return -1;
544 // Check the rest of the elements to see if they are consequtive.
545 for (++i; i != 16; ++i)
546 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i))
549 // Check the rest of the elements to see if they are consequtive.
550 for (++i; i != 16; ++i)
551 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15))
558 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
559 /// specifies a splat of a single element that is suitable for input to
560 /// VSPLTB/VSPLTH/VSPLTW.
561 bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) {
562 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
563 N->getNumOperands() == 16 &&
564 (EltSize == 1 || EltSize == 2 || EltSize == 4));
566 // This is a splat operation if each element of the permute is the same, and
567 // if the value doesn't reference the second vector.
568 unsigned ElementBase = 0;
569 SDOperand Elt = N->getOperand(0);
570 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt))
571 ElementBase = EltV->getValue();
573 return false; // FIXME: Handle UNDEF elements too!
575 if (cast<ConstantSDNode>(Elt)->getValue() >= 16)
578 // Check that they are consequtive.
579 for (unsigned i = 1; i != EltSize; ++i) {
580 if (!isa<ConstantSDNode>(N->getOperand(i)) ||
581 cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase)
585 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
586 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
587 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
588 assert(isa<ConstantSDNode>(N->getOperand(i)) &&
589 "Invalid VECTOR_SHUFFLE mask!");
590 for (unsigned j = 0; j != EltSize; ++j)
591 if (N->getOperand(i+j) != N->getOperand(j))
598 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
600 bool PPC::isAllNegativeZeroVector(SDNode *N) {
601 assert(N->getOpcode() == ISD::BUILD_VECTOR);
602 if (PPC::isSplatShuffleMask(N, N->getNumOperands()))
603 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N))
604 return CFP->getValueAPF().isNegZero();
608 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
609 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
610 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
611 assert(isSplatShuffleMask(N, EltSize));
612 return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize;
615 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
616 /// by using a vspltis[bhw] instruction of the specified element size, return
617 /// the constant being splatted. The ByteSize field indicates the number of
618 /// bytes of each element [124] -> [bhw].
619 SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
620 SDOperand OpVal(0, 0);
622 // If ByteSize of the splat is bigger than the element size of the
623 // build_vector, then we have a case where we are checking for a splat where
624 // multiple elements of the buildvector are folded together into a single
625 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
626 unsigned EltSize = 16/N->getNumOperands();
627 if (EltSize < ByteSize) {
628 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
629 SDOperand UniquedVals[4];
630 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
632 // See if all of the elements in the buildvector agree across.
633 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
634 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
635 // If the element isn't a constant, bail fully out.
636 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand();
639 if (UniquedVals[i&(Multiple-1)].Val == 0)
640 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
641 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
642 return SDOperand(); // no match.
645 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
646 // either constant or undef values that are identical for each chunk. See
647 // if these chunks can form into a larger vspltis*.
649 // Check to see if all of the leading entries are either 0 or -1. If
650 // neither, then this won't fit into the immediate field.
651 bool LeadingZero = true;
652 bool LeadingOnes = true;
653 for (unsigned i = 0; i != Multiple-1; ++i) {
654 if (UniquedVals[i].Val == 0) continue; // Must have been undefs.
656 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
657 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
659 // Finally, check the least significant entry.
661 if (UniquedVals[Multiple-1].Val == 0)
662 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
663 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue();
665 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
668 if (UniquedVals[Multiple-1].Val == 0)
669 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
670 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended();
671 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
672 return DAG.getTargetConstant(Val, MVT::i32);
678 // Check to see if this buildvec has a single non-undef value in its elements.
679 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
680 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
682 OpVal = N->getOperand(i);
683 else if (OpVal != N->getOperand(i))
687 if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def.
689 unsigned ValSizeInBytes = 0;
691 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
692 Value = CN->getValue();
693 ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8;
694 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
695 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
696 Value = FloatToBits(CN->getValueAPF().convertToFloat());
700 // If the splat value is larger than the element value, then we can never do
701 // this splat. The only case that we could fit the replicated bits into our
702 // immediate field for would be zero, and we prefer to use vxor for it.
703 if (ValSizeInBytes < ByteSize) return SDOperand();
705 // If the element value is larger than the splat value, cut it in half and
706 // check to see if the two halves are equal. Continue doing this until we
707 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
708 while (ValSizeInBytes > ByteSize) {
709 ValSizeInBytes >>= 1;
711 // If the top half equals the bottom half, we're still ok.
712 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
713 (Value & ((1 << (8*ValSizeInBytes))-1)))
717 // Properly sign extend the value.
718 int ShAmt = (4-ByteSize)*8;
719 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
721 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
722 if (MaskVal == 0) return SDOperand();
724 // Finally, if this value fits in a 5 bit sext field, return it
725 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
726 return DAG.getTargetConstant(MaskVal, MVT::i32);
730 //===----------------------------------------------------------------------===//
731 // Addressing Mode Selection
732 //===----------------------------------------------------------------------===//
734 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
735 /// or 64-bit immediate, and if the value can be accurately represented as a
736 /// sign extension from a 16-bit value. If so, this returns true and the
738 static bool isIntS16Immediate(SDNode *N, short &Imm) {
739 if (N->getOpcode() != ISD::Constant)
742 Imm = (short)cast<ConstantSDNode>(N)->getValue();
743 if (N->getValueType(0) == MVT::i32)
744 return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue();
746 return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue();
748 static bool isIntS16Immediate(SDOperand Op, short &Imm) {
749 return isIntS16Immediate(Op.Val, Imm);
753 /// SelectAddressRegReg - Given the specified addressed, check to see if it
754 /// can be represented as an indexed [r+r] operation. Returns false if it
755 /// can be more efficiently represented with [r+imm].
756 bool PPCTargetLowering::SelectAddressRegReg(SDOperand N, SDOperand &Base,
760 if (N.getOpcode() == ISD::ADD) {
761 if (isIntS16Immediate(N.getOperand(1), imm))
763 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
766 Base = N.getOperand(0);
767 Index = N.getOperand(1);
769 } else if (N.getOpcode() == ISD::OR) {
770 if (isIntS16Immediate(N.getOperand(1), imm))
771 return false; // r+i can fold it if we can.
773 // If this is an or of disjoint bitfields, we can codegen this as an add
774 // (for better address arithmetic) if the LHS and RHS of the OR are provably
776 APInt LHSKnownZero, LHSKnownOne;
777 APInt RHSKnownZero, RHSKnownOne;
778 DAG.ComputeMaskedBits(N.getOperand(0),
779 APInt::getAllOnesValue(N.getOperand(0)
780 .getValueSizeInBits()),
781 LHSKnownZero, LHSKnownOne);
783 if (LHSKnownZero.getBoolValue()) {
784 DAG.ComputeMaskedBits(N.getOperand(1),
785 APInt::getAllOnesValue(N.getOperand(1)
786 .getValueSizeInBits()),
787 RHSKnownZero, RHSKnownOne);
788 // If all of the bits are known zero on the LHS or RHS, the add won't
790 if (~(LHSKnownZero | RHSKnownZero) == 0) {
791 Base = N.getOperand(0);
792 Index = N.getOperand(1);
801 /// Returns true if the address N can be represented by a base register plus
802 /// a signed 16-bit displacement [r+imm], and if it is not better
803 /// represented as reg+reg.
804 bool PPCTargetLowering::SelectAddressRegImm(SDOperand N, SDOperand &Disp,
805 SDOperand &Base, SelectionDAG &DAG){
806 // If this can be more profitably realized as r+r, fail.
807 if (SelectAddressRegReg(N, Disp, Base, DAG))
810 if (N.getOpcode() == ISD::ADD) {
812 if (isIntS16Immediate(N.getOperand(1), imm)) {
813 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
814 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
815 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
817 Base = N.getOperand(0);
819 return true; // [r+i]
820 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
821 // Match LOAD (ADD (X, Lo(G))).
822 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
823 && "Cannot handle constant offsets yet!");
824 Disp = N.getOperand(1).getOperand(0); // The global address.
825 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
826 Disp.getOpcode() == ISD::TargetConstantPool ||
827 Disp.getOpcode() == ISD::TargetJumpTable);
828 Base = N.getOperand(0);
829 return true; // [&g+r]
831 } else if (N.getOpcode() == ISD::OR) {
833 if (isIntS16Immediate(N.getOperand(1), imm)) {
834 // If this is an or of disjoint bitfields, we can codegen this as an add
835 // (for better address arithmetic) if the LHS and RHS of the OR are
836 // provably disjoint.
837 APInt LHSKnownZero, LHSKnownOne;
838 DAG.ComputeMaskedBits(N.getOperand(0),
839 APInt::getAllOnesValue(N.getOperand(0)
840 .getValueSizeInBits()),
841 LHSKnownZero, LHSKnownOne);
843 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
844 // If all of the bits are known zero on the LHS or RHS, the add won't
846 Base = N.getOperand(0);
847 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
851 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
852 // Loading from a constant address.
854 // If this address fits entirely in a 16-bit sext immediate field, codegen
857 if (isIntS16Immediate(CN, Imm)) {
858 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
859 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
863 // Handle 32-bit sext immediates with LIS + addr mode.
864 if (CN->getValueType(0) == MVT::i32 ||
865 (int64_t)CN->getValue() == (int)CN->getValue()) {
866 int Addr = (int)CN->getValue();
868 // Otherwise, break this down into an LIS + disp.
869 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
871 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
872 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
873 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
878 Disp = DAG.getTargetConstant(0, getPointerTy());
879 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
880 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
883 return true; // [r+0]
886 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
887 /// represented as an indexed [r+r] operation.
888 bool PPCTargetLowering::SelectAddressRegRegOnly(SDOperand N, SDOperand &Base,
891 // Check to see if we can easily represent this as an [r+r] address. This
892 // will fail if it thinks that the address is more profitably represented as
893 // reg+imm, e.g. where imm = 0.
894 if (SelectAddressRegReg(N, Base, Index, DAG))
897 // If the operand is an addition, always emit this as [r+r], since this is
898 // better (for code size, and execution, as the memop does the add for free)
899 // than emitting an explicit add.
900 if (N.getOpcode() == ISD::ADD) {
901 Base = N.getOperand(0);
902 Index = N.getOperand(1);
906 // Otherwise, do it the hard way, using R0 as the base register.
907 Base = DAG.getRegister(PPC::R0, N.getValueType());
912 /// SelectAddressRegImmShift - Returns true if the address N can be
913 /// represented by a base register plus a signed 14-bit displacement
914 /// [r+imm*4]. Suitable for use by STD and friends.
915 bool PPCTargetLowering::SelectAddressRegImmShift(SDOperand N, SDOperand &Disp,
918 // If this can be more profitably realized as r+r, fail.
919 if (SelectAddressRegReg(N, Disp, Base, DAG))
922 if (N.getOpcode() == ISD::ADD) {
924 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
925 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
926 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
927 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
929 Base = N.getOperand(0);
931 return true; // [r+i]
932 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
933 // Match LOAD (ADD (X, Lo(G))).
934 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
935 && "Cannot handle constant offsets yet!");
936 Disp = N.getOperand(1).getOperand(0); // The global address.
937 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
938 Disp.getOpcode() == ISD::TargetConstantPool ||
939 Disp.getOpcode() == ISD::TargetJumpTable);
940 Base = N.getOperand(0);
941 return true; // [&g+r]
943 } else if (N.getOpcode() == ISD::OR) {
945 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
946 // If this is an or of disjoint bitfields, we can codegen this as an add
947 // (for better address arithmetic) if the LHS and RHS of the OR are
948 // provably disjoint.
949 APInt LHSKnownZero, LHSKnownOne;
950 DAG.ComputeMaskedBits(N.getOperand(0),
951 APInt::getAllOnesValue(N.getOperand(0)
952 .getValueSizeInBits()),
953 LHSKnownZero, LHSKnownOne);
954 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
955 // If all of the bits are known zero on the LHS or RHS, the add won't
957 Base = N.getOperand(0);
958 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
962 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
963 // Loading from a constant address. Verify low two bits are clear.
964 if ((CN->getValue() & 3) == 0) {
965 // If this address fits entirely in a 14-bit sext immediate field, codegen
968 if (isIntS16Immediate(CN, Imm)) {
969 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
970 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
974 // Fold the low-part of 32-bit absolute addresses into addr mode.
975 if (CN->getValueType(0) == MVT::i32 ||
976 (int64_t)CN->getValue() == (int)CN->getValue()) {
977 int Addr = (int)CN->getValue();
979 // Otherwise, break this down into an LIS + disp.
980 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
982 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
983 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
984 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
990 Disp = DAG.getTargetConstant(0, getPointerTy());
991 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
992 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
995 return true; // [r+0]
999 /// getPreIndexedAddressParts - returns true by value, base pointer and
1000 /// offset pointer and addressing mode by reference if the node's address
1001 /// can be legally represented as pre-indexed load / store address.
1002 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
1004 ISD::MemIndexedMode &AM,
1005 SelectionDAG &DAG) {
1006 // Disabled by default for now.
1007 if (!EnablePPCPreinc) return false;
1011 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1012 Ptr = LD->getBasePtr();
1013 VT = LD->getMemoryVT();
1015 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1017 Ptr = ST->getBasePtr();
1018 VT = ST->getMemoryVT();
1022 // PowerPC doesn't have preinc load/store instructions for vectors.
1023 if (MVT::isVector(VT))
1026 // TODO: Check reg+reg first.
1028 // LDU/STU use reg+imm*4, others use reg+imm.
1029 if (VT != MVT::i64) {
1031 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
1035 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
1039 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1040 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1041 // sext i32 to i64 when addr mode is r+i.
1042 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1043 LD->getExtensionType() == ISD::SEXTLOAD &&
1044 isa<ConstantSDNode>(Offset))
1052 //===----------------------------------------------------------------------===//
1053 // LowerOperation implementation
1054 //===----------------------------------------------------------------------===//
1056 SDOperand PPCTargetLowering::LowerConstantPool(SDOperand Op,
1057 SelectionDAG &DAG) {
1058 MVT::ValueType PtrVT = Op.getValueType();
1059 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1060 Constant *C = CP->getConstVal();
1061 SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
1062 SDOperand Zero = DAG.getConstant(0, PtrVT);
1064 const TargetMachine &TM = DAG.getTarget();
1066 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero);
1067 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero);
1069 // If this is a non-darwin platform, we don't support non-static relo models
1071 if (TM.getRelocationModel() == Reloc::Static ||
1072 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1073 // Generate non-pic code that has direct accesses to the constant pool.
1074 // The address of the global is just (hi(&g)+lo(&g)).
1075 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1078 if (TM.getRelocationModel() == Reloc::PIC_) {
1079 // With PIC, the first instruction is actually "GR+hi(&G)".
1080 Hi = DAG.getNode(ISD::ADD, PtrVT,
1081 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1084 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1088 SDOperand PPCTargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
1089 MVT::ValueType PtrVT = Op.getValueType();
1090 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1091 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1092 SDOperand Zero = DAG.getConstant(0, PtrVT);
1094 const TargetMachine &TM = DAG.getTarget();
1096 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero);
1097 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero);
1099 // If this is a non-darwin platform, we don't support non-static relo models
1101 if (TM.getRelocationModel() == Reloc::Static ||
1102 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1103 // Generate non-pic code that has direct accesses to the constant pool.
1104 // The address of the global is just (hi(&g)+lo(&g)).
1105 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1108 if (TM.getRelocationModel() == Reloc::PIC_) {
1109 // With PIC, the first instruction is actually "GR+hi(&G)".
1110 Hi = DAG.getNode(ISD::ADD, PtrVT,
1111 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1114 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1118 SDOperand PPCTargetLowering::LowerGlobalTLSAddress(SDOperand Op,
1119 SelectionDAG &DAG) {
1120 assert(0 && "TLS not implemented for PPC.");
1121 return SDOperand(); // Not reached
1124 SDOperand PPCTargetLowering::LowerGlobalAddress(SDOperand Op,
1125 SelectionDAG &DAG) {
1126 MVT::ValueType PtrVT = Op.getValueType();
1127 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1128 GlobalValue *GV = GSDN->getGlobal();
1129 SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
1130 // If it's a debug information descriptor, don't mess with it.
1131 if (DAG.isVerifiedDebugInfoDesc(Op))
1133 SDOperand Zero = DAG.getConstant(0, PtrVT);
1135 const TargetMachine &TM = DAG.getTarget();
1137 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero);
1138 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero);
1140 // If this is a non-darwin platform, we don't support non-static relo models
1142 if (TM.getRelocationModel() == Reloc::Static ||
1143 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1144 // Generate non-pic code that has direct accesses to globals.
1145 // The address of the global is just (hi(&g)+lo(&g)).
1146 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1149 if (TM.getRelocationModel() == Reloc::PIC_) {
1150 // With PIC, the first instruction is actually "GR+hi(&G)".
1151 Hi = DAG.getNode(ISD::ADD, PtrVT,
1152 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1155 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1157 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV))
1160 // If the global is weak or external, we have to go through the lazy
1162 return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0);
1165 SDOperand PPCTargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
1166 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1168 // If we're comparing for equality to zero, expose the fact that this is
1169 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1170 // fold the new nodes.
1171 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1172 if (C->isNullValue() && CC == ISD::SETEQ) {
1173 MVT::ValueType VT = Op.getOperand(0).getValueType();
1174 SDOperand Zext = Op.getOperand(0);
1175 if (VT < MVT::i32) {
1177 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0));
1179 unsigned Log2b = Log2_32(MVT::getSizeInBits(VT));
1180 SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext);
1181 SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz,
1182 DAG.getConstant(Log2b, MVT::i32));
1183 return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc);
1185 // Leave comparisons against 0 and -1 alone for now, since they're usually
1186 // optimized. FIXME: revisit this when we can custom lower all setcc
1188 if (C->isAllOnesValue() || C->isNullValue())
1192 // If we have an integer seteq/setne, turn it into a compare against zero
1193 // by xor'ing the rhs with the lhs, which is faster than setting a
1194 // condition register, reading it back out, and masking the correct bit. The
1195 // normal approach here uses sub to do this instead of xor. Using xor exposes
1196 // the result to other bit-twiddling opportunities.
1197 MVT::ValueType LHSVT = Op.getOperand(0).getValueType();
1198 if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1199 MVT::ValueType VT = Op.getValueType();
1200 SDOperand Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0),
1202 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC);
1207 SDOperand PPCTargetLowering::LowerVAARG(SDOperand Op, SelectionDAG &DAG,
1208 int VarArgsFrameIndex,
1209 int VarArgsStackOffset,
1210 unsigned VarArgsNumGPR,
1211 unsigned VarArgsNumFPR,
1212 const PPCSubtarget &Subtarget) {
1214 assert(0 && "VAARG in ELF32 ABI not implemented yet!");
1215 return SDOperand(); // Not reached
1218 SDOperand PPCTargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG,
1219 int VarArgsFrameIndex,
1220 int VarArgsStackOffset,
1221 unsigned VarArgsNumGPR,
1222 unsigned VarArgsNumFPR,
1223 const PPCSubtarget &Subtarget) {
1225 if (Subtarget.isMachoABI()) {
1226 // vastart just stores the address of the VarArgsFrameIndex slot into the
1227 // memory location argument.
1228 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1229 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1230 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1231 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0);
1234 // For ELF 32 ABI we follow the layout of the va_list struct.
1235 // We suppose the given va_list is already allocated.
1238 // char gpr; /* index into the array of 8 GPRs
1239 // * stored in the register save area
1240 // * gpr=0 corresponds to r3,
1241 // * gpr=1 to r4, etc.
1243 // char fpr; /* index into the array of 8 FPRs
1244 // * stored in the register save area
1245 // * fpr=0 corresponds to f1,
1246 // * fpr=1 to f2, etc.
1248 // char *overflow_arg_area;
1249 // /* location on stack that holds
1250 // * the next overflow argument
1252 // char *reg_save_area;
1253 // /* where r3:r10 and f1:f8 (if saved)
1259 SDOperand ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i8);
1260 SDOperand ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i8);
1263 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1265 SDOperand StackOffsetFI = DAG.getFrameIndex(VarArgsStackOffset, PtrVT);
1266 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1268 uint64_t FrameOffset = MVT::getSizeInBits(PtrVT)/8;
1269 SDOperand ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1271 uint64_t StackOffset = MVT::getSizeInBits(PtrVT)/8 - 1;
1272 SDOperand ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1274 uint64_t FPROffset = 1;
1275 SDOperand ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1277 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1279 // Store first byte : number of int regs
1280 SDOperand firstStore = DAG.getStore(Op.getOperand(0), ArgGPR,
1281 Op.getOperand(1), SV, 0);
1282 uint64_t nextOffset = FPROffset;
1283 SDOperand nextPtr = DAG.getNode(ISD::ADD, PtrVT, Op.getOperand(1),
1286 // Store second byte : number of float regs
1287 SDOperand secondStore =
1288 DAG.getStore(firstStore, ArgFPR, nextPtr, SV, nextOffset);
1289 nextOffset += StackOffset;
1290 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstStackOffset);
1292 // Store second word : arguments given on stack
1293 SDOperand thirdStore =
1294 DAG.getStore(secondStore, StackOffsetFI, nextPtr, SV, nextOffset);
1295 nextOffset += FrameOffset;
1296 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstFrameOffset);
1298 // Store third word : arguments given in registers
1299 return DAG.getStore(thirdStore, FR, nextPtr, SV, nextOffset);
1303 #include "PPCGenCallingConv.inc"
1305 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1306 /// depending on which subtarget is selected.
1307 static const unsigned *GetFPR(const PPCSubtarget &Subtarget) {
1308 if (Subtarget.isMachoABI()) {
1309 static const unsigned FPR[] = {
1310 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1311 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1317 static const unsigned FPR[] = {
1318 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1324 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
1326 static unsigned CalculateStackSlotSize(SDOperand Arg, SDOperand Flag,
1327 bool isVarArg, unsigned PtrByteSize) {
1328 MVT::ValueType ArgVT = Arg.getValueType();
1329 ISD::ArgFlagsTy Flags = cast<ARG_FLAGSSDNode>(Flag)->getArgFlags();
1330 unsigned ArgSize =MVT::getSizeInBits(ArgVT)/8;
1331 if (Flags.isByVal())
1332 ArgSize = Flags.getByValSize();
1333 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1339 PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op,
1341 int &VarArgsFrameIndex,
1342 int &VarArgsStackOffset,
1343 unsigned &VarArgsNumGPR,
1344 unsigned &VarArgsNumFPR,
1345 const PPCSubtarget &Subtarget) {
1346 // TODO: add description of PPC stack frame format, or at least some docs.
1348 MachineFunction &MF = DAG.getMachineFunction();
1349 MachineFrameInfo *MFI = MF.getFrameInfo();
1350 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1351 SmallVector<SDOperand, 8> ArgValues;
1352 SDOperand Root = Op.getOperand(0);
1353 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1355 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1356 bool isPPC64 = PtrVT == MVT::i64;
1357 bool isMachoABI = Subtarget.isMachoABI();
1358 bool isELF32_ABI = Subtarget.isELF32_ABI();
1359 // Potential tail calls could cause overwriting of argument stack slots.
1360 unsigned CC = MF.getFunction()->getCallingConv();
1361 bool isImmutable = !(PerformTailCallOpt && (CC==CallingConv::Fast));
1362 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1364 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1365 // Area that is at least reserved in caller of this function.
1366 unsigned MinReservedArea = ArgOffset;
1368 static const unsigned GPR_32[] = { // 32-bit registers.
1369 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1370 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1372 static const unsigned GPR_64[] = { // 64-bit registers.
1373 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1374 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1377 static const unsigned *FPR = GetFPR(Subtarget);
1379 static const unsigned VR[] = {
1380 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1381 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1384 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
1385 const unsigned Num_FPR_Regs = isMachoABI ? 13 : 8;
1386 const unsigned Num_VR_Regs = array_lengthof( VR);
1388 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1390 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1392 // In 32-bit non-varargs functions, the stack space for vectors is after the
1393 // stack space for non-vectors. We do not use this space unless we have
1394 // too many vectors to fit in registers, something that only occurs in
1395 // constructed examples:), but we have to walk the arglist to figure
1396 // that out...for the pathological case, compute VecArgOffset as the
1397 // start of the vector parameter area. Computing VecArgOffset is the
1398 // entire point of the following loop.
1399 // Altivec is not mentioned in the ppc32 Elf Supplement, so I'm not trying
1400 // to handle Elf here.
1401 unsigned VecArgOffset = ArgOffset;
1402 if (!isVarArg && !isPPC64) {
1403 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e;
1405 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
1406 unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8;
1407 ISD::ArgFlagsTy Flags =
1408 cast<ARG_FLAGSSDNode>(Op.getOperand(ArgNo+3))->getArgFlags();
1410 if (Flags.isByVal()) {
1411 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
1412 ObjSize = Flags.getByValSize();
1414 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1415 VecArgOffset += ArgSize;
1420 default: assert(0 && "Unhandled argument type!");
1423 VecArgOffset += isPPC64 ? 8 : 4;
1425 case MVT::i64: // PPC64
1433 // Nothing to do, we're only looking at Nonvector args here.
1438 // We've found where the vector parameter area in memory is. Skip the
1439 // first 12 parameters; these don't use that memory.
1440 VecArgOffset = ((VecArgOffset+15)/16)*16;
1441 VecArgOffset += 12*16;
1443 // Add DAG nodes to load the arguments or copy them out of registers. On
1444 // entry to a function on PPC, the arguments start after the linkage area,
1445 // although the first ones are often in registers.
1447 // In the ELF 32 ABI, GPRs and stack are double word align: an argument
1448 // represented with two words (long long or double) must be copied to an
1449 // even GPR_idx value or to an even ArgOffset value.
1451 SmallVector<SDOperand, 8> MemOps;
1452 unsigned nAltivecParamsAtEnd = 0;
1453 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
1455 bool needsLoad = false;
1456 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
1457 unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8;
1458 unsigned ArgSize = ObjSize;
1459 ISD::ArgFlagsTy Flags =
1460 cast<ARG_FLAGSSDNode>(Op.getOperand(ArgNo+3))->getArgFlags();
1461 // See if next argument requires stack alignment in ELF
1462 bool Align = Flags.isSplit();
1464 unsigned CurArgOffset = ArgOffset;
1466 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
1467 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
1468 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
1469 if (isVarArg || isPPC64) {
1470 MinReservedArea = ((MinReservedArea+15)/16)*16;
1471 MinReservedArea += CalculateStackSlotSize(Op.getValue(ArgNo),
1472 Op.getOperand(ArgNo+3),
1475 } else nAltivecParamsAtEnd++;
1477 // Calculate min reserved area.
1478 MinReservedArea += CalculateStackSlotSize(Op.getValue(ArgNo),
1479 Op.getOperand(ArgNo+3),
1483 // FIXME alignment for ELF may not be right
1484 // FIXME the codegen can be much improved in some cases.
1485 // We do not have to keep everything in memory.
1486 if (Flags.isByVal()) {
1487 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
1488 ObjSize = Flags.getByValSize();
1489 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1490 // Double word align in ELF
1491 if (Align && isELF32_ABI) GPR_idx += (GPR_idx % 2);
1492 // Objects of size 1 and 2 are right justified, everything else is
1493 // left justified. This means the memory address is adjusted forwards.
1494 if (ObjSize==1 || ObjSize==2) {
1495 CurArgOffset = CurArgOffset + (4 - ObjSize);
1497 // The value of the object is its address.
1498 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset);
1499 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
1500 ArgValues.push_back(FIN);
1501 if (ObjSize==1 || ObjSize==2) {
1502 if (GPR_idx != Num_GPR_Regs) {
1503 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
1504 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1505 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
1506 SDOperand Store = DAG.getTruncStore(Val.getValue(1), Val, FIN,
1507 NULL, 0, ObjSize==1 ? MVT::i8 : MVT::i16 );
1508 MemOps.push_back(Store);
1510 if (isMachoABI) ArgOffset += PtrByteSize;
1512 ArgOffset += PtrByteSize;
1516 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
1517 // Store whatever pieces of the object are in registers
1518 // to memory. ArgVal will be address of the beginning of
1520 if (GPR_idx != Num_GPR_Regs) {
1521 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
1522 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1523 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset);
1524 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
1525 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
1526 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1527 MemOps.push_back(Store);
1529 if (isMachoABI) ArgOffset += PtrByteSize;
1531 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
1539 default: assert(0 && "Unhandled argument type!");
1542 // Double word align in ELF
1543 if (Align && isELF32_ABI) GPR_idx += (GPR_idx % 2);
1545 if (GPR_idx != Num_GPR_Regs) {
1546 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
1547 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1548 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32);
1552 ArgSize = PtrByteSize;
1554 // Stack align in ELF
1555 if (needsLoad && Align && isELF32_ABI)
1556 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1557 // All int arguments reserve stack space in Macho ABI.
1558 if (isMachoABI || needsLoad) ArgOffset += PtrByteSize;
1562 case MVT::i64: // PPC64
1563 if (GPR_idx != Num_GPR_Regs) {
1564 unsigned VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
1565 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1566 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1568 if (ObjectVT == MVT::i32) {
1569 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
1570 // value to MVT::i64 and then truncate to the correct register size.
1572 ArgVal = DAG.getNode(ISD::AssertSext, MVT::i64, ArgVal,
1573 DAG.getValueType(ObjectVT));
1574 else if (Flags.isZExt())
1575 ArgVal = DAG.getNode(ISD::AssertZext, MVT::i64, ArgVal,
1576 DAG.getValueType(ObjectVT));
1578 ArgVal = DAG.getNode(ISD::TRUNCATE, MVT::i32, ArgVal);
1585 // All int arguments reserve stack space in Macho ABI.
1586 if (isMachoABI || needsLoad) ArgOffset += 8;
1591 // Every 4 bytes of argument space consumes one of the GPRs available for
1592 // argument passing.
1593 if (GPR_idx != Num_GPR_Regs && isMachoABI) {
1595 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
1598 if (FPR_idx != Num_FPR_Regs) {
1600 if (ObjectVT == MVT::f32)
1601 VReg = RegInfo.createVirtualRegister(&PPC::F4RCRegClass);
1603 VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
1604 RegInfo.addLiveIn(FPR[FPR_idx], VReg);
1605 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
1611 // Stack align in ELF
1612 if (needsLoad && Align && isELF32_ABI)
1613 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1614 // All FP arguments reserve stack space in Macho ABI.
1615 if (isMachoABI || needsLoad) ArgOffset += isPPC64 ? 8 : ObjSize;
1621 // Note that vector arguments in registers don't reserve stack space,
1622 // except in varargs functions.
1623 if (VR_idx != Num_VR_Regs) {
1624 unsigned VReg = RegInfo.createVirtualRegister(&PPC::VRRCRegClass);
1625 RegInfo.addLiveIn(VR[VR_idx], VReg);
1626 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
1628 while ((ArgOffset % 16) != 0) {
1629 ArgOffset += PtrByteSize;
1630 if (GPR_idx != Num_GPR_Regs)
1634 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs);
1638 if (!isVarArg && !isPPC64) {
1639 // Vectors go after all the nonvectors.
1640 CurArgOffset = VecArgOffset;
1643 // Vectors are aligned.
1644 ArgOffset = ((ArgOffset+15)/16)*16;
1645 CurArgOffset = ArgOffset;
1653 // We need to load the argument to a virtual register if we determined above
1654 // that we ran out of physical registers of the appropriate type.
1656 int FI = MFI->CreateFixedObject(ObjSize,
1657 CurArgOffset + (ArgSize - ObjSize),
1659 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
1660 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
1663 ArgValues.push_back(ArgVal);
1666 // Set the size that is at least reserved in caller of this function. Tail
1667 // call optimized function's reserved stack space needs to be aligned so that
1668 // taking the difference between two stack areas will result in an aligned
1670 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1671 // Add the Altivec parameters at the end, if needed.
1672 if (nAltivecParamsAtEnd) {
1673 MinReservedArea = ((MinReservedArea+15)/16)*16;
1674 MinReservedArea += 16*nAltivecParamsAtEnd;
1677 std::max(MinReservedArea,
1678 PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI));
1679 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
1680 getStackAlignment();
1681 unsigned AlignMask = TargetAlign-1;
1682 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
1683 FI->setMinReservedArea(MinReservedArea);
1685 // If the function takes variable number of arguments, make a frame index for
1686 // the start of the first vararg value... for expansion of llvm.va_start.
1691 VarArgsNumGPR = GPR_idx;
1692 VarArgsNumFPR = FPR_idx;
1694 // Make room for Num_GPR_Regs, Num_FPR_Regs and for a possible frame
1696 depth = -(Num_GPR_Regs * MVT::getSizeInBits(PtrVT)/8 +
1697 Num_FPR_Regs * MVT::getSizeInBits(MVT::f64)/8 +
1698 MVT::getSizeInBits(PtrVT)/8);
1700 VarArgsStackOffset = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8,
1707 VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8,
1709 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1711 // In ELF 32 ABI, the fixed integer arguments of a variadic function are
1712 // stored to the VarArgsFrameIndex on the stack.
1714 for (GPR_idx = 0; GPR_idx != VarArgsNumGPR; ++GPR_idx) {
1715 SDOperand Val = DAG.getRegister(GPR[GPR_idx], PtrVT);
1716 SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0);
1717 MemOps.push_back(Store);
1718 // Increment the address by four for the next argument to store
1719 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT);
1720 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1724 // If this function is vararg, store any remaining integer argument regs
1725 // to their spots on the stack so that they may be loaded by deferencing the
1726 // result of va_next.
1727 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
1730 VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
1732 VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
1734 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1735 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
1736 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1737 MemOps.push_back(Store);
1738 // Increment the address by four for the next argument to store
1739 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT);
1740 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1743 // In ELF 32 ABI, the double arguments are stored to the VarArgsFrameIndex
1746 for (FPR_idx = 0; FPR_idx != VarArgsNumFPR; ++FPR_idx) {
1747 SDOperand Val = DAG.getRegister(FPR[FPR_idx], MVT::f64);
1748 SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0);
1749 MemOps.push_back(Store);
1750 // Increment the address by eight for the next argument to store
1751 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8,
1753 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1756 for (; FPR_idx != Num_FPR_Regs; ++FPR_idx) {
1758 VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
1760 RegInfo.addLiveIn(FPR[FPR_idx], VReg);
1761 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::f64);
1762 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1763 MemOps.push_back(Store);
1764 // Increment the address by eight for the next argument to store
1765 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8,
1767 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1772 if (!MemOps.empty())
1773 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size());
1775 ArgValues.push_back(Root);
1777 // Return the new list of results.
1778 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
1779 Op.Val->value_end());
1780 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
1783 /// CalculateParameterAndLinkageAreaSize - Get the size of the paramter plus
1786 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
1792 unsigned &nAltivecParamsAtEnd) {
1793 // Count how many bytes are to be pushed on the stack, including the linkage
1794 // area, and parameter passing area. We start with 24/48 bytes, which is
1795 // prereserved space for [SP][CR][LR][3 x unused].
1796 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1797 unsigned NumOps = (Call.getNumOperands() - 5) / 2;
1798 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1800 // Add up all the space actually used.
1801 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
1802 // they all go in registers, but we must reserve stack space for them for
1803 // possible use by the caller. In varargs or 64-bit calls, parameters are
1804 // assigned stack space in order, with padding so Altivec parameters are
1806 nAltivecParamsAtEnd = 0;
1807 for (unsigned i = 0; i != NumOps; ++i) {
1808 SDOperand Arg = Call.getOperand(5+2*i);
1809 SDOperand Flag = Call.getOperand(5+2*i+1);
1810 MVT::ValueType ArgVT = Arg.getValueType();
1811 // Varargs Altivec parameters are padded to a 16 byte boundary.
1812 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
1813 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
1814 if (!isVarArg && !isPPC64) {
1815 // Non-varargs Altivec parameters go after all the non-Altivec
1816 // parameters; handle those later so we know how much padding we need.
1817 nAltivecParamsAtEnd++;
1820 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
1821 NumBytes = ((NumBytes+15)/16)*16;
1823 NumBytes += CalculateStackSlotSize(Arg, Flag, isVarArg, PtrByteSize);
1826 // Allow for Altivec parameters at the end, if needed.
1827 if (nAltivecParamsAtEnd) {
1828 NumBytes = ((NumBytes+15)/16)*16;
1829 NumBytes += 16*nAltivecParamsAtEnd;
1832 // The prolog code of the callee may store up to 8 GPR argument registers to
1833 // the stack, allowing va_start to index over them in memory if its varargs.
1834 // Because we cannot tell if this is needed on the caller side, we have to
1835 // conservatively assume that it is needed. As such, make sure we have at
1836 // least enough stack space for the caller to store the 8 GPRs.
1837 NumBytes = std::max(NumBytes,
1838 PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI));
1840 // Tail call needs the stack to be aligned.
1841 if (CC==CallingConv::Fast && PerformTailCallOpt) {
1842 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
1843 getStackAlignment();
1844 unsigned AlignMask = TargetAlign-1;
1845 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
1851 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
1852 /// adjusted to accomodate the arguments for the tailcall.
1853 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool IsTailCall,
1854 unsigned ParamSize) {
1856 if (!IsTailCall) return 0;
1858 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
1859 unsigned CallerMinReservedArea = FI->getMinReservedArea();
1860 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
1861 // Remember only if the new adjustement is bigger.
1862 if (SPDiff < FI->getTailCallSPDelta())
1863 FI->setTailCallSPDelta(SPDiff);
1868 /// IsEligibleForTailCallElimination - Check to see whether the next instruction
1869 /// following the call is a return. A function is eligible if caller/callee
1870 /// calling conventions match, currently only fastcc supports tail calls, and
1871 /// the function CALL is immediatly followed by a RET.
1873 PPCTargetLowering::IsEligibleForTailCallOptimization(SDOperand Call,
1875 SelectionDAG& DAG) const {
1876 // Variable argument functions are not supported.
1877 if (!PerformTailCallOpt ||
1878 cast<ConstantSDNode>(Call.getOperand(2))->getValue() != 0) return false;
1880 if (CheckTailCallReturnConstraints(Call, Ret)) {
1881 MachineFunction &MF = DAG.getMachineFunction();
1882 unsigned CallerCC = MF.getFunction()->getCallingConv();
1883 unsigned CalleeCC = cast<ConstantSDNode>(Call.getOperand(1))->getValue();
1884 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
1885 // Functions containing by val parameters are not supported.
1886 for (unsigned i = 0; i != ((Call.getNumOperands()-5)/2); i++) {
1887 ISD::ArgFlagsTy Flags = cast<ARG_FLAGSSDNode>(Call.getOperand(5+2*i+1))
1889 if (Flags.isByVal()) return false;
1892 SDOperand Callee = Call.getOperand(4);
1893 // Non PIC/GOT tail calls are supported.
1894 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
1897 // At the moment we can only do local tail calls (in same module, hidden
1898 // or protected) if we are generating PIC.
1899 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1900 return G->getGlobal()->hasHiddenVisibility()
1901 || G->getGlobal()->hasProtectedVisibility();
1908 /// isCallCompatibleAddress - Return the immediate to use if the specified
1909 /// 32-bit value is representable in the immediate field of a BxA instruction.
1910 static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) {
1911 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
1914 int Addr = C->getValue();
1915 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
1916 (Addr << 6 >> 6) != Addr)
1917 return 0; // Top 6 bits have to be sext of immediate.
1919 return DAG.getConstant((int)C->getValue() >> 2,
1920 DAG.getTargetLoweringInfo().getPointerTy()).Val;
1925 struct TailCallArgumentInfo {
1927 SDOperand FrameIdxOp;
1930 TailCallArgumentInfo() : FrameIdx(0) {}
1935 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
1937 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
1939 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs,
1940 SmallVector<SDOperand, 8> &MemOpChains) {
1941 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
1942 SDOperand Arg = TailCallArgs[i].Arg;
1943 SDOperand FIN = TailCallArgs[i].FrameIdxOp;
1944 int FI = TailCallArgs[i].FrameIdx;
1945 // Store relative to framepointer.
1946 MemOpChains.push_back(DAG.getStore(Chain, Arg, FIN,
1947 PseudoSourceValue::getFixedStack(),
1952 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
1953 /// the appropriate stack slot for the tail call optimized function call.
1954 static SDOperand EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
1955 MachineFunction &MF,
1957 SDOperand OldRetAddr,
1963 // Calculate the new stack slot for the return address.
1964 int SlotSize = isPPC64 ? 8 : 4;
1965 int NewRetAddrLoc = SPDiff + PPCFrameInfo::getReturnSaveOffset(isPPC64,
1967 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
1969 int NewFPLoc = SPDiff + PPCFrameInfo::getFramePointerSaveOffset(isPPC64,
1971 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc);
1973 MVT::ValueType VT = isPPC64 ? MVT::i64 : MVT::i32;
1974 SDOperand NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
1975 Chain = DAG.getStore(Chain, OldRetAddr, NewRetAddrFrIdx,
1976 PseudoSourceValue::getFixedStack(), NewRetAddr);
1977 SDOperand NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
1978 Chain = DAG.getStore(Chain, OldFP, NewFramePtrIdx,
1979 PseudoSourceValue::getFixedStack(), NewFPIdx);
1984 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
1985 /// the position of the argument.
1987 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
1988 SDOperand Arg, int SPDiff, unsigned ArgOffset,
1989 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
1990 int Offset = ArgOffset + SPDiff;
1991 uint32_t OpSize = (MVT::getSizeInBits(Arg.getValueType())+7)/8;
1992 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
1993 MVT::ValueType VT = isPPC64 ? MVT::i64 : MVT::i32;
1994 SDOperand FIN = DAG.getFrameIndex(FI, VT);
1995 TailCallArgumentInfo Info;
1997 Info.FrameIdxOp = FIN;
1999 TailCallArguments.push_back(Info);
2002 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
2003 /// stack slot. Returns the chain as result and the loaded frame pointers in
2004 /// LROpOut/FPOpout. Used when tail calling.
2005 SDOperand PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
2009 SDOperand &FPOpOut) {
2011 // Load the LR and FP stack slot for later adjusting.
2012 MVT::ValueType VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
2013 LROpOut = getReturnAddrFrameIndex(DAG);
2014 LROpOut = DAG.getLoad(VT, Chain, LROpOut, NULL, 0);
2015 Chain = SDOperand(LROpOut.Val, 1);
2016 FPOpOut = getFramePointerFrameIndex(DAG);
2017 FPOpOut = DAG.getLoad(VT, Chain, FPOpOut, NULL, 0);
2018 Chain = SDOperand(FPOpOut.Val, 1);
2023 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2024 /// by "Src" to address "Dst" of size "Size". Alignment information is
2025 /// specified by the specific parameter attribute. The copy will be passed as
2026 /// a byval function parameter.
2027 /// Sometimes what we are copying is the end of a larger object, the part that
2028 /// does not fit in registers.
2030 CreateCopyOfByValArgument(SDOperand Src, SDOperand Dst, SDOperand Chain,
2031 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2033 SDOperand SizeNode = DAG.getConstant(Size, MVT::i32);
2034 return DAG.getMemcpy(Chain, Dst, Src, SizeNode, Flags.getByValAlign(), false,
2038 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
2041 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDOperand Chain,
2042 SDOperand Arg, SDOperand PtrOff, int SPDiff,
2043 unsigned ArgOffset, bool isPPC64, bool isTailCall,
2044 bool isVector, SmallVector<SDOperand, 8> &MemOpChains,
2045 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
2046 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2051 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
2053 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2054 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr,
2055 DAG.getConstant(ArgOffset, PtrVT));
2057 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
2058 // Calculate and remember argument location.
2059 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
2063 SDOperand PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG,
2064 const PPCSubtarget &Subtarget,
2065 TargetMachine &TM) {
2066 SDOperand Chain = Op.getOperand(0);
2067 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
2068 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
2069 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0 &&
2070 CC == CallingConv::Fast && PerformTailCallOpt;
2071 SDOperand Callee = Op.getOperand(4);
2072 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
2074 bool isMachoABI = Subtarget.isMachoABI();
2075 bool isELF32_ABI = Subtarget.isELF32_ABI();
2077 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2078 bool isPPC64 = PtrVT == MVT::i64;
2079 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2081 MachineFunction &MF = DAG.getMachineFunction();
2083 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in
2084 // SelectExpr to use to put the arguments in the appropriate registers.
2085 std::vector<SDOperand> args_to_use;
2087 // Mark this function as potentially containing a function that contains a
2088 // tail call. As a consequence the frame pointer will be used for dynamicalloc
2089 // and restoring the callers stack pointer in this functions epilog. This is
2090 // done because by tail calling the called function might overwrite the value
2091 // in this function's (MF) stack pointer stack slot 0(SP).
2092 if (PerformTailCallOpt && CC==CallingConv::Fast)
2093 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
2095 unsigned nAltivecParamsAtEnd = 0;
2097 // Count how many bytes are to be pushed on the stack, including the linkage
2098 // area, and parameter passing area. We start with 24/48 bytes, which is
2099 // prereserved space for [SP][CR][LR][3 x unused].
2101 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isMachoABI, isVarArg, CC,
2102 Op, nAltivecParamsAtEnd);
2104 // Calculate by how many bytes the stack has to be adjusted in case of tail
2105 // call optimization.
2106 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
2108 // Adjust the stack pointer for the new arguments...
2109 // These operations are automatically eliminated by the prolog/epilog pass
2110 Chain = DAG.getCALLSEQ_START(Chain,
2111 DAG.getConstant(NumBytes, PtrVT));
2112 SDOperand CallSeqStart = Chain;
2114 // Load the return address and frame pointer so it can be move somewhere else
2116 SDOperand LROp, FPOp;
2117 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp);
2119 // Set up a copy of the stack pointer for use loading and storing any
2120 // arguments that may not fit in the registers available for argument
2124 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
2126 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2128 // Figure out which arguments are going to go in registers, and which in
2129 // memory. Also, if this is a vararg function, floating point operations
2130 // must be stored to our stack, and loaded into integer regs as well, if
2131 // any integer regs are available for argument passing.
2132 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
2133 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2135 static const unsigned GPR_32[] = { // 32-bit registers.
2136 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2137 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2139 static const unsigned GPR_64[] = { // 64-bit registers.
2140 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2141 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2143 static const unsigned *FPR = GetFPR(Subtarget);
2145 static const unsigned VR[] = {
2146 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2147 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2149 const unsigned NumGPRs = array_lengthof(GPR_32);
2150 const unsigned NumFPRs = isMachoABI ? 13 : 8;
2151 const unsigned NumVRs = array_lengthof( VR);
2153 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
2155 std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
2156 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
2158 SmallVector<SDOperand, 8> MemOpChains;
2159 for (unsigned i = 0; i != NumOps; ++i) {
2161 SDOperand Arg = Op.getOperand(5+2*i);
2162 ISD::ArgFlagsTy Flags =
2163 cast<ARG_FLAGSSDNode>(Op.getOperand(5+2*i+1))->getArgFlags();
2164 // See if next argument requires stack alignment in ELF
2165 bool Align = Flags.isSplit();
2167 // PtrOff will be used to store the current argument to the stack if a
2168 // register cannot be found for it.
2171 // Stack align in ELF 32
2172 if (isELF32_ABI && Align)
2173 PtrOff = DAG.getConstant(ArgOffset + ((ArgOffset/4) % 2) * PtrByteSize,
2174 StackPtr.getValueType());
2176 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
2178 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff);
2180 // On PPC64, promote integers to 64-bit values.
2181 if (isPPC64 && Arg.getValueType() == MVT::i32) {
2182 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
2183 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
2184 Arg = DAG.getNode(ExtOp, MVT::i64, Arg);
2187 // FIXME Elf untested, what are alignment rules?
2188 // FIXME memcpy is used way more than necessary. Correctness first.
2189 if (Flags.isByVal()) {
2190 unsigned Size = Flags.getByValSize();
2191 if (isELF32_ABI && Align) GPR_idx += (GPR_idx % 2);
2192 if (Size==1 || Size==2) {
2193 // Very small objects are passed right-justified.
2194 // Everything else is passed left-justified.
2195 MVT::ValueType VT = (Size==1) ? MVT::i8 : MVT::i16;
2196 if (GPR_idx != NumGPRs) {
2197 SDOperand Load = DAG.getExtLoad(ISD::EXTLOAD, PtrVT, Chain, Arg,
2199 MemOpChains.push_back(Load.getValue(1));
2200 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
2202 ArgOffset += PtrByteSize;
2204 SDOperand Const = DAG.getConstant(4 - Size, PtrOff.getValueType());
2205 SDOperand AddPtr = DAG.getNode(ISD::ADD, PtrVT, PtrOff, Const);
2206 SDOperand MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr,
2207 CallSeqStart.Val->getOperand(0),
2209 // This must go outside the CALLSEQ_START..END.
2210 SDOperand NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
2211 CallSeqStart.Val->getOperand(1));
2212 DAG.ReplaceAllUsesWith(CallSeqStart.Val, NewCallSeqStart.Val);
2213 Chain = CallSeqStart = NewCallSeqStart;
2214 ArgOffset += PtrByteSize;
2218 // Copy entire object into memory. There are cases where gcc-generated
2219 // code assumes it is there, even if it could be put entirely into
2220 // registers. (This is not what the doc says.)
2221 SDOperand MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
2222 CallSeqStart.Val->getOperand(0),
2224 // This must go outside the CALLSEQ_START..END.
2225 SDOperand NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
2226 CallSeqStart.Val->getOperand(1));
2227 DAG.ReplaceAllUsesWith(CallSeqStart.Val, NewCallSeqStart.Val);
2228 Chain = CallSeqStart = NewCallSeqStart;
2229 // And copy the pieces of it that fit into registers.
2230 for (unsigned j=0; j<Size; j+=PtrByteSize) {
2231 SDOperand Const = DAG.getConstant(j, PtrOff.getValueType());
2232 SDOperand AddArg = DAG.getNode(ISD::ADD, PtrVT, Arg, Const);
2233 if (GPR_idx != NumGPRs) {
2234 SDOperand Load = DAG.getLoad(PtrVT, Chain, AddArg, NULL, 0);
2235 MemOpChains.push_back(Load.getValue(1));
2236 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
2238 ArgOffset += PtrByteSize;
2240 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
2247 switch (Arg.getValueType()) {
2248 default: assert(0 && "Unexpected ValueType for argument!");
2251 // Double word align in ELF
2252 if (isELF32_ABI && Align) GPR_idx += (GPR_idx % 2);
2253 if (GPR_idx != NumGPRs) {
2254 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
2256 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
2257 isPPC64, isTailCall, false, MemOpChains,
2261 if (inMem || isMachoABI) {
2262 // Stack align in ELF
2263 if (isELF32_ABI && Align)
2264 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
2266 ArgOffset += PtrByteSize;
2271 if (FPR_idx != NumFPRs) {
2272 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
2275 SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
2276 MemOpChains.push_back(Store);
2278 // Float varargs are always shadowed in available integer registers
2279 if (GPR_idx != NumGPRs) {
2280 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
2281 MemOpChains.push_back(Load.getValue(1));
2282 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
2285 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
2286 SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType());
2287 PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour);
2288 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
2289 MemOpChains.push_back(Load.getValue(1));
2290 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
2294 // If we have any FPRs remaining, we may also have GPRs remaining.
2295 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
2298 if (GPR_idx != NumGPRs)
2300 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
2301 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
2306 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
2307 isPPC64, isTailCall, false, MemOpChains,
2311 if (inMem || isMachoABI) {
2312 // Stack align in ELF
2313 if (isELF32_ABI && Align)
2314 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
2318 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
2326 // These go aligned on the stack, or in the corresponding R registers
2327 // when within range. The Darwin PPC ABI doc claims they also go in
2328 // V registers; in fact gcc does this only for arguments that are
2329 // prototyped, not for those that match the ... We do it for all
2330 // arguments, seems to work.
2331 while (ArgOffset % 16 !=0) {
2332 ArgOffset += PtrByteSize;
2333 if (GPR_idx != NumGPRs)
2336 // We could elide this store in the case where the object fits
2337 // entirely in R registers. Maybe later.
2338 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr,
2339 DAG.getConstant(ArgOffset, PtrVT));
2340 SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
2341 MemOpChains.push_back(Store);
2342 if (VR_idx != NumVRs) {
2343 SDOperand Load = DAG.getLoad(MVT::v4f32, Store, PtrOff, NULL, 0);
2344 MemOpChains.push_back(Load.getValue(1));
2345 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
2348 for (unsigned i=0; i<16; i+=PtrByteSize) {
2349 if (GPR_idx == NumGPRs)
2351 SDOperand Ix = DAG.getNode(ISD::ADD, PtrVT, PtrOff,
2352 DAG.getConstant(i, PtrVT));
2353 SDOperand Load = DAG.getLoad(PtrVT, Store, Ix, NULL, 0);
2354 MemOpChains.push_back(Load.getValue(1));
2355 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
2360 // Non-varargs Altivec params generally go in registers, but have
2361 // stack space allocated at the end.
2362 if (VR_idx != NumVRs) {
2363 // Doesn't have GPR space allocated.
2364 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
2365 } else if (nAltivecParamsAtEnd==0) {
2366 // We are emitting Altivec params in order.
2367 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
2368 isPPC64, isTailCall, true, MemOpChains,
2375 // If all Altivec parameters fit in registers, as they usually do,
2376 // they get stack space following the non-Altivec parameters. We
2377 // don't track this here because nobody below needs it.
2378 // If there are more Altivec parameters than fit in registers emit
2380 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
2382 // Offset is aligned; skip 1st 12 params which go in V registers.
2383 ArgOffset = ((ArgOffset+15)/16)*16;
2385 for (unsigned i = 0; i != NumOps; ++i) {
2386 SDOperand Arg = Op.getOperand(5+2*i);
2387 MVT::ValueType ArgType = Arg.getValueType();
2388 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
2389 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
2392 // We are emitting Altivec params in order.
2393 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
2394 isPPC64, isTailCall, true, MemOpChains,
2402 if (!MemOpChains.empty())
2403 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
2404 &MemOpChains[0], MemOpChains.size());
2406 // Build a sequence of copy-to-reg nodes chained together with token chain
2407 // and flag operands which copy the outgoing args into the appropriate regs.
2409 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2410 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
2412 InFlag = Chain.getValue(1);
2415 // With the ELF 32 ABI, set CR6 to true if this is a vararg call.
2416 if (isVarArg && isELF32_ABI) {
2417 SDOperand SetCR(DAG.getTargetNode(PPC::CRSET, MVT::i32), 0);
2418 Chain = DAG.getCopyToReg(Chain, PPC::CR1EQ, SetCR, InFlag);
2419 InFlag = Chain.getValue(1);
2422 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
2423 // might overwrite each other in case of tail call optimization.
2425 SmallVector<SDOperand, 8> MemOpChains2;
2426 // Do not flag preceeding copytoreg stuff together with the following stuff.
2427 InFlag = SDOperand();
2428 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
2430 if (!MemOpChains2.empty())
2431 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
2432 &MemOpChains2[0], MemOpChains2.size());
2434 // Store the return address to the appropriate stack slot.
2435 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
2436 isPPC64, isMachoABI);
2439 // Emit callseq_end just before tailcall node.
2441 SmallVector<SDOperand, 8> CallSeqOps;
2442 SDVTList CallSeqNodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
2443 CallSeqOps.push_back(Chain);
2444 CallSeqOps.push_back(DAG.getIntPtrConstant(NumBytes));
2445 CallSeqOps.push_back(DAG.getIntPtrConstant(0));
2447 CallSeqOps.push_back(InFlag);
2448 Chain = DAG.getNode(ISD::CALLSEQ_END, CallSeqNodeTys, &CallSeqOps[0],
2450 InFlag = Chain.getValue(1);
2453 std::vector<MVT::ValueType> NodeTys;
2454 NodeTys.push_back(MVT::Other); // Returns a chain
2455 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
2457 SmallVector<SDOperand, 8> Ops;
2458 unsigned CallOpc = isMachoABI? PPCISD::CALL_Macho : PPCISD::CALL_ELF;
2460 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2461 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2462 // node so that legalize doesn't hack it.
2463 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2464 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
2465 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
2466 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType());
2467 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
2468 // If this is an absolute destination address, use the munged value.
2469 Callee = SDOperand(Dest, 0);
2471 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
2472 // to do the call, we can't use PPCISD::CALL.
2473 SDOperand MTCTROps[] = {Chain, Callee, InFlag};
2474 Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+(InFlag.Val!=0));
2475 InFlag = Chain.getValue(1);
2477 // Copy the callee address into R12/X12 on darwin.
2479 unsigned Reg = Callee.getValueType() == MVT::i32 ? PPC::R12 : PPC::X12;
2480 Chain = DAG.getCopyToReg(Chain, Reg, Callee, InFlag);
2481 InFlag = Chain.getValue(1);
2485 NodeTys.push_back(MVT::Other);
2486 NodeTys.push_back(MVT::Flag);
2487 Ops.push_back(Chain);
2488 CallOpc = isMachoABI ? PPCISD::BCTRL_Macho : PPCISD::BCTRL_ELF;
2490 // Add CTR register as callee so a bctr can be emitted later.
2492 Ops.push_back(DAG.getRegister(PPC::CTR, getPointerTy()));
2495 // If this is a direct call, pass the chain and the callee.
2497 Ops.push_back(Chain);
2498 Ops.push_back(Callee);
2500 // If this is a tail call add stack pointer delta.
2502 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
2504 // Add argument registers to the end of the list so that they are known live
2506 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2507 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2508 RegsToPass[i].second.getValueType()));
2510 // When performing tail call optimization the callee pops its arguments off
2511 // the stack. Account for this here so these bytes can be pushed back on in
2512 // PPCRegisterInfo::eliminateCallFramePseudoInstr.
2513 int BytesCalleePops =
2514 (CC==CallingConv::Fast && PerformTailCallOpt) ? NumBytes : 0;
2517 Ops.push_back(InFlag);
2521 assert(InFlag.Val &&
2522 "Flag must be set. Depend on flag being set in LowerRET");
2523 Chain = DAG.getNode(PPCISD::TAILCALL,
2524 Op.Val->getVTList(), &Ops[0], Ops.size());
2525 return SDOperand(Chain.Val, Op.ResNo);
2528 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
2529 InFlag = Chain.getValue(1);
2531 Chain = DAG.getCALLSEQ_END(Chain,
2532 DAG.getConstant(NumBytes, PtrVT),
2533 DAG.getConstant(BytesCalleePops, PtrVT),
2535 if (Op.Val->getValueType(0) != MVT::Other)
2536 InFlag = Chain.getValue(1);
2538 SmallVector<SDOperand, 16> ResultVals;
2539 SmallVector<CCValAssign, 16> RVLocs;
2540 unsigned CallerCC = DAG.getMachineFunction().getFunction()->getCallingConv();
2541 CCState CCInfo(CallerCC, isVarArg, TM, RVLocs);
2542 CCInfo.AnalyzeCallResult(Op.Val, RetCC_PPC);
2544 // Copy all of the result registers out of their specified physreg.
2545 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2546 CCValAssign &VA = RVLocs[i];
2547 MVT::ValueType VT = VA.getValVT();
2548 assert(VA.isRegLoc() && "Can only return in registers!");
2549 Chain = DAG.getCopyFromReg(Chain, VA.getLocReg(), VT, InFlag).getValue(1);
2550 ResultVals.push_back(Chain.getValue(0));
2551 InFlag = Chain.getValue(2);
2554 // If the function returns void, just return the chain.
2558 // Otherwise, merge everything together with a MERGE_VALUES node.
2559 ResultVals.push_back(Chain);
2560 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
2561 &ResultVals[0], ResultVals.size());
2562 return Res.getValue(Op.ResNo);
2565 SDOperand PPCTargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG,
2566 TargetMachine &TM) {
2567 SmallVector<CCValAssign, 16> RVLocs;
2568 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
2569 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
2570 CCState CCInfo(CC, isVarArg, TM, RVLocs);
2571 CCInfo.AnalyzeReturn(Op.Val, RetCC_PPC);
2573 // If this is the first return lowered for this function, add the regs to the
2574 // liveout set for the function.
2575 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
2576 for (unsigned i = 0; i != RVLocs.size(); ++i)
2577 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
2580 SDOperand Chain = Op.getOperand(0);
2582 Chain = GetPossiblePreceedingTailCall(Chain, PPCISD::TAILCALL);
2583 if (Chain.getOpcode() == PPCISD::TAILCALL) {
2584 SDOperand TailCall = Chain;
2585 SDOperand TargetAddress = TailCall.getOperand(1);
2586 SDOperand StackAdjustment = TailCall.getOperand(2);
2588 assert(((TargetAddress.getOpcode() == ISD::Register &&
2589 cast<RegisterSDNode>(TargetAddress)->getReg() == PPC::CTR) ||
2590 TargetAddress.getOpcode() == ISD::TargetExternalSymbol ||
2591 TargetAddress.getOpcode() == ISD::TargetGlobalAddress ||
2592 isa<ConstantSDNode>(TargetAddress)) &&
2593 "Expecting an global address, external symbol, absolute value or register");
2595 assert(StackAdjustment.getOpcode() == ISD::Constant &&
2596 "Expecting a const value");
2598 SmallVector<SDOperand,8> Operands;
2599 Operands.push_back(Chain.getOperand(0));
2600 Operands.push_back(TargetAddress);
2601 Operands.push_back(StackAdjustment);
2602 // Copy registers used by the call. Last operand is a flag so it is not
2604 for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) {
2605 Operands.push_back(Chain.getOperand(i));
2607 return DAG.getNode(PPCISD::TC_RETURN, MVT::Other, &Operands[0],
2613 // Copy the result values into the output registers.
2614 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2615 CCValAssign &VA = RVLocs[i];
2616 assert(VA.isRegLoc() && "Can only return in registers!");
2617 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
2618 Flag = Chain.getValue(1);
2622 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain, Flag);
2624 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain);
2627 SDOperand PPCTargetLowering::LowerSTACKRESTORE(SDOperand Op, SelectionDAG &DAG,
2628 const PPCSubtarget &Subtarget) {
2629 // When we pop the dynamic allocation we need to restore the SP link.
2631 // Get the corect type for pointers.
2632 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2634 // Construct the stack pointer operand.
2635 bool IsPPC64 = Subtarget.isPPC64();
2636 unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1;
2637 SDOperand StackPtr = DAG.getRegister(SP, PtrVT);
2639 // Get the operands for the STACKRESTORE.
2640 SDOperand Chain = Op.getOperand(0);
2641 SDOperand SaveSP = Op.getOperand(1);
2643 // Load the old link SP.
2644 SDOperand LoadLinkSP = DAG.getLoad(PtrVT, Chain, StackPtr, NULL, 0);
2646 // Restore the stack pointer.
2647 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), SP, SaveSP);
2649 // Store the old link SP.
2650 return DAG.getStore(Chain, LoadLinkSP, StackPtr, NULL, 0);
2656 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
2657 MachineFunction &MF = DAG.getMachineFunction();
2658 bool IsPPC64 = PPCSubTarget.isPPC64();
2659 bool isMachoABI = PPCSubTarget.isMachoABI();
2660 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2662 // Get current frame pointer save index. The users of this index will be
2663 // primarily DYNALLOC instructions.
2664 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2665 int RASI = FI->getReturnAddrSaveIndex();
2667 // If the frame pointer save index hasn't been defined yet.
2669 // Find out what the fix offset of the frame pointer save area.
2670 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, isMachoABI);
2671 // Allocate the frame index for frame pointer save area.
2672 RASI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, LROffset);
2674 FI->setReturnAddrSaveIndex(RASI);
2676 return DAG.getFrameIndex(RASI, PtrVT);
2680 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
2681 MachineFunction &MF = DAG.getMachineFunction();
2682 bool IsPPC64 = PPCSubTarget.isPPC64();
2683 bool isMachoABI = PPCSubTarget.isMachoABI();
2684 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2686 // Get current frame pointer save index. The users of this index will be
2687 // primarily DYNALLOC instructions.
2688 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2689 int FPSI = FI->getFramePointerSaveIndex();
2691 // If the frame pointer save index hasn't been defined yet.
2693 // Find out what the fix offset of the frame pointer save area.
2694 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isMachoABI);
2696 // Allocate the frame index for frame pointer save area.
2697 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
2699 FI->setFramePointerSaveIndex(FPSI);
2701 return DAG.getFrameIndex(FPSI, PtrVT);
2704 SDOperand PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDOperand Op,
2706 const PPCSubtarget &Subtarget) {
2708 SDOperand Chain = Op.getOperand(0);
2709 SDOperand Size = Op.getOperand(1);
2711 // Get the corect type for pointers.
2712 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2714 SDOperand NegSize = DAG.getNode(ISD::SUB, PtrVT,
2715 DAG.getConstant(0, PtrVT), Size);
2716 // Construct a node for the frame pointer save index.
2717 SDOperand FPSIdx = getFramePointerFrameIndex(DAG);
2718 // Build a DYNALLOC node.
2719 SDOperand Ops[3] = { Chain, NegSize, FPSIdx };
2720 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
2721 return DAG.getNode(PPCISD::DYNALLOC, VTs, Ops, 3);
2724 SDOperand PPCTargetLowering::LowerAtomicLAS(SDOperand Op, SelectionDAG &DAG) {
2725 MVT::ValueType VT = Op.Val->getValueType(0);
2726 SDOperand Chain = Op.getOperand(0);
2727 SDOperand Ptr = Op.getOperand(1);
2728 SDOperand Incr = Op.getOperand(2);
2730 // Issue a "load and reserve".
2731 std::vector<MVT::ValueType> VTs;
2733 VTs.push_back(MVT::Other);
2735 SDOperand Label = DAG.getConstant(PPCAtomicLabelIndex++, MVT::i32);
2741 SDOperand Load = DAG.getNode(PPCISD::LARX, VTs, Ops, 3);
2742 Chain = Load.getValue(1);
2744 // Compute new value.
2745 SDOperand NewVal = DAG.getNode(ISD::ADD, VT, Load, Incr);
2747 // Issue a "store and check".
2748 SDOperand Ops2[] = {
2754 SDOperand Store = DAG.getNode(PPCISD::STCX, MVT::Other, Ops2, 4);
2755 SDOperand OutOps[] = { Load, Store };
2756 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
2760 SDOperand PPCTargetLowering::LowerAtomicLCS(SDOperand Op, SelectionDAG &DAG) {
2761 MVT::ValueType VT = Op.Val->getValueType(0);
2762 SDOperand Chain = Op.getOperand(0);
2763 SDOperand Ptr = Op.getOperand(1);
2764 SDOperand NewVal = Op.getOperand(2);
2765 SDOperand OldVal = Op.getOperand(3);
2767 // Issue a "load and reserve".
2768 std::vector<MVT::ValueType> VTs;
2770 VTs.push_back(MVT::Other);
2772 SDOperand Label = DAG.getConstant(PPCAtomicLabelIndex++, MVT::i32);
2778 SDOperand Load = DAG.getNode(PPCISD::LARX, VTs, Ops, 3);
2779 Chain = Load.getValue(1);
2781 // Compare and unreserve if not equal.
2782 SDOperand Ops2[] = {
2784 OldVal, // Old value
2785 Load, // Value in memory
2788 Chain = DAG.getNode(PPCISD::CMP_UNRESERVE, MVT::Other, Ops2, 4);
2790 // Issue a "store and check".
2791 SDOperand Ops3[] = {
2797 SDOperand Store = DAG.getNode(PPCISD::STCX, MVT::Other, Ops3, 4);
2798 SDOperand OutOps[] = { Load, Store };
2799 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
2803 SDOperand PPCTargetLowering::LowerAtomicSWAP(SDOperand Op, SelectionDAG &DAG) {
2804 MVT::ValueType VT = Op.Val->getValueType(0);
2805 SDOperand Chain = Op.getOperand(0);
2806 SDOperand Ptr = Op.getOperand(1);
2807 SDOperand NewVal = Op.getOperand(2);
2809 // Issue a "load and reserve".
2810 std::vector<MVT::ValueType> VTs;
2812 VTs.push_back(MVT::Other);
2814 SDOperand Label = DAG.getConstant(PPCAtomicLabelIndex++, MVT::i32);
2820 SDOperand Load = DAG.getNode(PPCISD::LARX, VTs, Ops, 3);
2821 Chain = Load.getValue(1);
2823 // Issue a "store and check".
2824 SDOperand Ops2[] = {
2830 SDOperand Store = DAG.getNode(PPCISD::STCX, MVT::Other, Ops2, 4);
2831 SDOperand OutOps[] = { Load, Store };
2832 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
2836 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
2838 SDOperand PPCTargetLowering::LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
2839 // Not FP? Not a fsel.
2840 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) ||
2841 !MVT::isFloatingPoint(Op.getOperand(2).getValueType()))
2844 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2846 // Cannot handle SETEQ/SETNE.
2847 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand();
2849 MVT::ValueType ResVT = Op.getValueType();
2850 MVT::ValueType CmpVT = Op.getOperand(0).getValueType();
2851 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2852 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3);
2854 // If the RHS of the comparison is a 0.0, we don't need to do the
2855 // subtraction at all.
2856 if (isFloatingPointZero(RHS))
2858 default: break; // SETUO etc aren't handled by fsel.
2862 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
2866 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
2867 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
2868 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
2872 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
2876 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
2877 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
2878 return DAG.getNode(PPCISD::FSEL, ResVT,
2879 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV);
2884 default: break; // SETUO etc aren't handled by fsel.
2888 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
2889 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2890 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2891 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
2895 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
2896 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2897 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2898 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
2902 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
2903 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2904 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2905 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
2909 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
2910 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2911 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2912 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
2917 // FIXME: Split this code up when LegalizeDAGTypes lands.
2918 SDOperand PPCTargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
2919 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType()));
2920 SDOperand Src = Op.getOperand(0);
2921 if (Src.getValueType() == MVT::f32)
2922 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src);
2925 switch (Op.getValueType()) {
2926 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
2928 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src);
2931 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src);
2935 // Convert the FP value to an int value through memory.
2936 SDOperand FIPtr = DAG.CreateStackTemporary(MVT::f64);
2938 // Emit a store to the stack slot.
2939 SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Tmp, FIPtr, NULL, 0);
2941 // Result is a load from the stack slot. If loading 4 bytes, make sure to
2943 if (Op.getValueType() == MVT::i32)
2944 FIPtr = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr,
2945 DAG.getConstant(4, FIPtr.getValueType()));
2946 return DAG.getLoad(Op.getValueType(), Chain, FIPtr, NULL, 0);
2949 SDOperand PPCTargetLowering::LowerFP_ROUND_INREG(SDOperand Op,
2950 SelectionDAG &DAG) {
2951 assert(Op.getValueType() == MVT::ppcf128);
2952 SDNode *Node = Op.Val;
2953 assert(Node->getOperand(0).getValueType() == MVT::ppcf128);
2954 assert(Node->getOperand(0).Val->getOpcode() == ISD::BUILD_PAIR);
2955 SDOperand Lo = Node->getOperand(0).Val->getOperand(0);
2956 SDOperand Hi = Node->getOperand(0).Val->getOperand(1);
2958 // This sequence changes FPSCR to do round-to-zero, adds the two halves
2959 // of the long double, and puts FPSCR back the way it was. We do not
2960 // actually model FPSCR.
2961 std::vector<MVT::ValueType> NodeTys;
2962 SDOperand Ops[4], Result, MFFSreg, InFlag, FPreg;
2964 NodeTys.push_back(MVT::f64); // Return register
2965 NodeTys.push_back(MVT::Flag); // Returns a flag for later insns
2966 Result = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0);
2967 MFFSreg = Result.getValue(0);
2968 InFlag = Result.getValue(1);
2971 NodeTys.push_back(MVT::Flag); // Returns a flag
2972 Ops[0] = DAG.getConstant(31, MVT::i32);
2974 Result = DAG.getNode(PPCISD::MTFSB1, NodeTys, Ops, 2);
2975 InFlag = Result.getValue(0);
2978 NodeTys.push_back(MVT::Flag); // Returns a flag
2979 Ops[0] = DAG.getConstant(30, MVT::i32);
2981 Result = DAG.getNode(PPCISD::MTFSB0, NodeTys, Ops, 2);
2982 InFlag = Result.getValue(0);
2985 NodeTys.push_back(MVT::f64); // result of add
2986 NodeTys.push_back(MVT::Flag); // Returns a flag
2990 Result = DAG.getNode(PPCISD::FADDRTZ, NodeTys, Ops, 3);
2991 FPreg = Result.getValue(0);
2992 InFlag = Result.getValue(1);
2995 NodeTys.push_back(MVT::f64);
2996 Ops[0] = DAG.getConstant(1, MVT::i32);
3000 Result = DAG.getNode(PPCISD::MTFSF, NodeTys, Ops, 4);
3001 FPreg = Result.getValue(0);
3003 // We know the low half is about to be thrown away, so just use something
3005 return DAG.getNode(ISD::BUILD_PAIR, Lo.getValueType(), FPreg, FPreg);
3008 SDOperand PPCTargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
3009 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
3010 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
3013 if (Op.getOperand(0).getValueType() == MVT::i64) {
3014 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
3015 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
3016 if (Op.getValueType() == MVT::f32)
3017 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0));
3021 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
3022 "Unhandled SINT_TO_FP type in custom expander!");
3023 // Since we only generate this in 64-bit mode, we can take advantage of
3024 // 64-bit registers. In particular, sign extend the input value into the
3025 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
3026 // then lfd it and fcfid it.
3027 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
3028 int FrameIdx = FrameInfo->CreateStackObject(8, 8);
3029 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3030 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
3032 SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32,
3035 // STD the extended value into the stack slot.
3036 MachineMemOperand MO(PseudoSourceValue::getFixedStack(),
3037 MachineMemOperand::MOStore, FrameIdx, 8, 8);
3038 SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other,
3039 DAG.getEntryNode(), Ext64, FIdx,
3040 DAG.getMemOperand(MO));
3041 // Load the value as a double.
3042 SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0);
3044 // FCFID it and return it.
3045 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld);
3046 if (Op.getValueType() == MVT::f32)
3047 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0));
3051 SDOperand PPCTargetLowering::LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG) {
3053 The rounding mode is in bits 30:31 of FPSR, and has the following
3060 FLT_ROUNDS, on the other hand, expects the following:
3067 To perform the conversion, we do:
3068 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
3071 MachineFunction &MF = DAG.getMachineFunction();
3072 MVT::ValueType VT = Op.getValueType();
3073 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3074 std::vector<MVT::ValueType> NodeTys;
3075 SDOperand MFFSreg, InFlag;
3077 // Save FP Control Word to register
3078 NodeTys.push_back(MVT::f64); // return register
3079 NodeTys.push_back(MVT::Flag); // unused in this context
3080 SDOperand Chain = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0);
3082 // Save FP register to stack slot
3083 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
3084 SDOperand StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
3085 SDOperand Store = DAG.getStore(DAG.getEntryNode(), Chain,
3086 StackSlot, NULL, 0);
3088 // Load FP Control Word from low 32 bits of stack slot.
3089 SDOperand Four = DAG.getConstant(4, PtrVT);
3090 SDOperand Addr = DAG.getNode(ISD::ADD, PtrVT, StackSlot, Four);
3091 SDOperand CWD = DAG.getLoad(MVT::i32, Store, Addr, NULL, 0);
3093 // Transform as necessary
3095 DAG.getNode(ISD::AND, MVT::i32,
3096 CWD, DAG.getConstant(3, MVT::i32));
3098 DAG.getNode(ISD::SRL, MVT::i32,
3099 DAG.getNode(ISD::AND, MVT::i32,
3100 DAG.getNode(ISD::XOR, MVT::i32,
3101 CWD, DAG.getConstant(3, MVT::i32)),
3102 DAG.getConstant(3, MVT::i32)),
3103 DAG.getConstant(1, MVT::i8));
3106 DAG.getNode(ISD::XOR, MVT::i32, CWD1, CWD2);
3108 return DAG.getNode((MVT::getSizeInBits(VT) < 16 ?
3109 ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal);
3112 SDOperand PPCTargetLowering::LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) {
3113 MVT::ValueType VT = Op.getValueType();
3114 unsigned BitWidth = MVT::getSizeInBits(VT);
3115 assert(Op.getNumOperands() == 3 &&
3116 VT == Op.getOperand(1).getValueType() &&
3119 // Expand into a bunch of logical ops. Note that these ops
3120 // depend on the PPC behavior for oversized shift amounts.
3121 SDOperand Lo = Op.getOperand(0);
3122 SDOperand Hi = Op.getOperand(1);
3123 SDOperand Amt = Op.getOperand(2);
3124 MVT::ValueType AmtVT = Amt.getValueType();
3126 SDOperand Tmp1 = DAG.getNode(ISD::SUB, AmtVT,
3127 DAG.getConstant(BitWidth, AmtVT), Amt);
3128 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, VT, Hi, Amt);
3129 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, VT, Lo, Tmp1);
3130 SDOperand Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3);
3131 SDOperand Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt,
3132 DAG.getConstant(-BitWidth, AmtVT));
3133 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, VT, Lo, Tmp5);
3134 SDOperand OutHi = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6);
3135 SDOperand OutLo = DAG.getNode(PPCISD::SHL, VT, Lo, Amt);
3136 SDOperand OutOps[] = { OutLo, OutHi };
3137 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, VT),
3141 SDOperand PPCTargetLowering::LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) {
3142 MVT::ValueType VT = Op.getValueType();
3143 unsigned BitWidth = MVT::getSizeInBits(VT);
3144 assert(Op.getNumOperands() == 3 &&
3145 VT == Op.getOperand(1).getValueType() &&
3148 // Expand into a bunch of logical ops. Note that these ops
3149 // depend on the PPC behavior for oversized shift amounts.
3150 SDOperand Lo = Op.getOperand(0);
3151 SDOperand Hi = Op.getOperand(1);
3152 SDOperand Amt = Op.getOperand(2);
3153 MVT::ValueType AmtVT = Amt.getValueType();
3155 SDOperand Tmp1 = DAG.getNode(ISD::SUB, AmtVT,
3156 DAG.getConstant(BitWidth, AmtVT), Amt);
3157 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, VT, Lo, Amt);
3158 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, VT, Hi, Tmp1);
3159 SDOperand Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3);
3160 SDOperand Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt,
3161 DAG.getConstant(-BitWidth, AmtVT));
3162 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, VT, Hi, Tmp5);
3163 SDOperand OutLo = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6);
3164 SDOperand OutHi = DAG.getNode(PPCISD::SRL, VT, Hi, Amt);
3165 SDOperand OutOps[] = { OutLo, OutHi };
3166 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, VT),
3170 SDOperand PPCTargetLowering::LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) {
3171 MVT::ValueType VT = Op.getValueType();
3172 unsigned BitWidth = MVT::getSizeInBits(VT);
3173 assert(Op.getNumOperands() == 3 &&
3174 VT == Op.getOperand(1).getValueType() &&
3177 // Expand into a bunch of logical ops, followed by a select_cc.
3178 SDOperand Lo = Op.getOperand(0);
3179 SDOperand Hi = Op.getOperand(1);
3180 SDOperand Amt = Op.getOperand(2);
3181 MVT::ValueType AmtVT = Amt.getValueType();
3183 SDOperand Tmp1 = DAG.getNode(ISD::SUB, AmtVT,
3184 DAG.getConstant(BitWidth, AmtVT), Amt);
3185 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, VT, Lo, Amt);
3186 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, VT, Hi, Tmp1);
3187 SDOperand Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3);
3188 SDOperand Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt,
3189 DAG.getConstant(-BitWidth, AmtVT));
3190 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, VT, Hi, Tmp5);
3191 SDOperand OutHi = DAG.getNode(PPCISD::SRA, VT, Hi, Amt);
3192 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, AmtVT),
3193 Tmp4, Tmp6, ISD::SETLE);
3194 SDOperand OutOps[] = { OutLo, OutHi };
3195 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, VT),
3199 //===----------------------------------------------------------------------===//
3200 // Vector related lowering.
3203 // If this is a vector of constants or undefs, get the bits. A bit in
3204 // UndefBits is set if the corresponding element of the vector is an
3205 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
3206 // zero. Return true if this is not an array of constants, false if it is.
3208 static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
3209 uint64_t UndefBits[2]) {
3210 // Start with zero'd results.
3211 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0;
3213 unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType());
3214 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3215 SDOperand OpVal = BV->getOperand(i);
3217 unsigned PartNo = i >= e/2; // In the upper 128 bits?
3218 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t.
3220 uint64_t EltBits = 0;
3221 if (OpVal.getOpcode() == ISD::UNDEF) {
3222 uint64_t EltUndefBits = ~0U >> (32-EltBitSize);
3223 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize);
3225 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
3226 EltBits = CN->getValue() & (~0U >> (32-EltBitSize));
3227 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
3228 assert(CN->getValueType(0) == MVT::f32 &&
3229 "Only one legal FP vector type!");
3230 EltBits = FloatToBits(CN->getValueAPF().convertToFloat());
3232 // Nonconstant element.
3236 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize);
3239 //printf("%llx %llx %llx %llx\n",
3240 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]);
3244 // If this is a splat (repetition) of a value across the whole vector, return
3245 // the smallest size that splats it. For example, "0x01010101010101..." is a
3246 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
3247 // SplatSize = 1 byte.
3248 static bool isConstantSplat(const uint64_t Bits128[2],
3249 const uint64_t Undef128[2],
3250 unsigned &SplatBits, unsigned &SplatUndef,
3251 unsigned &SplatSize) {
3253 // Don't let undefs prevent splats from matching. See if the top 64-bits are
3254 // the same as the lower 64-bits, ignoring undefs.
3255 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0]))
3256 return false; // Can't be a splat if two pieces don't match.
3258 uint64_t Bits64 = Bits128[0] | Bits128[1];
3259 uint64_t Undef64 = Undef128[0] & Undef128[1];
3261 // Check that the top 32-bits are the same as the lower 32-bits, ignoring
3263 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64))
3264 return false; // Can't be a splat if two pieces don't match.
3266 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32);
3267 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32);
3269 // If the top 16-bits are different than the lower 16-bits, ignoring
3270 // undefs, we have an i32 splat.
3271 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) {
3273 SplatUndef = Undef32;
3278 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16);
3279 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16);
3281 // If the top 8-bits are different than the lower 8-bits, ignoring
3282 // undefs, we have an i16 splat.
3283 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) {
3285 SplatUndef = Undef16;
3290 // Otherwise, we have an 8-bit splat.
3291 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8);
3292 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8);
3297 /// BuildSplatI - Build a canonical splati of Val with an element size of
3298 /// SplatSize. Cast the result to VT.
3299 static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT,
3300 SelectionDAG &DAG) {
3301 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
3303 static const MVT::ValueType VTys[] = { // canonical VT to use for each size.
3304 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
3307 MVT::ValueType ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
3309 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
3313 MVT::ValueType CanonicalVT = VTys[SplatSize-1];
3315 // Build a canonical splat for this value.
3316 SDOperand Elt = DAG.getConstant(Val, MVT::getVectorElementType(CanonicalVT));
3317 SmallVector<SDOperand, 8> Ops;
3318 Ops.assign(MVT::getVectorNumElements(CanonicalVT), Elt);
3319 SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT,
3320 &Ops[0], Ops.size());
3321 return DAG.getNode(ISD::BIT_CONVERT, ReqVT, Res);
3324 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
3325 /// specified intrinsic ID.
3326 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS,
3328 MVT::ValueType DestVT = MVT::Other) {
3329 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
3330 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
3331 DAG.getConstant(IID, MVT::i32), LHS, RHS);
3334 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
3335 /// specified intrinsic ID.
3336 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1,
3337 SDOperand Op2, SelectionDAG &DAG,
3338 MVT::ValueType DestVT = MVT::Other) {
3339 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
3340 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
3341 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
3345 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
3346 /// amount. The result has the specified value type.
3347 static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt,
3348 MVT::ValueType VT, SelectionDAG &DAG) {
3349 // Force LHS/RHS to be the right type.
3350 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS);
3351 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS);
3354 for (unsigned i = 0; i != 16; ++i)
3355 Ops[i] = DAG.getConstant(i+Amt, MVT::i32);
3356 SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS,
3357 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16));
3358 return DAG.getNode(ISD::BIT_CONVERT, VT, T);
3361 // If this is a case we can't handle, return null and let the default
3362 // expansion code take care of it. If we CAN select this case, and if it
3363 // selects to a single instruction, return Op. Otherwise, if we can codegen
3364 // this case more efficiently than a constant pool load, lower it to the
3365 // sequence of ops that should be used.
3366 SDOperand PPCTargetLowering::LowerBUILD_VECTOR(SDOperand Op,
3367 SelectionDAG &DAG) {
3368 // If this is a vector of constants or undefs, get the bits. A bit in
3369 // UndefBits is set if the corresponding element of the vector is an
3370 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
3372 uint64_t VectorBits[2];
3373 uint64_t UndefBits[2];
3374 if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits))
3375 return SDOperand(); // Not a constant vector.
3377 // If this is a splat (repetition) of a value across the whole vector, return
3378 // the smallest size that splats it. For example, "0x01010101010101..." is a
3379 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
3380 // SplatSize = 1 byte.
3381 unsigned SplatBits, SplatUndef, SplatSize;
3382 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){
3383 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0;
3385 // First, handle single instruction cases.
3388 if (SplatBits == 0) {
3389 // Canonicalize all zero vectors to be v4i32.
3390 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
3391 SDOperand Z = DAG.getConstant(0, MVT::i32);
3392 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z);
3393 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z);
3398 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
3399 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize);
3400 if (SextVal >= -16 && SextVal <= 15)
3401 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG);
3404 // Two instruction sequences.
3406 // If this value is in the range [-32,30] and is even, use:
3407 // tmp = VSPLTI[bhw], result = add tmp, tmp
3408 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
3409 Op = BuildSplatI(SextVal >> 1, SplatSize, Op.getValueType(), DAG);
3410 return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op);
3413 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
3414 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
3416 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
3417 // Make -1 and vspltisw -1:
3418 SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG);
3420 // Make the VSLW intrinsic, computing 0x8000_0000.
3421 SDOperand Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
3424 // xor by OnesV to invert it.
3425 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV);
3426 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
3429 // Check to see if this is a wide variety of vsplti*, binop self cases.
3430 unsigned SplatBitSize = SplatSize*8;
3431 static const signed char SplatCsts[] = {
3432 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
3433 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
3436 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
3437 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
3438 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
3439 int i = SplatCsts[idx];
3441 // Figure out what shift amount will be used by altivec if shifted by i in
3443 unsigned TypeShiftAmt = i & (SplatBitSize-1);
3445 // vsplti + shl self.
3446 if (SextVal == (i << (int)TypeShiftAmt)) {
3447 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
3448 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3449 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
3450 Intrinsic::ppc_altivec_vslw
3452 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
3453 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
3456 // vsplti + srl self.
3457 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
3458 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
3459 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3460 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
3461 Intrinsic::ppc_altivec_vsrw
3463 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
3464 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
3467 // vsplti + sra self.
3468 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
3469 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
3470 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3471 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
3472 Intrinsic::ppc_altivec_vsraw
3474 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
3475 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
3478 // vsplti + rol self.
3479 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
3480 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
3481 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
3482 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3483 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
3484 Intrinsic::ppc_altivec_vrlw
3486 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
3487 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
3490 // t = vsplti c, result = vsldoi t, t, 1
3491 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
3492 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
3493 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG);
3495 // t = vsplti c, result = vsldoi t, t, 2
3496 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
3497 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
3498 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG);
3500 // t = vsplti c, result = vsldoi t, t, 3
3501 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
3502 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
3503 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG);
3507 // Three instruction sequences.
3509 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
3510 if (SextVal >= 0 && SextVal <= 31) {
3511 SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG);
3512 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
3513 LHS = DAG.getNode(ISD::SUB, LHS.getValueType(), LHS, RHS);
3514 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
3516 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
3517 if (SextVal >= -31 && SextVal <= 0) {
3518 SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG);
3519 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
3520 LHS = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS);
3521 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
3528 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
3529 /// the specified operations to build the shuffle.
3530 static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS,
3531 SDOperand RHS, SelectionDAG &DAG) {
3532 unsigned OpNum = (PFEntry >> 26) & 0x0F;
3533 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
3534 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
3537 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
3549 if (OpNum == OP_COPY) {
3550 if (LHSID == (1*9+2)*9+3) return LHS;
3551 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
3555 SDOperand OpLHS, OpRHS;
3556 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG);
3557 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG);
3559 unsigned ShufIdxs[16];
3561 default: assert(0 && "Unknown i32 permute!");
3563 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
3564 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
3565 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
3566 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
3569 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
3570 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
3571 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
3572 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
3575 for (unsigned i = 0; i != 16; ++i)
3576 ShufIdxs[i] = (i&3)+0;
3579 for (unsigned i = 0; i != 16; ++i)
3580 ShufIdxs[i] = (i&3)+4;
3583 for (unsigned i = 0; i != 16; ++i)
3584 ShufIdxs[i] = (i&3)+8;
3587 for (unsigned i = 0; i != 16; ++i)
3588 ShufIdxs[i] = (i&3)+12;
3591 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG);
3593 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG);
3595 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG);
3598 for (unsigned i = 0; i != 16; ++i)
3599 Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i32);
3601 return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS,
3602 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
3605 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
3606 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
3607 /// return the code it can be lowered into. Worst case, it can always be
3608 /// lowered into a vperm.
3609 SDOperand PPCTargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op,
3610 SelectionDAG &DAG) {
3611 SDOperand V1 = Op.getOperand(0);
3612 SDOperand V2 = Op.getOperand(1);
3613 SDOperand PermMask = Op.getOperand(2);
3615 // Cases that are handled by instructions that take permute immediates
3616 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
3617 // selected by the instruction selector.
3618 if (V2.getOpcode() == ISD::UNDEF) {
3619 if (PPC::isSplatShuffleMask(PermMask.Val, 1) ||
3620 PPC::isSplatShuffleMask(PermMask.Val, 2) ||
3621 PPC::isSplatShuffleMask(PermMask.Val, 4) ||
3622 PPC::isVPKUWUMShuffleMask(PermMask.Val, true) ||
3623 PPC::isVPKUHUMShuffleMask(PermMask.Val, true) ||
3624 PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 ||
3625 PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) ||
3626 PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) ||
3627 PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) ||
3628 PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) ||
3629 PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) ||
3630 PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) {
3635 // Altivec has a variety of "shuffle immediates" that take two vector inputs
3636 // and produce a fixed permutation. If any of these match, do not lower to
3638 if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) ||
3639 PPC::isVPKUHUMShuffleMask(PermMask.Val, false) ||
3640 PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 ||
3641 PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) ||
3642 PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) ||
3643 PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) ||
3644 PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) ||
3645 PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) ||
3646 PPC::isVMRGHShuffleMask(PermMask.Val, 4, false))
3649 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
3650 // perfect shuffle table to emit an optimal matching sequence.
3651 unsigned PFIndexes[4];
3652 bool isFourElementShuffle = true;
3653 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
3654 unsigned EltNo = 8; // Start out undef.
3655 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
3656 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF)
3657 continue; // Undef, ignore it.
3659 unsigned ByteSource =
3660 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue();
3661 if ((ByteSource & 3) != j) {
3662 isFourElementShuffle = false;
3667 EltNo = ByteSource/4;
3668 } else if (EltNo != ByteSource/4) {
3669 isFourElementShuffle = false;
3673 PFIndexes[i] = EltNo;
3676 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
3677 // perfect shuffle vector to determine if it is cost effective to do this as
3678 // discrete instructions, or whether we should use a vperm.
3679 if (isFourElementShuffle) {
3680 // Compute the index in the perfect shuffle table.
3681 unsigned PFTableIndex =
3682 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3684 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3685 unsigned Cost = (PFEntry >> 30);
3687 // Determining when to avoid vperm is tricky. Many things affect the cost
3688 // of vperm, particularly how many times the perm mask needs to be computed.
3689 // For example, if the perm mask can be hoisted out of a loop or is already
3690 // used (perhaps because there are multiple permutes with the same shuffle
3691 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
3692 // the loop requires an extra register.
3694 // As a compromise, we only emit discrete instructions if the shuffle can be
3695 // generated in 3 or fewer operations. When we have loop information
3696 // available, if this block is within a loop, we should avoid using vperm
3697 // for 3-operation perms and use a constant pool load instead.
3699 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG);
3702 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
3703 // vector that will get spilled to the constant pool.
3704 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
3706 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
3707 // that it is in input element units, not in bytes. Convert now.
3708 MVT::ValueType EltVT = MVT::getVectorElementType(V1.getValueType());
3709 unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8;
3711 SmallVector<SDOperand, 16> ResultMask;
3712 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
3714 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
3717 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue();
3719 for (unsigned j = 0; j != BytesPerElement; ++j)
3720 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
3724 SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8,
3725 &ResultMask[0], ResultMask.size());
3726 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
3729 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
3730 /// altivec comparison. If it is, return true and fill in Opc/isDot with
3731 /// information about the intrinsic.
3732 static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc,
3734 unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue();
3737 switch (IntrinsicID) {
3738 default: return false;
3739 // Comparison predicates.
3740 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
3741 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
3742 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
3743 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
3744 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
3745 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
3746 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
3747 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
3748 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
3749 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
3750 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
3751 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
3752 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
3754 // Normal Comparisons.
3755 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
3756 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
3757 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
3758 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
3759 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
3760 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
3761 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
3762 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
3763 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
3764 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
3765 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
3766 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
3767 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
3772 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
3773 /// lower, do it, otherwise return null.
3774 SDOperand PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op,
3775 SelectionDAG &DAG) {
3776 // If this is a lowered altivec predicate compare, CompareOpc is set to the
3777 // opcode number of the comparison.
3780 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
3781 return SDOperand(); // Don't custom lower most intrinsics.
3783 // If this is a non-dot comparison, make the VCMP node and we are done.
3785 SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(),
3786 Op.getOperand(1), Op.getOperand(2),
3787 DAG.getConstant(CompareOpc, MVT::i32));
3788 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp);
3791 // Create the PPCISD altivec 'dot' comparison node.
3793 Op.getOperand(2), // LHS
3794 Op.getOperand(3), // RHS
3795 DAG.getConstant(CompareOpc, MVT::i32)
3797 std::vector<MVT::ValueType> VTs;
3798 VTs.push_back(Op.getOperand(2).getValueType());
3799 VTs.push_back(MVT::Flag);
3800 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
3802 // Now that we have the comparison, emit a copy from the CR to a GPR.
3803 // This is flagged to the above dot comparison.
3804 SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32,
3805 DAG.getRegister(PPC::CR6, MVT::i32),
3806 CompNode.getValue(1));
3808 // Unpack the result based on how the target uses it.
3809 unsigned BitNo; // Bit # of CR6.
3810 bool InvertBit; // Invert result?
3811 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
3812 default: // Can't happen, don't crash on invalid number though.
3813 case 0: // Return the value of the EQ bit of CR6.
3814 BitNo = 0; InvertBit = false;
3816 case 1: // Return the inverted value of the EQ bit of CR6.
3817 BitNo = 0; InvertBit = true;
3819 case 2: // Return the value of the LT bit of CR6.
3820 BitNo = 2; InvertBit = false;
3822 case 3: // Return the inverted value of the LT bit of CR6.
3823 BitNo = 2; InvertBit = true;
3827 // Shift the bit into the low position.
3828 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags,
3829 DAG.getConstant(8-(3-BitNo), MVT::i32));
3831 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags,
3832 DAG.getConstant(1, MVT::i32));
3834 // If we are supposed to, toggle the bit.
3836 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags,
3837 DAG.getConstant(1, MVT::i32));
3841 SDOperand PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op,
3842 SelectionDAG &DAG) {
3843 // Create a stack slot that is 16-byte aligned.
3844 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
3845 int FrameIdx = FrameInfo->CreateStackObject(16, 16);
3846 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3847 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
3849 // Store the input value into Value#0 of the stack slot.
3850 SDOperand Store = DAG.getStore(DAG.getEntryNode(),
3851 Op.getOperand(0), FIdx, NULL, 0);
3853 return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0);
3856 SDOperand PPCTargetLowering::LowerMUL(SDOperand Op, SelectionDAG &DAG) {
3857 if (Op.getValueType() == MVT::v4i32) {
3858 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3860 SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG);
3861 SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt.
3863 SDOperand RHSSwap = // = vrlw RHS, 16
3864 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG);
3866 // Shrinkify inputs to v8i16.
3867 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS);
3868 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS);
3869 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap);
3871 // Low parts multiplied together, generating 32-bit results (we ignore the
3873 SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
3874 LHS, RHS, DAG, MVT::v4i32);
3876 SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
3877 LHS, RHSSwap, Zero, DAG, MVT::v4i32);
3878 // Shift the high parts up 16 bits.
3879 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG);
3880 return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd);
3881 } else if (Op.getValueType() == MVT::v8i16) {
3882 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3884 SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG);
3886 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
3887 LHS, RHS, Zero, DAG);
3888 } else if (Op.getValueType() == MVT::v16i8) {
3889 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3891 // Multiply the even 8-bit parts, producing 16-bit sums.
3892 SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
3893 LHS, RHS, DAG, MVT::v8i16);
3894 EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts);
3896 // Multiply the odd 8-bit parts, producing 16-bit sums.
3897 SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
3898 LHS, RHS, DAG, MVT::v8i16);
3899 OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts);
3901 // Merge the results together.
3903 for (unsigned i = 0; i != 8; ++i) {
3904 Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8);
3905 Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8);
3907 return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts,
3908 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
3910 assert(0 && "Unknown mul to lower!");
3915 /// LowerOperation - Provide custom lowering hooks for some operations.
3917 SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
3918 switch (Op.getOpcode()) {
3919 default: assert(0 && "Wasn't expecting to be able to lower this!");
3920 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3921 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
3922 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3923 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
3924 case ISD::SETCC: return LowerSETCC(Op, DAG);
3926 return LowerVASTART(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
3927 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
3930 return LowerVAARG(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
3931 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
3933 case ISD::FORMAL_ARGUMENTS:
3934 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex,
3935 VarArgsStackOffset, VarArgsNumGPR,
3936 VarArgsNumFPR, PPCSubTarget);
3938 case ISD::CALL: return LowerCALL(Op, DAG, PPCSubTarget,
3939 getTargetMachine());
3940 case ISD::RET: return LowerRET(Op, DAG, getTargetMachine());
3941 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
3942 case ISD::DYNAMIC_STACKALLOC:
3943 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
3945 case ISD::ATOMIC_LAS: return LowerAtomicLAS(Op, DAG);
3946 case ISD::ATOMIC_LCS: return LowerAtomicLCS(Op, DAG);
3947 case ISD::ATOMIC_SWAP: return LowerAtomicSWAP(Op, DAG);
3949 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
3950 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
3951 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
3952 case ISD::FP_ROUND_INREG: return LowerFP_ROUND_INREG(Op, DAG);
3953 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
3955 // Lower 64-bit shifts.
3956 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
3957 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
3958 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
3960 // Vector-related lowering.
3961 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
3962 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
3963 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
3964 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
3965 case ISD::MUL: return LowerMUL(Op, DAG);
3967 // Frame & Return address.
3968 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
3969 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
3974 SDNode *PPCTargetLowering::ExpandOperationResult(SDNode *N, SelectionDAG &DAG) {
3975 switch (N->getOpcode()) {
3976 default: assert(0 && "Wasn't expecting to be able to lower this!");
3977 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(SDOperand(N, 0), DAG).Val;
3982 //===----------------------------------------------------------------------===//
3983 // Other Lowering Code
3984 //===----------------------------------------------------------------------===//
3987 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
3988 MachineBasicBlock *BB) {
3989 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3990 assert((MI->getOpcode() == PPC::SELECT_CC_I4 ||
3991 MI->getOpcode() == PPC::SELECT_CC_I8 ||
3992 MI->getOpcode() == PPC::SELECT_CC_F4 ||
3993 MI->getOpcode() == PPC::SELECT_CC_F8 ||
3994 MI->getOpcode() == PPC::SELECT_CC_VRRC) &&
3995 "Unexpected instr type to insert");
3997 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
3998 // control-flow pattern. The incoming instruction knows the destination vreg
3999 // to set, the condition code register to branch on, the true/false values to
4000 // select between, and a branch opcode to use.
4001 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4002 ilist<MachineBasicBlock>::iterator It = BB;
4008 // cmpTY ccX, r1, r2
4010 // fallthrough --> copy0MBB
4011 MachineBasicBlock *thisMBB = BB;
4012 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
4013 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
4014 unsigned SelectPred = MI->getOperand(4).getImm();
4015 BuildMI(BB, TII->get(PPC::BCC))
4016 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
4017 MachineFunction *F = BB->getParent();
4018 F->getBasicBlockList().insert(It, copy0MBB);
4019 F->getBasicBlockList().insert(It, sinkMBB);
4020 // Update machine-CFG edges by first adding all successors of the current
4021 // block to the new block which will contain the Phi node for the select.
4022 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
4023 e = BB->succ_end(); i != e; ++i)
4024 sinkMBB->addSuccessor(*i);
4025 // Next, remove all successors of the current block, and add the true
4026 // and fallthrough blocks as its successors.
4027 while(!BB->succ_empty())
4028 BB->removeSuccessor(BB->succ_begin());
4029 BB->addSuccessor(copy0MBB);
4030 BB->addSuccessor(sinkMBB);
4033 // %FalseValue = ...
4034 // # fallthrough to sinkMBB
4037 // Update machine-CFG edges
4038 BB->addSuccessor(sinkMBB);
4041 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4044 BuildMI(BB, TII->get(PPC::PHI), MI->getOperand(0).getReg())
4045 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
4046 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4048 delete MI; // The pseudo instruction is gone now.
4052 //===----------------------------------------------------------------------===//
4053 // Target Optimization Hooks
4054 //===----------------------------------------------------------------------===//
4056 SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
4057 DAGCombinerInfo &DCI) const {
4058 TargetMachine &TM = getTargetMachine();
4059 SelectionDAG &DAG = DCI.DAG;
4060 switch (N->getOpcode()) {
4063 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
4064 if (C->getValue() == 0) // 0 << V -> 0.
4065 return N->getOperand(0);
4069 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
4070 if (C->getValue() == 0) // 0 >>u V -> 0.
4071 return N->getOperand(0);
4075 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
4076 if (C->getValue() == 0 || // 0 >>s V -> 0.
4077 C->isAllOnesValue()) // -1 >>s V -> -1.
4078 return N->getOperand(0);
4082 case ISD::SINT_TO_FP:
4083 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
4084 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
4085 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
4086 // We allow the src/dst to be either f32/f64, but the intermediate
4087 // type must be i64.
4088 if (N->getOperand(0).getValueType() == MVT::i64 &&
4089 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
4090 SDOperand Val = N->getOperand(0).getOperand(0);
4091 if (Val.getValueType() == MVT::f32) {
4092 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
4093 DCI.AddToWorklist(Val.Val);
4096 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val);
4097 DCI.AddToWorklist(Val.Val);
4098 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val);
4099 DCI.AddToWorklist(Val.Val);
4100 if (N->getValueType(0) == MVT::f32) {
4101 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val,
4102 DAG.getIntPtrConstant(0));
4103 DCI.AddToWorklist(Val.Val);
4106 } else if (N->getOperand(0).getValueType() == MVT::i32) {
4107 // If the intermediate type is i32, we can avoid the load/store here
4114 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
4115 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
4116 !cast<StoreSDNode>(N)->isTruncatingStore() &&
4117 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
4118 N->getOperand(1).getValueType() == MVT::i32 &&
4119 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
4120 SDOperand Val = N->getOperand(1).getOperand(0);
4121 if (Val.getValueType() == MVT::f32) {
4122 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
4123 DCI.AddToWorklist(Val.Val);
4125 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val);
4126 DCI.AddToWorklist(Val.Val);
4128 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val,
4129 N->getOperand(2), N->getOperand(3));
4130 DCI.AddToWorklist(Val.Val);
4134 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
4135 if (N->getOperand(1).getOpcode() == ISD::BSWAP &&
4136 N->getOperand(1).Val->hasOneUse() &&
4137 (N->getOperand(1).getValueType() == MVT::i32 ||
4138 N->getOperand(1).getValueType() == MVT::i16)) {
4139 SDOperand BSwapOp = N->getOperand(1).getOperand(0);
4140 // Do an any-extend to 32-bits if this is a half-word input.
4141 if (BSwapOp.getValueType() == MVT::i16)
4142 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp);
4144 return DAG.getNode(PPCISD::STBRX, MVT::Other, N->getOperand(0), BSwapOp,
4145 N->getOperand(2), N->getOperand(3),
4146 DAG.getValueType(N->getOperand(1).getValueType()));
4150 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
4151 if (ISD::isNON_EXTLoad(N->getOperand(0).Val) &&
4152 N->getOperand(0).hasOneUse() &&
4153 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
4154 SDOperand Load = N->getOperand(0);
4155 LoadSDNode *LD = cast<LoadSDNode>(Load);
4156 // Create the byte-swapping load.
4157 std::vector<MVT::ValueType> VTs;
4158 VTs.push_back(MVT::i32);
4159 VTs.push_back(MVT::Other);
4160 SDOperand MO = DAG.getMemOperand(LD->getMemOperand());
4162 LD->getChain(), // Chain
4163 LD->getBasePtr(), // Ptr
4165 DAG.getValueType(N->getValueType(0)) // VT
4167 SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4);
4169 // If this is an i16 load, insert the truncate.
4170 SDOperand ResVal = BSLoad;
4171 if (N->getValueType(0) == MVT::i16)
4172 ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad);
4174 // First, combine the bswap away. This makes the value produced by the
4176 DCI.CombineTo(N, ResVal);
4178 // Next, combine the load away, we give it a bogus result value but a real
4179 // chain result. The result value is dead because the bswap is dead.
4180 DCI.CombineTo(Load.Val, ResVal, BSLoad.getValue(1));
4182 // Return N so it doesn't get rechecked!
4183 return SDOperand(N, 0);
4187 case PPCISD::VCMP: {
4188 // If a VCMPo node already exists with exactly the same operands as this
4189 // node, use its result instead of this node (VCMPo computes both a CR6 and
4190 // a normal output).
4192 if (!N->getOperand(0).hasOneUse() &&
4193 !N->getOperand(1).hasOneUse() &&
4194 !N->getOperand(2).hasOneUse()) {
4196 // Scan all of the users of the LHS, looking for VCMPo's that match.
4197 SDNode *VCMPoNode = 0;
4199 SDNode *LHSN = N->getOperand(0).Val;
4200 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
4202 if ((*UI).getUser()->getOpcode() == PPCISD::VCMPo &&
4203 (*UI).getUser()->getOperand(1) == N->getOperand(1) &&
4204 (*UI).getUser()->getOperand(2) == N->getOperand(2) &&
4205 (*UI).getUser()->getOperand(0) == N->getOperand(0)) {
4206 VCMPoNode = UI->getUser();
4210 // If there is no VCMPo node, or if the flag value has a single use, don't
4212 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
4215 // Look at the (necessarily single) use of the flag value. If it has a
4216 // chain, this transformation is more complex. Note that multiple things
4217 // could use the value result, which we should ignore.
4218 SDNode *FlagUser = 0;
4219 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
4220 FlagUser == 0; ++UI) {
4221 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
4222 SDNode *User = UI->getUser();
4223 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
4224 if (User->getOperand(i) == SDOperand(VCMPoNode, 1)) {
4231 // If the user is a MFCR instruction, we know this is safe. Otherwise we
4232 // give up for right now.
4233 if (FlagUser->getOpcode() == PPCISD::MFCR)
4234 return SDOperand(VCMPoNode, 0);
4239 // If this is a branch on an altivec predicate comparison, lower this so
4240 // that we don't have to do a MFCR: instead, branch directly on CR6. This
4241 // lowering is done pre-legalize, because the legalizer lowers the predicate
4242 // compare down to code that is difficult to reassemble.
4243 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
4244 SDOperand LHS = N->getOperand(2), RHS = N->getOperand(3);
4248 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
4249 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
4250 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
4251 assert(isDot && "Can't compare against a vector result!");
4253 // If this is a comparison against something other than 0/1, then we know
4254 // that the condition is never/always true.
4255 unsigned Val = cast<ConstantSDNode>(RHS)->getValue();
4256 if (Val != 0 && Val != 1) {
4257 if (CC == ISD::SETEQ) // Cond never true, remove branch.
4258 return N->getOperand(0);
4259 // Always !=, turn it into an unconditional branch.
4260 return DAG.getNode(ISD::BR, MVT::Other,
4261 N->getOperand(0), N->getOperand(4));
4264 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
4266 // Create the PPCISD altivec 'dot' comparison node.
4267 std::vector<MVT::ValueType> VTs;
4269 LHS.getOperand(2), // LHS of compare
4270 LHS.getOperand(3), // RHS of compare
4271 DAG.getConstant(CompareOpc, MVT::i32)
4273 VTs.push_back(LHS.getOperand(2).getValueType());
4274 VTs.push_back(MVT::Flag);
4275 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
4277 // Unpack the result based on how the target uses it.
4278 PPC::Predicate CompOpc;
4279 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) {
4280 default: // Can't happen, don't crash on invalid number though.
4281 case 0: // Branch on the value of the EQ bit of CR6.
4282 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
4284 case 1: // Branch on the inverted value of the EQ bit of CR6.
4285 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
4287 case 2: // Branch on the value of the LT bit of CR6.
4288 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
4290 case 3: // Branch on the inverted value of the LT bit of CR6.
4291 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
4295 return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0),
4296 DAG.getConstant(CompOpc, MVT::i32),
4297 DAG.getRegister(PPC::CR6, MVT::i32),
4298 N->getOperand(4), CompNode.getValue(1));
4307 //===----------------------------------------------------------------------===//
4308 // Inline Assembly Support
4309 //===----------------------------------------------------------------------===//
4311 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
4315 const SelectionDAG &DAG,
4316 unsigned Depth) const {
4317 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
4318 switch (Op.getOpcode()) {
4320 case PPCISD::LBRX: {
4321 // lhbrx is known to have the top bits cleared out.
4322 if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16)
4323 KnownZero = 0xFFFF0000;
4326 case ISD::INTRINSIC_WO_CHAIN: {
4327 switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) {
4329 case Intrinsic::ppc_altivec_vcmpbfp_p:
4330 case Intrinsic::ppc_altivec_vcmpeqfp_p:
4331 case Intrinsic::ppc_altivec_vcmpequb_p:
4332 case Intrinsic::ppc_altivec_vcmpequh_p:
4333 case Intrinsic::ppc_altivec_vcmpequw_p:
4334 case Intrinsic::ppc_altivec_vcmpgefp_p:
4335 case Intrinsic::ppc_altivec_vcmpgtfp_p:
4336 case Intrinsic::ppc_altivec_vcmpgtsb_p:
4337 case Intrinsic::ppc_altivec_vcmpgtsh_p:
4338 case Intrinsic::ppc_altivec_vcmpgtsw_p:
4339 case Intrinsic::ppc_altivec_vcmpgtub_p:
4340 case Intrinsic::ppc_altivec_vcmpgtuh_p:
4341 case Intrinsic::ppc_altivec_vcmpgtuw_p:
4342 KnownZero = ~1U; // All bits but the low one are known to be zero.
4350 /// getConstraintType - Given a constraint, return the type of
4351 /// constraint it is for this target.
4352 PPCTargetLowering::ConstraintType
4353 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
4354 if (Constraint.size() == 1) {
4355 switch (Constraint[0]) {
4362 return C_RegisterClass;
4365 return TargetLowering::getConstraintType(Constraint);
4368 std::pair<unsigned, const TargetRegisterClass*>
4369 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
4370 MVT::ValueType VT) const {
4371 if (Constraint.size() == 1) {
4372 // GCC RS6000 Constraint Letters
4373 switch (Constraint[0]) {
4376 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
4377 return std::make_pair(0U, PPC::G8RCRegisterClass);
4378 return std::make_pair(0U, PPC::GPRCRegisterClass);
4381 return std::make_pair(0U, PPC::F4RCRegisterClass);
4382 else if (VT == MVT::f64)
4383 return std::make_pair(0U, PPC::F8RCRegisterClass);
4386 return std::make_pair(0U, PPC::VRRCRegisterClass);
4388 return std::make_pair(0U, PPC::CRRCRegisterClass);
4392 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
4396 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
4397 /// vector. If it is invalid, don't add anything to Ops.
4398 void PPCTargetLowering::LowerAsmOperandForConstraint(SDOperand Op, char Letter,
4399 std::vector<SDOperand>&Ops,
4400 SelectionDAG &DAG) const {
4401 SDOperand Result(0,0);
4412 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
4413 if (!CST) return; // Must be an immediate to match.
4414 unsigned Value = CST->getValue();
4416 default: assert(0 && "Unknown constraint letter!");
4417 case 'I': // "I" is a signed 16-bit constant.
4418 if ((short)Value == (int)Value)
4419 Result = DAG.getTargetConstant(Value, Op.getValueType());
4421 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
4422 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
4423 if ((short)Value == 0)
4424 Result = DAG.getTargetConstant(Value, Op.getValueType());
4426 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
4427 if ((Value >> 16) == 0)
4428 Result = DAG.getTargetConstant(Value, Op.getValueType());
4430 case 'M': // "M" is a constant that is greater than 31.
4432 Result = DAG.getTargetConstant(Value, Op.getValueType());
4434 case 'N': // "N" is a positive constant that is an exact power of two.
4435 if ((int)Value > 0 && isPowerOf2_32(Value))
4436 Result = DAG.getTargetConstant(Value, Op.getValueType());
4438 case 'O': // "O" is the constant zero.
4440 Result = DAG.getTargetConstant(Value, Op.getValueType());
4442 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
4443 if ((short)-Value == (int)-Value)
4444 Result = DAG.getTargetConstant(Value, Op.getValueType());
4452 Ops.push_back(Result);
4456 // Handle standard constraint letters.
4457 TargetLowering::LowerAsmOperandForConstraint(Op, Letter, Ops, DAG);
4460 // isLegalAddressingMode - Return true if the addressing mode represented
4461 // by AM is legal for this target, for a load/store of the specified type.
4462 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
4463 const Type *Ty) const {
4464 // FIXME: PPC does not allow r+i addressing modes for vectors!
4466 // PPC allows a sign-extended 16-bit immediate field.
4467 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
4470 // No global is ever allowed as a base.
4474 // PPC only support r+r,
4476 case 0: // "r+i" or just "i", depending on HasBaseReg.
4479 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
4481 // Otherwise we have r+r or r+i.
4484 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
4486 // Allow 2*r as r+r.
4489 // No other scales are supported.
4496 /// isLegalAddressImmediate - Return true if the integer value can be used
4497 /// as the offset of the target addressing mode for load / store of the
4499 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{
4500 // PPC allows a sign-extended 16-bit immediate field.
4501 return (V > -(1 << 16) && V < (1 << 16)-1);
4504 bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
4508 SDOperand PPCTargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) {
4509 // Depths > 0 not supported yet!
4510 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
4513 MachineFunction &MF = DAG.getMachineFunction();
4514 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
4516 // Just load the return address off the stack.
4517 SDOperand RetAddrFI = getReturnAddrFrameIndex(DAG);
4519 // Make sure the function really does not optimize away the store of the RA
4521 FuncInfo->setLRStoreRequired();
4522 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
4525 SDOperand PPCTargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) {
4526 // Depths > 0 not supported yet!
4527 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
4530 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4531 bool isPPC64 = PtrVT == MVT::i64;
4533 MachineFunction &MF = DAG.getMachineFunction();
4534 MachineFrameInfo *MFI = MF.getFrameInfo();
4535 bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects())
4536 && MFI->getStackSize();
4539 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::X31 : PPC::X1,
4542 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::R31 : PPC::R1,