1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCCallingConv.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCPerfectShuffle.h"
19 #include "PPCTargetMachine.h"
20 #include "PPCTargetObjectFile.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringSwitch.h"
23 #include "llvm/ADT/Triple.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineLoopInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAG.h"
31 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/Constants.h"
34 #include "llvm/IR/DerivedTypes.h"
35 #include "llvm/IR/Function.h"
36 #include "llvm/IR/Intrinsics.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/Target/TargetOptions.h"
45 // FIXME: Remove this once soft-float is supported.
46 static cl::opt<bool> DisablePPCFloatInVariadic("disable-ppc-float-in-variadic",
47 cl::desc("disable saving float registers for va_start on PPC"), cl::Hidden);
49 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
50 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
52 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
53 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
55 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
56 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
58 // FIXME: Remove this once the bug has been fixed!
59 extern cl::opt<bool> ANDIGlueBug;
61 PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
62 const PPCSubtarget &STI)
63 : TargetLowering(TM), Subtarget(STI) {
64 // Use _setjmp/_longjmp instead of setjmp/longjmp.
65 setUseUnderscoreSetJmp(true);
66 setUseUnderscoreLongJmp(true);
68 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
69 // arguments are at least 4/8 bytes aligned.
70 bool isPPC64 = Subtarget.isPPC64();
71 setMinStackArgumentAlignment(isPPC64 ? 8:4);
73 // Set up the register classes.
74 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
75 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
76 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
78 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
79 for (MVT VT : MVT::integer_valuetypes()) {
80 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
81 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
84 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
86 // PowerPC has pre-inc load and store's.
87 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
91 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
92 setIndexedLoadAction(ISD::PRE_INC, MVT::f32, Legal);
93 setIndexedLoadAction(ISD::PRE_INC, MVT::f64, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
99 setIndexedStoreAction(ISD::PRE_INC, MVT::f32, Legal);
100 setIndexedStoreAction(ISD::PRE_INC, MVT::f64, Legal);
102 if (Subtarget.useCRBits()) {
103 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
105 if (isPPC64 || Subtarget.hasFPCVT()) {
106 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
107 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
108 isPPC64 ? MVT::i64 : MVT::i32);
109 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
110 AddPromotedToType(ISD::UINT_TO_FP, MVT::i1,
111 isPPC64 ? MVT::i64 : MVT::i32);
113 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
114 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
117 // PowerPC does not support direct load / store of condition registers
118 setOperationAction(ISD::LOAD, MVT::i1, Custom);
119 setOperationAction(ISD::STORE, MVT::i1, Custom);
121 // FIXME: Remove this once the ANDI glue bug is fixed:
123 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
125 for (MVT VT : MVT::integer_valuetypes()) {
126 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
127 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
128 setTruncStoreAction(VT, MVT::i1, Expand);
131 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
134 // This is used in the ppcf128->int sequence. Note it has different semantics
135 // from FP_ROUND: that rounds to nearest, this rounds to zero.
136 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
138 // We do not currently implement these libm ops for PowerPC.
139 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
140 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
141 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
142 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
143 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
144 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
146 // PowerPC has no SREM/UREM instructions
147 setOperationAction(ISD::SREM, MVT::i32, Expand);
148 setOperationAction(ISD::UREM, MVT::i32, Expand);
149 setOperationAction(ISD::SREM, MVT::i64, Expand);
150 setOperationAction(ISD::UREM, MVT::i64, Expand);
152 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
153 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
154 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
155 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
156 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
157 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
158 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
159 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
160 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
162 // We don't support sin/cos/sqrt/fmod/pow
163 setOperationAction(ISD::FSIN , MVT::f64, Expand);
164 setOperationAction(ISD::FCOS , MVT::f64, Expand);
165 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
166 setOperationAction(ISD::FREM , MVT::f64, Expand);
167 setOperationAction(ISD::FPOW , MVT::f64, Expand);
168 setOperationAction(ISD::FMA , MVT::f64, Legal);
169 setOperationAction(ISD::FSIN , MVT::f32, Expand);
170 setOperationAction(ISD::FCOS , MVT::f32, Expand);
171 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
172 setOperationAction(ISD::FREM , MVT::f32, Expand);
173 setOperationAction(ISD::FPOW , MVT::f32, Expand);
174 setOperationAction(ISD::FMA , MVT::f32, Legal);
176 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
178 // If we're enabling GP optimizations, use hardware square root
179 if (!Subtarget.hasFSQRT() &&
180 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() &&
182 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
184 if (!Subtarget.hasFSQRT() &&
185 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTES() &&
186 Subtarget.hasFRES()))
187 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
189 if (Subtarget.hasFCPSGN()) {
190 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
191 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
193 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
194 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
197 if (Subtarget.hasFPRND()) {
198 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
199 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
200 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
201 setOperationAction(ISD::FROUND, MVT::f64, Legal);
203 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
204 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
205 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
206 setOperationAction(ISD::FROUND, MVT::f32, Legal);
209 // PowerPC does not have BSWAP, CTPOP or CTTZ
210 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
211 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
212 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
213 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
214 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
215 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
216 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
217 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
219 if (Subtarget.hasPOPCNTD()) {
220 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
221 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
223 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
224 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
227 // PowerPC does not have ROTR
228 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
229 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
231 if (!Subtarget.useCRBits()) {
232 // PowerPC does not have Select
233 setOperationAction(ISD::SELECT, MVT::i32, Expand);
234 setOperationAction(ISD::SELECT, MVT::i64, Expand);
235 setOperationAction(ISD::SELECT, MVT::f32, Expand);
236 setOperationAction(ISD::SELECT, MVT::f64, Expand);
239 // PowerPC wants to turn select_cc of FP into fsel when possible.
240 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
241 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
243 // PowerPC wants to optimize integer setcc a bit
244 if (!Subtarget.useCRBits())
245 setOperationAction(ISD::SETCC, MVT::i32, Custom);
247 // PowerPC does not have BRCOND which requires SetCC
248 if (!Subtarget.useCRBits())
249 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
251 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
253 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
254 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
256 // PowerPC does not have [U|S]INT_TO_FP
257 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
258 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
260 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
261 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
262 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
263 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
265 // We cannot sextinreg(i1). Expand to shifts.
266 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
268 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
269 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
270 // support continuation, user-level threading, and etc.. As a result, no
271 // other SjLj exception interfaces are implemented and please don't build
272 // your own exception handling based on them.
273 // LLVM/Clang supports zero-cost DWARF exception handling.
274 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
275 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
277 // We want to legalize GlobalAddress and ConstantPool nodes into the
278 // appropriate instructions to materialize the address.
279 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
280 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
281 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
282 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
283 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
284 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
285 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
286 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
287 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
288 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
291 setOperationAction(ISD::TRAP, MVT::Other, Legal);
293 // TRAMPOLINE is custom lowered.
294 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
295 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
297 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
298 setOperationAction(ISD::VASTART , MVT::Other, Custom);
300 if (Subtarget.isSVR4ABI()) {
302 // VAARG always uses double-word chunks, so promote anything smaller.
303 setOperationAction(ISD::VAARG, MVT::i1, Promote);
304 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
305 setOperationAction(ISD::VAARG, MVT::i8, Promote);
306 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
307 setOperationAction(ISD::VAARG, MVT::i16, Promote);
308 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
309 setOperationAction(ISD::VAARG, MVT::i32, Promote);
310 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
311 setOperationAction(ISD::VAARG, MVT::Other, Expand);
313 // VAARG is custom lowered with the 32-bit SVR4 ABI.
314 setOperationAction(ISD::VAARG, MVT::Other, Custom);
315 setOperationAction(ISD::VAARG, MVT::i64, Custom);
318 setOperationAction(ISD::VAARG, MVT::Other, Expand);
320 if (Subtarget.isSVR4ABI() && !isPPC64)
321 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
322 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
324 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
326 // Use the default implementation.
327 setOperationAction(ISD::VAEND , MVT::Other, Expand);
328 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
329 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
330 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
331 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
332 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, MVT::i32, Custom);
333 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, MVT::i64, Custom);
335 // We want to custom lower some of our intrinsics.
336 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
338 // To handle counter-based loop conditions.
339 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
341 // Comparisons that require checking two conditions.
342 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
343 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
344 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
345 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
346 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
347 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
348 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
349 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
350 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
351 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
352 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
353 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
355 if (Subtarget.has64BitSupport()) {
356 // They also have instructions for converting between i64 and fp.
357 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
358 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
359 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
360 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
361 // This is just the low 32 bits of a (signed) fp->i64 conversion.
362 // We cannot do this with Promote because i64 is not a legal type.
363 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
365 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
366 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
368 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
369 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
372 // With the instructions enabled under FPCVT, we can do everything.
373 if (Subtarget.hasFPCVT()) {
374 if (Subtarget.has64BitSupport()) {
375 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
376 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
377 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
378 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
381 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
382 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
383 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
384 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
387 if (Subtarget.use64BitRegs()) {
388 // 64-bit PowerPC implementations can support i64 types directly
389 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
390 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
391 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
392 // 64-bit PowerPC wants to expand i128 shifts itself.
393 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
394 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
395 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
397 // 32-bit PowerPC wants to expand i64 shifts itself.
398 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
399 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
400 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
403 if (Subtarget.hasAltivec()) {
404 // First set operation action for all vector types to expand. Then we
405 // will selectively turn on ones that can be effectively codegen'd.
406 for (MVT VT : MVT::vector_valuetypes()) {
407 // add/sub are legal for all supported vector VT's.
408 setOperationAction(ISD::ADD, VT, Legal);
409 setOperationAction(ISD::SUB, VT, Legal);
411 // Vector instructions introduced in P8
412 if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) {
413 setOperationAction(ISD::CTPOP, VT, Legal);
414 setOperationAction(ISD::CTLZ, VT, Legal);
417 setOperationAction(ISD::CTPOP, VT, Expand);
418 setOperationAction(ISD::CTLZ, VT, Expand);
421 // We promote all shuffles to v16i8.
422 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
423 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
425 // We promote all non-typed operations to v4i32.
426 setOperationAction(ISD::AND , VT, Promote);
427 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
428 setOperationAction(ISD::OR , VT, Promote);
429 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
430 setOperationAction(ISD::XOR , VT, Promote);
431 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
432 setOperationAction(ISD::LOAD , VT, Promote);
433 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
434 setOperationAction(ISD::SELECT, VT, Promote);
435 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
436 setOperationAction(ISD::SELECT_CC, VT, Promote);
437 AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32);
438 setOperationAction(ISD::STORE, VT, Promote);
439 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
441 // No other operations are legal.
442 setOperationAction(ISD::MUL , VT, Expand);
443 setOperationAction(ISD::SDIV, VT, Expand);
444 setOperationAction(ISD::SREM, VT, Expand);
445 setOperationAction(ISD::UDIV, VT, Expand);
446 setOperationAction(ISD::UREM, VT, Expand);
447 setOperationAction(ISD::FDIV, VT, Expand);
448 setOperationAction(ISD::FREM, VT, Expand);
449 setOperationAction(ISD::FNEG, VT, Expand);
450 setOperationAction(ISD::FSQRT, VT, Expand);
451 setOperationAction(ISD::FLOG, VT, Expand);
452 setOperationAction(ISD::FLOG10, VT, Expand);
453 setOperationAction(ISD::FLOG2, VT, Expand);
454 setOperationAction(ISD::FEXP, VT, Expand);
455 setOperationAction(ISD::FEXP2, VT, Expand);
456 setOperationAction(ISD::FSIN, VT, Expand);
457 setOperationAction(ISD::FCOS, VT, Expand);
458 setOperationAction(ISD::FABS, VT, Expand);
459 setOperationAction(ISD::FPOWI, VT, Expand);
460 setOperationAction(ISD::FFLOOR, VT, Expand);
461 setOperationAction(ISD::FCEIL, VT, Expand);
462 setOperationAction(ISD::FTRUNC, VT, Expand);
463 setOperationAction(ISD::FRINT, VT, Expand);
464 setOperationAction(ISD::FNEARBYINT, VT, Expand);
465 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
466 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
467 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
468 setOperationAction(ISD::MULHU, VT, Expand);
469 setOperationAction(ISD::MULHS, VT, Expand);
470 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
471 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
472 setOperationAction(ISD::UDIVREM, VT, Expand);
473 setOperationAction(ISD::SDIVREM, VT, Expand);
474 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
475 setOperationAction(ISD::FPOW, VT, Expand);
476 setOperationAction(ISD::BSWAP, VT, Expand);
477 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
478 setOperationAction(ISD::CTTZ, VT, Expand);
479 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
480 setOperationAction(ISD::VSELECT, VT, Expand);
481 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
482 setOperationAction(ISD::ROTL, VT, Expand);
483 setOperationAction(ISD::ROTR, VT, Expand);
485 for (MVT InnerVT : MVT::vector_valuetypes()) {
486 setTruncStoreAction(VT, InnerVT, Expand);
487 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
488 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
489 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
493 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
494 // with merges, splats, etc.
495 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
497 setOperationAction(ISD::AND , MVT::v4i32, Legal);
498 setOperationAction(ISD::OR , MVT::v4i32, Legal);
499 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
500 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
501 setOperationAction(ISD::SELECT, MVT::v4i32,
502 Subtarget.useCRBits() ? Legal : Expand);
503 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
504 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
505 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
506 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
507 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
508 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
509 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
510 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
511 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
513 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
514 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
515 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
516 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
518 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
519 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
521 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
522 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
523 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
526 if (Subtarget.hasP8Altivec())
527 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
529 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
531 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
532 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
534 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
535 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
537 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
538 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
539 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
540 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
542 // Altivec does not contain unordered floating-point compare instructions
543 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
544 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
545 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
546 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
548 if (Subtarget.hasVSX()) {
549 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
550 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
551 if (Subtarget.hasP8Vector()) {
552 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
553 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Legal);
555 if (Subtarget.hasDirectMove()) {
556 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal);
557 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Legal);
558 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Legal);
559 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Legal);
560 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Legal);
561 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Legal);
562 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal);
563 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
565 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
567 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
568 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
569 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
570 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
571 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
573 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
575 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
576 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
578 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
579 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
581 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
582 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
583 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
584 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
585 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
587 // Share the Altivec comparison restrictions.
588 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
589 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
590 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
591 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
593 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
594 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
596 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
598 if (Subtarget.hasP8Vector())
599 addRegisterClass(MVT::f32, &PPC::VSSRCRegClass);
601 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
603 addRegisterClass(MVT::v4i32, &PPC::VSRCRegClass);
604 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
605 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
607 if (Subtarget.hasP8Altivec()) {
608 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
609 setOperationAction(ISD::SRA, MVT::v2i64, Legal);
610 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
612 setOperationAction(ISD::SETCC, MVT::v2i64, Legal);
615 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
616 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
617 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
619 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
621 // VSX v2i64 only supports non-arithmetic operations.
622 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
623 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
626 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
627 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
628 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
629 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
631 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
633 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
634 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
635 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
636 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
638 // Vector operation legalization checks the result type of
639 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
640 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
641 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
642 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
643 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
645 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
648 if (Subtarget.hasP8Altivec()) {
649 addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass);
650 addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass);
654 if (Subtarget.hasQPX()) {
655 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
656 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
657 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
658 setOperationAction(ISD::FREM, MVT::v4f64, Expand);
660 setOperationAction(ISD::FCOPYSIGN, MVT::v4f64, Legal);
661 setOperationAction(ISD::FGETSIGN, MVT::v4f64, Expand);
663 setOperationAction(ISD::LOAD , MVT::v4f64, Custom);
664 setOperationAction(ISD::STORE , MVT::v4f64, Custom);
666 setTruncStoreAction(MVT::v4f64, MVT::v4f32, Custom);
667 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Custom);
669 if (!Subtarget.useCRBits())
670 setOperationAction(ISD::SELECT, MVT::v4f64, Expand);
671 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
673 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f64, Legal);
674 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f64, Expand);
675 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f64, Expand);
676 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f64, Expand);
677 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f64, Custom);
678 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f64, Legal);
679 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
681 setOperationAction(ISD::FP_TO_SINT , MVT::v4f64, Legal);
682 setOperationAction(ISD::FP_TO_UINT , MVT::v4f64, Expand);
684 setOperationAction(ISD::FP_ROUND , MVT::v4f32, Legal);
685 setOperationAction(ISD::FP_ROUND_INREG , MVT::v4f32, Expand);
686 setOperationAction(ISD::FP_EXTEND, MVT::v4f64, Legal);
688 setOperationAction(ISD::FNEG , MVT::v4f64, Legal);
689 setOperationAction(ISD::FABS , MVT::v4f64, Legal);
690 setOperationAction(ISD::FSIN , MVT::v4f64, Expand);
691 setOperationAction(ISD::FCOS , MVT::v4f64, Expand);
692 setOperationAction(ISD::FPOWI , MVT::v4f64, Expand);
693 setOperationAction(ISD::FPOW , MVT::v4f64, Expand);
694 setOperationAction(ISD::FLOG , MVT::v4f64, Expand);
695 setOperationAction(ISD::FLOG2 , MVT::v4f64, Expand);
696 setOperationAction(ISD::FLOG10 , MVT::v4f64, Expand);
697 setOperationAction(ISD::FEXP , MVT::v4f64, Expand);
698 setOperationAction(ISD::FEXP2 , MVT::v4f64, Expand);
700 setOperationAction(ISD::FMINNUM, MVT::v4f64, Legal);
701 setOperationAction(ISD::FMAXNUM, MVT::v4f64, Legal);
703 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f64, Legal);
704 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f64, Legal);
706 addRegisterClass(MVT::v4f64, &PPC::QFRCRegClass);
708 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
709 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
710 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
711 setOperationAction(ISD::FREM, MVT::v4f32, Expand);
713 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Legal);
714 setOperationAction(ISD::FGETSIGN, MVT::v4f32, Expand);
716 setOperationAction(ISD::LOAD , MVT::v4f32, Custom);
717 setOperationAction(ISD::STORE , MVT::v4f32, Custom);
719 if (!Subtarget.useCRBits())
720 setOperationAction(ISD::SELECT, MVT::v4f32, Expand);
721 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
723 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f32, Legal);
724 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f32, Expand);
725 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f32, Expand);
726 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f32, Expand);
727 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f32, Custom);
728 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
729 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
731 setOperationAction(ISD::FP_TO_SINT , MVT::v4f32, Legal);
732 setOperationAction(ISD::FP_TO_UINT , MVT::v4f32, Expand);
734 setOperationAction(ISD::FNEG , MVT::v4f32, Legal);
735 setOperationAction(ISD::FABS , MVT::v4f32, Legal);
736 setOperationAction(ISD::FSIN , MVT::v4f32, Expand);
737 setOperationAction(ISD::FCOS , MVT::v4f32, Expand);
738 setOperationAction(ISD::FPOWI , MVT::v4f32, Expand);
739 setOperationAction(ISD::FPOW , MVT::v4f32, Expand);
740 setOperationAction(ISD::FLOG , MVT::v4f32, Expand);
741 setOperationAction(ISD::FLOG2 , MVT::v4f32, Expand);
742 setOperationAction(ISD::FLOG10 , MVT::v4f32, Expand);
743 setOperationAction(ISD::FEXP , MVT::v4f32, Expand);
744 setOperationAction(ISD::FEXP2 , MVT::v4f32, Expand);
746 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
747 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
749 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f32, Legal);
750 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f32, Legal);
752 addRegisterClass(MVT::v4f32, &PPC::QSRCRegClass);
754 setOperationAction(ISD::AND , MVT::v4i1, Legal);
755 setOperationAction(ISD::OR , MVT::v4i1, Legal);
756 setOperationAction(ISD::XOR , MVT::v4i1, Legal);
758 if (!Subtarget.useCRBits())
759 setOperationAction(ISD::SELECT, MVT::v4i1, Expand);
760 setOperationAction(ISD::VSELECT, MVT::v4i1, Legal);
762 setOperationAction(ISD::LOAD , MVT::v4i1, Custom);
763 setOperationAction(ISD::STORE , MVT::v4i1, Custom);
765 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4i1, Custom);
766 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4i1, Expand);
767 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4i1, Expand);
768 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4i1, Expand);
769 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4i1, Custom);
770 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i1, Expand);
771 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
773 setOperationAction(ISD::SINT_TO_FP, MVT::v4i1, Custom);
774 setOperationAction(ISD::UINT_TO_FP, MVT::v4i1, Custom);
776 addRegisterClass(MVT::v4i1, &PPC::QBRCRegClass);
778 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
779 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
780 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
781 setOperationAction(ISD::FROUND, MVT::v4f64, Legal);
783 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
784 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
785 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
786 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
788 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Expand);
789 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
791 // These need to set FE_INEXACT, and so cannot be vectorized here.
792 setOperationAction(ISD::FRINT, MVT::v4f64, Expand);
793 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
795 if (TM.Options.UnsafeFPMath) {
796 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
797 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
799 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
800 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
802 setOperationAction(ISD::FDIV, MVT::v4f64, Expand);
803 setOperationAction(ISD::FSQRT, MVT::v4f64, Expand);
805 setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
806 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
810 if (Subtarget.has64BitSupport())
811 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
813 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
816 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
817 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
820 setBooleanContents(ZeroOrOneBooleanContent);
822 if (Subtarget.hasAltivec()) {
823 // Altivec instructions set fields to all zeros or all ones.
824 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
828 // These libcalls are not available in 32-bit.
829 setLibcallName(RTLIB::SHL_I128, nullptr);
830 setLibcallName(RTLIB::SRL_I128, nullptr);
831 setLibcallName(RTLIB::SRA_I128, nullptr);
834 setStackPointerRegisterToSaveRestore(isPPC64 ? PPC::X1 : PPC::R1);
836 // We have target-specific dag combine patterns for the following nodes:
837 setTargetDAGCombine(ISD::SINT_TO_FP);
838 if (Subtarget.hasFPCVT())
839 setTargetDAGCombine(ISD::UINT_TO_FP);
840 setTargetDAGCombine(ISD::LOAD);
841 setTargetDAGCombine(ISD::STORE);
842 setTargetDAGCombine(ISD::BR_CC);
843 if (Subtarget.useCRBits())
844 setTargetDAGCombine(ISD::BRCOND);
845 setTargetDAGCombine(ISD::BSWAP);
846 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
847 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
848 setTargetDAGCombine(ISD::INTRINSIC_VOID);
850 setTargetDAGCombine(ISD::SIGN_EXTEND);
851 setTargetDAGCombine(ISD::ZERO_EXTEND);
852 setTargetDAGCombine(ISD::ANY_EXTEND);
854 if (Subtarget.useCRBits()) {
855 setTargetDAGCombine(ISD::TRUNCATE);
856 setTargetDAGCombine(ISD::SETCC);
857 setTargetDAGCombine(ISD::SELECT_CC);
860 // Use reciprocal estimates.
861 if (TM.Options.UnsafeFPMath) {
862 setTargetDAGCombine(ISD::FDIV);
863 setTargetDAGCombine(ISD::FSQRT);
866 // Darwin long double math library functions have $LDBL128 appended.
867 if (Subtarget.isDarwin()) {
868 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
869 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
870 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
871 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
872 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
873 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
874 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
875 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
876 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
877 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
880 // With 32 condition bits, we don't need to sink (and duplicate) compares
881 // aggressively in CodeGenPrep.
882 if (Subtarget.useCRBits()) {
883 setHasMultipleConditionRegisters();
884 setJumpIsExpensive();
887 setMinFunctionAlignment(2);
888 if (Subtarget.isDarwin())
889 setPrefFunctionAlignment(4);
891 switch (Subtarget.getDarwinDirective()) {
895 case PPC::DIR_E500mc:
904 setPrefFunctionAlignment(4);
905 setPrefLoopAlignment(4);
909 setInsertFencesForAtomic(true);
911 if (Subtarget.enableMachineScheduler())
912 setSchedulingPreference(Sched::Source);
914 setSchedulingPreference(Sched::Hybrid);
916 computeRegisterProperties(STI.getRegisterInfo());
918 // The Freescale cores do better with aggressive inlining of memcpy and
919 // friends. GCC uses same threshold of 128 bytes (= 32 word stores).
920 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
921 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
922 MaxStoresPerMemset = 32;
923 MaxStoresPerMemsetOptSize = 16;
924 MaxStoresPerMemcpy = 32;
925 MaxStoresPerMemcpyOptSize = 8;
926 MaxStoresPerMemmove = 32;
927 MaxStoresPerMemmoveOptSize = 8;
928 } else if (Subtarget.getDarwinDirective() == PPC::DIR_A2) {
929 // The A2 also benefits from (very) aggressive inlining of memcpy and
930 // friends. The overhead of a the function call, even when warm, can be
931 // over one hundred cycles.
932 MaxStoresPerMemset = 128;
933 MaxStoresPerMemcpy = 128;
934 MaxStoresPerMemmove = 128;
938 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
939 /// the desired ByVal argument alignment.
940 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
941 unsigned MaxMaxAlign) {
942 if (MaxAlign == MaxMaxAlign)
944 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
945 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
947 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
949 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
950 unsigned EltAlign = 0;
951 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
952 if (EltAlign > MaxAlign)
954 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
955 for (auto *EltTy : STy->elements()) {
956 unsigned EltAlign = 0;
957 getMaxByValAlign(EltTy, EltAlign, MaxMaxAlign);
958 if (EltAlign > MaxAlign)
960 if (MaxAlign == MaxMaxAlign)
966 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
967 /// function arguments in the caller parameter area.
968 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty,
969 const DataLayout &DL) const {
970 // Darwin passes everything on 4 byte boundary.
971 if (Subtarget.isDarwin())
974 // 16byte and wider vectors are passed on 16byte boundary.
975 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
976 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
977 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
978 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
982 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
983 switch ((PPCISD::NodeType)Opcode) {
984 case PPCISD::FIRST_NUMBER: break;
985 case PPCISD::FSEL: return "PPCISD::FSEL";
986 case PPCISD::FCFID: return "PPCISD::FCFID";
987 case PPCISD::FCFIDU: return "PPCISD::FCFIDU";
988 case PPCISD::FCFIDS: return "PPCISD::FCFIDS";
989 case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS";
990 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
991 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
992 case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ";
993 case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ";
994 case PPCISD::FRE: return "PPCISD::FRE";
995 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
996 case PPCISD::STFIWX: return "PPCISD::STFIWX";
997 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
998 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
999 case PPCISD::VPERM: return "PPCISD::VPERM";
1000 case PPCISD::CMPB: return "PPCISD::CMPB";
1001 case PPCISD::Hi: return "PPCISD::Hi";
1002 case PPCISD::Lo: return "PPCISD::Lo";
1003 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
1004 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
1005 case PPCISD::DYNAREAOFFSET: return "PPCISD::DYNAREAOFFSET";
1006 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
1007 case PPCISD::SRL: return "PPCISD::SRL";
1008 case PPCISD::SRA: return "PPCISD::SRA";
1009 case PPCISD::SHL: return "PPCISD::SHL";
1010 case PPCISD::SRA_ADDZE: return "PPCISD::SRA_ADDZE";
1011 case PPCISD::CALL: return "PPCISD::CALL";
1012 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
1013 case PPCISD::MTCTR: return "PPCISD::MTCTR";
1014 case PPCISD::BCTRL: return "PPCISD::BCTRL";
1015 case PPCISD::BCTRL_LOAD_TOC: return "PPCISD::BCTRL_LOAD_TOC";
1016 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
1017 case PPCISD::READ_TIME_BASE: return "PPCISD::READ_TIME_BASE";
1018 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
1019 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
1020 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
1021 case PPCISD::MFVSR: return "PPCISD::MFVSR";
1022 case PPCISD::MTVSRA: return "PPCISD::MTVSRA";
1023 case PPCISD::MTVSRZ: return "PPCISD::MTVSRZ";
1024 case PPCISD::ANDIo_1_EQ_BIT: return "PPCISD::ANDIo_1_EQ_BIT";
1025 case PPCISD::ANDIo_1_GT_BIT: return "PPCISD::ANDIo_1_GT_BIT";
1026 case PPCISD::VCMP: return "PPCISD::VCMP";
1027 case PPCISD::VCMPo: return "PPCISD::VCMPo";
1028 case PPCISD::LBRX: return "PPCISD::LBRX";
1029 case PPCISD::STBRX: return "PPCISD::STBRX";
1030 case PPCISD::LFIWAX: return "PPCISD::LFIWAX";
1031 case PPCISD::LFIWZX: return "PPCISD::LFIWZX";
1032 case PPCISD::LXVD2X: return "PPCISD::LXVD2X";
1033 case PPCISD::STXVD2X: return "PPCISD::STXVD2X";
1034 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
1035 case PPCISD::BDNZ: return "PPCISD::BDNZ";
1036 case PPCISD::BDZ: return "PPCISD::BDZ";
1037 case PPCISD::MFFS: return "PPCISD::MFFS";
1038 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
1039 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
1040 case PPCISD::CR6SET: return "PPCISD::CR6SET";
1041 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
1042 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
1043 case PPCISD::PPC32_PICGOT: return "PPCISD::PPC32_PICGOT";
1044 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
1045 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
1046 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
1047 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
1048 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
1049 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
1050 case PPCISD::ADDI_TLSGD_L_ADDR: return "PPCISD::ADDI_TLSGD_L_ADDR";
1051 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
1052 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
1053 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
1054 case PPCISD::ADDI_TLSLD_L_ADDR: return "PPCISD::ADDI_TLSLD_L_ADDR";
1055 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
1056 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
1057 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
1058 case PPCISD::SC: return "PPCISD::SC";
1059 case PPCISD::CLRBHRB: return "PPCISD::CLRBHRB";
1060 case PPCISD::MFBHRBE: return "PPCISD::MFBHRBE";
1061 case PPCISD::RFEBB: return "PPCISD::RFEBB";
1062 case PPCISD::XXSWAPD: return "PPCISD::XXSWAPD";
1063 case PPCISD::QVFPERM: return "PPCISD::QVFPERM";
1064 case PPCISD::QVGPCI: return "PPCISD::QVGPCI";
1065 case PPCISD::QVALIGNI: return "PPCISD::QVALIGNI";
1066 case PPCISD::QVESPLATI: return "PPCISD::QVESPLATI";
1067 case PPCISD::QBFLT: return "PPCISD::QBFLT";
1068 case PPCISD::QVLFSb: return "PPCISD::QVLFSb";
1073 EVT PPCTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &C,
1076 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
1078 if (Subtarget.hasQPX())
1079 return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements());
1081 return VT.changeVectorElementTypeToInteger();
1084 bool PPCTargetLowering::enableAggressiveFMAFusion(EVT VT) const {
1085 assert(VT.isFloatingPoint() && "Non-floating-point FMA?");
1089 //===----------------------------------------------------------------------===//
1090 // Node matching predicates, for use by the tblgen matching code.
1091 //===----------------------------------------------------------------------===//
1093 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
1094 static bool isFloatingPointZero(SDValue Op) {
1095 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1096 return CFP->getValueAPF().isZero();
1097 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1098 // Maybe this has already been legalized into the constant pool?
1099 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
1100 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1101 return CFP->getValueAPF().isZero();
1106 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
1107 /// true if Op is undef or if it matches the specified value.
1108 static bool isConstantOrUndef(int Op, int Val) {
1109 return Op < 0 || Op == Val;
1112 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
1113 /// VPKUHUM instruction.
1114 /// The ShuffleKind distinguishes between big-endian operations with
1115 /// two different inputs (0), either-endian operations with two identical
1116 /// inputs (1), and little-endian operations with two different inputs (2).
1117 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1118 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1119 SelectionDAG &DAG) {
1120 bool IsLE = DAG.getDataLayout().isLittleEndian();
1121 if (ShuffleKind == 0) {
1124 for (unsigned i = 0; i != 16; ++i)
1125 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
1127 } else if (ShuffleKind == 2) {
1130 for (unsigned i = 0; i != 16; ++i)
1131 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
1133 } else if (ShuffleKind == 1) {
1134 unsigned j = IsLE ? 0 : 1;
1135 for (unsigned i = 0; i != 8; ++i)
1136 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
1137 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
1143 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
1144 /// VPKUWUM instruction.
1145 /// The ShuffleKind distinguishes between big-endian operations with
1146 /// two different inputs (0), either-endian operations with two identical
1147 /// inputs (1), and little-endian operations with two different inputs (2).
1148 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1149 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1150 SelectionDAG &DAG) {
1151 bool IsLE = DAG.getDataLayout().isLittleEndian();
1152 if (ShuffleKind == 0) {
1155 for (unsigned i = 0; i != 16; i += 2)
1156 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
1157 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
1159 } else if (ShuffleKind == 2) {
1162 for (unsigned i = 0; i != 16; i += 2)
1163 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1164 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
1166 } else if (ShuffleKind == 1) {
1167 unsigned j = IsLE ? 0 : 2;
1168 for (unsigned i = 0; i != 8; i += 2)
1169 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1170 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1171 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1172 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
1178 /// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
1179 /// VPKUDUM instruction, AND the VPKUDUM instruction exists for the
1180 /// current subtarget.
1182 /// The ShuffleKind distinguishes between big-endian operations with
1183 /// two different inputs (0), either-endian operations with two identical
1184 /// inputs (1), and little-endian operations with two different inputs (2).
1185 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1186 bool PPC::isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1187 SelectionDAG &DAG) {
1188 const PPCSubtarget& Subtarget =
1189 static_cast<const PPCSubtarget&>(DAG.getSubtarget());
1190 if (!Subtarget.hasP8Vector())
1193 bool IsLE = DAG.getDataLayout().isLittleEndian();
1194 if (ShuffleKind == 0) {
1197 for (unsigned i = 0; i != 16; i += 4)
1198 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+4) ||
1199 !isConstantOrUndef(N->getMaskElt(i+1), i*2+5) ||
1200 !isConstantOrUndef(N->getMaskElt(i+2), i*2+6) ||
1201 !isConstantOrUndef(N->getMaskElt(i+3), i*2+7))
1203 } else if (ShuffleKind == 2) {
1206 for (unsigned i = 0; i != 16; i += 4)
1207 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1208 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1) ||
1209 !isConstantOrUndef(N->getMaskElt(i+2), i*2+2) ||
1210 !isConstantOrUndef(N->getMaskElt(i+3), i*2+3))
1212 } else if (ShuffleKind == 1) {
1213 unsigned j = IsLE ? 0 : 4;
1214 for (unsigned i = 0; i != 8; i += 4)
1215 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1216 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1217 !isConstantOrUndef(N->getMaskElt(i+2), i*2+j+2) ||
1218 !isConstantOrUndef(N->getMaskElt(i+3), i*2+j+3) ||
1219 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1220 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1) ||
1221 !isConstantOrUndef(N->getMaskElt(i+10), i*2+j+2) ||
1222 !isConstantOrUndef(N->getMaskElt(i+11), i*2+j+3))
1228 /// isVMerge - Common function, used to match vmrg* shuffles.
1230 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
1231 unsigned LHSStart, unsigned RHSStart) {
1232 if (N->getValueType(0) != MVT::v16i8)
1234 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
1235 "Unsupported merge size!");
1237 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
1238 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
1239 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
1240 LHSStart+j+i*UnitSize) ||
1241 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
1242 RHSStart+j+i*UnitSize))
1248 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
1249 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
1250 /// The ShuffleKind distinguishes between big-endian merges with two
1251 /// different inputs (0), either-endian merges with two identical inputs (1),
1252 /// and little-endian merges with two different inputs (2). For the latter,
1253 /// the input operands are swapped (see PPCInstrAltivec.td).
1254 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1255 unsigned ShuffleKind, SelectionDAG &DAG) {
1256 if (DAG.getDataLayout().isLittleEndian()) {
1257 if (ShuffleKind == 1) // unary
1258 return isVMerge(N, UnitSize, 0, 0);
1259 else if (ShuffleKind == 2) // swapped
1260 return isVMerge(N, UnitSize, 0, 16);
1264 if (ShuffleKind == 1) // unary
1265 return isVMerge(N, UnitSize, 8, 8);
1266 else if (ShuffleKind == 0) // normal
1267 return isVMerge(N, UnitSize, 8, 24);
1273 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
1274 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
1275 /// The ShuffleKind distinguishes between big-endian merges with two
1276 /// different inputs (0), either-endian merges with two identical inputs (1),
1277 /// and little-endian merges with two different inputs (2). For the latter,
1278 /// the input operands are swapped (see PPCInstrAltivec.td).
1279 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1280 unsigned ShuffleKind, SelectionDAG &DAG) {
1281 if (DAG.getDataLayout().isLittleEndian()) {
1282 if (ShuffleKind == 1) // unary
1283 return isVMerge(N, UnitSize, 8, 8);
1284 else if (ShuffleKind == 2) // swapped
1285 return isVMerge(N, UnitSize, 8, 24);
1289 if (ShuffleKind == 1) // unary
1290 return isVMerge(N, UnitSize, 0, 0);
1291 else if (ShuffleKind == 0) // normal
1292 return isVMerge(N, UnitSize, 0, 16);
1299 * \brief Common function used to match vmrgew and vmrgow shuffles
1301 * The indexOffset determines whether to look for even or odd words in
1302 * the shuffle mask. This is based on the of the endianness of the target
1305 * - Use offset of 0 to check for odd elements
1306 * - Use offset of 4 to check for even elements
1308 * - Use offset of 0 to check for even elements
1309 * - Use offset of 4 to check for odd elements
1310 * A detailed description of the vector element ordering for little endian and
1311 * big endian can be found at
1312 * http://www.ibm.com/developerworks/library/l-ibm-xl-c-cpp-compiler/index.html
1313 * Targeting your applications - what little endian and big endian IBM XL C/C++
1314 * compiler differences mean to you
1316 * The mask to the shuffle vector instruction specifies the indices of the
1317 * elements from the two input vectors to place in the result. The elements are
1318 * numbered in array-access order, starting with the first vector. These vectors
1319 * are always of type v16i8, thus each vector will contain 16 elements of size
1320 * 8. More info on the shuffle vector can be found in the
1321 * http://llvm.org/docs/LangRef.html#shufflevector-instruction
1322 * Language Reference.
1324 * The RHSStartValue indicates whether the same input vectors are used (unary)
1325 * or two different input vectors are used, based on the following:
1326 * - If the instruction uses the same vector for both inputs, the range of the
1327 * indices will be 0 to 15. In this case, the RHSStart value passed should
1329 * - If the instruction has two different vectors then the range of the
1330 * indices will be 0 to 31. In this case, the RHSStart value passed should
1331 * be 16 (indices 0-15 specify elements in the first vector while indices 16
1332 * to 31 specify elements in the second vector).
1334 * \param[in] N The shuffle vector SD Node to analyze
1335 * \param[in] IndexOffset Specifies whether to look for even or odd elements
1336 * \param[in] RHSStartValue Specifies the starting index for the righthand input
1337 * vector to the shuffle_vector instruction
1338 * \return true iff this shuffle vector represents an even or odd word merge
1340 static bool isVMerge(ShuffleVectorSDNode *N, unsigned IndexOffset,
1341 unsigned RHSStartValue) {
1342 if (N->getValueType(0) != MVT::v16i8)
1345 for (unsigned i = 0; i < 2; ++i)
1346 for (unsigned j = 0; j < 4; ++j)
1347 if (!isConstantOrUndef(N->getMaskElt(i*4+j),
1348 i*RHSStartValue+j+IndexOffset) ||
1349 !isConstantOrUndef(N->getMaskElt(i*4+j+8),
1350 i*RHSStartValue+j+IndexOffset+8))
1356 * \brief Determine if the specified shuffle mask is suitable for the vmrgew or
1357 * vmrgow instructions.
1359 * \param[in] N The shuffle vector SD Node to analyze
1360 * \param[in] CheckEven Check for an even merge (true) or an odd merge (false)
1361 * \param[in] ShuffleKind Identify the type of merge:
1362 * - 0 = big-endian merge with two different inputs;
1363 * - 1 = either-endian merge with two identical inputs;
1364 * - 2 = little-endian merge with two different inputs (inputs are swapped for
1365 * little-endian merges).
1366 * \param[in] DAG The current SelectionDAG
1367 * \return true iff this shuffle mask
1369 bool PPC::isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven,
1370 unsigned ShuffleKind, SelectionDAG &DAG) {
1371 if (DAG.getDataLayout().isLittleEndian()) {
1372 unsigned indexOffset = CheckEven ? 4 : 0;
1373 if (ShuffleKind == 1) // Unary
1374 return isVMerge(N, indexOffset, 0);
1375 else if (ShuffleKind == 2) // swapped
1376 return isVMerge(N, indexOffset, 16);
1381 unsigned indexOffset = CheckEven ? 0 : 4;
1382 if (ShuffleKind == 1) // Unary
1383 return isVMerge(N, indexOffset, 0);
1384 else if (ShuffleKind == 0) // Normal
1385 return isVMerge(N, indexOffset, 16);
1392 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
1393 /// amount, otherwise return -1.
1394 /// The ShuffleKind distinguishes between big-endian operations with two
1395 /// different inputs (0), either-endian operations with two identical inputs
1396 /// (1), and little-endian operations with two different inputs (2). For the
1397 /// latter, the input operands are swapped (see PPCInstrAltivec.td).
1398 int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
1399 SelectionDAG &DAG) {
1400 if (N->getValueType(0) != MVT::v16i8)
1403 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1405 // Find the first non-undef value in the shuffle mask.
1407 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
1410 if (i == 16) return -1; // all undef.
1412 // Otherwise, check to see if the rest of the elements are consecutively
1413 // numbered from this value.
1414 unsigned ShiftAmt = SVOp->getMaskElt(i);
1415 if (ShiftAmt < i) return -1;
1418 bool isLE = DAG.getDataLayout().isLittleEndian();
1420 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
1421 // Check the rest of the elements to see if they are consecutive.
1422 for (++i; i != 16; ++i)
1423 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1425 } else if (ShuffleKind == 1) {
1426 // Check the rest of the elements to see if they are consecutive.
1427 for (++i; i != 16; ++i)
1428 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1434 ShiftAmt = 16 - ShiftAmt;
1439 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1440 /// specifies a splat of a single element that is suitable for input to
1441 /// VSPLTB/VSPLTH/VSPLTW.
1442 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1443 assert(N->getValueType(0) == MVT::v16i8 &&
1444 (EltSize == 1 || EltSize == 2 || EltSize == 4));
1446 // The consecutive indices need to specify an element, not part of two
1447 // different elements. So abandon ship early if this isn't the case.
1448 if (N->getMaskElt(0) % EltSize != 0)
1451 // This is a splat operation if each element of the permute is the same, and
1452 // if the value doesn't reference the second vector.
1453 unsigned ElementBase = N->getMaskElt(0);
1455 // FIXME: Handle UNDEF elements too!
1456 if (ElementBase >= 16)
1459 // Check that the indices are consecutive, in the case of a multi-byte element
1460 // splatted with a v16i8 mask.
1461 for (unsigned i = 1; i != EltSize; ++i)
1462 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1465 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1466 if (N->getMaskElt(i) < 0) continue;
1467 for (unsigned j = 0; j != EltSize; ++j)
1468 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1474 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1475 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1476 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1477 SelectionDAG &DAG) {
1478 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1479 assert(isSplatShuffleMask(SVOp, EltSize));
1480 if (DAG.getDataLayout().isLittleEndian())
1481 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1483 return SVOp->getMaskElt(0) / EltSize;
1486 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1487 /// by using a vspltis[bhw] instruction of the specified element size, return
1488 /// the constant being splatted. The ByteSize field indicates the number of
1489 /// bytes of each element [124] -> [bhw].
1490 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1491 SDValue OpVal(nullptr, 0);
1493 // If ByteSize of the splat is bigger than the element size of the
1494 // build_vector, then we have a case where we are checking for a splat where
1495 // multiple elements of the buildvector are folded together into a single
1496 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1497 unsigned EltSize = 16/N->getNumOperands();
1498 if (EltSize < ByteSize) {
1499 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1500 SDValue UniquedVals[4];
1501 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1503 // See if all of the elements in the buildvector agree across.
1504 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1505 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1506 // If the element isn't a constant, bail fully out.
1507 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1510 if (!UniquedVals[i&(Multiple-1)].getNode())
1511 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1512 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1513 return SDValue(); // no match.
1516 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1517 // either constant or undef values that are identical for each chunk. See
1518 // if these chunks can form into a larger vspltis*.
1520 // Check to see if all of the leading entries are either 0 or -1. If
1521 // neither, then this won't fit into the immediate field.
1522 bool LeadingZero = true;
1523 bool LeadingOnes = true;
1524 for (unsigned i = 0; i != Multiple-1; ++i) {
1525 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1527 LeadingZero &= isNullConstant(UniquedVals[i]);
1528 LeadingOnes &= isAllOnesConstant(UniquedVals[i]);
1530 // Finally, check the least significant entry.
1532 if (!UniquedVals[Multiple-1].getNode())
1533 return DAG.getTargetConstant(0, SDLoc(N), MVT::i32); // 0,0,0,undef
1534 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1535 if (Val < 16) // 0,0,0,4 -> vspltisw(4)
1536 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
1539 if (!UniquedVals[Multiple-1].getNode())
1540 return DAG.getTargetConstant(~0U, SDLoc(N), MVT::i32); // -1,-1,-1,undef
1541 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1542 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1543 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
1549 // Check to see if this buildvec has a single non-undef value in its elements.
1550 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1551 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1552 if (!OpVal.getNode())
1553 OpVal = N->getOperand(i);
1554 else if (OpVal != N->getOperand(i))
1558 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1560 unsigned ValSizeInBytes = EltSize;
1562 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1563 Value = CN->getZExtValue();
1564 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1565 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1566 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1569 // If the splat value is larger than the element value, then we can never do
1570 // this splat. The only case that we could fit the replicated bits into our
1571 // immediate field for would be zero, and we prefer to use vxor for it.
1572 if (ValSizeInBytes < ByteSize) return SDValue();
1574 // If the element value is larger than the splat value, check if it consists
1575 // of a repeated bit pattern of size ByteSize.
1576 if (!APInt(ValSizeInBytes * 8, Value).isSplat(ByteSize * 8))
1579 // Properly sign extend the value.
1580 int MaskVal = SignExtend32(Value, ByteSize * 8);
1582 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1583 if (MaskVal == 0) return SDValue();
1585 // Finally, if this value fits in a 5 bit sext field, return it
1586 if (SignExtend32<5>(MaskVal) == MaskVal)
1587 return DAG.getTargetConstant(MaskVal, SDLoc(N), MVT::i32);
1591 /// isQVALIGNIShuffleMask - If this is a qvaligni shuffle mask, return the shift
1592 /// amount, otherwise return -1.
1593 int PPC::isQVALIGNIShuffleMask(SDNode *N) {
1594 EVT VT = N->getValueType(0);
1595 if (VT != MVT::v4f64 && VT != MVT::v4f32 && VT != MVT::v4i1)
1598 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1600 // Find the first non-undef value in the shuffle mask.
1602 for (i = 0; i != 4 && SVOp->getMaskElt(i) < 0; ++i)
1605 if (i == 4) return -1; // all undef.
1607 // Otherwise, check to see if the rest of the elements are consecutively
1608 // numbered from this value.
1609 unsigned ShiftAmt = SVOp->getMaskElt(i);
1610 if (ShiftAmt < i) return -1;
1613 // Check the rest of the elements to see if they are consecutive.
1614 for (++i; i != 4; ++i)
1615 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1621 //===----------------------------------------------------------------------===//
1622 // Addressing Mode Selection
1623 //===----------------------------------------------------------------------===//
1625 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1626 /// or 64-bit immediate, and if the value can be accurately represented as a
1627 /// sign extension from a 16-bit value. If so, this returns true and the
1629 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1630 if (!isa<ConstantSDNode>(N))
1633 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1634 if (N->getValueType(0) == MVT::i32)
1635 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1637 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1639 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1640 return isIntS16Immediate(Op.getNode(), Imm);
1643 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1644 /// can be represented as an indexed [r+r] operation. Returns false if it
1645 /// can be more efficiently represented with [r+imm].
1646 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1648 SelectionDAG &DAG) const {
1650 if (N.getOpcode() == ISD::ADD) {
1651 if (isIntS16Immediate(N.getOperand(1), imm))
1652 return false; // r+i
1653 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1654 return false; // r+i
1656 Base = N.getOperand(0);
1657 Index = N.getOperand(1);
1659 } else if (N.getOpcode() == ISD::OR) {
1660 if (isIntS16Immediate(N.getOperand(1), imm))
1661 return false; // r+i can fold it if we can.
1663 // If this is an or of disjoint bitfields, we can codegen this as an add
1664 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1666 APInt LHSKnownZero, LHSKnownOne;
1667 APInt RHSKnownZero, RHSKnownOne;
1668 DAG.computeKnownBits(N.getOperand(0),
1669 LHSKnownZero, LHSKnownOne);
1671 if (LHSKnownZero.getBoolValue()) {
1672 DAG.computeKnownBits(N.getOperand(1),
1673 RHSKnownZero, RHSKnownOne);
1674 // If all of the bits are known zero on the LHS or RHS, the add won't
1676 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1677 Base = N.getOperand(0);
1678 Index = N.getOperand(1);
1687 // If we happen to be doing an i64 load or store into a stack slot that has
1688 // less than a 4-byte alignment, then the frame-index elimination may need to
1689 // use an indexed load or store instruction (because the offset may not be a
1690 // multiple of 4). The extra register needed to hold the offset comes from the
1691 // register scavenger, and it is possible that the scavenger will need to use
1692 // an emergency spill slot. As a result, we need to make sure that a spill slot
1693 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1695 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1696 // FIXME: This does not handle the LWA case.
1700 // NOTE: We'll exclude negative FIs here, which come from argument
1701 // lowering, because there are no known test cases triggering this problem
1702 // using packed structures (or similar). We can remove this exclusion if
1703 // we find such a test case. The reason why this is so test-case driven is
1704 // because this entire 'fixup' is only to prevent crashes (from the
1705 // register scavenger) on not-really-valid inputs. For example, if we have:
1707 // %b = bitcast i1* %a to i64*
1708 // store i64* a, i64 b
1709 // then the store should really be marked as 'align 1', but is not. If it
1710 // were marked as 'align 1' then the indexed form would have been
1711 // instruction-selected initially, and the problem this 'fixup' is preventing
1712 // won't happen regardless.
1716 MachineFunction &MF = DAG.getMachineFunction();
1717 MachineFrameInfo *MFI = MF.getFrameInfo();
1719 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1723 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1724 FuncInfo->setHasNonRISpills();
1727 /// Returns true if the address N can be represented by a base register plus
1728 /// a signed 16-bit displacement [r+imm], and if it is not better
1729 /// represented as reg+reg. If Aligned is true, only accept displacements
1730 /// suitable for STD and friends, i.e. multiples of 4.
1731 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1734 bool Aligned) const {
1735 // FIXME dl should come from parent load or store, not from address
1737 // If this can be more profitably realized as r+r, fail.
1738 if (SelectAddressRegReg(N, Disp, Base, DAG))
1741 if (N.getOpcode() == ISD::ADD) {
1743 if (isIntS16Immediate(N.getOperand(1), imm) &&
1744 (!Aligned || (imm & 3) == 0)) {
1745 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
1746 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1747 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1748 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1750 Base = N.getOperand(0);
1752 return true; // [r+i]
1753 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1754 // Match LOAD (ADD (X, Lo(G))).
1755 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1756 && "Cannot handle constant offsets yet!");
1757 Disp = N.getOperand(1).getOperand(0); // The global address.
1758 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1759 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1760 Disp.getOpcode() == ISD::TargetConstantPool ||
1761 Disp.getOpcode() == ISD::TargetJumpTable);
1762 Base = N.getOperand(0);
1763 return true; // [&g+r]
1765 } else if (N.getOpcode() == ISD::OR) {
1767 if (isIntS16Immediate(N.getOperand(1), imm) &&
1768 (!Aligned || (imm & 3) == 0)) {
1769 // If this is an or of disjoint bitfields, we can codegen this as an add
1770 // (for better address arithmetic) if the LHS and RHS of the OR are
1771 // provably disjoint.
1772 APInt LHSKnownZero, LHSKnownOne;
1773 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1775 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1776 // If all of the bits are known zero on the LHS or RHS, the add won't
1778 if (FrameIndexSDNode *FI =
1779 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1780 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1781 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1783 Base = N.getOperand(0);
1785 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
1789 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1790 // Loading from a constant address.
1792 // If this address fits entirely in a 16-bit sext immediate field, codegen
1795 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1796 Disp = DAG.getTargetConstant(Imm, dl, CN->getValueType(0));
1797 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1798 CN->getValueType(0));
1802 // Handle 32-bit sext immediates with LIS + addr mode.
1803 if ((CN->getValueType(0) == MVT::i32 ||
1804 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1805 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1806 int Addr = (int)CN->getZExtValue();
1808 // Otherwise, break this down into an LIS + disp.
1809 Disp = DAG.getTargetConstant((short)Addr, dl, MVT::i32);
1811 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, dl,
1813 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1814 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1819 Disp = DAG.getTargetConstant(0, dl, getPointerTy(DAG.getDataLayout()));
1820 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1821 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1822 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1825 return true; // [r+0]
1828 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1829 /// represented as an indexed [r+r] operation.
1830 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1832 SelectionDAG &DAG) const {
1833 // Check to see if we can easily represent this as an [r+r] address. This
1834 // will fail if it thinks that the address is more profitably represented as
1835 // reg+imm, e.g. where imm = 0.
1836 if (SelectAddressRegReg(N, Base, Index, DAG))
1839 // If the operand is an addition, always emit this as [r+r], since this is
1840 // better (for code size, and execution, as the memop does the add for free)
1841 // than emitting an explicit add.
1842 if (N.getOpcode() == ISD::ADD) {
1843 Base = N.getOperand(0);
1844 Index = N.getOperand(1);
1848 // Otherwise, do it the hard way, using R0 as the base register.
1849 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1855 /// getPreIndexedAddressParts - returns true by value, base pointer and
1856 /// offset pointer and addressing mode by reference if the node's address
1857 /// can be legally represented as pre-indexed load / store address.
1858 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1860 ISD::MemIndexedMode &AM,
1861 SelectionDAG &DAG) const {
1862 if (DisablePPCPreinc) return false;
1868 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1869 Ptr = LD->getBasePtr();
1870 VT = LD->getMemoryVT();
1871 Alignment = LD->getAlignment();
1872 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1873 Ptr = ST->getBasePtr();
1874 VT = ST->getMemoryVT();
1875 Alignment = ST->getAlignment();
1880 // PowerPC doesn't have preinc load/store instructions for vectors (except
1881 // for QPX, which does have preinc r+r forms).
1882 if (VT.isVector()) {
1883 if (!Subtarget.hasQPX() || (VT != MVT::v4f64 && VT != MVT::v4f32)) {
1885 } else if (SelectAddressRegRegOnly(Ptr, Offset, Base, DAG)) {
1891 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1893 // Common code will reject creating a pre-inc form if the base pointer
1894 // is a frame index, or if N is a store and the base pointer is either
1895 // the same as or a predecessor of the value being stored. Check for
1896 // those situations here, and try with swapped Base/Offset instead.
1899 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1902 SDValue Val = cast<StoreSDNode>(N)->getValue();
1903 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1908 std::swap(Base, Offset);
1914 // LDU/STU can only handle immediates that are a multiple of 4.
1915 if (VT != MVT::i64) {
1916 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1919 // LDU/STU need an address with at least 4-byte alignment.
1923 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1927 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1928 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1929 // sext i32 to i64 when addr mode is r+i.
1930 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1931 LD->getExtensionType() == ISD::SEXTLOAD &&
1932 isa<ConstantSDNode>(Offset))
1940 //===----------------------------------------------------------------------===//
1941 // LowerOperation implementation
1942 //===----------------------------------------------------------------------===//
1944 /// GetLabelAccessInfo - Return true if we should reference labels using a
1945 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1946 static bool GetLabelAccessInfo(const TargetMachine &TM,
1947 const PPCSubtarget &Subtarget,
1948 unsigned &HiOpFlags, unsigned &LoOpFlags,
1949 const GlobalValue *GV = nullptr) {
1950 HiOpFlags = PPCII::MO_HA;
1951 LoOpFlags = PPCII::MO_LO;
1953 // Don't use the pic base if not in PIC relocation model.
1954 bool isPIC = TM.getRelocationModel() == Reloc::PIC_;
1957 HiOpFlags |= PPCII::MO_PIC_FLAG;
1958 LoOpFlags |= PPCII::MO_PIC_FLAG;
1961 // If this is a reference to a global value that requires a non-lazy-ptr, make
1962 // sure that instruction lowering adds it.
1963 if (GV && Subtarget.hasLazyResolverStub(GV)) {
1964 HiOpFlags |= PPCII::MO_NLP_FLAG;
1965 LoOpFlags |= PPCII::MO_NLP_FLAG;
1967 if (GV->hasHiddenVisibility()) {
1968 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1969 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1976 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1977 SelectionDAG &DAG) {
1979 EVT PtrVT = HiPart.getValueType();
1980 SDValue Zero = DAG.getConstant(0, DL, PtrVT);
1982 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1983 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1985 // With PIC, the first instruction is actually "GR+hi(&G)".
1987 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1988 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1990 // Generate non-pic code that has direct accesses to the constant pool.
1991 // The address of the global is just (hi(&g)+lo(&g)).
1992 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1995 static void setUsesTOCBasePtr(MachineFunction &MF) {
1996 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1997 FuncInfo->setUsesTOCBasePtr();
2000 static void setUsesTOCBasePtr(SelectionDAG &DAG) {
2001 setUsesTOCBasePtr(DAG.getMachineFunction());
2004 static SDValue getTOCEntry(SelectionDAG &DAG, SDLoc dl, bool Is64Bit,
2006 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2007 SDValue Reg = Is64Bit ? DAG.getRegister(PPC::X2, VT) :
2008 DAG.getNode(PPCISD::GlobalBaseReg, dl, VT);
2010 SDValue Ops[] = { GA, Reg };
2011 return DAG.getMemIntrinsicNode(
2012 PPCISD::TOC_ENTRY, dl, DAG.getVTList(VT, MVT::Other), Ops, VT,
2013 MachinePointerInfo::getGOT(DAG.getMachineFunction()), 0, false, true,
2017 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
2018 SelectionDAG &DAG) const {
2019 EVT PtrVT = Op.getValueType();
2020 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2021 const Constant *C = CP->getConstVal();
2023 // 64-bit SVR4 ABI code is always position-independent.
2024 // The actual address of the GlobalValue is stored in the TOC.
2025 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2026 setUsesTOCBasePtr(DAG);
2027 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
2028 return getTOCEntry(DAG, SDLoc(CP), true, GA);
2031 unsigned MOHiFlag, MOLoFlag;
2033 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
2035 if (isPIC && Subtarget.isSVR4ABI()) {
2036 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
2037 PPCII::MO_PIC_FLAG);
2038 return getTOCEntry(DAG, SDLoc(CP), false, GA);
2042 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
2044 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
2045 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
2048 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
2049 EVT PtrVT = Op.getValueType();
2050 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
2052 // 64-bit SVR4 ABI code is always position-independent.
2053 // The actual address of the GlobalValue is stored in the TOC.
2054 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2055 setUsesTOCBasePtr(DAG);
2056 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
2057 return getTOCEntry(DAG, SDLoc(JT), true, GA);
2060 unsigned MOHiFlag, MOLoFlag;
2062 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
2064 if (isPIC && Subtarget.isSVR4ABI()) {
2065 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
2066 PPCII::MO_PIC_FLAG);
2067 return getTOCEntry(DAG, SDLoc(GA), false, GA);
2070 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
2071 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
2072 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
2075 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
2076 SelectionDAG &DAG) const {
2077 EVT PtrVT = Op.getValueType();
2078 BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
2079 const BlockAddress *BA = BASDN->getBlockAddress();
2081 // 64-bit SVR4 ABI code is always position-independent.
2082 // The actual BlockAddress is stored in the TOC.
2083 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2084 setUsesTOCBasePtr(DAG);
2085 SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
2086 return getTOCEntry(DAG, SDLoc(BASDN), true, GA);
2089 unsigned MOHiFlag, MOLoFlag;
2091 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
2092 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
2093 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
2094 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
2097 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
2098 SelectionDAG &DAG) const {
2100 // FIXME: TLS addresses currently use medium model code sequences,
2101 // which is the most useful form. Eventually support for small and
2102 // large models could be added if users need it, at the cost of
2103 // additional complexity.
2104 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2105 if (DAG.getTarget().Options.EmulatedTLS)
2106 return LowerToTLSEmulatedModel(GA, DAG);
2109 const GlobalValue *GV = GA->getGlobal();
2110 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2111 bool is64bit = Subtarget.isPPC64();
2112 const Module *M = DAG.getMachineFunction().getFunction()->getParent();
2113 PICLevel::Level picLevel = M->getPICLevel();
2115 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
2117 if (Model == TLSModel::LocalExec) {
2118 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2119 PPCII::MO_TPREL_HA);
2120 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2121 PPCII::MO_TPREL_LO);
2122 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
2123 is64bit ? MVT::i64 : MVT::i32);
2124 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
2125 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
2128 if (Model == TLSModel::InitialExec) {
2129 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2130 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2134 setUsesTOCBasePtr(DAG);
2135 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2136 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
2137 PtrVT, GOTReg, TGA);
2139 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
2140 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
2141 PtrVT, TGA, GOTPtr);
2142 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
2145 if (Model == TLSModel::GeneralDynamic) {
2146 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2149 setUsesTOCBasePtr(DAG);
2150 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2151 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
2154 if (picLevel == PICLevel::Small)
2155 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
2157 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
2159 return DAG.getNode(PPCISD::ADDI_TLSGD_L_ADDR, dl, PtrVT,
2163 if (Model == TLSModel::LocalDynamic) {
2164 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2167 setUsesTOCBasePtr(DAG);
2168 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2169 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
2172 if (picLevel == PICLevel::Small)
2173 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
2175 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
2177 SDValue TLSAddr = DAG.getNode(PPCISD::ADDI_TLSLD_L_ADDR, dl,
2178 PtrVT, GOTPtr, TGA, TGA);
2179 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl,
2180 PtrVT, TLSAddr, TGA);
2181 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
2184 llvm_unreachable("Unknown TLS model!");
2187 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
2188 SelectionDAG &DAG) const {
2189 EVT PtrVT = Op.getValueType();
2190 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
2192 const GlobalValue *GV = GSDN->getGlobal();
2194 // 64-bit SVR4 ABI code is always position-independent.
2195 // The actual address of the GlobalValue is stored in the TOC.
2196 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2197 setUsesTOCBasePtr(DAG);
2198 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
2199 return getTOCEntry(DAG, DL, true, GA);
2202 unsigned MOHiFlag, MOLoFlag;
2204 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag, GV);
2206 if (isPIC && Subtarget.isSVR4ABI()) {
2207 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
2209 PPCII::MO_PIC_FLAG);
2210 return getTOCEntry(DAG, DL, false, GA);
2214 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
2216 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
2218 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
2220 // If the global reference is actually to a non-lazy-pointer, we have to do an
2221 // extra load to get the address of the global.
2222 if (MOHiFlag & PPCII::MO_NLP_FLAG)
2223 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
2224 false, false, false, 0);
2228 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
2229 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2232 if (Op.getValueType() == MVT::v2i64) {
2233 // When the operands themselves are v2i64 values, we need to do something
2234 // special because VSX has no underlying comparison operations for these.
2235 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
2236 // Equality can be handled by casting to the legal type for Altivec
2237 // comparisons, everything else needs to be expanded.
2238 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
2239 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
2240 DAG.getSetCC(dl, MVT::v4i32,
2241 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
2242 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
2249 // We handle most of these in the usual way.
2253 // If we're comparing for equality to zero, expose the fact that this is
2254 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
2255 // fold the new nodes.
2256 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
2257 if (C->isNullValue() && CC == ISD::SETEQ) {
2258 EVT VT = Op.getOperand(0).getValueType();
2259 SDValue Zext = Op.getOperand(0);
2260 if (VT.bitsLT(MVT::i32)) {
2262 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
2264 unsigned Log2b = Log2_32(VT.getSizeInBits());
2265 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
2266 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
2267 DAG.getConstant(Log2b, dl, MVT::i32));
2268 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
2270 // Leave comparisons against 0 and -1 alone for now, since they're usually
2271 // optimized. FIXME: revisit this when we can custom lower all setcc
2273 if (C->isAllOnesValue() || C->isNullValue())
2277 // If we have an integer seteq/setne, turn it into a compare against zero
2278 // by xor'ing the rhs with the lhs, which is faster than setting a
2279 // condition register, reading it back out, and masking the correct bit. The
2280 // normal approach here uses sub to do this instead of xor. Using xor exposes
2281 // the result to other bit-twiddling opportunities.
2282 EVT LHSVT = Op.getOperand(0).getValueType();
2283 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
2284 EVT VT = Op.getValueType();
2285 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
2287 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, dl, LHSVT), CC);
2292 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
2293 const PPCSubtarget &Subtarget) const {
2294 SDNode *Node = Op.getNode();
2295 EVT VT = Node->getValueType(0);
2296 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
2297 SDValue InChain = Node->getOperand(0);
2298 SDValue VAListPtr = Node->getOperand(1);
2299 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2302 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
2305 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
2306 VAListPtr, MachinePointerInfo(SV), MVT::i8,
2307 false, false, false, 0);
2308 InChain = GprIndex.getValue(1);
2310 if (VT == MVT::i64) {
2311 // Check if GprIndex is even
2312 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
2313 DAG.getConstant(1, dl, MVT::i32));
2314 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
2315 DAG.getConstant(0, dl, MVT::i32), ISD::SETNE);
2316 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
2317 DAG.getConstant(1, dl, MVT::i32));
2318 // Align GprIndex to be even if it isn't
2319 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
2323 // fpr index is 1 byte after gpr
2324 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2325 DAG.getConstant(1, dl, MVT::i32));
2328 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
2329 FprPtr, MachinePointerInfo(SV), MVT::i8,
2330 false, false, false, 0);
2331 InChain = FprIndex.getValue(1);
2333 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2334 DAG.getConstant(8, dl, MVT::i32));
2336 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2337 DAG.getConstant(4, dl, MVT::i32));
2340 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
2341 MachinePointerInfo(), false, false,
2343 InChain = OverflowArea.getValue(1);
2345 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
2346 MachinePointerInfo(), false, false,
2348 InChain = RegSaveArea.getValue(1);
2350 // select overflow_area if index > 8
2351 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
2352 DAG.getConstant(8, dl, MVT::i32), ISD::SETLT);
2354 // adjustment constant gpr_index * 4/8
2355 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
2356 VT.isInteger() ? GprIndex : FprIndex,
2357 DAG.getConstant(VT.isInteger() ? 4 : 8, dl,
2360 // OurReg = RegSaveArea + RegConstant
2361 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
2364 // Floating types are 32 bytes into RegSaveArea
2365 if (VT.isFloatingPoint())
2366 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
2367 DAG.getConstant(32, dl, MVT::i32));
2369 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
2370 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
2371 VT.isInteger() ? GprIndex : FprIndex,
2372 DAG.getConstant(VT == MVT::i64 ? 2 : 1, dl,
2375 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
2376 VT.isInteger() ? VAListPtr : FprPtr,
2377 MachinePointerInfo(SV),
2378 MVT::i8, false, false, 0);
2380 // determine if we should load from reg_save_area or overflow_area
2381 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
2383 // increase overflow_area by 4/8 if gpr/fpr > 8
2384 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
2385 DAG.getConstant(VT.isInteger() ? 4 : 8,
2388 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
2391 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
2393 MachinePointerInfo(),
2394 MVT::i32, false, false, 0);
2396 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
2397 false, false, false, 0);
2400 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
2401 const PPCSubtarget &Subtarget) const {
2402 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
2404 // We have to copy the entire va_list struct:
2405 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
2406 return DAG.getMemcpy(Op.getOperand(0), Op,
2407 Op.getOperand(1), Op.getOperand(2),
2408 DAG.getConstant(12, SDLoc(Op), MVT::i32), 8, false, true,
2409 false, MachinePointerInfo(), MachinePointerInfo());
2412 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
2413 SelectionDAG &DAG) const {
2414 return Op.getOperand(0);
2417 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
2418 SelectionDAG &DAG) const {
2419 SDValue Chain = Op.getOperand(0);
2420 SDValue Trmp = Op.getOperand(1); // trampoline
2421 SDValue FPtr = Op.getOperand(2); // nested function
2422 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
2425 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
2426 bool isPPC64 = (PtrVT == MVT::i64);
2427 Type *IntPtrTy = DAG.getDataLayout().getIntPtrType(*DAG.getContext());
2429 TargetLowering::ArgListTy Args;
2430 TargetLowering::ArgListEntry Entry;
2432 Entry.Ty = IntPtrTy;
2433 Entry.Node = Trmp; Args.push_back(Entry);
2435 // TrampSize == (isPPC64 ? 48 : 40);
2436 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, dl,
2437 isPPC64 ? MVT::i64 : MVT::i32);
2438 Args.push_back(Entry);
2440 Entry.Node = FPtr; Args.push_back(Entry);
2441 Entry.Node = Nest; Args.push_back(Entry);
2443 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
2444 TargetLowering::CallLoweringInfo CLI(DAG);
2445 CLI.setDebugLoc(dl).setChain(Chain)
2446 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
2447 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
2448 std::move(Args), 0);
2450 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2451 return CallResult.second;
2454 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
2455 const PPCSubtarget &Subtarget) const {
2456 MachineFunction &MF = DAG.getMachineFunction();
2457 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2461 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
2462 // vastart just stores the address of the VarArgsFrameIndex slot into the
2463 // memory location argument.
2464 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
2465 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2466 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2467 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2468 MachinePointerInfo(SV),
2472 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
2473 // We suppose the given va_list is already allocated.
2476 // char gpr; /* index into the array of 8 GPRs
2477 // * stored in the register save area
2478 // * gpr=0 corresponds to r3,
2479 // * gpr=1 to r4, etc.
2481 // char fpr; /* index into the array of 8 FPRs
2482 // * stored in the register save area
2483 // * fpr=0 corresponds to f1,
2484 // * fpr=1 to f2, etc.
2486 // char *overflow_arg_area;
2487 // /* location on stack that holds
2488 // * the next overflow argument
2490 // char *reg_save_area;
2491 // /* where r3:r10 and f1:f8 (if saved)
2496 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), dl, MVT::i32);
2497 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), dl, MVT::i32);
2499 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
2501 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
2503 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2506 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2507 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, dl, PtrVT);
2509 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2510 SDValue ConstStackOffset = DAG.getConstant(StackOffset, dl, PtrVT);
2512 uint64_t FPROffset = 1;
2513 SDValue ConstFPROffset = DAG.getConstant(FPROffset, dl, PtrVT);
2515 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2517 // Store first byte : number of int regs
2518 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
2520 MachinePointerInfo(SV),
2521 MVT::i8, false, false, 0);
2522 uint64_t nextOffset = FPROffset;
2523 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2526 // Store second byte : number of float regs
2527 SDValue secondStore =
2528 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2529 MachinePointerInfo(SV, nextOffset), MVT::i8,
2531 nextOffset += StackOffset;
2532 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2534 // Store second word : arguments given on stack
2535 SDValue thirdStore =
2536 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2537 MachinePointerInfo(SV, nextOffset),
2539 nextOffset += FrameOffset;
2540 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2542 // Store third word : arguments given in registers
2543 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2544 MachinePointerInfo(SV, nextOffset),
2549 #include "PPCGenCallingConv.inc"
2551 // Function whose sole purpose is to kill compiler warnings
2552 // stemming from unused functions included from PPCGenCallingConv.inc.
2553 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2554 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2557 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2558 CCValAssign::LocInfo &LocInfo,
2559 ISD::ArgFlagsTy &ArgFlags,
2564 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2566 CCValAssign::LocInfo &LocInfo,
2567 ISD::ArgFlagsTy &ArgFlags,
2569 static const MCPhysReg ArgRegs[] = {
2570 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2571 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2573 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2575 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
2577 // Skip one register if the first unallocated register has an even register
2578 // number and there are still argument registers available which have not been
2579 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2580 // need to skip a register if RegNum is odd.
2581 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2582 State.AllocateReg(ArgRegs[RegNum]);
2585 // Always return false here, as this function only makes sure that the first
2586 // unallocated register has an odd register number and does not actually
2587 // allocate a register for the current argument.
2591 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2593 CCValAssign::LocInfo &LocInfo,
2594 ISD::ArgFlagsTy &ArgFlags,
2596 static const MCPhysReg ArgRegs[] = {
2597 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2601 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2603 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
2605 // If there is only one Floating-point register left we need to put both f64
2606 // values of a split ppc_fp128 value on the stack.
2607 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2608 State.AllocateReg(ArgRegs[RegNum]);
2611 // Always return false here, as this function only makes sure that the two f64
2612 // values a ppc_fp128 value is split into are both passed in registers or both
2613 // passed on the stack and does not actually allocate a register for the
2614 // current argument.
2618 /// FPR - The set of FP registers that should be allocated for arguments,
2620 static const MCPhysReg FPR[] = {PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5,
2621 PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10,
2622 PPC::F11, PPC::F12, PPC::F13};
2624 /// QFPR - The set of QPX registers that should be allocated for arguments.
2625 static const MCPhysReg QFPR[] = {
2626 PPC::QF1, PPC::QF2, PPC::QF3, PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7,
2627 PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11, PPC::QF12, PPC::QF13};
2629 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2631 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2632 unsigned PtrByteSize) {
2633 unsigned ArgSize = ArgVT.getStoreSize();
2634 if (Flags.isByVal())
2635 ArgSize = Flags.getByValSize();
2637 // Round up to multiples of the pointer size, except for array members,
2638 // which are always packed.
2639 if (!Flags.isInConsecutiveRegs())
2640 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2645 /// CalculateStackSlotAlignment - Calculates the alignment of this argument
2647 static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
2648 ISD::ArgFlagsTy Flags,
2649 unsigned PtrByteSize) {
2650 unsigned Align = PtrByteSize;
2652 // Altivec parameters are padded to a 16 byte boundary.
2653 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2654 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2655 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
2656 ArgVT == MVT::v1i128)
2658 // QPX vector types stored in double-precision are padded to a 32 byte
2660 else if (ArgVT == MVT::v4f64 || ArgVT == MVT::v4i1)
2663 // ByVal parameters are aligned as requested.
2664 if (Flags.isByVal()) {
2665 unsigned BVAlign = Flags.getByValAlign();
2666 if (BVAlign > PtrByteSize) {
2667 if (BVAlign % PtrByteSize != 0)
2669 "ByVal alignment is not a multiple of the pointer size");
2675 // Array members are always packed to their original alignment.
2676 if (Flags.isInConsecutiveRegs()) {
2677 // If the array member was split into multiple registers, the first
2678 // needs to be aligned to the size of the full type. (Except for
2679 // ppcf128, which is only aligned as its f64 components.)
2680 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
2681 Align = OrigVT.getStoreSize();
2683 Align = ArgVT.getStoreSize();
2689 /// CalculateStackSlotUsed - Return whether this argument will use its
2690 /// stack slot (instead of being passed in registers). ArgOffset,
2691 /// AvailableFPRs, and AvailableVRs must hold the current argument
2692 /// position, and will be updated to account for this argument.
2693 static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT,
2694 ISD::ArgFlagsTy Flags,
2695 unsigned PtrByteSize,
2696 unsigned LinkageSize,
2697 unsigned ParamAreaSize,
2698 unsigned &ArgOffset,
2699 unsigned &AvailableFPRs,
2700 unsigned &AvailableVRs, bool HasQPX) {
2701 bool UseMemory = false;
2703 // Respect alignment of argument on the stack.
2705 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
2706 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2707 // If there's no space left in the argument save area, we must
2708 // use memory (this check also catches zero-sized arguments).
2709 if (ArgOffset >= LinkageSize + ParamAreaSize)
2712 // Allocate argument on the stack.
2713 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2714 if (Flags.isInConsecutiveRegsLast())
2715 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2716 // If we overran the argument save area, we must use memory
2717 // (this check catches arguments passed partially in memory)
2718 if (ArgOffset > LinkageSize + ParamAreaSize)
2721 // However, if the argument is actually passed in an FPR or a VR,
2722 // we don't use memory after all.
2723 if (!Flags.isByVal()) {
2724 if (ArgVT == MVT::f32 || ArgVT == MVT::f64 ||
2725 // QPX registers overlap with the scalar FP registers.
2726 (HasQPX && (ArgVT == MVT::v4f32 ||
2727 ArgVT == MVT::v4f64 ||
2728 ArgVT == MVT::v4i1)))
2729 if (AvailableFPRs > 0) {
2733 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2734 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2735 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
2736 ArgVT == MVT::v1i128)
2737 if (AvailableVRs > 0) {
2746 /// EnsureStackAlignment - Round stack frame size up from NumBytes to
2747 /// ensure minimum alignment required for target.
2748 static unsigned EnsureStackAlignment(const PPCFrameLowering *Lowering,
2749 unsigned NumBytes) {
2750 unsigned TargetAlign = Lowering->getStackAlignment();
2751 unsigned AlignMask = TargetAlign - 1;
2752 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2757 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
2758 CallingConv::ID CallConv, bool isVarArg,
2759 const SmallVectorImpl<ISD::InputArg>
2761 SDLoc dl, SelectionDAG &DAG,
2762 SmallVectorImpl<SDValue> &InVals)
2764 if (Subtarget.isSVR4ABI()) {
2765 if (Subtarget.isPPC64())
2766 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2769 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2772 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2778 PPCTargetLowering::LowerFormalArguments_32SVR4(
2780 CallingConv::ID CallConv, bool isVarArg,
2781 const SmallVectorImpl<ISD::InputArg>
2783 SDLoc dl, SelectionDAG &DAG,
2784 SmallVectorImpl<SDValue> &InVals) const {
2786 // 32-bit SVR4 ABI Stack Frame Layout:
2787 // +-----------------------------------+
2788 // +--> | Back chain |
2789 // | +-----------------------------------+
2790 // | | Floating-point register save area |
2791 // | +-----------------------------------+
2792 // | | General register save area |
2793 // | +-----------------------------------+
2794 // | | CR save word |
2795 // | +-----------------------------------+
2796 // | | VRSAVE save word |
2797 // | +-----------------------------------+
2798 // | | Alignment padding |
2799 // | +-----------------------------------+
2800 // | | Vector register save area |
2801 // | +-----------------------------------+
2802 // | | Local variable space |
2803 // | +-----------------------------------+
2804 // | | Parameter list area |
2805 // | +-----------------------------------+
2806 // | | LR save word |
2807 // | +-----------------------------------+
2808 // SP--> +--- | Back chain |
2809 // +-----------------------------------+
2812 // System V Application Binary Interface PowerPC Processor Supplement
2813 // AltiVec Technology Programming Interface Manual
2815 MachineFunction &MF = DAG.getMachineFunction();
2816 MachineFrameInfo *MFI = MF.getFrameInfo();
2817 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2819 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
2820 // Potential tail calls could cause overwriting of argument stack slots.
2821 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2822 (CallConv == CallingConv::Fast));
2823 unsigned PtrByteSize = 4;
2825 // Assign locations to all of the incoming arguments.
2826 SmallVector<CCValAssign, 16> ArgLocs;
2827 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2830 // Reserve space for the linkage area on the stack.
2831 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
2832 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
2834 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2836 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2837 CCValAssign &VA = ArgLocs[i];
2839 // Arguments stored in registers.
2840 if (VA.isRegLoc()) {
2841 const TargetRegisterClass *RC;
2842 EVT ValVT = VA.getValVT();
2844 switch (ValVT.getSimpleVT().SimpleTy) {
2846 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2849 RC = &PPC::GPRCRegClass;
2852 if (Subtarget.hasP8Vector())
2853 RC = &PPC::VSSRCRegClass;
2855 RC = &PPC::F4RCRegClass;
2858 if (Subtarget.hasVSX())
2859 RC = &PPC::VSFRCRegClass;
2861 RC = &PPC::F8RCRegClass;
2866 RC = &PPC::VRRCRegClass;
2869 RC = Subtarget.hasQPX() ? &PPC::QSRCRegClass : &PPC::VRRCRegClass;
2873 RC = &PPC::VSHRCRegClass;
2876 RC = &PPC::QFRCRegClass;
2879 RC = &PPC::QBRCRegClass;
2883 // Transform the arguments stored in physical registers into virtual ones.
2884 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2885 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2886 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2888 if (ValVT == MVT::i1)
2889 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2891 InVals.push_back(ArgValue);
2893 // Argument stored in memory.
2894 assert(VA.isMemLoc());
2896 unsigned ArgSize = VA.getLocVT().getStoreSize();
2897 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2900 // Create load nodes to retrieve arguments from the stack.
2901 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2902 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2903 MachinePointerInfo(),
2904 false, false, false, 0));
2908 // Assign locations to all of the incoming aggregate by value arguments.
2909 // Aggregates passed by value are stored in the local variable space of the
2910 // caller's stack frame, right above the parameter list area.
2911 SmallVector<CCValAssign, 16> ByValArgLocs;
2912 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2913 ByValArgLocs, *DAG.getContext());
2915 // Reserve stack space for the allocations in CCInfo.
2916 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2918 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2920 // Area that is at least reserved in the caller of this function.
2921 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2922 MinReservedArea = std::max(MinReservedArea, LinkageSize);
2924 // Set the size that is at least reserved in caller of this function. Tail
2925 // call optimized function's reserved stack space needs to be aligned so that
2926 // taking the difference between two stack areas will result in an aligned
2929 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
2930 FuncInfo->setMinReservedArea(MinReservedArea);
2932 SmallVector<SDValue, 8> MemOps;
2934 // If the function takes variable number of arguments, make a frame index for
2935 // the start of the first vararg value... for expansion of llvm.va_start.
2937 static const MCPhysReg GPArgRegs[] = {
2938 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2939 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2941 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2943 static const MCPhysReg FPArgRegs[] = {
2944 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2947 unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2948 if (DisablePPCFloatInVariadic)
2951 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs));
2952 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs));
2954 // Make room for NumGPArgRegs and NumFPArgRegs.
2955 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2956 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8;
2958 FuncInfo->setVarArgsStackOffset(
2959 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2960 CCInfo.getNextStackOffset(), true));
2962 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2963 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2965 // The fixed integer arguments of a variadic function are stored to the
2966 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2967 // the result of va_next.
2968 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2969 // Get an existing live-in vreg, or add a new one.
2970 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2972 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2974 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2975 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2976 MachinePointerInfo(), false, false, 0);
2977 MemOps.push_back(Store);
2978 // Increment the address by four for the next argument to store
2979 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
2980 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2983 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2985 // The double arguments are stored to the VarArgsFrameIndex
2987 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2988 // Get an existing live-in vreg, or add a new one.
2989 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2991 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2993 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2994 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2995 MachinePointerInfo(), false, false, 0);
2996 MemOps.push_back(Store);
2997 // Increment the address by eight for the next argument to store
2998 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, dl,
3000 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3004 if (!MemOps.empty())
3005 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3010 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3011 // value to MVT::i64 and then truncate to the correct register size.
3013 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
3014 SelectionDAG &DAG, SDValue ArgVal,
3017 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
3018 DAG.getValueType(ObjectVT));
3019 else if (Flags.isZExt())
3020 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
3021 DAG.getValueType(ObjectVT));
3023 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
3027 PPCTargetLowering::LowerFormalArguments_64SVR4(
3029 CallingConv::ID CallConv, bool isVarArg,
3030 const SmallVectorImpl<ISD::InputArg>
3032 SDLoc dl, SelectionDAG &DAG,
3033 SmallVectorImpl<SDValue> &InVals) const {
3034 // TODO: add description of PPC stack frame format, or at least some docs.
3036 bool isELFv2ABI = Subtarget.isELFv2ABI();
3037 bool isLittleEndian = Subtarget.isLittleEndian();
3038 MachineFunction &MF = DAG.getMachineFunction();
3039 MachineFrameInfo *MFI = MF.getFrameInfo();
3040 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3042 assert(!(CallConv == CallingConv::Fast && isVarArg) &&
3043 "fastcc not supported on varargs functions");
3045 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
3046 // Potential tail calls could cause overwriting of argument stack slots.
3047 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3048 (CallConv == CallingConv::Fast));
3049 unsigned PtrByteSize = 8;
3050 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3052 static const MCPhysReg GPR[] = {
3053 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3054 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3056 static const MCPhysReg VR[] = {
3057 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3058 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3060 static const MCPhysReg VSRH[] = {
3061 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
3062 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
3065 const unsigned Num_GPR_Regs = array_lengthof(GPR);
3066 const unsigned Num_FPR_Regs = 13;
3067 const unsigned Num_VR_Regs = array_lengthof(VR);
3068 const unsigned Num_QFPR_Regs = Num_FPR_Regs;
3070 // Do a first pass over the arguments to determine whether the ABI
3071 // guarantees that our caller has allocated the parameter save area
3072 // on its stack frame. In the ELFv1 ABI, this is always the case;
3073 // in the ELFv2 ABI, it is true if this is a vararg function or if
3074 // any parameter is located in a stack slot.
3076 bool HasParameterArea = !isELFv2ABI || isVarArg;
3077 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
3078 unsigned NumBytes = LinkageSize;
3079 unsigned AvailableFPRs = Num_FPR_Regs;
3080 unsigned AvailableVRs = Num_VR_Regs;
3081 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3082 if (Ins[i].Flags.isNest())
3085 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
3086 PtrByteSize, LinkageSize, ParamAreaSize,
3087 NumBytes, AvailableFPRs, AvailableVRs,
3088 Subtarget.hasQPX()))
3089 HasParameterArea = true;
3092 // Add DAG nodes to load the arguments or copy them out of registers. On
3093 // entry to a function on PPC, the arguments start after the linkage area,
3094 // although the first ones are often in registers.
3096 unsigned ArgOffset = LinkageSize;
3097 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3098 unsigned &QFPR_idx = FPR_idx;
3099 SmallVector<SDValue, 8> MemOps;
3100 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3101 unsigned CurArgIdx = 0;
3102 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3104 bool needsLoad = false;
3105 EVT ObjectVT = Ins[ArgNo].VT;
3106 EVT OrigVT = Ins[ArgNo].ArgVT;
3107 unsigned ObjSize = ObjectVT.getStoreSize();
3108 unsigned ArgSize = ObjSize;
3109 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3110 if (Ins[ArgNo].isOrigArg()) {
3111 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
3112 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
3114 // We re-align the argument offset for each argument, except when using the
3115 // fast calling convention, when we need to make sure we do that only when
3116 // we'll actually use a stack slot.
3117 unsigned CurArgOffset, Align;
3118 auto ComputeArgOffset = [&]() {
3119 /* Respect alignment of argument on the stack. */
3120 Align = CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
3121 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
3122 CurArgOffset = ArgOffset;
3125 if (CallConv != CallingConv::Fast) {
3128 /* Compute GPR index associated with argument offset. */
3129 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
3130 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
3133 // FIXME the codegen can be much improved in some cases.
3134 // We do not have to keep everything in memory.
3135 if (Flags.isByVal()) {
3136 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit");
3138 if (CallConv == CallingConv::Fast)
3141 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3142 ObjSize = Flags.getByValSize();
3143 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3144 // Empty aggregate parameters do not take up registers. Examples:
3148 // etc. However, we have to provide a place-holder in InVals, so
3149 // pretend we have an 8-byte item at the current address for that
3152 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3153 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3154 InVals.push_back(FIN);
3158 // Create a stack object covering all stack doublewords occupied
3159 // by the argument. If the argument is (fully or partially) on
3160 // the stack, or if the argument is fully in registers but the
3161 // caller has allocated the parameter save anyway, we can refer
3162 // directly to the caller's stack frame. Otherwise, create a
3163 // local copy in our own frame.
3165 if (HasParameterArea ||
3166 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
3167 FI = MFI->CreateFixedObject(ArgSize, ArgOffset, false, true);
3169 FI = MFI->CreateStackObject(ArgSize, Align, false);
3170 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3172 // Handle aggregates smaller than 8 bytes.
3173 if (ObjSize < PtrByteSize) {
3174 // The value of the object is its address, which differs from the
3175 // address of the enclosing doubleword on big-endian systems.
3177 if (!isLittleEndian) {
3178 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, dl, PtrVT);
3179 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
3181 InVals.push_back(Arg);
3183 if (GPR_idx != Num_GPR_Regs) {
3184 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3185 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3188 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
3189 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
3190 (ObjSize == 2 ? MVT::i16 : MVT::i32));
3191 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
3192 MachinePointerInfo(&*FuncArg), ObjType,
3195 // For sizes that don't fit a truncating store (3, 5, 6, 7),
3196 // store the whole register as-is to the parameter save area
3199 DAG.getStore(Val.getValue(1), dl, Val, FIN,
3200 MachinePointerInfo(&*FuncArg), false, false, 0);
3203 MemOps.push_back(Store);
3205 // Whether we copied from a register or not, advance the offset
3206 // into the parameter save area by a full doubleword.
3207 ArgOffset += PtrByteSize;
3211 // The value of the object is its address, which is the address of
3212 // its first stack doubleword.
3213 InVals.push_back(FIN);
3215 // Store whatever pieces of the object are in registers to memory.
3216 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3217 if (GPR_idx == Num_GPR_Regs)
3220 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3221 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3224 SDValue Off = DAG.getConstant(j, dl, PtrVT);
3225 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
3228 DAG.getStore(Val.getValue(1), dl, Val, Addr,
3229 MachinePointerInfo(&*FuncArg, j), false, false, 0);
3230 MemOps.push_back(Store);
3233 ArgOffset += ArgSize;
3237 switch (ObjectVT.getSimpleVT().SimpleTy) {
3238 default: llvm_unreachable("Unhandled argument type!");
3242 if (Flags.isNest()) {
3243 // The 'nest' parameter, if any, is passed in R11.
3244 unsigned VReg = MF.addLiveIn(PPC::X11, &PPC::G8RCRegClass);
3245 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3247 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3248 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3253 // These can be scalar arguments or elements of an integer array type
3254 // passed directly. Clang may use those instead of "byval" aggregate
3255 // types to avoid forcing arguments to memory unnecessarily.
3256 if (GPR_idx != Num_GPR_Regs) {
3257 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3258 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3260 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3261 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3262 // value to MVT::i64 and then truncate to the correct register size.
3263 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3265 if (CallConv == CallingConv::Fast)
3269 ArgSize = PtrByteSize;
3271 if (CallConv != CallingConv::Fast || needsLoad)
3277 // These can be scalar arguments or elements of a float array type
3278 // passed directly. The latter are used to implement ELFv2 homogenous
3279 // float aggregates.
3280 if (FPR_idx != Num_FPR_Regs) {
3283 if (ObjectVT == MVT::f32)
3284 VReg = MF.addLiveIn(FPR[FPR_idx],
3285 Subtarget.hasP8Vector()
3286 ? &PPC::VSSRCRegClass
3287 : &PPC::F4RCRegClass);
3289 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX()
3290 ? &PPC::VSFRCRegClass
3291 : &PPC::F8RCRegClass);
3293 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3295 } else if (GPR_idx != Num_GPR_Regs && CallConv != CallingConv::Fast) {
3296 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
3297 // once we support fp <-> gpr moves.
3299 // This can only ever happen in the presence of f32 array types,
3300 // since otherwise we never run out of FPRs before running out
3302 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3303 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3305 if (ObjectVT == MVT::f32) {
3306 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
3307 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
3308 DAG.getConstant(32, dl, MVT::i32));
3309 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
3312 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
3314 if (CallConv == CallingConv::Fast)
3320 // When passing an array of floats, the array occupies consecutive
3321 // space in the argument area; only round up to the next doubleword
3322 // at the end of the array. Otherwise, each float takes 8 bytes.
3323 if (CallConv != CallingConv::Fast || needsLoad) {
3324 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
3325 ArgOffset += ArgSize;
3326 if (Flags.isInConsecutiveRegsLast())
3327 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3337 if (!Subtarget.hasQPX()) {
3338 // These can be scalar arguments or elements of a vector array type
3339 // passed directly. The latter are used to implement ELFv2 homogenous
3340 // vector aggregates.
3341 if (VR_idx != Num_VR_Regs) {
3342 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
3343 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
3344 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3345 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3348 if (CallConv == CallingConv::Fast)
3353 if (CallConv != CallingConv::Fast || needsLoad)
3358 assert(ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 &&
3359 "Invalid QPX parameter type");
3364 // QPX vectors are treated like their scalar floating-point subregisters
3365 // (except that they're larger).
3366 unsigned Sz = ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 ? 16 : 32;
3367 if (QFPR_idx != Num_QFPR_Regs) {
3368 const TargetRegisterClass *RC;
3369 switch (ObjectVT.getSimpleVT().SimpleTy) {
3370 case MVT::v4f64: RC = &PPC::QFRCRegClass; break;
3371 case MVT::v4f32: RC = &PPC::QSRCRegClass; break;
3372 default: RC = &PPC::QBRCRegClass; break;
3375 unsigned VReg = MF.addLiveIn(QFPR[QFPR_idx], RC);
3376 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3379 if (CallConv == CallingConv::Fast)
3383 if (CallConv != CallingConv::Fast || needsLoad)
3388 // We need to load the argument to a virtual register if we determined
3389 // above that we ran out of physical registers of the appropriate type.
3391 if (ObjSize < ArgSize && !isLittleEndian)
3392 CurArgOffset += ArgSize - ObjSize;
3393 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
3394 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3395 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3396 false, false, false, 0);
3399 InVals.push_back(ArgVal);
3402 // Area that is at least reserved in the caller of this function.
3403 unsigned MinReservedArea;
3404 if (HasParameterArea)
3405 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
3407 MinReservedArea = LinkageSize;
3409 // Set the size that is at least reserved in caller of this function. Tail
3410 // call optimized functions' reserved stack space needs to be aligned so that
3411 // taking the difference between two stack areas will result in an aligned
3414 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3415 FuncInfo->setMinReservedArea(MinReservedArea);
3417 // If the function takes variable number of arguments, make a frame index for
3418 // the start of the first vararg value... for expansion of llvm.va_start.
3420 int Depth = ArgOffset;
3422 FuncInfo->setVarArgsFrameIndex(
3423 MFI->CreateFixedObject(PtrByteSize, Depth, true));
3424 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3426 // If this function is vararg, store any remaining integer argument regs
3427 // to their spots on the stack so that they may be loaded by deferencing the
3428 // result of va_next.
3429 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
3430 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
3431 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3432 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3433 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3434 MachinePointerInfo(), false, false, 0);
3435 MemOps.push_back(Store);
3436 // Increment the address by four for the next argument to store
3437 SDValue PtrOff = DAG.getConstant(PtrByteSize, dl, PtrVT);
3438 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3442 if (!MemOps.empty())
3443 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3449 PPCTargetLowering::LowerFormalArguments_Darwin(
3451 CallingConv::ID CallConv, bool isVarArg,
3452 const SmallVectorImpl<ISD::InputArg>
3454 SDLoc dl, SelectionDAG &DAG,
3455 SmallVectorImpl<SDValue> &InVals) const {
3456 // TODO: add description of PPC stack frame format, or at least some docs.
3458 MachineFunction &MF = DAG.getMachineFunction();
3459 MachineFrameInfo *MFI = MF.getFrameInfo();
3460 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3462 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
3463 bool isPPC64 = PtrVT == MVT::i64;
3464 // Potential tail calls could cause overwriting of argument stack slots.
3465 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3466 (CallConv == CallingConv::Fast));
3467 unsigned PtrByteSize = isPPC64 ? 8 : 4;
3468 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3469 unsigned ArgOffset = LinkageSize;
3470 // Area that is at least reserved in caller of this function.
3471 unsigned MinReservedArea = ArgOffset;
3473 static const MCPhysReg GPR_32[] = { // 32-bit registers.
3474 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3475 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3477 static const MCPhysReg GPR_64[] = { // 64-bit registers.
3478 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3479 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3481 static const MCPhysReg VR[] = {
3482 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3483 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3486 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
3487 const unsigned Num_FPR_Regs = 13;
3488 const unsigned Num_VR_Regs = array_lengthof( VR);
3490 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3492 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
3494 // In 32-bit non-varargs functions, the stack space for vectors is after the
3495 // stack space for non-vectors. We do not use this space unless we have
3496 // too many vectors to fit in registers, something that only occurs in
3497 // constructed examples:), but we have to walk the arglist to figure
3498 // that out...for the pathological case, compute VecArgOffset as the
3499 // start of the vector parameter area. Computing VecArgOffset is the
3500 // entire point of the following loop.
3501 unsigned VecArgOffset = ArgOffset;
3502 if (!isVarArg && !isPPC64) {
3503 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
3505 EVT ObjectVT = Ins[ArgNo].VT;
3506 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3508 if (Flags.isByVal()) {
3509 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
3510 unsigned ObjSize = Flags.getByValSize();
3512 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3513 VecArgOffset += ArgSize;
3517 switch(ObjectVT.getSimpleVT().SimpleTy) {
3518 default: llvm_unreachable("Unhandled argument type!");
3524 case MVT::i64: // PPC64
3526 // FIXME: We are guaranteed to be !isPPC64 at this point.
3527 // Does MVT::i64 apply?
3534 // Nothing to do, we're only looking at Nonvector args here.
3539 // We've found where the vector parameter area in memory is. Skip the
3540 // first 12 parameters; these don't use that memory.
3541 VecArgOffset = ((VecArgOffset+15)/16)*16;
3542 VecArgOffset += 12*16;
3544 // Add DAG nodes to load the arguments or copy them out of registers. On
3545 // entry to a function on PPC, the arguments start after the linkage area,
3546 // although the first ones are often in registers.
3548 SmallVector<SDValue, 8> MemOps;
3549 unsigned nAltivecParamsAtEnd = 0;
3550 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3551 unsigned CurArgIdx = 0;
3552 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3554 bool needsLoad = false;
3555 EVT ObjectVT = Ins[ArgNo].VT;
3556 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
3557 unsigned ArgSize = ObjSize;
3558 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3559 if (Ins[ArgNo].isOrigArg()) {
3560 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
3561 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
3563 unsigned CurArgOffset = ArgOffset;
3565 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
3566 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
3567 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
3568 if (isVarArg || isPPC64) {
3569 MinReservedArea = ((MinReservedArea+15)/16)*16;
3570 MinReservedArea += CalculateStackSlotSize(ObjectVT,
3573 } else nAltivecParamsAtEnd++;
3575 // Calculate min reserved area.
3576 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
3580 // FIXME the codegen can be much improved in some cases.
3581 // We do not have to keep everything in memory.
3582 if (Flags.isByVal()) {
3583 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit");
3585 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3586 ObjSize = Flags.getByValSize();
3587 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3588 // Objects of size 1 and 2 are right justified, everything else is
3589 // left justified. This means the memory address is adjusted forwards.
3590 if (ObjSize==1 || ObjSize==2) {
3591 CurArgOffset = CurArgOffset + (4 - ObjSize);
3593 // The value of the object is its address.
3594 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, false, true);
3595 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3596 InVals.push_back(FIN);
3597 if (ObjSize==1 || ObjSize==2) {
3598 if (GPR_idx != Num_GPR_Regs) {
3601 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3603 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3604 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3605 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
3606 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
3607 MachinePointerInfo(&*FuncArg),
3608 ObjType, false, false, 0);
3609 MemOps.push_back(Store);
3613 ArgOffset += PtrByteSize;
3617 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3618 // Store whatever pieces of the object are in registers
3619 // to memory. ArgOffset will be the address of the beginning
3621 if (GPR_idx != Num_GPR_Regs) {
3624 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3626 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3627 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3628 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3629 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3631 DAG.getStore(Val.getValue(1), dl, Val, FIN,
3632 MachinePointerInfo(&*FuncArg, j), false, false, 0);
3633 MemOps.push_back(Store);
3635 ArgOffset += PtrByteSize;
3637 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
3644 switch (ObjectVT.getSimpleVT().SimpleTy) {
3645 default: llvm_unreachable("Unhandled argument type!");
3649 if (GPR_idx != Num_GPR_Regs) {
3650 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3651 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3653 if (ObjectVT == MVT::i1)
3654 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
3659 ArgSize = PtrByteSize;
3661 // All int arguments reserve stack space in the Darwin ABI.
3662 ArgOffset += PtrByteSize;
3666 case MVT::i64: // PPC64
3667 if (GPR_idx != Num_GPR_Regs) {
3668 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3669 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3671 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3672 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3673 // value to MVT::i64 and then truncate to the correct register size.
3674 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3679 ArgSize = PtrByteSize;
3681 // All int arguments reserve stack space in the Darwin ABI.
3687 // Every 4 bytes of argument space consumes one of the GPRs available for
3688 // argument passing.
3689 if (GPR_idx != Num_GPR_Regs) {
3691 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
3694 if (FPR_idx != Num_FPR_Regs) {
3697 if (ObjectVT == MVT::f32)
3698 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
3700 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
3702 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3708 // All FP arguments reserve stack space in the Darwin ABI.
3709 ArgOffset += isPPC64 ? 8 : ObjSize;
3715 // Note that vector arguments in registers don't reserve stack space,
3716 // except in varargs functions.
3717 if (VR_idx != Num_VR_Regs) {
3718 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3719 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3721 while ((ArgOffset % 16) != 0) {
3722 ArgOffset += PtrByteSize;
3723 if (GPR_idx != Num_GPR_Regs)
3727 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
3731 if (!isVarArg && !isPPC64) {
3732 // Vectors go after all the nonvectors.
3733 CurArgOffset = VecArgOffset;
3736 // Vectors are aligned.
3737 ArgOffset = ((ArgOffset+15)/16)*16;
3738 CurArgOffset = ArgOffset;
3746 // We need to load the argument to a virtual register if we determined above
3747 // that we ran out of physical registers of the appropriate type.
3749 int FI = MFI->CreateFixedObject(ObjSize,
3750 CurArgOffset + (ArgSize - ObjSize),
3752 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3753 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3754 false, false, false, 0);
3757 InVals.push_back(ArgVal);
3760 // Allow for Altivec parameters at the end, if needed.
3761 if (nAltivecParamsAtEnd) {
3762 MinReservedArea = ((MinReservedArea+15)/16)*16;
3763 MinReservedArea += 16*nAltivecParamsAtEnd;
3766 // Area that is at least reserved in the caller of this function.
3767 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
3769 // Set the size that is at least reserved in caller of this function. Tail
3770 // call optimized functions' reserved stack space needs to be aligned so that
3771 // taking the difference between two stack areas will result in an aligned
3774 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3775 FuncInfo->setMinReservedArea(MinReservedArea);
3777 // If the function takes variable number of arguments, make a frame index for
3778 // the start of the first vararg value... for expansion of llvm.va_start.
3780 int Depth = ArgOffset;
3782 FuncInfo->setVarArgsFrameIndex(
3783 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3785 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3787 // If this function is vararg, store any remaining integer argument regs
3788 // to their spots on the stack so that they may be loaded by deferencing the
3789 // result of va_next.
3790 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3794 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3796 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3798 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3799 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3800 MachinePointerInfo(), false, false, 0);
3801 MemOps.push_back(Store);
3802 // Increment the address by four for the next argument to store
3803 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
3804 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3808 if (!MemOps.empty())
3809 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3814 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3815 /// adjusted to accommodate the arguments for the tailcall.
3816 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3817 unsigned ParamSize) {
3819 if (!isTailCall) return 0;
3821 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3822 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3823 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3824 // Remember only if the new adjustement is bigger.
3825 if (SPDiff < FI->getTailCallSPDelta())
3826 FI->setTailCallSPDelta(SPDiff);
3831 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3832 /// for tail call optimization. Targets which want to do tail call
3833 /// optimization should implement this function.
3835 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3836 CallingConv::ID CalleeCC,
3838 const SmallVectorImpl<ISD::InputArg> &Ins,
3839 SelectionDAG& DAG) const {
3840 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3843 // Variable argument functions are not supported.
3847 MachineFunction &MF = DAG.getMachineFunction();
3848 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3849 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3850 // Functions containing by val parameters are not supported.
3851 for (unsigned i = 0; i != Ins.size(); i++) {
3852 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3853 if (Flags.isByVal()) return false;
3856 // Non-PIC/GOT tail calls are supported.
3857 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3860 // At the moment we can only do local tail calls (in same module, hidden
3861 // or protected) if we are generating PIC.
3862 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3863 return G->getGlobal()->hasHiddenVisibility()
3864 || G->getGlobal()->hasProtectedVisibility();
3870 /// isCallCompatibleAddress - Return the immediate to use if the specified
3871 /// 32-bit value is representable in the immediate field of a BxA instruction.
3872 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3873 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3874 if (!C) return nullptr;
3876 int Addr = C->getZExtValue();
3877 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3878 SignExtend32<26>(Addr) != Addr)
3879 return nullptr; // Top 6 bits have to be sext of immediate.
3881 return DAG.getConstant((int)C->getZExtValue() >> 2, SDLoc(Op),
3882 DAG.getTargetLoweringInfo().getPointerTy(
3883 DAG.getDataLayout())).getNode();
3888 struct TailCallArgumentInfo {
3893 TailCallArgumentInfo() : FrameIdx(0) {}
3897 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3899 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3901 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3902 SmallVectorImpl<SDValue> &MemOpChains,
3904 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3905 SDValue Arg = TailCallArgs[i].Arg;
3906 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3907 int FI = TailCallArgs[i].FrameIdx;
3908 // Store relative to framepointer.
3909 MemOpChains.push_back(DAG.getStore(
3910 Chain, dl, Arg, FIN,
3911 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), false,
3916 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3917 /// the appropriate stack slot for the tail call optimized function call.
3918 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3919 MachineFunction &MF,
3928 // Calculate the new stack slot for the return address.
3929 int SlotSize = isPPC64 ? 8 : 4;
3930 const PPCFrameLowering *FL =
3931 MF.getSubtarget<PPCSubtarget>().getFrameLowering();
3932 int NewRetAddrLoc = SPDiff + FL->getReturnSaveOffset();
3933 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3934 NewRetAddrLoc, true);
3935 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3936 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3937 Chain = DAG.getStore(
3938 Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3939 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), NewRetAddr),
3942 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3943 // slot as the FP is never overwritten.
3945 int NewFPLoc = SPDiff + FL->getFramePointerSaveOffset();
3946 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3948 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3949 Chain = DAG.getStore(
3950 Chain, dl, OldFP, NewFramePtrIdx,
3951 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), NewFPIdx),
3958 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3959 /// the position of the argument.
3961 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3962 SDValue Arg, int SPDiff, unsigned ArgOffset,
3963 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3964 int Offset = ArgOffset + SPDiff;
3965 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3966 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3967 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3968 SDValue FIN = DAG.getFrameIndex(FI, VT);
3969 TailCallArgumentInfo Info;
3971 Info.FrameIdxOp = FIN;
3973 TailCallArguments.push_back(Info);
3976 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3977 /// stack slot. Returns the chain as result and the loaded frame pointers in
3978 /// LROpOut/FPOpout. Used when tail calling.
3979 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3987 // Load the LR and FP stack slot for later adjusting.
3988 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
3989 LROpOut = getReturnAddrFrameIndex(DAG);
3990 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3991 false, false, false, 0);
3992 Chain = SDValue(LROpOut.getNode(), 1);
3994 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3995 // slot as the FP is never overwritten.
3997 FPOpOut = getFramePointerFrameIndex(DAG);
3998 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3999 false, false, false, 0);
4000 Chain = SDValue(FPOpOut.getNode(), 1);
4006 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
4007 /// by "Src" to address "Dst" of size "Size". Alignment information is
4008 /// specified by the specific parameter attribute. The copy will be passed as
4009 /// a byval function parameter.
4010 /// Sometimes what we are copying is the end of a larger object, the part that
4011 /// does not fit in registers.
4013 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
4014 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
4016 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
4017 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
4018 false, false, false, MachinePointerInfo(),
4019 MachinePointerInfo());
4022 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
4025 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
4026 SDValue Arg, SDValue PtrOff, int SPDiff,
4027 unsigned ArgOffset, bool isPPC64, bool isTailCall,
4028 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
4029 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
4031 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4036 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4038 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4039 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4040 DAG.getConstant(ArgOffset, dl, PtrVT));
4042 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4043 MachinePointerInfo(), false, false, 0));
4044 // Calculate and remember argument location.
4045 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
4050 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
4051 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
4052 SDValue LROp, SDValue FPOp, bool isDarwinABI,
4053 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
4054 MachineFunction &MF = DAG.getMachineFunction();
4056 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
4057 // might overwrite each other in case of tail call optimization.
4058 SmallVector<SDValue, 8> MemOpChains2;
4059 // Do not flag preceding copytoreg stuff together with the following stuff.
4061 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
4063 if (!MemOpChains2.empty())
4064 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
4066 // Store the return address to the appropriate stack slot.
4067 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
4068 isPPC64, isDarwinABI, dl);
4070 // Emit callseq_end just before tailcall node.
4071 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4072 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
4073 InFlag = Chain.getValue(1);
4076 // Is this global address that of a function that can be called by name? (as
4077 // opposed to something that must hold a descriptor for an indirect call).
4078 static bool isFunctionGlobalAddress(SDValue Callee) {
4079 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
4080 if (Callee.getOpcode() == ISD::GlobalTLSAddress ||
4081 Callee.getOpcode() == ISD::TargetGlobalTLSAddress)
4084 return G->getGlobal()->getType()->getElementType()->isFunctionTy();
4091 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
4092 SDValue &Chain, SDValue CallSeqStart, SDLoc dl, int SPDiff,
4093 bool isTailCall, bool IsPatchPoint, bool hasNest,
4094 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
4095 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
4096 ImmutableCallSite *CS, const PPCSubtarget &Subtarget) {
4098 bool isPPC64 = Subtarget.isPPC64();
4099 bool isSVR4ABI = Subtarget.isSVR4ABI();
4100 bool isELFv2ABI = Subtarget.isELFv2ABI();
4102 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4103 NodeTys.push_back(MVT::Other); // Returns a chain
4104 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
4106 unsigned CallOpc = PPCISD::CALL;
4108 bool needIndirectCall = true;
4109 if (!isSVR4ABI || !isPPC64)
4110 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
4111 // If this is an absolute destination address, use the munged value.
4112 Callee = SDValue(Dest, 0);
4113 needIndirectCall = false;
4116 if (isFunctionGlobalAddress(Callee)) {
4117 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Callee);
4118 // A call to a TLS address is actually an indirect call to a
4119 // thread-specific pointer.
4120 unsigned OpFlags = 0;
4121 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
4122 (Subtarget.getTargetTriple().isMacOSX() &&
4123 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
4124 !G->getGlobal()->isStrongDefinitionForLinker()) ||
4125 (Subtarget.isTargetELF() && !isPPC64 &&
4126 !G->getGlobal()->hasLocalLinkage() &&
4127 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
4128 // PC-relative references to external symbols should go through $stub,
4129 // unless we're building with the leopard linker or later, which
4130 // automatically synthesizes these stubs.
4131 OpFlags = PPCII::MO_PLT_OR_STUB;
4134 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
4135 // every direct call is) turn it into a TargetGlobalAddress /
4136 // TargetExternalSymbol node so that legalize doesn't hack it.
4137 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
4138 Callee.getValueType(), 0, OpFlags);
4139 needIndirectCall = false;
4142 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
4143 unsigned char OpFlags = 0;
4145 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
4146 (Subtarget.getTargetTriple().isMacOSX() &&
4147 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) ||
4148 (Subtarget.isTargetELF() && !isPPC64 &&
4149 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
4150 // PC-relative references to external symbols should go through $stub,
4151 // unless we're building with the leopard linker or later, which
4152 // automatically synthesizes these stubs.
4153 OpFlags = PPCII::MO_PLT_OR_STUB;
4156 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
4158 needIndirectCall = false;
4162 // We'll form an invalid direct call when lowering a patchpoint; the full
4163 // sequence for an indirect call is complicated, and many of the
4164 // instructions introduced might have side effects (and, thus, can't be
4165 // removed later). The call itself will be removed as soon as the
4166 // argument/return lowering is complete, so the fact that it has the wrong
4167 // kind of operands should not really matter.
4168 needIndirectCall = false;
4171 if (needIndirectCall) {
4172 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
4173 // to do the call, we can't use PPCISD::CALL.
4174 SDValue MTCTROps[] = {Chain, Callee, InFlag};
4176 if (isSVR4ABI && isPPC64 && !isELFv2ABI) {
4177 // Function pointers in the 64-bit SVR4 ABI do not point to the function
4178 // entry point, but to the function descriptor (the function entry point
4179 // address is part of the function descriptor though).
4180 // The function descriptor is a three doubleword structure with the
4181 // following fields: function entry point, TOC base address and
4182 // environment pointer.
4183 // Thus for a call through a function pointer, the following actions need
4185 // 1. Save the TOC of the caller in the TOC save area of its stack
4186 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
4187 // 2. Load the address of the function entry point from the function
4189 // 3. Load the TOC of the callee from the function descriptor into r2.
4190 // 4. Load the environment pointer from the function descriptor into
4192 // 5. Branch to the function entry point address.
4193 // 6. On return of the callee, the TOC of the caller needs to be
4194 // restored (this is done in FinishCall()).
4196 // The loads are scheduled at the beginning of the call sequence, and the
4197 // register copies are flagged together to ensure that no other
4198 // operations can be scheduled in between. E.g. without flagging the
4199 // copies together, a TOC access in the caller could be scheduled between
4200 // the assignment of the callee TOC and the branch to the callee, which
4201 // results in the TOC access going through the TOC of the callee instead
4202 // of going through the TOC of the caller, which leads to incorrect code.
4204 // Load the address of the function entry point from the function
4206 SDValue LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-1);
4207 if (LDChain.getValueType() == MVT::Glue)
4208 LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-2);
4210 bool LoadsInv = Subtarget.hasInvariantFunctionDescriptors();
4212 MachinePointerInfo MPI(CS ? CS->getCalledValue() : nullptr);
4213 SDValue LoadFuncPtr = DAG.getLoad(MVT::i64, dl, LDChain, Callee, MPI,
4214 false, false, LoadsInv, 8);
4216 // Load environment pointer into r11.
4217 SDValue PtrOff = DAG.getIntPtrConstant(16, dl);
4218 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
4219 SDValue LoadEnvPtr = DAG.getLoad(MVT::i64, dl, LDChain, AddPtr,
4220 MPI.getWithOffset(16), false, false,
4223 SDValue TOCOff = DAG.getIntPtrConstant(8, dl);
4224 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
4225 SDValue TOCPtr = DAG.getLoad(MVT::i64, dl, LDChain, AddTOC,
4226 MPI.getWithOffset(8), false, false,
4229 setUsesTOCBasePtr(DAG);
4230 SDValue TOCVal = DAG.getCopyToReg(Chain, dl, PPC::X2, TOCPtr,
4232 Chain = TOCVal.getValue(0);
4233 InFlag = TOCVal.getValue(1);
4235 // If the function call has an explicit 'nest' parameter, it takes the
4236 // place of the environment pointer.
4238 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
4241 Chain = EnvVal.getValue(0);
4242 InFlag = EnvVal.getValue(1);
4245 MTCTROps[0] = Chain;
4246 MTCTROps[1] = LoadFuncPtr;
4247 MTCTROps[2] = InFlag;
4250 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
4251 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
4252 InFlag = Chain.getValue(1);
4255 NodeTys.push_back(MVT::Other);
4256 NodeTys.push_back(MVT::Glue);
4257 Ops.push_back(Chain);
4258 CallOpc = PPCISD::BCTRL;
4259 Callee.setNode(nullptr);
4260 // Add use of X11 (holding environment pointer)
4261 if (isSVR4ABI && isPPC64 && !isELFv2ABI && !hasNest)
4262 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
4263 // Add CTR register as callee so a bctr can be emitted later.
4265 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
4268 // If this is a direct call, pass the chain and the callee.
4269 if (Callee.getNode()) {
4270 Ops.push_back(Chain);
4271 Ops.push_back(Callee);
4273 // If this is a tail call add stack pointer delta.
4275 Ops.push_back(DAG.getConstant(SPDiff, dl, MVT::i32));
4277 // Add argument registers to the end of the list so that they are known live
4279 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
4280 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
4281 RegsToPass[i].second.getValueType()));
4283 // All calls, in both the ELF V1 and V2 ABIs, need the TOC register live
4285 if (isSVR4ABI && isPPC64 && !IsPatchPoint) {
4286 setUsesTOCBasePtr(DAG);
4287 Ops.push_back(DAG.getRegister(PPC::X2, PtrVT));
4294 bool isLocalCall(const SDValue &Callee)
4296 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
4297 return G->getGlobal()->isStrongDefinitionForLinker();
4302 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
4303 CallingConv::ID CallConv, bool isVarArg,
4304 const SmallVectorImpl<ISD::InputArg> &Ins,
4305 SDLoc dl, SelectionDAG &DAG,
4306 SmallVectorImpl<SDValue> &InVals) const {
4308 SmallVector<CCValAssign, 16> RVLocs;
4309 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
4311 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
4313 // Copy all of the result registers out of their specified physreg.
4314 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
4315 CCValAssign &VA = RVLocs[i];
4316 assert(VA.isRegLoc() && "Can only return in registers!");
4318 SDValue Val = DAG.getCopyFromReg(Chain, dl,
4319 VA.getLocReg(), VA.getLocVT(), InFlag);
4320 Chain = Val.getValue(1);
4321 InFlag = Val.getValue(2);
4323 switch (VA.getLocInfo()) {
4324 default: llvm_unreachable("Unknown loc info!");
4325 case CCValAssign::Full: break;
4326 case CCValAssign::AExt:
4327 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4329 case CCValAssign::ZExt:
4330 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
4331 DAG.getValueType(VA.getValVT()));
4332 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4334 case CCValAssign::SExt:
4335 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
4336 DAG.getValueType(VA.getValVT()));
4337 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4341 InVals.push_back(Val);
4348 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
4349 bool isTailCall, bool isVarArg, bool IsPatchPoint,
4350 bool hasNest, SelectionDAG &DAG,
4351 SmallVector<std::pair<unsigned, SDValue>, 8>
4353 SDValue InFlag, SDValue Chain,
4354 SDValue CallSeqStart, SDValue &Callee,
4355 int SPDiff, unsigned NumBytes,
4356 const SmallVectorImpl<ISD::InputArg> &Ins,
4357 SmallVectorImpl<SDValue> &InVals,
4358 ImmutableCallSite *CS) const {
4360 std::vector<EVT> NodeTys;
4361 SmallVector<SDValue, 8> Ops;
4362 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, CallSeqStart, dl,
4363 SPDiff, isTailCall, IsPatchPoint, hasNest,
4364 RegsToPass, Ops, NodeTys, CS, Subtarget);
4366 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
4367 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
4368 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
4370 // When performing tail call optimization the callee pops its arguments off
4371 // the stack. Account for this here so these bytes can be pushed back on in
4372 // PPCFrameLowering::eliminateCallFramePseudoInstr.
4373 int BytesCalleePops =
4374 (CallConv == CallingConv::Fast &&
4375 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
4377 // Add a register mask operand representing the call-preserved registers.
4378 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
4379 const uint32_t *Mask =
4380 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
4381 assert(Mask && "Missing call preserved mask for calling convention");
4382 Ops.push_back(DAG.getRegisterMask(Mask));
4384 if (InFlag.getNode())
4385 Ops.push_back(InFlag);
4389 assert(((Callee.getOpcode() == ISD::Register &&
4390 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
4391 Callee.getOpcode() == ISD::TargetExternalSymbol ||
4392 Callee.getOpcode() == ISD::TargetGlobalAddress ||
4393 isa<ConstantSDNode>(Callee)) &&
4394 "Expecting an global address, external symbol, absolute value or register");
4396 DAG.getMachineFunction().getFrameInfo()->setHasTailCall();
4397 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
4400 // Add a NOP immediately after the branch instruction when using the 64-bit
4401 // SVR4 ABI. At link time, if caller and callee are in a different module and
4402 // thus have a different TOC, the call will be replaced with a call to a stub
4403 // function which saves the current TOC, loads the TOC of the callee and
4404 // branches to the callee. The NOP will be replaced with a load instruction
4405 // which restores the TOC of the caller from the TOC save slot of the current
4406 // stack frame. If caller and callee belong to the same module (and have the
4407 // same TOC), the NOP will remain unchanged.
4409 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64() &&
4411 if (CallOpc == PPCISD::BCTRL) {
4412 // This is a call through a function pointer.
4413 // Restore the caller TOC from the save area into R2.
4414 // See PrepareCall() for more information about calls through function
4415 // pointers in the 64-bit SVR4 ABI.
4416 // We are using a target-specific load with r2 hard coded, because the
4417 // result of a target-independent load would never go directly into r2,
4418 // since r2 is a reserved register (which prevents the register allocator
4419 // from allocating it), resulting in an additional register being
4420 // allocated and an unnecessary move instruction being generated.
4421 CallOpc = PPCISD::BCTRL_LOAD_TOC;
4423 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4424 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
4425 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
4426 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset, dl);
4427 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
4429 // The address needs to go after the chain input but before the flag (or
4430 // any other variadic arguments).
4431 Ops.insert(std::next(Ops.begin()), AddTOC);
4432 } else if ((CallOpc == PPCISD::CALL) &&
4433 (!isLocalCall(Callee) ||
4434 DAG.getTarget().getRelocationModel() == Reloc::PIC_))
4435 // Otherwise insert NOP for non-local calls.
4436 CallOpc = PPCISD::CALL_NOP;
4439 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
4440 InFlag = Chain.getValue(1);
4442 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4443 DAG.getIntPtrConstant(BytesCalleePops, dl, true),
4446 InFlag = Chain.getValue(1);
4448 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
4449 Ins, dl, DAG, InVals);
4453 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
4454 SmallVectorImpl<SDValue> &InVals) const {
4455 SelectionDAG &DAG = CLI.DAG;
4457 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
4458 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
4459 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
4460 SDValue Chain = CLI.Chain;
4461 SDValue Callee = CLI.Callee;
4462 bool &isTailCall = CLI.IsTailCall;
4463 CallingConv::ID CallConv = CLI.CallConv;
4464 bool isVarArg = CLI.IsVarArg;
4465 bool IsPatchPoint = CLI.IsPatchPoint;
4466 ImmutableCallSite *CS = CLI.CS;
4469 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
4472 if (!isTailCall && CS && CS->isMustTailCall())
4473 report_fatal_error("failed to perform tail call elimination on a call "
4474 "site marked musttail");
4476 if (Subtarget.isSVR4ABI()) {
4477 if (Subtarget.isPPC64())
4478 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
4479 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4480 dl, DAG, InVals, CS);
4482 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
4483 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4484 dl, DAG, InVals, CS);
4487 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
4488 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4489 dl, DAG, InVals, CS);
4493 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
4494 CallingConv::ID CallConv, bool isVarArg,
4495 bool isTailCall, bool IsPatchPoint,
4496 const SmallVectorImpl<ISD::OutputArg> &Outs,
4497 const SmallVectorImpl<SDValue> &OutVals,
4498 const SmallVectorImpl<ISD::InputArg> &Ins,
4499 SDLoc dl, SelectionDAG &DAG,
4500 SmallVectorImpl<SDValue> &InVals,
4501 ImmutableCallSite *CS) const {
4502 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
4503 // of the 32-bit SVR4 ABI stack frame layout.
4505 assert((CallConv == CallingConv::C ||
4506 CallConv == CallingConv::Fast) && "Unknown calling convention!");
4508 unsigned PtrByteSize = 4;
4510 MachineFunction &MF = DAG.getMachineFunction();
4512 // Mark this function as potentially containing a function that contains a
4513 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4514 // and restoring the callers stack pointer in this functions epilog. This is
4515 // done because by tail calling the called function might overwrite the value
4516 // in this function's (MF) stack pointer stack slot 0(SP).
4517 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4518 CallConv == CallingConv::Fast)
4519 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4521 // Count how many bytes are to be pushed on the stack, including the linkage
4522 // area, parameter list area and the part of the local variable space which
4523 // contains copies of aggregates which are passed by value.
4525 // Assign locations to all of the outgoing arguments.
4526 SmallVector<CCValAssign, 16> ArgLocs;
4527 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
4530 // Reserve space for the linkage area on the stack.
4531 CCInfo.AllocateStack(Subtarget.getFrameLowering()->getLinkageSize(),
4535 // Handle fixed and variable vector arguments differently.
4536 // Fixed vector arguments go into registers as long as registers are
4537 // available. Variable vector arguments always go into memory.
4538 unsigned NumArgs = Outs.size();
4540 for (unsigned i = 0; i != NumArgs; ++i) {
4541 MVT ArgVT = Outs[i].VT;
4542 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
4545 if (Outs[i].IsFixed) {
4546 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
4549 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
4555 errs() << "Call operand #" << i << " has unhandled type "
4556 << EVT(ArgVT).getEVTString() << "\n";
4558 llvm_unreachable(nullptr);
4562 // All arguments are treated the same.
4563 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
4566 // Assign locations to all of the outgoing aggregate by value arguments.
4567 SmallVector<CCValAssign, 16> ByValArgLocs;
4568 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4569 ByValArgLocs, *DAG.getContext());
4571 // Reserve stack space for the allocations in CCInfo.
4572 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
4574 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
4576 // Size of the linkage area, parameter list area and the part of the local
4577 // space variable where copies of aggregates which are passed by value are
4579 unsigned NumBytes = CCByValInfo.getNextStackOffset();
4581 // Calculate by how many bytes the stack has to be adjusted in case of tail
4582 // call optimization.
4583 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4585 // Adjust the stack pointer for the new arguments...
4586 // These operations are automatically eliminated by the prolog/epilog pass
4587 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4589 SDValue CallSeqStart = Chain;
4591 // Load the return address and frame pointer so it can be moved somewhere else
4594 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
4597 // Set up a copy of the stack pointer for use loading and storing any
4598 // arguments that may not fit in the registers available for argument
4600 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4602 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4603 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4604 SmallVector<SDValue, 8> MemOpChains;
4606 bool seenFloatArg = false;
4607 // Walk the register/memloc assignments, inserting copies/loads.
4608 for (unsigned i = 0, j = 0, e = ArgLocs.size();
4611 CCValAssign &VA = ArgLocs[i];
4612 SDValue Arg = OutVals[i];
4613 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4615 if (Flags.isByVal()) {
4616 // Argument is an aggregate which is passed by value, thus we need to
4617 // create a copy of it in the local variable space of the current stack
4618 // frame (which is the stack frame of the caller) and pass the address of
4619 // this copy to the callee.
4620 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
4621 CCValAssign &ByValVA = ByValArgLocs[j++];
4622 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
4624 // Memory reserved in the local variable space of the callers stack frame.
4625 unsigned LocMemOffset = ByValVA.getLocMemOffset();
4627 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
4628 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(MF.getDataLayout()),
4631 // Create a copy of the argument in the local area of the current
4633 SDValue MemcpyCall =
4634 CreateCopyOfByValArgument(Arg, PtrOff,
4635 CallSeqStart.getNode()->getOperand(0),
4638 // This must go outside the CALLSEQ_START..END.
4639 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4640 CallSeqStart.getNode()->getOperand(1),
4642 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4643 NewCallSeqStart.getNode());
4644 Chain = CallSeqStart = NewCallSeqStart;
4646 // Pass the address of the aggregate copy on the stack either in a
4647 // physical register or in the parameter list area of the current stack
4648 // frame to the callee.
4652 if (VA.isRegLoc()) {
4653 if (Arg.getValueType() == MVT::i1)
4654 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
4656 seenFloatArg |= VA.getLocVT().isFloatingPoint();
4657 // Put argument in a physical register.
4658 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
4660 // Put argument in the parameter list area of the current stack frame.
4661 assert(VA.isMemLoc());
4662 unsigned LocMemOffset = VA.getLocMemOffset();
4665 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
4666 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(MF.getDataLayout()),
4669 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4670 MachinePointerInfo(),
4673 // Calculate and remember argument location.
4674 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
4680 if (!MemOpChains.empty())
4681 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4683 // Build a sequence of copy-to-reg nodes chained together with token chain
4684 // and flag operands which copy the outgoing args into the appropriate regs.
4686 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4687 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4688 RegsToPass[i].second, InFlag);
4689 InFlag = Chain.getValue(1);
4692 // Set CR bit 6 to true if this is a vararg call with floating args passed in
4695 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
4696 SDValue Ops[] = { Chain, InFlag };
4698 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
4699 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
4701 InFlag = Chain.getValue(1);
4705 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
4706 false, TailCallArguments);
4708 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint,
4709 /* unused except on PPC64 ELFv1 */ false, DAG,
4710 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
4711 NumBytes, Ins, InVals, CS);
4714 // Copy an argument into memory, being careful to do this outside the
4715 // call sequence for the call to which the argument belongs.
4717 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
4718 SDValue CallSeqStart,
4719 ISD::ArgFlagsTy Flags,
4722 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
4723 CallSeqStart.getNode()->getOperand(0),
4725 // The MEMCPY must go outside the CALLSEQ_START..END.
4726 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4727 CallSeqStart.getNode()->getOperand(1),
4729 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4730 NewCallSeqStart.getNode());
4731 return NewCallSeqStart;
4735 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
4736 CallingConv::ID CallConv, bool isVarArg,
4737 bool isTailCall, bool IsPatchPoint,
4738 const SmallVectorImpl<ISD::OutputArg> &Outs,
4739 const SmallVectorImpl<SDValue> &OutVals,
4740 const SmallVectorImpl<ISD::InputArg> &Ins,
4741 SDLoc dl, SelectionDAG &DAG,
4742 SmallVectorImpl<SDValue> &InVals,
4743 ImmutableCallSite *CS) const {
4745 bool isELFv2ABI = Subtarget.isELFv2ABI();
4746 bool isLittleEndian = Subtarget.isLittleEndian();
4747 unsigned NumOps = Outs.size();
4748 bool hasNest = false;
4750 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4751 unsigned PtrByteSize = 8;
4753 MachineFunction &MF = DAG.getMachineFunction();
4755 // Mark this function as potentially containing a function that contains a
4756 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4757 // and restoring the callers stack pointer in this functions epilog. This is
4758 // done because by tail calling the called function might overwrite the value
4759 // in this function's (MF) stack pointer stack slot 0(SP).
4760 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4761 CallConv == CallingConv::Fast)
4762 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4764 assert(!(CallConv == CallingConv::Fast && isVarArg) &&
4765 "fastcc not supported on varargs functions");
4767 // Count how many bytes are to be pushed on the stack, including the linkage
4768 // area, and parameter passing area. On ELFv1, the linkage area is 48 bytes
4769 // reserved space for [SP][CR][LR][2 x unused][TOC]; on ELFv2, the linkage
4770 // area is 32 bytes reserved space for [SP][CR][LR][TOC].
4771 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
4772 unsigned NumBytes = LinkageSize;
4773 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4774 unsigned &QFPR_idx = FPR_idx;
4776 static const MCPhysReg GPR[] = {
4777 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4778 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4780 static const MCPhysReg VR[] = {
4781 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4782 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4784 static const MCPhysReg VSRH[] = {
4785 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4786 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4789 const unsigned NumGPRs = array_lengthof(GPR);
4790 const unsigned NumFPRs = 13;
4791 const unsigned NumVRs = array_lengthof(VR);
4792 const unsigned NumQFPRs = NumFPRs;
4794 // When using the fast calling convention, we don't provide backing for
4795 // arguments that will be in registers.
4796 unsigned NumGPRsUsed = 0, NumFPRsUsed = 0, NumVRsUsed = 0;
4798 // Add up all the space actually used.
4799 for (unsigned i = 0; i != NumOps; ++i) {
4800 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4801 EVT ArgVT = Outs[i].VT;
4802 EVT OrigVT = Outs[i].ArgVT;
4807 if (CallConv == CallingConv::Fast) {
4808 if (Flags.isByVal())
4809 NumGPRsUsed += (Flags.getByValSize()+7)/8;
4811 switch (ArgVT.getSimpleVT().SimpleTy) {
4812 default: llvm_unreachable("Unexpected ValueType for argument!");
4816 if (++NumGPRsUsed <= NumGPRs)
4825 if (++NumVRsUsed <= NumVRs)
4829 // When using QPX, this is handled like a FP register, otherwise, it
4830 // is an Altivec register.
4831 if (Subtarget.hasQPX()) {
4832 if (++NumFPRsUsed <= NumFPRs)
4835 if (++NumVRsUsed <= NumVRs)
4841 case MVT::v4f64: // QPX
4842 case MVT::v4i1: // QPX
4843 if (++NumFPRsUsed <= NumFPRs)
4849 /* Respect alignment of argument on the stack. */
4851 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4852 NumBytes = ((NumBytes + Align - 1) / Align) * Align;
4854 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4855 if (Flags.isInConsecutiveRegsLast())
4856 NumBytes = ((NumBytes + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4859 unsigned NumBytesActuallyUsed = NumBytes;
4861 // The prolog code of the callee may store up to 8 GPR argument registers to
4862 // the stack, allowing va_start to index over them in memory if its varargs.
4863 // Because we cannot tell if this is needed on the caller side, we have to
4864 // conservatively assume that it is needed. As such, make sure we have at
4865 // least enough stack space for the caller to store the 8 GPRs.
4866 // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
4867 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4869 // Tail call needs the stack to be aligned.
4870 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4871 CallConv == CallingConv::Fast)
4872 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes);
4874 // Calculate by how many bytes the stack has to be adjusted in case of tail
4875 // call optimization.
4876 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4878 // To protect arguments on the stack from being clobbered in a tail call,
4879 // force all the loads to happen before doing any other lowering.
4881 Chain = DAG.getStackArgumentTokenFactor(Chain);
4883 // Adjust the stack pointer for the new arguments...
4884 // These operations are automatically eliminated by the prolog/epilog pass
4885 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4887 SDValue CallSeqStart = Chain;
4889 // Load the return address and frame pointer so it can be move somewhere else
4892 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4895 // Set up a copy of the stack pointer for use loading and storing any
4896 // arguments that may not fit in the registers available for argument
4898 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4900 // Figure out which arguments are going to go in registers, and which in
4901 // memory. Also, if this is a vararg function, floating point operations
4902 // must be stored to our stack, and loaded into integer regs as well, if
4903 // any integer regs are available for argument passing.
4904 unsigned ArgOffset = LinkageSize;
4906 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4907 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4909 SmallVector<SDValue, 8> MemOpChains;
4910 for (unsigned i = 0; i != NumOps; ++i) {
4911 SDValue Arg = OutVals[i];
4912 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4913 EVT ArgVT = Outs[i].VT;
4914 EVT OrigVT = Outs[i].ArgVT;
4916 // PtrOff will be used to store the current argument to the stack if a
4917 // register cannot be found for it.
4920 // We re-align the argument offset for each argument, except when using the
4921 // fast calling convention, when we need to make sure we do that only when
4922 // we'll actually use a stack slot.
4923 auto ComputePtrOff = [&]() {
4924 /* Respect alignment of argument on the stack. */
4926 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4927 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
4929 PtrOff = DAG.getConstant(ArgOffset, dl, StackPtr.getValueType());
4931 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4934 if (CallConv != CallingConv::Fast) {
4937 /* Compute GPR index associated with argument offset. */
4938 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4939 GPR_idx = std::min(GPR_idx, NumGPRs);
4942 // Promote integers to 64-bit values.
4943 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4944 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4945 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4946 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4949 // FIXME memcpy is used way more than necessary. Correctness first.
4950 // Note: "by value" is code for passing a structure by value, not
4952 if (Flags.isByVal()) {
4953 // Note: Size includes alignment padding, so
4954 // struct x { short a; char b; }
4955 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4956 // These are the proper values we need for right-justifying the
4957 // aggregate in a parameter register.
4958 unsigned Size = Flags.getByValSize();
4960 // An empty aggregate parameter takes up no storage and no
4965 if (CallConv == CallingConv::Fast)
4968 // All aggregates smaller than 8 bytes must be passed right-justified.
4969 if (Size==1 || Size==2 || Size==4) {
4970 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4971 if (GPR_idx != NumGPRs) {
4972 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4973 MachinePointerInfo(), VT,
4974 false, false, false, 0);
4975 MemOpChains.push_back(Load.getValue(1));
4976 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4978 ArgOffset += PtrByteSize;
4983 if (GPR_idx == NumGPRs && Size < 8) {
4984 SDValue AddPtr = PtrOff;
4985 if (!isLittleEndian) {
4986 SDValue Const = DAG.getConstant(PtrByteSize - Size, dl,
4987 PtrOff.getValueType());
4988 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4990 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4993 ArgOffset += PtrByteSize;
4996 // Copy entire object into memory. There are cases where gcc-generated
4997 // code assumes it is there, even if it could be put entirely into
4998 // registers. (This is not what the doc says.)
5000 // FIXME: The above statement is likely due to a misunderstanding of the
5001 // documents. All arguments must be copied into the parameter area BY
5002 // THE CALLEE in the event that the callee takes the address of any
5003 // formal argument. That has not yet been implemented. However, it is
5004 // reasonable to use the stack area as a staging area for the register
5007 // Skip this for small aggregates, as we will use the same slot for a
5008 // right-justified copy, below.
5010 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
5014 // When a register is available, pass a small aggregate right-justified.
5015 if (Size < 8 && GPR_idx != NumGPRs) {
5016 // The easiest way to get this right-justified in a register
5017 // is to copy the structure into the rightmost portion of a
5018 // local variable slot, then load the whole slot into the
5020 // FIXME: The memcpy seems to produce pretty awful code for
5021 // small aggregates, particularly for packed ones.
5022 // FIXME: It would be preferable to use the slot in the
5023 // parameter save area instead of a new local variable.
5024 SDValue AddPtr = PtrOff;
5025 if (!isLittleEndian) {
5026 SDValue Const = DAG.getConstant(8 - Size, dl, PtrOff.getValueType());
5027 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
5029 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
5033 // Load the slot into the register.
5034 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
5035 MachinePointerInfo(),
5036 false, false, false, 0);
5037 MemOpChains.push_back(Load.getValue(1));
5038 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5040 // Done with this argument.
5041 ArgOffset += PtrByteSize;
5045 // For aggregates larger than PtrByteSize, copy the pieces of the
5046 // object that fit into registers from the parameter save area.
5047 for (unsigned j=0; j<Size; j+=PtrByteSize) {
5048 SDValue Const = DAG.getConstant(j, dl, PtrOff.getValueType());
5049 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
5050 if (GPR_idx != NumGPRs) {
5051 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
5052 MachinePointerInfo(),
5053 false, false, false, 0);
5054 MemOpChains.push_back(Load.getValue(1));
5055 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5056 ArgOffset += PtrByteSize;
5058 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
5065 switch (Arg.getSimpleValueType().SimpleTy) {
5066 default: llvm_unreachable("Unexpected ValueType for argument!");
5070 if (Flags.isNest()) {
5071 // The 'nest' parameter, if any, is passed in R11.
5072 RegsToPass.push_back(std::make_pair(PPC::X11, Arg));
5077 // These can be scalar arguments or elements of an integer array type
5078 // passed directly. Clang may use those instead of "byval" aggregate
5079 // types to avoid forcing arguments to memory unnecessarily.
5080 if (GPR_idx != NumGPRs) {
5081 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
5083 if (CallConv == CallingConv::Fast)
5086 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5087 true, isTailCall, false, MemOpChains,
5088 TailCallArguments, dl);
5089 if (CallConv == CallingConv::Fast)
5090 ArgOffset += PtrByteSize;
5092 if (CallConv != CallingConv::Fast)
5093 ArgOffset += PtrByteSize;
5097 // These can be scalar arguments or elements of a float array type
5098 // passed directly. The latter are used to implement ELFv2 homogenous
5099 // float aggregates.
5101 // Named arguments go into FPRs first, and once they overflow, the
5102 // remaining arguments go into GPRs and then the parameter save area.
5103 // Unnamed arguments for vararg functions always go to GPRs and
5104 // then the parameter save area. For now, put all arguments to vararg
5105 // routines always in both locations (FPR *and* GPR or stack slot).
5106 bool NeedGPROrStack = isVarArg || FPR_idx == NumFPRs;
5107 bool NeededLoad = false;
5109 // First load the argument into the next available FPR.
5110 if (FPR_idx != NumFPRs)
5111 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
5113 // Next, load the argument into GPR or stack slot if needed.
5114 if (!NeedGPROrStack)
5116 else if (GPR_idx != NumGPRs && CallConv != CallingConv::Fast) {
5117 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
5118 // once we support fp <-> gpr moves.
5120 // In the non-vararg case, this can only ever happen in the
5121 // presence of f32 array types, since otherwise we never run
5122 // out of FPRs before running out of GPRs.
5125 // Double values are always passed in a single GPR.
5126 if (Arg.getValueType() != MVT::f32) {
5127 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
5129 // Non-array float values are extended and passed in a GPR.
5130 } else if (!Flags.isInConsecutiveRegs()) {
5131 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
5132 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
5134 // If we have an array of floats, we collect every odd element
5135 // together with its predecessor into one GPR.
5136 } else if (ArgOffset % PtrByteSize != 0) {
5138 Lo = DAG.getNode(ISD::BITCAST, dl, MVT::i32, OutVals[i - 1]);
5139 Hi = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
5140 if (!isLittleEndian)
5142 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
5144 // The final element, if even, goes into the first half of a GPR.
5145 } else if (Flags.isInConsecutiveRegsLast()) {
5146 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
5147 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
5148 if (!isLittleEndian)
5149 ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal,
5150 DAG.getConstant(32, dl, MVT::i32));
5152 // Non-final even elements are skipped; they will be handled
5153 // together the with subsequent argument on the next go-around.
5157 if (ArgVal.getNode())
5158 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], ArgVal));
5160 if (CallConv == CallingConv::Fast)
5163 // Single-precision floating-point values are mapped to the
5164 // second (rightmost) word of the stack doubleword.
5165 if (Arg.getValueType() == MVT::f32 &&
5166 !isLittleEndian && !Flags.isInConsecutiveRegs()) {
5167 SDValue ConstFour = DAG.getConstant(4, dl, PtrOff.getValueType());
5168 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
5171 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5172 true, isTailCall, false, MemOpChains,
5173 TailCallArguments, dl);
5177 // When passing an array of floats, the array occupies consecutive
5178 // space in the argument area; only round up to the next doubleword
5179 // at the end of the array. Otherwise, each float takes 8 bytes.
5180 if (CallConv != CallingConv::Fast || NeededLoad) {
5181 ArgOffset += (Arg.getValueType() == MVT::f32 &&
5182 Flags.isInConsecutiveRegs()) ? 4 : 8;
5183 if (Flags.isInConsecutiveRegsLast())
5184 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
5195 if (!Subtarget.hasQPX()) {
5196 // These can be scalar arguments or elements of a vector array type
5197 // passed directly. The latter are used to implement ELFv2 homogenous
5198 // vector aggregates.
5200 // For a varargs call, named arguments go into VRs or on the stack as
5201 // usual; unnamed arguments always go to the stack or the corresponding
5202 // GPRs when within range. For now, we always put the value in both
5203 // locations (or even all three).
5205 // We could elide this store in the case where the object fits
5206 // entirely in R registers. Maybe later.
5207 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5208 MachinePointerInfo(), false, false, 0);
5209 MemOpChains.push_back(Store);
5210 if (VR_idx != NumVRs) {
5211 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
5212 MachinePointerInfo(),
5213 false, false, false, 0);
5214 MemOpChains.push_back(Load.getValue(1));
5216 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
5217 Arg.getSimpleValueType() == MVT::v2i64) ?
5218 VSRH[VR_idx] : VR[VR_idx];
5221 RegsToPass.push_back(std::make_pair(VReg, Load));
5224 for (unsigned i=0; i<16; i+=PtrByteSize) {
5225 if (GPR_idx == NumGPRs)
5227 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5228 DAG.getConstant(i, dl, PtrVT));
5229 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5230 false, false, false, 0);
5231 MemOpChains.push_back(Load.getValue(1));
5232 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5237 // Non-varargs Altivec params go into VRs or on the stack.
5238 if (VR_idx != NumVRs) {
5239 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
5240 Arg.getSimpleValueType() == MVT::v2i64) ?
5241 VSRH[VR_idx] : VR[VR_idx];
5244 RegsToPass.push_back(std::make_pair(VReg, Arg));
5246 if (CallConv == CallingConv::Fast)
5249 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5250 true, isTailCall, true, MemOpChains,
5251 TailCallArguments, dl);
5252 if (CallConv == CallingConv::Fast)
5256 if (CallConv != CallingConv::Fast)
5261 assert(Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32 &&
5262 "Invalid QPX parameter type");
5267 bool IsF32 = Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32;
5269 // We could elide this store in the case where the object fits
5270 // entirely in R registers. Maybe later.
5271 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5272 MachinePointerInfo(), false, false, 0);
5273 MemOpChains.push_back(Store);
5274 if (QFPR_idx != NumQFPRs) {
5275 SDValue Load = DAG.getLoad(IsF32 ? MVT::v4f32 : MVT::v4f64, dl,
5276 Store, PtrOff, MachinePointerInfo(),
5277 false, false, false, 0);
5278 MemOpChains.push_back(Load.getValue(1));
5279 RegsToPass.push_back(std::make_pair(QFPR[QFPR_idx++], Load));
5281 ArgOffset += (IsF32 ? 16 : 32);
5282 for (unsigned i = 0; i < (IsF32 ? 16U : 32U); i += PtrByteSize) {
5283 if (GPR_idx == NumGPRs)
5285 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5286 DAG.getConstant(i, dl, PtrVT));
5287 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5288 false, false, false, 0);
5289 MemOpChains.push_back(Load.getValue(1));
5290 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5295 // Non-varargs QPX params go into registers or on the stack.
5296 if (QFPR_idx != NumQFPRs) {
5297 RegsToPass.push_back(std::make_pair(QFPR[QFPR_idx++], Arg));
5299 if (CallConv == CallingConv::Fast)
5302 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5303 true, isTailCall, true, MemOpChains,
5304 TailCallArguments, dl);
5305 if (CallConv == CallingConv::Fast)
5306 ArgOffset += (IsF32 ? 16 : 32);
5309 if (CallConv != CallingConv::Fast)
5310 ArgOffset += (IsF32 ? 16 : 32);
5316 assert(NumBytesActuallyUsed == ArgOffset);
5317 (void)NumBytesActuallyUsed;
5319 if (!MemOpChains.empty())
5320 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5322 // Check if this is an indirect call (MTCTR/BCTRL).
5323 // See PrepareCall() for more information about calls through function
5324 // pointers in the 64-bit SVR4 ABI.
5325 if (!isTailCall && !IsPatchPoint &&
5326 !isFunctionGlobalAddress(Callee) &&
5327 !isa<ExternalSymbolSDNode>(Callee)) {
5328 // Load r2 into a virtual register and store it to the TOC save area.
5329 setUsesTOCBasePtr(DAG);
5330 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
5331 // TOC save area offset.
5332 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
5333 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset, dl);
5334 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
5335 Chain = DAG.getStore(
5336 Val.getValue(1), dl, Val, AddPtr,
5337 MachinePointerInfo::getStack(DAG.getMachineFunction(), TOCSaveOffset),
5339 // In the ELFv2 ABI, R12 must contain the address of an indirect callee.
5340 // This does not mean the MTCTR instruction must use R12; it's easier
5341 // to model this as an extra parameter, so do that.
5342 if (isELFv2ABI && !IsPatchPoint)
5343 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
5346 // Build a sequence of copy-to-reg nodes chained together with token chain
5347 // and flag operands which copy the outgoing args into the appropriate regs.
5349 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5350 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5351 RegsToPass[i].second, InFlag);
5352 InFlag = Chain.getValue(1);
5356 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
5357 FPOp, true, TailCallArguments);
5359 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint, hasNest,
5360 DAG, RegsToPass, InFlag, Chain, CallSeqStart, Callee,
5361 SPDiff, NumBytes, Ins, InVals, CS);
5365 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
5366 CallingConv::ID CallConv, bool isVarArg,
5367 bool isTailCall, bool IsPatchPoint,
5368 const SmallVectorImpl<ISD::OutputArg> &Outs,
5369 const SmallVectorImpl<SDValue> &OutVals,
5370 const SmallVectorImpl<ISD::InputArg> &Ins,
5371 SDLoc dl, SelectionDAG &DAG,
5372 SmallVectorImpl<SDValue> &InVals,
5373 ImmutableCallSite *CS) const {
5375 unsigned NumOps = Outs.size();
5377 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
5378 bool isPPC64 = PtrVT == MVT::i64;
5379 unsigned PtrByteSize = isPPC64 ? 8 : 4;
5381 MachineFunction &MF = DAG.getMachineFunction();
5383 // Mark this function as potentially containing a function that contains a
5384 // tail call. As a consequence the frame pointer will be used for dynamicalloc
5385 // and restoring the callers stack pointer in this functions epilog. This is
5386 // done because by tail calling the called function might overwrite the value
5387 // in this function's (MF) stack pointer stack slot 0(SP).
5388 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5389 CallConv == CallingConv::Fast)
5390 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
5392 // Count how many bytes are to be pushed on the stack, including the linkage
5393 // area, and parameter passing area. We start with 24/48 bytes, which is
5394 // prereserved space for [SP][CR][LR][3 x unused].
5395 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
5396 unsigned NumBytes = LinkageSize;
5398 // Add up all the space actually used.
5399 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
5400 // they all go in registers, but we must reserve stack space for them for
5401 // possible use by the caller. In varargs or 64-bit calls, parameters are
5402 // assigned stack space in order, with padding so Altivec parameters are
5404 unsigned nAltivecParamsAtEnd = 0;
5405 for (unsigned i = 0; i != NumOps; ++i) {
5406 ISD::ArgFlagsTy Flags = Outs[i].Flags;
5407 EVT ArgVT = Outs[i].VT;
5408 // Varargs Altivec parameters are padded to a 16 byte boundary.
5409 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
5410 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
5411 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) {
5412 if (!isVarArg && !isPPC64) {
5413 // Non-varargs Altivec parameters go after all the non-Altivec
5414 // parameters; handle those later so we know how much padding we need.
5415 nAltivecParamsAtEnd++;
5418 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
5419 NumBytes = ((NumBytes+15)/16)*16;
5421 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
5424 // Allow for Altivec parameters at the end, if needed.
5425 if (nAltivecParamsAtEnd) {
5426 NumBytes = ((NumBytes+15)/16)*16;
5427 NumBytes += 16*nAltivecParamsAtEnd;
5430 // The prolog code of the callee may store up to 8 GPR argument registers to
5431 // the stack, allowing va_start to index over them in memory if its varargs.
5432 // Because we cannot tell if this is needed on the caller side, we have to
5433 // conservatively assume that it is needed. As such, make sure we have at
5434 // least enough stack space for the caller to store the 8 GPRs.
5435 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
5437 // Tail call needs the stack to be aligned.
5438 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5439 CallConv == CallingConv::Fast)
5440 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes);
5442 // Calculate by how many bytes the stack has to be adjusted in case of tail
5443 // call optimization.
5444 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
5446 // To protect arguments on the stack from being clobbered in a tail call,
5447 // force all the loads to happen before doing any other lowering.
5449 Chain = DAG.getStackArgumentTokenFactor(Chain);
5451 // Adjust the stack pointer for the new arguments...
5452 // These operations are automatically eliminated by the prolog/epilog pass
5453 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
5455 SDValue CallSeqStart = Chain;
5457 // Load the return address and frame pointer so it can be move somewhere else
5460 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
5463 // Set up a copy of the stack pointer for use loading and storing any
5464 // arguments that may not fit in the registers available for argument
5468 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
5470 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
5472 // Figure out which arguments are going to go in registers, and which in
5473 // memory. Also, if this is a vararg function, floating point operations
5474 // must be stored to our stack, and loaded into integer regs as well, if
5475 // any integer regs are available for argument passing.
5476 unsigned ArgOffset = LinkageSize;
5477 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
5479 static const MCPhysReg GPR_32[] = { // 32-bit registers.
5480 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
5481 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
5483 static const MCPhysReg GPR_64[] = { // 64-bit registers.
5484 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
5485 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
5487 static const MCPhysReg VR[] = {
5488 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
5489 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
5491 const unsigned NumGPRs = array_lengthof(GPR_32);
5492 const unsigned NumFPRs = 13;
5493 const unsigned NumVRs = array_lengthof(VR);
5495 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
5497 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
5498 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
5500 SmallVector<SDValue, 8> MemOpChains;
5501 for (unsigned i = 0; i != NumOps; ++i) {
5502 SDValue Arg = OutVals[i];
5503 ISD::ArgFlagsTy Flags = Outs[i].Flags;
5505 // PtrOff will be used to store the current argument to the stack if a
5506 // register cannot be found for it.
5509 PtrOff = DAG.getConstant(ArgOffset, dl, StackPtr.getValueType());
5511 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
5513 // On PPC64, promote integers to 64-bit values.
5514 if (isPPC64 && Arg.getValueType() == MVT::i32) {
5515 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
5516 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
5517 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
5520 // FIXME memcpy is used way more than necessary. Correctness first.
5521 // Note: "by value" is code for passing a structure by value, not
5523 if (Flags.isByVal()) {
5524 unsigned Size = Flags.getByValSize();
5525 // Very small objects are passed right-justified. Everything else is
5526 // passed left-justified.
5527 if (Size==1 || Size==2) {
5528 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
5529 if (GPR_idx != NumGPRs) {
5530 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
5531 MachinePointerInfo(), VT,
5532 false, false, false, 0);
5533 MemOpChains.push_back(Load.getValue(1));
5534 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5536 ArgOffset += PtrByteSize;
5538 SDValue Const = DAG.getConstant(PtrByteSize - Size, dl,
5539 PtrOff.getValueType());
5540 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
5541 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
5544 ArgOffset += PtrByteSize;
5548 // Copy entire object into memory. There are cases where gcc-generated
5549 // code assumes it is there, even if it could be put entirely into
5550 // registers. (This is not what the doc says.)
5551 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
5555 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
5556 // copy the pieces of the object that fit into registers from the
5557 // parameter save area.
5558 for (unsigned j=0; j<Size; j+=PtrByteSize) {
5559 SDValue Const = DAG.getConstant(j, dl, PtrOff.getValueType());
5560 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
5561 if (GPR_idx != NumGPRs) {
5562 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
5563 MachinePointerInfo(),
5564 false, false, false, 0);
5565 MemOpChains.push_back(Load.getValue(1));
5566 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5567 ArgOffset += PtrByteSize;
5569 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
5576 switch (Arg.getSimpleValueType().SimpleTy) {
5577 default: llvm_unreachable("Unexpected ValueType for argument!");
5581 if (GPR_idx != NumGPRs) {
5582 if (Arg.getValueType() == MVT::i1)
5583 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
5585 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
5587 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5588 isPPC64, isTailCall, false, MemOpChains,
5589 TailCallArguments, dl);
5591 ArgOffset += PtrByteSize;
5595 if (FPR_idx != NumFPRs) {
5596 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
5599 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5600 MachinePointerInfo(), false, false, 0);
5601 MemOpChains.push_back(Store);
5603 // Float varargs are always shadowed in available integer registers
5604 if (GPR_idx != NumGPRs) {
5605 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
5606 MachinePointerInfo(), false, false,
5608 MemOpChains.push_back(Load.getValue(1));
5609 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5611 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
5612 SDValue ConstFour = DAG.getConstant(4, dl, PtrOff.getValueType());
5613 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
5614 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
5615 MachinePointerInfo(),
5616 false, false, false, 0);
5617 MemOpChains.push_back(Load.getValue(1));
5618 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5621 // If we have any FPRs remaining, we may also have GPRs remaining.
5622 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
5624 if (GPR_idx != NumGPRs)
5626 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
5627 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
5631 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5632 isPPC64, isTailCall, false, MemOpChains,
5633 TailCallArguments, dl);
5637 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
5644 // These go aligned on the stack, or in the corresponding R registers
5645 // when within range. The Darwin PPC ABI doc claims they also go in
5646 // V registers; in fact gcc does this only for arguments that are
5647 // prototyped, not for those that match the ... We do it for all
5648 // arguments, seems to work.
5649 while (ArgOffset % 16 !=0) {
5650 ArgOffset += PtrByteSize;
5651 if (GPR_idx != NumGPRs)
5654 // We could elide this store in the case where the object fits
5655 // entirely in R registers. Maybe later.
5656 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
5657 DAG.getConstant(ArgOffset, dl, PtrVT));
5658 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5659 MachinePointerInfo(), false, false, 0);
5660 MemOpChains.push_back(Store);
5661 if (VR_idx != NumVRs) {
5662 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
5663 MachinePointerInfo(),
5664 false, false, false, 0);
5665 MemOpChains.push_back(Load.getValue(1));
5666 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
5669 for (unsigned i=0; i<16; i+=PtrByteSize) {
5670 if (GPR_idx == NumGPRs)
5672 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5673 DAG.getConstant(i, dl, PtrVT));
5674 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5675 false, false, false, 0);
5676 MemOpChains.push_back(Load.getValue(1));
5677 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5682 // Non-varargs Altivec params generally go in registers, but have
5683 // stack space allocated at the end.
5684 if (VR_idx != NumVRs) {
5685 // Doesn't have GPR space allocated.
5686 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
5687 } else if (nAltivecParamsAtEnd==0) {
5688 // We are emitting Altivec params in order.
5689 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5690 isPPC64, isTailCall, true, MemOpChains,
5691 TailCallArguments, dl);
5697 // If all Altivec parameters fit in registers, as they usually do,
5698 // they get stack space following the non-Altivec parameters. We
5699 // don't track this here because nobody below needs it.
5700 // If there are more Altivec parameters than fit in registers emit
5702 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
5704 // Offset is aligned; skip 1st 12 params which go in V registers.
5705 ArgOffset = ((ArgOffset+15)/16)*16;
5707 for (unsigned i = 0; i != NumOps; ++i) {
5708 SDValue Arg = OutVals[i];
5709 EVT ArgType = Outs[i].VT;
5710 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
5711 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
5714 // We are emitting Altivec params in order.
5715 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5716 isPPC64, isTailCall, true, MemOpChains,
5717 TailCallArguments, dl);
5724 if (!MemOpChains.empty())
5725 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5727 // On Darwin, R12 must contain the address of an indirect callee. This does
5728 // not mean the MTCTR instruction must use R12; it's easier to model this as
5729 // an extra parameter, so do that.
5731 !isFunctionGlobalAddress(Callee) &&
5732 !isa<ExternalSymbolSDNode>(Callee) &&
5733 !isBLACompatibleAddress(Callee, DAG))
5734 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
5735 PPC::R12), Callee));
5737 // Build a sequence of copy-to-reg nodes chained together with token chain
5738 // and flag operands which copy the outgoing args into the appropriate regs.
5740 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5741 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5742 RegsToPass[i].second, InFlag);
5743 InFlag = Chain.getValue(1);
5747 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
5748 FPOp, true, TailCallArguments);
5750 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint,
5751 /* unused except on PPC64 ELFv1 */ false, DAG,
5752 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
5753 NumBytes, Ins, InVals, CS);
5757 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
5758 MachineFunction &MF, bool isVarArg,
5759 const SmallVectorImpl<ISD::OutputArg> &Outs,
5760 LLVMContext &Context) const {
5761 SmallVector<CCValAssign, 16> RVLocs;
5762 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
5763 return CCInfo.CheckReturn(Outs, RetCC_PPC);
5767 PPCTargetLowering::LowerReturn(SDValue Chain,
5768 CallingConv::ID CallConv, bool isVarArg,
5769 const SmallVectorImpl<ISD::OutputArg> &Outs,
5770 const SmallVectorImpl<SDValue> &OutVals,
5771 SDLoc dl, SelectionDAG &DAG) const {
5773 SmallVector<CCValAssign, 16> RVLocs;
5774 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
5776 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
5779 SmallVector<SDValue, 4> RetOps(1, Chain);
5781 // Copy the result values into the output registers.
5782 for (unsigned i = 0; i != RVLocs.size(); ++i) {
5783 CCValAssign &VA = RVLocs[i];
5784 assert(VA.isRegLoc() && "Can only return in registers!");
5786 SDValue Arg = OutVals[i];
5788 switch (VA.getLocInfo()) {
5789 default: llvm_unreachable("Unknown loc info!");
5790 case CCValAssign::Full: break;
5791 case CCValAssign::AExt:
5792 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
5794 case CCValAssign::ZExt:
5795 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
5797 case CCValAssign::SExt:
5798 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
5802 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
5803 Flag = Chain.getValue(1);
5804 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
5807 RetOps[0] = Chain; // Update chain.
5809 // Add the flag if we have it.
5811 RetOps.push_back(Flag);
5813 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
5816 SDValue PPCTargetLowering::LowerGET_DYNAMIC_AREA_OFFSET(
5817 SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget) const {
5820 // Get the corect type for integers.
5821 EVT IntVT = Op.getValueType();
5824 SDValue Chain = Op.getOperand(0);
5825 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
5826 // Build a DYNAREAOFFSET node.
5827 SDValue Ops[2] = {Chain, FPSIdx};
5828 SDVTList VTs = DAG.getVTList(IntVT);
5829 return DAG.getNode(PPCISD::DYNAREAOFFSET, dl, VTs, Ops);
5832 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
5833 const PPCSubtarget &Subtarget) const {
5834 // When we pop the dynamic allocation we need to restore the SP link.
5837 // Get the corect type for pointers.
5838 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
5840 // Construct the stack pointer operand.
5841 bool isPPC64 = Subtarget.isPPC64();
5842 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
5843 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
5845 // Get the operands for the STACKRESTORE.
5846 SDValue Chain = Op.getOperand(0);
5847 SDValue SaveSP = Op.getOperand(1);
5849 // Load the old link SP.
5850 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
5851 MachinePointerInfo(),
5852 false, false, false, 0);
5854 // Restore the stack pointer.
5855 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
5857 // Store the old link SP.
5858 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
5862 SDValue PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG &DAG) const {
5863 MachineFunction &MF = DAG.getMachineFunction();
5864 bool isPPC64 = Subtarget.isPPC64();
5865 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
5867 // Get current frame pointer save index. The users of this index will be
5868 // primarily DYNALLOC instructions.
5869 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5870 int RASI = FI->getReturnAddrSaveIndex();
5872 // If the frame pointer save index hasn't been defined yet.
5874 // Find out what the fix offset of the frame pointer save area.
5875 int LROffset = Subtarget.getFrameLowering()->getReturnSaveOffset();
5876 // Allocate the frame index for frame pointer save area.
5877 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, false);
5879 FI->setReturnAddrSaveIndex(RASI);
5881 return DAG.getFrameIndex(RASI, PtrVT);
5885 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
5886 MachineFunction &MF = DAG.getMachineFunction();
5887 bool isPPC64 = Subtarget.isPPC64();
5888 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
5890 // Get current frame pointer save index. The users of this index will be
5891 // primarily DYNALLOC instructions.
5892 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5893 int FPSI = FI->getFramePointerSaveIndex();
5895 // If the frame pointer save index hasn't been defined yet.
5897 // Find out what the fix offset of the frame pointer save area.
5898 int FPOffset = Subtarget.getFrameLowering()->getFramePointerSaveOffset();
5899 // Allocate the frame index for frame pointer save area.
5900 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
5902 FI->setFramePointerSaveIndex(FPSI);
5904 return DAG.getFrameIndex(FPSI, PtrVT);
5907 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5909 const PPCSubtarget &Subtarget) const {
5911 SDValue Chain = Op.getOperand(0);
5912 SDValue Size = Op.getOperand(1);
5915 // Get the corect type for pointers.
5916 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
5918 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
5919 DAG.getConstant(0, dl, PtrVT), Size);
5920 // Construct a node for the frame pointer save index.
5921 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
5922 // Build a DYNALLOC node.
5923 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
5924 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
5925 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
5928 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
5929 SelectionDAG &DAG) const {
5931 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
5932 DAG.getVTList(MVT::i32, MVT::Other),
5933 Op.getOperand(0), Op.getOperand(1));
5936 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
5937 SelectionDAG &DAG) const {
5939 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
5940 Op.getOperand(0), Op.getOperand(1));
5943 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
5944 if (Op.getValueType().isVector())
5945 return LowerVectorLoad(Op, DAG);
5947 assert(Op.getValueType() == MVT::i1 &&
5948 "Custom lowering only for i1 loads");
5950 // First, load 8 bits into 32 bits, then truncate to 1 bit.
5953 LoadSDNode *LD = cast<LoadSDNode>(Op);
5955 SDValue Chain = LD->getChain();
5956 SDValue BasePtr = LD->getBasePtr();
5957 MachineMemOperand *MMO = LD->getMemOperand();
5960 DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(DAG.getDataLayout()), Chain,
5961 BasePtr, MVT::i8, MMO);
5962 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
5964 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
5965 return DAG.getMergeValues(Ops, dl);
5968 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
5969 if (Op.getOperand(1).getValueType().isVector())
5970 return LowerVectorStore(Op, DAG);
5972 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
5973 "Custom lowering only for i1 stores");
5975 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
5978 StoreSDNode *ST = cast<StoreSDNode>(Op);
5980 SDValue Chain = ST->getChain();
5981 SDValue BasePtr = ST->getBasePtr();
5982 SDValue Value = ST->getValue();
5983 MachineMemOperand *MMO = ST->getMemOperand();
5985 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(DAG.getDataLayout()),
5987 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
5990 // FIXME: Remove this once the ANDI glue bug is fixed:
5991 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
5992 assert(Op.getValueType() == MVT::i1 &&
5993 "Custom lowering only for i1 results");
5996 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
6000 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
6002 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
6003 // Not FP? Not a fsel.
6004 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
6005 !Op.getOperand(2).getValueType().isFloatingPoint())
6008 // We might be able to do better than this under some circumstances, but in
6009 // general, fsel-based lowering of select is a finite-math-only optimization.
6010 // For more information, see section F.3 of the 2.06 ISA specification.
6011 if (!DAG.getTarget().Options.NoInfsFPMath ||
6012 !DAG.getTarget().Options.NoNaNsFPMath)
6014 // TODO: Propagate flags from the select rather than global settings.
6016 Flags.setNoInfs(true);
6017 Flags.setNoNaNs(true);
6019 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
6021 EVT ResVT = Op.getValueType();
6022 EVT CmpVT = Op.getOperand(0).getValueType();
6023 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6024 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
6027 // If the RHS of the comparison is a 0.0, we don't need to do the
6028 // subtraction at all.
6030 if (isFloatingPointZero(RHS))
6032 default: break; // SETUO etc aren't handled by fsel.
6036 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
6037 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
6038 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
6039 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
6040 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
6041 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
6042 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
6045 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
6048 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
6049 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
6050 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
6053 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
6056 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
6057 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
6058 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
6059 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
6064 default: break; // SETUO etc aren't handled by fsel.
6068 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, &Flags);
6069 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6070 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6071 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
6072 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
6073 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
6074 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
6075 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
6078 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, &Flags);
6079 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6080 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6081 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
6084 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, &Flags);
6085 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6086 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6087 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
6090 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS, &Flags);
6091 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6092 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6093 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
6096 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS, &Flags);
6097 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6098 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6099 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
6104 void PPCTargetLowering::LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
6107 assert(Op.getOperand(0).getValueType().isFloatingPoint());
6108 SDValue Src = Op.getOperand(0);
6109 if (Src.getValueType() == MVT::f32)
6110 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
6113 switch (Op.getSimpleValueType().SimpleTy) {
6114 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
6117 Op.getOpcode() == ISD::FP_TO_SINT
6119 : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ),
6123 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
6124 "i64 FP_TO_UINT is supported only with FPCVT");
6125 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
6131 // Convert the FP value to an int value through memory.
6132 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
6133 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
6134 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
6135 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
6136 MachinePointerInfo MPI =
6137 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
6139 // Emit a store to the stack slot.
6142 MachineFunction &MF = DAG.getMachineFunction();
6143 MachineMemOperand *MMO =
6144 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
6145 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
6146 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
6147 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
6149 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
6150 MPI, false, false, 0);
6152 // Result is a load from the stack slot. If loading 4 bytes, make sure to
6154 if (Op.getValueType() == MVT::i32 && !i32Stack) {
6155 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
6156 DAG.getConstant(4, dl, FIPtr.getValueType()));
6157 MPI = MPI.getWithOffset(4);
6165 /// \brief Custom lowers floating point to integer conversions to use
6166 /// the direct move instructions available in ISA 2.07 to avoid the
6167 /// need for load/store combinations.
6168 SDValue PPCTargetLowering::LowerFP_TO_INTDirectMove(SDValue Op,
6171 assert(Op.getOperand(0).getValueType().isFloatingPoint());
6172 SDValue Src = Op.getOperand(0);
6174 if (Src.getValueType() == MVT::f32)
6175 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
6178 switch (Op.getSimpleValueType().SimpleTy) {
6179 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
6182 Op.getOpcode() == ISD::FP_TO_SINT
6184 : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ),
6186 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i32, Tmp);
6189 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
6190 "i64 FP_TO_UINT is supported only with FPCVT");
6191 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
6194 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i64, Tmp);
6200 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
6202 if (Subtarget.hasDirectMove() && Subtarget.isPPC64())
6203 return LowerFP_TO_INTDirectMove(Op, DAG, dl);
6206 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
6208 return DAG.getLoad(Op.getValueType(), dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
6209 false, RLI.IsInvariant, RLI.Alignment, RLI.AAInfo,
6213 // We're trying to insert a regular store, S, and then a load, L. If the
6214 // incoming value, O, is a load, we might just be able to have our load use the
6215 // address used by O. However, we don't know if anything else will store to
6216 // that address before we can load from it. To prevent this situation, we need
6217 // to insert our load, L, into the chain as a peer of O. To do this, we give L
6218 // the same chain operand as O, we create a token factor from the chain results
6219 // of O and L, and we replace all uses of O's chain result with that token
6220 // factor (see spliceIntoChain below for this last part).
6221 bool PPCTargetLowering::canReuseLoadAddress(SDValue Op, EVT MemVT,
6224 ISD::LoadExtType ET) const {
6226 if (ET == ISD::NON_EXTLOAD &&
6227 (Op.getOpcode() == ISD::FP_TO_UINT ||
6228 Op.getOpcode() == ISD::FP_TO_SINT) &&
6229 isOperationLegalOrCustom(Op.getOpcode(),
6230 Op.getOperand(0).getValueType())) {
6232 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
6236 LoadSDNode *LD = dyn_cast<LoadSDNode>(Op);
6237 if (!LD || LD->getExtensionType() != ET || LD->isVolatile() ||
6238 LD->isNonTemporal())
6240 if (LD->getMemoryVT() != MemVT)
6243 RLI.Ptr = LD->getBasePtr();
6244 if (LD->isIndexed() && LD->getOffset().getOpcode() != ISD::UNDEF) {
6245 assert(LD->getAddressingMode() == ISD::PRE_INC &&
6246 "Non-pre-inc AM on PPC?");
6247 RLI.Ptr = DAG.getNode(ISD::ADD, dl, RLI.Ptr.getValueType(), RLI.Ptr,
6251 RLI.Chain = LD->getChain();
6252 RLI.MPI = LD->getPointerInfo();
6253 RLI.IsInvariant = LD->isInvariant();
6254 RLI.Alignment = LD->getAlignment();
6255 RLI.AAInfo = LD->getAAInfo();
6256 RLI.Ranges = LD->getRanges();
6258 RLI.ResChain = SDValue(LD, LD->isIndexed() ? 2 : 1);
6262 // Given the head of the old chain, ResChain, insert a token factor containing
6263 // it and NewResChain, and make users of ResChain now be users of that token
6265 void PPCTargetLowering::spliceIntoChain(SDValue ResChain,
6266 SDValue NewResChain,
6267 SelectionDAG &DAG) const {
6271 SDLoc dl(NewResChain);
6273 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6274 NewResChain, DAG.getUNDEF(MVT::Other));
6275 assert(TF.getNode() != NewResChain.getNode() &&
6276 "A new TF really is required here");
6278 DAG.ReplaceAllUsesOfValueWith(ResChain, TF);
6279 DAG.UpdateNodeOperands(TF.getNode(), ResChain, NewResChain);
6282 /// \brief Custom lowers integer to floating point conversions to use
6283 /// the direct move instructions available in ISA 2.07 to avoid the
6284 /// need for load/store combinations.
6285 SDValue PPCTargetLowering::LowerINT_TO_FPDirectMove(SDValue Op,
6288 assert((Op.getValueType() == MVT::f32 ||
6289 Op.getValueType() == MVT::f64) &&
6290 "Invalid floating point type as target of conversion");
6291 assert(Subtarget.hasFPCVT() &&
6292 "Int to FP conversions with direct moves require FPCVT");
6294 SDValue Src = Op.getOperand(0);
6295 bool SinglePrec = Op.getValueType() == MVT::f32;
6296 bool WordInt = Src.getSimpleValueType().SimpleTy == MVT::i32;
6297 bool Signed = Op.getOpcode() == ISD::SINT_TO_FP;
6298 unsigned ConvOp = Signed ? (SinglePrec ? PPCISD::FCFIDS : PPCISD::FCFID) :
6299 (SinglePrec ? PPCISD::FCFIDUS : PPCISD::FCFIDU);
6302 FP = DAG.getNode(Signed ? PPCISD::MTVSRA : PPCISD::MTVSRZ,
6304 FP = DAG.getNode(ConvOp, dl, SinglePrec ? MVT::f32 : MVT::f64, FP);
6307 FP = DAG.getNode(PPCISD::MTVSRA, dl, MVT::f64, Src);
6308 FP = DAG.getNode(ConvOp, dl, SinglePrec ? MVT::f32 : MVT::f64, FP);
6314 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
6315 SelectionDAG &DAG) const {
6318 if (Subtarget.hasQPX() && Op.getOperand(0).getValueType() == MVT::v4i1) {
6319 if (Op.getValueType() != MVT::v4f32 && Op.getValueType() != MVT::v4f64)
6322 SDValue Value = Op.getOperand(0);
6323 // The values are now known to be -1 (false) or 1 (true). To convert this
6324 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
6325 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
6326 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
6328 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::f64);
6329 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64, FPHalfs, FPHalfs,
6332 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
6334 if (Op.getValueType() != MVT::v4f64)
6335 Value = DAG.getNode(ISD::FP_ROUND, dl,
6336 Op.getValueType(), Value,
6337 DAG.getIntPtrConstant(1, dl));
6341 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
6342 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
6345 if (Op.getOperand(0).getValueType() == MVT::i1)
6346 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
6347 DAG.getConstantFP(1.0, dl, Op.getValueType()),
6348 DAG.getConstantFP(0.0, dl, Op.getValueType()));
6350 // If we have direct moves, we can do all the conversion, skip the store/load
6351 // however, without FPCVT we can't do most conversions.
6352 if (Subtarget.hasDirectMove() && Subtarget.isPPC64() && Subtarget.hasFPCVT())
6353 return LowerINT_TO_FPDirectMove(Op, DAG, dl);
6355 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
6356 "UINT_TO_FP is supported only with FPCVT");
6358 // If we have FCFIDS, then use it when converting to single-precision.
6359 // Otherwise, convert to double-precision and then round.
6360 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
6361 ? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
6363 : (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
6365 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
6369 if (Op.getOperand(0).getValueType() == MVT::i64) {
6370 SDValue SINT = Op.getOperand(0);
6371 // When converting to single-precision, we actually need to convert
6372 // to double-precision first and then round to single-precision.
6373 // To avoid double-rounding effects during that operation, we have
6374 // to prepare the input operand. Bits that might be truncated when
6375 // converting to double-precision are replaced by a bit that won't
6376 // be lost at this stage, but is below the single-precision rounding
6379 // However, if -enable-unsafe-fp-math is in effect, accept double
6380 // rounding to avoid the extra overhead.
6381 if (Op.getValueType() == MVT::f32 &&
6382 !Subtarget.hasFPCVT() &&
6383 !DAG.getTarget().Options.UnsafeFPMath) {
6385 // Twiddle input to make sure the low 11 bits are zero. (If this
6386 // is the case, we are guaranteed the value will fit into the 53 bit
6387 // mantissa of an IEEE double-precision value without rounding.)
6388 // If any of those low 11 bits were not zero originally, make sure
6389 // bit 12 (value 2048) is set instead, so that the final rounding
6390 // to single-precision gets the correct result.
6391 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
6392 SINT, DAG.getConstant(2047, dl, MVT::i64));
6393 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
6394 Round, DAG.getConstant(2047, dl, MVT::i64));
6395 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
6396 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
6397 Round, DAG.getConstant(-2048, dl, MVT::i64));
6399 // However, we cannot use that value unconditionally: if the magnitude
6400 // of the input value is small, the bit-twiddling we did above might
6401 // end up visibly changing the output. Fortunately, in that case, we
6402 // don't need to twiddle bits since the original input will convert
6403 // exactly to double-precision floating-point already. Therefore,
6404 // construct a conditional to use the original value if the top 11
6405 // bits are all sign-bit copies, and use the rounded value computed
6407 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
6408 SINT, DAG.getConstant(53, dl, MVT::i32));
6409 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
6410 Cond, DAG.getConstant(1, dl, MVT::i64));
6411 Cond = DAG.getSetCC(dl, MVT::i32,
6412 Cond, DAG.getConstant(1, dl, MVT::i64), ISD::SETUGT);
6414 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
6420 MachineFunction &MF = DAG.getMachineFunction();
6421 if (canReuseLoadAddress(SINT, MVT::i64, RLI, DAG)) {
6422 Bits = DAG.getLoad(MVT::f64, dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
6423 false, RLI.IsInvariant, RLI.Alignment, RLI.AAInfo,
6425 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
6426 } else if (Subtarget.hasLFIWAX() &&
6427 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::SEXTLOAD)) {
6428 MachineMemOperand *MMO =
6429 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6430 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6431 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6432 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWAX, dl,
6433 DAG.getVTList(MVT::f64, MVT::Other),
6434 Ops, MVT::i32, MMO);
6435 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
6436 } else if (Subtarget.hasFPCVT() &&
6437 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::ZEXTLOAD)) {
6438 MachineMemOperand *MMO =
6439 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6440 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6441 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6442 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWZX, dl,
6443 DAG.getVTList(MVT::f64, MVT::Other),
6444 Ops, MVT::i32, MMO);
6445 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
6446 } else if (((Subtarget.hasLFIWAX() &&
6447 SINT.getOpcode() == ISD::SIGN_EXTEND) ||
6448 (Subtarget.hasFPCVT() &&
6449 SINT.getOpcode() == ISD::ZERO_EXTEND)) &&
6450 SINT.getOperand(0).getValueType() == MVT::i32) {
6451 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
6452 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
6454 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
6455 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6457 SDValue Store = DAG.getStore(
6458 DAG.getEntryNode(), dl, SINT.getOperand(0), FIdx,
6459 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx),
6462 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
6463 "Expected an i32 store");
6468 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
6471 MachineMemOperand *MMO =
6472 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6473 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6474 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6475 Bits = DAG.getMemIntrinsicNode(SINT.getOpcode() == ISD::ZERO_EXTEND ?
6476 PPCISD::LFIWZX : PPCISD::LFIWAX,
6477 dl, DAG.getVTList(MVT::f64, MVT::Other),
6478 Ops, MVT::i32, MMO);
6480 Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
6482 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
6484 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
6485 FP = DAG.getNode(ISD::FP_ROUND, dl,
6486 MVT::f32, FP, DAG.getIntPtrConstant(0, dl));
6490 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
6491 "Unhandled INT_TO_FP type in custom expander!");
6492 // Since we only generate this in 64-bit mode, we can take advantage of
6493 // 64-bit registers. In particular, sign extend the input value into the
6494 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
6495 // then lfd it and fcfid it.
6496 MachineFunction &MF = DAG.getMachineFunction();
6497 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
6498 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
6501 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
6504 if (!(ReusingLoad = canReuseLoadAddress(Op.getOperand(0), MVT::i32, RLI,
6506 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
6507 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6509 SDValue Store = DAG.getStore(
6510 DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
6511 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx),
6514 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
6515 "Expected an i32 store");
6520 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
6524 MachineMemOperand *MMO =
6525 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6526 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6527 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6528 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
6529 PPCISD::LFIWZX : PPCISD::LFIWAX,
6530 dl, DAG.getVTList(MVT::f64, MVT::Other),
6531 Ops, MVT::i32, MMO);
6533 spliceIntoChain(RLI.ResChain, Ld.getValue(1), DAG);
6535 assert(Subtarget.isPPC64() &&
6536 "i32->FP without LFIWAX supported only on PPC64");
6538 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
6539 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6541 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
6544 // STD the extended value into the stack slot.
6545 SDValue Store = DAG.getStore(
6546 DAG.getEntryNode(), dl, Ext64, FIdx,
6547 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx),
6550 // Load the value as a double.
6552 MVT::f64, dl, Store, FIdx,
6553 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx),
6554 false, false, false, 0);
6557 // FCFID it and return it.
6558 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
6559 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
6560 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP,
6561 DAG.getIntPtrConstant(0, dl));
6565 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
6566 SelectionDAG &DAG) const {
6569 The rounding mode is in bits 30:31 of FPSR, and has the following
6576 FLT_ROUNDS, on the other hand, expects the following:
6583 To perform the conversion, we do:
6584 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
6587 MachineFunction &MF = DAG.getMachineFunction();
6588 EVT VT = Op.getValueType();
6589 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
6591 // Save FP Control Word to register
6593 MVT::f64, // return register
6594 MVT::Glue // unused in this context
6596 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
6598 // Save FP register to stack slot
6599 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
6600 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
6601 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
6602 StackSlot, MachinePointerInfo(), false, false,0);
6604 // Load FP Control Word from low 32 bits of stack slot.
6605 SDValue Four = DAG.getConstant(4, dl, PtrVT);
6606 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
6607 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
6608 false, false, false, 0);
6610 // Transform as necessary
6612 DAG.getNode(ISD::AND, dl, MVT::i32,
6613 CWD, DAG.getConstant(3, dl, MVT::i32));
6615 DAG.getNode(ISD::SRL, dl, MVT::i32,
6616 DAG.getNode(ISD::AND, dl, MVT::i32,
6617 DAG.getNode(ISD::XOR, dl, MVT::i32,
6618 CWD, DAG.getConstant(3, dl, MVT::i32)),
6619 DAG.getConstant(3, dl, MVT::i32)),
6620 DAG.getConstant(1, dl, MVT::i32));
6623 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
6625 return DAG.getNode((VT.getSizeInBits() < 16 ?
6626 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
6629 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
6630 EVT VT = Op.getValueType();
6631 unsigned BitWidth = VT.getSizeInBits();
6633 assert(Op.getNumOperands() == 3 &&
6634 VT == Op.getOperand(1).getValueType() &&
6637 // Expand into a bunch of logical ops. Note that these ops
6638 // depend on the PPC behavior for oversized shift amounts.
6639 SDValue Lo = Op.getOperand(0);
6640 SDValue Hi = Op.getOperand(1);
6641 SDValue Amt = Op.getOperand(2);
6642 EVT AmtVT = Amt.getValueType();
6644 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6645 DAG.getConstant(BitWidth, dl, AmtVT), Amt);
6646 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
6647 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
6648 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
6649 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6650 DAG.getConstant(-BitWidth, dl, AmtVT));
6651 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
6652 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
6653 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
6654 SDValue OutOps[] = { OutLo, OutHi };
6655 return DAG.getMergeValues(OutOps, dl);
6658 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
6659 EVT VT = Op.getValueType();
6661 unsigned BitWidth = VT.getSizeInBits();
6662 assert(Op.getNumOperands() == 3 &&
6663 VT == Op.getOperand(1).getValueType() &&
6666 // Expand into a bunch of logical ops. Note that these ops
6667 // depend on the PPC behavior for oversized shift amounts.
6668 SDValue Lo = Op.getOperand(0);
6669 SDValue Hi = Op.getOperand(1);
6670 SDValue Amt = Op.getOperand(2);
6671 EVT AmtVT = Amt.getValueType();
6673 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6674 DAG.getConstant(BitWidth, dl, AmtVT), Amt);
6675 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
6676 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
6677 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
6678 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6679 DAG.getConstant(-BitWidth, dl, AmtVT));
6680 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
6681 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
6682 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
6683 SDValue OutOps[] = { OutLo, OutHi };
6684 return DAG.getMergeValues(OutOps, dl);
6687 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
6689 EVT VT = Op.getValueType();
6690 unsigned BitWidth = VT.getSizeInBits();
6691 assert(Op.getNumOperands() == 3 &&
6692 VT == Op.getOperand(1).getValueType() &&
6695 // Expand into a bunch of logical ops, followed by a select_cc.
6696 SDValue Lo = Op.getOperand(0);
6697 SDValue Hi = Op.getOperand(1);
6698 SDValue Amt = Op.getOperand(2);
6699 EVT AmtVT = Amt.getValueType();
6701 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6702 DAG.getConstant(BitWidth, dl, AmtVT), Amt);
6703 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
6704 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
6705 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
6706 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6707 DAG.getConstant(-BitWidth, dl, AmtVT));
6708 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
6709 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
6710 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, dl, AmtVT),
6711 Tmp4, Tmp6, ISD::SETLE);
6712 SDValue OutOps[] = { OutLo, OutHi };
6713 return DAG.getMergeValues(OutOps, dl);
6716 //===----------------------------------------------------------------------===//
6717 // Vector related lowering.
6720 /// BuildSplatI - Build a canonical splati of Val with an element size of
6721 /// SplatSize. Cast the result to VT.
6722 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
6723 SelectionDAG &DAG, SDLoc dl) {
6724 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
6726 static const MVT VTys[] = { // canonical VT to use for each size.
6727 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
6730 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
6732 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
6736 EVT CanonicalVT = VTys[SplatSize-1];
6738 // Build a canonical splat for this value.
6739 SDValue Elt = DAG.getConstant(Val, dl, MVT::i32);
6740 SmallVector<SDValue, 8> Ops;
6741 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
6742 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
6743 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
6746 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
6747 /// specified intrinsic ID.
6748 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
6749 SelectionDAG &DAG, SDLoc dl,
6750 EVT DestVT = MVT::Other) {
6751 if (DestVT == MVT::Other) DestVT = Op.getValueType();
6752 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6753 DAG.getConstant(IID, dl, MVT::i32), Op);
6756 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
6757 /// specified intrinsic ID.
6758 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
6759 SelectionDAG &DAG, SDLoc dl,
6760 EVT DestVT = MVT::Other) {
6761 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
6762 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6763 DAG.getConstant(IID, dl, MVT::i32), LHS, RHS);
6766 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
6767 /// specified intrinsic ID.
6768 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
6769 SDValue Op2, SelectionDAG &DAG,
6770 SDLoc dl, EVT DestVT = MVT::Other) {
6771 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
6772 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6773 DAG.getConstant(IID, dl, MVT::i32), Op0, Op1, Op2);
6776 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
6777 /// amount. The result has the specified value type.
6778 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
6779 EVT VT, SelectionDAG &DAG, SDLoc dl) {
6780 // Force LHS/RHS to be the right type.
6781 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
6782 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
6785 for (unsigned i = 0; i != 16; ++i)
6787 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
6788 return DAG.getNode(ISD::BITCAST, dl, VT, T);
6791 // If this is a case we can't handle, return null and let the default
6792 // expansion code take care of it. If we CAN select this case, and if it
6793 // selects to a single instruction, return Op. Otherwise, if we can codegen
6794 // this case more efficiently than a constant pool load, lower it to the
6795 // sequence of ops that should be used.
6796 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
6797 SelectionDAG &DAG) const {
6799 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6800 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
6802 if (Subtarget.hasQPX() && Op.getValueType() == MVT::v4i1) {
6803 // We first build an i32 vector, load it into a QPX register,
6804 // then convert it to a floating-point vector and compare it
6805 // to a zero vector to get the boolean result.
6806 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6807 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
6808 MachinePointerInfo PtrInfo =
6809 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
6810 EVT PtrVT = getPointerTy(DAG.getDataLayout());
6811 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6813 assert(BVN->getNumOperands() == 4 &&
6814 "BUILD_VECTOR for v4i1 does not have 4 operands");
6816 bool IsConst = true;
6817 for (unsigned i = 0; i < 4; ++i) {
6818 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF) continue;
6819 if (!isa<ConstantSDNode>(BVN->getOperand(i))) {
6827 ConstantFP::get(Type::getFloatTy(*DAG.getContext()), 1.0);
6829 ConstantFP::get(Type::getFloatTy(*DAG.getContext()), -1.0);
6831 SmallVector<Constant*, 4> CV(4, NegOne);
6832 for (unsigned i = 0; i < 4; ++i) {
6833 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF)
6834 CV[i] = UndefValue::get(Type::getFloatTy(*DAG.getContext()));
6835 else if (isNullConstant(BVN->getOperand(i)))
6841 Constant *CP = ConstantVector::get(CV);
6842 SDValue CPIdx = DAG.getConstantPool(CP, getPointerTy(DAG.getDataLayout()),
6843 16 /* alignment */);
6845 SmallVector<SDValue, 2> Ops;
6846 Ops.push_back(DAG.getEntryNode());
6847 Ops.push_back(CPIdx);
6849 SmallVector<EVT, 2> ValueVTs;
6850 ValueVTs.push_back(MVT::v4i1);
6851 ValueVTs.push_back(MVT::Other); // chain
6852 SDVTList VTs = DAG.getVTList(ValueVTs);
6854 return DAG.getMemIntrinsicNode(
6855 PPCISD::QVLFSb, dl, VTs, Ops, MVT::v4f32,
6856 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
6859 SmallVector<SDValue, 4> Stores;
6860 for (unsigned i = 0; i < 4; ++i) {
6861 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF) continue;
6863 unsigned Offset = 4*i;
6864 SDValue Idx = DAG.getConstant(Offset, dl, FIdx.getValueType());
6865 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
6867 unsigned StoreSize = BVN->getOperand(i).getValueType().getStoreSize();
6868 if (StoreSize > 4) {
6869 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
6870 BVN->getOperand(i), Idx,
6871 PtrInfo.getWithOffset(Offset),
6872 MVT::i32, false, false, 0));
6874 SDValue StoreValue = BVN->getOperand(i);
6876 StoreValue = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, StoreValue);
6878 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
6880 PtrInfo.getWithOffset(Offset),
6886 if (!Stores.empty())
6887 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
6889 StoreChain = DAG.getEntryNode();
6891 // Now load from v4i32 into the QPX register; this will extend it to
6892 // v4i64 but not yet convert it to a floating point. Nevertheless, this
6893 // is typed as v4f64 because the QPX register integer states are not
6894 // explicitly represented.
6896 SmallVector<SDValue, 2> Ops;
6897 Ops.push_back(StoreChain);
6898 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvlfiwz, dl, MVT::i32));
6899 Ops.push_back(FIdx);
6901 SmallVector<EVT, 2> ValueVTs;
6902 ValueVTs.push_back(MVT::v4f64);
6903 ValueVTs.push_back(MVT::Other); // chain
6904 SDVTList VTs = DAG.getVTList(ValueVTs);
6906 SDValue LoadedVect = DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN,
6907 dl, VTs, Ops, MVT::v4i32, PtrInfo);
6908 LoadedVect = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
6909 DAG.getConstant(Intrinsic::ppc_qpx_qvfcfidu, dl, MVT::i32),
6912 SDValue FPZeros = DAG.getConstantFP(0.0, dl, MVT::f64);
6913 FPZeros = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
6914 FPZeros, FPZeros, FPZeros, FPZeros);
6916 return DAG.getSetCC(dl, MVT::v4i1, LoadedVect, FPZeros, ISD::SETEQ);
6919 // All other QPX vectors are handled by generic code.
6920 if (Subtarget.hasQPX())
6923 // Check if this is a splat of a constant value.
6924 APInt APSplatBits, APSplatUndef;
6925 unsigned SplatBitSize;
6927 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
6928 HasAnyUndefs, 0, !Subtarget.isLittleEndian()) ||
6932 unsigned SplatBits = APSplatBits.getZExtValue();
6933 unsigned SplatUndef = APSplatUndef.getZExtValue();
6934 unsigned SplatSize = SplatBitSize / 8;
6936 // First, handle single instruction cases.
6939 if (SplatBits == 0) {
6940 // Canonicalize all zero vectors to be v4i32.
6941 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
6942 SDValue Z = DAG.getConstant(0, dl, MVT::i32);
6943 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
6944 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
6949 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
6950 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
6952 if (SextVal >= -16 && SextVal <= 15)
6953 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
6955 // Two instruction sequences.
6957 // If this value is in the range [-32,30] and is even, use:
6958 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
6959 // If this value is in the range [17,31] and is odd, use:
6960 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
6961 // If this value is in the range [-31,-17] and is odd, use:
6962 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
6963 // Note the last two are three-instruction sequences.
6964 if (SextVal >= -32 && SextVal <= 31) {
6965 // To avoid having these optimizations undone by constant folding,
6966 // we convert to a pseudo that will be expanded later into one of
6968 SDValue Elt = DAG.getConstant(SextVal, dl, MVT::i32);
6969 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
6970 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
6971 SDValue EltSize = DAG.getConstant(SplatSize, dl, MVT::i32);
6972 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
6973 if (VT == Op.getValueType())
6976 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
6979 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
6980 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
6982 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
6983 // Make -1 and vspltisw -1:
6984 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
6986 // Make the VSLW intrinsic, computing 0x8000_0000.
6987 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
6990 // xor by OnesV to invert it.
6991 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
6992 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6995 // Check to see if this is a wide variety of vsplti*, binop self cases.
6996 static const signed char SplatCsts[] = {
6997 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
6998 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
7001 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
7002 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
7003 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
7004 int i = SplatCsts[idx];
7006 // Figure out what shift amount will be used by altivec if shifted by i in
7008 unsigned TypeShiftAmt = i & (SplatBitSize-1);
7010 // vsplti + shl self.
7011 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
7012 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
7013 static const unsigned IIDs[] = { // Intrinsic to use for each size.
7014 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
7015 Intrinsic::ppc_altivec_vslw
7017 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
7018 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7021 // vsplti + srl self.
7022 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
7023 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
7024 static const unsigned IIDs[] = { // Intrinsic to use for each size.
7025 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
7026 Intrinsic::ppc_altivec_vsrw
7028 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
7029 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7032 // vsplti + sra self.
7033 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
7034 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
7035 static const unsigned IIDs[] = { // Intrinsic to use for each size.
7036 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
7037 Intrinsic::ppc_altivec_vsraw
7039 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
7040 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7043 // vsplti + rol self.
7044 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
7045 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
7046 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
7047 static const unsigned IIDs[] = { // Intrinsic to use for each size.
7048 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
7049 Intrinsic::ppc_altivec_vrlw
7051 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
7052 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7055 // t = vsplti c, result = vsldoi t, t, 1
7056 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
7057 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
7058 unsigned Amt = Subtarget.isLittleEndian() ? 15 : 1;
7059 return BuildVSLDOI(T, T, Amt, Op.getValueType(), DAG, dl);
7061 // t = vsplti c, result = vsldoi t, t, 2
7062 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
7063 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
7064 unsigned Amt = Subtarget.isLittleEndian() ? 14 : 2;
7065 return BuildVSLDOI(T, T, Amt, Op.getValueType(), DAG, dl);
7067 // t = vsplti c, result = vsldoi t, t, 3
7068 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
7069 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
7070 unsigned Amt = Subtarget.isLittleEndian() ? 13 : 3;
7071 return BuildVSLDOI(T, T, Amt, Op.getValueType(), DAG, dl);
7078 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
7079 /// the specified operations to build the shuffle.
7080 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
7081 SDValue RHS, SelectionDAG &DAG,
7083 unsigned OpNum = (PFEntry >> 26) & 0x0F;
7084 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
7085 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
7088 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
7100 if (OpNum == OP_COPY) {
7101 if (LHSID == (1*9+2)*9+3) return LHS;
7102 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
7106 SDValue OpLHS, OpRHS;
7107 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
7108 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
7112 default: llvm_unreachable("Unknown i32 permute!");
7114 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
7115 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
7116 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
7117 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
7120 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
7121 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
7122 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
7123 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
7126 for (unsigned i = 0; i != 16; ++i)
7127 ShufIdxs[i] = (i&3)+0;
7130 for (unsigned i = 0; i != 16; ++i)
7131 ShufIdxs[i] = (i&3)+4;
7134 for (unsigned i = 0; i != 16; ++i)
7135 ShufIdxs[i] = (i&3)+8;
7138 for (unsigned i = 0; i != 16; ++i)
7139 ShufIdxs[i] = (i&3)+12;
7142 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
7144 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
7146 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
7148 EVT VT = OpLHS.getValueType();
7149 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
7150 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
7151 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
7152 return DAG.getNode(ISD::BITCAST, dl, VT, T);
7155 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
7156 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
7157 /// return the code it can be lowered into. Worst case, it can always be
7158 /// lowered into a vperm.
7159 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
7160 SelectionDAG &DAG) const {
7162 SDValue V1 = Op.getOperand(0);
7163 SDValue V2 = Op.getOperand(1);
7164 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7165 EVT VT = Op.getValueType();
7166 bool isLittleEndian = Subtarget.isLittleEndian();
7168 if (Subtarget.hasQPX()) {
7169 if (VT.getVectorNumElements() != 4)
7172 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
7174 int AlignIdx = PPC::isQVALIGNIShuffleMask(SVOp);
7175 if (AlignIdx != -1) {
7176 return DAG.getNode(PPCISD::QVALIGNI, dl, VT, V1, V2,
7177 DAG.getConstant(AlignIdx, dl, MVT::i32));
7178 } else if (SVOp->isSplat()) {
7179 int SplatIdx = SVOp->getSplatIndex();
7180 if (SplatIdx >= 4) {
7185 // FIXME: If SplatIdx == 0 and the input came from a load, then there is
7188 return DAG.getNode(PPCISD::QVESPLATI, dl, VT, V1,
7189 DAG.getConstant(SplatIdx, dl, MVT::i32));
7192 // Lower this into a qvgpci/qvfperm pair.
7194 // Compute the qvgpci literal
7196 for (unsigned i = 0; i < 4; ++i) {
7197 int m = SVOp->getMaskElt(i);
7198 unsigned mm = m >= 0 ? (unsigned) m : i;
7199 idx |= mm << (3-i)*3;
7202 SDValue V3 = DAG.getNode(PPCISD::QVGPCI, dl, MVT::v4f64,
7203 DAG.getConstant(idx, dl, MVT::i32));
7204 return DAG.getNode(PPCISD::QVFPERM, dl, VT, V1, V2, V3);
7207 // Cases that are handled by instructions that take permute immediates
7208 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
7209 // selected by the instruction selector.
7210 if (V2.getOpcode() == ISD::UNDEF) {
7211 if (PPC::isSplatShuffleMask(SVOp, 1) ||
7212 PPC::isSplatShuffleMask(SVOp, 2) ||
7213 PPC::isSplatShuffleMask(SVOp, 4) ||
7214 PPC::isVPKUWUMShuffleMask(SVOp, 1, DAG) ||
7215 PPC::isVPKUHUMShuffleMask(SVOp, 1, DAG) ||
7216 PPC::isVSLDOIShuffleMask(SVOp, 1, DAG) != -1 ||
7217 PPC::isVMRGLShuffleMask(SVOp, 1, 1, DAG) ||
7218 PPC::isVMRGLShuffleMask(SVOp, 2, 1, DAG) ||
7219 PPC::isVMRGLShuffleMask(SVOp, 4, 1, DAG) ||
7220 PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) ||
7221 PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) ||
7222 PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG) ||
7223 (Subtarget.hasP8Altivec() && (
7224 PPC::isVPKUDUMShuffleMask(SVOp, 1, DAG) ||
7225 PPC::isVMRGEOShuffleMask(SVOp, true, 1, DAG) ||
7226 PPC::isVMRGEOShuffleMask(SVOp, false, 1, DAG)))) {
7231 // Altivec has a variety of "shuffle immediates" that take two vector inputs
7232 // and produce a fixed permutation. If any of these match, do not lower to
7234 unsigned int ShuffleKind = isLittleEndian ? 2 : 0;
7235 if (PPC::isVPKUWUMShuffleMask(SVOp, ShuffleKind, DAG) ||
7236 PPC::isVPKUHUMShuffleMask(SVOp, ShuffleKind, DAG) ||
7237 PPC::isVSLDOIShuffleMask(SVOp, ShuffleKind, DAG) != -1 ||
7238 PPC::isVMRGLShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
7239 PPC::isVMRGLShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
7240 PPC::isVMRGLShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
7241 PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
7242 PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
7243 PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
7244 (Subtarget.hasP8Altivec() && (
7245 PPC::isVPKUDUMShuffleMask(SVOp, ShuffleKind, DAG) ||
7246 PPC::isVMRGEOShuffleMask(SVOp, true, ShuffleKind, DAG) ||
7247 PPC::isVMRGEOShuffleMask(SVOp, false, ShuffleKind, DAG))))
7250 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
7251 // perfect shuffle table to emit an optimal matching sequence.
7252 ArrayRef<int> PermMask = SVOp->getMask();
7254 unsigned PFIndexes[4];
7255 bool isFourElementShuffle = true;
7256 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
7257 unsigned EltNo = 8; // Start out undef.
7258 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
7259 if (PermMask[i*4+j] < 0)
7260 continue; // Undef, ignore it.
7262 unsigned ByteSource = PermMask[i*4+j];
7263 if ((ByteSource & 3) != j) {
7264 isFourElementShuffle = false;
7269 EltNo = ByteSource/4;
7270 } else if (EltNo != ByteSource/4) {
7271 isFourElementShuffle = false;
7275 PFIndexes[i] = EltNo;
7278 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
7279 // perfect shuffle vector to determine if it is cost effective to do this as
7280 // discrete instructions, or whether we should use a vperm.
7281 // For now, we skip this for little endian until such time as we have a
7282 // little-endian perfect shuffle table.
7283 if (isFourElementShuffle && !isLittleEndian) {
7284 // Compute the index in the perfect shuffle table.
7285 unsigned PFTableIndex =
7286 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
7288 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
7289 unsigned Cost = (PFEntry >> 30);
7291 // Determining when to avoid vperm is tricky. Many things affect the cost
7292 // of vperm, particularly how many times the perm mask needs to be computed.
7293 // For example, if the perm mask can be hoisted out of a loop or is already
7294 // used (perhaps because there are multiple permutes with the same shuffle
7295 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
7296 // the loop requires an extra register.
7298 // As a compromise, we only emit discrete instructions if the shuffle can be
7299 // generated in 3 or fewer operations. When we have loop information
7300 // available, if this block is within a loop, we should avoid using vperm
7301 // for 3-operation perms and use a constant pool load instead.
7303 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
7306 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
7307 // vector that will get spilled to the constant pool.
7308 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
7310 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
7311 // that it is in input element units, not in bytes. Convert now.
7313 // For little endian, the order of the input vectors is reversed, and
7314 // the permutation mask is complemented with respect to 31. This is
7315 // necessary to produce proper semantics with the big-endian-biased vperm
7317 EVT EltVT = V1.getValueType().getVectorElementType();
7318 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
7320 SmallVector<SDValue, 16> ResultMask;
7321 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
7322 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
7324 for (unsigned j = 0; j != BytesPerElement; ++j)
7326 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement + j),
7329 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement + j, dl,
7333 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
7336 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
7339 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
7343 /// getVectorCompareInfo - Given an intrinsic, return false if it is not a
7344 /// vector comparison. If it is, return true and fill in Opc/isDot with
7345 /// information about the intrinsic.
7346 static bool getVectorCompareInfo(SDValue Intrin, int &CompareOpc,
7347 bool &isDot, const PPCSubtarget &Subtarget) {
7348 unsigned IntrinsicID =
7349 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
7352 switch (IntrinsicID) {
7353 default: return false;
7354 // Comparison predicates.
7355 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
7356 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
7357 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
7358 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
7359 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
7360 case Intrinsic::ppc_altivec_vcmpequd_p:
7361 if (Subtarget.hasP8Altivec()) {
7368 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
7369 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
7370 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
7371 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
7372 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
7373 case Intrinsic::ppc_altivec_vcmpgtsd_p:
7374 if (Subtarget.hasP8Altivec()) {
7381 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
7382 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
7383 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
7384 case Intrinsic::ppc_altivec_vcmpgtud_p:
7385 if (Subtarget.hasP8Altivec()) {
7392 // VSX predicate comparisons use the same infrastructure
7393 case Intrinsic::ppc_vsx_xvcmpeqdp_p:
7394 case Intrinsic::ppc_vsx_xvcmpgedp_p:
7395 case Intrinsic::ppc_vsx_xvcmpgtdp_p:
7396 case Intrinsic::ppc_vsx_xvcmpeqsp_p:
7397 case Intrinsic::ppc_vsx_xvcmpgesp_p:
7398 case Intrinsic::ppc_vsx_xvcmpgtsp_p:
7399 if (Subtarget.hasVSX()) {
7400 switch (IntrinsicID) {
7401 case Intrinsic::ppc_vsx_xvcmpeqdp_p: CompareOpc = 99; break;
7402 case Intrinsic::ppc_vsx_xvcmpgedp_p: CompareOpc = 115; break;
7403 case Intrinsic::ppc_vsx_xvcmpgtdp_p: CompareOpc = 107; break;
7404 case Intrinsic::ppc_vsx_xvcmpeqsp_p: CompareOpc = 67; break;
7405 case Intrinsic::ppc_vsx_xvcmpgesp_p: CompareOpc = 83; break;
7406 case Intrinsic::ppc_vsx_xvcmpgtsp_p: CompareOpc = 75; break;
7415 // Normal Comparisons.
7416 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
7417 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
7418 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
7419 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
7420 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
7421 case Intrinsic::ppc_altivec_vcmpequd:
7422 if (Subtarget.hasP8Altivec()) {
7429 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
7430 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
7431 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
7432 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
7433 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
7434 case Intrinsic::ppc_altivec_vcmpgtsd:
7435 if (Subtarget.hasP8Altivec()) {
7442 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
7443 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
7444 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
7445 case Intrinsic::ppc_altivec_vcmpgtud:
7446 if (Subtarget.hasP8Altivec()) {
7457 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
7458 /// lower, do it, otherwise return null.
7459 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
7460 SelectionDAG &DAG) const {
7461 // If this is a lowered altivec predicate compare, CompareOpc is set to the
7462 // opcode number of the comparison.
7466 if (!getVectorCompareInfo(Op, CompareOpc, isDot, Subtarget))
7467 return SDValue(); // Don't custom lower most intrinsics.
7469 // If this is a non-dot comparison, make the VCMP node and we are done.
7471 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
7472 Op.getOperand(1), Op.getOperand(2),
7473 DAG.getConstant(CompareOpc, dl, MVT::i32));
7474 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
7477 // Create the PPCISD altivec 'dot' comparison node.
7479 Op.getOperand(2), // LHS
7480 Op.getOperand(3), // RHS
7481 DAG.getConstant(CompareOpc, dl, MVT::i32)
7483 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
7484 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
7486 // Now that we have the comparison, emit a copy from the CR to a GPR.
7487 // This is flagged to the above dot comparison.
7488 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
7489 DAG.getRegister(PPC::CR6, MVT::i32),
7490 CompNode.getValue(1));
7492 // Unpack the result based on how the target uses it.
7493 unsigned BitNo; // Bit # of CR6.
7494 bool InvertBit; // Invert result?
7495 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
7496 default: // Can't happen, don't crash on invalid number though.
7497 case 0: // Return the value of the EQ bit of CR6.
7498 BitNo = 0; InvertBit = false;
7500 case 1: // Return the inverted value of the EQ bit of CR6.
7501 BitNo = 0; InvertBit = true;
7503 case 2: // Return the value of the LT bit of CR6.
7504 BitNo = 2; InvertBit = false;
7506 case 3: // Return the inverted value of the LT bit of CR6.
7507 BitNo = 2; InvertBit = true;
7511 // Shift the bit into the low position.
7512 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
7513 DAG.getConstant(8 - (3 - BitNo), dl, MVT::i32));
7515 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
7516 DAG.getConstant(1, dl, MVT::i32));
7518 // If we are supposed to, toggle the bit.
7520 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
7521 DAG.getConstant(1, dl, MVT::i32));
7525 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
7526 SelectionDAG &DAG) const {
7528 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
7529 // instructions), but for smaller types, we need to first extend up to v2i32
7530 // before doing going farther.
7531 if (Op.getValueType() == MVT::v2i64) {
7532 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
7533 if (ExtVT != MVT::v2i32) {
7534 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
7535 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
7536 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
7537 ExtVT.getVectorElementType(), 4)));
7538 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
7539 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
7540 DAG.getValueType(MVT::v2i32));
7549 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
7550 SelectionDAG &DAG) const {
7552 // Create a stack slot that is 16-byte aligned.
7553 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
7554 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
7555 EVT PtrVT = getPointerTy(DAG.getDataLayout());
7556 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
7558 // Store the input value into Value#0 of the stack slot.
7559 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
7560 Op.getOperand(0), FIdx, MachinePointerInfo(),
7563 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
7564 false, false, false, 0);
7567 SDValue PPCTargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
7568 SelectionDAG &DAG) const {
7570 SDNode *N = Op.getNode();
7572 assert(N->getOperand(0).getValueType() == MVT::v4i1 &&
7573 "Unknown extract_vector_elt type");
7575 SDValue Value = N->getOperand(0);
7577 // The first part of this is like the store lowering except that we don't
7578 // need to track the chain.
7580 // The values are now known to be -1 (false) or 1 (true). To convert this
7581 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
7582 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
7583 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
7585 // FIXME: We can make this an f32 vector, but the BUILD_VECTOR code needs to
7586 // understand how to form the extending load.
7587 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::f64);
7588 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
7589 FPHalfs, FPHalfs, FPHalfs, FPHalfs);
7591 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
7593 // Now convert to an integer and store.
7594 Value = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
7595 DAG.getConstant(Intrinsic::ppc_qpx_qvfctiwu, dl, MVT::i32),
7598 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
7599 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
7600 MachinePointerInfo PtrInfo =
7601 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
7602 EVT PtrVT = getPointerTy(DAG.getDataLayout());
7603 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
7605 SDValue StoreChain = DAG.getEntryNode();
7606 SmallVector<SDValue, 2> Ops;
7607 Ops.push_back(StoreChain);
7608 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvstfiw, dl, MVT::i32));
7609 Ops.push_back(Value);
7610 Ops.push_back(FIdx);
7612 SmallVector<EVT, 2> ValueVTs;
7613 ValueVTs.push_back(MVT::Other); // chain
7614 SDVTList VTs = DAG.getVTList(ValueVTs);
7616 StoreChain = DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID,
7617 dl, VTs, Ops, MVT::v4i32, PtrInfo);
7619 // Extract the value requested.
7620 unsigned Offset = 4*cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
7621 SDValue Idx = DAG.getConstant(Offset, dl, FIdx.getValueType());
7622 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
7624 SDValue IntVal = DAG.getLoad(MVT::i32, dl, StoreChain, Idx,
7625 PtrInfo.getWithOffset(Offset),
7626 false, false, false, 0);
7628 if (!Subtarget.useCRBits())
7631 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, IntVal);
7634 /// Lowering for QPX v4i1 loads
7635 SDValue PPCTargetLowering::LowerVectorLoad(SDValue Op,
7636 SelectionDAG &DAG) const {
7638 LoadSDNode *LN = cast<LoadSDNode>(Op.getNode());
7639 SDValue LoadChain = LN->getChain();
7640 SDValue BasePtr = LN->getBasePtr();
7642 if (Op.getValueType() == MVT::v4f64 ||
7643 Op.getValueType() == MVT::v4f32) {
7644 EVT MemVT = LN->getMemoryVT();
7645 unsigned Alignment = LN->getAlignment();
7647 // If this load is properly aligned, then it is legal.
7648 if (Alignment >= MemVT.getStoreSize())
7651 EVT ScalarVT = Op.getValueType().getScalarType(),
7652 ScalarMemVT = MemVT.getScalarType();
7653 unsigned Stride = ScalarMemVT.getStoreSize();
7655 SmallVector<SDValue, 8> Vals, LoadChains;
7656 for (unsigned Idx = 0; Idx < 4; ++Idx) {
7658 if (ScalarVT != ScalarMemVT)
7660 DAG.getExtLoad(LN->getExtensionType(), dl, ScalarVT, LoadChain,
7662 LN->getPointerInfo().getWithOffset(Idx*Stride),
7663 ScalarMemVT, LN->isVolatile(), LN->isNonTemporal(),
7664 LN->isInvariant(), MinAlign(Alignment, Idx*Stride),
7668 DAG.getLoad(ScalarVT, dl, LoadChain, BasePtr,
7669 LN->getPointerInfo().getWithOffset(Idx*Stride),
7670 LN->isVolatile(), LN->isNonTemporal(),
7671 LN->isInvariant(), MinAlign(Alignment, Idx*Stride),
7674 if (Idx == 0 && LN->isIndexed()) {
7675 assert(LN->getAddressingMode() == ISD::PRE_INC &&
7676 "Unknown addressing mode on vector load");
7677 Load = DAG.getIndexedLoad(Load, dl, BasePtr, LN->getOffset(),
7678 LN->getAddressingMode());
7681 Vals.push_back(Load);
7682 LoadChains.push_back(Load.getValue(1));
7684 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
7685 DAG.getConstant(Stride, dl,
7686 BasePtr.getValueType()));
7689 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
7690 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl,
7691 Op.getValueType(), Vals);
7693 if (LN->isIndexed()) {
7694 SDValue RetOps[] = { Value, Vals[0].getValue(1), TF };
7695 return DAG.getMergeValues(RetOps, dl);
7698 SDValue RetOps[] = { Value, TF };
7699 return DAG.getMergeValues(RetOps, dl);
7702 assert(Op.getValueType() == MVT::v4i1 && "Unknown load to lower");
7703 assert(LN->isUnindexed() && "Indexed v4i1 loads are not supported");
7705 // To lower v4i1 from a byte array, we load the byte elements of the
7706 // vector and then reuse the BUILD_VECTOR logic.
7708 SmallVector<SDValue, 4> VectElmts, VectElmtChains;
7709 for (unsigned i = 0; i < 4; ++i) {
7710 SDValue Idx = DAG.getConstant(i, dl, BasePtr.getValueType());
7711 Idx = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, Idx);
7713 VectElmts.push_back(DAG.getExtLoad(ISD::EXTLOAD,
7714 dl, MVT::i32, LoadChain, Idx,
7715 LN->getPointerInfo().getWithOffset(i),
7716 MVT::i8 /* memory type */,
7717 LN->isVolatile(), LN->isNonTemporal(),
7719 1 /* alignment */, LN->getAAInfo()));
7720 VectElmtChains.push_back(VectElmts[i].getValue(1));
7723 LoadChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, VectElmtChains);
7724 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i1, VectElmts);
7726 SDValue RVals[] = { Value, LoadChain };
7727 return DAG.getMergeValues(RVals, dl);
7730 /// Lowering for QPX v4i1 stores
7731 SDValue PPCTargetLowering::LowerVectorStore(SDValue Op,
7732 SelectionDAG &DAG) const {
7734 StoreSDNode *SN = cast<StoreSDNode>(Op.getNode());
7735 SDValue StoreChain = SN->getChain();
7736 SDValue BasePtr = SN->getBasePtr();
7737 SDValue Value = SN->getValue();
7739 if (Value.getValueType() == MVT::v4f64 ||
7740 Value.getValueType() == MVT::v4f32) {
7741 EVT MemVT = SN->getMemoryVT();
7742 unsigned Alignment = SN->getAlignment();
7744 // If this store is properly aligned, then it is legal.
7745 if (Alignment >= MemVT.getStoreSize())
7748 EVT ScalarVT = Value.getValueType().getScalarType(),
7749 ScalarMemVT = MemVT.getScalarType();
7750 unsigned Stride = ScalarMemVT.getStoreSize();
7752 SmallVector<SDValue, 8> Stores;
7753 for (unsigned Idx = 0; Idx < 4; ++Idx) {
7754 SDValue Ex = DAG.getNode(
7755 ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, Value,
7756 DAG.getConstant(Idx, dl, getVectorIdxTy(DAG.getDataLayout())));
7758 if (ScalarVT != ScalarMemVT)
7760 DAG.getTruncStore(StoreChain, dl, Ex, BasePtr,
7761 SN->getPointerInfo().getWithOffset(Idx*Stride),
7762 ScalarMemVT, SN->isVolatile(), SN->isNonTemporal(),
7763 MinAlign(Alignment, Idx*Stride), SN->getAAInfo());
7766 DAG.getStore(StoreChain, dl, Ex, BasePtr,
7767 SN->getPointerInfo().getWithOffset(Idx*Stride),
7768 SN->isVolatile(), SN->isNonTemporal(),
7769 MinAlign(Alignment, Idx*Stride), SN->getAAInfo());
7771 if (Idx == 0 && SN->isIndexed()) {
7772 assert(SN->getAddressingMode() == ISD::PRE_INC &&
7773 "Unknown addressing mode on vector store");
7774 Store = DAG.getIndexedStore(Store, dl, BasePtr, SN->getOffset(),
7775 SN->getAddressingMode());
7778 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
7779 DAG.getConstant(Stride, dl,
7780 BasePtr.getValueType()));
7781 Stores.push_back(Store);
7784 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
7786 if (SN->isIndexed()) {
7787 SDValue RetOps[] = { TF, Stores[0].getValue(1) };
7788 return DAG.getMergeValues(RetOps, dl);
7794 assert(SN->isUnindexed() && "Indexed v4i1 stores are not supported");
7795 assert(Value.getValueType() == MVT::v4i1 && "Unknown store to lower");
7797 // The values are now known to be -1 (false) or 1 (true). To convert this
7798 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
7799 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
7800 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
7802 // FIXME: We can make this an f32 vector, but the BUILD_VECTOR code needs to
7803 // understand how to form the extending load.
7804 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::f64);
7805 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
7806 FPHalfs, FPHalfs, FPHalfs, FPHalfs);
7808 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
7810 // Now convert to an integer and store.
7811 Value = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
7812 DAG.getConstant(Intrinsic::ppc_qpx_qvfctiwu, dl, MVT::i32),
7815 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
7816 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
7817 MachinePointerInfo PtrInfo =
7818 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
7819 EVT PtrVT = getPointerTy(DAG.getDataLayout());
7820 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
7822 SmallVector<SDValue, 2> Ops;
7823 Ops.push_back(StoreChain);
7824 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvstfiw, dl, MVT::i32));
7825 Ops.push_back(Value);
7826 Ops.push_back(FIdx);
7828 SmallVector<EVT, 2> ValueVTs;
7829 ValueVTs.push_back(MVT::Other); // chain
7830 SDVTList VTs = DAG.getVTList(ValueVTs);
7832 StoreChain = DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID,
7833 dl, VTs, Ops, MVT::v4i32, PtrInfo);
7835 // Move data into the byte array.
7836 SmallVector<SDValue, 4> Loads, LoadChains;
7837 for (unsigned i = 0; i < 4; ++i) {
7838 unsigned Offset = 4*i;
7839 SDValue Idx = DAG.getConstant(Offset, dl, FIdx.getValueType());
7840 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
7842 Loads.push_back(DAG.getLoad(MVT::i32, dl, StoreChain, Idx,
7843 PtrInfo.getWithOffset(Offset),
7844 false, false, false, 0));
7845 LoadChains.push_back(Loads[i].getValue(1));
7848 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
7850 SmallVector<SDValue, 4> Stores;
7851 for (unsigned i = 0; i < 4; ++i) {
7852 SDValue Idx = DAG.getConstant(i, dl, BasePtr.getValueType());
7853 Idx = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, Idx);
7855 Stores.push_back(DAG.getTruncStore(
7856 StoreChain, dl, Loads[i], Idx, SN->getPointerInfo().getWithOffset(i),
7857 MVT::i8 /* memory type */, SN->isNonTemporal(), SN->isVolatile(),
7858 1 /* alignment */, SN->getAAInfo()));
7861 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
7866 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
7868 if (Op.getValueType() == MVT::v4i32) {
7869 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
7871 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
7872 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
7874 SDValue RHSSwap = // = vrlw RHS, 16
7875 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
7877 // Shrinkify inputs to v8i16.
7878 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
7879 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
7880 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
7882 // Low parts multiplied together, generating 32-bit results (we ignore the
7884 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
7885 LHS, RHS, DAG, dl, MVT::v4i32);
7887 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
7888 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
7889 // Shift the high parts up 16 bits.
7890 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
7892 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
7893 } else if (Op.getValueType() == MVT::v8i16) {
7894 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
7896 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
7898 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
7899 LHS, RHS, Zero, DAG, dl);
7900 } else if (Op.getValueType() == MVT::v16i8) {
7901 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
7902 bool isLittleEndian = Subtarget.isLittleEndian();
7904 // Multiply the even 8-bit parts, producing 16-bit sums.
7905 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
7906 LHS, RHS, DAG, dl, MVT::v8i16);
7907 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
7909 // Multiply the odd 8-bit parts, producing 16-bit sums.
7910 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
7911 LHS, RHS, DAG, dl, MVT::v8i16);
7912 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
7914 // Merge the results together. Because vmuleub and vmuloub are
7915 // instructions with a big-endian bias, we must reverse the
7916 // element numbering and reverse the meaning of "odd" and "even"
7917 // when generating little endian code.
7919 for (unsigned i = 0; i != 8; ++i) {
7920 if (isLittleEndian) {
7922 Ops[i*2+1] = 2*i+16;
7925 Ops[i*2+1] = 2*i+1+16;
7929 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
7931 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
7933 llvm_unreachable("Unknown mul to lower!");
7937 /// LowerOperation - Provide custom lowering hooks for some operations.
7939 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7940 switch (Op.getOpcode()) {
7941 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
7942 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
7943 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
7944 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
7945 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
7946 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
7947 case ISD::SETCC: return LowerSETCC(Op, DAG);
7948 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
7949 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
7951 return LowerVASTART(Op, DAG, Subtarget);
7954 return LowerVAARG(Op, DAG, Subtarget);
7957 return LowerVACOPY(Op, DAG, Subtarget);
7959 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget);
7960 case ISD::DYNAMIC_STACKALLOC:
7961 return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget);
7962 case ISD::GET_DYNAMIC_AREA_OFFSET: return LowerGET_DYNAMIC_AREA_OFFSET(Op, DAG, Subtarget);
7964 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
7965 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
7967 case ISD::LOAD: return LowerLOAD(Op, DAG);
7968 case ISD::STORE: return LowerSTORE(Op, DAG);
7969 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
7970 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
7971 case ISD::FP_TO_UINT:
7972 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
7974 case ISD::UINT_TO_FP:
7975 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
7976 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
7978 // Lower 64-bit shifts.
7979 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
7980 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
7981 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
7983 // Vector-related lowering.
7984 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
7985 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
7986 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
7987 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
7988 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
7989 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
7990 case ISD::MUL: return LowerMUL(Op, DAG);
7992 // For counter-based loop handling.
7993 case ISD::INTRINSIC_W_CHAIN: return SDValue();
7995 // Frame & Return address.
7996 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
7997 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
8001 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
8002 SmallVectorImpl<SDValue>&Results,
8003 SelectionDAG &DAG) const {
8005 switch (N->getOpcode()) {
8007 llvm_unreachable("Do not know how to custom type legalize this operation!");
8008 case ISD::READCYCLECOUNTER: {
8009 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
8010 SDValue RTB = DAG.getNode(PPCISD::READ_TIME_BASE, dl, VTs, N->getOperand(0));
8012 Results.push_back(RTB);
8013 Results.push_back(RTB.getValue(1));
8014 Results.push_back(RTB.getValue(2));
8017 case ISD::INTRINSIC_W_CHAIN: {
8018 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
8019 Intrinsic::ppc_is_decremented_ctr_nonzero)
8022 assert(N->getValueType(0) == MVT::i1 &&
8023 "Unexpected result type for CTR decrement intrinsic");
8024 EVT SVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
8025 N->getValueType(0));
8026 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
8027 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
8030 Results.push_back(NewInt);
8031 Results.push_back(NewInt.getValue(1));
8035 if (!Subtarget.isSVR4ABI() || Subtarget.isPPC64())
8038 EVT VT = N->getValueType(0);
8040 if (VT == MVT::i64) {
8041 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget);
8043 Results.push_back(NewNode);
8044 Results.push_back(NewNode.getValue(1));
8048 case ISD::FP_ROUND_INREG: {
8049 assert(N->getValueType(0) == MVT::ppcf128);
8050 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
8051 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
8052 MVT::f64, N->getOperand(0),
8053 DAG.getIntPtrConstant(0, dl));
8054 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
8055 MVT::f64, N->getOperand(0),
8056 DAG.getIntPtrConstant(1, dl));
8058 // Add the two halves of the long double in round-to-zero mode.
8059 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
8061 // We know the low half is about to be thrown away, so just use something
8063 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
8067 case ISD::FP_TO_SINT:
8068 case ISD::FP_TO_UINT:
8069 // LowerFP_TO_INT() can only handle f32 and f64.
8070 if (N->getOperand(0).getValueType() == MVT::ppcf128)
8072 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
8077 //===----------------------------------------------------------------------===//
8078 // Other Lowering Code
8079 //===----------------------------------------------------------------------===//
8081 static Instruction* callIntrinsic(IRBuilder<> &Builder, Intrinsic::ID Id) {
8082 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
8083 Function *Func = Intrinsic::getDeclaration(M, Id);
8084 return Builder.CreateCall(Func, {});
8087 // The mappings for emitLeading/TrailingFence is taken from
8088 // http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
8089 Instruction* PPCTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
8090 AtomicOrdering Ord, bool IsStore,
8091 bool IsLoad) const {
8092 if (Ord == SequentiallyConsistent)
8093 return callIntrinsic(Builder, Intrinsic::ppc_sync);
8094 if (isAtLeastRelease(Ord))
8095 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
8099 Instruction* PPCTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
8100 AtomicOrdering Ord, bool IsStore,
8101 bool IsLoad) const {
8102 if (IsLoad && isAtLeastAcquire(Ord))
8103 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
8104 // FIXME: this is too conservative, a dependent branch + isync is enough.
8105 // See http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html and
8106 // http://www.rdrop.com/users/paulmck/scalability/paper/N2745r.2011.03.04a.html
8107 // and http://www.cl.cam.ac.uk/~pes20/cppppc/ for justification.
8112 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
8113 unsigned AtomicSize,
8114 unsigned BinOpcode) const {
8115 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
8116 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8118 auto LoadMnemonic = PPC::LDARX;
8119 auto StoreMnemonic = PPC::STDCX;
8120 switch (AtomicSize) {
8122 llvm_unreachable("Unexpected size of atomic entity");
8124 LoadMnemonic = PPC::LBARX;
8125 StoreMnemonic = PPC::STBCX;
8126 assert(Subtarget.hasPartwordAtomics() && "Call this only with size >=4");
8129 LoadMnemonic = PPC::LHARX;
8130 StoreMnemonic = PPC::STHCX;
8131 assert(Subtarget.hasPartwordAtomics() && "Call this only with size >=4");
8134 LoadMnemonic = PPC::LWARX;
8135 StoreMnemonic = PPC::STWCX;
8138 LoadMnemonic = PPC::LDARX;
8139 StoreMnemonic = PPC::STDCX;
8143 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8144 MachineFunction *F = BB->getParent();
8145 MachineFunction::iterator It = ++BB->getIterator();
8147 unsigned dest = MI->getOperand(0).getReg();
8148 unsigned ptrA = MI->getOperand(1).getReg();
8149 unsigned ptrB = MI->getOperand(2).getReg();
8150 unsigned incr = MI->getOperand(3).getReg();
8151 DebugLoc dl = MI->getDebugLoc();
8153 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
8154 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8155 F->insert(It, loopMBB);
8156 F->insert(It, exitMBB);
8157 exitMBB->splice(exitMBB->begin(), BB,
8158 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8159 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8161 MachineRegisterInfo &RegInfo = F->getRegInfo();
8162 unsigned TmpReg = (!BinOpcode) ? incr :
8163 RegInfo.createVirtualRegister( AtomicSize == 8 ? &PPC::G8RCRegClass
8164 : &PPC::GPRCRegClass);
8168 // fallthrough --> loopMBB
8169 BB->addSuccessor(loopMBB);
8172 // l[wd]arx dest, ptr
8173 // add r0, dest, incr
8174 // st[wd]cx. r0, ptr
8176 // fallthrough --> exitMBB
8178 BuildMI(BB, dl, TII->get(LoadMnemonic), dest)
8179 .addReg(ptrA).addReg(ptrB);
8181 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
8182 BuildMI(BB, dl, TII->get(StoreMnemonic))
8183 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
8184 BuildMI(BB, dl, TII->get(PPC::BCC))
8185 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
8186 BB->addSuccessor(loopMBB);
8187 BB->addSuccessor(exitMBB);
8196 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
8197 MachineBasicBlock *BB,
8198 bool is8bit, // operation
8199 unsigned BinOpcode) const {
8200 // If we support part-word atomic mnemonics, just use them
8201 if (Subtarget.hasPartwordAtomics())
8202 return EmitAtomicBinary(MI, BB, is8bit ? 1 : 2, BinOpcode);
8204 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
8205 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8206 // In 64 bit mode we have to use 64 bits for addresses, even though the
8207 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
8208 // registers without caring whether they're 32 or 64, but here we're
8209 // doing actual arithmetic on the addresses.
8210 bool is64bit = Subtarget.isPPC64();
8211 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
8213 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8214 MachineFunction *F = BB->getParent();
8215 MachineFunction::iterator It = ++BB->getIterator();
8217 unsigned dest = MI->getOperand(0).getReg();
8218 unsigned ptrA = MI->getOperand(1).getReg();
8219 unsigned ptrB = MI->getOperand(2).getReg();
8220 unsigned incr = MI->getOperand(3).getReg();
8221 DebugLoc dl = MI->getDebugLoc();
8223 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
8224 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8225 F->insert(It, loopMBB);
8226 F->insert(It, exitMBB);
8227 exitMBB->splice(exitMBB->begin(), BB,
8228 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8229 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8231 MachineRegisterInfo &RegInfo = F->getRegInfo();
8232 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
8233 : &PPC::GPRCRegClass;
8234 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
8235 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
8236 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
8237 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
8238 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
8239 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
8240 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
8241 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
8242 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
8243 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
8244 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
8246 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
8250 // fallthrough --> loopMBB
8251 BB->addSuccessor(loopMBB);
8253 // The 4-byte load must be aligned, while a char or short may be
8254 // anywhere in the word. Hence all this nasty bookkeeping code.
8255 // add ptr1, ptrA, ptrB [copy if ptrA==0]
8256 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
8257 // xori shift, shift1, 24 [16]
8258 // rlwinm ptr, ptr1, 0, 0, 29
8259 // slw incr2, incr, shift
8260 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
8261 // slw mask, mask2, shift
8263 // lwarx tmpDest, ptr
8264 // add tmp, tmpDest, incr2
8265 // andc tmp2, tmpDest, mask
8266 // and tmp3, tmp, mask
8267 // or tmp4, tmp3, tmp2
8270 // fallthrough --> exitMBB
8271 // srw dest, tmpDest, shift
8272 if (ptrA != ZeroReg) {
8273 Ptr1Reg = RegInfo.createVirtualRegister(RC);
8274 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
8275 .addReg(ptrA).addReg(ptrB);
8279 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
8280 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
8281 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
8282 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
8284 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
8285 .addReg(Ptr1Reg).addImm(0).addImm(61);
8287 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
8288 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
8289 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
8290 .addReg(incr).addReg(ShiftReg);
8292 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
8294 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
8295 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
8297 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
8298 .addReg(Mask2Reg).addReg(ShiftReg);
8301 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
8302 .addReg(ZeroReg).addReg(PtrReg);
8304 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
8305 .addReg(Incr2Reg).addReg(TmpDestReg);
8306 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
8307 .addReg(TmpDestReg).addReg(MaskReg);
8308 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
8309 .addReg(TmpReg).addReg(MaskReg);
8310 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
8311 .addReg(Tmp3Reg).addReg(Tmp2Reg);
8312 BuildMI(BB, dl, TII->get(PPC::STWCX))
8313 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
8314 BuildMI(BB, dl, TII->get(PPC::BCC))
8315 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
8316 BB->addSuccessor(loopMBB);
8317 BB->addSuccessor(exitMBB);
8322 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
8327 llvm::MachineBasicBlock*
8328 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
8329 MachineBasicBlock *MBB) const {
8330 DebugLoc DL = MI->getDebugLoc();
8331 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8333 MachineFunction *MF = MBB->getParent();
8334 MachineRegisterInfo &MRI = MF->getRegInfo();
8336 const BasicBlock *BB = MBB->getBasicBlock();
8337 MachineFunction::iterator I = ++MBB->getIterator();
8340 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
8341 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
8343 unsigned DstReg = MI->getOperand(0).getReg();
8344 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
8345 assert(RC->hasType(MVT::i32) && "Invalid destination!");
8346 unsigned mainDstReg = MRI.createVirtualRegister(RC);
8347 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
8349 MVT PVT = getPointerTy(MF->getDataLayout());
8350 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
8351 "Invalid Pointer Size!");
8352 // For v = setjmp(buf), we generate
8355 // SjLjSetup mainMBB
8361 // buf[LabelOffset] = LR
8365 // v = phi(main, restore)
8368 MachineBasicBlock *thisMBB = MBB;
8369 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
8370 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
8371 MF->insert(I, mainMBB);
8372 MF->insert(I, sinkMBB);
8374 MachineInstrBuilder MIB;
8376 // Transfer the remainder of BB and its successor edges to sinkMBB.
8377 sinkMBB->splice(sinkMBB->begin(), MBB,
8378 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
8379 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
8381 // Note that the structure of the jmp_buf used here is not compatible
8382 // with that used by libc, and is not designed to be. Specifically, it
8383 // stores only those 'reserved' registers that LLVM does not otherwise
8384 // understand how to spill. Also, by convention, by the time this
8385 // intrinsic is called, Clang has already stored the frame address in the
8386 // first slot of the buffer and stack address in the third. Following the
8387 // X86 target code, we'll store the jump address in the second slot. We also
8388 // need to save the TOC pointer (R2) to handle jumps between shared
8389 // libraries, and that will be stored in the fourth slot. The thread
8390 // identifier (R13) is not affected.
8393 const int64_t LabelOffset = 1 * PVT.getStoreSize();
8394 const int64_t TOCOffset = 3 * PVT.getStoreSize();
8395 const int64_t BPOffset = 4 * PVT.getStoreSize();
8397 // Prepare IP either in reg.
8398 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
8399 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
8400 unsigned BufReg = MI->getOperand(1).getReg();
8402 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
8403 setUsesTOCBasePtr(*MBB->getParent());
8404 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
8408 MIB.setMemRefs(MMOBegin, MMOEnd);
8411 // Naked functions never have a base pointer, and so we use r1. For all
8412 // other functions, this decision must be delayed until during PEI.
8414 if (MF->getFunction()->hasFnAttribute(Attribute::Naked))
8415 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
8417 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
8419 MIB = BuildMI(*thisMBB, MI, DL,
8420 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
8424 MIB.setMemRefs(MMOBegin, MMOEnd);
8427 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
8428 const PPCRegisterInfo *TRI = Subtarget.getRegisterInfo();
8429 MIB.addRegMask(TRI->getNoPreservedMask());
8431 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
8433 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
8435 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
8437 thisMBB->addSuccessor(mainMBB, BranchProbability::getZero());
8438 thisMBB->addSuccessor(sinkMBB, BranchProbability::getOne());
8443 BuildMI(mainMBB, DL,
8444 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
8447 if (Subtarget.isPPC64()) {
8448 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
8450 .addImm(LabelOffset)
8453 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
8455 .addImm(LabelOffset)
8459 MIB.setMemRefs(MMOBegin, MMOEnd);
8461 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
8462 mainMBB->addSuccessor(sinkMBB);
8465 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
8466 TII->get(PPC::PHI), DstReg)
8467 .addReg(mainDstReg).addMBB(mainMBB)
8468 .addReg(restoreDstReg).addMBB(thisMBB);
8470 MI->eraseFromParent();
8475 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
8476 MachineBasicBlock *MBB) const {
8477 DebugLoc DL = MI->getDebugLoc();
8478 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8480 MachineFunction *MF = MBB->getParent();
8481 MachineRegisterInfo &MRI = MF->getRegInfo();
8484 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
8485 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
8487 MVT PVT = getPointerTy(MF->getDataLayout());
8488 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
8489 "Invalid Pointer Size!");
8491 const TargetRegisterClass *RC =
8492 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
8493 unsigned Tmp = MRI.createVirtualRegister(RC);
8494 // Since FP is only updated here but NOT referenced, it's treated as GPR.
8495 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
8496 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
8500 : (Subtarget.isSVR4ABI() &&
8501 MF->getTarget().getRelocationModel() == Reloc::PIC_
8505 MachineInstrBuilder MIB;
8507 const int64_t LabelOffset = 1 * PVT.getStoreSize();
8508 const int64_t SPOffset = 2 * PVT.getStoreSize();
8509 const int64_t TOCOffset = 3 * PVT.getStoreSize();
8510 const int64_t BPOffset = 4 * PVT.getStoreSize();
8512 unsigned BufReg = MI->getOperand(0).getReg();
8514 // Reload FP (the jumped-to function may not have had a
8515 // frame pointer, and if so, then its r31 will be restored
8517 if (PVT == MVT::i64) {
8518 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
8522 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
8526 MIB.setMemRefs(MMOBegin, MMOEnd);
8529 if (PVT == MVT::i64) {
8530 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
8531 .addImm(LabelOffset)
8534 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
8535 .addImm(LabelOffset)
8538 MIB.setMemRefs(MMOBegin, MMOEnd);
8541 if (PVT == MVT::i64) {
8542 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
8546 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
8550 MIB.setMemRefs(MMOBegin, MMOEnd);
8553 if (PVT == MVT::i64) {
8554 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
8558 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
8562 MIB.setMemRefs(MMOBegin, MMOEnd);
8565 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
8566 setUsesTOCBasePtr(*MBB->getParent());
8567 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
8571 MIB.setMemRefs(MMOBegin, MMOEnd);
8575 BuildMI(*MBB, MI, DL,
8576 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
8577 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
8579 MI->eraseFromParent();
8584 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
8585 MachineBasicBlock *BB) const {
8586 if (MI->getOpcode() == TargetOpcode::STACKMAP ||
8587 MI->getOpcode() == TargetOpcode::PATCHPOINT) {
8588 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI() &&
8589 MI->getOpcode() == TargetOpcode::PATCHPOINT) {
8590 // Call lowering should have added an r2 operand to indicate a dependence
8591 // on the TOC base pointer value. It can't however, because there is no
8592 // way to mark the dependence as implicit there, and so the stackmap code
8593 // will confuse it with a regular operand. Instead, add the dependence
8595 setUsesTOCBasePtr(*BB->getParent());
8596 MI->addOperand(MachineOperand::CreateReg(PPC::X2, false, true));
8599 return emitPatchPoint(MI, BB);
8602 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
8603 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
8604 return emitEHSjLjSetJmp(MI, BB);
8605 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
8606 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
8607 return emitEHSjLjLongJmp(MI, BB);
8610 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8612 // To "insert" these instructions we actually have to insert their
8613 // control-flow patterns.
8614 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8615 MachineFunction::iterator It = ++BB->getIterator();
8617 MachineFunction *F = BB->getParent();
8619 if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
8620 MI->getOpcode() == PPC::SELECT_CC_I8 ||
8621 MI->getOpcode() == PPC::SELECT_I4 ||
8622 MI->getOpcode() == PPC::SELECT_I8)) {
8623 SmallVector<MachineOperand, 2> Cond;
8624 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
8625 MI->getOpcode() == PPC::SELECT_CC_I8)
8626 Cond.push_back(MI->getOperand(4));
8628 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
8629 Cond.push_back(MI->getOperand(1));
8631 DebugLoc dl = MI->getDebugLoc();
8632 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
8633 Cond, MI->getOperand(2).getReg(),
8634 MI->getOperand(3).getReg());
8635 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
8636 MI->getOpcode() == PPC::SELECT_CC_I8 ||
8637 MI->getOpcode() == PPC::SELECT_CC_F4 ||
8638 MI->getOpcode() == PPC::SELECT_CC_F8 ||
8639 MI->getOpcode() == PPC::SELECT_CC_QFRC ||
8640 MI->getOpcode() == PPC::SELECT_CC_QSRC ||
8641 MI->getOpcode() == PPC::SELECT_CC_QBRC ||
8642 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
8643 MI->getOpcode() == PPC::SELECT_CC_VSFRC ||
8644 MI->getOpcode() == PPC::SELECT_CC_VSSRC ||
8645 MI->getOpcode() == PPC::SELECT_CC_VSRC ||
8646 MI->getOpcode() == PPC::SELECT_I4 ||
8647 MI->getOpcode() == PPC::SELECT_I8 ||
8648 MI->getOpcode() == PPC::SELECT_F4 ||
8649 MI->getOpcode() == PPC::SELECT_F8 ||
8650 MI->getOpcode() == PPC::SELECT_QFRC ||
8651 MI->getOpcode() == PPC::SELECT_QSRC ||
8652 MI->getOpcode() == PPC::SELECT_QBRC ||
8653 MI->getOpcode() == PPC::SELECT_VRRC ||
8654 MI->getOpcode() == PPC::SELECT_VSFRC ||
8655 MI->getOpcode() == PPC::SELECT_VSSRC ||
8656 MI->getOpcode() == PPC::SELECT_VSRC) {
8657 // The incoming instruction knows the destination vreg to set, the
8658 // condition code register to branch on, the true/false values to
8659 // select between, and a branch opcode to use.
8664 // cmpTY ccX, r1, r2
8666 // fallthrough --> copy0MBB
8667 MachineBasicBlock *thisMBB = BB;
8668 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
8669 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8670 DebugLoc dl = MI->getDebugLoc();
8671 F->insert(It, copy0MBB);
8672 F->insert(It, sinkMBB);
8674 // Transfer the remainder of BB and its successor edges to sinkMBB.
8675 sinkMBB->splice(sinkMBB->begin(), BB,
8676 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8677 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
8679 // Next, add the true and fallthrough blocks as its successors.
8680 BB->addSuccessor(copy0MBB);
8681 BB->addSuccessor(sinkMBB);
8683 if (MI->getOpcode() == PPC::SELECT_I4 ||
8684 MI->getOpcode() == PPC::SELECT_I8 ||
8685 MI->getOpcode() == PPC::SELECT_F4 ||
8686 MI->getOpcode() == PPC::SELECT_F8 ||
8687 MI->getOpcode() == PPC::SELECT_QFRC ||
8688 MI->getOpcode() == PPC::SELECT_QSRC ||
8689 MI->getOpcode() == PPC::SELECT_QBRC ||
8690 MI->getOpcode() == PPC::SELECT_VRRC ||
8691 MI->getOpcode() == PPC::SELECT_VSFRC ||
8692 MI->getOpcode() == PPC::SELECT_VSSRC ||
8693 MI->getOpcode() == PPC::SELECT_VSRC) {
8694 BuildMI(BB, dl, TII->get(PPC::BC))
8695 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
8697 unsigned SelectPred = MI->getOperand(4).getImm();
8698 BuildMI(BB, dl, TII->get(PPC::BCC))
8699 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
8703 // %FalseValue = ...
8704 // # fallthrough to sinkMBB
8707 // Update machine-CFG edges
8708 BB->addSuccessor(sinkMBB);
8711 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
8714 BuildMI(*BB, BB->begin(), dl,
8715 TII->get(PPC::PHI), MI->getOperand(0).getReg())
8716 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
8717 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
8718 } else if (MI->getOpcode() == PPC::ReadTB) {
8719 // To read the 64-bit time-base register on a 32-bit target, we read the
8720 // two halves. Should the counter have wrapped while it was being read, we
8721 // need to try again.
8724 // mfspr Rx,TBU # load from TBU
8725 // mfspr Ry,TB # load from TB
8726 // mfspr Rz,TBU # load from TBU
8727 // cmpw crX,Rx,Rz # check if 'old'='new'
8728 // bne readLoop # branch if they're not equal
8731 MachineBasicBlock *readMBB = F->CreateMachineBasicBlock(LLVM_BB);
8732 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8733 DebugLoc dl = MI->getDebugLoc();
8734 F->insert(It, readMBB);
8735 F->insert(It, sinkMBB);
8737 // Transfer the remainder of BB and its successor edges to sinkMBB.
8738 sinkMBB->splice(sinkMBB->begin(), BB,
8739 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8740 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
8742 BB->addSuccessor(readMBB);
8745 MachineRegisterInfo &RegInfo = F->getRegInfo();
8746 unsigned ReadAgainReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
8747 unsigned LoReg = MI->getOperand(0).getReg();
8748 unsigned HiReg = MI->getOperand(1).getReg();
8750 BuildMI(BB, dl, TII->get(PPC::MFSPR), HiReg).addImm(269);
8751 BuildMI(BB, dl, TII->get(PPC::MFSPR), LoReg).addImm(268);
8752 BuildMI(BB, dl, TII->get(PPC::MFSPR), ReadAgainReg).addImm(269);
8754 unsigned CmpReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
8756 BuildMI(BB, dl, TII->get(PPC::CMPW), CmpReg)
8757 .addReg(HiReg).addReg(ReadAgainReg);
8758 BuildMI(BB, dl, TII->get(PPC::BCC))
8759 .addImm(PPC::PRED_NE).addReg(CmpReg).addMBB(readMBB);
8761 BB->addSuccessor(readMBB);
8762 BB->addSuccessor(sinkMBB);
8764 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
8765 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
8766 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
8767 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
8768 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
8769 BB = EmitAtomicBinary(MI, BB, 4, PPC::ADD4);
8770 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
8771 BB = EmitAtomicBinary(MI, BB, 8, PPC::ADD8);
8773 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
8774 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
8775 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
8776 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
8777 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
8778 BB = EmitAtomicBinary(MI, BB, 4, PPC::AND);
8779 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
8780 BB = EmitAtomicBinary(MI, BB, 8, PPC::AND8);
8782 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
8783 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
8784 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
8785 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
8786 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
8787 BB = EmitAtomicBinary(MI, BB, 4, PPC::OR);
8788 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
8789 BB = EmitAtomicBinary(MI, BB, 8, PPC::OR8);
8791 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
8792 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
8793 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
8794 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
8795 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
8796 BB = EmitAtomicBinary(MI, BB, 4, PPC::XOR);
8797 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
8798 BB = EmitAtomicBinary(MI, BB, 8, PPC::XOR8);
8800 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
8801 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND);
8802 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
8803 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND);
8804 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
8805 BB = EmitAtomicBinary(MI, BB, 4, PPC::NAND);
8806 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
8807 BB = EmitAtomicBinary(MI, BB, 8, PPC::NAND8);
8809 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
8810 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
8811 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
8812 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
8813 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
8814 BB = EmitAtomicBinary(MI, BB, 4, PPC::SUBF);
8815 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
8816 BB = EmitAtomicBinary(MI, BB, 8, PPC::SUBF8);
8818 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
8819 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
8820 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
8821 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
8822 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
8823 BB = EmitAtomicBinary(MI, BB, 4, 0);
8824 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
8825 BB = EmitAtomicBinary(MI, BB, 8, 0);
8827 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
8828 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64 ||
8829 (Subtarget.hasPartwordAtomics() &&
8830 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8) ||
8831 (Subtarget.hasPartwordAtomics() &&
8832 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16)) {
8833 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
8835 auto LoadMnemonic = PPC::LDARX;
8836 auto StoreMnemonic = PPC::STDCX;
8837 switch(MI->getOpcode()) {
8839 llvm_unreachable("Compare and swap of unknown size");
8840 case PPC::ATOMIC_CMP_SWAP_I8:
8841 LoadMnemonic = PPC::LBARX;
8842 StoreMnemonic = PPC::STBCX;
8843 assert(Subtarget.hasPartwordAtomics() && "No support partword atomics.");
8845 case PPC::ATOMIC_CMP_SWAP_I16:
8846 LoadMnemonic = PPC::LHARX;
8847 StoreMnemonic = PPC::STHCX;
8848 assert(Subtarget.hasPartwordAtomics() && "No support partword atomics.");
8850 case PPC::ATOMIC_CMP_SWAP_I32:
8851 LoadMnemonic = PPC::LWARX;
8852 StoreMnemonic = PPC::STWCX;
8854 case PPC::ATOMIC_CMP_SWAP_I64:
8855 LoadMnemonic = PPC::LDARX;
8856 StoreMnemonic = PPC::STDCX;
8859 unsigned dest = MI->getOperand(0).getReg();
8860 unsigned ptrA = MI->getOperand(1).getReg();
8861 unsigned ptrB = MI->getOperand(2).getReg();
8862 unsigned oldval = MI->getOperand(3).getReg();
8863 unsigned newval = MI->getOperand(4).getReg();
8864 DebugLoc dl = MI->getDebugLoc();
8866 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
8867 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
8868 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
8869 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8870 F->insert(It, loop1MBB);
8871 F->insert(It, loop2MBB);
8872 F->insert(It, midMBB);
8873 F->insert(It, exitMBB);
8874 exitMBB->splice(exitMBB->begin(), BB,
8875 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8876 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8880 // fallthrough --> loopMBB
8881 BB->addSuccessor(loop1MBB);
8884 // l[bhwd]arx dest, ptr
8885 // cmp[wd] dest, oldval
8888 // st[bhwd]cx. newval, ptr
8892 // st[bhwd]cx. dest, ptr
8895 BuildMI(BB, dl, TII->get(LoadMnemonic), dest)
8896 .addReg(ptrA).addReg(ptrB);
8897 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
8898 .addReg(oldval).addReg(dest);
8899 BuildMI(BB, dl, TII->get(PPC::BCC))
8900 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
8901 BB->addSuccessor(loop2MBB);
8902 BB->addSuccessor(midMBB);
8905 BuildMI(BB, dl, TII->get(StoreMnemonic))
8906 .addReg(newval).addReg(ptrA).addReg(ptrB);
8907 BuildMI(BB, dl, TII->get(PPC::BCC))
8908 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
8909 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
8910 BB->addSuccessor(loop1MBB);
8911 BB->addSuccessor(exitMBB);
8914 BuildMI(BB, dl, TII->get(StoreMnemonic))
8915 .addReg(dest).addReg(ptrA).addReg(ptrB);
8916 BB->addSuccessor(exitMBB);
8921 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
8922 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
8923 // We must use 64-bit registers for addresses when targeting 64-bit,
8924 // since we're actually doing arithmetic on them. Other registers
8926 bool is64bit = Subtarget.isPPC64();
8927 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
8929 unsigned dest = MI->getOperand(0).getReg();
8930 unsigned ptrA = MI->getOperand(1).getReg();
8931 unsigned ptrB = MI->getOperand(2).getReg();
8932 unsigned oldval = MI->getOperand(3).getReg();
8933 unsigned newval = MI->getOperand(4).getReg();
8934 DebugLoc dl = MI->getDebugLoc();
8936 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
8937 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
8938 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
8939 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8940 F->insert(It, loop1MBB);
8941 F->insert(It, loop2MBB);
8942 F->insert(It, midMBB);
8943 F->insert(It, exitMBB);
8944 exitMBB->splice(exitMBB->begin(), BB,
8945 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8946 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8948 MachineRegisterInfo &RegInfo = F->getRegInfo();
8949 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
8950 : &PPC::GPRCRegClass;
8951 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
8952 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
8953 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
8954 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
8955 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
8956 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
8957 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
8958 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
8959 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
8960 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
8961 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
8962 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
8963 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
8965 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
8966 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
8969 // fallthrough --> loopMBB
8970 BB->addSuccessor(loop1MBB);
8972 // The 4-byte load must be aligned, while a char or short may be
8973 // anywhere in the word. Hence all this nasty bookkeeping code.
8974 // add ptr1, ptrA, ptrB [copy if ptrA==0]
8975 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
8976 // xori shift, shift1, 24 [16]
8977 // rlwinm ptr, ptr1, 0, 0, 29
8978 // slw newval2, newval, shift
8979 // slw oldval2, oldval,shift
8980 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
8981 // slw mask, mask2, shift
8982 // and newval3, newval2, mask
8983 // and oldval3, oldval2, mask
8985 // lwarx tmpDest, ptr
8986 // and tmp, tmpDest, mask
8987 // cmpw tmp, oldval3
8990 // andc tmp2, tmpDest, mask
8991 // or tmp4, tmp2, newval3
8996 // stwcx. tmpDest, ptr
8998 // srw dest, tmpDest, shift
8999 if (ptrA != ZeroReg) {
9000 Ptr1Reg = RegInfo.createVirtualRegister(RC);
9001 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
9002 .addReg(ptrA).addReg(ptrB);
9006 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
9007 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
9008 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
9009 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
9011 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
9012 .addReg(Ptr1Reg).addImm(0).addImm(61);
9014 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
9015 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
9016 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
9017 .addReg(newval).addReg(ShiftReg);
9018 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
9019 .addReg(oldval).addReg(ShiftReg);
9021 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
9023 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
9024 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
9025 .addReg(Mask3Reg).addImm(65535);
9027 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
9028 .addReg(Mask2Reg).addReg(ShiftReg);
9029 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
9030 .addReg(NewVal2Reg).addReg(MaskReg);
9031 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
9032 .addReg(OldVal2Reg).addReg(MaskReg);
9035 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
9036 .addReg(ZeroReg).addReg(PtrReg);
9037 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
9038 .addReg(TmpDestReg).addReg(MaskReg);
9039 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
9040 .addReg(TmpReg).addReg(OldVal3Reg);
9041 BuildMI(BB, dl, TII->get(PPC::BCC))
9042 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
9043 BB->addSuccessor(loop2MBB);
9044 BB->addSuccessor(midMBB);
9047 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
9048 .addReg(TmpDestReg).addReg(MaskReg);
9049 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
9050 .addReg(Tmp2Reg).addReg(NewVal3Reg);
9051 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
9052 .addReg(ZeroReg).addReg(PtrReg);
9053 BuildMI(BB, dl, TII->get(PPC::BCC))
9054 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
9055 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
9056 BB->addSuccessor(loop1MBB);
9057 BB->addSuccessor(exitMBB);
9060 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
9061 .addReg(ZeroReg).addReg(PtrReg);
9062 BB->addSuccessor(exitMBB);
9067 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
9069 } else if (MI->getOpcode() == PPC::FADDrtz) {
9070 // This pseudo performs an FADD with rounding mode temporarily forced
9071 // to round-to-zero. We emit this via custom inserter since the FPSCR
9072 // is not modeled at the SelectionDAG level.
9073 unsigned Dest = MI->getOperand(0).getReg();
9074 unsigned Src1 = MI->getOperand(1).getReg();
9075 unsigned Src2 = MI->getOperand(2).getReg();
9076 DebugLoc dl = MI->getDebugLoc();
9078 MachineRegisterInfo &RegInfo = F->getRegInfo();
9079 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
9081 // Save FPSCR value.
9082 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
9084 // Set rounding mode to round-to-zero.
9085 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
9086 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
9088 // Perform addition.
9089 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
9091 // Restore FPSCR value.
9092 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSFb)).addImm(1).addReg(MFFSReg);
9093 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
9094 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
9095 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
9096 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
9097 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
9098 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
9099 PPC::ANDIo8 : PPC::ANDIo;
9100 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
9101 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
9103 MachineRegisterInfo &RegInfo = F->getRegInfo();
9104 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
9105 &PPC::GPRCRegClass :
9106 &PPC::G8RCRegClass);
9108 DebugLoc dl = MI->getDebugLoc();
9109 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
9110 .addReg(MI->getOperand(1).getReg()).addImm(1);
9111 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
9112 MI->getOperand(0).getReg())
9113 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
9114 } else if (MI->getOpcode() == PPC::TCHECK_RET) {
9115 DebugLoc Dl = MI->getDebugLoc();
9116 MachineRegisterInfo &RegInfo = F->getRegInfo();
9117 unsigned CRReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
9118 BuildMI(*BB, MI, Dl, TII->get(PPC::TCHECK), CRReg);
9121 llvm_unreachable("Unexpected instr type to insert");
9124 MI->eraseFromParent(); // The pseudo instruction is gone now.
9128 //===----------------------------------------------------------------------===//
9129 // Target Optimization Hooks
9130 //===----------------------------------------------------------------------===//
9132 static std::string getRecipOp(const char *Base, EVT VT) {
9133 std::string RecipOp(Base);
9134 if (VT.getScalarType() == MVT::f64)
9140 RecipOp = "vec-" + RecipOp;
9145 SDValue PPCTargetLowering::getRsqrtEstimate(SDValue Operand,
9146 DAGCombinerInfo &DCI,
9147 unsigned &RefinementSteps,
9148 bool &UseOneConstNR) const {
9149 EVT VT = Operand.getValueType();
9150 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
9151 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
9152 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
9153 (VT == MVT::v2f64 && Subtarget.hasVSX()) ||
9154 (VT == MVT::v4f32 && Subtarget.hasQPX()) ||
9155 (VT == MVT::v4f64 && Subtarget.hasQPX())) {
9156 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
9157 std::string RecipOp = getRecipOp("sqrt", VT);
9158 if (!Recips.isEnabled(RecipOp))
9161 RefinementSteps = Recips.getRefinementSteps(RecipOp);
9162 UseOneConstNR = true;
9163 return DCI.DAG.getNode(PPCISD::FRSQRTE, SDLoc(Operand), VT, Operand);
9168 SDValue PPCTargetLowering::getRecipEstimate(SDValue Operand,
9169 DAGCombinerInfo &DCI,
9170 unsigned &RefinementSteps) const {
9171 EVT VT = Operand.getValueType();
9172 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
9173 (VT == MVT::f64 && Subtarget.hasFRE()) ||
9174 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
9175 (VT == MVT::v2f64 && Subtarget.hasVSX()) ||
9176 (VT == MVT::v4f32 && Subtarget.hasQPX()) ||
9177 (VT == MVT::v4f64 && Subtarget.hasQPX())) {
9178 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
9179 std::string RecipOp = getRecipOp("div", VT);
9180 if (!Recips.isEnabled(RecipOp))
9183 RefinementSteps = Recips.getRefinementSteps(RecipOp);
9184 return DCI.DAG.getNode(PPCISD::FRE, SDLoc(Operand), VT, Operand);
9189 unsigned PPCTargetLowering::combineRepeatedFPDivisors() const {
9190 // Note: This functionality is used only when unsafe-fp-math is enabled, and
9191 // on cores with reciprocal estimates (which are used when unsafe-fp-math is
9192 // enabled for division), this functionality is redundant with the default
9193 // combiner logic (once the division -> reciprocal/multiply transformation
9194 // has taken place). As a result, this matters more for older cores than for
9197 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
9198 // reciprocal if there are two or more FDIVs (for embedded cores with only
9199 // one FP pipeline) for three or more FDIVs (for generic OOO cores).
9200 switch (Subtarget.getDarwinDirective()) {
9205 case PPC::DIR_E500mc:
9206 case PPC::DIR_E5500:
9211 // isConsecutiveLSLoc needs to work even if all adds have not yet been
9212 // collapsed, and so we need to look through chains of them.
9213 static void getBaseWithConstantOffset(SDValue Loc, SDValue &Base,
9214 int64_t& Offset, SelectionDAG &DAG) {
9215 if (DAG.isBaseWithConstantOffset(Loc)) {
9216 Base = Loc.getOperand(0);
9217 Offset += cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue();
9219 // The base might itself be a base plus an offset, and if so, accumulate
9221 getBaseWithConstantOffset(Loc.getOperand(0), Base, Offset, DAG);
9225 static bool isConsecutiveLSLoc(SDValue Loc, EVT VT, LSBaseSDNode *Base,
9226 unsigned Bytes, int Dist,
9227 SelectionDAG &DAG) {
9228 if (VT.getSizeInBits() / 8 != Bytes)
9231 SDValue BaseLoc = Base->getBasePtr();
9232 if (Loc.getOpcode() == ISD::FrameIndex) {
9233 if (BaseLoc.getOpcode() != ISD::FrameIndex)
9235 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9236 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
9237 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
9238 int FS = MFI->getObjectSize(FI);
9239 int BFS = MFI->getObjectSize(BFI);
9240 if (FS != BFS || FS != (int)Bytes) return false;
9241 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
9244 SDValue Base1 = Loc, Base2 = BaseLoc;
9245 int64_t Offset1 = 0, Offset2 = 0;
9246 getBaseWithConstantOffset(Loc, Base1, Offset1, DAG);
9247 getBaseWithConstantOffset(BaseLoc, Base2, Offset2, DAG);
9248 if (Base1 == Base2 && Offset1 == (Offset2 + Dist * Bytes))
9251 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9252 const GlobalValue *GV1 = nullptr;
9253 const GlobalValue *GV2 = nullptr;
9256 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
9257 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
9258 if (isGA1 && isGA2 && GV1 == GV2)
9259 return Offset1 == (Offset2 + Dist*Bytes);
9263 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
9264 // not enforce equality of the chain operands.
9265 static bool isConsecutiveLS(SDNode *N, LSBaseSDNode *Base,
9266 unsigned Bytes, int Dist,
9267 SelectionDAG &DAG) {
9268 if (LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(N)) {
9269 EVT VT = LS->getMemoryVT();
9270 SDValue Loc = LS->getBasePtr();
9271 return isConsecutiveLSLoc(Loc, VT, Base, Bytes, Dist, DAG);
9274 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
9276 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9277 default: return false;
9278 case Intrinsic::ppc_qpx_qvlfd:
9279 case Intrinsic::ppc_qpx_qvlfda:
9282 case Intrinsic::ppc_qpx_qvlfs:
9283 case Intrinsic::ppc_qpx_qvlfsa:
9286 case Intrinsic::ppc_qpx_qvlfcd:
9287 case Intrinsic::ppc_qpx_qvlfcda:
9290 case Intrinsic::ppc_qpx_qvlfcs:
9291 case Intrinsic::ppc_qpx_qvlfcsa:
9294 case Intrinsic::ppc_qpx_qvlfiwa:
9295 case Intrinsic::ppc_qpx_qvlfiwz:
9296 case Intrinsic::ppc_altivec_lvx:
9297 case Intrinsic::ppc_altivec_lvxl:
9298 case Intrinsic::ppc_vsx_lxvw4x:
9301 case Intrinsic::ppc_vsx_lxvd2x:
9304 case Intrinsic::ppc_altivec_lvebx:
9307 case Intrinsic::ppc_altivec_lvehx:
9310 case Intrinsic::ppc_altivec_lvewx:
9315 return isConsecutiveLSLoc(N->getOperand(2), VT, Base, Bytes, Dist, DAG);
9318 if (N->getOpcode() == ISD::INTRINSIC_VOID) {
9320 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9321 default: return false;
9322 case Intrinsic::ppc_qpx_qvstfd:
9323 case Intrinsic::ppc_qpx_qvstfda:
9326 case Intrinsic::ppc_qpx_qvstfs:
9327 case Intrinsic::ppc_qpx_qvstfsa:
9330 case Intrinsic::ppc_qpx_qvstfcd:
9331 case Intrinsic::ppc_qpx_qvstfcda:
9334 case Intrinsic::ppc_qpx_qvstfcs:
9335 case Intrinsic::ppc_qpx_qvstfcsa:
9338 case Intrinsic::ppc_qpx_qvstfiw:
9339 case Intrinsic::ppc_qpx_qvstfiwa:
9340 case Intrinsic::ppc_altivec_stvx:
9341 case Intrinsic::ppc_altivec_stvxl:
9342 case Intrinsic::ppc_vsx_stxvw4x:
9345 case Intrinsic::ppc_vsx_stxvd2x:
9348 case Intrinsic::ppc_altivec_stvebx:
9351 case Intrinsic::ppc_altivec_stvehx:
9354 case Intrinsic::ppc_altivec_stvewx:
9359 return isConsecutiveLSLoc(N->getOperand(3), VT, Base, Bytes, Dist, DAG);
9365 // Return true is there is a nearyby consecutive load to the one provided
9366 // (regardless of alignment). We search up and down the chain, looking though
9367 // token factors and other loads (but nothing else). As a result, a true result
9368 // indicates that it is safe to create a new consecutive load adjacent to the
9370 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
9371 SDValue Chain = LD->getChain();
9372 EVT VT = LD->getMemoryVT();
9374 SmallSet<SDNode *, 16> LoadRoots;
9375 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
9376 SmallSet<SDNode *, 16> Visited;
9378 // First, search up the chain, branching to follow all token-factor operands.
9379 // If we find a consecutive load, then we're done, otherwise, record all
9380 // nodes just above the top-level loads and token factors.
9381 while (!Queue.empty()) {
9382 SDNode *ChainNext = Queue.pop_back_val();
9383 if (!Visited.insert(ChainNext).second)
9386 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(ChainNext)) {
9387 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
9390 if (!Visited.count(ChainLD->getChain().getNode()))
9391 Queue.push_back(ChainLD->getChain().getNode());
9392 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
9393 for (const SDUse &O : ChainNext->ops())
9394 if (!Visited.count(O.getNode()))
9395 Queue.push_back(O.getNode());
9397 LoadRoots.insert(ChainNext);
9400 // Second, search down the chain, starting from the top-level nodes recorded
9401 // in the first phase. These top-level nodes are the nodes just above all
9402 // loads and token factors. Starting with their uses, recursively look though
9403 // all loads (just the chain uses) and token factors to find a consecutive
9408 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
9409 IE = LoadRoots.end(); I != IE; ++I) {
9410 Queue.push_back(*I);
9412 while (!Queue.empty()) {
9413 SDNode *LoadRoot = Queue.pop_back_val();
9414 if (!Visited.insert(LoadRoot).second)
9417 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(LoadRoot))
9418 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
9421 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
9422 UE = LoadRoot->use_end(); UI != UE; ++UI)
9423 if (((isa<MemSDNode>(*UI) &&
9424 cast<MemSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
9425 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
9426 Queue.push_back(*UI);
9433 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
9434 DAGCombinerInfo &DCI) const {
9435 SelectionDAG &DAG = DCI.DAG;
9438 assert(Subtarget.useCRBits() && "Expecting to be tracking CR bits");
9439 // If we're tracking CR bits, we need to be careful that we don't have:
9440 // trunc(binary-ops(zext(x), zext(y)))
9442 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
9443 // such that we're unnecessarily moving things into GPRs when it would be
9444 // better to keep them in CR bits.
9446 // Note that trunc here can be an actual i1 trunc, or can be the effective
9447 // truncation that comes from a setcc or select_cc.
9448 if (N->getOpcode() == ISD::TRUNCATE &&
9449 N->getValueType(0) != MVT::i1)
9452 if (N->getOperand(0).getValueType() != MVT::i32 &&
9453 N->getOperand(0).getValueType() != MVT::i64)
9456 if (N->getOpcode() == ISD::SETCC ||
9457 N->getOpcode() == ISD::SELECT_CC) {
9458 // If we're looking at a comparison, then we need to make sure that the
9459 // high bits (all except for the first) don't matter the result.
9461 cast<CondCodeSDNode>(N->getOperand(
9462 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
9463 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
9465 if (ISD::isSignedIntSetCC(CC)) {
9466 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
9467 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
9469 } else if (ISD::isUnsignedIntSetCC(CC)) {
9470 if (!DAG.MaskedValueIsZero(N->getOperand(0),
9471 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
9472 !DAG.MaskedValueIsZero(N->getOperand(1),
9473 APInt::getHighBitsSet(OpBits, OpBits-1)))
9476 // This is neither a signed nor an unsigned comparison, just make sure
9477 // that the high bits are equal.
9478 APInt Op1Zero, Op1One;
9479 APInt Op2Zero, Op2One;
9480 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
9481 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
9483 // We don't really care about what is known about the first bit (if
9484 // anything), so clear it in all masks prior to comparing them.
9485 Op1Zero.clearBit(0); Op1One.clearBit(0);
9486 Op2Zero.clearBit(0); Op2One.clearBit(0);
9488 if (Op1Zero != Op2Zero || Op1One != Op2One)
9493 // We now know that the higher-order bits are irrelevant, we just need to
9494 // make sure that all of the intermediate operations are bit operations, and
9495 // all inputs are extensions.
9496 if (N->getOperand(0).getOpcode() != ISD::AND &&
9497 N->getOperand(0).getOpcode() != ISD::OR &&
9498 N->getOperand(0).getOpcode() != ISD::XOR &&
9499 N->getOperand(0).getOpcode() != ISD::SELECT &&
9500 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
9501 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
9502 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
9503 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
9504 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
9507 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
9508 N->getOperand(1).getOpcode() != ISD::AND &&
9509 N->getOperand(1).getOpcode() != ISD::OR &&
9510 N->getOperand(1).getOpcode() != ISD::XOR &&
9511 N->getOperand(1).getOpcode() != ISD::SELECT &&
9512 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
9513 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
9514 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
9515 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
9516 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
9519 SmallVector<SDValue, 4> Inputs;
9520 SmallVector<SDValue, 8> BinOps, PromOps;
9521 SmallPtrSet<SDNode *, 16> Visited;
9523 for (unsigned i = 0; i < 2; ++i) {
9524 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
9525 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
9526 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
9527 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
9528 isa<ConstantSDNode>(N->getOperand(i)))
9529 Inputs.push_back(N->getOperand(i));
9531 BinOps.push_back(N->getOperand(i));
9533 if (N->getOpcode() == ISD::TRUNCATE)
9537 // Visit all inputs, collect all binary operations (and, or, xor and
9538 // select) that are all fed by extensions.
9539 while (!BinOps.empty()) {
9540 SDValue BinOp = BinOps.back();
9543 if (!Visited.insert(BinOp.getNode()).second)
9546 PromOps.push_back(BinOp);
9548 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
9549 // The condition of the select is not promoted.
9550 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
9552 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
9555 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
9556 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
9557 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
9558 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
9559 isa<ConstantSDNode>(BinOp.getOperand(i))) {
9560 Inputs.push_back(BinOp.getOperand(i));
9561 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
9562 BinOp.getOperand(i).getOpcode() == ISD::OR ||
9563 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
9564 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
9565 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
9566 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
9567 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
9568 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
9569 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
9570 BinOps.push_back(BinOp.getOperand(i));
9572 // We have an input that is not an extension or another binary
9573 // operation; we'll abort this transformation.
9579 // Make sure that this is a self-contained cluster of operations (which
9580 // is not quite the same thing as saying that everything has only one
9582 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9583 if (isa<ConstantSDNode>(Inputs[i]))
9586 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
9587 UE = Inputs[i].getNode()->use_end();
9590 if (User != N && !Visited.count(User))
9593 // Make sure that we're not going to promote the non-output-value
9594 // operand(s) or SELECT or SELECT_CC.
9595 // FIXME: Although we could sometimes handle this, and it does occur in
9596 // practice that one of the condition inputs to the select is also one of
9597 // the outputs, we currently can't deal with this.
9598 if (User->getOpcode() == ISD::SELECT) {
9599 if (User->getOperand(0) == Inputs[i])
9601 } else if (User->getOpcode() == ISD::SELECT_CC) {
9602 if (User->getOperand(0) == Inputs[i] ||
9603 User->getOperand(1) == Inputs[i])
9609 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
9610 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
9611 UE = PromOps[i].getNode()->use_end();
9614 if (User != N && !Visited.count(User))
9617 // Make sure that we're not going to promote the non-output-value
9618 // operand(s) or SELECT or SELECT_CC.
9619 // FIXME: Although we could sometimes handle this, and it does occur in
9620 // practice that one of the condition inputs to the select is also one of
9621 // the outputs, we currently can't deal with this.
9622 if (User->getOpcode() == ISD::SELECT) {
9623 if (User->getOperand(0) == PromOps[i])
9625 } else if (User->getOpcode() == ISD::SELECT_CC) {
9626 if (User->getOperand(0) == PromOps[i] ||
9627 User->getOperand(1) == PromOps[i])
9633 // Replace all inputs with the extension operand.
9634 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9635 // Constants may have users outside the cluster of to-be-promoted nodes,
9636 // and so we need to replace those as we do the promotions.
9637 if (isa<ConstantSDNode>(Inputs[i]))
9640 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
9643 // Replace all operations (these are all the same, but have a different
9644 // (i1) return type). DAG.getNode will validate that the types of
9645 // a binary operator match, so go through the list in reverse so that
9646 // we've likely promoted both operands first. Any intermediate truncations or
9647 // extensions disappear.
9648 while (!PromOps.empty()) {
9649 SDValue PromOp = PromOps.back();
9652 if (PromOp.getOpcode() == ISD::TRUNCATE ||
9653 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
9654 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
9655 PromOp.getOpcode() == ISD::ANY_EXTEND) {
9656 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
9657 PromOp.getOperand(0).getValueType() != MVT::i1) {
9658 // The operand is not yet ready (see comment below).
9659 PromOps.insert(PromOps.begin(), PromOp);
9663 SDValue RepValue = PromOp.getOperand(0);
9664 if (isa<ConstantSDNode>(RepValue))
9665 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
9667 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
9672 switch (PromOp.getOpcode()) {
9673 default: C = 0; break;
9674 case ISD::SELECT: C = 1; break;
9675 case ISD::SELECT_CC: C = 2; break;
9678 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
9679 PromOp.getOperand(C).getValueType() != MVT::i1) ||
9680 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
9681 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
9682 // The to-be-promoted operands of this node have not yet been
9683 // promoted (this should be rare because we're going through the
9684 // list backward, but if one of the operands has several users in
9685 // this cluster of to-be-promoted nodes, it is possible).
9686 PromOps.insert(PromOps.begin(), PromOp);
9690 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
9691 PromOp.getNode()->op_end());
9693 // If there are any constant inputs, make sure they're replaced now.
9694 for (unsigned i = 0; i < 2; ++i)
9695 if (isa<ConstantSDNode>(Ops[C+i]))
9696 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
9698 DAG.ReplaceAllUsesOfValueWith(PromOp,
9699 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
9702 // Now we're left with the initial truncation itself.
9703 if (N->getOpcode() == ISD::TRUNCATE)
9704 return N->getOperand(0);
9706 // Otherwise, this is a comparison. The operands to be compared have just
9707 // changed type (to i1), but everything else is the same.
9708 return SDValue(N, 0);
9711 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
9712 DAGCombinerInfo &DCI) const {
9713 SelectionDAG &DAG = DCI.DAG;
9716 // If we're tracking CR bits, we need to be careful that we don't have:
9717 // zext(binary-ops(trunc(x), trunc(y)))
9719 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
9720 // such that we're unnecessarily moving things into CR bits that can more
9721 // efficiently stay in GPRs. Note that if we're not certain that the high
9722 // bits are set as required by the final extension, we still may need to do
9723 // some masking to get the proper behavior.
9725 // This same functionality is important on PPC64 when dealing with
9726 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
9727 // the return values of functions. Because it is so similar, it is handled
9730 if (N->getValueType(0) != MVT::i32 &&
9731 N->getValueType(0) != MVT::i64)
9734 if (!((N->getOperand(0).getValueType() == MVT::i1 && Subtarget.useCRBits()) ||
9735 (N->getOperand(0).getValueType() == MVT::i32 && Subtarget.isPPC64())))
9738 if (N->getOperand(0).getOpcode() != ISD::AND &&
9739 N->getOperand(0).getOpcode() != ISD::OR &&
9740 N->getOperand(0).getOpcode() != ISD::XOR &&
9741 N->getOperand(0).getOpcode() != ISD::SELECT &&
9742 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
9745 SmallVector<SDValue, 4> Inputs;
9746 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
9747 SmallPtrSet<SDNode *, 16> Visited;
9749 // Visit all inputs, collect all binary operations (and, or, xor and
9750 // select) that are all fed by truncations.
9751 while (!BinOps.empty()) {
9752 SDValue BinOp = BinOps.back();
9755 if (!Visited.insert(BinOp.getNode()).second)
9758 PromOps.push_back(BinOp);
9760 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
9761 // The condition of the select is not promoted.
9762 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
9764 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
9767 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
9768 isa<ConstantSDNode>(BinOp.getOperand(i))) {
9769 Inputs.push_back(BinOp.getOperand(i));
9770 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
9771 BinOp.getOperand(i).getOpcode() == ISD::OR ||
9772 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
9773 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
9774 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
9775 BinOps.push_back(BinOp.getOperand(i));
9777 // We have an input that is not a truncation or another binary
9778 // operation; we'll abort this transformation.
9784 // The operands of a select that must be truncated when the select is
9785 // promoted because the operand is actually part of the to-be-promoted set.
9786 DenseMap<SDNode *, EVT> SelectTruncOp[2];
9788 // Make sure that this is a self-contained cluster of operations (which
9789 // is not quite the same thing as saying that everything has only one
9791 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9792 if (isa<ConstantSDNode>(Inputs[i]))
9795 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
9796 UE = Inputs[i].getNode()->use_end();
9799 if (User != N && !Visited.count(User))
9802 // If we're going to promote the non-output-value operand(s) or SELECT or
9803 // SELECT_CC, record them for truncation.
9804 if (User->getOpcode() == ISD::SELECT) {
9805 if (User->getOperand(0) == Inputs[i])
9806 SelectTruncOp[0].insert(std::make_pair(User,
9807 User->getOperand(0).getValueType()));
9808 } else if (User->getOpcode() == ISD::SELECT_CC) {
9809 if (User->getOperand(0) == Inputs[i])
9810 SelectTruncOp[0].insert(std::make_pair(User,
9811 User->getOperand(0).getValueType()));
9812 if (User->getOperand(1) == Inputs[i])
9813 SelectTruncOp[1].insert(std::make_pair(User,
9814 User->getOperand(1).getValueType()));
9819 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
9820 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
9821 UE = PromOps[i].getNode()->use_end();
9824 if (User != N && !Visited.count(User))
9827 // If we're going to promote the non-output-value operand(s) or SELECT or
9828 // SELECT_CC, record them for truncation.
9829 if (User->getOpcode() == ISD::SELECT) {
9830 if (User->getOperand(0) == PromOps[i])
9831 SelectTruncOp[0].insert(std::make_pair(User,
9832 User->getOperand(0).getValueType()));
9833 } else if (User->getOpcode() == ISD::SELECT_CC) {
9834 if (User->getOperand(0) == PromOps[i])
9835 SelectTruncOp[0].insert(std::make_pair(User,
9836 User->getOperand(0).getValueType()));
9837 if (User->getOperand(1) == PromOps[i])
9838 SelectTruncOp[1].insert(std::make_pair(User,
9839 User->getOperand(1).getValueType()));
9844 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
9845 bool ReallyNeedsExt = false;
9846 if (N->getOpcode() != ISD::ANY_EXTEND) {
9847 // If all of the inputs are not already sign/zero extended, then
9848 // we'll still need to do that at the end.
9849 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9850 if (isa<ConstantSDNode>(Inputs[i]))
9854 Inputs[i].getOperand(0).getValueSizeInBits();
9855 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
9857 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
9858 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
9859 APInt::getHighBitsSet(OpBits,
9860 OpBits-PromBits))) ||
9861 (N->getOpcode() == ISD::SIGN_EXTEND &&
9862 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
9863 (OpBits-(PromBits-1)))) {
9864 ReallyNeedsExt = true;
9870 // Replace all inputs, either with the truncation operand, or a
9871 // truncation or extension to the final output type.
9872 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9873 // Constant inputs need to be replaced with the to-be-promoted nodes that
9874 // use them because they might have users outside of the cluster of
9876 if (isa<ConstantSDNode>(Inputs[i]))
9879 SDValue InSrc = Inputs[i].getOperand(0);
9880 if (Inputs[i].getValueType() == N->getValueType(0))
9881 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
9882 else if (N->getOpcode() == ISD::SIGN_EXTEND)
9883 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
9884 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
9885 else if (N->getOpcode() == ISD::ZERO_EXTEND)
9886 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
9887 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
9889 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
9890 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
9893 // Replace all operations (these are all the same, but have a different
9894 // (promoted) return type). DAG.getNode will validate that the types of
9895 // a binary operator match, so go through the list in reverse so that
9896 // we've likely promoted both operands first.
9897 while (!PromOps.empty()) {
9898 SDValue PromOp = PromOps.back();
9902 switch (PromOp.getOpcode()) {
9903 default: C = 0; break;
9904 case ISD::SELECT: C = 1; break;
9905 case ISD::SELECT_CC: C = 2; break;
9908 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
9909 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
9910 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
9911 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
9912 // The to-be-promoted operands of this node have not yet been
9913 // promoted (this should be rare because we're going through the
9914 // list backward, but if one of the operands has several users in
9915 // this cluster of to-be-promoted nodes, it is possible).
9916 PromOps.insert(PromOps.begin(), PromOp);
9920 // For SELECT and SELECT_CC nodes, we do a similar check for any
9921 // to-be-promoted comparison inputs.
9922 if (PromOp.getOpcode() == ISD::SELECT ||
9923 PromOp.getOpcode() == ISD::SELECT_CC) {
9924 if ((SelectTruncOp[0].count(PromOp.getNode()) &&
9925 PromOp.getOperand(0).getValueType() != N->getValueType(0)) ||
9926 (SelectTruncOp[1].count(PromOp.getNode()) &&
9927 PromOp.getOperand(1).getValueType() != N->getValueType(0))) {
9928 PromOps.insert(PromOps.begin(), PromOp);
9933 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
9934 PromOp.getNode()->op_end());
9936 // If this node has constant inputs, then they'll need to be promoted here.
9937 for (unsigned i = 0; i < 2; ++i) {
9938 if (!isa<ConstantSDNode>(Ops[C+i]))
9940 if (Ops[C+i].getValueType() == N->getValueType(0))
9943 if (N->getOpcode() == ISD::SIGN_EXTEND)
9944 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
9945 else if (N->getOpcode() == ISD::ZERO_EXTEND)
9946 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
9948 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
9951 // If we've promoted the comparison inputs of a SELECT or SELECT_CC,
9952 // truncate them again to the original value type.
9953 if (PromOp.getOpcode() == ISD::SELECT ||
9954 PromOp.getOpcode() == ISD::SELECT_CC) {
9955 auto SI0 = SelectTruncOp[0].find(PromOp.getNode());
9956 if (SI0 != SelectTruncOp[0].end())
9957 Ops[0] = DAG.getNode(ISD::TRUNCATE, dl, SI0->second, Ops[0]);
9958 auto SI1 = SelectTruncOp[1].find(PromOp.getNode());
9959 if (SI1 != SelectTruncOp[1].end())
9960 Ops[1] = DAG.getNode(ISD::TRUNCATE, dl, SI1->second, Ops[1]);
9963 DAG.ReplaceAllUsesOfValueWith(PromOp,
9964 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
9967 // Now we're left with the initial extension itself.
9968 if (!ReallyNeedsExt)
9969 return N->getOperand(0);
9971 // To zero extend, just mask off everything except for the first bit (in the
9973 if (N->getOpcode() == ISD::ZERO_EXTEND)
9974 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
9975 DAG.getConstant(APInt::getLowBitsSet(
9976 N->getValueSizeInBits(0), PromBits),
9977 dl, N->getValueType(0)));
9979 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
9980 "Invalid extension type");
9981 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0), DAG.getDataLayout());
9983 DAG.getConstant(N->getValueSizeInBits(0) - PromBits, dl, ShiftAmountTy);
9985 ISD::SRA, dl, N->getValueType(0),
9986 DAG.getNode(ISD::SHL, dl, N->getValueType(0), N->getOperand(0), ShiftCst),
9990 SDValue PPCTargetLowering::combineFPToIntToFP(SDNode *N,
9991 DAGCombinerInfo &DCI) const {
9992 assert((N->getOpcode() == ISD::SINT_TO_FP ||
9993 N->getOpcode() == ISD::UINT_TO_FP) &&
9994 "Need an int -> FP conversion node here");
9996 if (!Subtarget.has64BitSupport())
9999 SelectionDAG &DAG = DCI.DAG;
10003 // Don't handle ppc_fp128 here or i1 conversions.
10004 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
10006 if (Op.getOperand(0).getValueType() == MVT::i1)
10009 // For i32 intermediate values, unfortunately, the conversion functions
10010 // leave the upper 32 bits of the value are undefined. Within the set of
10011 // scalar instructions, we have no method for zero- or sign-extending the
10012 // value. Thus, we cannot handle i32 intermediate values here.
10013 if (Op.getOperand(0).getValueType() == MVT::i32)
10016 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
10017 "UINT_TO_FP is supported only with FPCVT");
10019 // If we have FCFIDS, then use it when converting to single-precision.
10020 // Otherwise, convert to double-precision and then round.
10021 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
10022 ? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
10024 : (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
10026 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
10030 // If we're converting from a float, to an int, and back to a float again,
10031 // then we don't need the store/load pair at all.
10032 if ((Op.getOperand(0).getOpcode() == ISD::FP_TO_UINT &&
10033 Subtarget.hasFPCVT()) ||
10034 (Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT)) {
10035 SDValue Src = Op.getOperand(0).getOperand(0);
10036 if (Src.getValueType() == MVT::f32) {
10037 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
10038 DCI.AddToWorklist(Src.getNode());
10039 } else if (Src.getValueType() != MVT::f64) {
10040 // Make sure that we don't pick up a ppc_fp128 source value.
10045 Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
10048 SDValue Tmp = DAG.getNode(FCTOp, dl, MVT::f64, Src);
10049 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Tmp);
10051 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) {
10052 FP = DAG.getNode(ISD::FP_ROUND, dl,
10053 MVT::f32, FP, DAG.getIntPtrConstant(0, dl));
10054 DCI.AddToWorklist(FP.getNode());
10063 // expandVSXLoadForLE - Convert VSX loads (which may be intrinsics for
10064 // builtins) into loads with swaps.
10065 SDValue PPCTargetLowering::expandVSXLoadForLE(SDNode *N,
10066 DAGCombinerInfo &DCI) const {
10067 SelectionDAG &DAG = DCI.DAG;
10071 MachineMemOperand *MMO;
10073 switch (N->getOpcode()) {
10075 llvm_unreachable("Unexpected opcode for little endian VSX load");
10077 LoadSDNode *LD = cast<LoadSDNode>(N);
10078 Chain = LD->getChain();
10079 Base = LD->getBasePtr();
10080 MMO = LD->getMemOperand();
10081 // If the MMO suggests this isn't a load of a full vector, leave
10082 // things alone. For a built-in, we have to make the change for
10083 // correctness, so if there is a size problem that will be a bug.
10084 if (MMO->getSize() < 16)
10088 case ISD::INTRINSIC_W_CHAIN: {
10089 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
10090 Chain = Intrin->getChain();
10091 // Similarly to the store case below, Intrin->getBasePtr() doesn't get
10092 // us what we want. Get operand 2 instead.
10093 Base = Intrin->getOperand(2);
10094 MMO = Intrin->getMemOperand();
10099 MVT VecTy = N->getValueType(0).getSimpleVT();
10100 SDValue LoadOps[] = { Chain, Base };
10101 SDValue Load = DAG.getMemIntrinsicNode(PPCISD::LXVD2X, dl,
10102 DAG.getVTList(VecTy, MVT::Other),
10103 LoadOps, VecTy, MMO);
10104 DCI.AddToWorklist(Load.getNode());
10105 Chain = Load.getValue(1);
10106 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
10107 DAG.getVTList(VecTy, MVT::Other), Chain, Load);
10108 DCI.AddToWorklist(Swap.getNode());
10112 // expandVSXStoreForLE - Convert VSX stores (which may be intrinsics for
10113 // builtins) into stores with swaps.
10114 SDValue PPCTargetLowering::expandVSXStoreForLE(SDNode *N,
10115 DAGCombinerInfo &DCI) const {
10116 SelectionDAG &DAG = DCI.DAG;
10121 MachineMemOperand *MMO;
10123 switch (N->getOpcode()) {
10125 llvm_unreachable("Unexpected opcode for little endian VSX store");
10127 StoreSDNode *ST = cast<StoreSDNode>(N);
10128 Chain = ST->getChain();
10129 Base = ST->getBasePtr();
10130 MMO = ST->getMemOperand();
10132 // If the MMO suggests this isn't a store of a full vector, leave
10133 // things alone. For a built-in, we have to make the change for
10134 // correctness, so if there is a size problem that will be a bug.
10135 if (MMO->getSize() < 16)
10139 case ISD::INTRINSIC_VOID: {
10140 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
10141 Chain = Intrin->getChain();
10142 // Intrin->getBasePtr() oddly does not get what we want.
10143 Base = Intrin->getOperand(3);
10144 MMO = Intrin->getMemOperand();
10150 SDValue Src = N->getOperand(SrcOpnd);
10151 MVT VecTy = Src.getValueType().getSimpleVT();
10152 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
10153 DAG.getVTList(VecTy, MVT::Other), Chain, Src);
10154 DCI.AddToWorklist(Swap.getNode());
10155 Chain = Swap.getValue(1);
10156 SDValue StoreOps[] = { Chain, Swap, Base };
10157 SDValue Store = DAG.getMemIntrinsicNode(PPCISD::STXVD2X, dl,
10158 DAG.getVTList(MVT::Other),
10159 StoreOps, VecTy, MMO);
10160 DCI.AddToWorklist(Store.getNode());
10164 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
10165 DAGCombinerInfo &DCI) const {
10166 SelectionDAG &DAG = DCI.DAG;
10168 switch (N->getOpcode()) {
10171 if (isNullConstant(N->getOperand(0))) // 0 << V -> 0.
10172 return N->getOperand(0);
10175 if (isNullConstant(N->getOperand(0))) // 0 >>u V -> 0.
10176 return N->getOperand(0);
10179 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
10180 if (C->isNullValue() || // 0 >>s V -> 0.
10181 C->isAllOnesValue()) // -1 >>s V -> -1.
10182 return N->getOperand(0);
10185 case ISD::SIGN_EXTEND:
10186 case ISD::ZERO_EXTEND:
10187 case ISD::ANY_EXTEND:
10188 return DAGCombineExtBoolTrunc(N, DCI);
10189 case ISD::TRUNCATE:
10191 case ISD::SELECT_CC:
10192 return DAGCombineTruncBoolExt(N, DCI);
10193 case ISD::SINT_TO_FP:
10194 case ISD::UINT_TO_FP:
10195 return combineFPToIntToFP(N, DCI);
10197 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
10198 if (Subtarget.hasSTFIWX() && !cast<StoreSDNode>(N)->isTruncatingStore() &&
10199 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
10200 N->getOperand(1).getValueType() == MVT::i32 &&
10201 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
10202 SDValue Val = N->getOperand(1).getOperand(0);
10203 if (Val.getValueType() == MVT::f32) {
10204 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
10205 DCI.AddToWorklist(Val.getNode());
10207 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
10208 DCI.AddToWorklist(Val.getNode());
10211 N->getOperand(0), Val, N->getOperand(2),
10212 DAG.getValueType(N->getOperand(1).getValueType())
10215 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
10216 DAG.getVTList(MVT::Other), Ops,
10217 cast<StoreSDNode>(N)->getMemoryVT(),
10218 cast<StoreSDNode>(N)->getMemOperand());
10219 DCI.AddToWorklist(Val.getNode());
10223 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
10224 if (cast<StoreSDNode>(N)->isUnindexed() &&
10225 N->getOperand(1).getOpcode() == ISD::BSWAP &&
10226 N->getOperand(1).getNode()->hasOneUse() &&
10227 (N->getOperand(1).getValueType() == MVT::i32 ||
10228 N->getOperand(1).getValueType() == MVT::i16 ||
10229 (Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
10230 N->getOperand(1).getValueType() == MVT::i64))) {
10231 SDValue BSwapOp = N->getOperand(1).getOperand(0);
10232 // Do an any-extend to 32-bits if this is a half-word input.
10233 if (BSwapOp.getValueType() == MVT::i16)
10234 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
10237 N->getOperand(0), BSwapOp, N->getOperand(2),
10238 DAG.getValueType(N->getOperand(1).getValueType())
10241 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
10242 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
10243 cast<StoreSDNode>(N)->getMemOperand());
10246 // For little endian, VSX stores require generating xxswapd/lxvd2x.
10247 EVT VT = N->getOperand(1).getValueType();
10248 if (VT.isSimple()) {
10249 MVT StoreVT = VT.getSimpleVT();
10250 if (Subtarget.hasVSX() && Subtarget.isLittleEndian() &&
10251 (StoreVT == MVT::v2f64 || StoreVT == MVT::v2i64 ||
10252 StoreVT == MVT::v4f32 || StoreVT == MVT::v4i32))
10253 return expandVSXStoreForLE(N, DCI);
10258 LoadSDNode *LD = cast<LoadSDNode>(N);
10259 EVT VT = LD->getValueType(0);
10261 // For little endian, VSX loads require generating lxvd2x/xxswapd.
10262 if (VT.isSimple()) {
10263 MVT LoadVT = VT.getSimpleVT();
10264 if (Subtarget.hasVSX() && Subtarget.isLittleEndian() &&
10265 (LoadVT == MVT::v2f64 || LoadVT == MVT::v2i64 ||
10266 LoadVT == MVT::v4f32 || LoadVT == MVT::v4i32))
10267 return expandVSXLoadForLE(N, DCI);
10270 EVT MemVT = LD->getMemoryVT();
10271 Type *Ty = MemVT.getTypeForEVT(*DAG.getContext());
10272 unsigned ABIAlignment = DAG.getDataLayout().getABITypeAlignment(Ty);
10273 Type *STy = MemVT.getScalarType().getTypeForEVT(*DAG.getContext());
10274 unsigned ScalarABIAlignment = DAG.getDataLayout().getABITypeAlignment(STy);
10275 if (LD->isUnindexed() && VT.isVector() &&
10276 ((Subtarget.hasAltivec() && ISD::isNON_EXTLoad(N) &&
10277 // P8 and later hardware should just use LOAD.
10278 !Subtarget.hasP8Vector() && (VT == MVT::v16i8 || VT == MVT::v8i16 ||
10279 VT == MVT::v4i32 || VT == MVT::v4f32)) ||
10280 (Subtarget.hasQPX() && (VT == MVT::v4f64 || VT == MVT::v4f32) &&
10281 LD->getAlignment() >= ScalarABIAlignment)) &&
10282 LD->getAlignment() < ABIAlignment) {
10283 // This is a type-legal unaligned Altivec or QPX load.
10284 SDValue Chain = LD->getChain();
10285 SDValue Ptr = LD->getBasePtr();
10286 bool isLittleEndian = Subtarget.isLittleEndian();
10288 // This implements the loading of unaligned vectors as described in
10289 // the venerable Apple Velocity Engine overview. Specifically:
10290 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
10291 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
10293 // The general idea is to expand a sequence of one or more unaligned
10294 // loads into an alignment-based permutation-control instruction (lvsl
10295 // or lvsr), a series of regular vector loads (which always truncate
10296 // their input address to an aligned address), and a series of
10297 // permutations. The results of these permutations are the requested
10298 // loaded values. The trick is that the last "extra" load is not taken
10299 // from the address you might suspect (sizeof(vector) bytes after the
10300 // last requested load), but rather sizeof(vector) - 1 bytes after the
10301 // last requested vector. The point of this is to avoid a page fault if
10302 // the base address happened to be aligned. This works because if the
10303 // base address is aligned, then adding less than a full vector length
10304 // will cause the last vector in the sequence to be (re)loaded.
10305 // Otherwise, the next vector will be fetched as you might suspect was
10308 // We might be able to reuse the permutation generation from
10309 // a different base address offset from this one by an aligned amount.
10310 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
10311 // optimization later.
10312 Intrinsic::ID Intr, IntrLD, IntrPerm;
10313 MVT PermCntlTy, PermTy, LDTy;
10314 if (Subtarget.hasAltivec()) {
10315 Intr = isLittleEndian ? Intrinsic::ppc_altivec_lvsr :
10316 Intrinsic::ppc_altivec_lvsl;
10317 IntrLD = Intrinsic::ppc_altivec_lvx;
10318 IntrPerm = Intrinsic::ppc_altivec_vperm;
10319 PermCntlTy = MVT::v16i8;
10320 PermTy = MVT::v4i32;
10323 Intr = MemVT == MVT::v4f64 ? Intrinsic::ppc_qpx_qvlpcld :
10324 Intrinsic::ppc_qpx_qvlpcls;
10325 IntrLD = MemVT == MVT::v4f64 ? Intrinsic::ppc_qpx_qvlfd :
10326 Intrinsic::ppc_qpx_qvlfs;
10327 IntrPerm = Intrinsic::ppc_qpx_qvfperm;
10328 PermCntlTy = MVT::v4f64;
10329 PermTy = MVT::v4f64;
10330 LDTy = MemVT.getSimpleVT();
10333 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, PermCntlTy);
10335 // Create the new MMO for the new base load. It is like the original MMO,
10336 // but represents an area in memory almost twice the vector size centered
10337 // on the original address. If the address is unaligned, we might start
10338 // reading up to (sizeof(vector)-1) bytes below the address of the
10339 // original unaligned load.
10340 MachineFunction &MF = DAG.getMachineFunction();
10341 MachineMemOperand *BaseMMO =
10342 MF.getMachineMemOperand(LD->getMemOperand(),
10343 -(long)MemVT.getStoreSize()+1,
10344 2*MemVT.getStoreSize()-1);
10346 // Create the new base load.
10348 DAG.getTargetConstant(IntrLD, dl, getPointerTy(MF.getDataLayout()));
10349 SDValue BaseLoadOps[] = { Chain, LDXIntID, Ptr };
10351 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
10352 DAG.getVTList(PermTy, MVT::Other),
10353 BaseLoadOps, LDTy, BaseMMO);
10355 // Note that the value of IncOffset (which is provided to the next
10356 // load's pointer info offset value, and thus used to calculate the
10357 // alignment), and the value of IncValue (which is actually used to
10358 // increment the pointer value) are different! This is because we
10359 // require the next load to appear to be aligned, even though it
10360 // is actually offset from the base pointer by a lesser amount.
10361 int IncOffset = VT.getSizeInBits() / 8;
10362 int IncValue = IncOffset;
10364 // Walk (both up and down) the chain looking for another load at the real
10365 // (aligned) offset (the alignment of the other load does not matter in
10366 // this case). If found, then do not use the offset reduction trick, as
10367 // that will prevent the loads from being later combined (as they would
10368 // otherwise be duplicates).
10369 if (!findConsecutiveLoad(LD, DAG))
10372 SDValue Increment =
10373 DAG.getConstant(IncValue, dl, getPointerTy(MF.getDataLayout()));
10374 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
10376 MachineMemOperand *ExtraMMO =
10377 MF.getMachineMemOperand(LD->getMemOperand(),
10378 1, 2*MemVT.getStoreSize()-1);
10379 SDValue ExtraLoadOps[] = { Chain, LDXIntID, Ptr };
10380 SDValue ExtraLoad =
10381 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
10382 DAG.getVTList(PermTy, MVT::Other),
10383 ExtraLoadOps, LDTy, ExtraMMO);
10385 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
10386 BaseLoad.getValue(1), ExtraLoad.getValue(1));
10388 // Because vperm has a big-endian bias, we must reverse the order
10389 // of the input vectors and complement the permute control vector
10390 // when generating little endian code. We have already handled the
10391 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
10392 // and ExtraLoad here.
10394 if (isLittleEndian)
10395 Perm = BuildIntrinsicOp(IntrPerm,
10396 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
10398 Perm = BuildIntrinsicOp(IntrPerm,
10399 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
10402 Perm = Subtarget.hasAltivec() ?
10403 DAG.getNode(ISD::BITCAST, dl, VT, Perm) :
10404 DAG.getNode(ISD::FP_ROUND, dl, VT, Perm, // QPX
10405 DAG.getTargetConstant(1, dl, MVT::i64));
10406 // second argument is 1 because this rounding
10407 // is always exact.
10409 // The output of the permutation is our loaded result, the TokenFactor is
10411 DCI.CombineTo(N, Perm, TF);
10412 return SDValue(N, 0);
10416 case ISD::INTRINSIC_WO_CHAIN: {
10417 bool isLittleEndian = Subtarget.isLittleEndian();
10418 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
10419 Intrinsic::ID Intr = (isLittleEndian ? Intrinsic::ppc_altivec_lvsr
10420 : Intrinsic::ppc_altivec_lvsl);
10421 if ((IID == Intr ||
10422 IID == Intrinsic::ppc_qpx_qvlpcld ||
10423 IID == Intrinsic::ppc_qpx_qvlpcls) &&
10424 N->getOperand(1)->getOpcode() == ISD::ADD) {
10425 SDValue Add = N->getOperand(1);
10427 int Bits = IID == Intrinsic::ppc_qpx_qvlpcld ?
10428 5 /* 32 byte alignment */ : 4 /* 16 byte alignment */;
10430 if (DAG.MaskedValueIsZero(
10431 Add->getOperand(1),
10432 APInt::getAllOnesValue(Bits /* alignment */)
10434 Add.getValueType().getScalarType().getSizeInBits()))) {
10435 SDNode *BasePtr = Add->getOperand(0).getNode();
10436 for (SDNode::use_iterator UI = BasePtr->use_begin(),
10437 UE = BasePtr->use_end();
10439 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
10440 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() == IID) {
10441 // We've found another LVSL/LVSR, and this address is an aligned
10442 // multiple of that one. The results will be the same, so use the
10443 // one we've just found instead.
10445 return SDValue(*UI, 0);
10450 if (isa<ConstantSDNode>(Add->getOperand(1))) {
10451 SDNode *BasePtr = Add->getOperand(0).getNode();
10452 for (SDNode::use_iterator UI = BasePtr->use_begin(),
10453 UE = BasePtr->use_end(); UI != UE; ++UI) {
10454 if (UI->getOpcode() == ISD::ADD &&
10455 isa<ConstantSDNode>(UI->getOperand(1)) &&
10456 (cast<ConstantSDNode>(Add->getOperand(1))->getZExtValue() -
10457 cast<ConstantSDNode>(UI->getOperand(1))->getZExtValue()) %
10458 (1ULL << Bits) == 0) {
10459 SDNode *OtherAdd = *UI;
10460 for (SDNode::use_iterator VI = OtherAdd->use_begin(),
10461 VE = OtherAdd->use_end(); VI != VE; ++VI) {
10462 if (VI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
10463 cast<ConstantSDNode>(VI->getOperand(0))->getZExtValue() == IID) {
10464 return SDValue(*VI, 0);
10474 case ISD::INTRINSIC_W_CHAIN: {
10475 // For little endian, VSX loads require generating lxvd2x/xxswapd.
10476 if (Subtarget.hasVSX() && Subtarget.isLittleEndian()) {
10477 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
10480 case Intrinsic::ppc_vsx_lxvw4x:
10481 case Intrinsic::ppc_vsx_lxvd2x:
10482 return expandVSXLoadForLE(N, DCI);
10487 case ISD::INTRINSIC_VOID: {
10488 // For little endian, VSX stores require generating xxswapd/stxvd2x.
10489 if (Subtarget.hasVSX() && Subtarget.isLittleEndian()) {
10490 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
10493 case Intrinsic::ppc_vsx_stxvw4x:
10494 case Intrinsic::ppc_vsx_stxvd2x:
10495 return expandVSXStoreForLE(N, DCI);
10501 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
10502 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
10503 N->getOperand(0).hasOneUse() &&
10504 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
10505 (Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
10506 N->getValueType(0) == MVT::i64))) {
10507 SDValue Load = N->getOperand(0);
10508 LoadSDNode *LD = cast<LoadSDNode>(Load);
10509 // Create the byte-swapping load.
10511 LD->getChain(), // Chain
10512 LD->getBasePtr(), // Ptr
10513 DAG.getValueType(N->getValueType(0)) // VT
10516 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
10517 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
10518 MVT::i64 : MVT::i32, MVT::Other),
10519 Ops, LD->getMemoryVT(), LD->getMemOperand());
10521 // If this is an i16 load, insert the truncate.
10522 SDValue ResVal = BSLoad;
10523 if (N->getValueType(0) == MVT::i16)
10524 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
10526 // First, combine the bswap away. This makes the value produced by the
10528 DCI.CombineTo(N, ResVal);
10530 // Next, combine the load away, we give it a bogus result value but a real
10531 // chain result. The result value is dead because the bswap is dead.
10532 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
10534 // Return N so it doesn't get rechecked!
10535 return SDValue(N, 0);
10539 case PPCISD::VCMP: {
10540 // If a VCMPo node already exists with exactly the same operands as this
10541 // node, use its result instead of this node (VCMPo computes both a CR6 and
10542 // a normal output).
10544 if (!N->getOperand(0).hasOneUse() &&
10545 !N->getOperand(1).hasOneUse() &&
10546 !N->getOperand(2).hasOneUse()) {
10548 // Scan all of the users of the LHS, looking for VCMPo's that match.
10549 SDNode *VCMPoNode = nullptr;
10551 SDNode *LHSN = N->getOperand(0).getNode();
10552 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
10554 if (UI->getOpcode() == PPCISD::VCMPo &&
10555 UI->getOperand(1) == N->getOperand(1) &&
10556 UI->getOperand(2) == N->getOperand(2) &&
10557 UI->getOperand(0) == N->getOperand(0)) {
10562 // If there is no VCMPo node, or if the flag value has a single use, don't
10564 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
10567 // Look at the (necessarily single) use of the flag value. If it has a
10568 // chain, this transformation is more complex. Note that multiple things
10569 // could use the value result, which we should ignore.
10570 SDNode *FlagUser = nullptr;
10571 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
10572 FlagUser == nullptr; ++UI) {
10573 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
10574 SDNode *User = *UI;
10575 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
10576 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
10583 // If the user is a MFOCRF instruction, we know this is safe.
10584 // Otherwise we give up for right now.
10585 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
10586 return SDValue(VCMPoNode, 0);
10590 case ISD::BRCOND: {
10591 SDValue Cond = N->getOperand(1);
10592 SDValue Target = N->getOperand(2);
10594 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
10595 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
10596 Intrinsic::ppc_is_decremented_ctr_nonzero) {
10598 // We now need to make the intrinsic dead (it cannot be instruction
10600 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
10601 assert(Cond.getNode()->hasOneUse() &&
10602 "Counter decrement has more than one use");
10604 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
10605 N->getOperand(0), Target);
10610 // If this is a branch on an altivec predicate comparison, lower this so
10611 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
10612 // lowering is done pre-legalize, because the legalizer lowers the predicate
10613 // compare down to code that is difficult to reassemble.
10614 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
10615 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
10617 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
10618 // value. If so, pass-through the AND to get to the intrinsic.
10619 if (LHS.getOpcode() == ISD::AND &&
10620 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
10621 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
10622 Intrinsic::ppc_is_decremented_ctr_nonzero &&
10623 isa<ConstantSDNode>(LHS.getOperand(1)) &&
10624 !isNullConstant(LHS.getOperand(1)))
10625 LHS = LHS.getOperand(0);
10627 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
10628 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
10629 Intrinsic::ppc_is_decremented_ctr_nonzero &&
10630 isa<ConstantSDNode>(RHS)) {
10631 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
10632 "Counter decrement comparison is not EQ or NE");
10634 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
10635 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
10636 (CC == ISD::SETNE && !Val);
10638 // We now need to make the intrinsic dead (it cannot be instruction
10640 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
10641 assert(LHS.getNode()->hasOneUse() &&
10642 "Counter decrement has more than one use");
10644 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
10645 N->getOperand(0), N->getOperand(4));
10651 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
10652 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
10653 getVectorCompareInfo(LHS, CompareOpc, isDot, Subtarget)) {
10654 assert(isDot && "Can't compare against a vector result!");
10656 // If this is a comparison against something other than 0/1, then we know
10657 // that the condition is never/always true.
10658 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
10659 if (Val != 0 && Val != 1) {
10660 if (CC == ISD::SETEQ) // Cond never true, remove branch.
10661 return N->getOperand(0);
10662 // Always !=, turn it into an unconditional branch.
10663 return DAG.getNode(ISD::BR, dl, MVT::Other,
10664 N->getOperand(0), N->getOperand(4));
10667 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
10669 // Create the PPCISD altivec 'dot' comparison node.
10671 LHS.getOperand(2), // LHS of compare
10672 LHS.getOperand(3), // RHS of compare
10673 DAG.getConstant(CompareOpc, dl, MVT::i32)
10675 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
10676 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
10678 // Unpack the result based on how the target uses it.
10679 PPC::Predicate CompOpc;
10680 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
10681 default: // Can't happen, don't crash on invalid number though.
10682 case 0: // Branch on the value of the EQ bit of CR6.
10683 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
10685 case 1: // Branch on the inverted value of the EQ bit of CR6.
10686 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
10688 case 2: // Branch on the value of the LT bit of CR6.
10689 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
10691 case 3: // Branch on the inverted value of the LT bit of CR6.
10692 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
10696 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
10697 DAG.getConstant(CompOpc, dl, MVT::i32),
10698 DAG.getRegister(PPC::CR6, MVT::i32),
10699 N->getOperand(4), CompNode.getValue(1));
10709 PPCTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
10711 std::vector<SDNode *> *Created) const {
10712 // fold (sdiv X, pow2)
10713 EVT VT = N->getValueType(0);
10714 if (VT == MVT::i64 && !Subtarget.isPPC64())
10716 if ((VT != MVT::i32 && VT != MVT::i64) ||
10717 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
10721 SDValue N0 = N->getOperand(0);
10723 bool IsNegPow2 = (-Divisor).isPowerOf2();
10724 unsigned Lg2 = (IsNegPow2 ? -Divisor : Divisor).countTrailingZeros();
10725 SDValue ShiftAmt = DAG.getConstant(Lg2, DL, VT);
10727 SDValue Op = DAG.getNode(PPCISD::SRA_ADDZE, DL, VT, N0, ShiftAmt);
10729 Created->push_back(Op.getNode());
10732 Op = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Op);
10734 Created->push_back(Op.getNode());
10740 //===----------------------------------------------------------------------===//
10741 // Inline Assembly Support
10742 //===----------------------------------------------------------------------===//
10744 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
10747 const SelectionDAG &DAG,
10748 unsigned Depth) const {
10749 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
10750 switch (Op.getOpcode()) {
10752 case PPCISD::LBRX: {
10753 // lhbrx is known to have the top bits cleared out.
10754 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
10755 KnownZero = 0xFFFF0000;
10758 case ISD::INTRINSIC_WO_CHAIN: {
10759 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
10761 case Intrinsic::ppc_altivec_vcmpbfp_p:
10762 case Intrinsic::ppc_altivec_vcmpeqfp_p:
10763 case Intrinsic::ppc_altivec_vcmpequb_p:
10764 case Intrinsic::ppc_altivec_vcmpequh_p:
10765 case Intrinsic::ppc_altivec_vcmpequw_p:
10766 case Intrinsic::ppc_altivec_vcmpequd_p:
10767 case Intrinsic::ppc_altivec_vcmpgefp_p:
10768 case Intrinsic::ppc_altivec_vcmpgtfp_p:
10769 case Intrinsic::ppc_altivec_vcmpgtsb_p:
10770 case Intrinsic::ppc_altivec_vcmpgtsh_p:
10771 case Intrinsic::ppc_altivec_vcmpgtsw_p:
10772 case Intrinsic::ppc_altivec_vcmpgtsd_p:
10773 case Intrinsic::ppc_altivec_vcmpgtub_p:
10774 case Intrinsic::ppc_altivec_vcmpgtuh_p:
10775 case Intrinsic::ppc_altivec_vcmpgtuw_p:
10776 case Intrinsic::ppc_altivec_vcmpgtud_p:
10777 KnownZero = ~1U; // All bits but the low one are known to be zero.
10784 unsigned PPCTargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
10785 switch (Subtarget.getDarwinDirective()) {
10788 case PPC::DIR_PWR4:
10789 case PPC::DIR_PWR5:
10790 case PPC::DIR_PWR5X:
10791 case PPC::DIR_PWR6:
10792 case PPC::DIR_PWR6X:
10793 case PPC::DIR_PWR7:
10794 case PPC::DIR_PWR8: {
10798 const PPCInstrInfo *TII = Subtarget.getInstrInfo();
10800 // For small loops (between 5 and 8 instructions), align to a 32-byte
10801 // boundary so that the entire loop fits in one instruction-cache line.
10802 uint64_t LoopSize = 0;
10803 for (auto I = ML->block_begin(), IE = ML->block_end(); I != IE; ++I)
10804 for (auto J = (*I)->begin(), JE = (*I)->end(); J != JE; ++J)
10805 LoopSize += TII->GetInstSizeInBytes(J);
10807 if (LoopSize > 16 && LoopSize <= 32)
10814 return TargetLowering::getPrefLoopAlignment(ML);
10817 /// getConstraintType - Given a constraint, return the type of
10818 /// constraint it is for this target.
10819 PPCTargetLowering::ConstraintType
10820 PPCTargetLowering::getConstraintType(StringRef Constraint) const {
10821 if (Constraint.size() == 1) {
10822 switch (Constraint[0]) {
10829 return C_RegisterClass;
10831 // FIXME: While Z does indicate a memory constraint, it specifically
10832 // indicates an r+r address (used in conjunction with the 'y' modifier
10833 // in the replacement string). Currently, we're forcing the base
10834 // register to be r0 in the asm printer (which is interpreted as zero)
10835 // and forming the complete address in the second register. This is
10839 } else if (Constraint == "wc") { // individual CR bits.
10840 return C_RegisterClass;
10841 } else if (Constraint == "wa" || Constraint == "wd" ||
10842 Constraint == "wf" || Constraint == "ws") {
10843 return C_RegisterClass; // VSX registers.
10845 return TargetLowering::getConstraintType(Constraint);
10848 /// Examine constraint type and operand type and determine a weight value.
10849 /// This object must already have been set up with the operand type
10850 /// and the current alternative constraint selected.
10851 TargetLowering::ConstraintWeight
10852 PPCTargetLowering::getSingleConstraintMatchWeight(
10853 AsmOperandInfo &info, const char *constraint) const {
10854 ConstraintWeight weight = CW_Invalid;
10855 Value *CallOperandVal = info.CallOperandVal;
10856 // If we don't have a value, we can't do a match,
10857 // but allow it at the lowest weight.
10858 if (!CallOperandVal)
10860 Type *type = CallOperandVal->getType();
10862 // Look at the constraint type.
10863 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
10864 return CW_Register; // an individual CR bit.
10865 else if ((StringRef(constraint) == "wa" ||
10866 StringRef(constraint) == "wd" ||
10867 StringRef(constraint) == "wf") &&
10868 type->isVectorTy())
10869 return CW_Register;
10870 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
10871 return CW_Register;
10873 switch (*constraint) {
10875 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
10878 if (type->isIntegerTy())
10879 weight = CW_Register;
10882 if (type->isFloatTy())
10883 weight = CW_Register;
10886 if (type->isDoubleTy())
10887 weight = CW_Register;
10890 if (type->isVectorTy())
10891 weight = CW_Register;
10894 weight = CW_Register;
10897 weight = CW_Memory;
10903 std::pair<unsigned, const TargetRegisterClass *>
10904 PPCTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
10905 StringRef Constraint,
10907 if (Constraint.size() == 1) {
10908 // GCC RS6000 Constraint Letters
10909 switch (Constraint[0]) {
10910 case 'b': // R1-R31
10911 if (VT == MVT::i64 && Subtarget.isPPC64())
10912 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
10913 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
10914 case 'r': // R0-R31
10915 if (VT == MVT::i64 && Subtarget.isPPC64())
10916 return std::make_pair(0U, &PPC::G8RCRegClass);
10917 return std::make_pair(0U, &PPC::GPRCRegClass);
10919 if (VT == MVT::f32 || VT == MVT::i32)
10920 return std::make_pair(0U, &PPC::F4RCRegClass);
10921 if (VT == MVT::f64 || VT == MVT::i64)
10922 return std::make_pair(0U, &PPC::F8RCRegClass);
10923 if (VT == MVT::v4f64 && Subtarget.hasQPX())
10924 return std::make_pair(0U, &PPC::QFRCRegClass);
10925 if (VT == MVT::v4f32 && Subtarget.hasQPX())
10926 return std::make_pair(0U, &PPC::QSRCRegClass);
10929 if (VT == MVT::v4f64 && Subtarget.hasQPX())
10930 return std::make_pair(0U, &PPC::QFRCRegClass);
10931 if (VT == MVT::v4f32 && Subtarget.hasQPX())
10932 return std::make_pair(0U, &PPC::QSRCRegClass);
10933 if (Subtarget.hasAltivec())
10934 return std::make_pair(0U, &PPC::VRRCRegClass);
10936 return std::make_pair(0U, &PPC::CRRCRegClass);
10938 } else if (Constraint == "wc" && Subtarget.useCRBits()) {
10939 // An individual CR bit.
10940 return std::make_pair(0U, &PPC::CRBITRCRegClass);
10941 } else if ((Constraint == "wa" || Constraint == "wd" ||
10942 Constraint == "wf") && Subtarget.hasVSX()) {
10943 return std::make_pair(0U, &PPC::VSRCRegClass);
10944 } else if (Constraint == "ws" && Subtarget.hasVSX()) {
10945 if (VT == MVT::f32 && Subtarget.hasP8Vector())
10946 return std::make_pair(0U, &PPC::VSSRCRegClass);
10948 return std::make_pair(0U, &PPC::VSFRCRegClass);
10951 std::pair<unsigned, const TargetRegisterClass *> R =
10952 TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
10954 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
10955 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
10956 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
10958 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
10959 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
10960 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
10961 PPC::GPRCRegClass.contains(R.first))
10962 return std::make_pair(TRI->getMatchingSuperReg(R.first,
10963 PPC::sub_32, &PPC::G8RCRegClass),
10964 &PPC::G8RCRegClass);
10966 // GCC accepts 'cc' as an alias for 'cr0', and we need to do the same.
10967 if (!R.second && StringRef("{cc}").equals_lower(Constraint)) {
10968 R.first = PPC::CR0;
10969 R.second = &PPC::CRRCRegClass;
10975 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
10976 /// vector. If it is invalid, don't add anything to Ops.
10977 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
10978 std::string &Constraint,
10979 std::vector<SDValue>&Ops,
10980 SelectionDAG &DAG) const {
10983 // Only support length 1 constraints.
10984 if (Constraint.length() > 1) return;
10986 char Letter = Constraint[0];
10997 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
10998 if (!CST) return; // Must be an immediate to match.
11000 int64_t Value = CST->getSExtValue();
11001 EVT TCVT = MVT::i64; // All constants taken to be 64 bits so that negative
11002 // numbers are printed as such.
11004 default: llvm_unreachable("Unknown constraint letter!");
11005 case 'I': // "I" is a signed 16-bit constant.
11006 if (isInt<16>(Value))
11007 Result = DAG.getTargetConstant(Value, dl, TCVT);
11009 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
11010 if (isShiftedUInt<16, 16>(Value))
11011 Result = DAG.getTargetConstant(Value, dl, TCVT);
11013 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
11014 if (isShiftedInt<16, 16>(Value))
11015 Result = DAG.getTargetConstant(Value, dl, TCVT);
11017 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
11018 if (isUInt<16>(Value))
11019 Result = DAG.getTargetConstant(Value, dl, TCVT);
11021 case 'M': // "M" is a constant that is greater than 31.
11023 Result = DAG.getTargetConstant(Value, dl, TCVT);
11025 case 'N': // "N" is a positive constant that is an exact power of two.
11026 if (Value > 0 && isPowerOf2_64(Value))
11027 Result = DAG.getTargetConstant(Value, dl, TCVT);
11029 case 'O': // "O" is the constant zero.
11031 Result = DAG.getTargetConstant(Value, dl, TCVT);
11033 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
11034 if (isInt<16>(-Value))
11035 Result = DAG.getTargetConstant(Value, dl, TCVT);
11042 if (Result.getNode()) {
11043 Ops.push_back(Result);
11047 // Handle standard constraint letters.
11048 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
11051 // isLegalAddressingMode - Return true if the addressing mode represented
11052 // by AM is legal for this target, for a load/store of the specified type.
11053 bool PPCTargetLowering::isLegalAddressingMode(const DataLayout &DL,
11054 const AddrMode &AM, Type *Ty,
11055 unsigned AS) const {
11056 // PPC does not allow r+i addressing modes for vectors!
11057 if (Ty->isVectorTy() && AM.BaseOffs != 0)
11060 // PPC allows a sign-extended 16-bit immediate field.
11061 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
11064 // No global is ever allowed as a base.
11068 // PPC only support r+r,
11069 switch (AM.Scale) {
11070 case 0: // "r+i" or just "i", depending on HasBaseReg.
11073 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
11075 // Otherwise we have r+r or r+i.
11078 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
11080 // Allow 2*r as r+r.
11083 // No other scales are supported.
11090 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
11091 SelectionDAG &DAG) const {
11092 MachineFunction &MF = DAG.getMachineFunction();
11093 MachineFrameInfo *MFI = MF.getFrameInfo();
11094 MFI->setReturnAddressIsTaken(true);
11096 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
11100 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11102 // Make sure the function does not optimize away the store of the RA to
11104 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
11105 FuncInfo->setLRStoreRequired();
11106 bool isPPC64 = Subtarget.isPPC64();
11107 auto PtrVT = getPointerTy(MF.getDataLayout());
11110 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
11112 DAG.getConstant(Subtarget.getFrameLowering()->getReturnSaveOffset(), dl,
11113 isPPC64 ? MVT::i64 : MVT::i32);
11114 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
11115 DAG.getNode(ISD::ADD, dl, PtrVT, FrameAddr, Offset),
11116 MachinePointerInfo(), false, false, false, 0);
11119 // Just load the return address off the stack.
11120 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
11121 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), RetAddrFI,
11122 MachinePointerInfo(), false, false, false, 0);
11125 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
11126 SelectionDAG &DAG) const {
11128 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11130 MachineFunction &MF = DAG.getMachineFunction();
11131 MachineFrameInfo *MFI = MF.getFrameInfo();
11132 MFI->setFrameAddressIsTaken(true);
11134 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
11135 bool isPPC64 = PtrVT == MVT::i64;
11137 // Naked functions never have a frame pointer, and so we use r1. For all
11138 // other functions, this decision must be delayed until during PEI.
11140 if (MF.getFunction()->hasFnAttribute(Attribute::Naked))
11141 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
11143 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
11145 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
11148 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
11149 FrameAddr, MachinePointerInfo(), false, false,
11154 // FIXME? Maybe this could be a TableGen attribute on some registers and
11155 // this table could be generated automatically from RegInfo.
11156 unsigned PPCTargetLowering::getRegisterByName(const char* RegName, EVT VT,
11157 SelectionDAG &DAG) const {
11158 bool isPPC64 = Subtarget.isPPC64();
11159 bool isDarwinABI = Subtarget.isDarwinABI();
11161 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
11162 (!isPPC64 && VT != MVT::i32))
11163 report_fatal_error("Invalid register global variable type");
11165 bool is64Bit = isPPC64 && VT == MVT::i64;
11166 unsigned Reg = StringSwitch<unsigned>(RegName)
11167 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
11168 .Case("r2", (isDarwinABI || isPPC64) ? 0 : PPC::R2)
11169 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
11170 (is64Bit ? PPC::X13 : PPC::R13))
11175 report_fatal_error("Invalid register name global variable");
11179 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
11180 // The PowerPC target isn't yet aware of offsets.
11184 bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
11186 unsigned Intrinsic) const {
11188 switch (Intrinsic) {
11189 case Intrinsic::ppc_qpx_qvlfd:
11190 case Intrinsic::ppc_qpx_qvlfs:
11191 case Intrinsic::ppc_qpx_qvlfcd:
11192 case Intrinsic::ppc_qpx_qvlfcs:
11193 case Intrinsic::ppc_qpx_qvlfiwa:
11194 case Intrinsic::ppc_qpx_qvlfiwz:
11195 case Intrinsic::ppc_altivec_lvx:
11196 case Intrinsic::ppc_altivec_lvxl:
11197 case Intrinsic::ppc_altivec_lvebx:
11198 case Intrinsic::ppc_altivec_lvehx:
11199 case Intrinsic::ppc_altivec_lvewx:
11200 case Intrinsic::ppc_vsx_lxvd2x:
11201 case Intrinsic::ppc_vsx_lxvw4x: {
11203 switch (Intrinsic) {
11204 case Intrinsic::ppc_altivec_lvebx:
11207 case Intrinsic::ppc_altivec_lvehx:
11210 case Intrinsic::ppc_altivec_lvewx:
11213 case Intrinsic::ppc_vsx_lxvd2x:
11216 case Intrinsic::ppc_qpx_qvlfd:
11219 case Intrinsic::ppc_qpx_qvlfs:
11222 case Intrinsic::ppc_qpx_qvlfcd:
11225 case Intrinsic::ppc_qpx_qvlfcs:
11233 Info.opc = ISD::INTRINSIC_W_CHAIN;
11235 Info.ptrVal = I.getArgOperand(0);
11236 Info.offset = -VT.getStoreSize()+1;
11237 Info.size = 2*VT.getStoreSize()-1;
11240 Info.readMem = true;
11241 Info.writeMem = false;
11244 case Intrinsic::ppc_qpx_qvlfda:
11245 case Intrinsic::ppc_qpx_qvlfsa:
11246 case Intrinsic::ppc_qpx_qvlfcda:
11247 case Intrinsic::ppc_qpx_qvlfcsa:
11248 case Intrinsic::ppc_qpx_qvlfiwaa:
11249 case Intrinsic::ppc_qpx_qvlfiwza: {
11251 switch (Intrinsic) {
11252 case Intrinsic::ppc_qpx_qvlfda:
11255 case Intrinsic::ppc_qpx_qvlfsa:
11258 case Intrinsic::ppc_qpx_qvlfcda:
11261 case Intrinsic::ppc_qpx_qvlfcsa:
11269 Info.opc = ISD::INTRINSIC_W_CHAIN;
11271 Info.ptrVal = I.getArgOperand(0);
11273 Info.size = VT.getStoreSize();
11276 Info.readMem = true;
11277 Info.writeMem = false;
11280 case Intrinsic::ppc_qpx_qvstfd:
11281 case Intrinsic::ppc_qpx_qvstfs:
11282 case Intrinsic::ppc_qpx_qvstfcd:
11283 case Intrinsic::ppc_qpx_qvstfcs:
11284 case Intrinsic::ppc_qpx_qvstfiw:
11285 case Intrinsic::ppc_altivec_stvx:
11286 case Intrinsic::ppc_altivec_stvxl:
11287 case Intrinsic::ppc_altivec_stvebx:
11288 case Intrinsic::ppc_altivec_stvehx:
11289 case Intrinsic::ppc_altivec_stvewx:
11290 case Intrinsic::ppc_vsx_stxvd2x:
11291 case Intrinsic::ppc_vsx_stxvw4x: {
11293 switch (Intrinsic) {
11294 case Intrinsic::ppc_altivec_stvebx:
11297 case Intrinsic::ppc_altivec_stvehx:
11300 case Intrinsic::ppc_altivec_stvewx:
11303 case Intrinsic::ppc_vsx_stxvd2x:
11306 case Intrinsic::ppc_qpx_qvstfd:
11309 case Intrinsic::ppc_qpx_qvstfs:
11312 case Intrinsic::ppc_qpx_qvstfcd:
11315 case Intrinsic::ppc_qpx_qvstfcs:
11323 Info.opc = ISD::INTRINSIC_VOID;
11325 Info.ptrVal = I.getArgOperand(1);
11326 Info.offset = -VT.getStoreSize()+1;
11327 Info.size = 2*VT.getStoreSize()-1;
11330 Info.readMem = false;
11331 Info.writeMem = true;
11334 case Intrinsic::ppc_qpx_qvstfda:
11335 case Intrinsic::ppc_qpx_qvstfsa:
11336 case Intrinsic::ppc_qpx_qvstfcda:
11337 case Intrinsic::ppc_qpx_qvstfcsa:
11338 case Intrinsic::ppc_qpx_qvstfiwa: {
11340 switch (Intrinsic) {
11341 case Intrinsic::ppc_qpx_qvstfda:
11344 case Intrinsic::ppc_qpx_qvstfsa:
11347 case Intrinsic::ppc_qpx_qvstfcda:
11350 case Intrinsic::ppc_qpx_qvstfcsa:
11358 Info.opc = ISD::INTRINSIC_VOID;
11360 Info.ptrVal = I.getArgOperand(1);
11362 Info.size = VT.getStoreSize();
11365 Info.readMem = false;
11366 Info.writeMem = true;
11376 /// getOptimalMemOpType - Returns the target specific optimal type for load
11377 /// and store operations as a result of memset, memcpy, and memmove
11378 /// lowering. If DstAlign is zero that means it's safe to destination
11379 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
11380 /// means there isn't a need to check it against alignment requirement,
11381 /// probably because the source does not need to be loaded. If 'IsMemset' is
11382 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
11383 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
11384 /// source is constant so it does not need to be loaded.
11385 /// It returns EVT::Other if the type should be determined using generic
11386 /// target-independent logic.
11387 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
11388 unsigned DstAlign, unsigned SrcAlign,
11389 bool IsMemset, bool ZeroMemset,
11391 MachineFunction &MF) const {
11392 if (getTargetMachine().getOptLevel() != CodeGenOpt::None) {
11393 const Function *F = MF.getFunction();
11394 // When expanding a memset, require at least two QPX instructions to cover
11395 // the cost of loading the value to be stored from the constant pool.
11396 if (Subtarget.hasQPX() && Size >= 32 && (!IsMemset || Size >= 64) &&
11397 (!SrcAlign || SrcAlign >= 32) && (!DstAlign || DstAlign >= 32) &&
11398 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
11402 // We should use Altivec/VSX loads and stores when available. For unaligned
11403 // addresses, unaligned VSX loads are only fast starting with the P8.
11404 if (Subtarget.hasAltivec() && Size >= 16 &&
11405 (((!SrcAlign || SrcAlign >= 16) && (!DstAlign || DstAlign >= 16)) ||
11406 ((IsMemset && Subtarget.hasVSX()) || Subtarget.hasP8Vector())))
11410 if (Subtarget.isPPC64()) {
11417 /// \brief Returns true if it is beneficial to convert a load of a constant
11418 /// to just the constant itself.
11419 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
11421 assert(Ty->isIntegerTy());
11423 unsigned BitSize = Ty->getPrimitiveSizeInBits();
11424 if (BitSize == 0 || BitSize > 64)
11429 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11430 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11432 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11433 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11434 return NumBits1 == 64 && NumBits2 == 32;
11437 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11438 if (!VT1.isInteger() || !VT2.isInteger())
11440 unsigned NumBits1 = VT1.getSizeInBits();
11441 unsigned NumBits2 = VT2.getSizeInBits();
11442 return NumBits1 == 64 && NumBits2 == 32;
11445 bool PPCTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
11446 // Generally speaking, zexts are not free, but they are free when they can be
11447 // folded with other operations.
11448 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Val)) {
11449 EVT MemVT = LD->getMemoryVT();
11450 if ((MemVT == MVT::i1 || MemVT == MVT::i8 || MemVT == MVT::i16 ||
11451 (Subtarget.isPPC64() && MemVT == MVT::i32)) &&
11452 (LD->getExtensionType() == ISD::NON_EXTLOAD ||
11453 LD->getExtensionType() == ISD::ZEXTLOAD))
11457 // FIXME: Add other cases...
11458 // - 32-bit shifts with a zext to i64
11459 // - zext after ctlz, bswap, etc.
11460 // - zext after and by a constant mask
11462 return TargetLowering::isZExtFree(Val, VT2);
11465 bool PPCTargetLowering::isFPExtFree(EVT VT) const {
11466 assert(VT.isFloatingPoint());
11470 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
11471 return isInt<16>(Imm) || isUInt<16>(Imm);
11474 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
11475 return isInt<16>(Imm) || isUInt<16>(Imm);
11478 bool PPCTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
11481 bool *Fast) const {
11482 if (DisablePPCUnaligned)
11485 // PowerPC supports unaligned memory access for simple non-vector types.
11486 // Although accessing unaligned addresses is not as efficient as accessing
11487 // aligned addresses, it is generally more efficient than manual expansion,
11488 // and generally only traps for software emulation when crossing page
11491 if (!VT.isSimple())
11494 if (VT.getSimpleVT().isVector()) {
11495 if (Subtarget.hasVSX()) {
11496 if (VT != MVT::v2f64 && VT != MVT::v2i64 &&
11497 VT != MVT::v4f32 && VT != MVT::v4i32)
11504 if (VT == MVT::ppcf128)
11513 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
11514 VT = VT.getScalarType();
11516 if (!VT.isSimple())
11519 switch (VT.getSimpleVT().SimpleTy) {
11531 PPCTargetLowering::getScratchRegisters(CallingConv::ID) const {
11532 // LR is a callee-save register, but we must treat it as clobbered by any call
11533 // site. Hence we include LR in the scratch registers, which are in turn added
11534 // as implicit-defs for stackmaps and patchpoints. The same reasoning applies
11535 // to CTR, which is used by any indirect call.
11536 static const MCPhysReg ScratchRegs[] = {
11537 PPC::X12, PPC::LR8, PPC::CTR8, 0
11540 return ScratchRegs;
11543 unsigned PPCTargetLowering::getExceptionPointerRegister(
11544 const Constant *PersonalityFn) const {
11545 return Subtarget.isPPC64() ? PPC::X3 : PPC::R3;
11548 unsigned PPCTargetLowering::getExceptionSelectorRegister(
11549 const Constant *PersonalityFn) const {
11550 return Subtarget.isPPC64() ? PPC::X4 : PPC::R4;
11554 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
11555 EVT VT , unsigned DefinedValues) const {
11556 if (VT == MVT::v2i64)
11557 return Subtarget.hasDirectMove(); // Don't need stack ops with direct moves
11559 if (Subtarget.hasQPX()) {
11560 if (VT == MVT::v4f32 || VT == MVT::v4f64 || VT == MVT::v4i1)
11564 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
11567 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
11568 if (DisableILPPref || Subtarget.enableMachineScheduler())
11569 return TargetLowering::getSchedulingPreference(N);
11574 // Create a fast isel object.
11576 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
11577 const TargetLibraryInfo *LibInfo) const {
11578 return PPC::createFastISel(FuncInfo, LibInfo);