1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCCallingConv.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCPerfectShuffle.h"
19 #include "PPCTargetMachine.h"
20 #include "PPCTargetObjectFile.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringSwitch.h"
23 #include "llvm/ADT/Triple.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineLoopInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAG.h"
31 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/Constants.h"
34 #include "llvm/IR/DerivedTypes.h"
35 #include "llvm/IR/Function.h"
36 #include "llvm/IR/Intrinsics.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/Target/TargetOptions.h"
44 // FIXME: Remove this once soft-float is supported.
45 static cl::opt<bool> DisablePPCFloatInVariadic("disable-ppc-float-in-variadic",
46 cl::desc("disable saving float registers for va_start on PPC"), cl::Hidden);
48 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
49 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
51 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
52 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
54 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
55 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
57 // FIXME: Remove this once the bug has been fixed!
58 extern cl::opt<bool> ANDIGlueBug;
60 PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM)
62 Subtarget(*TM.getSubtargetImpl()) {
63 // Use _setjmp/_longjmp instead of setjmp/longjmp.
64 setUseUnderscoreSetJmp(true);
65 setUseUnderscoreLongJmp(true);
67 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
68 // arguments are at least 4/8 bytes aligned.
69 bool isPPC64 = Subtarget.isPPC64();
70 setMinStackArgumentAlignment(isPPC64 ? 8:4);
72 // Set up the register classes.
73 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
74 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
75 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
77 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
78 for (MVT VT : MVT::integer_valuetypes()) {
79 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
80 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
83 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
85 // PowerPC has pre-inc load and store's.
86 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
87 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
91 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
92 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
93 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
97 if (Subtarget.useCRBits()) {
98 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
100 if (isPPC64 || Subtarget.hasFPCVT()) {
101 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
102 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
103 isPPC64 ? MVT::i64 : MVT::i32);
104 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
105 AddPromotedToType (ISD::UINT_TO_FP, MVT::i1,
106 isPPC64 ? MVT::i64 : MVT::i32);
108 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
109 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
112 // PowerPC does not support direct load / store of condition registers
113 setOperationAction(ISD::LOAD, MVT::i1, Custom);
114 setOperationAction(ISD::STORE, MVT::i1, Custom);
116 // FIXME: Remove this once the ANDI glue bug is fixed:
118 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
120 for (MVT VT : MVT::integer_valuetypes()) {
121 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
122 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
123 setTruncStoreAction(VT, MVT::i1, Expand);
126 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
129 // This is used in the ppcf128->int sequence. Note it has different semantics
130 // from FP_ROUND: that rounds to nearest, this rounds to zero.
131 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
133 // We do not currently implement these libm ops for PowerPC.
134 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
135 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
136 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
137 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
138 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
139 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
141 // PowerPC has no SREM/UREM instructions
142 setOperationAction(ISD::SREM, MVT::i32, Expand);
143 setOperationAction(ISD::UREM, MVT::i32, Expand);
144 setOperationAction(ISD::SREM, MVT::i64, Expand);
145 setOperationAction(ISD::UREM, MVT::i64, Expand);
147 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
148 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
149 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
150 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
151 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
152 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
153 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
154 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
155 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
157 // We don't support sin/cos/sqrt/fmod/pow
158 setOperationAction(ISD::FSIN , MVT::f64, Expand);
159 setOperationAction(ISD::FCOS , MVT::f64, Expand);
160 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
161 setOperationAction(ISD::FREM , MVT::f64, Expand);
162 setOperationAction(ISD::FPOW , MVT::f64, Expand);
163 setOperationAction(ISD::FMA , MVT::f64, Legal);
164 setOperationAction(ISD::FSIN , MVT::f32, Expand);
165 setOperationAction(ISD::FCOS , MVT::f32, Expand);
166 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
167 setOperationAction(ISD::FREM , MVT::f32, Expand);
168 setOperationAction(ISD::FPOW , MVT::f32, Expand);
169 setOperationAction(ISD::FMA , MVT::f32, Legal);
171 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
173 // If we're enabling GP optimizations, use hardware square root
174 if (!Subtarget.hasFSQRT() &&
175 !(TM.Options.UnsafeFPMath &&
176 Subtarget.hasFRSQRTE() && Subtarget.hasFRE()))
177 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
179 if (!Subtarget.hasFSQRT() &&
180 !(TM.Options.UnsafeFPMath &&
181 Subtarget.hasFRSQRTES() && Subtarget.hasFRES()))
182 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
184 if (Subtarget.hasFCPSGN()) {
185 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
186 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
188 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
189 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
192 if (Subtarget.hasFPRND()) {
193 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
194 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
195 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
196 setOperationAction(ISD::FROUND, MVT::f64, Legal);
198 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
199 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
200 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
201 setOperationAction(ISD::FROUND, MVT::f32, Legal);
204 // PowerPC does not have BSWAP, CTPOP or CTTZ
205 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
206 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
207 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
208 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
209 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
210 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
211 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
212 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
214 if (Subtarget.hasPOPCNTD()) {
215 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
216 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
218 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
219 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
222 // PowerPC does not have ROTR
223 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
224 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
226 if (!Subtarget.useCRBits()) {
227 // PowerPC does not have Select
228 setOperationAction(ISD::SELECT, MVT::i32, Expand);
229 setOperationAction(ISD::SELECT, MVT::i64, Expand);
230 setOperationAction(ISD::SELECT, MVT::f32, Expand);
231 setOperationAction(ISD::SELECT, MVT::f64, Expand);
234 // PowerPC wants to turn select_cc of FP into fsel when possible.
235 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
236 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
238 // PowerPC wants to optimize integer setcc a bit
239 if (!Subtarget.useCRBits())
240 setOperationAction(ISD::SETCC, MVT::i32, Custom);
242 // PowerPC does not have BRCOND which requires SetCC
243 if (!Subtarget.useCRBits())
244 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
246 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
248 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
249 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
251 // PowerPC does not have [U|S]INT_TO_FP
252 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
253 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
255 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
256 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
257 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
258 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
260 // We cannot sextinreg(i1). Expand to shifts.
261 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
263 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
264 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
265 // support continuation, user-level threading, and etc.. As a result, no
266 // other SjLj exception interfaces are implemented and please don't build
267 // your own exception handling based on them.
268 // LLVM/Clang supports zero-cost DWARF exception handling.
269 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
270 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
272 // We want to legalize GlobalAddress and ConstantPool nodes into the
273 // appropriate instructions to materialize the address.
274 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
275 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
276 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
277 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
278 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
279 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
280 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
281 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
282 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
283 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
286 setOperationAction(ISD::TRAP, MVT::Other, Legal);
288 // TRAMPOLINE is custom lowered.
289 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
290 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
292 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
293 setOperationAction(ISD::VASTART , MVT::Other, Custom);
295 if (Subtarget.isSVR4ABI()) {
297 // VAARG always uses double-word chunks, so promote anything smaller.
298 setOperationAction(ISD::VAARG, MVT::i1, Promote);
299 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
300 setOperationAction(ISD::VAARG, MVT::i8, Promote);
301 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
302 setOperationAction(ISD::VAARG, MVT::i16, Promote);
303 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
304 setOperationAction(ISD::VAARG, MVT::i32, Promote);
305 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
306 setOperationAction(ISD::VAARG, MVT::Other, Expand);
308 // VAARG is custom lowered with the 32-bit SVR4 ABI.
309 setOperationAction(ISD::VAARG, MVT::Other, Custom);
310 setOperationAction(ISD::VAARG, MVT::i64, Custom);
313 setOperationAction(ISD::VAARG, MVT::Other, Expand);
315 if (Subtarget.isSVR4ABI() && !isPPC64)
316 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
317 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
319 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
321 // Use the default implementation.
322 setOperationAction(ISD::VAEND , MVT::Other, Expand);
323 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
324 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
325 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
326 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
328 // We want to custom lower some of our intrinsics.
329 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
331 // To handle counter-based loop conditions.
332 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
334 // Comparisons that require checking two conditions.
335 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
336 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
337 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
338 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
339 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
340 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
341 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
342 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
343 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
344 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
345 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
346 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
348 if (Subtarget.has64BitSupport()) {
349 // They also have instructions for converting between i64 and fp.
350 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
351 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
352 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
353 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
354 // This is just the low 32 bits of a (signed) fp->i64 conversion.
355 // We cannot do this with Promote because i64 is not a legal type.
356 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
358 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
359 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
361 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
362 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
365 // With the instructions enabled under FPCVT, we can do everything.
366 if (Subtarget.hasFPCVT()) {
367 if (Subtarget.has64BitSupport()) {
368 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
369 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
370 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
371 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
374 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
375 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
376 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
377 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
380 if (Subtarget.use64BitRegs()) {
381 // 64-bit PowerPC implementations can support i64 types directly
382 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
383 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
384 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
385 // 64-bit PowerPC wants to expand i128 shifts itself.
386 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
387 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
388 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
390 // 32-bit PowerPC wants to expand i64 shifts itself.
391 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
392 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
393 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
396 if (Subtarget.hasAltivec()) {
397 // First set operation action for all vector types to expand. Then we
398 // will selectively turn on ones that can be effectively codegen'd.
399 for (MVT VT : MVT::vector_valuetypes()) {
400 // add/sub are legal for all supported vector VT's.
401 setOperationAction(ISD::ADD , VT, Legal);
402 setOperationAction(ISD::SUB , VT, Legal);
404 // We promote all shuffles to v16i8.
405 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
406 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
408 // We promote all non-typed operations to v4i32.
409 setOperationAction(ISD::AND , VT, Promote);
410 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
411 setOperationAction(ISD::OR , VT, Promote);
412 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
413 setOperationAction(ISD::XOR , VT, Promote);
414 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
415 setOperationAction(ISD::LOAD , VT, Promote);
416 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
417 setOperationAction(ISD::SELECT, VT, Promote);
418 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
419 setOperationAction(ISD::STORE, VT, Promote);
420 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
422 // No other operations are legal.
423 setOperationAction(ISD::MUL , VT, Expand);
424 setOperationAction(ISD::SDIV, VT, Expand);
425 setOperationAction(ISD::SREM, VT, Expand);
426 setOperationAction(ISD::UDIV, VT, Expand);
427 setOperationAction(ISD::UREM, VT, Expand);
428 setOperationAction(ISD::FDIV, VT, Expand);
429 setOperationAction(ISD::FREM, VT, Expand);
430 setOperationAction(ISD::FNEG, VT, Expand);
431 setOperationAction(ISD::FSQRT, VT, Expand);
432 setOperationAction(ISD::FLOG, VT, Expand);
433 setOperationAction(ISD::FLOG10, VT, Expand);
434 setOperationAction(ISD::FLOG2, VT, Expand);
435 setOperationAction(ISD::FEXP, VT, Expand);
436 setOperationAction(ISD::FEXP2, VT, Expand);
437 setOperationAction(ISD::FSIN, VT, Expand);
438 setOperationAction(ISD::FCOS, VT, Expand);
439 setOperationAction(ISD::FABS, VT, Expand);
440 setOperationAction(ISD::FPOWI, VT, Expand);
441 setOperationAction(ISD::FFLOOR, VT, Expand);
442 setOperationAction(ISD::FCEIL, VT, Expand);
443 setOperationAction(ISD::FTRUNC, VT, Expand);
444 setOperationAction(ISD::FRINT, VT, Expand);
445 setOperationAction(ISD::FNEARBYINT, VT, Expand);
446 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
447 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
448 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
449 setOperationAction(ISD::MULHU, VT, Expand);
450 setOperationAction(ISD::MULHS, VT, Expand);
451 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
452 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
453 setOperationAction(ISD::UDIVREM, VT, Expand);
454 setOperationAction(ISD::SDIVREM, VT, Expand);
455 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
456 setOperationAction(ISD::FPOW, VT, Expand);
457 setOperationAction(ISD::BSWAP, VT, Expand);
458 setOperationAction(ISD::CTPOP, VT, Expand);
459 setOperationAction(ISD::CTLZ, VT, Expand);
460 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
461 setOperationAction(ISD::CTTZ, VT, Expand);
462 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
463 setOperationAction(ISD::VSELECT, VT, Expand);
464 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
466 for (MVT InnerVT : MVT::vector_valuetypes()) {
467 setTruncStoreAction(VT, InnerVT, Expand);
468 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
469 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
470 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
474 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
475 // with merges, splats, etc.
476 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
478 setOperationAction(ISD::AND , MVT::v4i32, Legal);
479 setOperationAction(ISD::OR , MVT::v4i32, Legal);
480 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
481 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
482 setOperationAction(ISD::SELECT, MVT::v4i32,
483 Subtarget.useCRBits() ? Legal : Expand);
484 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
485 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
486 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
487 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
488 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
489 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
490 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
491 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
492 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
494 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
495 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
496 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
497 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
499 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
500 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
502 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
503 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
504 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
507 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
508 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
509 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
511 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
512 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
514 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
515 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
516 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
517 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
519 // Altivec does not contain unordered floating-point compare instructions
520 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
521 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
522 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
523 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
525 if (Subtarget.hasVSX()) {
526 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
527 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
529 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
530 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
531 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
532 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
533 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
535 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
537 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
538 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
540 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
541 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
543 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
544 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
545 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
546 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
547 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
549 // Share the Altivec comparison restrictions.
550 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
551 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
552 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
553 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
555 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
556 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
558 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
560 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
562 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
563 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
565 // VSX v2i64 only supports non-arithmetic operations.
566 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
567 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
569 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
570 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
571 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
573 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
575 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
576 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
577 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
578 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
580 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
582 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
583 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
584 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
585 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
587 // Vector operation legalization checks the result type of
588 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
589 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
590 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
591 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
592 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
594 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
598 if (Subtarget.has64BitSupport())
599 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
601 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
604 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
605 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
608 setBooleanContents(ZeroOrOneBooleanContent);
609 // Altivec instructions set fields to all zeros or all ones.
610 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
613 // These libcalls are not available in 32-bit.
614 setLibcallName(RTLIB::SHL_I128, nullptr);
615 setLibcallName(RTLIB::SRL_I128, nullptr);
616 setLibcallName(RTLIB::SRA_I128, nullptr);
620 setStackPointerRegisterToSaveRestore(PPC::X1);
621 setExceptionPointerRegister(PPC::X3);
622 setExceptionSelectorRegister(PPC::X4);
624 setStackPointerRegisterToSaveRestore(PPC::R1);
625 setExceptionPointerRegister(PPC::R3);
626 setExceptionSelectorRegister(PPC::R4);
629 // We have target-specific dag combine patterns for the following nodes:
630 setTargetDAGCombine(ISD::SINT_TO_FP);
631 if (Subtarget.hasFPCVT())
632 setTargetDAGCombine(ISD::UINT_TO_FP);
633 setTargetDAGCombine(ISD::LOAD);
634 setTargetDAGCombine(ISD::STORE);
635 setTargetDAGCombine(ISD::BR_CC);
636 if (Subtarget.useCRBits())
637 setTargetDAGCombine(ISD::BRCOND);
638 setTargetDAGCombine(ISD::BSWAP);
639 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
640 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
641 setTargetDAGCombine(ISD::INTRINSIC_VOID);
643 setTargetDAGCombine(ISD::SIGN_EXTEND);
644 setTargetDAGCombine(ISD::ZERO_EXTEND);
645 setTargetDAGCombine(ISD::ANY_EXTEND);
647 if (Subtarget.useCRBits()) {
648 setTargetDAGCombine(ISD::TRUNCATE);
649 setTargetDAGCombine(ISD::SETCC);
650 setTargetDAGCombine(ISD::SELECT_CC);
653 // Use reciprocal estimates.
654 if (TM.Options.UnsafeFPMath) {
655 setTargetDAGCombine(ISD::FDIV);
656 setTargetDAGCombine(ISD::FSQRT);
659 // Darwin long double math library functions have $LDBL128 appended.
660 if (Subtarget.isDarwin()) {
661 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
662 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
663 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
664 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
665 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
666 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
667 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
668 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
669 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
670 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
673 // With 32 condition bits, we don't need to sink (and duplicate) compares
674 // aggressively in CodeGenPrep.
675 if (Subtarget.useCRBits())
676 setHasMultipleConditionRegisters();
678 setMinFunctionAlignment(2);
679 if (Subtarget.isDarwin())
680 setPrefFunctionAlignment(4);
682 switch (Subtarget.getDarwinDirective()) {
686 case PPC::DIR_E500mc:
695 setPrefFunctionAlignment(4);
696 setPrefLoopAlignment(4);
700 setInsertFencesForAtomic(true);
702 if (Subtarget.enableMachineScheduler())
703 setSchedulingPreference(Sched::Source);
705 setSchedulingPreference(Sched::Hybrid);
707 computeRegisterProperties();
709 // The Freescale cores do better with aggressive inlining of memcpy and
710 // friends. GCC uses same threshold of 128 bytes (= 32 word stores).
711 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
712 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
713 MaxStoresPerMemset = 32;
714 MaxStoresPerMemsetOptSize = 16;
715 MaxStoresPerMemcpy = 32;
716 MaxStoresPerMemcpyOptSize = 8;
717 MaxStoresPerMemmove = 32;
718 MaxStoresPerMemmoveOptSize = 8;
722 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
723 /// the desired ByVal argument alignment.
724 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
725 unsigned MaxMaxAlign) {
726 if (MaxAlign == MaxMaxAlign)
728 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
729 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
731 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
733 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
734 unsigned EltAlign = 0;
735 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
736 if (EltAlign > MaxAlign)
738 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
739 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
740 unsigned EltAlign = 0;
741 getMaxByValAlign(STy->getElementType(i), EltAlign, MaxMaxAlign);
742 if (EltAlign > MaxAlign)
744 if (MaxAlign == MaxMaxAlign)
750 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
751 /// function arguments in the caller parameter area.
752 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
753 // Darwin passes everything on 4 byte boundary.
754 if (Subtarget.isDarwin())
757 // 16byte and wider vectors are passed on 16byte boundary.
758 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
759 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
760 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
761 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
765 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
767 default: return nullptr;
768 case PPCISD::FSEL: return "PPCISD::FSEL";
769 case PPCISD::FCFID: return "PPCISD::FCFID";
770 case PPCISD::FCFIDU: return "PPCISD::FCFIDU";
771 case PPCISD::FCFIDS: return "PPCISD::FCFIDS";
772 case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS";
773 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
774 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
775 case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ";
776 case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ";
777 case PPCISD::FRE: return "PPCISD::FRE";
778 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
779 case PPCISD::STFIWX: return "PPCISD::STFIWX";
780 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
781 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
782 case PPCISD::VPERM: return "PPCISD::VPERM";
783 case PPCISD::CMPB: return "PPCISD::CMPB";
784 case PPCISD::Hi: return "PPCISD::Hi";
785 case PPCISD::Lo: return "PPCISD::Lo";
786 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
787 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
788 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
789 case PPCISD::SRL: return "PPCISD::SRL";
790 case PPCISD::SRA: return "PPCISD::SRA";
791 case PPCISD::SHL: return "PPCISD::SHL";
792 case PPCISD::CALL: return "PPCISD::CALL";
793 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
794 case PPCISD::CALL_TLS: return "PPCISD::CALL_TLS";
795 case PPCISD::CALL_NOP_TLS: return "PPCISD::CALL_NOP_TLS";
796 case PPCISD::MTCTR: return "PPCISD::MTCTR";
797 case PPCISD::BCTRL: return "PPCISD::BCTRL";
798 case PPCISD::BCTRL_LOAD_TOC: return "PPCISD::BCTRL_LOAD_TOC";
799 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
800 case PPCISD::READ_TIME_BASE: return "PPCISD::READ_TIME_BASE";
801 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
802 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
803 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
804 case PPCISD::VCMP: return "PPCISD::VCMP";
805 case PPCISD::VCMPo: return "PPCISD::VCMPo";
806 case PPCISD::LBRX: return "PPCISD::LBRX";
807 case PPCISD::STBRX: return "PPCISD::STBRX";
808 case PPCISD::LFIWAX: return "PPCISD::LFIWAX";
809 case PPCISD::LFIWZX: return "PPCISD::LFIWZX";
810 case PPCISD::LARX: return "PPCISD::LARX";
811 case PPCISD::STCX: return "PPCISD::STCX";
812 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
813 case PPCISD::BDNZ: return "PPCISD::BDNZ";
814 case PPCISD::BDZ: return "PPCISD::BDZ";
815 case PPCISD::MFFS: return "PPCISD::MFFS";
816 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
817 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
818 case PPCISD::CR6SET: return "PPCISD::CR6SET";
819 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
820 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
821 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
822 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
823 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
824 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
825 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
826 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
827 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
828 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
829 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
830 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
831 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
832 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
833 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
834 case PPCISD::SC: return "PPCISD::SC";
838 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
840 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
841 return VT.changeVectorElementTypeToInteger();
844 bool PPCTargetLowering::enableAggressiveFMAFusion(EVT VT) const {
845 assert(VT.isFloatingPoint() && "Non-floating-point FMA?");
849 //===----------------------------------------------------------------------===//
850 // Node matching predicates, for use by the tblgen matching code.
851 //===----------------------------------------------------------------------===//
853 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
854 static bool isFloatingPointZero(SDValue Op) {
855 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
856 return CFP->getValueAPF().isZero();
857 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
858 // Maybe this has already been legalized into the constant pool?
859 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
860 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
861 return CFP->getValueAPF().isZero();
866 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
867 /// true if Op is undef or if it matches the specified value.
868 static bool isConstantOrUndef(int Op, int Val) {
869 return Op < 0 || Op == Val;
872 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
873 /// VPKUHUM instruction.
874 /// The ShuffleKind distinguishes between big-endian operations with
875 /// two different inputs (0), either-endian operations with two identical
876 /// inputs (1), and little-endian operantion with two different inputs (2).
877 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
878 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
880 bool IsLE = DAG.getSubtarget().getDataLayout()->isLittleEndian();
881 if (ShuffleKind == 0) {
884 for (unsigned i = 0; i != 16; ++i)
885 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
887 } else if (ShuffleKind == 2) {
890 for (unsigned i = 0; i != 16; ++i)
891 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
893 } else if (ShuffleKind == 1) {
894 unsigned j = IsLE ? 0 : 1;
895 for (unsigned i = 0; i != 8; ++i)
896 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
897 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
903 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
904 /// VPKUWUM instruction.
905 /// The ShuffleKind distinguishes between big-endian operations with
906 /// two different inputs (0), either-endian operations with two identical
907 /// inputs (1), and little-endian operantion with two different inputs (2).
908 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
909 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
911 bool IsLE = DAG.getSubtarget().getDataLayout()->isLittleEndian();
912 if (ShuffleKind == 0) {
915 for (unsigned i = 0; i != 16; i += 2)
916 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
917 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
919 } else if (ShuffleKind == 2) {
922 for (unsigned i = 0; i != 16; i += 2)
923 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
924 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
926 } else if (ShuffleKind == 1) {
927 unsigned j = IsLE ? 0 : 2;
928 for (unsigned i = 0; i != 8; i += 2)
929 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
930 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
931 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
932 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
938 /// isVMerge - Common function, used to match vmrg* shuffles.
940 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
941 unsigned LHSStart, unsigned RHSStart) {
942 if (N->getValueType(0) != MVT::v16i8)
944 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
945 "Unsupported merge size!");
947 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
948 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
949 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
950 LHSStart+j+i*UnitSize) ||
951 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
952 RHSStart+j+i*UnitSize))
958 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
959 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
960 /// The ShuffleKind distinguishes between big-endian merges with two
961 /// different inputs (0), either-endian merges with two identical inputs (1),
962 /// and little-endian merges with two different inputs (2). For the latter,
963 /// the input operands are swapped (see PPCInstrAltivec.td).
964 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
965 unsigned ShuffleKind, SelectionDAG &DAG) {
966 if (DAG.getSubtarget().getDataLayout()->isLittleEndian()) {
967 if (ShuffleKind == 1) // unary
968 return isVMerge(N, UnitSize, 0, 0);
969 else if (ShuffleKind == 2) // swapped
970 return isVMerge(N, UnitSize, 0, 16);
974 if (ShuffleKind == 1) // unary
975 return isVMerge(N, UnitSize, 8, 8);
976 else if (ShuffleKind == 0) // normal
977 return isVMerge(N, UnitSize, 8, 24);
983 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
984 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
985 /// The ShuffleKind distinguishes between big-endian merges with two
986 /// different inputs (0), either-endian merges with two identical inputs (1),
987 /// and little-endian merges with two different inputs (2). For the latter,
988 /// the input operands are swapped (see PPCInstrAltivec.td).
989 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
990 unsigned ShuffleKind, SelectionDAG &DAG) {
991 if (DAG.getSubtarget().getDataLayout()->isLittleEndian()) {
992 if (ShuffleKind == 1) // unary
993 return isVMerge(N, UnitSize, 8, 8);
994 else if (ShuffleKind == 2) // swapped
995 return isVMerge(N, UnitSize, 8, 24);
999 if (ShuffleKind == 1) // unary
1000 return isVMerge(N, UnitSize, 0, 0);
1001 else if (ShuffleKind == 0) // normal
1002 return isVMerge(N, UnitSize, 0, 16);
1009 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
1010 /// amount, otherwise return -1.
1011 /// The ShuffleKind distinguishes between big-endian operations with two
1012 /// different inputs (0), either-endian operations with two identical inputs
1013 /// (1), and little-endian operations with two different inputs (2). For the
1014 /// latter, the input operands are swapped (see PPCInstrAltivec.td).
1015 int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
1016 SelectionDAG &DAG) {
1017 if (N->getValueType(0) != MVT::v16i8)
1020 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1022 // Find the first non-undef value in the shuffle mask.
1024 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
1027 if (i == 16) return -1; // all undef.
1029 // Otherwise, check to see if the rest of the elements are consecutively
1030 // numbered from this value.
1031 unsigned ShiftAmt = SVOp->getMaskElt(i);
1032 if (ShiftAmt < i) return -1;
1035 bool isLE = DAG.getTarget().getSubtargetImpl()->getDataLayout()->
1038 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
1039 // Check the rest of the elements to see if they are consecutive.
1040 for (++i; i != 16; ++i)
1041 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1043 } else if (ShuffleKind == 1) {
1044 // Check the rest of the elements to see if they are consecutive.
1045 for (++i; i != 16; ++i)
1046 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1051 if (ShuffleKind == 2 && isLE)
1052 ShiftAmt = 16 - ShiftAmt;
1057 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1058 /// specifies a splat of a single element that is suitable for input to
1059 /// VSPLTB/VSPLTH/VSPLTW.
1060 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1061 assert(N->getValueType(0) == MVT::v16i8 &&
1062 (EltSize == 1 || EltSize == 2 || EltSize == 4));
1064 // This is a splat operation if each element of the permute is the same, and
1065 // if the value doesn't reference the second vector.
1066 unsigned ElementBase = N->getMaskElt(0);
1068 // FIXME: Handle UNDEF elements too!
1069 if (ElementBase >= 16)
1072 // Check that the indices are consecutive, in the case of a multi-byte element
1073 // splatted with a v16i8 mask.
1074 for (unsigned i = 1; i != EltSize; ++i)
1075 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1078 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1079 if (N->getMaskElt(i) < 0) continue;
1080 for (unsigned j = 0; j != EltSize; ++j)
1081 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1087 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
1089 bool PPC::isAllNegativeZeroVector(SDNode *N) {
1090 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
1092 APInt APVal, APUndef;
1096 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
1097 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
1098 return CFP->getValueAPF().isNegZero();
1103 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1104 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1105 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1106 SelectionDAG &DAG) {
1107 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1108 assert(isSplatShuffleMask(SVOp, EltSize));
1109 if (DAG.getSubtarget().getDataLayout()->isLittleEndian())
1110 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1112 return SVOp->getMaskElt(0) / EltSize;
1115 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1116 /// by using a vspltis[bhw] instruction of the specified element size, return
1117 /// the constant being splatted. The ByteSize field indicates the number of
1118 /// bytes of each element [124] -> [bhw].
1119 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1120 SDValue OpVal(nullptr, 0);
1122 // If ByteSize of the splat is bigger than the element size of the
1123 // build_vector, then we have a case where we are checking for a splat where
1124 // multiple elements of the buildvector are folded together into a single
1125 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1126 unsigned EltSize = 16/N->getNumOperands();
1127 if (EltSize < ByteSize) {
1128 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1129 SDValue UniquedVals[4];
1130 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1132 // See if all of the elements in the buildvector agree across.
1133 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1134 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1135 // If the element isn't a constant, bail fully out.
1136 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1139 if (!UniquedVals[i&(Multiple-1)].getNode())
1140 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1141 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1142 return SDValue(); // no match.
1145 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1146 // either constant or undef values that are identical for each chunk. See
1147 // if these chunks can form into a larger vspltis*.
1149 // Check to see if all of the leading entries are either 0 or -1. If
1150 // neither, then this won't fit into the immediate field.
1151 bool LeadingZero = true;
1152 bool LeadingOnes = true;
1153 for (unsigned i = 0; i != Multiple-1; ++i) {
1154 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1156 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
1157 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
1159 // Finally, check the least significant entry.
1161 if (!UniquedVals[Multiple-1].getNode())
1162 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
1163 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1165 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
1168 if (!UniquedVals[Multiple-1].getNode())
1169 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
1170 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1171 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1172 return DAG.getTargetConstant(Val, MVT::i32);
1178 // Check to see if this buildvec has a single non-undef value in its elements.
1179 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1180 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1181 if (!OpVal.getNode())
1182 OpVal = N->getOperand(i);
1183 else if (OpVal != N->getOperand(i))
1187 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1189 unsigned ValSizeInBytes = EltSize;
1191 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1192 Value = CN->getZExtValue();
1193 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1194 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1195 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1198 // If the splat value is larger than the element value, then we can never do
1199 // this splat. The only case that we could fit the replicated bits into our
1200 // immediate field for would be zero, and we prefer to use vxor for it.
1201 if (ValSizeInBytes < ByteSize) return SDValue();
1203 // If the element value is larger than the splat value, cut it in half and
1204 // check to see if the two halves are equal. Continue doing this until we
1205 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
1206 while (ValSizeInBytes > ByteSize) {
1207 ValSizeInBytes >>= 1;
1209 // If the top half equals the bottom half, we're still ok.
1210 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
1211 (Value & ((1 << (8*ValSizeInBytes))-1)))
1215 // Properly sign extend the value.
1216 int MaskVal = SignExtend32(Value, ByteSize * 8);
1218 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1219 if (MaskVal == 0) return SDValue();
1221 // Finally, if this value fits in a 5 bit sext field, return it
1222 if (SignExtend32<5>(MaskVal) == MaskVal)
1223 return DAG.getTargetConstant(MaskVal, MVT::i32);
1227 //===----------------------------------------------------------------------===//
1228 // Addressing Mode Selection
1229 //===----------------------------------------------------------------------===//
1231 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1232 /// or 64-bit immediate, and if the value can be accurately represented as a
1233 /// sign extension from a 16-bit value. If so, this returns true and the
1235 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1236 if (!isa<ConstantSDNode>(N))
1239 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1240 if (N->getValueType(0) == MVT::i32)
1241 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1243 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1245 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1246 return isIntS16Immediate(Op.getNode(), Imm);
1250 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1251 /// can be represented as an indexed [r+r] operation. Returns false if it
1252 /// can be more efficiently represented with [r+imm].
1253 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1255 SelectionDAG &DAG) const {
1257 if (N.getOpcode() == ISD::ADD) {
1258 if (isIntS16Immediate(N.getOperand(1), imm))
1259 return false; // r+i
1260 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1261 return false; // r+i
1263 Base = N.getOperand(0);
1264 Index = N.getOperand(1);
1266 } else if (N.getOpcode() == ISD::OR) {
1267 if (isIntS16Immediate(N.getOperand(1), imm))
1268 return false; // r+i can fold it if we can.
1270 // If this is an or of disjoint bitfields, we can codegen this as an add
1271 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1273 APInt LHSKnownZero, LHSKnownOne;
1274 APInt RHSKnownZero, RHSKnownOne;
1275 DAG.computeKnownBits(N.getOperand(0),
1276 LHSKnownZero, LHSKnownOne);
1278 if (LHSKnownZero.getBoolValue()) {
1279 DAG.computeKnownBits(N.getOperand(1),
1280 RHSKnownZero, RHSKnownOne);
1281 // If all of the bits are known zero on the LHS or RHS, the add won't
1283 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1284 Base = N.getOperand(0);
1285 Index = N.getOperand(1);
1294 // If we happen to be doing an i64 load or store into a stack slot that has
1295 // less than a 4-byte alignment, then the frame-index elimination may need to
1296 // use an indexed load or store instruction (because the offset may not be a
1297 // multiple of 4). The extra register needed to hold the offset comes from the
1298 // register scavenger, and it is possible that the scavenger will need to use
1299 // an emergency spill slot. As a result, we need to make sure that a spill slot
1300 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1302 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1303 // FIXME: This does not handle the LWA case.
1307 // NOTE: We'll exclude negative FIs here, which come from argument
1308 // lowering, because there are no known test cases triggering this problem
1309 // using packed structures (or similar). We can remove this exclusion if
1310 // we find such a test case. The reason why this is so test-case driven is
1311 // because this entire 'fixup' is only to prevent crashes (from the
1312 // register scavenger) on not-really-valid inputs. For example, if we have:
1314 // %b = bitcast i1* %a to i64*
1315 // store i64* a, i64 b
1316 // then the store should really be marked as 'align 1', but is not. If it
1317 // were marked as 'align 1' then the indexed form would have been
1318 // instruction-selected initially, and the problem this 'fixup' is preventing
1319 // won't happen regardless.
1323 MachineFunction &MF = DAG.getMachineFunction();
1324 MachineFrameInfo *MFI = MF.getFrameInfo();
1326 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1330 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1331 FuncInfo->setHasNonRISpills();
1334 /// Returns true if the address N can be represented by a base register plus
1335 /// a signed 16-bit displacement [r+imm], and if it is not better
1336 /// represented as reg+reg. If Aligned is true, only accept displacements
1337 /// suitable for STD and friends, i.e. multiples of 4.
1338 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1341 bool Aligned) const {
1342 // FIXME dl should come from parent load or store, not from address
1344 // If this can be more profitably realized as r+r, fail.
1345 if (SelectAddressRegReg(N, Disp, Base, DAG))
1348 if (N.getOpcode() == ISD::ADD) {
1350 if (isIntS16Immediate(N.getOperand(1), imm) &&
1351 (!Aligned || (imm & 3) == 0)) {
1352 Disp = DAG.getTargetConstant(imm, N.getValueType());
1353 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1354 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1355 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1357 Base = N.getOperand(0);
1359 return true; // [r+i]
1360 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1361 // Match LOAD (ADD (X, Lo(G))).
1362 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1363 && "Cannot handle constant offsets yet!");
1364 Disp = N.getOperand(1).getOperand(0); // The global address.
1365 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1366 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1367 Disp.getOpcode() == ISD::TargetConstantPool ||
1368 Disp.getOpcode() == ISD::TargetJumpTable);
1369 Base = N.getOperand(0);
1370 return true; // [&g+r]
1372 } else if (N.getOpcode() == ISD::OR) {
1374 if (isIntS16Immediate(N.getOperand(1), imm) &&
1375 (!Aligned || (imm & 3) == 0)) {
1376 // If this is an or of disjoint bitfields, we can codegen this as an add
1377 // (for better address arithmetic) if the LHS and RHS of the OR are
1378 // provably disjoint.
1379 APInt LHSKnownZero, LHSKnownOne;
1380 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1382 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1383 // If all of the bits are known zero on the LHS or RHS, the add won't
1385 if (FrameIndexSDNode *FI =
1386 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1387 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1388 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1390 Base = N.getOperand(0);
1392 Disp = DAG.getTargetConstant(imm, N.getValueType());
1396 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1397 // Loading from a constant address.
1399 // If this address fits entirely in a 16-bit sext immediate field, codegen
1402 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1403 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1404 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1405 CN->getValueType(0));
1409 // Handle 32-bit sext immediates with LIS + addr mode.
1410 if ((CN->getValueType(0) == MVT::i32 ||
1411 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1412 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1413 int Addr = (int)CN->getZExtValue();
1415 // Otherwise, break this down into an LIS + disp.
1416 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1418 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1419 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1420 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1425 Disp = DAG.getTargetConstant(0, getPointerTy());
1426 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1427 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1428 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1431 return true; // [r+0]
1434 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1435 /// represented as an indexed [r+r] operation.
1436 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1438 SelectionDAG &DAG) const {
1439 // Check to see if we can easily represent this as an [r+r] address. This
1440 // will fail if it thinks that the address is more profitably represented as
1441 // reg+imm, e.g. where imm = 0.
1442 if (SelectAddressRegReg(N, Base, Index, DAG))
1445 // If the operand is an addition, always emit this as [r+r], since this is
1446 // better (for code size, and execution, as the memop does the add for free)
1447 // than emitting an explicit add.
1448 if (N.getOpcode() == ISD::ADD) {
1449 Base = N.getOperand(0);
1450 Index = N.getOperand(1);
1454 // Otherwise, do it the hard way, using R0 as the base register.
1455 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1461 /// getPreIndexedAddressParts - returns true by value, base pointer and
1462 /// offset pointer and addressing mode by reference if the node's address
1463 /// can be legally represented as pre-indexed load / store address.
1464 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1466 ISD::MemIndexedMode &AM,
1467 SelectionDAG &DAG) const {
1468 if (DisablePPCPreinc) return false;
1474 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1475 Ptr = LD->getBasePtr();
1476 VT = LD->getMemoryVT();
1477 Alignment = LD->getAlignment();
1478 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1479 Ptr = ST->getBasePtr();
1480 VT = ST->getMemoryVT();
1481 Alignment = ST->getAlignment();
1486 // PowerPC doesn't have preinc load/store instructions for vectors.
1490 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1492 // Common code will reject creating a pre-inc form if the base pointer
1493 // is a frame index, or if N is a store and the base pointer is either
1494 // the same as or a predecessor of the value being stored. Check for
1495 // those situations here, and try with swapped Base/Offset instead.
1498 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1501 SDValue Val = cast<StoreSDNode>(N)->getValue();
1502 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1507 std::swap(Base, Offset);
1513 // LDU/STU can only handle immediates that are a multiple of 4.
1514 if (VT != MVT::i64) {
1515 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1518 // LDU/STU need an address with at least 4-byte alignment.
1522 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1526 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1527 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1528 // sext i32 to i64 when addr mode is r+i.
1529 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1530 LD->getExtensionType() == ISD::SEXTLOAD &&
1531 isa<ConstantSDNode>(Offset))
1539 //===----------------------------------------------------------------------===//
1540 // LowerOperation implementation
1541 //===----------------------------------------------------------------------===//
1543 /// GetLabelAccessInfo - Return true if we should reference labels using a
1544 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1545 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1546 unsigned &LoOpFlags,
1547 const GlobalValue *GV = nullptr) {
1548 HiOpFlags = PPCII::MO_HA;
1549 LoOpFlags = PPCII::MO_LO;
1551 // Don't use the pic base if not in PIC relocation model.
1552 bool isPIC = TM.getRelocationModel() == Reloc::PIC_;
1555 HiOpFlags |= PPCII::MO_PIC_FLAG;
1556 LoOpFlags |= PPCII::MO_PIC_FLAG;
1559 // If this is a reference to a global value that requires a non-lazy-ptr, make
1560 // sure that instruction lowering adds it.
1561 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1562 HiOpFlags |= PPCII::MO_NLP_FLAG;
1563 LoOpFlags |= PPCII::MO_NLP_FLAG;
1565 if (GV->hasHiddenVisibility()) {
1566 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1567 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1574 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1575 SelectionDAG &DAG) {
1576 EVT PtrVT = HiPart.getValueType();
1577 SDValue Zero = DAG.getConstant(0, PtrVT);
1580 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1581 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1583 // With PIC, the first instruction is actually "GR+hi(&G)".
1585 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1586 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1588 // Generate non-pic code that has direct accesses to the constant pool.
1589 // The address of the global is just (hi(&g)+lo(&g)).
1590 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1593 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1594 SelectionDAG &DAG) const {
1595 EVT PtrVT = Op.getValueType();
1596 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1597 const Constant *C = CP->getConstVal();
1599 // 64-bit SVR4 ABI code is always position-independent.
1600 // The actual address of the GlobalValue is stored in the TOC.
1601 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1602 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1603 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1604 DAG.getRegister(PPC::X2, MVT::i64));
1607 unsigned MOHiFlag, MOLoFlag;
1608 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1610 if (isPIC && Subtarget.isSVR4ABI()) {
1611 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
1612 PPCII::MO_PIC_FLAG);
1614 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1615 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1619 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1621 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1622 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1625 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1626 EVT PtrVT = Op.getValueType();
1627 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1629 // 64-bit SVR4 ABI code is always position-independent.
1630 // The actual address of the GlobalValue is stored in the TOC.
1631 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1632 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1633 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1634 DAG.getRegister(PPC::X2, MVT::i64));
1637 unsigned MOHiFlag, MOLoFlag;
1638 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1640 if (isPIC && Subtarget.isSVR4ABI()) {
1641 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
1642 PPCII::MO_PIC_FLAG);
1644 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), PtrVT, GA,
1645 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1648 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1649 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1650 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1653 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1654 SelectionDAG &DAG) const {
1655 EVT PtrVT = Op.getValueType();
1656 BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
1657 const BlockAddress *BA = BASDN->getBlockAddress();
1659 // 64-bit SVR4 ABI code is always position-independent.
1660 // The actual BlockAddress is stored in the TOC.
1661 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1662 SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
1663 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(BASDN), MVT::i64, GA,
1664 DAG.getRegister(PPC::X2, MVT::i64));
1667 unsigned MOHiFlag, MOLoFlag;
1668 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1669 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1670 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1671 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1674 // Generate a call to __tls_get_addr for the given GOT entry Op.
1675 std::pair<SDValue,SDValue>
1676 PPCTargetLowering::lowerTLSCall(SDValue Op, SDLoc dl,
1677 SelectionDAG &DAG) const {
1679 Type *IntPtrTy = getDataLayout()->getIntPtrType(*DAG.getContext());
1680 TargetLowering::ArgListTy Args;
1681 TargetLowering::ArgListEntry Entry;
1683 Entry.Ty = IntPtrTy;
1684 Args.push_back(Entry);
1686 TargetLowering::CallLoweringInfo CLI(DAG);
1687 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
1688 .setCallee(CallingConv::C, IntPtrTy,
1689 DAG.getTargetExternalSymbol("__tls_get_addr", getPointerTy()),
1690 std::move(Args), 0);
1692 return LowerCallTo(CLI);
1695 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1696 SelectionDAG &DAG) const {
1698 // FIXME: TLS addresses currently use medium model code sequences,
1699 // which is the most useful form. Eventually support for small and
1700 // large models could be added if users need it, at the cost of
1701 // additional complexity.
1702 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1704 const GlobalValue *GV = GA->getGlobal();
1705 EVT PtrVT = getPointerTy();
1706 bool is64bit = Subtarget.isPPC64();
1707 const Module *M = DAG.getMachineFunction().getFunction()->getParent();
1708 PICLevel::Level picLevel = M->getPICLevel();
1710 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1712 if (Model == TLSModel::LocalExec) {
1713 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1714 PPCII::MO_TPREL_HA);
1715 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1716 PPCII::MO_TPREL_LO);
1717 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1718 is64bit ? MVT::i64 : MVT::i32);
1719 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1720 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1723 if (Model == TLSModel::InitialExec) {
1724 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1725 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1729 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1730 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1731 PtrVT, GOTReg, TGA);
1733 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
1734 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1735 PtrVT, TGA, GOTPtr);
1736 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
1739 if (Model == TLSModel::GeneralDynamic) {
1740 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1744 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1745 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1748 if (picLevel == PICLevel::Small)
1749 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
1751 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
1753 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1755 std::pair<SDValue, SDValue> CallResult = lowerTLSCall(GOTEntry, dl, DAG);
1756 return CallResult.first;
1759 if (Model == TLSModel::LocalDynamic) {
1760 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1764 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1765 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1768 if (picLevel == PICLevel::Small)
1769 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
1771 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
1773 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1775 std::pair<SDValue, SDValue> CallResult = lowerTLSCall(GOTEntry, dl, DAG);
1776 SDValue TLSAddr = CallResult.first;
1777 SDValue Chain = CallResult.second;
1778 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1779 Chain, TLSAddr, TGA);
1780 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1783 llvm_unreachable("Unknown TLS model!");
1786 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1787 SelectionDAG &DAG) const {
1788 EVT PtrVT = Op.getValueType();
1789 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1791 const GlobalValue *GV = GSDN->getGlobal();
1793 // 64-bit SVR4 ABI code is always position-independent.
1794 // The actual address of the GlobalValue is stored in the TOC.
1795 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1796 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1797 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1798 DAG.getRegister(PPC::X2, MVT::i64));
1801 unsigned MOHiFlag, MOLoFlag;
1802 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1804 if (isPIC && Subtarget.isSVR4ABI()) {
1805 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
1807 PPCII::MO_PIC_FLAG);
1808 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1809 DAG.getNode(PPCISD::GlobalBaseReg, DL, MVT::i32));
1813 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1815 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1817 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1819 // If the global reference is actually to a non-lazy-pointer, we have to do an
1820 // extra load to get the address of the global.
1821 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1822 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1823 false, false, false, 0);
1827 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1828 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1831 if (Op.getValueType() == MVT::v2i64) {
1832 // When the operands themselves are v2i64 values, we need to do something
1833 // special because VSX has no underlying comparison operations for these.
1834 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
1835 // Equality can be handled by casting to the legal type for Altivec
1836 // comparisons, everything else needs to be expanded.
1837 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1838 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
1839 DAG.getSetCC(dl, MVT::v4i32,
1840 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
1841 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
1848 // We handle most of these in the usual way.
1852 // If we're comparing for equality to zero, expose the fact that this is
1853 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1854 // fold the new nodes.
1855 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1856 if (C->isNullValue() && CC == ISD::SETEQ) {
1857 EVT VT = Op.getOperand(0).getValueType();
1858 SDValue Zext = Op.getOperand(0);
1859 if (VT.bitsLT(MVT::i32)) {
1861 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1863 unsigned Log2b = Log2_32(VT.getSizeInBits());
1864 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1865 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1866 DAG.getConstant(Log2b, MVT::i32));
1867 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1869 // Leave comparisons against 0 and -1 alone for now, since they're usually
1870 // optimized. FIXME: revisit this when we can custom lower all setcc
1872 if (C->isAllOnesValue() || C->isNullValue())
1876 // If we have an integer seteq/setne, turn it into a compare against zero
1877 // by xor'ing the rhs with the lhs, which is faster than setting a
1878 // condition register, reading it back out, and masking the correct bit. The
1879 // normal approach here uses sub to do this instead of xor. Using xor exposes
1880 // the result to other bit-twiddling opportunities.
1881 EVT LHSVT = Op.getOperand(0).getValueType();
1882 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1883 EVT VT = Op.getValueType();
1884 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1886 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1891 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1892 const PPCSubtarget &Subtarget) const {
1893 SDNode *Node = Op.getNode();
1894 EVT VT = Node->getValueType(0);
1895 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1896 SDValue InChain = Node->getOperand(0);
1897 SDValue VAListPtr = Node->getOperand(1);
1898 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1901 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1904 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1905 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1906 false, false, false, 0);
1907 InChain = GprIndex.getValue(1);
1909 if (VT == MVT::i64) {
1910 // Check if GprIndex is even
1911 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1912 DAG.getConstant(1, MVT::i32));
1913 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1914 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1915 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1916 DAG.getConstant(1, MVT::i32));
1917 // Align GprIndex to be even if it isn't
1918 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1922 // fpr index is 1 byte after gpr
1923 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1924 DAG.getConstant(1, MVT::i32));
1927 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1928 FprPtr, MachinePointerInfo(SV), MVT::i8,
1929 false, false, false, 0);
1930 InChain = FprIndex.getValue(1);
1932 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1933 DAG.getConstant(8, MVT::i32));
1935 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1936 DAG.getConstant(4, MVT::i32));
1939 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1940 MachinePointerInfo(), false, false,
1942 InChain = OverflowArea.getValue(1);
1944 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1945 MachinePointerInfo(), false, false,
1947 InChain = RegSaveArea.getValue(1);
1949 // select overflow_area if index > 8
1950 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1951 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1953 // adjustment constant gpr_index * 4/8
1954 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1955 VT.isInteger() ? GprIndex : FprIndex,
1956 DAG.getConstant(VT.isInteger() ? 4 : 8,
1959 // OurReg = RegSaveArea + RegConstant
1960 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1963 // Floating types are 32 bytes into RegSaveArea
1964 if (VT.isFloatingPoint())
1965 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1966 DAG.getConstant(32, MVT::i32));
1968 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1969 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1970 VT.isInteger() ? GprIndex : FprIndex,
1971 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1974 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1975 VT.isInteger() ? VAListPtr : FprPtr,
1976 MachinePointerInfo(SV),
1977 MVT::i8, false, false, 0);
1979 // determine if we should load from reg_save_area or overflow_area
1980 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1982 // increase overflow_area by 4/8 if gpr/fpr > 8
1983 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1984 DAG.getConstant(VT.isInteger() ? 4 : 8,
1987 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1990 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1992 MachinePointerInfo(),
1993 MVT::i32, false, false, 0);
1995 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1996 false, false, false, 0);
1999 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
2000 const PPCSubtarget &Subtarget) const {
2001 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
2003 // We have to copy the entire va_list struct:
2004 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
2005 return DAG.getMemcpy(Op.getOperand(0), Op,
2006 Op.getOperand(1), Op.getOperand(2),
2007 DAG.getConstant(12, MVT::i32), 8, false, true,
2008 MachinePointerInfo(), MachinePointerInfo());
2011 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
2012 SelectionDAG &DAG) const {
2013 return Op.getOperand(0);
2016 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
2017 SelectionDAG &DAG) const {
2018 SDValue Chain = Op.getOperand(0);
2019 SDValue Trmp = Op.getOperand(1); // trampoline
2020 SDValue FPtr = Op.getOperand(2); // nested function
2021 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
2024 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2025 bool isPPC64 = (PtrVT == MVT::i64);
2027 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
2030 TargetLowering::ArgListTy Args;
2031 TargetLowering::ArgListEntry Entry;
2033 Entry.Ty = IntPtrTy;
2034 Entry.Node = Trmp; Args.push_back(Entry);
2036 // TrampSize == (isPPC64 ? 48 : 40);
2037 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
2038 isPPC64 ? MVT::i64 : MVT::i32);
2039 Args.push_back(Entry);
2041 Entry.Node = FPtr; Args.push_back(Entry);
2042 Entry.Node = Nest; Args.push_back(Entry);
2044 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
2045 TargetLowering::CallLoweringInfo CLI(DAG);
2046 CLI.setDebugLoc(dl).setChain(Chain)
2047 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
2048 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
2049 std::move(Args), 0);
2051 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2052 return CallResult.second;
2055 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
2056 const PPCSubtarget &Subtarget) const {
2057 MachineFunction &MF = DAG.getMachineFunction();
2058 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2062 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
2063 // vastart just stores the address of the VarArgsFrameIndex slot into the
2064 // memory location argument.
2065 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2066 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2067 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2068 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2069 MachinePointerInfo(SV),
2073 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
2074 // We suppose the given va_list is already allocated.
2077 // char gpr; /* index into the array of 8 GPRs
2078 // * stored in the register save area
2079 // * gpr=0 corresponds to r3,
2080 // * gpr=1 to r4, etc.
2082 // char fpr; /* index into the array of 8 FPRs
2083 // * stored in the register save area
2084 // * fpr=0 corresponds to f1,
2085 // * fpr=1 to f2, etc.
2087 // char *overflow_arg_area;
2088 // /* location on stack that holds
2089 // * the next overflow argument
2091 // char *reg_save_area;
2092 // /* where r3:r10 and f1:f8 (if saved)
2098 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
2099 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
2102 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2104 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
2106 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2109 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2110 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
2112 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2113 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
2115 uint64_t FPROffset = 1;
2116 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
2118 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2120 // Store first byte : number of int regs
2121 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
2123 MachinePointerInfo(SV),
2124 MVT::i8, false, false, 0);
2125 uint64_t nextOffset = FPROffset;
2126 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2129 // Store second byte : number of float regs
2130 SDValue secondStore =
2131 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2132 MachinePointerInfo(SV, nextOffset), MVT::i8,
2134 nextOffset += StackOffset;
2135 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2137 // Store second word : arguments given on stack
2138 SDValue thirdStore =
2139 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2140 MachinePointerInfo(SV, nextOffset),
2142 nextOffset += FrameOffset;
2143 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2145 // Store third word : arguments given in registers
2146 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2147 MachinePointerInfo(SV, nextOffset),
2152 #include "PPCGenCallingConv.inc"
2154 // Function whose sole purpose is to kill compiler warnings
2155 // stemming from unused functions included from PPCGenCallingConv.inc.
2156 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2157 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2160 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2161 CCValAssign::LocInfo &LocInfo,
2162 ISD::ArgFlagsTy &ArgFlags,
2167 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2169 CCValAssign::LocInfo &LocInfo,
2170 ISD::ArgFlagsTy &ArgFlags,
2172 static const MCPhysReg ArgRegs[] = {
2173 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2174 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2176 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2178 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2180 // Skip one register if the first unallocated register has an even register
2181 // number and there are still argument registers available which have not been
2182 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2183 // need to skip a register if RegNum is odd.
2184 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2185 State.AllocateReg(ArgRegs[RegNum]);
2188 // Always return false here, as this function only makes sure that the first
2189 // unallocated register has an odd register number and does not actually
2190 // allocate a register for the current argument.
2194 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2196 CCValAssign::LocInfo &LocInfo,
2197 ISD::ArgFlagsTy &ArgFlags,
2199 static const MCPhysReg ArgRegs[] = {
2200 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2204 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2206 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2208 // If there is only one Floating-point register left we need to put both f64
2209 // values of a split ppc_fp128 value on the stack.
2210 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2211 State.AllocateReg(ArgRegs[RegNum]);
2214 // Always return false here, as this function only makes sure that the two f64
2215 // values a ppc_fp128 value is split into are both passed in registers or both
2216 // passed on the stack and does not actually allocate a register for the
2217 // current argument.
2221 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
2223 static const MCPhysReg *GetFPR() {
2224 static const MCPhysReg FPR[] = {
2225 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2226 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
2232 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2234 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2235 unsigned PtrByteSize) {
2236 unsigned ArgSize = ArgVT.getStoreSize();
2237 if (Flags.isByVal())
2238 ArgSize = Flags.getByValSize();
2240 // Round up to multiples of the pointer size, except for array members,
2241 // which are always packed.
2242 if (!Flags.isInConsecutiveRegs())
2243 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2248 /// CalculateStackSlotAlignment - Calculates the alignment of this argument
2250 static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
2251 ISD::ArgFlagsTy Flags,
2252 unsigned PtrByteSize) {
2253 unsigned Align = PtrByteSize;
2255 // Altivec parameters are padded to a 16 byte boundary.
2256 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2257 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2258 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2261 // ByVal parameters are aligned as requested.
2262 if (Flags.isByVal()) {
2263 unsigned BVAlign = Flags.getByValAlign();
2264 if (BVAlign > PtrByteSize) {
2265 if (BVAlign % PtrByteSize != 0)
2267 "ByVal alignment is not a multiple of the pointer size");
2273 // Array members are always packed to their original alignment.
2274 if (Flags.isInConsecutiveRegs()) {
2275 // If the array member was split into multiple registers, the first
2276 // needs to be aligned to the size of the full type. (Except for
2277 // ppcf128, which is only aligned as its f64 components.)
2278 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
2279 Align = OrigVT.getStoreSize();
2281 Align = ArgVT.getStoreSize();
2287 /// CalculateStackSlotUsed - Return whether this argument will use its
2288 /// stack slot (instead of being passed in registers). ArgOffset,
2289 /// AvailableFPRs, and AvailableVRs must hold the current argument
2290 /// position, and will be updated to account for this argument.
2291 static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT,
2292 ISD::ArgFlagsTy Flags,
2293 unsigned PtrByteSize,
2294 unsigned LinkageSize,
2295 unsigned ParamAreaSize,
2296 unsigned &ArgOffset,
2297 unsigned &AvailableFPRs,
2298 unsigned &AvailableVRs) {
2299 bool UseMemory = false;
2301 // Respect alignment of argument on the stack.
2303 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
2304 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2305 // If there's no space left in the argument save area, we must
2306 // use memory (this check also catches zero-sized arguments).
2307 if (ArgOffset >= LinkageSize + ParamAreaSize)
2310 // Allocate argument on the stack.
2311 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2312 if (Flags.isInConsecutiveRegsLast())
2313 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2314 // If we overran the argument save area, we must use memory
2315 // (this check catches arguments passed partially in memory)
2316 if (ArgOffset > LinkageSize + ParamAreaSize)
2319 // However, if the argument is actually passed in an FPR or a VR,
2320 // we don't use memory after all.
2321 if (!Flags.isByVal()) {
2322 if (ArgVT == MVT::f32 || ArgVT == MVT::f64)
2323 if (AvailableFPRs > 0) {
2327 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2328 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2329 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2330 if (AvailableVRs > 0) {
2339 /// EnsureStackAlignment - Round stack frame size up from NumBytes to
2340 /// ensure minimum alignment required for target.
2341 static unsigned EnsureStackAlignment(const TargetMachine &Target,
2342 unsigned NumBytes) {
2343 unsigned TargetAlign =
2344 Target.getSubtargetImpl()->getFrameLowering()->getStackAlignment();
2345 unsigned AlignMask = TargetAlign - 1;
2346 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2351 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
2352 CallingConv::ID CallConv, bool isVarArg,
2353 const SmallVectorImpl<ISD::InputArg>
2355 SDLoc dl, SelectionDAG &DAG,
2356 SmallVectorImpl<SDValue> &InVals)
2358 if (Subtarget.isSVR4ABI()) {
2359 if (Subtarget.isPPC64())
2360 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2363 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2366 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2372 PPCTargetLowering::LowerFormalArguments_32SVR4(
2374 CallingConv::ID CallConv, bool isVarArg,
2375 const SmallVectorImpl<ISD::InputArg>
2377 SDLoc dl, SelectionDAG &DAG,
2378 SmallVectorImpl<SDValue> &InVals) const {
2380 // 32-bit SVR4 ABI Stack Frame Layout:
2381 // +-----------------------------------+
2382 // +--> | Back chain |
2383 // | +-----------------------------------+
2384 // | | Floating-point register save area |
2385 // | +-----------------------------------+
2386 // | | General register save area |
2387 // | +-----------------------------------+
2388 // | | CR save word |
2389 // | +-----------------------------------+
2390 // | | VRSAVE save word |
2391 // | +-----------------------------------+
2392 // | | Alignment padding |
2393 // | +-----------------------------------+
2394 // | | Vector register save area |
2395 // | +-----------------------------------+
2396 // | | Local variable space |
2397 // | +-----------------------------------+
2398 // | | Parameter list area |
2399 // | +-----------------------------------+
2400 // | | LR save word |
2401 // | +-----------------------------------+
2402 // SP--> +--- | Back chain |
2403 // +-----------------------------------+
2406 // System V Application Binary Interface PowerPC Processor Supplement
2407 // AltiVec Technology Programming Interface Manual
2409 MachineFunction &MF = DAG.getMachineFunction();
2410 MachineFrameInfo *MFI = MF.getFrameInfo();
2411 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2413 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2414 // Potential tail calls could cause overwriting of argument stack slots.
2415 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2416 (CallConv == CallingConv::Fast));
2417 unsigned PtrByteSize = 4;
2419 // Assign locations to all of the incoming arguments.
2420 SmallVector<CCValAssign, 16> ArgLocs;
2421 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2424 // Reserve space for the linkage area on the stack.
2425 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(false, false, false);
2426 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
2428 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2430 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2431 CCValAssign &VA = ArgLocs[i];
2433 // Arguments stored in registers.
2434 if (VA.isRegLoc()) {
2435 const TargetRegisterClass *RC;
2436 EVT ValVT = VA.getValVT();
2438 switch (ValVT.getSimpleVT().SimpleTy) {
2440 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2443 RC = &PPC::GPRCRegClass;
2446 RC = &PPC::F4RCRegClass;
2449 if (Subtarget.hasVSX())
2450 RC = &PPC::VSFRCRegClass;
2452 RC = &PPC::F8RCRegClass;
2458 RC = &PPC::VRRCRegClass;
2462 RC = &PPC::VSHRCRegClass;
2466 // Transform the arguments stored in physical registers into virtual ones.
2467 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2468 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2469 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2471 if (ValVT == MVT::i1)
2472 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2474 InVals.push_back(ArgValue);
2476 // Argument stored in memory.
2477 assert(VA.isMemLoc());
2479 unsigned ArgSize = VA.getLocVT().getStoreSize();
2480 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2483 // Create load nodes to retrieve arguments from the stack.
2484 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2485 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2486 MachinePointerInfo(),
2487 false, false, false, 0));
2491 // Assign locations to all of the incoming aggregate by value arguments.
2492 // Aggregates passed by value are stored in the local variable space of the
2493 // caller's stack frame, right above the parameter list area.
2494 SmallVector<CCValAssign, 16> ByValArgLocs;
2495 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2496 ByValArgLocs, *DAG.getContext());
2498 // Reserve stack space for the allocations in CCInfo.
2499 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2501 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2503 // Area that is at least reserved in the caller of this function.
2504 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2505 MinReservedArea = std::max(MinReservedArea, LinkageSize);
2507 // Set the size that is at least reserved in caller of this function. Tail
2508 // call optimized function's reserved stack space needs to be aligned so that
2509 // taking the difference between two stack areas will result in an aligned
2511 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2512 FuncInfo->setMinReservedArea(MinReservedArea);
2514 SmallVector<SDValue, 8> MemOps;
2516 // If the function takes variable number of arguments, make a frame index for
2517 // the start of the first vararg value... for expansion of llvm.va_start.
2519 static const MCPhysReg GPArgRegs[] = {
2520 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2521 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2523 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2525 static const MCPhysReg FPArgRegs[] = {
2526 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2529 unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2530 if (DisablePPCFloatInVariadic)
2533 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2535 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2538 // Make room for NumGPArgRegs and NumFPArgRegs.
2539 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2540 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8;
2542 FuncInfo->setVarArgsStackOffset(
2543 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2544 CCInfo.getNextStackOffset(), true));
2546 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2547 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2549 // The fixed integer arguments of a variadic function are stored to the
2550 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2551 // the result of va_next.
2552 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2553 // Get an existing live-in vreg, or add a new one.
2554 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2556 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2558 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2559 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2560 MachinePointerInfo(), false, false, 0);
2561 MemOps.push_back(Store);
2562 // Increment the address by four for the next argument to store
2563 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2564 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2567 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2569 // The double arguments are stored to the VarArgsFrameIndex
2571 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2572 // Get an existing live-in vreg, or add a new one.
2573 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2575 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2577 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2578 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2579 MachinePointerInfo(), false, false, 0);
2580 MemOps.push_back(Store);
2581 // Increment the address by eight for the next argument to store
2582 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8,
2584 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2588 if (!MemOps.empty())
2589 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2594 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2595 // value to MVT::i64 and then truncate to the correct register size.
2597 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2598 SelectionDAG &DAG, SDValue ArgVal,
2601 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2602 DAG.getValueType(ObjectVT));
2603 else if (Flags.isZExt())
2604 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2605 DAG.getValueType(ObjectVT));
2607 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
2611 PPCTargetLowering::LowerFormalArguments_64SVR4(
2613 CallingConv::ID CallConv, bool isVarArg,
2614 const SmallVectorImpl<ISD::InputArg>
2616 SDLoc dl, SelectionDAG &DAG,
2617 SmallVectorImpl<SDValue> &InVals) const {
2618 // TODO: add description of PPC stack frame format, or at least some docs.
2620 bool isELFv2ABI = Subtarget.isELFv2ABI();
2621 bool isLittleEndian = Subtarget.isLittleEndian();
2622 MachineFunction &MF = DAG.getMachineFunction();
2623 MachineFrameInfo *MFI = MF.getFrameInfo();
2624 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2626 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2627 // Potential tail calls could cause overwriting of argument stack slots.
2628 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2629 (CallConv == CallingConv::Fast));
2630 unsigned PtrByteSize = 8;
2632 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
2635 static const MCPhysReg GPR[] = {
2636 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2637 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2640 static const MCPhysReg *FPR = GetFPR();
2642 static const MCPhysReg VR[] = {
2643 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2644 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2646 static const MCPhysReg VSRH[] = {
2647 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
2648 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
2651 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2652 const unsigned Num_FPR_Regs = 13;
2653 const unsigned Num_VR_Regs = array_lengthof(VR);
2655 // Do a first pass over the arguments to determine whether the ABI
2656 // guarantees that our caller has allocated the parameter save area
2657 // on its stack frame. In the ELFv1 ABI, this is always the case;
2658 // in the ELFv2 ABI, it is true if this is a vararg function or if
2659 // any parameter is located in a stack slot.
2661 bool HasParameterArea = !isELFv2ABI || isVarArg;
2662 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
2663 unsigned NumBytes = LinkageSize;
2664 unsigned AvailableFPRs = Num_FPR_Regs;
2665 unsigned AvailableVRs = Num_VR_Regs;
2666 for (unsigned i = 0, e = Ins.size(); i != e; ++i)
2667 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
2668 PtrByteSize, LinkageSize, ParamAreaSize,
2669 NumBytes, AvailableFPRs, AvailableVRs))
2670 HasParameterArea = true;
2672 // Add DAG nodes to load the arguments or copy them out of registers. On
2673 // entry to a function on PPC, the arguments start after the linkage area,
2674 // although the first ones are often in registers.
2676 unsigned ArgOffset = LinkageSize;
2677 unsigned GPR_idx, FPR_idx = 0, VR_idx = 0;
2678 SmallVector<SDValue, 8> MemOps;
2679 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2680 unsigned CurArgIdx = 0;
2681 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2683 bool needsLoad = false;
2684 EVT ObjectVT = Ins[ArgNo].VT;
2685 EVT OrigVT = Ins[ArgNo].ArgVT;
2686 unsigned ObjSize = ObjectVT.getStoreSize();
2687 unsigned ArgSize = ObjSize;
2688 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2689 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2690 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2692 /* Respect alignment of argument on the stack. */
2694 CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
2695 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2696 unsigned CurArgOffset = ArgOffset;
2698 /* Compute GPR index associated with argument offset. */
2699 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2700 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
2702 // FIXME the codegen can be much improved in some cases.
2703 // We do not have to keep everything in memory.
2704 if (Flags.isByVal()) {
2705 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2706 ObjSize = Flags.getByValSize();
2707 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2708 // Empty aggregate parameters do not take up registers. Examples:
2712 // etc. However, we have to provide a place-holder in InVals, so
2713 // pretend we have an 8-byte item at the current address for that
2716 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2717 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2718 InVals.push_back(FIN);
2722 // Create a stack object covering all stack doublewords occupied
2723 // by the argument. If the argument is (fully or partially) on
2724 // the stack, or if the argument is fully in registers but the
2725 // caller has allocated the parameter save anyway, we can refer
2726 // directly to the caller's stack frame. Otherwise, create a
2727 // local copy in our own frame.
2729 if (HasParameterArea ||
2730 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
2731 FI = MFI->CreateFixedObject(ArgSize, ArgOffset, false, true);
2733 FI = MFI->CreateStackObject(ArgSize, Align, false);
2734 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2736 // Handle aggregates smaller than 8 bytes.
2737 if (ObjSize < PtrByteSize) {
2738 // The value of the object is its address, which differs from the
2739 // address of the enclosing doubleword on big-endian systems.
2741 if (!isLittleEndian) {
2742 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, PtrVT);
2743 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
2745 InVals.push_back(Arg);
2747 if (GPR_idx != Num_GPR_Regs) {
2748 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2749 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2752 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2753 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2754 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2755 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
2756 MachinePointerInfo(FuncArg),
2757 ObjType, false, false, 0);
2759 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2760 // store the whole register as-is to the parameter save area
2762 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2763 MachinePointerInfo(FuncArg),
2767 MemOps.push_back(Store);
2769 // Whether we copied from a register or not, advance the offset
2770 // into the parameter save area by a full doubleword.
2771 ArgOffset += PtrByteSize;
2775 // The value of the object is its address, which is the address of
2776 // its first stack doubleword.
2777 InVals.push_back(FIN);
2779 // Store whatever pieces of the object are in registers to memory.
2780 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2781 if (GPR_idx == Num_GPR_Regs)
2784 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2785 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2788 SDValue Off = DAG.getConstant(j, PtrVT);
2789 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
2791 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
2792 MachinePointerInfo(FuncArg, j),
2794 MemOps.push_back(Store);
2797 ArgOffset += ArgSize;
2801 switch (ObjectVT.getSimpleVT().SimpleTy) {
2802 default: llvm_unreachable("Unhandled argument type!");
2806 // These can be scalar arguments or elements of an integer array type
2807 // passed directly. Clang may use those instead of "byval" aggregate
2808 // types to avoid forcing arguments to memory unnecessarily.
2809 if (GPR_idx != Num_GPR_Regs) {
2810 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2811 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2813 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
2814 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2815 // value to MVT::i64 and then truncate to the correct register size.
2816 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2819 ArgSize = PtrByteSize;
2826 // These can be scalar arguments or elements of a float array type
2827 // passed directly. The latter are used to implement ELFv2 homogenous
2828 // float aggregates.
2829 if (FPR_idx != Num_FPR_Regs) {
2832 if (ObjectVT == MVT::f32)
2833 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2835 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX() ?
2836 &PPC::VSFRCRegClass :
2837 &PPC::F8RCRegClass);
2839 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2841 } else if (GPR_idx != Num_GPR_Regs) {
2842 // This can only ever happen in the presence of f32 array types,
2843 // since otherwise we never run out of FPRs before running out
2845 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2846 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2848 if (ObjectVT == MVT::f32) {
2849 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
2850 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
2851 DAG.getConstant(32, MVT::i32));
2852 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2855 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
2860 // When passing an array of floats, the array occupies consecutive
2861 // space in the argument area; only round up to the next doubleword
2862 // at the end of the array. Otherwise, each float takes 8 bytes.
2863 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
2864 ArgOffset += ArgSize;
2865 if (Flags.isInConsecutiveRegsLast())
2866 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2874 // These can be scalar arguments or elements of a vector array type
2875 // passed directly. The latter are used to implement ELFv2 homogenous
2876 // vector aggregates.
2877 if (VR_idx != Num_VR_Regs) {
2878 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
2879 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
2880 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2881 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2890 // We need to load the argument to a virtual register if we determined
2891 // above that we ran out of physical registers of the appropriate type.
2893 if (ObjSize < ArgSize && !isLittleEndian)
2894 CurArgOffset += ArgSize - ObjSize;
2895 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
2896 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2897 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2898 false, false, false, 0);
2901 InVals.push_back(ArgVal);
2904 // Area that is at least reserved in the caller of this function.
2905 unsigned MinReservedArea;
2906 if (HasParameterArea)
2907 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
2909 MinReservedArea = LinkageSize;
2911 // Set the size that is at least reserved in caller of this function. Tail
2912 // call optimized functions' reserved stack space needs to be aligned so that
2913 // taking the difference between two stack areas will result in an aligned
2915 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2916 FuncInfo->setMinReservedArea(MinReservedArea);
2918 // If the function takes variable number of arguments, make a frame index for
2919 // the start of the first vararg value... for expansion of llvm.va_start.
2921 int Depth = ArgOffset;
2923 FuncInfo->setVarArgsFrameIndex(
2924 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2925 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2927 // If this function is vararg, store any remaining integer argument regs
2928 // to their spots on the stack so that they may be loaded by deferencing the
2929 // result of va_next.
2930 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2931 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
2932 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2933 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2934 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2935 MachinePointerInfo(), false, false, 0);
2936 MemOps.push_back(Store);
2937 // Increment the address by four for the next argument to store
2938 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2939 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2943 if (!MemOps.empty())
2944 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2950 PPCTargetLowering::LowerFormalArguments_Darwin(
2952 CallingConv::ID CallConv, bool isVarArg,
2953 const SmallVectorImpl<ISD::InputArg>
2955 SDLoc dl, SelectionDAG &DAG,
2956 SmallVectorImpl<SDValue> &InVals) const {
2957 // TODO: add description of PPC stack frame format, or at least some docs.
2959 MachineFunction &MF = DAG.getMachineFunction();
2960 MachineFrameInfo *MFI = MF.getFrameInfo();
2961 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2963 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2964 bool isPPC64 = PtrVT == MVT::i64;
2965 // Potential tail calls could cause overwriting of argument stack slots.
2966 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2967 (CallConv == CallingConv::Fast));
2968 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2970 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true,
2972 unsigned ArgOffset = LinkageSize;
2973 // Area that is at least reserved in caller of this function.
2974 unsigned MinReservedArea = ArgOffset;
2976 static const MCPhysReg GPR_32[] = { // 32-bit registers.
2977 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2978 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2980 static const MCPhysReg GPR_64[] = { // 64-bit registers.
2981 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2982 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2985 static const MCPhysReg *FPR = GetFPR();
2987 static const MCPhysReg VR[] = {
2988 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2989 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2992 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2993 const unsigned Num_FPR_Regs = 13;
2994 const unsigned Num_VR_Regs = array_lengthof( VR);
2996 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2998 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
3000 // In 32-bit non-varargs functions, the stack space for vectors is after the
3001 // stack space for non-vectors. We do not use this space unless we have
3002 // too many vectors to fit in registers, something that only occurs in
3003 // constructed examples:), but we have to walk the arglist to figure
3004 // that out...for the pathological case, compute VecArgOffset as the
3005 // start of the vector parameter area. Computing VecArgOffset is the
3006 // entire point of the following loop.
3007 unsigned VecArgOffset = ArgOffset;
3008 if (!isVarArg && !isPPC64) {
3009 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
3011 EVT ObjectVT = Ins[ArgNo].VT;
3012 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3014 if (Flags.isByVal()) {
3015 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
3016 unsigned ObjSize = Flags.getByValSize();
3018 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3019 VecArgOffset += ArgSize;
3023 switch(ObjectVT.getSimpleVT().SimpleTy) {
3024 default: llvm_unreachable("Unhandled argument type!");
3030 case MVT::i64: // PPC64
3032 // FIXME: We are guaranteed to be !isPPC64 at this point.
3033 // Does MVT::i64 apply?
3040 // Nothing to do, we're only looking at Nonvector args here.
3045 // We've found where the vector parameter area in memory is. Skip the
3046 // first 12 parameters; these don't use that memory.
3047 VecArgOffset = ((VecArgOffset+15)/16)*16;
3048 VecArgOffset += 12*16;
3050 // Add DAG nodes to load the arguments or copy them out of registers. On
3051 // entry to a function on PPC, the arguments start after the linkage area,
3052 // although the first ones are often in registers.
3054 SmallVector<SDValue, 8> MemOps;
3055 unsigned nAltivecParamsAtEnd = 0;
3056 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3057 unsigned CurArgIdx = 0;
3058 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3060 bool needsLoad = false;
3061 EVT ObjectVT = Ins[ArgNo].VT;
3062 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
3063 unsigned ArgSize = ObjSize;
3064 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3065 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
3066 CurArgIdx = Ins[ArgNo].OrigArgIndex;
3068 unsigned CurArgOffset = ArgOffset;
3070 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
3071 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
3072 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
3073 if (isVarArg || isPPC64) {
3074 MinReservedArea = ((MinReservedArea+15)/16)*16;
3075 MinReservedArea += CalculateStackSlotSize(ObjectVT,
3078 } else nAltivecParamsAtEnd++;
3080 // Calculate min reserved area.
3081 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
3085 // FIXME the codegen can be much improved in some cases.
3086 // We do not have to keep everything in memory.
3087 if (Flags.isByVal()) {
3088 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3089 ObjSize = Flags.getByValSize();
3090 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3091 // Objects of size 1 and 2 are right justified, everything else is
3092 // left justified. This means the memory address is adjusted forwards.
3093 if (ObjSize==1 || ObjSize==2) {
3094 CurArgOffset = CurArgOffset + (4 - ObjSize);
3096 // The value of the object is its address.
3097 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, false, true);
3098 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3099 InVals.push_back(FIN);
3100 if (ObjSize==1 || ObjSize==2) {
3101 if (GPR_idx != Num_GPR_Regs) {
3104 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3106 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3107 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3108 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
3109 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
3110 MachinePointerInfo(FuncArg),
3111 ObjType, false, false, 0);
3112 MemOps.push_back(Store);
3116 ArgOffset += PtrByteSize;
3120 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3121 // Store whatever pieces of the object are in registers
3122 // to memory. ArgOffset will be the address of the beginning
3124 if (GPR_idx != Num_GPR_Regs) {
3127 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3129 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3130 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3131 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3132 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3133 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3134 MachinePointerInfo(FuncArg, j),
3136 MemOps.push_back(Store);
3138 ArgOffset += PtrByteSize;
3140 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
3147 switch (ObjectVT.getSimpleVT().SimpleTy) {
3148 default: llvm_unreachable("Unhandled argument type!");
3152 if (GPR_idx != Num_GPR_Regs) {
3153 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3154 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3156 if (ObjectVT == MVT::i1)
3157 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
3162 ArgSize = PtrByteSize;
3164 // All int arguments reserve stack space in the Darwin ABI.
3165 ArgOffset += PtrByteSize;
3169 case MVT::i64: // PPC64
3170 if (GPR_idx != Num_GPR_Regs) {
3171 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3172 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3174 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3175 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3176 // value to MVT::i64 and then truncate to the correct register size.
3177 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3182 ArgSize = PtrByteSize;
3184 // All int arguments reserve stack space in the Darwin ABI.
3190 // Every 4 bytes of argument space consumes one of the GPRs available for
3191 // argument passing.
3192 if (GPR_idx != Num_GPR_Regs) {
3194 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
3197 if (FPR_idx != Num_FPR_Regs) {
3200 if (ObjectVT == MVT::f32)
3201 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
3203 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
3205 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3211 // All FP arguments reserve stack space in the Darwin ABI.
3212 ArgOffset += isPPC64 ? 8 : ObjSize;
3218 // Note that vector arguments in registers don't reserve stack space,
3219 // except in varargs functions.
3220 if (VR_idx != Num_VR_Regs) {
3221 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3222 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3224 while ((ArgOffset % 16) != 0) {
3225 ArgOffset += PtrByteSize;
3226 if (GPR_idx != Num_GPR_Regs)
3230 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
3234 if (!isVarArg && !isPPC64) {
3235 // Vectors go after all the nonvectors.
3236 CurArgOffset = VecArgOffset;
3239 // Vectors are aligned.
3240 ArgOffset = ((ArgOffset+15)/16)*16;
3241 CurArgOffset = ArgOffset;
3249 // We need to load the argument to a virtual register if we determined above
3250 // that we ran out of physical registers of the appropriate type.
3252 int FI = MFI->CreateFixedObject(ObjSize,
3253 CurArgOffset + (ArgSize - ObjSize),
3255 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3256 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3257 false, false, false, 0);
3260 InVals.push_back(ArgVal);
3263 // Allow for Altivec parameters at the end, if needed.
3264 if (nAltivecParamsAtEnd) {
3265 MinReservedArea = ((MinReservedArea+15)/16)*16;
3266 MinReservedArea += 16*nAltivecParamsAtEnd;
3269 // Area that is at least reserved in the caller of this function.
3270 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
3272 // Set the size that is at least reserved in caller of this function. Tail
3273 // call optimized functions' reserved stack space needs to be aligned so that
3274 // taking the difference between two stack areas will result in an aligned
3276 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
3277 FuncInfo->setMinReservedArea(MinReservedArea);
3279 // If the function takes variable number of arguments, make a frame index for
3280 // the start of the first vararg value... for expansion of llvm.va_start.
3282 int Depth = ArgOffset;
3284 FuncInfo->setVarArgsFrameIndex(
3285 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3287 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3289 // If this function is vararg, store any remaining integer argument regs
3290 // to their spots on the stack so that they may be loaded by deferencing the
3291 // result of va_next.
3292 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3296 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3298 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3300 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3301 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3302 MachinePointerInfo(), false, false, 0);
3303 MemOps.push_back(Store);
3304 // Increment the address by four for the next argument to store
3305 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
3306 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3310 if (!MemOps.empty())
3311 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3316 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3317 /// adjusted to accommodate the arguments for the tailcall.
3318 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3319 unsigned ParamSize) {
3321 if (!isTailCall) return 0;
3323 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3324 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3325 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3326 // Remember only if the new adjustement is bigger.
3327 if (SPDiff < FI->getTailCallSPDelta())
3328 FI->setTailCallSPDelta(SPDiff);
3333 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3334 /// for tail call optimization. Targets which want to do tail call
3335 /// optimization should implement this function.
3337 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3338 CallingConv::ID CalleeCC,
3340 const SmallVectorImpl<ISD::InputArg> &Ins,
3341 SelectionDAG& DAG) const {
3342 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3345 // Variable argument functions are not supported.
3349 MachineFunction &MF = DAG.getMachineFunction();
3350 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3351 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3352 // Functions containing by val parameters are not supported.
3353 for (unsigned i = 0; i != Ins.size(); i++) {
3354 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3355 if (Flags.isByVal()) return false;
3358 // Non-PIC/GOT tail calls are supported.
3359 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3362 // At the moment we can only do local tail calls (in same module, hidden
3363 // or protected) if we are generating PIC.
3364 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3365 return G->getGlobal()->hasHiddenVisibility()
3366 || G->getGlobal()->hasProtectedVisibility();
3372 /// isCallCompatibleAddress - Return the immediate to use if the specified
3373 /// 32-bit value is representable in the immediate field of a BxA instruction.
3374 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3375 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3376 if (!C) return nullptr;
3378 int Addr = C->getZExtValue();
3379 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3380 SignExtend32<26>(Addr) != Addr)
3381 return nullptr; // Top 6 bits have to be sext of immediate.
3383 return DAG.getConstant((int)C->getZExtValue() >> 2,
3384 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
3389 struct TailCallArgumentInfo {
3394 TailCallArgumentInfo() : FrameIdx(0) {}
3399 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3401 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3403 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3404 SmallVectorImpl<SDValue> &MemOpChains,
3406 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3407 SDValue Arg = TailCallArgs[i].Arg;
3408 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3409 int FI = TailCallArgs[i].FrameIdx;
3410 // Store relative to framepointer.
3411 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
3412 MachinePointerInfo::getFixedStack(FI),
3417 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3418 /// the appropriate stack slot for the tail call optimized function call.
3419 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3420 MachineFunction &MF,
3429 // Calculate the new stack slot for the return address.
3430 int SlotSize = isPPC64 ? 8 : 4;
3431 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
3433 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3434 NewRetAddrLoc, true);
3435 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3436 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3437 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3438 MachinePointerInfo::getFixedStack(NewRetAddr),
3441 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3442 // slot as the FP is never overwritten.
3445 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
3446 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3448 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3449 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3450 MachinePointerInfo::getFixedStack(NewFPIdx),
3457 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3458 /// the position of the argument.
3460 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3461 SDValue Arg, int SPDiff, unsigned ArgOffset,
3462 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3463 int Offset = ArgOffset + SPDiff;
3464 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3465 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3466 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3467 SDValue FIN = DAG.getFrameIndex(FI, VT);
3468 TailCallArgumentInfo Info;
3470 Info.FrameIdxOp = FIN;
3472 TailCallArguments.push_back(Info);
3475 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3476 /// stack slot. Returns the chain as result and the loaded frame pointers in
3477 /// LROpOut/FPOpout. Used when tail calling.
3478 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3486 // Load the LR and FP stack slot for later adjusting.
3487 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
3488 LROpOut = getReturnAddrFrameIndex(DAG);
3489 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3490 false, false, false, 0);
3491 Chain = SDValue(LROpOut.getNode(), 1);
3493 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3494 // slot as the FP is never overwritten.
3496 FPOpOut = getFramePointerFrameIndex(DAG);
3497 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3498 false, false, false, 0);
3499 Chain = SDValue(FPOpOut.getNode(), 1);
3505 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3506 /// by "Src" to address "Dst" of size "Size". Alignment information is
3507 /// specified by the specific parameter attribute. The copy will be passed as
3508 /// a byval function parameter.
3509 /// Sometimes what we are copying is the end of a larger object, the part that
3510 /// does not fit in registers.
3512 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3513 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3515 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3516 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3517 false, false, MachinePointerInfo(),
3518 MachinePointerInfo());
3521 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3524 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3525 SDValue Arg, SDValue PtrOff, int SPDiff,
3526 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3527 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
3528 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
3530 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3535 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3537 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3538 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3539 DAG.getConstant(ArgOffset, PtrVT));
3541 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3542 MachinePointerInfo(), false, false, 0));
3543 // Calculate and remember argument location.
3544 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3549 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3550 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3551 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3552 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
3553 MachineFunction &MF = DAG.getMachineFunction();
3555 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3556 // might overwrite each other in case of tail call optimization.
3557 SmallVector<SDValue, 8> MemOpChains2;
3558 // Do not flag preceding copytoreg stuff together with the following stuff.
3560 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3562 if (!MemOpChains2.empty())
3563 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3565 // Store the return address to the appropriate stack slot.
3566 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3567 isPPC64, isDarwinABI, dl);
3569 // Emit callseq_end just before tailcall node.
3570 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3571 DAG.getIntPtrConstant(0, true), InFlag, dl);
3572 InFlag = Chain.getValue(1);
3575 // Is this global address that of a function that can be called by name? (as
3576 // opposed to something that must hold a descriptor for an indirect call).
3577 static bool isFunctionGlobalAddress(SDValue Callee) {
3578 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3579 if (Callee.getOpcode() == ISD::GlobalTLSAddress ||
3580 Callee.getOpcode() == ISD::TargetGlobalTLSAddress)
3583 return G->getGlobal()->getType()->getElementType()->isFunctionTy();
3590 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3591 SDValue &Chain, SDValue CallSeqStart, SDLoc dl, int SPDiff,
3592 bool isTailCall, bool IsPatchPoint,
3593 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
3594 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
3595 ImmutableCallSite *CS, const PPCSubtarget &Subtarget) {
3597 bool isPPC64 = Subtarget.isPPC64();
3598 bool isSVR4ABI = Subtarget.isSVR4ABI();
3599 bool isELFv2ABI = Subtarget.isELFv2ABI();
3601 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3602 NodeTys.push_back(MVT::Other); // Returns a chain
3603 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3605 unsigned CallOpc = PPCISD::CALL;
3607 bool needIndirectCall = true;
3608 if (!isSVR4ABI || !isPPC64)
3609 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3610 // If this is an absolute destination address, use the munged value.
3611 Callee = SDValue(Dest, 0);
3612 needIndirectCall = false;
3615 if (isFunctionGlobalAddress(Callee)) {
3616 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Callee);
3617 // A call to a TLS address is actually an indirect call to a
3618 // thread-specific pointer.
3619 unsigned OpFlags = 0;
3620 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3621 (Subtarget.getTargetTriple().isMacOSX() &&
3622 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3623 (G->getGlobal()->isDeclaration() ||
3624 G->getGlobal()->isWeakForLinker())) ||
3625 (Subtarget.isTargetELF() && !isPPC64 &&
3626 !G->getGlobal()->hasLocalLinkage() &&
3627 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3628 // PC-relative references to external symbols should go through $stub,
3629 // unless we're building with the leopard linker or later, which
3630 // automatically synthesizes these stubs.
3631 OpFlags = PPCII::MO_PLT_OR_STUB;
3634 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3635 // every direct call is) turn it into a TargetGlobalAddress /
3636 // TargetExternalSymbol node so that legalize doesn't hack it.
3637 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3638 Callee.getValueType(), 0, OpFlags);
3639 needIndirectCall = false;
3642 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3643 unsigned char OpFlags = 0;
3645 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3646 (Subtarget.getTargetTriple().isMacOSX() &&
3647 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) ||
3648 (Subtarget.isTargetELF() && !isPPC64 &&
3649 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3650 // PC-relative references to external symbols should go through $stub,
3651 // unless we're building with the leopard linker or later, which
3652 // automatically synthesizes these stubs.
3653 OpFlags = PPCII::MO_PLT_OR_STUB;
3656 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3658 needIndirectCall = false;
3662 // We'll form an invalid direct call when lowering a patchpoint; the full
3663 // sequence for an indirect call is complicated, and many of the
3664 // instructions introduced might have side effects (and, thus, can't be
3665 // removed later). The call itself will be removed as soon as the
3666 // argument/return lowering is complete, so the fact that it has the wrong
3667 // kind of operands should not really matter.
3668 needIndirectCall = false;
3671 if (needIndirectCall) {
3672 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3673 // to do the call, we can't use PPCISD::CALL.
3674 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3676 if (isSVR4ABI && isPPC64 && !isELFv2ABI) {
3677 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3678 // entry point, but to the function descriptor (the function entry point
3679 // address is part of the function descriptor though).
3680 // The function descriptor is a three doubleword structure with the
3681 // following fields: function entry point, TOC base address and
3682 // environment pointer.
3683 // Thus for a call through a function pointer, the following actions need
3685 // 1. Save the TOC of the caller in the TOC save area of its stack
3686 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3687 // 2. Load the address of the function entry point from the function
3689 // 3. Load the TOC of the callee from the function descriptor into r2.
3690 // 4. Load the environment pointer from the function descriptor into
3692 // 5. Branch to the function entry point address.
3693 // 6. On return of the callee, the TOC of the caller needs to be
3694 // restored (this is done in FinishCall()).
3696 // The loads are scheduled at the beginning of the call sequence, and the
3697 // register copies are flagged together to ensure that no other
3698 // operations can be scheduled in between. E.g. without flagging the
3699 // copies together, a TOC access in the caller could be scheduled between
3700 // the assignment of the callee TOC and the branch to the callee, which
3701 // results in the TOC access going through the TOC of the callee instead
3702 // of going through the TOC of the caller, which leads to incorrect code.
3704 // Load the address of the function entry point from the function
3706 SDValue LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-1);
3707 if (LDChain.getValueType() == MVT::Glue)
3708 LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-2);
3710 bool LoadsInv = Subtarget.hasInvariantFunctionDescriptors();
3712 MachinePointerInfo MPI(CS ? CS->getCalledValue() : nullptr);
3713 SDValue LoadFuncPtr = DAG.getLoad(MVT::i64, dl, LDChain, Callee, MPI,
3714 false, false, LoadsInv, 8);
3716 // Load environment pointer into r11.
3717 SDValue PtrOff = DAG.getIntPtrConstant(16);
3718 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3719 SDValue LoadEnvPtr = DAG.getLoad(MVT::i64, dl, LDChain, AddPtr,
3720 MPI.getWithOffset(16), false, false,
3723 SDValue TOCOff = DAG.getIntPtrConstant(8);
3724 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
3725 SDValue TOCPtr = DAG.getLoad(MVT::i64, dl, LDChain, AddTOC,
3726 MPI.getWithOffset(8), false, false,
3729 SDValue TOCVal = DAG.getCopyToReg(Chain, dl, PPC::X2, TOCPtr,
3731 Chain = TOCVal.getValue(0);
3732 InFlag = TOCVal.getValue(1);
3734 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3737 Chain = EnvVal.getValue(0);
3738 InFlag = EnvVal.getValue(1);
3740 MTCTROps[0] = Chain;
3741 MTCTROps[1] = LoadFuncPtr;
3742 MTCTROps[2] = InFlag;
3745 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
3746 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3747 InFlag = Chain.getValue(1);
3750 NodeTys.push_back(MVT::Other);
3751 NodeTys.push_back(MVT::Glue);
3752 Ops.push_back(Chain);
3753 CallOpc = PPCISD::BCTRL;
3754 Callee.setNode(nullptr);
3755 // Add use of X11 (holding environment pointer)
3756 if (isSVR4ABI && isPPC64 && !isELFv2ABI)
3757 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3758 // Add CTR register as callee so a bctr can be emitted later.
3760 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3763 // If this is a direct call, pass the chain and the callee.
3764 if (Callee.getNode()) {
3765 Ops.push_back(Chain);
3766 Ops.push_back(Callee);
3768 // If this is a call to __tls_get_addr, find the symbol whose address
3769 // is to be taken and add it to the list. This will be used to
3770 // generate __tls_get_addr(<sym>@tlsgd) or __tls_get_addr(<sym>@tlsld).
3771 // We find the symbol by walking the chain to the CopyFromReg, walking
3772 // back from the CopyFromReg to the ADDI_TLSGD_L or ADDI_TLSLD_L, and
3773 // pulling the symbol from that node.
3774 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
3775 if (!strcmp(S->getSymbol(), "__tls_get_addr")) {
3776 assert(!needIndirectCall && "Indirect call to __tls_get_addr???");
3777 SDNode *AddI = Chain.getNode()->getOperand(2).getNode();
3778 SDValue TGTAddr = AddI->getOperand(1);
3779 assert(TGTAddr.getNode()->getOpcode() == ISD::TargetGlobalTLSAddress &&
3780 "Didn't find target global TLS address where we expected one");
3781 Ops.push_back(TGTAddr);
3782 CallOpc = PPCISD::CALL_TLS;
3785 // If this is a tail call add stack pointer delta.
3787 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3789 // Add argument registers to the end of the list so that they are known live
3791 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3792 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3793 RegsToPass[i].second.getValueType()));
3795 // Direct calls in the ELFv2 ABI need the TOC register live into the call.
3796 if (Callee.getNode() && isELFv2ABI && !IsPatchPoint)
3797 Ops.push_back(DAG.getRegister(PPC::X2, PtrVT));
3803 bool isLocalCall(const SDValue &Callee)
3805 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3806 return !G->getGlobal()->isDeclaration() &&
3807 !G->getGlobal()->isWeakForLinker();
3812 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3813 CallingConv::ID CallConv, bool isVarArg,
3814 const SmallVectorImpl<ISD::InputArg> &Ins,
3815 SDLoc dl, SelectionDAG &DAG,
3816 SmallVectorImpl<SDValue> &InVals) const {
3818 SmallVector<CCValAssign, 16> RVLocs;
3819 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
3821 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3823 // Copy all of the result registers out of their specified physreg.
3824 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3825 CCValAssign &VA = RVLocs[i];
3826 assert(VA.isRegLoc() && "Can only return in registers!");
3828 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3829 VA.getLocReg(), VA.getLocVT(), InFlag);
3830 Chain = Val.getValue(1);
3831 InFlag = Val.getValue(2);
3833 switch (VA.getLocInfo()) {
3834 default: llvm_unreachable("Unknown loc info!");
3835 case CCValAssign::Full: break;
3836 case CCValAssign::AExt:
3837 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3839 case CCValAssign::ZExt:
3840 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3841 DAG.getValueType(VA.getValVT()));
3842 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3844 case CCValAssign::SExt:
3845 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3846 DAG.getValueType(VA.getValVT()));
3847 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3851 InVals.push_back(Val);
3858 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
3859 bool isTailCall, bool isVarArg, bool IsPatchPoint,
3861 SmallVector<std::pair<unsigned, SDValue>, 8>
3863 SDValue InFlag, SDValue Chain,
3864 SDValue CallSeqStart, SDValue &Callee,
3865 int SPDiff, unsigned NumBytes,
3866 const SmallVectorImpl<ISD::InputArg> &Ins,
3867 SmallVectorImpl<SDValue> &InVals,
3868 ImmutableCallSite *CS) const {
3870 bool isELFv2ABI = Subtarget.isELFv2ABI();
3871 std::vector<EVT> NodeTys;
3872 SmallVector<SDValue, 8> Ops;
3873 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, CallSeqStart, dl,
3874 SPDiff, isTailCall, IsPatchPoint, RegsToPass,
3875 Ops, NodeTys, CS, Subtarget);
3877 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3878 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
3879 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3881 // When performing tail call optimization the callee pops its arguments off
3882 // the stack. Account for this here so these bytes can be pushed back on in
3883 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3884 int BytesCalleePops =
3885 (CallConv == CallingConv::Fast &&
3886 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3888 // Add a register mask operand representing the call-preserved registers.
3889 const TargetRegisterInfo *TRI =
3890 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
3891 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3892 assert(Mask && "Missing call preserved mask for calling convention");
3893 Ops.push_back(DAG.getRegisterMask(Mask));
3895 if (InFlag.getNode())
3896 Ops.push_back(InFlag);
3900 assert(((Callee.getOpcode() == ISD::Register &&
3901 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3902 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3903 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3904 isa<ConstantSDNode>(Callee)) &&
3905 "Expecting an global address, external symbol, absolute value or register");
3907 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
3910 // Add a NOP immediately after the branch instruction when using the 64-bit
3911 // SVR4 ABI. At link time, if caller and callee are in a different module and
3912 // thus have a different TOC, the call will be replaced with a call to a stub
3913 // function which saves the current TOC, loads the TOC of the callee and
3914 // branches to the callee. The NOP will be replaced with a load instruction
3915 // which restores the TOC of the caller from the TOC save slot of the current
3916 // stack frame. If caller and callee belong to the same module (and have the
3917 // same TOC), the NOP will remain unchanged.
3919 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64() &&
3921 if (CallOpc == PPCISD::BCTRL) {
3922 // This is a call through a function pointer.
3923 // Restore the caller TOC from the save area into R2.
3924 // See PrepareCall() for more information about calls through function
3925 // pointers in the 64-bit SVR4 ABI.
3926 // We are using a target-specific load with r2 hard coded, because the
3927 // result of a target-independent load would never go directly into r2,
3928 // since r2 is a reserved register (which prevents the register allocator
3929 // from allocating it), resulting in an additional register being
3930 // allocated and an unnecessary move instruction being generated.
3931 CallOpc = PPCISD::BCTRL_LOAD_TOC;
3933 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3934 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
3935 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset(isELFv2ABI);
3936 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset);
3937 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
3939 // The address needs to go after the chain input but before the flag (or
3940 // any other variadic arguments).
3941 Ops.insert(std::next(Ops.begin()), AddTOC);
3942 } else if ((CallOpc == PPCISD::CALL) &&
3943 (!isLocalCall(Callee) ||
3944 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3945 // Otherwise insert NOP for non-local calls.
3946 CallOpc = PPCISD::CALL_NOP;
3947 } else if (CallOpc == PPCISD::CALL_TLS)
3948 // For 64-bit SVR4, TLS calls are always non-local.
3949 CallOpc = PPCISD::CALL_NOP_TLS;
3952 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
3953 InFlag = Chain.getValue(1);
3955 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3956 DAG.getIntPtrConstant(BytesCalleePops, true),
3959 InFlag = Chain.getValue(1);
3961 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3962 Ins, dl, DAG, InVals);
3966 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3967 SmallVectorImpl<SDValue> &InVals) const {
3968 SelectionDAG &DAG = CLI.DAG;
3970 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3971 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3972 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3973 SDValue Chain = CLI.Chain;
3974 SDValue Callee = CLI.Callee;
3975 bool &isTailCall = CLI.IsTailCall;
3976 CallingConv::ID CallConv = CLI.CallConv;
3977 bool isVarArg = CLI.IsVarArg;
3978 bool IsPatchPoint = CLI.IsPatchPoint;
3979 ImmutableCallSite *CS = CLI.CS;
3982 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3985 if (!isTailCall && CS && CS->isMustTailCall())
3986 report_fatal_error("failed to perform tail call elimination on a call "
3987 "site marked musttail");
3989 if (Subtarget.isSVR4ABI()) {
3990 if (Subtarget.isPPC64())
3991 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3992 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
3993 dl, DAG, InVals, CS);
3995 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3996 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
3997 dl, DAG, InVals, CS);
4000 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
4001 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4002 dl, DAG, InVals, CS);
4006 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
4007 CallingConv::ID CallConv, bool isVarArg,
4008 bool isTailCall, bool IsPatchPoint,
4009 const SmallVectorImpl<ISD::OutputArg> &Outs,
4010 const SmallVectorImpl<SDValue> &OutVals,
4011 const SmallVectorImpl<ISD::InputArg> &Ins,
4012 SDLoc dl, SelectionDAG &DAG,
4013 SmallVectorImpl<SDValue> &InVals,
4014 ImmutableCallSite *CS) const {
4015 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
4016 // of the 32-bit SVR4 ABI stack frame layout.
4018 assert((CallConv == CallingConv::C ||
4019 CallConv == CallingConv::Fast) && "Unknown calling convention!");
4021 unsigned PtrByteSize = 4;
4023 MachineFunction &MF = DAG.getMachineFunction();
4025 // Mark this function as potentially containing a function that contains a
4026 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4027 // and restoring the callers stack pointer in this functions epilog. This is
4028 // done because by tail calling the called function might overwrite the value
4029 // in this function's (MF) stack pointer stack slot 0(SP).
4030 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4031 CallConv == CallingConv::Fast)
4032 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4034 // Count how many bytes are to be pushed on the stack, including the linkage
4035 // area, parameter list area and the part of the local variable space which
4036 // contains copies of aggregates which are passed by value.
4038 // Assign locations to all of the outgoing arguments.
4039 SmallVector<CCValAssign, 16> ArgLocs;
4040 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
4043 // Reserve space for the linkage area on the stack.
4044 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false, false),
4048 // Handle fixed and variable vector arguments differently.
4049 // Fixed vector arguments go into registers as long as registers are
4050 // available. Variable vector arguments always go into memory.
4051 unsigned NumArgs = Outs.size();
4053 for (unsigned i = 0; i != NumArgs; ++i) {
4054 MVT ArgVT = Outs[i].VT;
4055 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
4058 if (Outs[i].IsFixed) {
4059 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
4062 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
4068 errs() << "Call operand #" << i << " has unhandled type "
4069 << EVT(ArgVT).getEVTString() << "\n";
4071 llvm_unreachable(nullptr);
4075 // All arguments are treated the same.
4076 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
4079 // Assign locations to all of the outgoing aggregate by value arguments.
4080 SmallVector<CCValAssign, 16> ByValArgLocs;
4081 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4082 ByValArgLocs, *DAG.getContext());
4084 // Reserve stack space for the allocations in CCInfo.
4085 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
4087 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
4089 // Size of the linkage area, parameter list area and the part of the local
4090 // space variable where copies of aggregates which are passed by value are
4092 unsigned NumBytes = CCByValInfo.getNextStackOffset();
4094 // Calculate by how many bytes the stack has to be adjusted in case of tail
4095 // call optimization.
4096 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4098 // Adjust the stack pointer for the new arguments...
4099 // These operations are automatically eliminated by the prolog/epilog pass
4100 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4102 SDValue CallSeqStart = Chain;
4104 // Load the return address and frame pointer so it can be moved somewhere else
4107 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
4110 // Set up a copy of the stack pointer for use loading and storing any
4111 // arguments that may not fit in the registers available for argument
4113 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4115 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4116 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4117 SmallVector<SDValue, 8> MemOpChains;
4119 bool seenFloatArg = false;
4120 // Walk the register/memloc assignments, inserting copies/loads.
4121 for (unsigned i = 0, j = 0, e = ArgLocs.size();
4124 CCValAssign &VA = ArgLocs[i];
4125 SDValue Arg = OutVals[i];
4126 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4128 if (Flags.isByVal()) {
4129 // Argument is an aggregate which is passed by value, thus we need to
4130 // create a copy of it in the local variable space of the current stack
4131 // frame (which is the stack frame of the caller) and pass the address of
4132 // this copy to the callee.
4133 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
4134 CCValAssign &ByValVA = ByValArgLocs[j++];
4135 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
4137 // Memory reserved in the local variable space of the callers stack frame.
4138 unsigned LocMemOffset = ByValVA.getLocMemOffset();
4140 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4141 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4143 // Create a copy of the argument in the local area of the current
4145 SDValue MemcpyCall =
4146 CreateCopyOfByValArgument(Arg, PtrOff,
4147 CallSeqStart.getNode()->getOperand(0),
4150 // This must go outside the CALLSEQ_START..END.
4151 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4152 CallSeqStart.getNode()->getOperand(1),
4154 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4155 NewCallSeqStart.getNode());
4156 Chain = CallSeqStart = NewCallSeqStart;
4158 // Pass the address of the aggregate copy on the stack either in a
4159 // physical register or in the parameter list area of the current stack
4160 // frame to the callee.
4164 if (VA.isRegLoc()) {
4165 if (Arg.getValueType() == MVT::i1)
4166 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
4168 seenFloatArg |= VA.getLocVT().isFloatingPoint();
4169 // Put argument in a physical register.
4170 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
4172 // Put argument in the parameter list area of the current stack frame.
4173 assert(VA.isMemLoc());
4174 unsigned LocMemOffset = VA.getLocMemOffset();
4177 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4178 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4180 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4181 MachinePointerInfo(),
4184 // Calculate and remember argument location.
4185 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
4191 if (!MemOpChains.empty())
4192 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4194 // Build a sequence of copy-to-reg nodes chained together with token chain
4195 // and flag operands which copy the outgoing args into the appropriate regs.
4197 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4198 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4199 RegsToPass[i].second, InFlag);
4200 InFlag = Chain.getValue(1);
4203 // Set CR bit 6 to true if this is a vararg call with floating args passed in
4206 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
4207 SDValue Ops[] = { Chain, InFlag };
4209 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
4210 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
4212 InFlag = Chain.getValue(1);
4216 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
4217 false, TailCallArguments);
4219 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint, DAG,
4220 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
4221 NumBytes, Ins, InVals, CS);
4224 // Copy an argument into memory, being careful to do this outside the
4225 // call sequence for the call to which the argument belongs.
4227 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
4228 SDValue CallSeqStart,
4229 ISD::ArgFlagsTy Flags,
4232 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
4233 CallSeqStart.getNode()->getOperand(0),
4235 // The MEMCPY must go outside the CALLSEQ_START..END.
4236 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4237 CallSeqStart.getNode()->getOperand(1),
4239 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4240 NewCallSeqStart.getNode());
4241 return NewCallSeqStart;
4245 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
4246 CallingConv::ID CallConv, bool isVarArg,
4247 bool isTailCall, bool IsPatchPoint,
4248 const SmallVectorImpl<ISD::OutputArg> &Outs,
4249 const SmallVectorImpl<SDValue> &OutVals,
4250 const SmallVectorImpl<ISD::InputArg> &Ins,
4251 SDLoc dl, SelectionDAG &DAG,
4252 SmallVectorImpl<SDValue> &InVals,
4253 ImmutableCallSite *CS) const {
4255 bool isELFv2ABI = Subtarget.isELFv2ABI();
4256 bool isLittleEndian = Subtarget.isLittleEndian();
4257 unsigned NumOps = Outs.size();
4259 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4260 unsigned PtrByteSize = 8;
4262 MachineFunction &MF = DAG.getMachineFunction();
4264 // Mark this function as potentially containing a function that contains a
4265 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4266 // and restoring the callers stack pointer in this functions epilog. This is
4267 // done because by tail calling the called function might overwrite the value
4268 // in this function's (MF) stack pointer stack slot 0(SP).
4269 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4270 CallConv == CallingConv::Fast)
4271 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4273 // Count how many bytes are to be pushed on the stack, including the linkage
4274 // area, and parameter passing area. On ELFv1, the linkage area is 48 bytes
4275 // reserved space for [SP][CR][LR][2 x unused][TOC]; on ELFv2, the linkage
4276 // area is 32 bytes reserved space for [SP][CR][LR][TOC].
4277 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
4279 unsigned NumBytes = LinkageSize;
4281 // Add up all the space actually used.
4282 for (unsigned i = 0; i != NumOps; ++i) {
4283 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4284 EVT ArgVT = Outs[i].VT;
4285 EVT OrigVT = Outs[i].ArgVT;
4287 /* Respect alignment of argument on the stack. */
4289 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4290 NumBytes = ((NumBytes + Align - 1) / Align) * Align;
4292 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4293 if (Flags.isInConsecutiveRegsLast())
4294 NumBytes = ((NumBytes + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4297 unsigned NumBytesActuallyUsed = NumBytes;
4299 // The prolog code of the callee may store up to 8 GPR argument registers to
4300 // the stack, allowing va_start to index over them in memory if its varargs.
4301 // Because we cannot tell if this is needed on the caller side, we have to
4302 // conservatively assume that it is needed. As such, make sure we have at
4303 // least enough stack space for the caller to store the 8 GPRs.
4304 // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
4305 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4307 // Tail call needs the stack to be aligned.
4308 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4309 CallConv == CallingConv::Fast)
4310 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
4312 // Calculate by how many bytes the stack has to be adjusted in case of tail
4313 // call optimization.
4314 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4316 // To protect arguments on the stack from being clobbered in a tail call,
4317 // force all the loads to happen before doing any other lowering.
4319 Chain = DAG.getStackArgumentTokenFactor(Chain);
4321 // Adjust the stack pointer for the new arguments...
4322 // These operations are automatically eliminated by the prolog/epilog pass
4323 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4325 SDValue CallSeqStart = Chain;
4327 // Load the return address and frame pointer so it can be move somewhere else
4330 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4333 // Set up a copy of the stack pointer for use loading and storing any
4334 // arguments that may not fit in the registers available for argument
4336 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4338 // Figure out which arguments are going to go in registers, and which in
4339 // memory. Also, if this is a vararg function, floating point operations
4340 // must be stored to our stack, and loaded into integer regs as well, if
4341 // any integer regs are available for argument passing.
4342 unsigned ArgOffset = LinkageSize;
4343 unsigned GPR_idx, FPR_idx = 0, VR_idx = 0;
4345 static const MCPhysReg GPR[] = {
4346 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4347 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4349 static const MCPhysReg *FPR = GetFPR();
4351 static const MCPhysReg VR[] = {
4352 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4353 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4355 static const MCPhysReg VSRH[] = {
4356 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4357 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4360 const unsigned NumGPRs = array_lengthof(GPR);
4361 const unsigned NumFPRs = 13;
4362 const unsigned NumVRs = array_lengthof(VR);
4364 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4365 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4367 SmallVector<SDValue, 8> MemOpChains;
4368 for (unsigned i = 0; i != NumOps; ++i) {
4369 SDValue Arg = OutVals[i];
4370 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4371 EVT ArgVT = Outs[i].VT;
4372 EVT OrigVT = Outs[i].ArgVT;
4374 /* Respect alignment of argument on the stack. */
4376 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4377 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
4379 /* Compute GPR index associated with argument offset. */
4380 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4381 GPR_idx = std::min(GPR_idx, NumGPRs);
4383 // PtrOff will be used to store the current argument to the stack if a
4384 // register cannot be found for it.
4387 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4389 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4391 // Promote integers to 64-bit values.
4392 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4393 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4394 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4395 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4398 // FIXME memcpy is used way more than necessary. Correctness first.
4399 // Note: "by value" is code for passing a structure by value, not
4401 if (Flags.isByVal()) {
4402 // Note: Size includes alignment padding, so
4403 // struct x { short a; char b; }
4404 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4405 // These are the proper values we need for right-justifying the
4406 // aggregate in a parameter register.
4407 unsigned Size = Flags.getByValSize();
4409 // An empty aggregate parameter takes up no storage and no
4414 // All aggregates smaller than 8 bytes must be passed right-justified.
4415 if (Size==1 || Size==2 || Size==4) {
4416 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4417 if (GPR_idx != NumGPRs) {
4418 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4419 MachinePointerInfo(), VT,
4420 false, false, false, 0);
4421 MemOpChains.push_back(Load.getValue(1));
4422 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Load));
4424 ArgOffset += PtrByteSize;
4429 if (GPR_idx == NumGPRs && Size < 8) {
4430 SDValue AddPtr = PtrOff;
4431 if (!isLittleEndian) {
4432 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4433 PtrOff.getValueType());
4434 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4436 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4439 ArgOffset += PtrByteSize;
4442 // Copy entire object into memory. There are cases where gcc-generated
4443 // code assumes it is there, even if it could be put entirely into
4444 // registers. (This is not what the doc says.)
4446 // FIXME: The above statement is likely due to a misunderstanding of the
4447 // documents. All arguments must be copied into the parameter area BY
4448 // THE CALLEE in the event that the callee takes the address of any
4449 // formal argument. That has not yet been implemented. However, it is
4450 // reasonable to use the stack area as a staging area for the register
4453 // Skip this for small aggregates, as we will use the same slot for a
4454 // right-justified copy, below.
4456 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4460 // When a register is available, pass a small aggregate right-justified.
4461 if (Size < 8 && GPR_idx != NumGPRs) {
4462 // The easiest way to get this right-justified in a register
4463 // is to copy the structure into the rightmost portion of a
4464 // local variable slot, then load the whole slot into the
4466 // FIXME: The memcpy seems to produce pretty awful code for
4467 // small aggregates, particularly for packed ones.
4468 // FIXME: It would be preferable to use the slot in the
4469 // parameter save area instead of a new local variable.
4470 SDValue AddPtr = PtrOff;
4471 if (!isLittleEndian) {
4472 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
4473 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4475 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4479 // Load the slot into the register.
4480 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
4481 MachinePointerInfo(),
4482 false, false, false, 0);
4483 MemOpChains.push_back(Load.getValue(1));
4484 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Load));
4486 // Done with this argument.
4487 ArgOffset += PtrByteSize;
4491 // For aggregates larger than PtrByteSize, copy the pieces of the
4492 // object that fit into registers from the parameter save area.
4493 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4494 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4495 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4496 if (GPR_idx != NumGPRs) {
4497 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4498 MachinePointerInfo(),
4499 false, false, false, 0);
4500 MemOpChains.push_back(Load.getValue(1));
4501 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4502 ArgOffset += PtrByteSize;
4504 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4511 switch (Arg.getSimpleValueType().SimpleTy) {
4512 default: llvm_unreachable("Unexpected ValueType for argument!");
4516 // These can be scalar arguments or elements of an integer array type
4517 // passed directly. Clang may use those instead of "byval" aggregate
4518 // types to avoid forcing arguments to memory unnecessarily.
4519 if (GPR_idx != NumGPRs) {
4520 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Arg));
4522 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4523 true, isTailCall, false, MemOpChains,
4524 TailCallArguments, dl);
4526 ArgOffset += PtrByteSize;
4530 // These can be scalar arguments or elements of a float array type
4531 // passed directly. The latter are used to implement ELFv2 homogenous
4532 // float aggregates.
4534 // Named arguments go into FPRs first, and once they overflow, the
4535 // remaining arguments go into GPRs and then the parameter save area.
4536 // Unnamed arguments for vararg functions always go to GPRs and
4537 // then the parameter save area. For now, put all arguments to vararg
4538 // routines always in both locations (FPR *and* GPR or stack slot).
4539 bool NeedGPROrStack = isVarArg || FPR_idx == NumFPRs;
4541 // First load the argument into the next available FPR.
4542 if (FPR_idx != NumFPRs)
4543 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4545 // Next, load the argument into GPR or stack slot if needed.
4546 if (!NeedGPROrStack)
4548 else if (GPR_idx != NumGPRs) {
4549 // In the non-vararg case, this can only ever happen in the
4550 // presence of f32 array types, since otherwise we never run
4551 // out of FPRs before running out of GPRs.
4554 // Double values are always passed in a single GPR.
4555 if (Arg.getValueType() != MVT::f32) {
4556 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
4558 // Non-array float values are extended and passed in a GPR.
4559 } else if (!Flags.isInConsecutiveRegs()) {
4560 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4561 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4563 // If we have an array of floats, we collect every odd element
4564 // together with its predecessor into one GPR.
4565 } else if (ArgOffset % PtrByteSize != 0) {
4567 Lo = DAG.getNode(ISD::BITCAST, dl, MVT::i32, OutVals[i - 1]);
4568 Hi = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4569 if (!isLittleEndian)
4571 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
4573 // The final element, if even, goes into the first half of a GPR.
4574 } else if (Flags.isInConsecutiveRegsLast()) {
4575 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4576 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4577 if (!isLittleEndian)
4578 ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal,
4579 DAG.getConstant(32, MVT::i32));
4581 // Non-final even elements are skipped; they will be handled
4582 // together the with subsequent argument on the next go-around.
4586 if (ArgVal.getNode())
4587 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], ArgVal));
4589 // Single-precision floating-point values are mapped to the
4590 // second (rightmost) word of the stack doubleword.
4591 if (Arg.getValueType() == MVT::f32 &&
4592 !isLittleEndian && !Flags.isInConsecutiveRegs()) {
4593 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4594 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4597 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4598 true, isTailCall, false, MemOpChains,
4599 TailCallArguments, dl);
4601 // When passing an array of floats, the array occupies consecutive
4602 // space in the argument area; only round up to the next doubleword
4603 // at the end of the array. Otherwise, each float takes 8 bytes.
4604 ArgOffset += (Arg.getValueType() == MVT::f32 &&
4605 Flags.isInConsecutiveRegs()) ? 4 : 8;
4606 if (Flags.isInConsecutiveRegsLast())
4607 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4616 // These can be scalar arguments or elements of a vector array type
4617 // passed directly. The latter are used to implement ELFv2 homogenous
4618 // vector aggregates.
4620 // For a varargs call, named arguments go into VRs or on the stack as
4621 // usual; unnamed arguments always go to the stack or the corresponding
4622 // GPRs when within range. For now, we always put the value in both
4623 // locations (or even all three).
4625 // We could elide this store in the case where the object fits
4626 // entirely in R registers. Maybe later.
4627 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4628 MachinePointerInfo(), false, false, 0);
4629 MemOpChains.push_back(Store);
4630 if (VR_idx != NumVRs) {
4631 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4632 MachinePointerInfo(),
4633 false, false, false, 0);
4634 MemOpChains.push_back(Load.getValue(1));
4636 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4637 Arg.getSimpleValueType() == MVT::v2i64) ?
4638 VSRH[VR_idx] : VR[VR_idx];
4641 RegsToPass.push_back(std::make_pair(VReg, Load));
4644 for (unsigned i=0; i<16; i+=PtrByteSize) {
4645 if (GPR_idx == NumGPRs)
4647 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4648 DAG.getConstant(i, PtrVT));
4649 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4650 false, false, false, 0);
4651 MemOpChains.push_back(Load.getValue(1));
4652 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4657 // Non-varargs Altivec params go into VRs or on the stack.
4658 if (VR_idx != NumVRs) {
4659 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4660 Arg.getSimpleValueType() == MVT::v2i64) ?
4661 VSRH[VR_idx] : VR[VR_idx];
4664 RegsToPass.push_back(std::make_pair(VReg, Arg));
4666 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4667 true, isTailCall, true, MemOpChains,
4668 TailCallArguments, dl);
4675 assert(NumBytesActuallyUsed == ArgOffset);
4676 (void)NumBytesActuallyUsed;
4678 if (!MemOpChains.empty())
4679 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4681 // Check if this is an indirect call (MTCTR/BCTRL).
4682 // See PrepareCall() for more information about calls through function
4683 // pointers in the 64-bit SVR4 ABI.
4684 if (!isTailCall && !IsPatchPoint &&
4685 !isFunctionGlobalAddress(Callee) &&
4686 !isa<ExternalSymbolSDNode>(Callee)) {
4687 // Load r2 into a virtual register and store it to the TOC save area.
4688 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4689 // TOC save area offset.
4690 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset(isELFv2ABI);
4691 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset);
4692 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4693 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr,
4694 MachinePointerInfo::getStack(TOCSaveOffset),
4696 // In the ELFv2 ABI, R12 must contain the address of an indirect callee.
4697 // This does not mean the MTCTR instruction must use R12; it's easier
4698 // to model this as an extra parameter, so do that.
4699 if (isELFv2ABI && !IsPatchPoint)
4700 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
4703 // Build a sequence of copy-to-reg nodes chained together with token chain
4704 // and flag operands which copy the outgoing args into the appropriate regs.
4706 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4707 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4708 RegsToPass[i].second, InFlag);
4709 InFlag = Chain.getValue(1);
4713 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4714 FPOp, true, TailCallArguments);
4716 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint, DAG,
4717 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
4718 NumBytes, Ins, InVals, CS);
4722 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4723 CallingConv::ID CallConv, bool isVarArg,
4724 bool isTailCall, bool IsPatchPoint,
4725 const SmallVectorImpl<ISD::OutputArg> &Outs,
4726 const SmallVectorImpl<SDValue> &OutVals,
4727 const SmallVectorImpl<ISD::InputArg> &Ins,
4728 SDLoc dl, SelectionDAG &DAG,
4729 SmallVectorImpl<SDValue> &InVals,
4730 ImmutableCallSite *CS) const {
4732 unsigned NumOps = Outs.size();
4734 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4735 bool isPPC64 = PtrVT == MVT::i64;
4736 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4738 MachineFunction &MF = DAG.getMachineFunction();
4740 // Mark this function as potentially containing a function that contains a
4741 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4742 // and restoring the callers stack pointer in this functions epilog. This is
4743 // done because by tail calling the called function might overwrite the value
4744 // in this function's (MF) stack pointer stack slot 0(SP).
4745 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4746 CallConv == CallingConv::Fast)
4747 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4749 // Count how many bytes are to be pushed on the stack, including the linkage
4750 // area, and parameter passing area. We start with 24/48 bytes, which is
4751 // prereserved space for [SP][CR][LR][3 x unused].
4752 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true,
4754 unsigned NumBytes = LinkageSize;
4756 // Add up all the space actually used.
4757 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
4758 // they all go in registers, but we must reserve stack space for them for
4759 // possible use by the caller. In varargs or 64-bit calls, parameters are
4760 // assigned stack space in order, with padding so Altivec parameters are
4762 unsigned nAltivecParamsAtEnd = 0;
4763 for (unsigned i = 0; i != NumOps; ++i) {
4764 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4765 EVT ArgVT = Outs[i].VT;
4766 // Varargs Altivec parameters are padded to a 16 byte boundary.
4767 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
4768 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
4769 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) {
4770 if (!isVarArg && !isPPC64) {
4771 // Non-varargs Altivec parameters go after all the non-Altivec
4772 // parameters; handle those later so we know how much padding we need.
4773 nAltivecParamsAtEnd++;
4776 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
4777 NumBytes = ((NumBytes+15)/16)*16;
4779 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4782 // Allow for Altivec parameters at the end, if needed.
4783 if (nAltivecParamsAtEnd) {
4784 NumBytes = ((NumBytes+15)/16)*16;
4785 NumBytes += 16*nAltivecParamsAtEnd;
4788 // The prolog code of the callee may store up to 8 GPR argument registers to
4789 // the stack, allowing va_start to index over them in memory if its varargs.
4790 // Because we cannot tell if this is needed on the caller side, we have to
4791 // conservatively assume that it is needed. As such, make sure we have at
4792 // least enough stack space for the caller to store the 8 GPRs.
4793 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4795 // Tail call needs the stack to be aligned.
4796 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4797 CallConv == CallingConv::Fast)
4798 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
4800 // Calculate by how many bytes the stack has to be adjusted in case of tail
4801 // call optimization.
4802 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4804 // To protect arguments on the stack from being clobbered in a tail call,
4805 // force all the loads to happen before doing any other lowering.
4807 Chain = DAG.getStackArgumentTokenFactor(Chain);
4809 // Adjust the stack pointer for the new arguments...
4810 // These operations are automatically eliminated by the prolog/epilog pass
4811 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4813 SDValue CallSeqStart = Chain;
4815 // Load the return address and frame pointer so it can be move somewhere else
4818 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4821 // Set up a copy of the stack pointer for use loading and storing any
4822 // arguments that may not fit in the registers available for argument
4826 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4828 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4830 // Figure out which arguments are going to go in registers, and which in
4831 // memory. Also, if this is a vararg function, floating point operations
4832 // must be stored to our stack, and loaded into integer regs as well, if
4833 // any integer regs are available for argument passing.
4834 unsigned ArgOffset = LinkageSize;
4835 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4837 static const MCPhysReg GPR_32[] = { // 32-bit registers.
4838 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4839 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4841 static const MCPhysReg GPR_64[] = { // 64-bit registers.
4842 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4843 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4845 static const MCPhysReg *FPR = GetFPR();
4847 static const MCPhysReg VR[] = {
4848 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4849 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4851 const unsigned NumGPRs = array_lengthof(GPR_32);
4852 const unsigned NumFPRs = 13;
4853 const unsigned NumVRs = array_lengthof(VR);
4855 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
4857 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4858 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4860 SmallVector<SDValue, 8> MemOpChains;
4861 for (unsigned i = 0; i != NumOps; ++i) {
4862 SDValue Arg = OutVals[i];
4863 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4865 // PtrOff will be used to store the current argument to the stack if a
4866 // register cannot be found for it.
4869 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4871 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4873 // On PPC64, promote integers to 64-bit values.
4874 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4875 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4876 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4877 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4880 // FIXME memcpy is used way more than necessary. Correctness first.
4881 // Note: "by value" is code for passing a structure by value, not
4883 if (Flags.isByVal()) {
4884 unsigned Size = Flags.getByValSize();
4885 // Very small objects are passed right-justified. Everything else is
4886 // passed left-justified.
4887 if (Size==1 || Size==2) {
4888 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4889 if (GPR_idx != NumGPRs) {
4890 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4891 MachinePointerInfo(), VT,
4892 false, false, false, 0);
4893 MemOpChains.push_back(Load.getValue(1));
4894 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4896 ArgOffset += PtrByteSize;
4898 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4899 PtrOff.getValueType());
4900 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4901 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4904 ArgOffset += PtrByteSize;
4908 // Copy entire object into memory. There are cases where gcc-generated
4909 // code assumes it is there, even if it could be put entirely into
4910 // registers. (This is not what the doc says.)
4911 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4915 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4916 // copy the pieces of the object that fit into registers from the
4917 // parameter save area.
4918 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4919 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4920 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4921 if (GPR_idx != NumGPRs) {
4922 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4923 MachinePointerInfo(),
4924 false, false, false, 0);
4925 MemOpChains.push_back(Load.getValue(1));
4926 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4927 ArgOffset += PtrByteSize;
4929 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4936 switch (Arg.getSimpleValueType().SimpleTy) {
4937 default: llvm_unreachable("Unexpected ValueType for argument!");
4941 if (GPR_idx != NumGPRs) {
4942 if (Arg.getValueType() == MVT::i1)
4943 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
4945 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4947 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4948 isPPC64, isTailCall, false, MemOpChains,
4949 TailCallArguments, dl);
4951 ArgOffset += PtrByteSize;
4955 if (FPR_idx != NumFPRs) {
4956 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4959 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4960 MachinePointerInfo(), false, false, 0);
4961 MemOpChains.push_back(Store);
4963 // Float varargs are always shadowed in available integer registers
4964 if (GPR_idx != NumGPRs) {
4965 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4966 MachinePointerInfo(), false, false,
4968 MemOpChains.push_back(Load.getValue(1));
4969 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4971 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4972 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4973 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4974 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4975 MachinePointerInfo(),
4976 false, false, false, 0);
4977 MemOpChains.push_back(Load.getValue(1));
4978 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4981 // If we have any FPRs remaining, we may also have GPRs remaining.
4982 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4984 if (GPR_idx != NumGPRs)
4986 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4987 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4991 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4992 isPPC64, isTailCall, false, MemOpChains,
4993 TailCallArguments, dl);
4997 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
5004 // These go aligned on the stack, or in the corresponding R registers
5005 // when within range. The Darwin PPC ABI doc claims they also go in
5006 // V registers; in fact gcc does this only for arguments that are
5007 // prototyped, not for those that match the ... We do it for all
5008 // arguments, seems to work.
5009 while (ArgOffset % 16 !=0) {
5010 ArgOffset += PtrByteSize;
5011 if (GPR_idx != NumGPRs)
5014 // We could elide this store in the case where the object fits
5015 // entirely in R registers. Maybe later.
5016 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
5017 DAG.getConstant(ArgOffset, PtrVT));
5018 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5019 MachinePointerInfo(), false, false, 0);
5020 MemOpChains.push_back(Store);
5021 if (VR_idx != NumVRs) {
5022 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
5023 MachinePointerInfo(),
5024 false, false, false, 0);
5025 MemOpChains.push_back(Load.getValue(1));
5026 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
5029 for (unsigned i=0; i<16; i+=PtrByteSize) {
5030 if (GPR_idx == NumGPRs)
5032 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5033 DAG.getConstant(i, PtrVT));
5034 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5035 false, false, false, 0);
5036 MemOpChains.push_back(Load.getValue(1));
5037 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5042 // Non-varargs Altivec params generally go in registers, but have
5043 // stack space allocated at the end.
5044 if (VR_idx != NumVRs) {
5045 // Doesn't have GPR space allocated.
5046 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
5047 } else if (nAltivecParamsAtEnd==0) {
5048 // We are emitting Altivec params in order.
5049 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5050 isPPC64, isTailCall, true, MemOpChains,
5051 TailCallArguments, dl);
5057 // If all Altivec parameters fit in registers, as they usually do,
5058 // they get stack space following the non-Altivec parameters. We
5059 // don't track this here because nobody below needs it.
5060 // If there are more Altivec parameters than fit in registers emit
5062 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
5064 // Offset is aligned; skip 1st 12 params which go in V registers.
5065 ArgOffset = ((ArgOffset+15)/16)*16;
5067 for (unsigned i = 0; i != NumOps; ++i) {
5068 SDValue Arg = OutVals[i];
5069 EVT ArgType = Outs[i].VT;
5070 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
5071 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
5074 // We are emitting Altivec params in order.
5075 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5076 isPPC64, isTailCall, true, MemOpChains,
5077 TailCallArguments, dl);
5084 if (!MemOpChains.empty())
5085 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5087 // On Darwin, R12 must contain the address of an indirect callee. This does
5088 // not mean the MTCTR instruction must use R12; it's easier to model this as
5089 // an extra parameter, so do that.
5091 !isFunctionGlobalAddress(Callee) &&
5092 !isa<ExternalSymbolSDNode>(Callee) &&
5093 !isBLACompatibleAddress(Callee, DAG))
5094 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
5095 PPC::R12), Callee));
5097 // Build a sequence of copy-to-reg nodes chained together with token chain
5098 // and flag operands which copy the outgoing args into the appropriate regs.
5100 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5101 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5102 RegsToPass[i].second, InFlag);
5103 InFlag = Chain.getValue(1);
5107 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
5108 FPOp, true, TailCallArguments);
5110 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint, DAG,
5111 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
5112 NumBytes, Ins, InVals, CS);
5116 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
5117 MachineFunction &MF, bool isVarArg,
5118 const SmallVectorImpl<ISD::OutputArg> &Outs,
5119 LLVMContext &Context) const {
5120 SmallVector<CCValAssign, 16> RVLocs;
5121 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
5122 return CCInfo.CheckReturn(Outs, RetCC_PPC);
5126 PPCTargetLowering::LowerReturn(SDValue Chain,
5127 CallingConv::ID CallConv, bool isVarArg,
5128 const SmallVectorImpl<ISD::OutputArg> &Outs,
5129 const SmallVectorImpl<SDValue> &OutVals,
5130 SDLoc dl, SelectionDAG &DAG) const {
5132 SmallVector<CCValAssign, 16> RVLocs;
5133 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
5135 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
5138 SmallVector<SDValue, 4> RetOps(1, Chain);
5140 // Copy the result values into the output registers.
5141 for (unsigned i = 0; i != RVLocs.size(); ++i) {
5142 CCValAssign &VA = RVLocs[i];
5143 assert(VA.isRegLoc() && "Can only return in registers!");
5145 SDValue Arg = OutVals[i];
5147 switch (VA.getLocInfo()) {
5148 default: llvm_unreachable("Unknown loc info!");
5149 case CCValAssign::Full: break;
5150 case CCValAssign::AExt:
5151 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
5153 case CCValAssign::ZExt:
5154 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
5156 case CCValAssign::SExt:
5157 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
5161 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
5162 Flag = Chain.getValue(1);
5163 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
5166 RetOps[0] = Chain; // Update chain.
5168 // Add the flag if we have it.
5170 RetOps.push_back(Flag);
5172 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
5175 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
5176 const PPCSubtarget &Subtarget) const {
5177 // When we pop the dynamic allocation we need to restore the SP link.
5180 // Get the corect type for pointers.
5181 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5183 // Construct the stack pointer operand.
5184 bool isPPC64 = Subtarget.isPPC64();
5185 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
5186 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
5188 // Get the operands for the STACKRESTORE.
5189 SDValue Chain = Op.getOperand(0);
5190 SDValue SaveSP = Op.getOperand(1);
5192 // Load the old link SP.
5193 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
5194 MachinePointerInfo(),
5195 false, false, false, 0);
5197 // Restore the stack pointer.
5198 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
5200 // Store the old link SP.
5201 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
5208 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
5209 MachineFunction &MF = DAG.getMachineFunction();
5210 bool isPPC64 = Subtarget.isPPC64();
5211 bool isDarwinABI = Subtarget.isDarwinABI();
5212 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5214 // Get current frame pointer save index. The users of this index will be
5215 // primarily DYNALLOC instructions.
5216 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5217 int RASI = FI->getReturnAddrSaveIndex();
5219 // If the frame pointer save index hasn't been defined yet.
5221 // Find out what the fix offset of the frame pointer save area.
5222 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
5223 // Allocate the frame index for frame pointer save area.
5224 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, false);
5226 FI->setReturnAddrSaveIndex(RASI);
5228 return DAG.getFrameIndex(RASI, PtrVT);
5232 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
5233 MachineFunction &MF = DAG.getMachineFunction();
5234 bool isPPC64 = Subtarget.isPPC64();
5235 bool isDarwinABI = Subtarget.isDarwinABI();
5236 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5238 // Get current frame pointer save index. The users of this index will be
5239 // primarily DYNALLOC instructions.
5240 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5241 int FPSI = FI->getFramePointerSaveIndex();
5243 // If the frame pointer save index hasn't been defined yet.
5245 // Find out what the fix offset of the frame pointer save area.
5246 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
5249 // Allocate the frame index for frame pointer save area.
5250 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
5252 FI->setFramePointerSaveIndex(FPSI);
5254 return DAG.getFrameIndex(FPSI, PtrVT);
5257 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5259 const PPCSubtarget &Subtarget) const {
5261 SDValue Chain = Op.getOperand(0);
5262 SDValue Size = Op.getOperand(1);
5265 // Get the corect type for pointers.
5266 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5268 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
5269 DAG.getConstant(0, PtrVT), Size);
5270 // Construct a node for the frame pointer save index.
5271 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
5272 // Build a DYNALLOC node.
5273 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
5274 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
5275 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
5278 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
5279 SelectionDAG &DAG) const {
5281 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
5282 DAG.getVTList(MVT::i32, MVT::Other),
5283 Op.getOperand(0), Op.getOperand(1));
5286 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
5287 SelectionDAG &DAG) const {
5289 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
5290 Op.getOperand(0), Op.getOperand(1));
5293 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
5294 assert(Op.getValueType() == MVT::i1 &&
5295 "Custom lowering only for i1 loads");
5297 // First, load 8 bits into 32 bits, then truncate to 1 bit.
5300 LoadSDNode *LD = cast<LoadSDNode>(Op);
5302 SDValue Chain = LD->getChain();
5303 SDValue BasePtr = LD->getBasePtr();
5304 MachineMemOperand *MMO = LD->getMemOperand();
5306 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(), Chain,
5307 BasePtr, MVT::i8, MMO);
5308 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
5310 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
5311 return DAG.getMergeValues(Ops, dl);
5314 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
5315 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
5316 "Custom lowering only for i1 stores");
5318 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
5321 StoreSDNode *ST = cast<StoreSDNode>(Op);
5323 SDValue Chain = ST->getChain();
5324 SDValue BasePtr = ST->getBasePtr();
5325 SDValue Value = ST->getValue();
5326 MachineMemOperand *MMO = ST->getMemOperand();
5328 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(), Value);
5329 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
5332 // FIXME: Remove this once the ANDI glue bug is fixed:
5333 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
5334 assert(Op.getValueType() == MVT::i1 &&
5335 "Custom lowering only for i1 results");
5338 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
5342 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
5344 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5345 // Not FP? Not a fsel.
5346 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
5347 !Op.getOperand(2).getValueType().isFloatingPoint())
5350 // We might be able to do better than this under some circumstances, but in
5351 // general, fsel-based lowering of select is a finite-math-only optimization.
5352 // For more information, see section F.3 of the 2.06 ISA specification.
5353 if (!DAG.getTarget().Options.NoInfsFPMath ||
5354 !DAG.getTarget().Options.NoNaNsFPMath)
5357 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5359 EVT ResVT = Op.getValueType();
5360 EVT CmpVT = Op.getOperand(0).getValueType();
5361 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5362 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
5365 // If the RHS of the comparison is a 0.0, we don't need to do the
5366 // subtraction at all.
5368 if (isFloatingPointZero(RHS))
5370 default: break; // SETUO etc aren't handled by fsel.
5374 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5375 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5376 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5377 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5378 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5379 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5380 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
5383 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5386 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5387 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5388 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5391 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5394 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5395 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5396 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5397 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
5402 default: break; // SETUO etc aren't handled by fsel.
5406 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5407 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5408 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5409 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5410 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5411 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5412 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5413 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
5416 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5417 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5418 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5419 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5422 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5423 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5424 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5425 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5428 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5429 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5430 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5431 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5434 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5435 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5436 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5437 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5442 void PPCTargetLowering::LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
5445 assert(Op.getOperand(0).getValueType().isFloatingPoint());
5446 SDValue Src = Op.getOperand(0);
5447 if (Src.getValueType() == MVT::f32)
5448 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
5451 switch (Op.getSimpleValueType().SimpleTy) {
5452 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
5454 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
5455 (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ :
5460 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
5461 "i64 FP_TO_UINT is supported only with FPCVT");
5462 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
5468 // Convert the FP value to an int value through memory.
5469 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
5470 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
5471 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
5472 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
5473 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
5475 // Emit a store to the stack slot.
5478 MachineFunction &MF = DAG.getMachineFunction();
5479 MachineMemOperand *MMO =
5480 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
5481 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
5482 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
5483 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
5485 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
5486 MPI, false, false, 0);
5488 // Result is a load from the stack slot. If loading 4 bytes, make sure to
5490 if (Op.getValueType() == MVT::i32 && !i32Stack) {
5491 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
5492 DAG.getConstant(4, FIPtr.getValueType()));
5493 MPI = MPI.getWithOffset(4);
5501 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
5504 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
5506 return DAG.getLoad(Op.getValueType(), dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
5507 false, RLI.IsInvariant, RLI.Alignment, RLI.AAInfo,
5511 // We're trying to insert a regular store, S, and then a load, L. If the
5512 // incoming value, O, is a load, we might just be able to have our load use the
5513 // address used by O. However, we don't know if anything else will store to
5514 // that address before we can load from it. To prevent this situation, we need
5515 // to insert our load, L, into the chain as a peer of O. To do this, we give L
5516 // the same chain operand as O, we create a token factor from the chain results
5517 // of O and L, and we replace all uses of O's chain result with that token
5518 // factor (see spliceIntoChain below for this last part).
5519 bool PPCTargetLowering::canReuseLoadAddress(SDValue Op, EVT MemVT,
5522 ISD::LoadExtType ET) const {
5524 if (ET == ISD::NON_EXTLOAD &&
5525 (Op.getOpcode() == ISD::FP_TO_UINT ||
5526 Op.getOpcode() == ISD::FP_TO_SINT) &&
5527 isOperationLegalOrCustom(Op.getOpcode(),
5528 Op.getOperand(0).getValueType())) {
5530 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
5534 LoadSDNode *LD = dyn_cast<LoadSDNode>(Op);
5535 if (!LD || LD->getExtensionType() != ET || LD->isVolatile() ||
5536 LD->isNonTemporal())
5538 if (LD->getMemoryVT() != MemVT)
5541 RLI.Ptr = LD->getBasePtr();
5542 if (LD->isIndexed() && LD->getOffset().getOpcode() != ISD::UNDEF) {
5543 assert(LD->getAddressingMode() == ISD::PRE_INC &&
5544 "Non-pre-inc AM on PPC?");
5545 RLI.Ptr = DAG.getNode(ISD::ADD, dl, RLI.Ptr.getValueType(), RLI.Ptr,
5549 RLI.Chain = LD->getChain();
5550 RLI.MPI = LD->getPointerInfo();
5551 RLI.IsInvariant = LD->isInvariant();
5552 RLI.Alignment = LD->getAlignment();
5553 RLI.AAInfo = LD->getAAInfo();
5554 RLI.Ranges = LD->getRanges();
5556 RLI.ResChain = SDValue(LD, LD->isIndexed() ? 2 : 1);
5560 // Given the head of the old chain, ResChain, insert a token factor containing
5561 // it and NewResChain, and make users of ResChain now be users of that token
5563 void PPCTargetLowering::spliceIntoChain(SDValue ResChain,
5564 SDValue NewResChain,
5565 SelectionDAG &DAG) const {
5569 SDLoc dl(NewResChain);
5571 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
5572 NewResChain, DAG.getUNDEF(MVT::Other));
5573 assert(TF.getNode() != NewResChain.getNode() &&
5574 "A new TF really is required here");
5576 DAG.ReplaceAllUsesOfValueWith(ResChain, TF);
5577 DAG.UpdateNodeOperands(TF.getNode(), ResChain, NewResChain);
5580 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
5581 SelectionDAG &DAG) const {
5583 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
5584 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
5587 if (Op.getOperand(0).getValueType() == MVT::i1)
5588 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
5589 DAG.getConstantFP(1.0, Op.getValueType()),
5590 DAG.getConstantFP(0.0, Op.getValueType()));
5592 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
5593 "UINT_TO_FP is supported only with FPCVT");
5595 // If we have FCFIDS, then use it when converting to single-precision.
5596 // Otherwise, convert to double-precision and then round.
5597 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5598 (Op.getOpcode() == ISD::UINT_TO_FP ?
5599 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
5600 (Op.getOpcode() == ISD::UINT_TO_FP ?
5601 PPCISD::FCFIDU : PPCISD::FCFID);
5602 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5603 MVT::f32 : MVT::f64;
5605 if (Op.getOperand(0).getValueType() == MVT::i64) {
5606 SDValue SINT = Op.getOperand(0);
5607 // When converting to single-precision, we actually need to convert
5608 // to double-precision first and then round to single-precision.
5609 // To avoid double-rounding effects during that operation, we have
5610 // to prepare the input operand. Bits that might be truncated when
5611 // converting to double-precision are replaced by a bit that won't
5612 // be lost at this stage, but is below the single-precision rounding
5615 // However, if -enable-unsafe-fp-math is in effect, accept double
5616 // rounding to avoid the extra overhead.
5617 if (Op.getValueType() == MVT::f32 &&
5618 !Subtarget.hasFPCVT() &&
5619 !DAG.getTarget().Options.UnsafeFPMath) {
5621 // Twiddle input to make sure the low 11 bits are zero. (If this
5622 // is the case, we are guaranteed the value will fit into the 53 bit
5623 // mantissa of an IEEE double-precision value without rounding.)
5624 // If any of those low 11 bits were not zero originally, make sure
5625 // bit 12 (value 2048) is set instead, so that the final rounding
5626 // to single-precision gets the correct result.
5627 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5628 SINT, DAG.getConstant(2047, MVT::i64));
5629 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
5630 Round, DAG.getConstant(2047, MVT::i64));
5631 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
5632 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5633 Round, DAG.getConstant(-2048, MVT::i64));
5635 // However, we cannot use that value unconditionally: if the magnitude
5636 // of the input value is small, the bit-twiddling we did above might
5637 // end up visibly changing the output. Fortunately, in that case, we
5638 // don't need to twiddle bits since the original input will convert
5639 // exactly to double-precision floating-point already. Therefore,
5640 // construct a conditional to use the original value if the top 11
5641 // bits are all sign-bit copies, and use the rounded value computed
5643 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
5644 SINT, DAG.getConstant(53, MVT::i32));
5645 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
5646 Cond, DAG.getConstant(1, MVT::i64));
5647 Cond = DAG.getSetCC(dl, MVT::i32,
5648 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
5650 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
5656 MachineFunction &MF = DAG.getMachineFunction();
5657 if (canReuseLoadAddress(SINT, MVT::i64, RLI, DAG)) {
5658 Bits = DAG.getLoad(MVT::f64, dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
5659 false, RLI.IsInvariant, RLI.Alignment, RLI.AAInfo,
5661 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
5662 } else if (Subtarget.hasLFIWAX() &&
5663 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::SEXTLOAD)) {
5664 MachineMemOperand *MMO =
5665 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
5666 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
5667 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
5668 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWAX, dl,
5669 DAG.getVTList(MVT::f64, MVT::Other),
5670 Ops, MVT::i32, MMO);
5671 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
5672 } else if (Subtarget.hasFPCVT() &&
5673 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::ZEXTLOAD)) {
5674 MachineMemOperand *MMO =
5675 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
5676 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
5677 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
5678 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWZX, dl,
5679 DAG.getVTList(MVT::f64, MVT::Other),
5680 Ops, MVT::i32, MMO);
5681 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
5682 } else if (((Subtarget.hasLFIWAX() &&
5683 SINT.getOpcode() == ISD::SIGN_EXTEND) ||
5684 (Subtarget.hasFPCVT() &&
5685 SINT.getOpcode() == ISD::ZERO_EXTEND)) &&
5686 SINT.getOperand(0).getValueType() == MVT::i32) {
5687 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
5688 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5690 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
5691 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5694 DAG.getStore(DAG.getEntryNode(), dl, SINT.getOperand(0), FIdx,
5695 MachinePointerInfo::getFixedStack(FrameIdx),
5698 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
5699 "Expected an i32 store");
5703 RLI.MPI = MachinePointerInfo::getFixedStack(FrameIdx);
5706 MachineMemOperand *MMO =
5707 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
5708 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
5709 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
5710 Bits = DAG.getMemIntrinsicNode(SINT.getOpcode() == ISD::ZERO_EXTEND ?
5711 PPCISD::LFIWZX : PPCISD::LFIWAX,
5712 dl, DAG.getVTList(MVT::f64, MVT::Other),
5713 Ops, MVT::i32, MMO);
5715 Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
5717 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
5719 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5720 FP = DAG.getNode(ISD::FP_ROUND, dl,
5721 MVT::f32, FP, DAG.getIntPtrConstant(0));
5725 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
5726 "Unhandled INT_TO_FP type in custom expander!");
5727 // Since we only generate this in 64-bit mode, we can take advantage of
5728 // 64-bit registers. In particular, sign extend the input value into the
5729 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
5730 // then lfd it and fcfid it.
5731 MachineFunction &MF = DAG.getMachineFunction();
5732 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
5733 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5736 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
5739 if (!(ReusingLoad = canReuseLoadAddress(Op.getOperand(0), MVT::i32, RLI,
5741 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
5742 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5744 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
5745 MachinePointerInfo::getFixedStack(FrameIdx),
5748 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
5749 "Expected an i32 store");
5753 RLI.MPI = MachinePointerInfo::getFixedStack(FrameIdx);
5757 MachineMemOperand *MMO =
5758 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
5759 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
5760 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
5761 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
5762 PPCISD::LFIWZX : PPCISD::LFIWAX,
5763 dl, DAG.getVTList(MVT::f64, MVT::Other),
5764 Ops, MVT::i32, MMO);
5766 spliceIntoChain(RLI.ResChain, Ld.getValue(1), DAG);
5768 assert(Subtarget.isPPC64() &&
5769 "i32->FP without LFIWAX supported only on PPC64");
5771 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
5772 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5774 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
5777 // STD the extended value into the stack slot.
5778 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
5779 MachinePointerInfo::getFixedStack(FrameIdx),
5782 // Load the value as a double.
5783 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
5784 MachinePointerInfo::getFixedStack(FrameIdx),
5785 false, false, false, 0);
5788 // FCFID it and return it.
5789 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
5790 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5791 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
5795 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
5796 SelectionDAG &DAG) const {
5799 The rounding mode is in bits 30:31 of FPSR, and has the following
5806 FLT_ROUNDS, on the other hand, expects the following:
5813 To perform the conversion, we do:
5814 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
5817 MachineFunction &MF = DAG.getMachineFunction();
5818 EVT VT = Op.getValueType();
5819 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5821 // Save FP Control Word to register
5823 MVT::f64, // return register
5824 MVT::Glue // unused in this context
5826 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
5828 // Save FP register to stack slot
5829 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5830 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
5831 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
5832 StackSlot, MachinePointerInfo(), false, false,0);
5834 // Load FP Control Word from low 32 bits of stack slot.
5835 SDValue Four = DAG.getConstant(4, PtrVT);
5836 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
5837 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
5838 false, false, false, 0);
5840 // Transform as necessary
5842 DAG.getNode(ISD::AND, dl, MVT::i32,
5843 CWD, DAG.getConstant(3, MVT::i32));
5845 DAG.getNode(ISD::SRL, dl, MVT::i32,
5846 DAG.getNode(ISD::AND, dl, MVT::i32,
5847 DAG.getNode(ISD::XOR, dl, MVT::i32,
5848 CWD, DAG.getConstant(3, MVT::i32)),
5849 DAG.getConstant(3, MVT::i32)),
5850 DAG.getConstant(1, MVT::i32));
5853 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
5855 return DAG.getNode((VT.getSizeInBits() < 16 ?
5856 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
5859 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5860 EVT VT = Op.getValueType();
5861 unsigned BitWidth = VT.getSizeInBits();
5863 assert(Op.getNumOperands() == 3 &&
5864 VT == Op.getOperand(1).getValueType() &&
5867 // Expand into a bunch of logical ops. Note that these ops
5868 // depend on the PPC behavior for oversized shift amounts.
5869 SDValue Lo = Op.getOperand(0);
5870 SDValue Hi = Op.getOperand(1);
5871 SDValue Amt = Op.getOperand(2);
5872 EVT AmtVT = Amt.getValueType();
5874 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5875 DAG.getConstant(BitWidth, AmtVT), Amt);
5876 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
5877 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5878 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5879 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5880 DAG.getConstant(-BitWidth, AmtVT));
5881 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5882 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5883 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
5884 SDValue OutOps[] = { OutLo, OutHi };
5885 return DAG.getMergeValues(OutOps, dl);
5888 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5889 EVT VT = Op.getValueType();
5891 unsigned BitWidth = VT.getSizeInBits();
5892 assert(Op.getNumOperands() == 3 &&
5893 VT == Op.getOperand(1).getValueType() &&
5896 // Expand into a bunch of logical ops. Note that these ops
5897 // depend on the PPC behavior for oversized shift amounts.
5898 SDValue Lo = Op.getOperand(0);
5899 SDValue Hi = Op.getOperand(1);
5900 SDValue Amt = Op.getOperand(2);
5901 EVT AmtVT = Amt.getValueType();
5903 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5904 DAG.getConstant(BitWidth, AmtVT), Amt);
5905 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5906 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5907 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5908 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5909 DAG.getConstant(-BitWidth, AmtVT));
5910 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
5911 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5912 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
5913 SDValue OutOps[] = { OutLo, OutHi };
5914 return DAG.getMergeValues(OutOps, dl);
5917 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
5919 EVT VT = Op.getValueType();
5920 unsigned BitWidth = VT.getSizeInBits();
5921 assert(Op.getNumOperands() == 3 &&
5922 VT == Op.getOperand(1).getValueType() &&
5925 // Expand into a bunch of logical ops, followed by a select_cc.
5926 SDValue Lo = Op.getOperand(0);
5927 SDValue Hi = Op.getOperand(1);
5928 SDValue Amt = Op.getOperand(2);
5929 EVT AmtVT = Amt.getValueType();
5931 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5932 DAG.getConstant(BitWidth, AmtVT), Amt);
5933 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5934 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5935 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5936 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5937 DAG.getConstant(-BitWidth, AmtVT));
5938 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
5939 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
5940 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
5941 Tmp4, Tmp6, ISD::SETLE);
5942 SDValue OutOps[] = { OutLo, OutHi };
5943 return DAG.getMergeValues(OutOps, dl);
5946 //===----------------------------------------------------------------------===//
5947 // Vector related lowering.
5950 /// BuildSplatI - Build a canonical splati of Val with an element size of
5951 /// SplatSize. Cast the result to VT.
5952 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
5953 SelectionDAG &DAG, SDLoc dl) {
5954 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
5956 static const EVT VTys[] = { // canonical VT to use for each size.
5957 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
5960 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
5962 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
5966 EVT CanonicalVT = VTys[SplatSize-1];
5968 // Build a canonical splat for this value.
5969 SDValue Elt = DAG.getConstant(Val, MVT::i32);
5970 SmallVector<SDValue, 8> Ops;
5971 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
5972 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
5973 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
5976 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
5977 /// specified intrinsic ID.
5978 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
5979 SelectionDAG &DAG, SDLoc dl,
5980 EVT DestVT = MVT::Other) {
5981 if (DestVT == MVT::Other) DestVT = Op.getValueType();
5982 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5983 DAG.getConstant(IID, MVT::i32), Op);
5986 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
5987 /// specified intrinsic ID.
5988 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
5989 SelectionDAG &DAG, SDLoc dl,
5990 EVT DestVT = MVT::Other) {
5991 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
5992 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5993 DAG.getConstant(IID, MVT::i32), LHS, RHS);
5996 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
5997 /// specified intrinsic ID.
5998 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
5999 SDValue Op2, SelectionDAG &DAG,
6000 SDLoc dl, EVT DestVT = MVT::Other) {
6001 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
6002 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6003 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
6007 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
6008 /// amount. The result has the specified value type.
6009 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
6010 EVT VT, SelectionDAG &DAG, SDLoc dl) {
6011 // Force LHS/RHS to be the right type.
6012 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
6013 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
6016 for (unsigned i = 0; i != 16; ++i)
6018 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
6019 return DAG.getNode(ISD::BITCAST, dl, VT, T);
6022 // If this is a case we can't handle, return null and let the default
6023 // expansion code take care of it. If we CAN select this case, and if it
6024 // selects to a single instruction, return Op. Otherwise, if we can codegen
6025 // this case more efficiently than a constant pool load, lower it to the
6026 // sequence of ops that should be used.
6027 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
6028 SelectionDAG &DAG) const {
6030 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6031 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
6033 // Check if this is a splat of a constant value.
6034 APInt APSplatBits, APSplatUndef;
6035 unsigned SplatBitSize;
6037 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
6038 HasAnyUndefs, 0, true) || SplatBitSize > 32)
6041 unsigned SplatBits = APSplatBits.getZExtValue();
6042 unsigned SplatUndef = APSplatUndef.getZExtValue();
6043 unsigned SplatSize = SplatBitSize / 8;
6045 // First, handle single instruction cases.
6048 if (SplatBits == 0) {
6049 // Canonicalize all zero vectors to be v4i32.
6050 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
6051 SDValue Z = DAG.getConstant(0, MVT::i32);
6052 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
6053 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
6058 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
6059 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
6061 if (SextVal >= -16 && SextVal <= 15)
6062 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
6065 // Two instruction sequences.
6067 // If this value is in the range [-32,30] and is even, use:
6068 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
6069 // If this value is in the range [17,31] and is odd, use:
6070 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
6071 // If this value is in the range [-31,-17] and is odd, use:
6072 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
6073 // Note the last two are three-instruction sequences.
6074 if (SextVal >= -32 && SextVal <= 31) {
6075 // To avoid having these optimizations undone by constant folding,
6076 // we convert to a pseudo that will be expanded later into one of
6078 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
6079 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
6080 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
6081 SDValue EltSize = DAG.getConstant(SplatSize, MVT::i32);
6082 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
6083 if (VT == Op.getValueType())
6086 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
6089 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
6090 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
6092 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
6093 // Make -1 and vspltisw -1:
6094 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
6096 // Make the VSLW intrinsic, computing 0x8000_0000.
6097 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
6100 // xor by OnesV to invert it.
6101 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
6102 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6105 // The remaining cases assume either big endian element order or
6106 // a splat-size that equates to the element size of the vector
6107 // to be built. An example that doesn't work for little endian is
6108 // {0, -1, 0, -1, 0, -1, 0, -1} which has a splat size of 32 bits
6109 // and a vector element size of 16 bits. The code below will
6110 // produce the vector in big endian element order, which for little
6111 // endian is {-1, 0, -1, 0, -1, 0, -1, 0}.
6113 // For now, just avoid these optimizations in that case.
6114 // FIXME: Develop correct optimizations for LE with mismatched
6115 // splat and element sizes.
6117 if (Subtarget.isLittleEndian() &&
6118 SplatSize != Op.getValueType().getVectorElementType().getSizeInBits())
6121 // Check to see if this is a wide variety of vsplti*, binop self cases.
6122 static const signed char SplatCsts[] = {
6123 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
6124 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
6127 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
6128 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
6129 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
6130 int i = SplatCsts[idx];
6132 // Figure out what shift amount will be used by altivec if shifted by i in
6134 unsigned TypeShiftAmt = i & (SplatBitSize-1);
6136 // vsplti + shl self.
6137 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
6138 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6139 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6140 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
6141 Intrinsic::ppc_altivec_vslw
6143 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6144 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6147 // vsplti + srl self.
6148 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
6149 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6150 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6151 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
6152 Intrinsic::ppc_altivec_vsrw
6154 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6155 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6158 // vsplti + sra self.
6159 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
6160 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6161 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6162 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
6163 Intrinsic::ppc_altivec_vsraw
6165 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6166 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6169 // vsplti + rol self.
6170 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
6171 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
6172 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6173 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6174 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
6175 Intrinsic::ppc_altivec_vrlw
6177 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6178 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6181 // t = vsplti c, result = vsldoi t, t, 1
6182 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
6183 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
6184 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
6186 // t = vsplti c, result = vsldoi t, t, 2
6187 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
6188 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
6189 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
6191 // t = vsplti c, result = vsldoi t, t, 3
6192 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
6193 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
6194 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
6201 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
6202 /// the specified operations to build the shuffle.
6203 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
6204 SDValue RHS, SelectionDAG &DAG,
6206 unsigned OpNum = (PFEntry >> 26) & 0x0F;
6207 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
6208 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
6211 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
6223 if (OpNum == OP_COPY) {
6224 if (LHSID == (1*9+2)*9+3) return LHS;
6225 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
6229 SDValue OpLHS, OpRHS;
6230 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
6231 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
6235 default: llvm_unreachable("Unknown i32 permute!");
6237 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
6238 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
6239 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
6240 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
6243 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
6244 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
6245 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
6246 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
6249 for (unsigned i = 0; i != 16; ++i)
6250 ShufIdxs[i] = (i&3)+0;
6253 for (unsigned i = 0; i != 16; ++i)
6254 ShufIdxs[i] = (i&3)+4;
6257 for (unsigned i = 0; i != 16; ++i)
6258 ShufIdxs[i] = (i&3)+8;
6261 for (unsigned i = 0; i != 16; ++i)
6262 ShufIdxs[i] = (i&3)+12;
6265 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
6267 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
6269 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
6271 EVT VT = OpLHS.getValueType();
6272 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
6273 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
6274 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
6275 return DAG.getNode(ISD::BITCAST, dl, VT, T);
6278 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
6279 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
6280 /// return the code it can be lowered into. Worst case, it can always be
6281 /// lowered into a vperm.
6282 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
6283 SelectionDAG &DAG) const {
6285 SDValue V1 = Op.getOperand(0);
6286 SDValue V2 = Op.getOperand(1);
6287 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6288 EVT VT = Op.getValueType();
6289 bool isLittleEndian = Subtarget.isLittleEndian();
6291 // Cases that are handled by instructions that take permute immediates
6292 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
6293 // selected by the instruction selector.
6294 if (V2.getOpcode() == ISD::UNDEF) {
6295 if (PPC::isSplatShuffleMask(SVOp, 1) ||
6296 PPC::isSplatShuffleMask(SVOp, 2) ||
6297 PPC::isSplatShuffleMask(SVOp, 4) ||
6298 PPC::isVPKUWUMShuffleMask(SVOp, 1, DAG) ||
6299 PPC::isVPKUHUMShuffleMask(SVOp, 1, DAG) ||
6300 PPC::isVSLDOIShuffleMask(SVOp, 1, DAG) != -1 ||
6301 PPC::isVMRGLShuffleMask(SVOp, 1, 1, DAG) ||
6302 PPC::isVMRGLShuffleMask(SVOp, 2, 1, DAG) ||
6303 PPC::isVMRGLShuffleMask(SVOp, 4, 1, DAG) ||
6304 PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) ||
6305 PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) ||
6306 PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG)) {
6311 // Altivec has a variety of "shuffle immediates" that take two vector inputs
6312 // and produce a fixed permutation. If any of these match, do not lower to
6314 unsigned int ShuffleKind = isLittleEndian ? 2 : 0;
6315 if (PPC::isVPKUWUMShuffleMask(SVOp, ShuffleKind, DAG) ||
6316 PPC::isVPKUHUMShuffleMask(SVOp, ShuffleKind, DAG) ||
6317 PPC::isVSLDOIShuffleMask(SVOp, ShuffleKind, DAG) != -1 ||
6318 PPC::isVMRGLShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6319 PPC::isVMRGLShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6320 PPC::isVMRGLShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
6321 PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6322 PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6323 PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG))
6326 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
6327 // perfect shuffle table to emit an optimal matching sequence.
6328 ArrayRef<int> PermMask = SVOp->getMask();
6330 unsigned PFIndexes[4];
6331 bool isFourElementShuffle = true;
6332 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
6333 unsigned EltNo = 8; // Start out undef.
6334 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
6335 if (PermMask[i*4+j] < 0)
6336 continue; // Undef, ignore it.
6338 unsigned ByteSource = PermMask[i*4+j];
6339 if ((ByteSource & 3) != j) {
6340 isFourElementShuffle = false;
6345 EltNo = ByteSource/4;
6346 } else if (EltNo != ByteSource/4) {
6347 isFourElementShuffle = false;
6351 PFIndexes[i] = EltNo;
6354 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
6355 // perfect shuffle vector to determine if it is cost effective to do this as
6356 // discrete instructions, or whether we should use a vperm.
6357 // For now, we skip this for little endian until such time as we have a
6358 // little-endian perfect shuffle table.
6359 if (isFourElementShuffle && !isLittleEndian) {
6360 // Compute the index in the perfect shuffle table.
6361 unsigned PFTableIndex =
6362 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
6364 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6365 unsigned Cost = (PFEntry >> 30);
6367 // Determining when to avoid vperm is tricky. Many things affect the cost
6368 // of vperm, particularly how many times the perm mask needs to be computed.
6369 // For example, if the perm mask can be hoisted out of a loop or is already
6370 // used (perhaps because there are multiple permutes with the same shuffle
6371 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
6372 // the loop requires an extra register.
6374 // As a compromise, we only emit discrete instructions if the shuffle can be
6375 // generated in 3 or fewer operations. When we have loop information
6376 // available, if this block is within a loop, we should avoid using vperm
6377 // for 3-operation perms and use a constant pool load instead.
6379 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
6382 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
6383 // vector that will get spilled to the constant pool.
6384 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
6386 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
6387 // that it is in input element units, not in bytes. Convert now.
6389 // For little endian, the order of the input vectors is reversed, and
6390 // the permutation mask is complemented with respect to 31. This is
6391 // necessary to produce proper semantics with the big-endian-biased vperm
6393 EVT EltVT = V1.getValueType().getVectorElementType();
6394 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
6396 SmallVector<SDValue, 16> ResultMask;
6397 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
6398 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
6400 for (unsigned j = 0; j != BytesPerElement; ++j)
6402 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement+j),
6405 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
6409 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
6412 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
6415 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
6419 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
6420 /// altivec comparison. If it is, return true and fill in Opc/isDot with
6421 /// information about the intrinsic.
6422 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
6424 unsigned IntrinsicID =
6425 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
6428 switch (IntrinsicID) {
6429 default: return false;
6430 // Comparison predicates.
6431 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
6432 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
6433 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
6434 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
6435 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
6436 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
6437 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
6438 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
6439 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
6440 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
6441 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
6442 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
6443 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
6445 // Normal Comparisons.
6446 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
6447 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
6448 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
6449 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
6450 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
6451 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
6452 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
6453 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
6454 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
6455 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
6456 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
6457 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
6458 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
6463 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
6464 /// lower, do it, otherwise return null.
6465 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
6466 SelectionDAG &DAG) const {
6467 // If this is a lowered altivec predicate compare, CompareOpc is set to the
6468 // opcode number of the comparison.
6472 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
6473 return SDValue(); // Don't custom lower most intrinsics.
6475 // If this is a non-dot comparison, make the VCMP node and we are done.
6477 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
6478 Op.getOperand(1), Op.getOperand(2),
6479 DAG.getConstant(CompareOpc, MVT::i32));
6480 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
6483 // Create the PPCISD altivec 'dot' comparison node.
6485 Op.getOperand(2), // LHS
6486 Op.getOperand(3), // RHS
6487 DAG.getConstant(CompareOpc, MVT::i32)
6489 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
6490 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
6492 // Now that we have the comparison, emit a copy from the CR to a GPR.
6493 // This is flagged to the above dot comparison.
6494 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
6495 DAG.getRegister(PPC::CR6, MVT::i32),
6496 CompNode.getValue(1));
6498 // Unpack the result based on how the target uses it.
6499 unsigned BitNo; // Bit # of CR6.
6500 bool InvertBit; // Invert result?
6501 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
6502 default: // Can't happen, don't crash on invalid number though.
6503 case 0: // Return the value of the EQ bit of CR6.
6504 BitNo = 0; InvertBit = false;
6506 case 1: // Return the inverted value of the EQ bit of CR6.
6507 BitNo = 0; InvertBit = true;
6509 case 2: // Return the value of the LT bit of CR6.
6510 BitNo = 2; InvertBit = false;
6512 case 3: // Return the inverted value of the LT bit of CR6.
6513 BitNo = 2; InvertBit = true;
6517 // Shift the bit into the low position.
6518 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
6519 DAG.getConstant(8-(3-BitNo), MVT::i32));
6521 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
6522 DAG.getConstant(1, MVT::i32));
6524 // If we are supposed to, toggle the bit.
6526 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
6527 DAG.getConstant(1, MVT::i32));
6531 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
6532 SelectionDAG &DAG) const {
6534 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
6535 // instructions), but for smaller types, we need to first extend up to v2i32
6536 // before doing going farther.
6537 if (Op.getValueType() == MVT::v2i64) {
6538 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
6539 if (ExtVT != MVT::v2i32) {
6540 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
6541 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
6542 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
6543 ExtVT.getVectorElementType(), 4)));
6544 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
6545 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
6546 DAG.getValueType(MVT::v2i32));
6555 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
6556 SelectionDAG &DAG) const {
6558 // Create a stack slot that is 16-byte aligned.
6559 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6560 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
6561 EVT PtrVT = getPointerTy();
6562 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6564 // Store the input value into Value#0 of the stack slot.
6565 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
6566 Op.getOperand(0), FIdx, MachinePointerInfo(),
6569 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
6570 false, false, false, 0);
6573 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
6575 if (Op.getValueType() == MVT::v4i32) {
6576 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6578 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
6579 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
6581 SDValue RHSSwap = // = vrlw RHS, 16
6582 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
6584 // Shrinkify inputs to v8i16.
6585 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
6586 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
6587 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
6589 // Low parts multiplied together, generating 32-bit results (we ignore the
6591 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
6592 LHS, RHS, DAG, dl, MVT::v4i32);
6594 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
6595 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
6596 // Shift the high parts up 16 bits.
6597 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
6599 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
6600 } else if (Op.getValueType() == MVT::v8i16) {
6601 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6603 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
6605 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
6606 LHS, RHS, Zero, DAG, dl);
6607 } else if (Op.getValueType() == MVT::v16i8) {
6608 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6609 bool isLittleEndian = Subtarget.isLittleEndian();
6611 // Multiply the even 8-bit parts, producing 16-bit sums.
6612 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
6613 LHS, RHS, DAG, dl, MVT::v8i16);
6614 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
6616 // Multiply the odd 8-bit parts, producing 16-bit sums.
6617 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
6618 LHS, RHS, DAG, dl, MVT::v8i16);
6619 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
6621 // Merge the results together. Because vmuleub and vmuloub are
6622 // instructions with a big-endian bias, we must reverse the
6623 // element numbering and reverse the meaning of "odd" and "even"
6624 // when generating little endian code.
6626 for (unsigned i = 0; i != 8; ++i) {
6627 if (isLittleEndian) {
6629 Ops[i*2+1] = 2*i+16;
6632 Ops[i*2+1] = 2*i+1+16;
6636 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
6638 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
6640 llvm_unreachable("Unknown mul to lower!");
6644 /// LowerOperation - Provide custom lowering hooks for some operations.
6646 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6647 switch (Op.getOpcode()) {
6648 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
6649 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6650 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
6651 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6652 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6653 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6654 case ISD::SETCC: return LowerSETCC(Op, DAG);
6655 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
6656 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
6658 return LowerVASTART(Op, DAG, Subtarget);
6661 return LowerVAARG(Op, DAG, Subtarget);
6664 return LowerVACOPY(Op, DAG, Subtarget);
6666 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget);
6667 case ISD::DYNAMIC_STACKALLOC:
6668 return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget);
6670 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
6671 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
6673 case ISD::LOAD: return LowerLOAD(Op, DAG);
6674 case ISD::STORE: return LowerSTORE(Op, DAG);
6675 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
6676 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6677 case ISD::FP_TO_UINT:
6678 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
6680 case ISD::UINT_TO_FP:
6681 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6682 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6684 // Lower 64-bit shifts.
6685 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
6686 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
6687 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
6689 // Vector-related lowering.
6690 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6691 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6692 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6693 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6694 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
6695 case ISD::MUL: return LowerMUL(Op, DAG);
6697 // For counter-based loop handling.
6698 case ISD::INTRINSIC_W_CHAIN: return SDValue();
6700 // Frame & Return address.
6701 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6702 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6706 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
6707 SmallVectorImpl<SDValue>&Results,
6708 SelectionDAG &DAG) const {
6709 const TargetMachine &TM = getTargetMachine();
6711 switch (N->getOpcode()) {
6713 llvm_unreachable("Do not know how to custom type legalize this operation!");
6714 case ISD::READCYCLECOUNTER: {
6715 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
6716 SDValue RTB = DAG.getNode(PPCISD::READ_TIME_BASE, dl, VTs, N->getOperand(0));
6718 Results.push_back(RTB);
6719 Results.push_back(RTB.getValue(1));
6720 Results.push_back(RTB.getValue(2));
6723 case ISD::INTRINSIC_W_CHAIN: {
6724 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
6725 Intrinsic::ppc_is_decremented_ctr_nonzero)
6728 assert(N->getValueType(0) == MVT::i1 &&
6729 "Unexpected result type for CTR decrement intrinsic");
6730 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
6731 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
6732 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
6735 Results.push_back(NewInt);
6736 Results.push_back(NewInt.getValue(1));
6740 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
6741 || TM.getSubtarget<PPCSubtarget>().isPPC64())
6744 EVT VT = N->getValueType(0);
6746 if (VT == MVT::i64) {
6747 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget);
6749 Results.push_back(NewNode);
6750 Results.push_back(NewNode.getValue(1));
6754 case ISD::FP_ROUND_INREG: {
6755 assert(N->getValueType(0) == MVT::ppcf128);
6756 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
6757 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6758 MVT::f64, N->getOperand(0),
6759 DAG.getIntPtrConstant(0));
6760 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6761 MVT::f64, N->getOperand(0),
6762 DAG.getIntPtrConstant(1));
6764 // Add the two halves of the long double in round-to-zero mode.
6765 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
6767 // We know the low half is about to be thrown away, so just use something
6769 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
6773 case ISD::FP_TO_SINT:
6774 // LowerFP_TO_INT() can only handle f32 and f64.
6775 if (N->getOperand(0).getValueType() == MVT::ppcf128)
6777 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
6783 //===----------------------------------------------------------------------===//
6784 // Other Lowering Code
6785 //===----------------------------------------------------------------------===//
6787 static Instruction* callIntrinsic(IRBuilder<> &Builder, Intrinsic::ID Id) {
6788 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
6789 Function *Func = Intrinsic::getDeclaration(M, Id);
6790 return Builder.CreateCall(Func);
6793 // The mappings for emitLeading/TrailingFence is taken from
6794 // http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
6795 Instruction* PPCTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
6796 AtomicOrdering Ord, bool IsStore,
6797 bool IsLoad) const {
6798 if (Ord == SequentiallyConsistent)
6799 return callIntrinsic(Builder, Intrinsic::ppc_sync);
6800 else if (isAtLeastRelease(Ord))
6801 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
6806 Instruction* PPCTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
6807 AtomicOrdering Ord, bool IsStore,
6808 bool IsLoad) const {
6809 if (IsLoad && isAtLeastAcquire(Ord))
6810 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
6811 // FIXME: this is too conservative, a dependent branch + isync is enough.
6812 // See http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html and
6813 // http://www.rdrop.com/users/paulmck/scalability/paper/N2745r.2011.03.04a.html
6814 // and http://www.cl.cam.ac.uk/~pes20/cppppc/ for justification.
6820 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
6821 bool is64bit, unsigned BinOpcode) const {
6822 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6823 const TargetInstrInfo *TII =
6824 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6826 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6827 MachineFunction *F = BB->getParent();
6828 MachineFunction::iterator It = BB;
6831 unsigned dest = MI->getOperand(0).getReg();
6832 unsigned ptrA = MI->getOperand(1).getReg();
6833 unsigned ptrB = MI->getOperand(2).getReg();
6834 unsigned incr = MI->getOperand(3).getReg();
6835 DebugLoc dl = MI->getDebugLoc();
6837 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6838 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6839 F->insert(It, loopMBB);
6840 F->insert(It, exitMBB);
6841 exitMBB->splice(exitMBB->begin(), BB,
6842 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6843 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6845 MachineRegisterInfo &RegInfo = F->getRegInfo();
6846 unsigned TmpReg = (!BinOpcode) ? incr :
6847 RegInfo.createVirtualRegister( is64bit ? &PPC::G8RCRegClass
6848 : &PPC::GPRCRegClass);
6852 // fallthrough --> loopMBB
6853 BB->addSuccessor(loopMBB);
6856 // l[wd]arx dest, ptr
6857 // add r0, dest, incr
6858 // st[wd]cx. r0, ptr
6860 // fallthrough --> exitMBB
6862 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6863 .addReg(ptrA).addReg(ptrB);
6865 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
6866 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6867 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
6868 BuildMI(BB, dl, TII->get(PPC::BCC))
6869 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6870 BB->addSuccessor(loopMBB);
6871 BB->addSuccessor(exitMBB);
6880 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
6881 MachineBasicBlock *BB,
6882 bool is8bit, // operation
6883 unsigned BinOpcode) const {
6884 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6885 const TargetInstrInfo *TII =
6886 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6887 // In 64 bit mode we have to use 64 bits for addresses, even though the
6888 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
6889 // registers without caring whether they're 32 or 64, but here we're
6890 // doing actual arithmetic on the addresses.
6891 bool is64bit = Subtarget.isPPC64();
6892 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6894 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6895 MachineFunction *F = BB->getParent();
6896 MachineFunction::iterator It = BB;
6899 unsigned dest = MI->getOperand(0).getReg();
6900 unsigned ptrA = MI->getOperand(1).getReg();
6901 unsigned ptrB = MI->getOperand(2).getReg();
6902 unsigned incr = MI->getOperand(3).getReg();
6903 DebugLoc dl = MI->getDebugLoc();
6905 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6906 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6907 F->insert(It, loopMBB);
6908 F->insert(It, exitMBB);
6909 exitMBB->splice(exitMBB->begin(), BB,
6910 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6911 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6913 MachineRegisterInfo &RegInfo = F->getRegInfo();
6914 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
6915 : &PPC::GPRCRegClass;
6916 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6917 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6918 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6919 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
6920 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6921 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6922 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6923 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6924 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
6925 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6926 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6928 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
6932 // fallthrough --> loopMBB
6933 BB->addSuccessor(loopMBB);
6935 // The 4-byte load must be aligned, while a char or short may be
6936 // anywhere in the word. Hence all this nasty bookkeeping code.
6937 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6938 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6939 // xori shift, shift1, 24 [16]
6940 // rlwinm ptr, ptr1, 0, 0, 29
6941 // slw incr2, incr, shift
6942 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6943 // slw mask, mask2, shift
6945 // lwarx tmpDest, ptr
6946 // add tmp, tmpDest, incr2
6947 // andc tmp2, tmpDest, mask
6948 // and tmp3, tmp, mask
6949 // or tmp4, tmp3, tmp2
6952 // fallthrough --> exitMBB
6953 // srw dest, tmpDest, shift
6954 if (ptrA != ZeroReg) {
6955 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6956 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6957 .addReg(ptrA).addReg(ptrB);
6961 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6962 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6963 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6964 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6966 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6967 .addReg(Ptr1Reg).addImm(0).addImm(61);
6969 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6970 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6971 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
6972 .addReg(incr).addReg(ShiftReg);
6974 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6976 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6977 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
6979 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6980 .addReg(Mask2Reg).addReg(ShiftReg);
6983 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6984 .addReg(ZeroReg).addReg(PtrReg);
6986 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
6987 .addReg(Incr2Reg).addReg(TmpDestReg);
6988 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
6989 .addReg(TmpDestReg).addReg(MaskReg);
6990 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
6991 .addReg(TmpReg).addReg(MaskReg);
6992 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
6993 .addReg(Tmp3Reg).addReg(Tmp2Reg);
6994 BuildMI(BB, dl, TII->get(PPC::STWCX))
6995 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
6996 BuildMI(BB, dl, TII->get(PPC::BCC))
6997 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6998 BB->addSuccessor(loopMBB);
6999 BB->addSuccessor(exitMBB);
7004 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
7009 llvm::MachineBasicBlock*
7010 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
7011 MachineBasicBlock *MBB) const {
7012 DebugLoc DL = MI->getDebugLoc();
7013 const TargetInstrInfo *TII =
7014 getTargetMachine().getSubtargetImpl()->getInstrInfo();
7016 MachineFunction *MF = MBB->getParent();
7017 MachineRegisterInfo &MRI = MF->getRegInfo();
7019 const BasicBlock *BB = MBB->getBasicBlock();
7020 MachineFunction::iterator I = MBB;
7024 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
7025 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
7027 unsigned DstReg = MI->getOperand(0).getReg();
7028 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
7029 assert(RC->hasType(MVT::i32) && "Invalid destination!");
7030 unsigned mainDstReg = MRI.createVirtualRegister(RC);
7031 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
7033 MVT PVT = getPointerTy();
7034 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
7035 "Invalid Pointer Size!");
7036 // For v = setjmp(buf), we generate
7039 // SjLjSetup mainMBB
7045 // buf[LabelOffset] = LR
7049 // v = phi(main, restore)
7052 MachineBasicBlock *thisMBB = MBB;
7053 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
7054 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
7055 MF->insert(I, mainMBB);
7056 MF->insert(I, sinkMBB);
7058 MachineInstrBuilder MIB;
7060 // Transfer the remainder of BB and its successor edges to sinkMBB.
7061 sinkMBB->splice(sinkMBB->begin(), MBB,
7062 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
7063 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
7065 // Note that the structure of the jmp_buf used here is not compatible
7066 // with that used by libc, and is not designed to be. Specifically, it
7067 // stores only those 'reserved' registers that LLVM does not otherwise
7068 // understand how to spill. Also, by convention, by the time this
7069 // intrinsic is called, Clang has already stored the frame address in the
7070 // first slot of the buffer and stack address in the third. Following the
7071 // X86 target code, we'll store the jump address in the second slot. We also
7072 // need to save the TOC pointer (R2) to handle jumps between shared
7073 // libraries, and that will be stored in the fourth slot. The thread
7074 // identifier (R13) is not affected.
7077 const int64_t LabelOffset = 1 * PVT.getStoreSize();
7078 const int64_t TOCOffset = 3 * PVT.getStoreSize();
7079 const int64_t BPOffset = 4 * PVT.getStoreSize();
7081 // Prepare IP either in reg.
7082 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
7083 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
7084 unsigned BufReg = MI->getOperand(1).getReg();
7086 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
7087 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
7091 MIB.setMemRefs(MMOBegin, MMOEnd);
7094 // Naked functions never have a base pointer, and so we use r1. For all
7095 // other functions, this decision must be delayed until during PEI.
7097 if (MF->getFunction()->getAttributes().hasAttribute(
7098 AttributeSet::FunctionIndex, Attribute::Naked))
7099 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
7101 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
7103 MIB = BuildMI(*thisMBB, MI, DL,
7104 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
7108 MIB.setMemRefs(MMOBegin, MMOEnd);
7111 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
7112 const PPCRegisterInfo *TRI =
7113 getTargetMachine().getSubtarget<PPCSubtarget>().getRegisterInfo();
7114 MIB.addRegMask(TRI->getNoPreservedMask());
7116 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
7118 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
7120 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
7122 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
7123 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
7127 MIB = BuildMI(mainMBB, DL,
7128 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
7131 if (Subtarget.isPPC64()) {
7132 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
7134 .addImm(LabelOffset)
7137 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
7139 .addImm(LabelOffset)
7143 MIB.setMemRefs(MMOBegin, MMOEnd);
7145 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
7146 mainMBB->addSuccessor(sinkMBB);
7149 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
7150 TII->get(PPC::PHI), DstReg)
7151 .addReg(mainDstReg).addMBB(mainMBB)
7152 .addReg(restoreDstReg).addMBB(thisMBB);
7154 MI->eraseFromParent();
7159 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
7160 MachineBasicBlock *MBB) const {
7161 DebugLoc DL = MI->getDebugLoc();
7162 const TargetInstrInfo *TII =
7163 getTargetMachine().getSubtargetImpl()->getInstrInfo();
7165 MachineFunction *MF = MBB->getParent();
7166 MachineRegisterInfo &MRI = MF->getRegInfo();
7169 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
7170 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
7172 MVT PVT = getPointerTy();
7173 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
7174 "Invalid Pointer Size!");
7176 const TargetRegisterClass *RC =
7177 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
7178 unsigned Tmp = MRI.createVirtualRegister(RC);
7179 // Since FP is only updated here but NOT referenced, it's treated as GPR.
7180 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
7181 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
7182 unsigned BP = (PVT == MVT::i64) ? PPC::X30 :
7183 (Subtarget.isSVR4ABI() &&
7184 MF->getTarget().getRelocationModel() == Reloc::PIC_ ?
7185 PPC::R29 : PPC::R30);
7187 MachineInstrBuilder MIB;
7189 const int64_t LabelOffset = 1 * PVT.getStoreSize();
7190 const int64_t SPOffset = 2 * PVT.getStoreSize();
7191 const int64_t TOCOffset = 3 * PVT.getStoreSize();
7192 const int64_t BPOffset = 4 * PVT.getStoreSize();
7194 unsigned BufReg = MI->getOperand(0).getReg();
7196 // Reload FP (the jumped-to function may not have had a
7197 // frame pointer, and if so, then its r31 will be restored
7199 if (PVT == MVT::i64) {
7200 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
7204 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
7208 MIB.setMemRefs(MMOBegin, MMOEnd);
7211 if (PVT == MVT::i64) {
7212 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
7213 .addImm(LabelOffset)
7216 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
7217 .addImm(LabelOffset)
7220 MIB.setMemRefs(MMOBegin, MMOEnd);
7223 if (PVT == MVT::i64) {
7224 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
7228 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
7232 MIB.setMemRefs(MMOBegin, MMOEnd);
7235 if (PVT == MVT::i64) {
7236 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
7240 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
7244 MIB.setMemRefs(MMOBegin, MMOEnd);
7247 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
7248 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
7252 MIB.setMemRefs(MMOBegin, MMOEnd);
7256 BuildMI(*MBB, MI, DL,
7257 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
7258 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
7260 MI->eraseFromParent();
7265 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
7266 MachineBasicBlock *BB) const {
7267 if (MI->getOpcode() == TargetOpcode::STACKMAP ||
7268 MI->getOpcode() == TargetOpcode::PATCHPOINT)
7269 return emitPatchPoint(MI, BB);
7271 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
7272 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
7273 return emitEHSjLjSetJmp(MI, BB);
7274 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
7275 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
7276 return emitEHSjLjLongJmp(MI, BB);
7279 const TargetInstrInfo *TII =
7280 getTargetMachine().getSubtargetImpl()->getInstrInfo();
7282 // To "insert" these instructions we actually have to insert their
7283 // control-flow patterns.
7284 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7285 MachineFunction::iterator It = BB;
7288 MachineFunction *F = BB->getParent();
7290 if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7291 MI->getOpcode() == PPC::SELECT_CC_I8 ||
7292 MI->getOpcode() == PPC::SELECT_I4 ||
7293 MI->getOpcode() == PPC::SELECT_I8)) {
7294 SmallVector<MachineOperand, 2> Cond;
7295 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7296 MI->getOpcode() == PPC::SELECT_CC_I8)
7297 Cond.push_back(MI->getOperand(4));
7299 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
7300 Cond.push_back(MI->getOperand(1));
7302 DebugLoc dl = MI->getDebugLoc();
7303 const TargetInstrInfo *TII =
7304 getTargetMachine().getSubtargetImpl()->getInstrInfo();
7305 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
7306 Cond, MI->getOperand(2).getReg(),
7307 MI->getOperand(3).getReg());
7308 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7309 MI->getOpcode() == PPC::SELECT_CC_I8 ||
7310 MI->getOpcode() == PPC::SELECT_CC_F4 ||
7311 MI->getOpcode() == PPC::SELECT_CC_F8 ||
7312 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
7313 MI->getOpcode() == PPC::SELECT_CC_VSFRC ||
7314 MI->getOpcode() == PPC::SELECT_CC_VSRC ||
7315 MI->getOpcode() == PPC::SELECT_I4 ||
7316 MI->getOpcode() == PPC::SELECT_I8 ||
7317 MI->getOpcode() == PPC::SELECT_F4 ||
7318 MI->getOpcode() == PPC::SELECT_F8 ||
7319 MI->getOpcode() == PPC::SELECT_VRRC ||
7320 MI->getOpcode() == PPC::SELECT_VSFRC ||
7321 MI->getOpcode() == PPC::SELECT_VSRC) {
7322 // The incoming instruction knows the destination vreg to set, the
7323 // condition code register to branch on, the true/false values to
7324 // select between, and a branch opcode to use.
7329 // cmpTY ccX, r1, r2
7331 // fallthrough --> copy0MBB
7332 MachineBasicBlock *thisMBB = BB;
7333 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7334 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7335 DebugLoc dl = MI->getDebugLoc();
7336 F->insert(It, copy0MBB);
7337 F->insert(It, sinkMBB);
7339 // Transfer the remainder of BB and its successor edges to sinkMBB.
7340 sinkMBB->splice(sinkMBB->begin(), BB,
7341 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7342 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7344 // Next, add the true and fallthrough blocks as its successors.
7345 BB->addSuccessor(copy0MBB);
7346 BB->addSuccessor(sinkMBB);
7348 if (MI->getOpcode() == PPC::SELECT_I4 ||
7349 MI->getOpcode() == PPC::SELECT_I8 ||
7350 MI->getOpcode() == PPC::SELECT_F4 ||
7351 MI->getOpcode() == PPC::SELECT_F8 ||
7352 MI->getOpcode() == PPC::SELECT_VRRC ||
7353 MI->getOpcode() == PPC::SELECT_VSFRC ||
7354 MI->getOpcode() == PPC::SELECT_VSRC) {
7355 BuildMI(BB, dl, TII->get(PPC::BC))
7356 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
7358 unsigned SelectPred = MI->getOperand(4).getImm();
7359 BuildMI(BB, dl, TII->get(PPC::BCC))
7360 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
7364 // %FalseValue = ...
7365 // # fallthrough to sinkMBB
7368 // Update machine-CFG edges
7369 BB->addSuccessor(sinkMBB);
7372 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7375 BuildMI(*BB, BB->begin(), dl,
7376 TII->get(PPC::PHI), MI->getOperand(0).getReg())
7377 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
7378 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7379 } else if (MI->getOpcode() == PPC::ReadTB) {
7380 // To read the 64-bit time-base register on a 32-bit target, we read the
7381 // two halves. Should the counter have wrapped while it was being read, we
7382 // need to try again.
7385 // mfspr Rx,TBU # load from TBU
7386 // mfspr Ry,TB # load from TB
7387 // mfspr Rz,TBU # load from TBU
7388 // cmpw crX,Rx,Rz # check if ‘old’=’new’
7389 // bne readLoop # branch if they're not equal
7392 MachineBasicBlock *readMBB = F->CreateMachineBasicBlock(LLVM_BB);
7393 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7394 DebugLoc dl = MI->getDebugLoc();
7395 F->insert(It, readMBB);
7396 F->insert(It, sinkMBB);
7398 // Transfer the remainder of BB and its successor edges to sinkMBB.
7399 sinkMBB->splice(sinkMBB->begin(), BB,
7400 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7401 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7403 BB->addSuccessor(readMBB);
7406 MachineRegisterInfo &RegInfo = F->getRegInfo();
7407 unsigned ReadAgainReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
7408 unsigned LoReg = MI->getOperand(0).getReg();
7409 unsigned HiReg = MI->getOperand(1).getReg();
7411 BuildMI(BB, dl, TII->get(PPC::MFSPR), HiReg).addImm(269);
7412 BuildMI(BB, dl, TII->get(PPC::MFSPR), LoReg).addImm(268);
7413 BuildMI(BB, dl, TII->get(PPC::MFSPR), ReadAgainReg).addImm(269);
7415 unsigned CmpReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
7417 BuildMI(BB, dl, TII->get(PPC::CMPW), CmpReg)
7418 .addReg(HiReg).addReg(ReadAgainReg);
7419 BuildMI(BB, dl, TII->get(PPC::BCC))
7420 .addImm(PPC::PRED_NE).addReg(CmpReg).addMBB(readMBB);
7422 BB->addSuccessor(readMBB);
7423 BB->addSuccessor(sinkMBB);
7425 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
7426 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
7427 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
7428 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
7429 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
7430 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
7431 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
7432 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
7434 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
7435 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
7436 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
7437 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
7438 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
7439 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
7440 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
7441 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
7443 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
7444 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
7445 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
7446 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
7447 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
7448 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
7449 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
7450 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
7452 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
7453 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
7454 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
7455 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
7456 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
7457 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
7458 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
7459 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
7461 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
7462 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND);
7463 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
7464 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND);
7465 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
7466 BB = EmitAtomicBinary(MI, BB, false, PPC::NAND);
7467 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
7468 BB = EmitAtomicBinary(MI, BB, true, PPC::NAND8);
7470 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
7471 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
7472 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
7473 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
7474 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
7475 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
7476 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
7477 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
7479 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
7480 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
7481 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
7482 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
7483 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
7484 BB = EmitAtomicBinary(MI, BB, false, 0);
7485 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
7486 BB = EmitAtomicBinary(MI, BB, true, 0);
7488 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
7489 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
7490 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
7492 unsigned dest = MI->getOperand(0).getReg();
7493 unsigned ptrA = MI->getOperand(1).getReg();
7494 unsigned ptrB = MI->getOperand(2).getReg();
7495 unsigned oldval = MI->getOperand(3).getReg();
7496 unsigned newval = MI->getOperand(4).getReg();
7497 DebugLoc dl = MI->getDebugLoc();
7499 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
7500 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
7501 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
7502 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7503 F->insert(It, loop1MBB);
7504 F->insert(It, loop2MBB);
7505 F->insert(It, midMBB);
7506 F->insert(It, exitMBB);
7507 exitMBB->splice(exitMBB->begin(), BB,
7508 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7509 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7513 // fallthrough --> loopMBB
7514 BB->addSuccessor(loop1MBB);
7517 // l[wd]arx dest, ptr
7518 // cmp[wd] dest, oldval
7521 // st[wd]cx. newval, ptr
7525 // st[wd]cx. dest, ptr
7528 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
7529 .addReg(ptrA).addReg(ptrB);
7530 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
7531 .addReg(oldval).addReg(dest);
7532 BuildMI(BB, dl, TII->get(PPC::BCC))
7533 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7534 BB->addSuccessor(loop2MBB);
7535 BB->addSuccessor(midMBB);
7538 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7539 .addReg(newval).addReg(ptrA).addReg(ptrB);
7540 BuildMI(BB, dl, TII->get(PPC::BCC))
7541 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7542 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7543 BB->addSuccessor(loop1MBB);
7544 BB->addSuccessor(exitMBB);
7547 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7548 .addReg(dest).addReg(ptrA).addReg(ptrB);
7549 BB->addSuccessor(exitMBB);
7554 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
7555 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
7556 // We must use 64-bit registers for addresses when targeting 64-bit,
7557 // since we're actually doing arithmetic on them. Other registers
7559 bool is64bit = Subtarget.isPPC64();
7560 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
7562 unsigned dest = MI->getOperand(0).getReg();
7563 unsigned ptrA = MI->getOperand(1).getReg();
7564 unsigned ptrB = MI->getOperand(2).getReg();
7565 unsigned oldval = MI->getOperand(3).getReg();
7566 unsigned newval = MI->getOperand(4).getReg();
7567 DebugLoc dl = MI->getDebugLoc();
7569 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
7570 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
7571 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
7572 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7573 F->insert(It, loop1MBB);
7574 F->insert(It, loop2MBB);
7575 F->insert(It, midMBB);
7576 F->insert(It, exitMBB);
7577 exitMBB->splice(exitMBB->begin(), BB,
7578 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7579 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7581 MachineRegisterInfo &RegInfo = F->getRegInfo();
7582 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
7583 : &PPC::GPRCRegClass;
7584 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
7585 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
7586 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
7587 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
7588 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
7589 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
7590 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
7591 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
7592 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
7593 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
7594 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
7595 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
7596 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
7598 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
7599 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
7602 // fallthrough --> loopMBB
7603 BB->addSuccessor(loop1MBB);
7605 // The 4-byte load must be aligned, while a char or short may be
7606 // anywhere in the word. Hence all this nasty bookkeeping code.
7607 // add ptr1, ptrA, ptrB [copy if ptrA==0]
7608 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
7609 // xori shift, shift1, 24 [16]
7610 // rlwinm ptr, ptr1, 0, 0, 29
7611 // slw newval2, newval, shift
7612 // slw oldval2, oldval,shift
7613 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
7614 // slw mask, mask2, shift
7615 // and newval3, newval2, mask
7616 // and oldval3, oldval2, mask
7618 // lwarx tmpDest, ptr
7619 // and tmp, tmpDest, mask
7620 // cmpw tmp, oldval3
7623 // andc tmp2, tmpDest, mask
7624 // or tmp4, tmp2, newval3
7629 // stwcx. tmpDest, ptr
7631 // srw dest, tmpDest, shift
7632 if (ptrA != ZeroReg) {
7633 Ptr1Reg = RegInfo.createVirtualRegister(RC);
7634 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
7635 .addReg(ptrA).addReg(ptrB);
7639 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
7640 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
7641 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
7642 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
7644 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
7645 .addReg(Ptr1Reg).addImm(0).addImm(61);
7647 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
7648 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
7649 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
7650 .addReg(newval).addReg(ShiftReg);
7651 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
7652 .addReg(oldval).addReg(ShiftReg);
7654 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
7656 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
7657 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
7658 .addReg(Mask3Reg).addImm(65535);
7660 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
7661 .addReg(Mask2Reg).addReg(ShiftReg);
7662 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
7663 .addReg(NewVal2Reg).addReg(MaskReg);
7664 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
7665 .addReg(OldVal2Reg).addReg(MaskReg);
7668 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
7669 .addReg(ZeroReg).addReg(PtrReg);
7670 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
7671 .addReg(TmpDestReg).addReg(MaskReg);
7672 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
7673 .addReg(TmpReg).addReg(OldVal3Reg);
7674 BuildMI(BB, dl, TII->get(PPC::BCC))
7675 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7676 BB->addSuccessor(loop2MBB);
7677 BB->addSuccessor(midMBB);
7680 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
7681 .addReg(TmpDestReg).addReg(MaskReg);
7682 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
7683 .addReg(Tmp2Reg).addReg(NewVal3Reg);
7684 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
7685 .addReg(ZeroReg).addReg(PtrReg);
7686 BuildMI(BB, dl, TII->get(PPC::BCC))
7687 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7688 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7689 BB->addSuccessor(loop1MBB);
7690 BB->addSuccessor(exitMBB);
7693 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
7694 .addReg(ZeroReg).addReg(PtrReg);
7695 BB->addSuccessor(exitMBB);
7700 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
7702 } else if (MI->getOpcode() == PPC::FADDrtz) {
7703 // This pseudo performs an FADD with rounding mode temporarily forced
7704 // to round-to-zero. We emit this via custom inserter since the FPSCR
7705 // is not modeled at the SelectionDAG level.
7706 unsigned Dest = MI->getOperand(0).getReg();
7707 unsigned Src1 = MI->getOperand(1).getReg();
7708 unsigned Src2 = MI->getOperand(2).getReg();
7709 DebugLoc dl = MI->getDebugLoc();
7711 MachineRegisterInfo &RegInfo = F->getRegInfo();
7712 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
7714 // Save FPSCR value.
7715 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
7717 // Set rounding mode to round-to-zero.
7718 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
7719 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
7721 // Perform addition.
7722 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
7724 // Restore FPSCR value.
7725 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSFb)).addImm(1).addReg(MFFSReg);
7726 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7727 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
7728 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7729 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
7730 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7731 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
7732 PPC::ANDIo8 : PPC::ANDIo;
7733 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7734 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
7736 MachineRegisterInfo &RegInfo = F->getRegInfo();
7737 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
7738 &PPC::GPRCRegClass :
7739 &PPC::G8RCRegClass);
7741 DebugLoc dl = MI->getDebugLoc();
7742 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
7743 .addReg(MI->getOperand(1).getReg()).addImm(1);
7744 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
7745 MI->getOperand(0).getReg())
7746 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
7748 llvm_unreachable("Unexpected instr type to insert");
7751 MI->eraseFromParent(); // The pseudo instruction is gone now.
7755 //===----------------------------------------------------------------------===//
7756 // Target Optimization Hooks
7757 //===----------------------------------------------------------------------===//
7759 SDValue PPCTargetLowering::getRsqrtEstimate(SDValue Operand,
7760 DAGCombinerInfo &DCI,
7761 unsigned &RefinementSteps,
7762 bool &UseOneConstNR) const {
7763 EVT VT = Operand.getValueType();
7764 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
7765 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
7766 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7767 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7768 // Convergence is quadratic, so we essentially double the number of digits
7769 // correct after every iteration. For both FRE and FRSQRTE, the minimum
7770 // architected relative accuracy is 2^-5. When hasRecipPrec(), this is
7771 // 2^-14. IEEE float has 23 digits and double has 52 digits.
7772 RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3;
7773 if (VT.getScalarType() == MVT::f64)
7775 UseOneConstNR = true;
7776 return DCI.DAG.getNode(PPCISD::FRSQRTE, SDLoc(Operand), VT, Operand);
7781 SDValue PPCTargetLowering::getRecipEstimate(SDValue Operand,
7782 DAGCombinerInfo &DCI,
7783 unsigned &RefinementSteps) const {
7784 EVT VT = Operand.getValueType();
7785 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
7786 (VT == MVT::f64 && Subtarget.hasFRE()) ||
7787 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7788 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7789 // Convergence is quadratic, so we essentially double the number of digits
7790 // correct after every iteration. For both FRE and FRSQRTE, the minimum
7791 // architected relative accuracy is 2^-5. When hasRecipPrec(), this is
7792 // 2^-14. IEEE float has 23 digits and double has 52 digits.
7793 RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3;
7794 if (VT.getScalarType() == MVT::f64)
7796 return DCI.DAG.getNode(PPCISD::FRE, SDLoc(Operand), VT, Operand);
7801 bool PPCTargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
7802 // Note: This functionality is used only when unsafe-fp-math is enabled, and
7803 // on cores with reciprocal estimates (which are used when unsafe-fp-math is
7804 // enabled for division), this functionality is redundant with the default
7805 // combiner logic (once the division -> reciprocal/multiply transformation
7806 // has taken place). As a result, this matters more for older cores than for
7809 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
7810 // reciprocal if there are two or more FDIVs (for embedded cores with only
7811 // one FP pipeline) for three or more FDIVs (for generic OOO cores).
7812 switch (Subtarget.getDarwinDirective()) {
7814 return NumUsers > 2;
7817 case PPC::DIR_E500mc:
7818 case PPC::DIR_E5500:
7819 return NumUsers > 1;
7823 static bool isConsecutiveLSLoc(SDValue Loc, EVT VT, LSBaseSDNode *Base,
7824 unsigned Bytes, int Dist,
7825 SelectionDAG &DAG) {
7826 if (VT.getSizeInBits() / 8 != Bytes)
7829 SDValue BaseLoc = Base->getBasePtr();
7830 if (Loc.getOpcode() == ISD::FrameIndex) {
7831 if (BaseLoc.getOpcode() != ISD::FrameIndex)
7833 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7834 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
7835 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
7836 int FS = MFI->getObjectSize(FI);
7837 int BFS = MFI->getObjectSize(BFI);
7838 if (FS != BFS || FS != (int)Bytes) return false;
7839 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
7843 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
7844 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
7847 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7848 const GlobalValue *GV1 = nullptr;
7849 const GlobalValue *GV2 = nullptr;
7850 int64_t Offset1 = 0;
7851 int64_t Offset2 = 0;
7852 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
7853 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
7854 if (isGA1 && isGA2 && GV1 == GV2)
7855 return Offset1 == (Offset2 + Dist*Bytes);
7859 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
7860 // not enforce equality of the chain operands.
7861 static bool isConsecutiveLS(SDNode *N, LSBaseSDNode *Base,
7862 unsigned Bytes, int Dist,
7863 SelectionDAG &DAG) {
7864 if (LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(N)) {
7865 EVT VT = LS->getMemoryVT();
7866 SDValue Loc = LS->getBasePtr();
7867 return isConsecutiveLSLoc(Loc, VT, Base, Bytes, Dist, DAG);
7870 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
7872 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
7873 default: return false;
7874 case Intrinsic::ppc_altivec_lvx:
7875 case Intrinsic::ppc_altivec_lvxl:
7876 case Intrinsic::ppc_vsx_lxvw4x:
7879 case Intrinsic::ppc_vsx_lxvd2x:
7882 case Intrinsic::ppc_altivec_lvebx:
7885 case Intrinsic::ppc_altivec_lvehx:
7888 case Intrinsic::ppc_altivec_lvewx:
7893 return isConsecutiveLSLoc(N->getOperand(2), VT, Base, Bytes, Dist, DAG);
7896 if (N->getOpcode() == ISD::INTRINSIC_VOID) {
7898 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
7899 default: return false;
7900 case Intrinsic::ppc_altivec_stvx:
7901 case Intrinsic::ppc_altivec_stvxl:
7902 case Intrinsic::ppc_vsx_stxvw4x:
7905 case Intrinsic::ppc_vsx_stxvd2x:
7908 case Intrinsic::ppc_altivec_stvebx:
7911 case Intrinsic::ppc_altivec_stvehx:
7914 case Intrinsic::ppc_altivec_stvewx:
7919 return isConsecutiveLSLoc(N->getOperand(3), VT, Base, Bytes, Dist, DAG);
7925 // Return true is there is a nearyby consecutive load to the one provided
7926 // (regardless of alignment). We search up and down the chain, looking though
7927 // token factors and other loads (but nothing else). As a result, a true result
7928 // indicates that it is safe to create a new consecutive load adjacent to the
7930 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
7931 SDValue Chain = LD->getChain();
7932 EVT VT = LD->getMemoryVT();
7934 SmallSet<SDNode *, 16> LoadRoots;
7935 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
7936 SmallSet<SDNode *, 16> Visited;
7938 // First, search up the chain, branching to follow all token-factor operands.
7939 // If we find a consecutive load, then we're done, otherwise, record all
7940 // nodes just above the top-level loads and token factors.
7941 while (!Queue.empty()) {
7942 SDNode *ChainNext = Queue.pop_back_val();
7943 if (!Visited.insert(ChainNext).second)
7946 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(ChainNext)) {
7947 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7950 if (!Visited.count(ChainLD->getChain().getNode()))
7951 Queue.push_back(ChainLD->getChain().getNode());
7952 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
7953 for (const SDUse &O : ChainNext->ops())
7954 if (!Visited.count(O.getNode()))
7955 Queue.push_back(O.getNode());
7957 LoadRoots.insert(ChainNext);
7960 // Second, search down the chain, starting from the top-level nodes recorded
7961 // in the first phase. These top-level nodes are the nodes just above all
7962 // loads and token factors. Starting with their uses, recursively look though
7963 // all loads (just the chain uses) and token factors to find a consecutive
7968 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
7969 IE = LoadRoots.end(); I != IE; ++I) {
7970 Queue.push_back(*I);
7972 while (!Queue.empty()) {
7973 SDNode *LoadRoot = Queue.pop_back_val();
7974 if (!Visited.insert(LoadRoot).second)
7977 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(LoadRoot))
7978 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7981 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
7982 UE = LoadRoot->use_end(); UI != UE; ++UI)
7983 if (((isa<MemSDNode>(*UI) &&
7984 cast<MemSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
7985 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
7986 Queue.push_back(*UI);
7993 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
7994 DAGCombinerInfo &DCI) const {
7995 SelectionDAG &DAG = DCI.DAG;
7998 assert(Subtarget.useCRBits() &&
7999 "Expecting to be tracking CR bits");
8000 // If we're tracking CR bits, we need to be careful that we don't have:
8001 // trunc(binary-ops(zext(x), zext(y)))
8003 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
8004 // such that we're unnecessarily moving things into GPRs when it would be
8005 // better to keep them in CR bits.
8007 // Note that trunc here can be an actual i1 trunc, or can be the effective
8008 // truncation that comes from a setcc or select_cc.
8009 if (N->getOpcode() == ISD::TRUNCATE &&
8010 N->getValueType(0) != MVT::i1)
8013 if (N->getOperand(0).getValueType() != MVT::i32 &&
8014 N->getOperand(0).getValueType() != MVT::i64)
8017 if (N->getOpcode() == ISD::SETCC ||
8018 N->getOpcode() == ISD::SELECT_CC) {
8019 // If we're looking at a comparison, then we need to make sure that the
8020 // high bits (all except for the first) don't matter the result.
8022 cast<CondCodeSDNode>(N->getOperand(
8023 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
8024 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
8026 if (ISD::isSignedIntSetCC(CC)) {
8027 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
8028 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
8030 } else if (ISD::isUnsignedIntSetCC(CC)) {
8031 if (!DAG.MaskedValueIsZero(N->getOperand(0),
8032 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
8033 !DAG.MaskedValueIsZero(N->getOperand(1),
8034 APInt::getHighBitsSet(OpBits, OpBits-1)))
8037 // This is neither a signed nor an unsigned comparison, just make sure
8038 // that the high bits are equal.
8039 APInt Op1Zero, Op1One;
8040 APInt Op2Zero, Op2One;
8041 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
8042 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
8044 // We don't really care about what is known about the first bit (if
8045 // anything), so clear it in all masks prior to comparing them.
8046 Op1Zero.clearBit(0); Op1One.clearBit(0);
8047 Op2Zero.clearBit(0); Op2One.clearBit(0);
8049 if (Op1Zero != Op2Zero || Op1One != Op2One)
8054 // We now know that the higher-order bits are irrelevant, we just need to
8055 // make sure that all of the intermediate operations are bit operations, and
8056 // all inputs are extensions.
8057 if (N->getOperand(0).getOpcode() != ISD::AND &&
8058 N->getOperand(0).getOpcode() != ISD::OR &&
8059 N->getOperand(0).getOpcode() != ISD::XOR &&
8060 N->getOperand(0).getOpcode() != ISD::SELECT &&
8061 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
8062 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
8063 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
8064 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
8065 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
8068 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
8069 N->getOperand(1).getOpcode() != ISD::AND &&
8070 N->getOperand(1).getOpcode() != ISD::OR &&
8071 N->getOperand(1).getOpcode() != ISD::XOR &&
8072 N->getOperand(1).getOpcode() != ISD::SELECT &&
8073 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
8074 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
8075 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
8076 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
8077 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
8080 SmallVector<SDValue, 4> Inputs;
8081 SmallVector<SDValue, 8> BinOps, PromOps;
8082 SmallPtrSet<SDNode *, 16> Visited;
8084 for (unsigned i = 0; i < 2; ++i) {
8085 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
8086 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
8087 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
8088 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
8089 isa<ConstantSDNode>(N->getOperand(i)))
8090 Inputs.push_back(N->getOperand(i));
8092 BinOps.push_back(N->getOperand(i));
8094 if (N->getOpcode() == ISD::TRUNCATE)
8098 // Visit all inputs, collect all binary operations (and, or, xor and
8099 // select) that are all fed by extensions.
8100 while (!BinOps.empty()) {
8101 SDValue BinOp = BinOps.back();
8104 if (!Visited.insert(BinOp.getNode()).second)
8107 PromOps.push_back(BinOp);
8109 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
8110 // The condition of the select is not promoted.
8111 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
8113 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
8116 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
8117 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
8118 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
8119 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
8120 isa<ConstantSDNode>(BinOp.getOperand(i))) {
8121 Inputs.push_back(BinOp.getOperand(i));
8122 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
8123 BinOp.getOperand(i).getOpcode() == ISD::OR ||
8124 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
8125 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
8126 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
8127 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
8128 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
8129 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
8130 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
8131 BinOps.push_back(BinOp.getOperand(i));
8133 // We have an input that is not an extension or another binary
8134 // operation; we'll abort this transformation.
8140 // Make sure that this is a self-contained cluster of operations (which
8141 // is not quite the same thing as saying that everything has only one
8143 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8144 if (isa<ConstantSDNode>(Inputs[i]))
8147 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
8148 UE = Inputs[i].getNode()->use_end();
8151 if (User != N && !Visited.count(User))
8154 // Make sure that we're not going to promote the non-output-value
8155 // operand(s) or SELECT or SELECT_CC.
8156 // FIXME: Although we could sometimes handle this, and it does occur in
8157 // practice that one of the condition inputs to the select is also one of
8158 // the outputs, we currently can't deal with this.
8159 if (User->getOpcode() == ISD::SELECT) {
8160 if (User->getOperand(0) == Inputs[i])
8162 } else if (User->getOpcode() == ISD::SELECT_CC) {
8163 if (User->getOperand(0) == Inputs[i] ||
8164 User->getOperand(1) == Inputs[i])
8170 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
8171 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
8172 UE = PromOps[i].getNode()->use_end();
8175 if (User != N && !Visited.count(User))
8178 // Make sure that we're not going to promote the non-output-value
8179 // operand(s) or SELECT or SELECT_CC.
8180 // FIXME: Although we could sometimes handle this, and it does occur in
8181 // practice that one of the condition inputs to the select is also one of
8182 // the outputs, we currently can't deal with this.
8183 if (User->getOpcode() == ISD::SELECT) {
8184 if (User->getOperand(0) == PromOps[i])
8186 } else if (User->getOpcode() == ISD::SELECT_CC) {
8187 if (User->getOperand(0) == PromOps[i] ||
8188 User->getOperand(1) == PromOps[i])
8194 // Replace all inputs with the extension operand.
8195 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8196 // Constants may have users outside the cluster of to-be-promoted nodes,
8197 // and so we need to replace those as we do the promotions.
8198 if (isa<ConstantSDNode>(Inputs[i]))
8201 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
8204 // Replace all operations (these are all the same, but have a different
8205 // (i1) return type). DAG.getNode will validate that the types of
8206 // a binary operator match, so go through the list in reverse so that
8207 // we've likely promoted both operands first. Any intermediate truncations or
8208 // extensions disappear.
8209 while (!PromOps.empty()) {
8210 SDValue PromOp = PromOps.back();
8213 if (PromOp.getOpcode() == ISD::TRUNCATE ||
8214 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
8215 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
8216 PromOp.getOpcode() == ISD::ANY_EXTEND) {
8217 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
8218 PromOp.getOperand(0).getValueType() != MVT::i1) {
8219 // The operand is not yet ready (see comment below).
8220 PromOps.insert(PromOps.begin(), PromOp);
8224 SDValue RepValue = PromOp.getOperand(0);
8225 if (isa<ConstantSDNode>(RepValue))
8226 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
8228 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
8233 switch (PromOp.getOpcode()) {
8234 default: C = 0; break;
8235 case ISD::SELECT: C = 1; break;
8236 case ISD::SELECT_CC: C = 2; break;
8239 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
8240 PromOp.getOperand(C).getValueType() != MVT::i1) ||
8241 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
8242 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
8243 // The to-be-promoted operands of this node have not yet been
8244 // promoted (this should be rare because we're going through the
8245 // list backward, but if one of the operands has several users in
8246 // this cluster of to-be-promoted nodes, it is possible).
8247 PromOps.insert(PromOps.begin(), PromOp);
8251 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
8252 PromOp.getNode()->op_end());
8254 // If there are any constant inputs, make sure they're replaced now.
8255 for (unsigned i = 0; i < 2; ++i)
8256 if (isa<ConstantSDNode>(Ops[C+i]))
8257 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
8259 DAG.ReplaceAllUsesOfValueWith(PromOp,
8260 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
8263 // Now we're left with the initial truncation itself.
8264 if (N->getOpcode() == ISD::TRUNCATE)
8265 return N->getOperand(0);
8267 // Otherwise, this is a comparison. The operands to be compared have just
8268 // changed type (to i1), but everything else is the same.
8269 return SDValue(N, 0);
8272 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
8273 DAGCombinerInfo &DCI) const {
8274 SelectionDAG &DAG = DCI.DAG;
8277 // If we're tracking CR bits, we need to be careful that we don't have:
8278 // zext(binary-ops(trunc(x), trunc(y)))
8280 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
8281 // such that we're unnecessarily moving things into CR bits that can more
8282 // efficiently stay in GPRs. Note that if we're not certain that the high
8283 // bits are set as required by the final extension, we still may need to do
8284 // some masking to get the proper behavior.
8286 // This same functionality is important on PPC64 when dealing with
8287 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
8288 // the return values of functions. Because it is so similar, it is handled
8291 if (N->getValueType(0) != MVT::i32 &&
8292 N->getValueType(0) != MVT::i64)
8295 if (!((N->getOperand(0).getValueType() == MVT::i1 &&
8296 Subtarget.useCRBits()) ||
8297 (N->getOperand(0).getValueType() == MVT::i32 &&
8298 Subtarget.isPPC64())))
8301 if (N->getOperand(0).getOpcode() != ISD::AND &&
8302 N->getOperand(0).getOpcode() != ISD::OR &&
8303 N->getOperand(0).getOpcode() != ISD::XOR &&
8304 N->getOperand(0).getOpcode() != ISD::SELECT &&
8305 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
8308 SmallVector<SDValue, 4> Inputs;
8309 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
8310 SmallPtrSet<SDNode *, 16> Visited;
8312 // Visit all inputs, collect all binary operations (and, or, xor and
8313 // select) that are all fed by truncations.
8314 while (!BinOps.empty()) {
8315 SDValue BinOp = BinOps.back();
8318 if (!Visited.insert(BinOp.getNode()).second)
8321 PromOps.push_back(BinOp);
8323 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
8324 // The condition of the select is not promoted.
8325 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
8327 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
8330 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
8331 isa<ConstantSDNode>(BinOp.getOperand(i))) {
8332 Inputs.push_back(BinOp.getOperand(i));
8333 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
8334 BinOp.getOperand(i).getOpcode() == ISD::OR ||
8335 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
8336 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
8337 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
8338 BinOps.push_back(BinOp.getOperand(i));
8340 // We have an input that is not a truncation or another binary
8341 // operation; we'll abort this transformation.
8347 // The operands of a select that must be truncated when the select is
8348 // promoted because the operand is actually part of the to-be-promoted set.
8349 DenseMap<SDNode *, EVT> SelectTruncOp[2];
8351 // Make sure that this is a self-contained cluster of operations (which
8352 // is not quite the same thing as saying that everything has only one
8354 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8355 if (isa<ConstantSDNode>(Inputs[i]))
8358 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
8359 UE = Inputs[i].getNode()->use_end();
8362 if (User != N && !Visited.count(User))
8365 // If we're going to promote the non-output-value operand(s) or SELECT or
8366 // SELECT_CC, record them for truncation.
8367 if (User->getOpcode() == ISD::SELECT) {
8368 if (User->getOperand(0) == Inputs[i])
8369 SelectTruncOp[0].insert(std::make_pair(User,
8370 User->getOperand(0).getValueType()));
8371 } else if (User->getOpcode() == ISD::SELECT_CC) {
8372 if (User->getOperand(0) == Inputs[i])
8373 SelectTruncOp[0].insert(std::make_pair(User,
8374 User->getOperand(0).getValueType()));
8375 if (User->getOperand(1) == Inputs[i])
8376 SelectTruncOp[1].insert(std::make_pair(User,
8377 User->getOperand(1).getValueType()));
8382 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
8383 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
8384 UE = PromOps[i].getNode()->use_end();
8387 if (User != N && !Visited.count(User))
8390 // If we're going to promote the non-output-value operand(s) or SELECT or
8391 // SELECT_CC, record them for truncation.
8392 if (User->getOpcode() == ISD::SELECT) {
8393 if (User->getOperand(0) == PromOps[i])
8394 SelectTruncOp[0].insert(std::make_pair(User,
8395 User->getOperand(0).getValueType()));
8396 } else if (User->getOpcode() == ISD::SELECT_CC) {
8397 if (User->getOperand(0) == PromOps[i])
8398 SelectTruncOp[0].insert(std::make_pair(User,
8399 User->getOperand(0).getValueType()));
8400 if (User->getOperand(1) == PromOps[i])
8401 SelectTruncOp[1].insert(std::make_pair(User,
8402 User->getOperand(1).getValueType()));
8407 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
8408 bool ReallyNeedsExt = false;
8409 if (N->getOpcode() != ISD::ANY_EXTEND) {
8410 // If all of the inputs are not already sign/zero extended, then
8411 // we'll still need to do that at the end.
8412 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8413 if (isa<ConstantSDNode>(Inputs[i]))
8417 Inputs[i].getOperand(0).getValueSizeInBits();
8418 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
8420 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
8421 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
8422 APInt::getHighBitsSet(OpBits,
8423 OpBits-PromBits))) ||
8424 (N->getOpcode() == ISD::SIGN_EXTEND &&
8425 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
8426 (OpBits-(PromBits-1)))) {
8427 ReallyNeedsExt = true;
8433 // Replace all inputs, either with the truncation operand, or a
8434 // truncation or extension to the final output type.
8435 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8436 // Constant inputs need to be replaced with the to-be-promoted nodes that
8437 // use them because they might have users outside of the cluster of
8439 if (isa<ConstantSDNode>(Inputs[i]))
8442 SDValue InSrc = Inputs[i].getOperand(0);
8443 if (Inputs[i].getValueType() == N->getValueType(0))
8444 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
8445 else if (N->getOpcode() == ISD::SIGN_EXTEND)
8446 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8447 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
8448 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8449 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8450 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
8452 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8453 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
8456 // Replace all operations (these are all the same, but have a different
8457 // (promoted) return type). DAG.getNode will validate that the types of
8458 // a binary operator match, so go through the list in reverse so that
8459 // we've likely promoted both operands first.
8460 while (!PromOps.empty()) {
8461 SDValue PromOp = PromOps.back();
8465 switch (PromOp.getOpcode()) {
8466 default: C = 0; break;
8467 case ISD::SELECT: C = 1; break;
8468 case ISD::SELECT_CC: C = 2; break;
8471 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
8472 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
8473 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
8474 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
8475 // The to-be-promoted operands of this node have not yet been
8476 // promoted (this should be rare because we're going through the
8477 // list backward, but if one of the operands has several users in
8478 // this cluster of to-be-promoted nodes, it is possible).
8479 PromOps.insert(PromOps.begin(), PromOp);
8483 // For SELECT and SELECT_CC nodes, we do a similar check for any
8484 // to-be-promoted comparison inputs.
8485 if (PromOp.getOpcode() == ISD::SELECT ||
8486 PromOp.getOpcode() == ISD::SELECT_CC) {
8487 if ((SelectTruncOp[0].count(PromOp.getNode()) &&
8488 PromOp.getOperand(0).getValueType() != N->getValueType(0)) ||
8489 (SelectTruncOp[1].count(PromOp.getNode()) &&
8490 PromOp.getOperand(1).getValueType() != N->getValueType(0))) {
8491 PromOps.insert(PromOps.begin(), PromOp);
8496 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
8497 PromOp.getNode()->op_end());
8499 // If this node has constant inputs, then they'll need to be promoted here.
8500 for (unsigned i = 0; i < 2; ++i) {
8501 if (!isa<ConstantSDNode>(Ops[C+i]))
8503 if (Ops[C+i].getValueType() == N->getValueType(0))
8506 if (N->getOpcode() == ISD::SIGN_EXTEND)
8507 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8508 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8509 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8511 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8514 // If we've promoted the comparison inputs of a SELECT or SELECT_CC,
8515 // truncate them again to the original value type.
8516 if (PromOp.getOpcode() == ISD::SELECT ||
8517 PromOp.getOpcode() == ISD::SELECT_CC) {
8518 auto SI0 = SelectTruncOp[0].find(PromOp.getNode());
8519 if (SI0 != SelectTruncOp[0].end())
8520 Ops[0] = DAG.getNode(ISD::TRUNCATE, dl, SI0->second, Ops[0]);
8521 auto SI1 = SelectTruncOp[1].find(PromOp.getNode());
8522 if (SI1 != SelectTruncOp[1].end())
8523 Ops[1] = DAG.getNode(ISD::TRUNCATE, dl, SI1->second, Ops[1]);
8526 DAG.ReplaceAllUsesOfValueWith(PromOp,
8527 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
8530 // Now we're left with the initial extension itself.
8531 if (!ReallyNeedsExt)
8532 return N->getOperand(0);
8534 // To zero extend, just mask off everything except for the first bit (in the
8536 if (N->getOpcode() == ISD::ZERO_EXTEND)
8537 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
8538 DAG.getConstant(APInt::getLowBitsSet(
8539 N->getValueSizeInBits(0), PromBits),
8540 N->getValueType(0)));
8542 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
8543 "Invalid extension type");
8544 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0));
8546 DAG.getConstant(N->getValueSizeInBits(0)-PromBits, ShiftAmountTy);
8547 return DAG.getNode(ISD::SRA, dl, N->getValueType(0),
8548 DAG.getNode(ISD::SHL, dl, N->getValueType(0),
8549 N->getOperand(0), ShiftCst), ShiftCst);
8552 SDValue PPCTargetLowering::combineFPToIntToFP(SDNode *N,
8553 DAGCombinerInfo &DCI) const {
8554 assert((N->getOpcode() == ISD::SINT_TO_FP ||
8555 N->getOpcode() == ISD::UINT_TO_FP) &&
8556 "Need an int -> FP conversion node here");
8558 if (!Subtarget.has64BitSupport())
8561 SelectionDAG &DAG = DCI.DAG;
8565 // Don't handle ppc_fp128 here or i1 conversions.
8566 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
8568 if (Op.getOperand(0).getValueType() == MVT::i1)
8571 // For i32 intermediate values, unfortunately, the conversion functions
8572 // leave the upper 32 bits of the value are undefined. Within the set of
8573 // scalar instructions, we have no method for zero- or sign-extending the
8574 // value. Thus, we cannot handle i32 intermediate values here.
8575 if (Op.getOperand(0).getValueType() == MVT::i32)
8578 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
8579 "UINT_TO_FP is supported only with FPCVT");
8581 // If we have FCFIDS, then use it when converting to single-precision.
8582 // Otherwise, convert to double-precision and then round.
8583 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
8584 (Op.getOpcode() == ISD::UINT_TO_FP ?
8585 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
8586 (Op.getOpcode() == ISD::UINT_TO_FP ?
8587 PPCISD::FCFIDU : PPCISD::FCFID);
8588 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
8589 MVT::f32 : MVT::f64;
8591 // If we're converting from a float, to an int, and back to a float again,
8592 // then we don't need the store/load pair at all.
8593 if ((Op.getOperand(0).getOpcode() == ISD::FP_TO_UINT &&
8594 Subtarget.hasFPCVT()) ||
8595 (Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT)) {
8596 SDValue Src = Op.getOperand(0).getOperand(0);
8597 if (Src.getValueType() == MVT::f32) {
8598 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
8599 DCI.AddToWorklist(Src.getNode());
8603 Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
8606 SDValue Tmp = DAG.getNode(FCTOp, dl, MVT::f64, Src);
8607 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Tmp);
8609 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) {
8610 FP = DAG.getNode(ISD::FP_ROUND, dl,
8611 MVT::f32, FP, DAG.getIntPtrConstant(0));
8612 DCI.AddToWorklist(FP.getNode());
8621 // expandVSXLoadForLE - Convert VSX loads (which may be intrinsics for
8622 // builtins) into loads with swaps.
8623 SDValue PPCTargetLowering::expandVSXLoadForLE(SDNode *N,
8624 DAGCombinerInfo &DCI) const {
8625 SelectionDAG &DAG = DCI.DAG;
8629 MachineMemOperand *MMO;
8631 switch (N->getOpcode()) {
8633 llvm_unreachable("Unexpected opcode for little endian VSX load");
8635 LoadSDNode *LD = cast<LoadSDNode>(N);
8636 Chain = LD->getChain();
8637 Base = LD->getBasePtr();
8638 MMO = LD->getMemOperand();
8639 // If the MMO suggests this isn't a load of a full vector, leave
8640 // things alone. For a built-in, we have to make the change for
8641 // correctness, so if there is a size problem that will be a bug.
8642 if (MMO->getSize() < 16)
8646 case ISD::INTRINSIC_W_CHAIN: {
8647 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
8648 Chain = Intrin->getChain();
8649 Base = Intrin->getBasePtr();
8650 MMO = Intrin->getMemOperand();
8655 MVT VecTy = N->getValueType(0).getSimpleVT();
8656 SDValue LoadOps[] = { Chain, Base };
8657 SDValue Load = DAG.getMemIntrinsicNode(PPCISD::LXVD2X, dl,
8658 DAG.getVTList(VecTy, MVT::Other),
8659 LoadOps, VecTy, MMO);
8660 DCI.AddToWorklist(Load.getNode());
8661 Chain = Load.getValue(1);
8662 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
8663 DAG.getVTList(VecTy, MVT::Other), Chain, Load);
8664 DCI.AddToWorklist(Swap.getNode());
8668 // expandVSXStoreForLE - Convert VSX stores (which may be intrinsics for
8669 // builtins) into stores with swaps.
8670 SDValue PPCTargetLowering::expandVSXStoreForLE(SDNode *N,
8671 DAGCombinerInfo &DCI) const {
8672 SelectionDAG &DAG = DCI.DAG;
8677 MachineMemOperand *MMO;
8679 switch (N->getOpcode()) {
8681 llvm_unreachable("Unexpected opcode for little endian VSX store");
8683 StoreSDNode *ST = cast<StoreSDNode>(N);
8684 Chain = ST->getChain();
8685 Base = ST->getBasePtr();
8686 MMO = ST->getMemOperand();
8688 // If the MMO suggests this isn't a store of a full vector, leave
8689 // things alone. For a built-in, we have to make the change for
8690 // correctness, so if there is a size problem that will be a bug.
8691 if (MMO->getSize() < 16)
8695 case ISD::INTRINSIC_VOID: {
8696 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
8697 Chain = Intrin->getChain();
8698 // Intrin->getBasePtr() oddly does not get what we want.
8699 Base = Intrin->getOperand(3);
8700 MMO = Intrin->getMemOperand();
8706 SDValue Src = N->getOperand(SrcOpnd);
8707 MVT VecTy = Src.getValueType().getSimpleVT();
8708 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
8709 DAG.getVTList(VecTy, MVT::Other), Chain, Src);
8710 DCI.AddToWorklist(Swap.getNode());
8711 Chain = Swap.getValue(1);
8712 SDValue StoreOps[] = { Chain, Swap, Base };
8713 SDValue Store = DAG.getMemIntrinsicNode(PPCISD::STXVD2X, dl,
8714 DAG.getVTList(MVT::Other),
8715 StoreOps, VecTy, MMO);
8716 DCI.AddToWorklist(Store.getNode());
8720 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
8721 DAGCombinerInfo &DCI) const {
8722 const TargetMachine &TM = getTargetMachine();
8723 SelectionDAG &DAG = DCI.DAG;
8725 switch (N->getOpcode()) {
8728 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8729 if (C->isNullValue()) // 0 << V -> 0.
8730 return N->getOperand(0);
8734 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8735 if (C->isNullValue()) // 0 >>u V -> 0.
8736 return N->getOperand(0);
8740 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8741 if (C->isNullValue() || // 0 >>s V -> 0.
8742 C->isAllOnesValue()) // -1 >>s V -> -1.
8743 return N->getOperand(0);
8746 case ISD::SIGN_EXTEND:
8747 case ISD::ZERO_EXTEND:
8748 case ISD::ANY_EXTEND:
8749 return DAGCombineExtBoolTrunc(N, DCI);
8752 case ISD::SELECT_CC:
8753 return DAGCombineTruncBoolExt(N, DCI);
8754 case ISD::SINT_TO_FP:
8755 case ISD::UINT_TO_FP:
8756 return combineFPToIntToFP(N, DCI);
8758 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
8759 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
8760 !cast<StoreSDNode>(N)->isTruncatingStore() &&
8761 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
8762 N->getOperand(1).getValueType() == MVT::i32 &&
8763 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
8764 SDValue Val = N->getOperand(1).getOperand(0);
8765 if (Val.getValueType() == MVT::f32) {
8766 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8767 DCI.AddToWorklist(Val.getNode());
8769 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
8770 DCI.AddToWorklist(Val.getNode());
8773 N->getOperand(0), Val, N->getOperand(2),
8774 DAG.getValueType(N->getOperand(1).getValueType())
8777 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
8778 DAG.getVTList(MVT::Other), Ops,
8779 cast<StoreSDNode>(N)->getMemoryVT(),
8780 cast<StoreSDNode>(N)->getMemOperand());
8781 DCI.AddToWorklist(Val.getNode());
8785 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
8786 if (cast<StoreSDNode>(N)->isUnindexed() &&
8787 N->getOperand(1).getOpcode() == ISD::BSWAP &&
8788 N->getOperand(1).getNode()->hasOneUse() &&
8789 (N->getOperand(1).getValueType() == MVT::i32 ||
8790 N->getOperand(1).getValueType() == MVT::i16 ||
8791 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8792 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8793 N->getOperand(1).getValueType() == MVT::i64))) {
8794 SDValue BSwapOp = N->getOperand(1).getOperand(0);
8795 // Do an any-extend to 32-bits if this is a half-word input.
8796 if (BSwapOp.getValueType() == MVT::i16)
8797 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
8800 N->getOperand(0), BSwapOp, N->getOperand(2),
8801 DAG.getValueType(N->getOperand(1).getValueType())
8804 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
8805 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
8806 cast<StoreSDNode>(N)->getMemOperand());
8809 // For little endian, VSX stores require generating xxswapd/lxvd2x.
8810 EVT VT = N->getOperand(1).getValueType();
8811 if (VT.isSimple()) {
8812 MVT StoreVT = VT.getSimpleVT();
8813 if (TM.getSubtarget<PPCSubtarget>().hasVSX() &&
8814 TM.getSubtarget<PPCSubtarget>().isLittleEndian() &&
8815 (StoreVT == MVT::v2f64 || StoreVT == MVT::v2i64 ||
8816 StoreVT == MVT::v4f32 || StoreVT == MVT::v4i32))
8817 return expandVSXStoreForLE(N, DCI);
8822 LoadSDNode *LD = cast<LoadSDNode>(N);
8823 EVT VT = LD->getValueType(0);
8825 // For little endian, VSX loads require generating lxvd2x/xxswapd.
8826 if (VT.isSimple()) {
8827 MVT LoadVT = VT.getSimpleVT();
8828 if (TM.getSubtarget<PPCSubtarget>().hasVSX() &&
8829 TM.getSubtarget<PPCSubtarget>().isLittleEndian() &&
8830 (LoadVT == MVT::v2f64 || LoadVT == MVT::v2i64 ||
8831 LoadVT == MVT::v4f32 || LoadVT == MVT::v4i32))
8832 return expandVSXLoadForLE(N, DCI);
8835 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
8836 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
8837 if (ISD::isNON_EXTLoad(N) && VT.isVector() &&
8838 TM.getSubtarget<PPCSubtarget>().hasAltivec() &&
8839 // P8 and later hardware should just use LOAD.
8840 !TM.getSubtarget<PPCSubtarget>().hasP8Vector() &&
8841 (VT == MVT::v16i8 || VT == MVT::v8i16 ||
8842 VT == MVT::v4i32 || VT == MVT::v4f32) &&
8843 LD->getAlignment() < ABIAlignment) {
8844 // This is a type-legal unaligned Altivec load.
8845 SDValue Chain = LD->getChain();
8846 SDValue Ptr = LD->getBasePtr();
8847 bool isLittleEndian = Subtarget.isLittleEndian();
8849 // This implements the loading of unaligned vectors as described in
8850 // the venerable Apple Velocity Engine overview. Specifically:
8851 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
8852 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
8854 // The general idea is to expand a sequence of one or more unaligned
8855 // loads into an alignment-based permutation-control instruction (lvsl
8856 // or lvsr), a series of regular vector loads (which always truncate
8857 // their input address to an aligned address), and a series of
8858 // permutations. The results of these permutations are the requested
8859 // loaded values. The trick is that the last "extra" load is not taken
8860 // from the address you might suspect (sizeof(vector) bytes after the
8861 // last requested load), but rather sizeof(vector) - 1 bytes after the
8862 // last requested vector. The point of this is to avoid a page fault if
8863 // the base address happened to be aligned. This works because if the
8864 // base address is aligned, then adding less than a full vector length
8865 // will cause the last vector in the sequence to be (re)loaded.
8866 // Otherwise, the next vector will be fetched as you might suspect was
8869 // We might be able to reuse the permutation generation from
8870 // a different base address offset from this one by an aligned amount.
8871 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
8872 // optimization later.
8873 Intrinsic::ID Intr = (isLittleEndian ?
8874 Intrinsic::ppc_altivec_lvsr :
8875 Intrinsic::ppc_altivec_lvsl);
8876 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, MVT::v16i8);
8878 // Create the new MMO for the new base load. It is like the original MMO,
8879 // but represents an area in memory almost twice the vector size centered
8880 // on the original address. If the address is unaligned, we might start
8881 // reading up to (sizeof(vector)-1) bytes below the address of the
8882 // original unaligned load.
8883 MachineFunction &MF = DAG.getMachineFunction();
8884 MachineMemOperand *BaseMMO =
8885 MF.getMachineMemOperand(LD->getMemOperand(),
8886 -LD->getMemoryVT().getStoreSize()+1,
8887 2*LD->getMemoryVT().getStoreSize()-1);
8889 // Create the new base load.
8890 SDValue LDXIntID = DAG.getTargetConstant(Intrinsic::ppc_altivec_lvx,
8892 SDValue BaseLoadOps[] = { Chain, LDXIntID, Ptr };
8894 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
8895 DAG.getVTList(MVT::v4i32, MVT::Other),
8896 BaseLoadOps, MVT::v4i32, BaseMMO);
8898 // Note that the value of IncOffset (which is provided to the next
8899 // load's pointer info offset value, and thus used to calculate the
8900 // alignment), and the value of IncValue (which is actually used to
8901 // increment the pointer value) are different! This is because we
8902 // require the next load to appear to be aligned, even though it
8903 // is actually offset from the base pointer by a lesser amount.
8904 int IncOffset = VT.getSizeInBits() / 8;
8905 int IncValue = IncOffset;
8907 // Walk (both up and down) the chain looking for another load at the real
8908 // (aligned) offset (the alignment of the other load does not matter in
8909 // this case). If found, then do not use the offset reduction trick, as
8910 // that will prevent the loads from being later combined (as they would
8911 // otherwise be duplicates).
8912 if (!findConsecutiveLoad(LD, DAG))
8915 SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
8916 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
8918 MachineMemOperand *ExtraMMO =
8919 MF.getMachineMemOperand(LD->getMemOperand(),
8920 1, 2*LD->getMemoryVT().getStoreSize()-1);
8921 SDValue ExtraLoadOps[] = { Chain, LDXIntID, Ptr };
8923 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
8924 DAG.getVTList(MVT::v4i32, MVT::Other),
8925 ExtraLoadOps, MVT::v4i32, ExtraMMO);
8927 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
8928 BaseLoad.getValue(1), ExtraLoad.getValue(1));
8930 // Because vperm has a big-endian bias, we must reverse the order
8931 // of the input vectors and complement the permute control vector
8932 // when generating little endian code. We have already handled the
8933 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
8934 // and ExtraLoad here.
8937 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8938 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
8940 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8941 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
8943 if (VT != MVT::v4i32)
8944 Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm);
8946 // The output of the permutation is our loaded result, the TokenFactor is
8948 DCI.CombineTo(N, Perm, TF);
8949 return SDValue(N, 0);
8953 case ISD::INTRINSIC_WO_CHAIN: {
8954 bool isLittleEndian = Subtarget.isLittleEndian();
8955 Intrinsic::ID Intr = (isLittleEndian ?
8956 Intrinsic::ppc_altivec_lvsr :
8957 Intrinsic::ppc_altivec_lvsl);
8958 if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() == Intr &&
8959 N->getOperand(1)->getOpcode() == ISD::ADD) {
8960 SDValue Add = N->getOperand(1);
8962 if (DAG.MaskedValueIsZero(Add->getOperand(1),
8963 APInt::getAllOnesValue(4 /* 16 byte alignment */).zext(
8964 Add.getValueType().getScalarType().getSizeInBits()))) {
8965 SDNode *BasePtr = Add->getOperand(0).getNode();
8966 for (SDNode::use_iterator UI = BasePtr->use_begin(),
8967 UE = BasePtr->use_end(); UI != UE; ++UI) {
8968 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8969 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() ==
8971 // We've found another LVSL/LVSR, and this address is an aligned
8972 // multiple of that one. The results will be the same, so use the
8973 // one we've just found instead.
8975 return SDValue(*UI, 0);
8983 case ISD::INTRINSIC_W_CHAIN: {
8984 // For little endian, VSX loads require generating lxvd2x/xxswapd.
8985 if (TM.getSubtarget<PPCSubtarget>().hasVSX() &&
8986 TM.getSubtarget<PPCSubtarget>().isLittleEndian()) {
8987 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
8990 case Intrinsic::ppc_vsx_lxvw4x:
8991 case Intrinsic::ppc_vsx_lxvd2x:
8992 return expandVSXLoadForLE(N, DCI);
8997 case ISD::INTRINSIC_VOID: {
8998 // For little endian, VSX stores require generating xxswapd/stxvd2x.
8999 if (TM.getSubtarget<PPCSubtarget>().hasVSX() &&
9000 TM.getSubtarget<PPCSubtarget>().isLittleEndian()) {
9001 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9004 case Intrinsic::ppc_vsx_stxvw4x:
9005 case Intrinsic::ppc_vsx_stxvd2x:
9006 return expandVSXStoreForLE(N, DCI);
9012 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
9013 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
9014 N->getOperand(0).hasOneUse() &&
9015 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
9016 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
9017 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
9018 N->getValueType(0) == MVT::i64))) {
9019 SDValue Load = N->getOperand(0);
9020 LoadSDNode *LD = cast<LoadSDNode>(Load);
9021 // Create the byte-swapping load.
9023 LD->getChain(), // Chain
9024 LD->getBasePtr(), // Ptr
9025 DAG.getValueType(N->getValueType(0)) // VT
9028 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
9029 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
9030 MVT::i64 : MVT::i32, MVT::Other),
9031 Ops, LD->getMemoryVT(), LD->getMemOperand());
9033 // If this is an i16 load, insert the truncate.
9034 SDValue ResVal = BSLoad;
9035 if (N->getValueType(0) == MVT::i16)
9036 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
9038 // First, combine the bswap away. This makes the value produced by the
9040 DCI.CombineTo(N, ResVal);
9042 // Next, combine the load away, we give it a bogus result value but a real
9043 // chain result. The result value is dead because the bswap is dead.
9044 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
9046 // Return N so it doesn't get rechecked!
9047 return SDValue(N, 0);
9051 case PPCISD::VCMP: {
9052 // If a VCMPo node already exists with exactly the same operands as this
9053 // node, use its result instead of this node (VCMPo computes both a CR6 and
9054 // a normal output).
9056 if (!N->getOperand(0).hasOneUse() &&
9057 !N->getOperand(1).hasOneUse() &&
9058 !N->getOperand(2).hasOneUse()) {
9060 // Scan all of the users of the LHS, looking for VCMPo's that match.
9061 SDNode *VCMPoNode = nullptr;
9063 SDNode *LHSN = N->getOperand(0).getNode();
9064 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
9066 if (UI->getOpcode() == PPCISD::VCMPo &&
9067 UI->getOperand(1) == N->getOperand(1) &&
9068 UI->getOperand(2) == N->getOperand(2) &&
9069 UI->getOperand(0) == N->getOperand(0)) {
9074 // If there is no VCMPo node, or if the flag value has a single use, don't
9076 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
9079 // Look at the (necessarily single) use of the flag value. If it has a
9080 // chain, this transformation is more complex. Note that multiple things
9081 // could use the value result, which we should ignore.
9082 SDNode *FlagUser = nullptr;
9083 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
9084 FlagUser == nullptr; ++UI) {
9085 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
9087 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
9088 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
9095 // If the user is a MFOCRF instruction, we know this is safe.
9096 // Otherwise we give up for right now.
9097 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
9098 return SDValue(VCMPoNode, 0);
9103 SDValue Cond = N->getOperand(1);
9104 SDValue Target = N->getOperand(2);
9106 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
9107 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
9108 Intrinsic::ppc_is_decremented_ctr_nonzero) {
9110 // We now need to make the intrinsic dead (it cannot be instruction
9112 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
9113 assert(Cond.getNode()->hasOneUse() &&
9114 "Counter decrement has more than one use");
9116 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
9117 N->getOperand(0), Target);
9122 // If this is a branch on an altivec predicate comparison, lower this so
9123 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
9124 // lowering is done pre-legalize, because the legalizer lowers the predicate
9125 // compare down to code that is difficult to reassemble.
9126 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
9127 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
9129 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
9130 // value. If so, pass-through the AND to get to the intrinsic.
9131 if (LHS.getOpcode() == ISD::AND &&
9132 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
9133 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
9134 Intrinsic::ppc_is_decremented_ctr_nonzero &&
9135 isa<ConstantSDNode>(LHS.getOperand(1)) &&
9136 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
9138 LHS = LHS.getOperand(0);
9140 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
9141 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
9142 Intrinsic::ppc_is_decremented_ctr_nonzero &&
9143 isa<ConstantSDNode>(RHS)) {
9144 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
9145 "Counter decrement comparison is not EQ or NE");
9147 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
9148 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
9149 (CC == ISD::SETNE && !Val);
9151 // We now need to make the intrinsic dead (it cannot be instruction
9153 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
9154 assert(LHS.getNode()->hasOneUse() &&
9155 "Counter decrement has more than one use");
9157 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
9158 N->getOperand(0), N->getOperand(4));
9164 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
9165 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
9166 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
9167 assert(isDot && "Can't compare against a vector result!");
9169 // If this is a comparison against something other than 0/1, then we know
9170 // that the condition is never/always true.
9171 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
9172 if (Val != 0 && Val != 1) {
9173 if (CC == ISD::SETEQ) // Cond never true, remove branch.
9174 return N->getOperand(0);
9175 // Always !=, turn it into an unconditional branch.
9176 return DAG.getNode(ISD::BR, dl, MVT::Other,
9177 N->getOperand(0), N->getOperand(4));
9180 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
9182 // Create the PPCISD altivec 'dot' comparison node.
9184 LHS.getOperand(2), // LHS of compare
9185 LHS.getOperand(3), // RHS of compare
9186 DAG.getConstant(CompareOpc, MVT::i32)
9188 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
9189 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
9191 // Unpack the result based on how the target uses it.
9192 PPC::Predicate CompOpc;
9193 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
9194 default: // Can't happen, don't crash on invalid number though.
9195 case 0: // Branch on the value of the EQ bit of CR6.
9196 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
9198 case 1: // Branch on the inverted value of the EQ bit of CR6.
9199 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
9201 case 2: // Branch on the value of the LT bit of CR6.
9202 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
9204 case 3: // Branch on the inverted value of the LT bit of CR6.
9205 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
9209 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
9210 DAG.getConstant(CompOpc, MVT::i32),
9211 DAG.getRegister(PPC::CR6, MVT::i32),
9212 N->getOperand(4), CompNode.getValue(1));
9222 PPCTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
9224 std::vector<SDNode *> *Created) const {
9225 // fold (sdiv X, pow2)
9226 EVT VT = N->getValueType(0);
9227 if (VT == MVT::i64 && !Subtarget.isPPC64())
9229 if ((VT != MVT::i32 && VT != MVT::i64) ||
9230 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
9234 SDValue N0 = N->getOperand(0);
9236 bool IsNegPow2 = (-Divisor).isPowerOf2();
9237 unsigned Lg2 = (IsNegPow2 ? -Divisor : Divisor).countTrailingZeros();
9238 SDValue ShiftAmt = DAG.getConstant(Lg2, VT);
9240 SDValue Op = DAG.getNode(PPCISD::SRA_ADDZE, DL, VT, N0, ShiftAmt);
9242 Created->push_back(Op.getNode());
9245 Op = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT), Op);
9247 Created->push_back(Op.getNode());
9253 //===----------------------------------------------------------------------===//
9254 // Inline Assembly Support
9255 //===----------------------------------------------------------------------===//
9257 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
9260 const SelectionDAG &DAG,
9261 unsigned Depth) const {
9262 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
9263 switch (Op.getOpcode()) {
9265 case PPCISD::LBRX: {
9266 // lhbrx is known to have the top bits cleared out.
9267 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
9268 KnownZero = 0xFFFF0000;
9271 case ISD::INTRINSIC_WO_CHAIN: {
9272 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
9274 case Intrinsic::ppc_altivec_vcmpbfp_p:
9275 case Intrinsic::ppc_altivec_vcmpeqfp_p:
9276 case Intrinsic::ppc_altivec_vcmpequb_p:
9277 case Intrinsic::ppc_altivec_vcmpequh_p:
9278 case Intrinsic::ppc_altivec_vcmpequw_p:
9279 case Intrinsic::ppc_altivec_vcmpgefp_p:
9280 case Intrinsic::ppc_altivec_vcmpgtfp_p:
9281 case Intrinsic::ppc_altivec_vcmpgtsb_p:
9282 case Intrinsic::ppc_altivec_vcmpgtsh_p:
9283 case Intrinsic::ppc_altivec_vcmpgtsw_p:
9284 case Intrinsic::ppc_altivec_vcmpgtub_p:
9285 case Intrinsic::ppc_altivec_vcmpgtuh_p:
9286 case Intrinsic::ppc_altivec_vcmpgtuw_p:
9287 KnownZero = ~1U; // All bits but the low one are known to be zero.
9294 unsigned PPCTargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
9295 switch (Subtarget.getDarwinDirective()) {
9300 case PPC::DIR_PWR5X:
9302 case PPC::DIR_PWR6X:
9304 case PPC::DIR_PWR8: {
9308 const PPCInstrInfo *TII =
9309 static_cast<const PPCInstrInfo *>(getTargetMachine().getSubtargetImpl()->
9312 // For small loops (between 5 and 8 instructions), align to a 32-byte
9313 // boundary so that the entire loop fits in one instruction-cache line.
9314 uint64_t LoopSize = 0;
9315 for (auto I = ML->block_begin(), IE = ML->block_end(); I != IE; ++I)
9316 for (auto J = (*I)->begin(), JE = (*I)->end(); J != JE; ++J)
9317 LoopSize += TII->GetInstSizeInBytes(J);
9319 if (LoopSize > 16 && LoopSize <= 32)
9326 return TargetLowering::getPrefLoopAlignment(ML);
9329 /// getConstraintType - Given a constraint, return the type of
9330 /// constraint it is for this target.
9331 PPCTargetLowering::ConstraintType
9332 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
9333 if (Constraint.size() == 1) {
9334 switch (Constraint[0]) {
9341 return C_RegisterClass;
9343 // FIXME: While Z does indicate a memory constraint, it specifically
9344 // indicates an r+r address (used in conjunction with the 'y' modifier
9345 // in the replacement string). Currently, we're forcing the base
9346 // register to be r0 in the asm printer (which is interpreted as zero)
9347 // and forming the complete address in the second register. This is
9351 } else if (Constraint == "wc") { // individual CR bits.
9352 return C_RegisterClass;
9353 } else if (Constraint == "wa" || Constraint == "wd" ||
9354 Constraint == "wf" || Constraint == "ws") {
9355 return C_RegisterClass; // VSX registers.
9357 return TargetLowering::getConstraintType(Constraint);
9360 /// Examine constraint type and operand type and determine a weight value.
9361 /// This object must already have been set up with the operand type
9362 /// and the current alternative constraint selected.
9363 TargetLowering::ConstraintWeight
9364 PPCTargetLowering::getSingleConstraintMatchWeight(
9365 AsmOperandInfo &info, const char *constraint) const {
9366 ConstraintWeight weight = CW_Invalid;
9367 Value *CallOperandVal = info.CallOperandVal;
9368 // If we don't have a value, we can't do a match,
9369 // but allow it at the lowest weight.
9370 if (!CallOperandVal)
9372 Type *type = CallOperandVal->getType();
9374 // Look at the constraint type.
9375 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
9376 return CW_Register; // an individual CR bit.
9377 else if ((StringRef(constraint) == "wa" ||
9378 StringRef(constraint) == "wd" ||
9379 StringRef(constraint) == "wf") &&
9382 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
9385 switch (*constraint) {
9387 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
9390 if (type->isIntegerTy())
9391 weight = CW_Register;
9394 if (type->isFloatTy())
9395 weight = CW_Register;
9398 if (type->isDoubleTy())
9399 weight = CW_Register;
9402 if (type->isVectorTy())
9403 weight = CW_Register;
9406 weight = CW_Register;
9415 std::pair<unsigned, const TargetRegisterClass*>
9416 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
9418 if (Constraint.size() == 1) {
9419 // GCC RS6000 Constraint Letters
9420 switch (Constraint[0]) {
9422 if (VT == MVT::i64 && Subtarget.isPPC64())
9423 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
9424 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
9426 if (VT == MVT::i64 && Subtarget.isPPC64())
9427 return std::make_pair(0U, &PPC::G8RCRegClass);
9428 return std::make_pair(0U, &PPC::GPRCRegClass);
9430 if (VT == MVT::f32 || VT == MVT::i32)
9431 return std::make_pair(0U, &PPC::F4RCRegClass);
9432 if (VT == MVT::f64 || VT == MVT::i64)
9433 return std::make_pair(0U, &PPC::F8RCRegClass);
9436 return std::make_pair(0U, &PPC::VRRCRegClass);
9438 return std::make_pair(0U, &PPC::CRRCRegClass);
9440 } else if (Constraint == "wc") { // an individual CR bit.
9441 return std::make_pair(0U, &PPC::CRBITRCRegClass);
9442 } else if (Constraint == "wa" || Constraint == "wd" ||
9443 Constraint == "wf") {
9444 return std::make_pair(0U, &PPC::VSRCRegClass);
9445 } else if (Constraint == "ws") {
9446 return std::make_pair(0U, &PPC::VSFRCRegClass);
9449 std::pair<unsigned, const TargetRegisterClass*> R =
9450 TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
9452 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
9453 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
9454 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
9456 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
9457 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
9458 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
9459 PPC::GPRCRegClass.contains(R.first)) {
9460 const TargetRegisterInfo *TRI =
9461 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
9462 return std::make_pair(TRI->getMatchingSuperReg(R.first,
9463 PPC::sub_32, &PPC::G8RCRegClass),
9464 &PPC::G8RCRegClass);
9467 // GCC accepts 'cc' as an alias for 'cr0', and we need to do the same.
9468 if (!R.second && StringRef("{cc}").equals_lower(Constraint)) {
9470 R.second = &PPC::CRRCRegClass;
9477 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
9478 /// vector. If it is invalid, don't add anything to Ops.
9479 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
9480 std::string &Constraint,
9481 std::vector<SDValue>&Ops,
9482 SelectionDAG &DAG) const {
9485 // Only support length 1 constraints.
9486 if (Constraint.length() > 1) return;
9488 char Letter = Constraint[0];
9499 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
9500 if (!CST) return; // Must be an immediate to match.
9501 int64_t Value = CST->getSExtValue();
9502 EVT TCVT = MVT::i64; // All constants taken to be 64 bits so that negative
9503 // numbers are printed as such.
9505 default: llvm_unreachable("Unknown constraint letter!");
9506 case 'I': // "I" is a signed 16-bit constant.
9507 if (isInt<16>(Value))
9508 Result = DAG.getTargetConstant(Value, TCVT);
9510 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
9511 if (isShiftedUInt<16, 16>(Value))
9512 Result = DAG.getTargetConstant(Value, TCVT);
9514 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
9515 if (isShiftedInt<16, 16>(Value))
9516 Result = DAG.getTargetConstant(Value, TCVT);
9518 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
9519 if (isUInt<16>(Value))
9520 Result = DAG.getTargetConstant(Value, TCVT);
9522 case 'M': // "M" is a constant that is greater than 31.
9524 Result = DAG.getTargetConstant(Value, TCVT);
9526 case 'N': // "N" is a positive constant that is an exact power of two.
9527 if (Value > 0 && isPowerOf2_64(Value))
9528 Result = DAG.getTargetConstant(Value, TCVT);
9530 case 'O': // "O" is the constant zero.
9532 Result = DAG.getTargetConstant(Value, TCVT);
9534 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
9535 if (isInt<16>(-Value))
9536 Result = DAG.getTargetConstant(Value, TCVT);
9543 if (Result.getNode()) {
9544 Ops.push_back(Result);
9548 // Handle standard constraint letters.
9549 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
9552 // isLegalAddressingMode - Return true if the addressing mode represented
9553 // by AM is legal for this target, for a load/store of the specified type.
9554 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
9556 // FIXME: PPC does not allow r+i addressing modes for vectors!
9558 // PPC allows a sign-extended 16-bit immediate field.
9559 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
9562 // No global is ever allowed as a base.
9566 // PPC only support r+r,
9568 case 0: // "r+i" or just "i", depending on HasBaseReg.
9571 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
9573 // Otherwise we have r+r or r+i.
9576 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
9578 // Allow 2*r as r+r.
9581 // No other scales are supported.
9588 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
9589 SelectionDAG &DAG) const {
9590 MachineFunction &MF = DAG.getMachineFunction();
9591 MachineFrameInfo *MFI = MF.getFrameInfo();
9592 MFI->setReturnAddressIsTaken(true);
9594 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
9598 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9600 // Make sure the function does not optimize away the store of the RA to
9602 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
9603 FuncInfo->setLRStoreRequired();
9604 bool isPPC64 = Subtarget.isPPC64();
9605 bool isDarwinABI = Subtarget.isDarwinABI();
9608 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9611 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
9612 isPPC64? MVT::i64 : MVT::i32);
9613 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9614 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9616 MachinePointerInfo(), false, false, false, 0);
9619 // Just load the return address off the stack.
9620 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
9621 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9622 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9625 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
9626 SelectionDAG &DAG) const {
9628 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9630 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
9631 bool isPPC64 = PtrVT == MVT::i64;
9633 MachineFunction &MF = DAG.getMachineFunction();
9634 MachineFrameInfo *MFI = MF.getFrameInfo();
9635 MFI->setFrameAddressIsTaken(true);
9637 // Naked functions never have a frame pointer, and so we use r1. For all
9638 // other functions, this decision must be delayed until during PEI.
9640 if (MF.getFunction()->getAttributes().hasAttribute(
9641 AttributeSet::FunctionIndex, Attribute::Naked))
9642 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
9644 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
9646 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
9649 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
9650 FrameAddr, MachinePointerInfo(), false, false,
9655 // FIXME? Maybe this could be a TableGen attribute on some registers and
9656 // this table could be generated automatically from RegInfo.
9657 unsigned PPCTargetLowering::getRegisterByName(const char* RegName,
9659 bool isPPC64 = Subtarget.isPPC64();
9660 bool isDarwinABI = Subtarget.isDarwinABI();
9662 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
9663 (!isPPC64 && VT != MVT::i32))
9664 report_fatal_error("Invalid register global variable type");
9666 bool is64Bit = isPPC64 && VT == MVT::i64;
9667 unsigned Reg = StringSwitch<unsigned>(RegName)
9668 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
9669 .Case("r2", isDarwinABI ? 0 : (is64Bit ? PPC::X2 : PPC::R2))
9670 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
9671 (is64Bit ? PPC::X13 : PPC::R13))
9676 report_fatal_error("Invalid register name global variable");
9680 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
9681 // The PowerPC target isn't yet aware of offsets.
9685 bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
9687 unsigned Intrinsic) const {
9689 switch (Intrinsic) {
9690 case Intrinsic::ppc_altivec_lvx:
9691 case Intrinsic::ppc_altivec_lvxl:
9692 case Intrinsic::ppc_altivec_lvebx:
9693 case Intrinsic::ppc_altivec_lvehx:
9694 case Intrinsic::ppc_altivec_lvewx:
9695 case Intrinsic::ppc_vsx_lxvd2x:
9696 case Intrinsic::ppc_vsx_lxvw4x: {
9698 switch (Intrinsic) {
9699 case Intrinsic::ppc_altivec_lvebx:
9702 case Intrinsic::ppc_altivec_lvehx:
9705 case Intrinsic::ppc_altivec_lvewx:
9708 case Intrinsic::ppc_vsx_lxvd2x:
9716 Info.opc = ISD::INTRINSIC_W_CHAIN;
9718 Info.ptrVal = I.getArgOperand(0);
9719 Info.offset = -VT.getStoreSize()+1;
9720 Info.size = 2*VT.getStoreSize()-1;
9723 Info.readMem = true;
9724 Info.writeMem = false;
9727 case Intrinsic::ppc_altivec_stvx:
9728 case Intrinsic::ppc_altivec_stvxl:
9729 case Intrinsic::ppc_altivec_stvebx:
9730 case Intrinsic::ppc_altivec_stvehx:
9731 case Intrinsic::ppc_altivec_stvewx:
9732 case Intrinsic::ppc_vsx_stxvd2x:
9733 case Intrinsic::ppc_vsx_stxvw4x: {
9735 switch (Intrinsic) {
9736 case Intrinsic::ppc_altivec_stvebx:
9739 case Intrinsic::ppc_altivec_stvehx:
9742 case Intrinsic::ppc_altivec_stvewx:
9745 case Intrinsic::ppc_vsx_stxvd2x:
9753 Info.opc = ISD::INTRINSIC_VOID;
9755 Info.ptrVal = I.getArgOperand(1);
9756 Info.offset = -VT.getStoreSize()+1;
9757 Info.size = 2*VT.getStoreSize()-1;
9760 Info.readMem = false;
9761 Info.writeMem = true;
9771 /// getOptimalMemOpType - Returns the target specific optimal type for load
9772 /// and store operations as a result of memset, memcpy, and memmove
9773 /// lowering. If DstAlign is zero that means it's safe to destination
9774 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
9775 /// means there isn't a need to check it against alignment requirement,
9776 /// probably because the source does not need to be loaded. If 'IsMemset' is
9777 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
9778 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
9779 /// source is constant so it does not need to be loaded.
9780 /// It returns EVT::Other if the type should be determined using generic
9781 /// target-independent logic.
9782 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
9783 unsigned DstAlign, unsigned SrcAlign,
9784 bool IsMemset, bool ZeroMemset,
9786 MachineFunction &MF) const {
9787 if (Subtarget.isPPC64()) {
9794 /// \brief Returns true if it is beneficial to convert a load of a constant
9795 /// to just the constant itself.
9796 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
9798 assert(Ty->isIntegerTy());
9800 unsigned BitSize = Ty->getPrimitiveSizeInBits();
9801 if (BitSize == 0 || BitSize > 64)
9806 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
9807 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
9809 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
9810 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
9811 return NumBits1 == 64 && NumBits2 == 32;
9814 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
9815 if (!VT1.isInteger() || !VT2.isInteger())
9817 unsigned NumBits1 = VT1.getSizeInBits();
9818 unsigned NumBits2 = VT2.getSizeInBits();
9819 return NumBits1 == 64 && NumBits2 == 32;
9822 bool PPCTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
9823 // Generally speaking, zexts are not free, but they are free when they can be
9824 // folded with other operations.
9825 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Val)) {
9826 EVT MemVT = LD->getMemoryVT();
9827 if ((MemVT == MVT::i1 || MemVT == MVT::i8 || MemVT == MVT::i16 ||
9828 (Subtarget.isPPC64() && MemVT == MVT::i32)) &&
9829 (LD->getExtensionType() == ISD::NON_EXTLOAD ||
9830 LD->getExtensionType() == ISD::ZEXTLOAD))
9834 // FIXME: Add other cases...
9835 // - 32-bit shifts with a zext to i64
9836 // - zext after ctlz, bswap, etc.
9837 // - zext after and by a constant mask
9839 return TargetLowering::isZExtFree(Val, VT2);
9842 bool PPCTargetLowering::isFPExtFree(EVT VT) const {
9843 assert(VT.isFloatingPoint());
9847 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
9848 return isInt<16>(Imm) || isUInt<16>(Imm);
9851 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
9852 return isInt<16>(Imm) || isUInt<16>(Imm);
9855 bool PPCTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
9859 if (DisablePPCUnaligned)
9862 // PowerPC supports unaligned memory access for simple non-vector types.
9863 // Although accessing unaligned addresses is not as efficient as accessing
9864 // aligned addresses, it is generally more efficient than manual expansion,
9865 // and generally only traps for software emulation when crossing page
9871 if (VT.getSimpleVT().isVector()) {
9872 if (Subtarget.hasVSX()) {
9873 if (VT != MVT::v2f64 && VT != MVT::v2i64 &&
9874 VT != MVT::v4f32 && VT != MVT::v4i32)
9881 if (VT == MVT::ppcf128)
9890 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
9891 VT = VT.getScalarType();
9896 switch (VT.getSimpleVT().SimpleTy) {
9908 PPCTargetLowering::getScratchRegisters(CallingConv::ID) const {
9909 // LR is a callee-save register, but we must treat it as clobbered by any call
9910 // site. Hence we include LR in the scratch registers, which are in turn added
9911 // as implicit-defs for stackmaps and patchpoints. The same reasoning applies
9912 // to CTR, which is used by any indirect call.
9913 static const MCPhysReg ScratchRegs[] = {
9914 PPC::X11, PPC::X12, PPC::LR8, PPC::CTR8, 0
9921 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
9922 EVT VT , unsigned DefinedValues) const {
9923 if (VT == MVT::v2i64)
9926 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
9929 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
9930 if (DisableILPPref || Subtarget.enableMachineScheduler())
9931 return TargetLowering::getSchedulingPreference(N);
9936 // Create a fast isel object.
9938 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
9939 const TargetLibraryInfo *LibInfo) const {
9940 return PPC::createFastISel(FuncInfo, LibInfo);