1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCMachineFunctionInfo.h"
16 #include "PPCPredicates.h"
17 #include "PPCTargetMachine.h"
18 #include "PPCPerfectShuffle.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/VectorExtras.h"
21 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/PseudoSourceValue.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/Constants.h"
30 #include "llvm/Function.h"
31 #include "llvm/Intrinsics.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/Support/CommandLine.h"
37 static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc",
38 cl::desc("enable preincrement load/store generation on PPC (experimental)"),
41 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
42 : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) {
46 // Use _setjmp/_longjmp instead of setjmp/longjmp.
47 setUseUnderscoreSetJmp(true);
48 setUseUnderscoreLongJmp(true);
50 // Set up the register classes.
51 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
52 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
53 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
55 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
56 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
57 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand);
59 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
61 // PowerPC has pre-inc load and store's.
62 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
63 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
64 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
65 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
66 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
67 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
68 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
69 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
70 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
71 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
73 // Shortening conversions involving ppcf128 get expanded (2 regs -> 1 reg)
74 setConvertAction(MVT::ppcf128, MVT::f64, Expand);
75 setConvertAction(MVT::ppcf128, MVT::f32, Expand);
76 // This is used in the ppcf128->int sequence. Note it has different semantics
77 // from FP_ROUND: that rounds to nearest, this rounds to zero.
78 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
80 // PowerPC has no intrinsics for these particular operations
81 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
82 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
83 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
84 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
86 // PowerPC has no SREM/UREM instructions
87 setOperationAction(ISD::SREM, MVT::i32, Expand);
88 setOperationAction(ISD::UREM, MVT::i32, Expand);
89 setOperationAction(ISD::SREM, MVT::i64, Expand);
90 setOperationAction(ISD::UREM, MVT::i64, Expand);
92 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
93 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
94 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
95 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
96 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
97 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
98 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
99 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
100 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
102 // We don't support sin/cos/sqrt/fmod/pow
103 setOperationAction(ISD::FSIN , MVT::f64, Expand);
104 setOperationAction(ISD::FCOS , MVT::f64, Expand);
105 setOperationAction(ISD::FREM , MVT::f64, Expand);
106 setOperationAction(ISD::FPOW , MVT::f64, Expand);
107 setOperationAction(ISD::FSIN , MVT::f32, Expand);
108 setOperationAction(ISD::FCOS , MVT::f32, Expand);
109 setOperationAction(ISD::FREM , MVT::f32, Expand);
110 setOperationAction(ISD::FPOW , MVT::f32, Expand);
112 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
114 // If we're enabling GP optimizations, use hardware square root
115 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
116 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
117 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
120 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
121 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
123 // PowerPC does not have BSWAP, CTPOP or CTTZ
124 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
125 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
126 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
127 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
128 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
129 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
131 // PowerPC does not have ROTR
132 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
134 // PowerPC does not have Select
135 setOperationAction(ISD::SELECT, MVT::i32, Expand);
136 setOperationAction(ISD::SELECT, MVT::i64, Expand);
137 setOperationAction(ISD::SELECT, MVT::f32, Expand);
138 setOperationAction(ISD::SELECT, MVT::f64, Expand);
140 // PowerPC wants to turn select_cc of FP into fsel when possible.
141 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
142 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
144 // PowerPC wants to optimize integer setcc a bit
145 setOperationAction(ISD::SETCC, MVT::i32, Custom);
147 // PowerPC does not have BRCOND which requires SetCC
148 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
150 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
152 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
153 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
155 // PowerPC does not have [U|S]INT_TO_FP
156 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
157 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
159 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
160 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
161 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
162 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
164 // We cannot sextinreg(i1). Expand to shifts.
165 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
167 // Support label based line numbers.
168 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
169 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
171 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
172 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
173 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
174 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
177 // We want to legalize GlobalAddress and ConstantPool nodes into the
178 // appropriate instructions to materialize the address.
179 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
180 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
181 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
182 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
183 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
184 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
185 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
186 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
188 // RET must be custom lowered, to meet ABI requirements
189 setOperationAction(ISD::RET , MVT::Other, Custom);
191 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
192 setOperationAction(ISD::VASTART , MVT::Other, Custom);
194 // VAARG is custom lowered with ELF 32 ABI
195 if (TM.getSubtarget<PPCSubtarget>().isELF32_ABI())
196 setOperationAction(ISD::VAARG, MVT::Other, Custom);
198 setOperationAction(ISD::VAARG, MVT::Other, Expand);
200 // Use the default implementation.
201 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
202 setOperationAction(ISD::VAEND , MVT::Other, Expand);
203 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
204 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
205 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
206 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
208 // We want to custom lower some of our intrinsics.
209 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
211 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
212 // They also have instructions for converting between i64 and fp.
213 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
214 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
215 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
216 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
217 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
219 // FIXME: disable this lowered code. This generates 64-bit register values,
220 // and we don't model the fact that the top part is clobbered by calls. We
221 // need to flag these together so that the value isn't live across a call.
222 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
224 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
225 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
227 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
228 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
231 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
232 // 64-bit PowerPC implementations can support i64 types directly
233 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
234 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
235 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
237 // 32-bit PowerPC wants to expand i64 shifts itself.
238 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
239 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
240 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
243 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
244 // First set operation action for all vector types to expand. Then we
245 // will selectively turn on ones that can be effectively codegen'd.
246 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
247 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
248 // add/sub are legal for all supported vector VT's.
249 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal);
250 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal);
252 // We promote all shuffles to v16i8.
253 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote);
254 AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8);
256 // We promote all non-typed operations to v4i32.
257 setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote);
258 AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32);
259 setOperationAction(ISD::OR , (MVT::ValueType)VT, Promote);
260 AddPromotedToType (ISD::OR , (MVT::ValueType)VT, MVT::v4i32);
261 setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote);
262 AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32);
263 setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote);
264 AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32);
265 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
266 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32);
267 setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote);
268 AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32);
270 // No other operations are legal.
271 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
272 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
273 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
274 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
275 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
276 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
277 setOperationAction(ISD::FNEG, (MVT::ValueType)VT, Expand);
278 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
279 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
280 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
281 setOperationAction(ISD::UMUL_LOHI, (MVT::ValueType)VT, Expand);
282 setOperationAction(ISD::SMUL_LOHI, (MVT::ValueType)VT, Expand);
283 setOperationAction(ISD::UDIVREM, (MVT::ValueType)VT, Expand);
284 setOperationAction(ISD::SDIVREM, (MVT::ValueType)VT, Expand);
285 setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand);
286 setOperationAction(ISD::FPOW, (MVT::ValueType)VT, Expand);
287 setOperationAction(ISD::CTPOP, (MVT::ValueType)VT, Expand);
288 setOperationAction(ISD::CTLZ, (MVT::ValueType)VT, Expand);
289 setOperationAction(ISD::CTTZ, (MVT::ValueType)VT, Expand);
292 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
293 // with merges, splats, etc.
294 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
296 setOperationAction(ISD::AND , MVT::v4i32, Legal);
297 setOperationAction(ISD::OR , MVT::v4i32, Legal);
298 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
299 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
300 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
301 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
303 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
304 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
305 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
306 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
308 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
309 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
310 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
311 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
313 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
314 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
316 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
317 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
318 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
319 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
322 setSetCCResultType(MVT::i32);
323 setShiftAmountType(MVT::i32);
324 setSetCCResultContents(ZeroOrOneSetCCResult);
326 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
327 setStackPointerRegisterToSaveRestore(PPC::X1);
328 setExceptionPointerRegister(PPC::X3);
329 setExceptionSelectorRegister(PPC::X4);
331 setStackPointerRegisterToSaveRestore(PPC::R1);
332 setExceptionPointerRegister(PPC::R3);
333 setExceptionSelectorRegister(PPC::R4);
336 // We have target-specific dag combine patterns for the following nodes:
337 setTargetDAGCombine(ISD::SINT_TO_FP);
338 setTargetDAGCombine(ISD::STORE);
339 setTargetDAGCombine(ISD::BR_CC);
340 setTargetDAGCombine(ISD::BSWAP);
342 // Darwin long double math library functions have $LDBL128 appended.
343 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) {
344 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
345 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
346 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
347 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
348 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
351 computeRegisterProperties();
354 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
357 case PPCISD::FSEL: return "PPCISD::FSEL";
358 case PPCISD::FCFID: return "PPCISD::FCFID";
359 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
360 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
361 case PPCISD::STFIWX: return "PPCISD::STFIWX";
362 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
363 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
364 case PPCISD::VPERM: return "PPCISD::VPERM";
365 case PPCISD::Hi: return "PPCISD::Hi";
366 case PPCISD::Lo: return "PPCISD::Lo";
367 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
368 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
369 case PPCISD::SRL: return "PPCISD::SRL";
370 case PPCISD::SRA: return "PPCISD::SRA";
371 case PPCISD::SHL: return "PPCISD::SHL";
372 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
373 case PPCISD::STD_32: return "PPCISD::STD_32";
374 case PPCISD::CALL_ELF: return "PPCISD::CALL_ELF";
375 case PPCISD::CALL_Macho: return "PPCISD::CALL_Macho";
376 case PPCISD::MTCTR: return "PPCISD::MTCTR";
377 case PPCISD::BCTRL_Macho: return "PPCISD::BCTRL_Macho";
378 case PPCISD::BCTRL_ELF: return "PPCISD::BCTRL_ELF";
379 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
380 case PPCISD::MFCR: return "PPCISD::MFCR";
381 case PPCISD::VCMP: return "PPCISD::VCMP";
382 case PPCISD::VCMPo: return "PPCISD::VCMPo";
383 case PPCISD::LBRX: return "PPCISD::LBRX";
384 case PPCISD::STBRX: return "PPCISD::STBRX";
385 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
386 case PPCISD::MFFS: return "PPCISD::MFFS";
387 case PPCISD::MTFSB0: return "PPCISD::MTFSB0";
388 case PPCISD::MTFSB1: return "PPCISD::MTFSB1";
389 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
390 case PPCISD::MTFSF: return "PPCISD::MTFSF";
394 //===----------------------------------------------------------------------===//
395 // Node matching predicates, for use by the tblgen matching code.
396 //===----------------------------------------------------------------------===//
398 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
399 static bool isFloatingPointZero(SDOperand Op) {
400 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
401 return CFP->getValueAPF().isZero();
402 else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
403 // Maybe this has already been legalized into the constant pool?
404 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
405 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
406 return CFP->getValueAPF().isZero();
411 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
412 /// true if Op is undef or if it matches the specified value.
413 static bool isConstantOrUndef(SDOperand Op, unsigned Val) {
414 return Op.getOpcode() == ISD::UNDEF ||
415 cast<ConstantSDNode>(Op)->getValue() == Val;
418 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
419 /// VPKUHUM instruction.
420 bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) {
422 for (unsigned i = 0; i != 16; ++i)
423 if (!isConstantOrUndef(N->getOperand(i), i*2+1))
426 for (unsigned i = 0; i != 8; ++i)
427 if (!isConstantOrUndef(N->getOperand(i), i*2+1) ||
428 !isConstantOrUndef(N->getOperand(i+8), i*2+1))
434 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
435 /// VPKUWUM instruction.
436 bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) {
438 for (unsigned i = 0; i != 16; i += 2)
439 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
440 !isConstantOrUndef(N->getOperand(i+1), i*2+3))
443 for (unsigned i = 0; i != 8; i += 2)
444 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
445 !isConstantOrUndef(N->getOperand(i+1), i*2+3) ||
446 !isConstantOrUndef(N->getOperand(i+8), i*2+2) ||
447 !isConstantOrUndef(N->getOperand(i+9), i*2+3))
453 /// isVMerge - Common function, used to match vmrg* shuffles.
455 static bool isVMerge(SDNode *N, unsigned UnitSize,
456 unsigned LHSStart, unsigned RHSStart) {
457 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
458 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
459 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
460 "Unsupported merge size!");
462 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
463 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
464 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j),
465 LHSStart+j+i*UnitSize) ||
466 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j),
467 RHSStart+j+i*UnitSize))
473 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
474 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
475 bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
477 return isVMerge(N, UnitSize, 8, 24);
478 return isVMerge(N, UnitSize, 8, 8);
481 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
482 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
483 bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
485 return isVMerge(N, UnitSize, 0, 16);
486 return isVMerge(N, UnitSize, 0, 0);
490 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
491 /// amount, otherwise return -1.
492 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
493 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
494 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
495 // Find the first non-undef value in the shuffle mask.
497 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i)
500 if (i == 16) return -1; // all undef.
502 // Otherwise, check to see if the rest of the elements are consequtively
503 // numbered from this value.
504 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue();
505 if (ShiftAmt < i) return -1;
509 // Check the rest of the elements to see if they are consequtive.
510 for (++i; i != 16; ++i)
511 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i))
514 // Check the rest of the elements to see if they are consequtive.
515 for (++i; i != 16; ++i)
516 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15))
523 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
524 /// specifies a splat of a single element that is suitable for input to
525 /// VSPLTB/VSPLTH/VSPLTW.
526 bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) {
527 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
528 N->getNumOperands() == 16 &&
529 (EltSize == 1 || EltSize == 2 || EltSize == 4));
531 // This is a splat operation if each element of the permute is the same, and
532 // if the value doesn't reference the second vector.
533 unsigned ElementBase = 0;
534 SDOperand Elt = N->getOperand(0);
535 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt))
536 ElementBase = EltV->getValue();
538 return false; // FIXME: Handle UNDEF elements too!
540 if (cast<ConstantSDNode>(Elt)->getValue() >= 16)
543 // Check that they are consequtive.
544 for (unsigned i = 1; i != EltSize; ++i) {
545 if (!isa<ConstantSDNode>(N->getOperand(i)) ||
546 cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase)
550 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
551 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
552 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
553 assert(isa<ConstantSDNode>(N->getOperand(i)) &&
554 "Invalid VECTOR_SHUFFLE mask!");
555 for (unsigned j = 0; j != EltSize; ++j)
556 if (N->getOperand(i+j) != N->getOperand(j))
563 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
565 bool PPC::isAllNegativeZeroVector(SDNode *N) {
566 assert(N->getOpcode() == ISD::BUILD_VECTOR);
567 if (PPC::isSplatShuffleMask(N, N->getNumOperands()))
568 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N))
569 return CFP->getValueAPF().isNegZero();
573 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
574 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
575 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
576 assert(isSplatShuffleMask(N, EltSize));
577 return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize;
580 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
581 /// by using a vspltis[bhw] instruction of the specified element size, return
582 /// the constant being splatted. The ByteSize field indicates the number of
583 /// bytes of each element [124] -> [bhw].
584 SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
585 SDOperand OpVal(0, 0);
587 // If ByteSize of the splat is bigger than the element size of the
588 // build_vector, then we have a case where we are checking for a splat where
589 // multiple elements of the buildvector are folded together into a single
590 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
591 unsigned EltSize = 16/N->getNumOperands();
592 if (EltSize < ByteSize) {
593 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
594 SDOperand UniquedVals[4];
595 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
597 // See if all of the elements in the buildvector agree across.
598 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
599 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
600 // If the element isn't a constant, bail fully out.
601 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand();
604 if (UniquedVals[i&(Multiple-1)].Val == 0)
605 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
606 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
607 return SDOperand(); // no match.
610 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
611 // either constant or undef values that are identical for each chunk. See
612 // if these chunks can form into a larger vspltis*.
614 // Check to see if all of the leading entries are either 0 or -1. If
615 // neither, then this won't fit into the immediate field.
616 bool LeadingZero = true;
617 bool LeadingOnes = true;
618 for (unsigned i = 0; i != Multiple-1; ++i) {
619 if (UniquedVals[i].Val == 0) continue; // Must have been undefs.
621 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
622 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
624 // Finally, check the least significant entry.
626 if (UniquedVals[Multiple-1].Val == 0)
627 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
628 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue();
630 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
633 if (UniquedVals[Multiple-1].Val == 0)
634 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
635 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended();
636 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
637 return DAG.getTargetConstant(Val, MVT::i32);
643 // Check to see if this buildvec has a single non-undef value in its elements.
644 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
645 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
647 OpVal = N->getOperand(i);
648 else if (OpVal != N->getOperand(i))
652 if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def.
654 unsigned ValSizeInBytes = 0;
656 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
657 Value = CN->getValue();
658 ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8;
659 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
660 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
661 Value = FloatToBits(CN->getValueAPF().convertToFloat());
665 // If the splat value is larger than the element value, then we can never do
666 // this splat. The only case that we could fit the replicated bits into our
667 // immediate field for would be zero, and we prefer to use vxor for it.
668 if (ValSizeInBytes < ByteSize) return SDOperand();
670 // If the element value is larger than the splat value, cut it in half and
671 // check to see if the two halves are equal. Continue doing this until we
672 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
673 while (ValSizeInBytes > ByteSize) {
674 ValSizeInBytes >>= 1;
676 // If the top half equals the bottom half, we're still ok.
677 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
678 (Value & ((1 << (8*ValSizeInBytes))-1)))
682 // Properly sign extend the value.
683 int ShAmt = (4-ByteSize)*8;
684 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
686 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
687 if (MaskVal == 0) return SDOperand();
689 // Finally, if this value fits in a 5 bit sext field, return it
690 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
691 return DAG.getTargetConstant(MaskVal, MVT::i32);
695 //===----------------------------------------------------------------------===//
696 // Addressing Mode Selection
697 //===----------------------------------------------------------------------===//
699 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
700 /// or 64-bit immediate, and if the value can be accurately represented as a
701 /// sign extension from a 16-bit value. If so, this returns true and the
703 static bool isIntS16Immediate(SDNode *N, short &Imm) {
704 if (N->getOpcode() != ISD::Constant)
707 Imm = (short)cast<ConstantSDNode>(N)->getValue();
708 if (N->getValueType(0) == MVT::i32)
709 return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue();
711 return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue();
713 static bool isIntS16Immediate(SDOperand Op, short &Imm) {
714 return isIntS16Immediate(Op.Val, Imm);
718 /// SelectAddressRegReg - Given the specified addressed, check to see if it
719 /// can be represented as an indexed [r+r] operation. Returns false if it
720 /// can be more efficiently represented with [r+imm].
721 bool PPCTargetLowering::SelectAddressRegReg(SDOperand N, SDOperand &Base,
725 if (N.getOpcode() == ISD::ADD) {
726 if (isIntS16Immediate(N.getOperand(1), imm))
728 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
731 Base = N.getOperand(0);
732 Index = N.getOperand(1);
734 } else if (N.getOpcode() == ISD::OR) {
735 if (isIntS16Immediate(N.getOperand(1), imm))
736 return false; // r+i can fold it if we can.
738 // If this is an or of disjoint bitfields, we can codegen this as an add
739 // (for better address arithmetic) if the LHS and RHS of the OR are provably
741 APInt LHSKnownZero, LHSKnownOne;
742 APInt RHSKnownZero, RHSKnownOne;
743 DAG.ComputeMaskedBits(N.getOperand(0),
744 APInt::getAllOnesValue(32),
745 LHSKnownZero, LHSKnownOne);
747 if (LHSKnownZero.getBoolValue()) {
748 DAG.ComputeMaskedBits(N.getOperand(1),
749 APInt::getAllOnesValue(32),
750 RHSKnownZero, RHSKnownOne);
751 // If all of the bits are known zero on the LHS or RHS, the add won't
753 if ((LHSKnownZero | RHSKnownZero) == ~0U) {
754 Base = N.getOperand(0);
755 Index = N.getOperand(1);
764 /// Returns true if the address N can be represented by a base register plus
765 /// a signed 16-bit displacement [r+imm], and if it is not better
766 /// represented as reg+reg.
767 bool PPCTargetLowering::SelectAddressRegImm(SDOperand N, SDOperand &Disp,
768 SDOperand &Base, SelectionDAG &DAG){
769 // If this can be more profitably realized as r+r, fail.
770 if (SelectAddressRegReg(N, Disp, Base, DAG))
773 if (N.getOpcode() == ISD::ADD) {
775 if (isIntS16Immediate(N.getOperand(1), imm)) {
776 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
777 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
778 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
780 Base = N.getOperand(0);
782 return true; // [r+i]
783 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
784 // Match LOAD (ADD (X, Lo(G))).
785 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
786 && "Cannot handle constant offsets yet!");
787 Disp = N.getOperand(1).getOperand(0); // The global address.
788 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
789 Disp.getOpcode() == ISD::TargetConstantPool ||
790 Disp.getOpcode() == ISD::TargetJumpTable);
791 Base = N.getOperand(0);
792 return true; // [&g+r]
794 } else if (N.getOpcode() == ISD::OR) {
796 if (isIntS16Immediate(N.getOperand(1), imm)) {
797 // If this is an or of disjoint bitfields, we can codegen this as an add
798 // (for better address arithmetic) if the LHS and RHS of the OR are
799 // provably disjoint.
800 APInt LHSKnownZero, LHSKnownOne;
801 DAG.ComputeMaskedBits(N.getOperand(0),
802 APInt::getAllOnesValue(32),
803 LHSKnownZero, LHSKnownOne);
804 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
805 // If all of the bits are known zero on the LHS or RHS, the add won't
807 Base = N.getOperand(0);
808 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
812 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
813 // Loading from a constant address.
815 // If this address fits entirely in a 16-bit sext immediate field, codegen
818 if (isIntS16Immediate(CN, Imm)) {
819 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
820 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
824 // Handle 32-bit sext immediates with LIS + addr mode.
825 if (CN->getValueType(0) == MVT::i32 ||
826 (int64_t)CN->getValue() == (int)CN->getValue()) {
827 int Addr = (int)CN->getValue();
829 // Otherwise, break this down into an LIS + disp.
830 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
832 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
833 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
834 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
839 Disp = DAG.getTargetConstant(0, getPointerTy());
840 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
841 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
844 return true; // [r+0]
847 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
848 /// represented as an indexed [r+r] operation.
849 bool PPCTargetLowering::SelectAddressRegRegOnly(SDOperand N, SDOperand &Base,
852 // Check to see if we can easily represent this as an [r+r] address. This
853 // will fail if it thinks that the address is more profitably represented as
854 // reg+imm, e.g. where imm = 0.
855 if (SelectAddressRegReg(N, Base, Index, DAG))
858 // If the operand is an addition, always emit this as [r+r], since this is
859 // better (for code size, and execution, as the memop does the add for free)
860 // than emitting an explicit add.
861 if (N.getOpcode() == ISD::ADD) {
862 Base = N.getOperand(0);
863 Index = N.getOperand(1);
867 // Otherwise, do it the hard way, using R0 as the base register.
868 Base = DAG.getRegister(PPC::R0, N.getValueType());
873 /// SelectAddressRegImmShift - Returns true if the address N can be
874 /// represented by a base register plus a signed 14-bit displacement
875 /// [r+imm*4]. Suitable for use by STD and friends.
876 bool PPCTargetLowering::SelectAddressRegImmShift(SDOperand N, SDOperand &Disp,
879 // If this can be more profitably realized as r+r, fail.
880 if (SelectAddressRegReg(N, Disp, Base, DAG))
883 if (N.getOpcode() == ISD::ADD) {
885 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
886 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
887 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
888 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
890 Base = N.getOperand(0);
892 return true; // [r+i]
893 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
894 // Match LOAD (ADD (X, Lo(G))).
895 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
896 && "Cannot handle constant offsets yet!");
897 Disp = N.getOperand(1).getOperand(0); // The global address.
898 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
899 Disp.getOpcode() == ISD::TargetConstantPool ||
900 Disp.getOpcode() == ISD::TargetJumpTable);
901 Base = N.getOperand(0);
902 return true; // [&g+r]
904 } else if (N.getOpcode() == ISD::OR) {
906 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
907 // If this is an or of disjoint bitfields, we can codegen this as an add
908 // (for better address arithmetic) if the LHS and RHS of the OR are
909 // provably disjoint.
910 APInt LHSKnownZero, LHSKnownOne;
911 DAG.ComputeMaskedBits(N.getOperand(0),
912 APInt::getAllOnesValue(32),
913 LHSKnownZero, LHSKnownOne);
914 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
915 // If all of the bits are known zero on the LHS or RHS, the add won't
917 Base = N.getOperand(0);
918 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
922 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
923 // Loading from a constant address. Verify low two bits are clear.
924 if ((CN->getValue() & 3) == 0) {
925 // If this address fits entirely in a 14-bit sext immediate field, codegen
928 if (isIntS16Immediate(CN, Imm)) {
929 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
930 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
934 // Fold the low-part of 32-bit absolute addresses into addr mode.
935 if (CN->getValueType(0) == MVT::i32 ||
936 (int64_t)CN->getValue() == (int)CN->getValue()) {
937 int Addr = (int)CN->getValue();
939 // Otherwise, break this down into an LIS + disp.
940 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
942 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
943 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
944 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
950 Disp = DAG.getTargetConstant(0, getPointerTy());
951 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
952 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
955 return true; // [r+0]
959 /// getPreIndexedAddressParts - returns true by value, base pointer and
960 /// offset pointer and addressing mode by reference if the node's address
961 /// can be legally represented as pre-indexed load / store address.
962 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
964 ISD::MemIndexedMode &AM,
966 // Disabled by default for now.
967 if (!EnablePPCPreinc) return false;
971 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
972 Ptr = LD->getBasePtr();
973 VT = LD->getMemoryVT();
975 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
977 Ptr = ST->getBasePtr();
978 VT = ST->getMemoryVT();
982 // PowerPC doesn't have preinc load/store instructions for vectors.
983 if (MVT::isVector(VT))
986 // TODO: Check reg+reg first.
988 // LDU/STU use reg+imm*4, others use reg+imm.
989 if (VT != MVT::i64) {
991 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
995 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
999 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1000 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1001 // sext i32 to i64 when addr mode is r+i.
1002 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1003 LD->getExtensionType() == ISD::SEXTLOAD &&
1004 isa<ConstantSDNode>(Offset))
1012 //===----------------------------------------------------------------------===//
1013 // LowerOperation implementation
1014 //===----------------------------------------------------------------------===//
1016 static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
1017 MVT::ValueType PtrVT = Op.getValueType();
1018 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1019 Constant *C = CP->getConstVal();
1020 SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
1021 SDOperand Zero = DAG.getConstant(0, PtrVT);
1023 const TargetMachine &TM = DAG.getTarget();
1025 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero);
1026 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero);
1028 // If this is a non-darwin platform, we don't support non-static relo models
1030 if (TM.getRelocationModel() == Reloc::Static ||
1031 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1032 // Generate non-pic code that has direct accesses to the constant pool.
1033 // The address of the global is just (hi(&g)+lo(&g)).
1034 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1037 if (TM.getRelocationModel() == Reloc::PIC_) {
1038 // With PIC, the first instruction is actually "GR+hi(&G)".
1039 Hi = DAG.getNode(ISD::ADD, PtrVT,
1040 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1043 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1047 static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
1048 MVT::ValueType PtrVT = Op.getValueType();
1049 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1050 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1051 SDOperand Zero = DAG.getConstant(0, PtrVT);
1053 const TargetMachine &TM = DAG.getTarget();
1055 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero);
1056 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero);
1058 // If this is a non-darwin platform, we don't support non-static relo models
1060 if (TM.getRelocationModel() == Reloc::Static ||
1061 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1062 // Generate non-pic code that has direct accesses to the constant pool.
1063 // The address of the global is just (hi(&g)+lo(&g)).
1064 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1067 if (TM.getRelocationModel() == Reloc::PIC_) {
1068 // With PIC, the first instruction is actually "GR+hi(&G)".
1069 Hi = DAG.getNode(ISD::ADD, PtrVT,
1070 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1073 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1077 static SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) {
1078 assert(0 && "TLS not implemented for PPC.");
1081 static SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
1082 MVT::ValueType PtrVT = Op.getValueType();
1083 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1084 GlobalValue *GV = GSDN->getGlobal();
1085 SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
1086 // If it's a debug information descriptor, don't mess with it.
1087 if (DAG.isVerifiedDebugInfoDesc(Op))
1089 SDOperand Zero = DAG.getConstant(0, PtrVT);
1091 const TargetMachine &TM = DAG.getTarget();
1093 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero);
1094 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero);
1096 // If this is a non-darwin platform, we don't support non-static relo models
1098 if (TM.getRelocationModel() == Reloc::Static ||
1099 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1100 // Generate non-pic code that has direct accesses to globals.
1101 // The address of the global is just (hi(&g)+lo(&g)).
1102 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1105 if (TM.getRelocationModel() == Reloc::PIC_) {
1106 // With PIC, the first instruction is actually "GR+hi(&G)".
1107 Hi = DAG.getNode(ISD::ADD, PtrVT,
1108 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1111 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1113 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV))
1116 // If the global is weak or external, we have to go through the lazy
1118 return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0);
1121 static SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
1122 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1124 // If we're comparing for equality to zero, expose the fact that this is
1125 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1126 // fold the new nodes.
1127 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1128 if (C->isNullValue() && CC == ISD::SETEQ) {
1129 MVT::ValueType VT = Op.getOperand(0).getValueType();
1130 SDOperand Zext = Op.getOperand(0);
1131 if (VT < MVT::i32) {
1133 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0));
1135 unsigned Log2b = Log2_32(MVT::getSizeInBits(VT));
1136 SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext);
1137 SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz,
1138 DAG.getConstant(Log2b, MVT::i32));
1139 return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc);
1141 // Leave comparisons against 0 and -1 alone for now, since they're usually
1142 // optimized. FIXME: revisit this when we can custom lower all setcc
1144 if (C->isAllOnesValue() || C->isNullValue())
1148 // If we have an integer seteq/setne, turn it into a compare against zero
1149 // by xor'ing the rhs with the lhs, which is faster than setting a
1150 // condition register, reading it back out, and masking the correct bit. The
1151 // normal approach here uses sub to do this instead of xor. Using xor exposes
1152 // the result to other bit-twiddling opportunities.
1153 MVT::ValueType LHSVT = Op.getOperand(0).getValueType();
1154 if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1155 MVT::ValueType VT = Op.getValueType();
1156 SDOperand Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0),
1158 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC);
1163 static SDOperand LowerVAARG(SDOperand Op, SelectionDAG &DAG,
1164 int VarArgsFrameIndex,
1165 int VarArgsStackOffset,
1166 unsigned VarArgsNumGPR,
1167 unsigned VarArgsNumFPR,
1168 const PPCSubtarget &Subtarget) {
1170 assert(0 && "VAARG in ELF32 ABI not implemented yet!");
1173 static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
1174 int VarArgsFrameIndex,
1175 int VarArgsStackOffset,
1176 unsigned VarArgsNumGPR,
1177 unsigned VarArgsNumFPR,
1178 const PPCSubtarget &Subtarget) {
1180 if (Subtarget.isMachoABI()) {
1181 // vastart just stores the address of the VarArgsFrameIndex slot into the
1182 // memory location argument.
1183 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1184 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1185 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1186 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0);
1189 // For ELF 32 ABI we follow the layout of the va_list struct.
1190 // We suppose the given va_list is already allocated.
1193 // char gpr; /* index into the array of 8 GPRs
1194 // * stored in the register save area
1195 // * gpr=0 corresponds to r3,
1196 // * gpr=1 to r4, etc.
1198 // char fpr; /* index into the array of 8 FPRs
1199 // * stored in the register save area
1200 // * fpr=0 corresponds to f1,
1201 // * fpr=1 to f2, etc.
1203 // char *overflow_arg_area;
1204 // /* location on stack that holds
1205 // * the next overflow argument
1207 // char *reg_save_area;
1208 // /* where r3:r10 and f1:f8 (if saved)
1214 SDOperand ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i8);
1215 SDOperand ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i8);
1218 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1220 SDOperand StackOffsetFI = DAG.getFrameIndex(VarArgsStackOffset, PtrVT);
1221 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1223 uint64_t FrameOffset = MVT::getSizeInBits(PtrVT)/8;
1224 SDOperand ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1226 uint64_t StackOffset = MVT::getSizeInBits(PtrVT)/8 - 1;
1227 SDOperand ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1229 uint64_t FPROffset = 1;
1230 SDOperand ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1232 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1234 // Store first byte : number of int regs
1235 SDOperand firstStore = DAG.getStore(Op.getOperand(0), ArgGPR,
1236 Op.getOperand(1), SV, 0);
1237 uint64_t nextOffset = FPROffset;
1238 SDOperand nextPtr = DAG.getNode(ISD::ADD, PtrVT, Op.getOperand(1),
1241 // Store second byte : number of float regs
1242 SDOperand secondStore =
1243 DAG.getStore(firstStore, ArgFPR, nextPtr, SV, nextOffset);
1244 nextOffset += StackOffset;
1245 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstStackOffset);
1247 // Store second word : arguments given on stack
1248 SDOperand thirdStore =
1249 DAG.getStore(secondStore, StackOffsetFI, nextPtr, SV, nextOffset);
1250 nextOffset += FrameOffset;
1251 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstFrameOffset);
1253 // Store third word : arguments given in registers
1254 return DAG.getStore(thirdStore, FR, nextPtr, SV, nextOffset);
1258 #include "PPCGenCallingConv.inc"
1260 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1261 /// depending on which subtarget is selected.
1262 static const unsigned *GetFPR(const PPCSubtarget &Subtarget) {
1263 if (Subtarget.isMachoABI()) {
1264 static const unsigned FPR[] = {
1265 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1266 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1272 static const unsigned FPR[] = {
1273 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1279 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
1280 int &VarArgsFrameIndex,
1281 int &VarArgsStackOffset,
1282 unsigned &VarArgsNumGPR,
1283 unsigned &VarArgsNumFPR,
1284 const PPCSubtarget &Subtarget) {
1285 // TODO: add description of PPC stack frame format, or at least some docs.
1287 MachineFunction &MF = DAG.getMachineFunction();
1288 MachineFrameInfo *MFI = MF.getFrameInfo();
1289 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1290 SmallVector<SDOperand, 8> ArgValues;
1291 SDOperand Root = Op.getOperand(0);
1293 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1294 bool isPPC64 = PtrVT == MVT::i64;
1295 bool isMachoABI = Subtarget.isMachoABI();
1296 bool isELF32_ABI = Subtarget.isELF32_ABI();
1297 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1299 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1301 static const unsigned GPR_32[] = { // 32-bit registers.
1302 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1303 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1305 static const unsigned GPR_64[] = { // 64-bit registers.
1306 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1307 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1310 static const unsigned *FPR = GetFPR(Subtarget);
1312 static const unsigned VR[] = {
1313 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1314 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1317 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
1318 const unsigned Num_FPR_Regs = isMachoABI ? 13 : 8;
1319 const unsigned Num_VR_Regs = array_lengthof( VR);
1321 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1323 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1325 // Add DAG nodes to load the arguments or copy them out of registers. On
1326 // entry to a function on PPC, the arguments start after the linkage area,
1327 // although the first ones are often in registers.
1329 // In the ELF 32 ABI, GPRs and stack are double word align: an argument
1330 // represented with two words (long long or double) must be copied to an
1331 // even GPR_idx value or to an even ArgOffset value.
1333 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
1335 bool needsLoad = false;
1336 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
1337 unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8;
1338 unsigned ArgSize = ObjSize;
1339 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(ArgNo+3))->getValue();
1340 unsigned AlignFlag = 1 << ISD::ParamFlags::OrigAlignmentOffs;
1341 // See if next argument requires stack alignment in ELF
1342 bool Expand = (ObjectVT == MVT::f64) || ((ArgNo + 1 < e) &&
1343 (cast<ConstantSDNode>(Op.getOperand(ArgNo+4))->getValue() & AlignFlag) &&
1344 (!(Flags & AlignFlag)));
1346 unsigned CurArgOffset = ArgOffset;
1348 default: assert(0 && "Unhandled argument type!");
1350 // Double word align in ELF
1351 if (Expand && isELF32_ABI) GPR_idx += (GPR_idx % 2);
1352 if (GPR_idx != Num_GPR_Regs) {
1353 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
1354 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1355 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32);
1359 ArgSize = PtrByteSize;
1361 // Stack align in ELF
1362 if (needsLoad && Expand && isELF32_ABI)
1363 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1364 // All int arguments reserve stack space in Macho ABI.
1365 if (isMachoABI || needsLoad) ArgOffset += PtrByteSize;
1368 case MVT::i64: // PPC64
1369 if (GPR_idx != Num_GPR_Regs) {
1370 unsigned VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
1371 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1372 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1377 // All int arguments reserve stack space in Macho ABI.
1378 if (isMachoABI || needsLoad) ArgOffset += 8;
1383 // Every 4 bytes of argument space consumes one of the GPRs available for
1384 // argument passing.
1385 if (GPR_idx != Num_GPR_Regs && isMachoABI) {
1387 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
1390 if (FPR_idx != Num_FPR_Regs) {
1392 if (ObjectVT == MVT::f32)
1393 VReg = RegInfo.createVirtualRegister(&PPC::F4RCRegClass);
1395 VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
1396 RegInfo.addLiveIn(FPR[FPR_idx], VReg);
1397 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
1403 // Stack align in ELF
1404 if (needsLoad && Expand && isELF32_ABI)
1405 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1406 // All FP arguments reserve stack space in Macho ABI.
1407 if (isMachoABI || needsLoad) ArgOffset += isPPC64 ? 8 : ObjSize;
1413 // Note that vector arguments in registers don't reserve stack space.
1414 if (VR_idx != Num_VR_Regs) {
1415 unsigned VReg = RegInfo.createVirtualRegister(&PPC::VRRCRegClass);
1416 RegInfo.addLiveIn(VR[VR_idx], VReg);
1417 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
1420 // This should be simple, but requires getting 16-byte aligned stack
1422 assert(0 && "Loading VR argument not implemented yet!");
1428 // We need to load the argument to a virtual register if we determined above
1429 // that we ran out of physical registers of the appropriate type.
1431 int FI = MFI->CreateFixedObject(ObjSize,
1432 CurArgOffset + (ArgSize - ObjSize));
1433 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
1434 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
1437 ArgValues.push_back(ArgVal);
1440 // If the function takes variable number of arguments, make a frame index for
1441 // the start of the first vararg value... for expansion of llvm.va_start.
1442 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1447 VarArgsNumGPR = GPR_idx;
1448 VarArgsNumFPR = FPR_idx;
1450 // Make room for Num_GPR_Regs, Num_FPR_Regs and for a possible frame
1452 depth = -(Num_GPR_Regs * MVT::getSizeInBits(PtrVT)/8 +
1453 Num_FPR_Regs * MVT::getSizeInBits(MVT::f64)/8 +
1454 MVT::getSizeInBits(PtrVT)/8);
1456 VarArgsStackOffset = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8,
1463 VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8,
1465 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1467 SmallVector<SDOperand, 8> MemOps;
1469 // In ELF 32 ABI, the fixed integer arguments of a variadic function are
1470 // stored to the VarArgsFrameIndex on the stack.
1472 for (GPR_idx = 0; GPR_idx != VarArgsNumGPR; ++GPR_idx) {
1473 SDOperand Val = DAG.getRegister(GPR[GPR_idx], PtrVT);
1474 SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0);
1475 MemOps.push_back(Store);
1476 // Increment the address by four for the next argument to store
1477 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT);
1478 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1482 // If this function is vararg, store any remaining integer argument regs
1483 // to their spots on the stack so that they may be loaded by deferencing the
1484 // result of va_next.
1485 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
1488 VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
1490 VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
1492 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1493 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
1494 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1495 MemOps.push_back(Store);
1496 // Increment the address by four for the next argument to store
1497 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT);
1498 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1501 // In ELF 32 ABI, the double arguments are stored to the VarArgsFrameIndex
1504 for (FPR_idx = 0; FPR_idx != VarArgsNumFPR; ++FPR_idx) {
1505 SDOperand Val = DAG.getRegister(FPR[FPR_idx], MVT::f64);
1506 SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0);
1507 MemOps.push_back(Store);
1508 // Increment the address by eight for the next argument to store
1509 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8,
1511 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1514 for (; FPR_idx != Num_FPR_Regs; ++FPR_idx) {
1516 VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
1518 RegInfo.addLiveIn(FPR[FPR_idx], VReg);
1519 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::f64);
1520 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1521 MemOps.push_back(Store);
1522 // Increment the address by eight for the next argument to store
1523 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8,
1525 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1529 if (!MemOps.empty())
1530 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size());
1533 ArgValues.push_back(Root);
1535 // Return the new list of results.
1536 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
1537 Op.Val->value_end());
1538 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
1541 /// isCallCompatibleAddress - Return the immediate to use if the specified
1542 /// 32-bit value is representable in the immediate field of a BxA instruction.
1543 static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) {
1544 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
1547 int Addr = C->getValue();
1548 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
1549 (Addr << 6 >> 6) != Addr)
1550 return 0; // Top 6 bits have to be sext of immediate.
1552 return DAG.getConstant((int)C->getValue() >> 2,
1553 DAG.getTargetLoweringInfo().getPointerTy()).Val;
1557 static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG,
1558 const PPCSubtarget &Subtarget) {
1559 SDOperand Chain = Op.getOperand(0);
1560 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1561 SDOperand Callee = Op.getOperand(4);
1562 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
1564 bool isMachoABI = Subtarget.isMachoABI();
1565 bool isELF32_ABI = Subtarget.isELF32_ABI();
1567 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1568 bool isPPC64 = PtrVT == MVT::i64;
1569 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1571 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in
1572 // SelectExpr to use to put the arguments in the appropriate registers.
1573 std::vector<SDOperand> args_to_use;
1575 // Count how many bytes are to be pushed on the stack, including the linkage
1576 // area, and parameter passing area. We start with 24/48 bytes, which is
1577 // prereserved space for [SP][CR][LR][3 x unused].
1578 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1580 // Add up all the space actually used.
1581 for (unsigned i = 0; i != NumOps; ++i) {
1582 unsigned ArgSize =MVT::getSizeInBits(Op.getOperand(5+2*i).getValueType())/8;
1583 ArgSize = std::max(ArgSize, PtrByteSize);
1584 NumBytes += ArgSize;
1587 // The prolog code of the callee may store up to 8 GPR argument registers to
1588 // the stack, allowing va_start to index over them in memory if its varargs.
1589 // Because we cannot tell if this is needed on the caller side, we have to
1590 // conservatively assume that it is needed. As such, make sure we have at
1591 // least enough stack space for the caller to store the 8 GPRs.
1592 NumBytes = std::max(NumBytes,
1593 PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI));
1595 // Adjust the stack pointer for the new arguments...
1596 // These operations are automatically eliminated by the prolog/epilog pass
1597 Chain = DAG.getCALLSEQ_START(Chain,
1598 DAG.getConstant(NumBytes, PtrVT));
1600 // Set up a copy of the stack pointer for use loading and storing any
1601 // arguments that may not fit in the registers available for argument
1605 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
1607 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
1609 // Figure out which arguments are going to go in registers, and which in
1610 // memory. Also, if this is a vararg function, floating point operations
1611 // must be stored to our stack, and loaded into integer regs as well, if
1612 // any integer regs are available for argument passing.
1613 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1614 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1616 static const unsigned GPR_32[] = { // 32-bit registers.
1617 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1618 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1620 static const unsigned GPR_64[] = { // 64-bit registers.
1621 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1622 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1624 static const unsigned *FPR = GetFPR(Subtarget);
1626 static const unsigned VR[] = {
1627 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1628 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1630 const unsigned NumGPRs = array_lengthof(GPR_32);
1631 const unsigned NumFPRs = isMachoABI ? 13 : 8;
1632 const unsigned NumVRs = array_lengthof( VR);
1634 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1636 std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
1637 SmallVector<SDOperand, 8> MemOpChains;
1638 for (unsigned i = 0; i != NumOps; ++i) {
1640 SDOperand Arg = Op.getOperand(5+2*i);
1641 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue();
1642 unsigned AlignFlag = 1 << ISD::ParamFlags::OrigAlignmentOffs;
1643 // See if next argument requires stack alignment in ELF
1644 unsigned next = 5+2*(i+1)+1;
1645 bool Expand = (Arg.getValueType() == MVT::f64) || ((i + 1 < NumOps) &&
1646 (cast<ConstantSDNode>(Op.getOperand(next))->getValue() & AlignFlag) &&
1647 (!(Flags & AlignFlag)));
1649 // PtrOff will be used to store the current argument to the stack if a
1650 // register cannot be found for it.
1653 // Stack align in ELF 32
1654 if (isELF32_ABI && Expand)
1655 PtrOff = DAG.getConstant(ArgOffset + ((ArgOffset/4) % 2) * PtrByteSize,
1656 StackPtr.getValueType());
1658 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
1660 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff);
1662 // On PPC64, promote integers to 64-bit values.
1663 if (isPPC64 && Arg.getValueType() == MVT::i32) {
1664 unsigned ExtOp = (Flags & 1) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1666 Arg = DAG.getNode(ExtOp, MVT::i64, Arg);
1669 switch (Arg.getValueType()) {
1670 default: assert(0 && "Unexpected ValueType for argument!");
1673 // Double word align in ELF
1674 if (isELF32_ABI && Expand) GPR_idx += (GPR_idx % 2);
1675 if (GPR_idx != NumGPRs) {
1676 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
1678 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1681 if (inMem || isMachoABI) {
1682 // Stack align in ELF
1683 if (isELF32_ABI && Expand)
1684 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1686 ArgOffset += PtrByteSize;
1692 // Float varargs need to be promoted to double.
1693 if (Arg.getValueType() == MVT::f32)
1694 Arg = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Arg);
1697 if (FPR_idx != NumFPRs) {
1698 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
1701 SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
1702 MemOpChains.push_back(Store);
1704 // Float varargs are always shadowed in available integer registers
1705 if (GPR_idx != NumGPRs) {
1706 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
1707 MemOpChains.push_back(Load.getValue(1));
1708 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
1711 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
1712 SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType());
1713 PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour);
1714 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
1715 MemOpChains.push_back(Load.getValue(1));
1716 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
1720 // If we have any FPRs remaining, we may also have GPRs remaining.
1721 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
1724 if (GPR_idx != NumGPRs)
1726 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
1727 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
1732 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1735 if (inMem || isMachoABI) {
1736 // Stack align in ELF
1737 if (isELF32_ABI && Expand)
1738 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1742 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
1749 assert(!isVarArg && "Don't support passing vectors to varargs yet!");
1750 assert(VR_idx != NumVRs &&
1751 "Don't support passing more than 12 vector args yet!");
1752 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
1756 if (!MemOpChains.empty())
1757 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1758 &MemOpChains[0], MemOpChains.size());
1760 // Build a sequence of copy-to-reg nodes chained together with token chain
1761 // and flag operands which copy the outgoing args into the appropriate regs.
1763 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1764 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1766 InFlag = Chain.getValue(1);
1769 // With the ELF 32 ABI, set CR6 to true if this is a vararg call.
1770 if (isVarArg && isELF32_ABI) {
1771 SDOperand SetCR(DAG.getTargetNode(PPC::SETCR, MVT::i32), 0);
1772 Chain = DAG.getCopyToReg(Chain, PPC::CR6, SetCR, InFlag);
1773 InFlag = Chain.getValue(1);
1776 std::vector<MVT::ValueType> NodeTys;
1777 NodeTys.push_back(MVT::Other); // Returns a chain
1778 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
1780 SmallVector<SDOperand, 8> Ops;
1781 unsigned CallOpc = isMachoABI? PPCISD::CALL_Macho : PPCISD::CALL_ELF;
1783 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1784 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1785 // node so that legalize doesn't hack it.
1786 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1787 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
1788 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1789 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType());
1790 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
1791 // If this is an absolute destination address, use the munged value.
1792 Callee = SDOperand(Dest, 0);
1794 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
1795 // to do the call, we can't use PPCISD::CALL.
1796 SDOperand MTCTROps[] = {Chain, Callee, InFlag};
1797 Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+(InFlag.Val!=0));
1798 InFlag = Chain.getValue(1);
1800 // Copy the callee address into R12 on darwin.
1802 Chain = DAG.getCopyToReg(Chain, PPC::R12, Callee, InFlag);
1803 InFlag = Chain.getValue(1);
1807 NodeTys.push_back(MVT::Other);
1808 NodeTys.push_back(MVT::Flag);
1809 Ops.push_back(Chain);
1810 CallOpc = isMachoABI ? PPCISD::BCTRL_Macho : PPCISD::BCTRL_ELF;
1814 // If this is a direct call, pass the chain and the callee.
1816 Ops.push_back(Chain);
1817 Ops.push_back(Callee);
1820 // Add argument registers to the end of the list so that they are known live
1822 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1823 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1824 RegsToPass[i].second.getValueType()));
1827 Ops.push_back(InFlag);
1828 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
1829 InFlag = Chain.getValue(1);
1831 Chain = DAG.getCALLSEQ_END(Chain,
1832 DAG.getConstant(NumBytes, PtrVT),
1833 DAG.getConstant(0, PtrVT),
1835 if (Op.Val->getValueType(0) != MVT::Other)
1836 InFlag = Chain.getValue(1);
1838 SDOperand ResultVals[3];
1839 unsigned NumResults = 0;
1842 // If the call has results, copy the values out of the ret val registers.
1843 switch (Op.Val->getValueType(0)) {
1844 default: assert(0 && "Unexpected ret value!");
1845 case MVT::Other: break;
1847 if (Op.Val->getValueType(1) == MVT::i32) {
1848 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1);
1849 ResultVals[0] = Chain.getValue(0);
1850 Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32,
1851 Chain.getValue(2)).getValue(1);
1852 ResultVals[1] = Chain.getValue(0);
1854 NodeTys.push_back(MVT::i32);
1856 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1);
1857 ResultVals[0] = Chain.getValue(0);
1860 NodeTys.push_back(MVT::i32);
1863 Chain = DAG.getCopyFromReg(Chain, PPC::X3, MVT::i64, InFlag).getValue(1);
1864 ResultVals[0] = Chain.getValue(0);
1866 NodeTys.push_back(MVT::i64);
1869 if (Op.Val->getValueType(1) == MVT::f64) {
1870 Chain = DAG.getCopyFromReg(Chain, PPC::F1, MVT::f64, InFlag).getValue(1);
1871 ResultVals[0] = Chain.getValue(0);
1872 Chain = DAG.getCopyFromReg(Chain, PPC::F2, MVT::f64,
1873 Chain.getValue(2)).getValue(1);
1874 ResultVals[1] = Chain.getValue(0);
1876 NodeTys.push_back(MVT::f64);
1877 NodeTys.push_back(MVT::f64);
1880 // else fall through
1882 Chain = DAG.getCopyFromReg(Chain, PPC::F1, Op.Val->getValueType(0),
1883 InFlag).getValue(1);
1884 ResultVals[0] = Chain.getValue(0);
1886 NodeTys.push_back(Op.Val->getValueType(0));
1892 Chain = DAG.getCopyFromReg(Chain, PPC::V2, Op.Val->getValueType(0),
1893 InFlag).getValue(1);
1894 ResultVals[0] = Chain.getValue(0);
1896 NodeTys.push_back(Op.Val->getValueType(0));
1900 NodeTys.push_back(MVT::Other);
1902 // If the function returns void, just return the chain.
1903 if (NumResults == 0)
1906 // Otherwise, merge everything together with a MERGE_VALUES node.
1907 ResultVals[NumResults++] = Chain;
1908 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys,
1909 ResultVals, NumResults);
1910 return Res.getValue(Op.ResNo);
1913 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG, TargetMachine &TM) {
1914 SmallVector<CCValAssign, 16> RVLocs;
1915 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
1916 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1917 CCState CCInfo(CC, isVarArg, TM, RVLocs);
1918 CCInfo.AnalyzeReturn(Op.Val, RetCC_PPC);
1920 // If this is the first return lowered for this function, add the regs to the
1921 // liveout set for the function.
1922 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1923 for (unsigned i = 0; i != RVLocs.size(); ++i)
1924 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1927 SDOperand Chain = Op.getOperand(0);
1930 // Copy the result values into the output registers.
1931 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1932 CCValAssign &VA = RVLocs[i];
1933 assert(VA.isRegLoc() && "Can only return in registers!");
1934 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
1935 Flag = Chain.getValue(1);
1939 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain, Flag);
1941 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain);
1944 static SDOperand LowerSTACKRESTORE(SDOperand Op, SelectionDAG &DAG,
1945 const PPCSubtarget &Subtarget) {
1946 // When we pop the dynamic allocation we need to restore the SP link.
1948 // Get the corect type for pointers.
1949 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1951 // Construct the stack pointer operand.
1952 bool IsPPC64 = Subtarget.isPPC64();
1953 unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1;
1954 SDOperand StackPtr = DAG.getRegister(SP, PtrVT);
1956 // Get the operands for the STACKRESTORE.
1957 SDOperand Chain = Op.getOperand(0);
1958 SDOperand SaveSP = Op.getOperand(1);
1960 // Load the old link SP.
1961 SDOperand LoadLinkSP = DAG.getLoad(PtrVT, Chain, StackPtr, NULL, 0);
1963 // Restore the stack pointer.
1964 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), SP, SaveSP);
1966 // Store the old link SP.
1967 return DAG.getStore(Chain, LoadLinkSP, StackPtr, NULL, 0);
1970 static SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG,
1971 const PPCSubtarget &Subtarget) {
1972 MachineFunction &MF = DAG.getMachineFunction();
1973 bool IsPPC64 = Subtarget.isPPC64();
1974 bool isMachoABI = Subtarget.isMachoABI();
1976 // Get current frame pointer save index. The users of this index will be
1977 // primarily DYNALLOC instructions.
1978 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1979 int FPSI = FI->getFramePointerSaveIndex();
1981 // If the frame pointer save index hasn't been defined yet.
1983 // Find out what the fix offset of the frame pointer save area.
1984 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isMachoABI);
1986 // Allocate the frame index for frame pointer save area.
1987 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
1989 FI->setFramePointerSaveIndex(FPSI);
1993 SDOperand Chain = Op.getOperand(0);
1994 SDOperand Size = Op.getOperand(1);
1996 // Get the corect type for pointers.
1997 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1999 SDOperand NegSize = DAG.getNode(ISD::SUB, PtrVT,
2000 DAG.getConstant(0, PtrVT), Size);
2001 // Construct a node for the frame pointer save index.
2002 SDOperand FPSIdx = DAG.getFrameIndex(FPSI, PtrVT);
2003 // Build a DYNALLOC node.
2004 SDOperand Ops[3] = { Chain, NegSize, FPSIdx };
2005 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
2006 return DAG.getNode(PPCISD::DYNALLOC, VTs, Ops, 3);
2010 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
2012 static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
2013 // Not FP? Not a fsel.
2014 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) ||
2015 !MVT::isFloatingPoint(Op.getOperand(2).getValueType()))
2018 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2020 // Cannot handle SETEQ/SETNE.
2021 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand();
2023 MVT::ValueType ResVT = Op.getValueType();
2024 MVT::ValueType CmpVT = Op.getOperand(0).getValueType();
2025 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2026 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3);
2028 // If the RHS of the comparison is a 0.0, we don't need to do the
2029 // subtraction at all.
2030 if (isFloatingPointZero(RHS))
2032 default: break; // SETUO etc aren't handled by fsel.
2036 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
2040 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
2041 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
2042 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
2046 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
2050 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
2051 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
2052 return DAG.getNode(PPCISD::FSEL, ResVT,
2053 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV);
2058 default: break; // SETUO etc aren't handled by fsel.
2062 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
2063 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2064 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2065 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
2069 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
2070 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2071 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2072 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
2076 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
2077 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2078 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2079 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
2083 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
2084 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2085 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2086 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
2091 // FIXME: Split this code up when LegalizeDAGTypes lands.
2092 static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
2093 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType()));
2094 SDOperand Src = Op.getOperand(0);
2095 if (Src.getValueType() == MVT::f32)
2096 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src);
2099 switch (Op.getValueType()) {
2100 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
2102 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src);
2105 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src);
2109 // Convert the FP value to an int value through memory.
2110 SDOperand FIPtr = DAG.CreateStackTemporary(MVT::f64);
2112 // Emit a store to the stack slot.
2113 SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Tmp, FIPtr, NULL, 0);
2115 // Result is a load from the stack slot. If loading 4 bytes, make sure to
2117 if (Op.getValueType() == MVT::i32)
2118 FIPtr = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr,
2119 DAG.getConstant(4, FIPtr.getValueType()));
2120 return DAG.getLoad(Op.getValueType(), Chain, FIPtr, NULL, 0);
2123 static SDOperand LowerFP_ROUND_INREG(SDOperand Op, SelectionDAG &DAG) {
2124 assert(Op.getValueType() == MVT::ppcf128);
2125 SDNode *Node = Op.Val;
2126 assert(Node->getOperand(0).getValueType() == MVT::ppcf128);
2127 assert(Node->getOperand(0).Val->getOpcode() == ISD::BUILD_PAIR);
2128 SDOperand Lo = Node->getOperand(0).Val->getOperand(0);
2129 SDOperand Hi = Node->getOperand(0).Val->getOperand(1);
2131 // This sequence changes FPSCR to do round-to-zero, adds the two halves
2132 // of the long double, and puts FPSCR back the way it was. We do not
2133 // actually model FPSCR.
2134 std::vector<MVT::ValueType> NodeTys;
2135 SDOperand Ops[4], Result, MFFSreg, InFlag, FPreg;
2137 NodeTys.push_back(MVT::f64); // Return register
2138 NodeTys.push_back(MVT::Flag); // Returns a flag for later insns
2139 Result = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0);
2140 MFFSreg = Result.getValue(0);
2141 InFlag = Result.getValue(1);
2144 NodeTys.push_back(MVT::Flag); // Returns a flag
2145 Ops[0] = DAG.getConstant(31, MVT::i32);
2147 Result = DAG.getNode(PPCISD::MTFSB1, NodeTys, Ops, 2);
2148 InFlag = Result.getValue(0);
2151 NodeTys.push_back(MVT::Flag); // Returns a flag
2152 Ops[0] = DAG.getConstant(30, MVT::i32);
2154 Result = DAG.getNode(PPCISD::MTFSB0, NodeTys, Ops, 2);
2155 InFlag = Result.getValue(0);
2158 NodeTys.push_back(MVT::f64); // result of add
2159 NodeTys.push_back(MVT::Flag); // Returns a flag
2163 Result = DAG.getNode(PPCISD::FADDRTZ, NodeTys, Ops, 3);
2164 FPreg = Result.getValue(0);
2165 InFlag = Result.getValue(1);
2168 NodeTys.push_back(MVT::f64);
2169 Ops[0] = DAG.getConstant(1, MVT::i32);
2173 Result = DAG.getNode(PPCISD::MTFSF, NodeTys, Ops, 4);
2174 FPreg = Result.getValue(0);
2176 // We know the low half is about to be thrown away, so just use something
2178 return DAG.getNode(ISD::BUILD_PAIR, Lo.getValueType(), FPreg, FPreg);
2181 static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
2182 if (Op.getOperand(0).getValueType() == MVT::i64) {
2183 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
2184 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
2185 if (Op.getValueType() == MVT::f32)
2186 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0));
2190 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
2191 "Unhandled SINT_TO_FP type in custom expander!");
2192 // Since we only generate this in 64-bit mode, we can take advantage of
2193 // 64-bit registers. In particular, sign extend the input value into the
2194 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
2195 // then lfd it and fcfid it.
2196 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
2197 int FrameIdx = FrameInfo->CreateStackObject(8, 8);
2198 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2199 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
2201 SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32,
2204 // STD the extended value into the stack slot.
2205 MemOperand MO(PseudoSourceValue::getFixedStack(),
2206 MemOperand::MOStore, FrameIdx, 8, 8);
2207 SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other,
2208 DAG.getEntryNode(), Ext64, FIdx,
2209 DAG.getMemOperand(MO));
2210 // Load the value as a double.
2211 SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0);
2213 // FCFID it and return it.
2214 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld);
2215 if (Op.getValueType() == MVT::f32)
2216 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0));
2220 static SDOperand LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG) {
2222 The rounding mode is in bits 30:31 of FPSR, and has the following
2229 FLT_ROUNDS, on the other hand, expects the following:
2236 To perform the conversion, we do:
2237 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
2240 MachineFunction &MF = DAG.getMachineFunction();
2241 MVT::ValueType VT = Op.getValueType();
2242 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2243 std::vector<MVT::ValueType> NodeTys;
2244 SDOperand MFFSreg, InFlag;
2246 // Save FP Control Word to register
2247 NodeTys.push_back(MVT::f64); // return register
2248 NodeTys.push_back(MVT::Flag); // unused in this context
2249 SDOperand Chain = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0);
2251 // Save FP register to stack slot
2252 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
2253 SDOperand StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
2254 SDOperand Store = DAG.getStore(DAG.getEntryNode(), Chain,
2255 StackSlot, NULL, 0);
2257 // Load FP Control Word from low 32 bits of stack slot.
2258 SDOperand Four = DAG.getConstant(4, PtrVT);
2259 SDOperand Addr = DAG.getNode(ISD::ADD, PtrVT, StackSlot, Four);
2260 SDOperand CWD = DAG.getLoad(MVT::i32, Store, Addr, NULL, 0);
2262 // Transform as necessary
2264 DAG.getNode(ISD::AND, MVT::i32,
2265 CWD, DAG.getConstant(3, MVT::i32));
2267 DAG.getNode(ISD::SRL, MVT::i32,
2268 DAG.getNode(ISD::AND, MVT::i32,
2269 DAG.getNode(ISD::XOR, MVT::i32,
2270 CWD, DAG.getConstant(3, MVT::i32)),
2271 DAG.getConstant(3, MVT::i32)),
2272 DAG.getConstant(1, MVT::i8));
2275 DAG.getNode(ISD::XOR, MVT::i32, CWD1, CWD2);
2277 return DAG.getNode((MVT::getSizeInBits(VT) < 16 ?
2278 ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal);
2281 static SDOperand LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) {
2282 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
2283 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
2285 // Expand into a bunch of logical ops. Note that these ops
2286 // depend on the PPC behavior for oversized shift amounts.
2287 SDOperand Lo = Op.getOperand(0);
2288 SDOperand Hi = Op.getOperand(1);
2289 SDOperand Amt = Op.getOperand(2);
2291 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
2292 DAG.getConstant(32, MVT::i32), Amt);
2293 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt);
2294 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1);
2295 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
2296 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
2297 DAG.getConstant(-32U, MVT::i32));
2298 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5);
2299 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
2300 SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt);
2301 SDOperand OutOps[] = { OutLo, OutHi };
2302 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
2306 static SDOperand LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) {
2307 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
2308 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRL!");
2310 // Otherwise, expand into a bunch of logical ops. Note that these ops
2311 // depend on the PPC behavior for oversized shift amounts.
2312 SDOperand Lo = Op.getOperand(0);
2313 SDOperand Hi = Op.getOperand(1);
2314 SDOperand Amt = Op.getOperand(2);
2316 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
2317 DAG.getConstant(32, MVT::i32), Amt);
2318 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
2319 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
2320 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
2321 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
2322 DAG.getConstant(-32U, MVT::i32));
2323 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5);
2324 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
2325 SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt);
2326 SDOperand OutOps[] = { OutLo, OutHi };
2327 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
2331 static SDOperand LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) {
2332 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
2333 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!");
2335 // Otherwise, expand into a bunch of logical ops, followed by a select_cc.
2336 SDOperand Lo = Op.getOperand(0);
2337 SDOperand Hi = Op.getOperand(1);
2338 SDOperand Amt = Op.getOperand(2);
2340 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
2341 DAG.getConstant(32, MVT::i32), Amt);
2342 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
2343 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
2344 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
2345 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
2346 DAG.getConstant(-32U, MVT::i32));
2347 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5);
2348 SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt);
2349 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32),
2350 Tmp4, Tmp6, ISD::SETLE);
2351 SDOperand OutOps[] = { OutLo, OutHi };
2352 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
2356 //===----------------------------------------------------------------------===//
2357 // Vector related lowering.
2360 // If this is a vector of constants or undefs, get the bits. A bit in
2361 // UndefBits is set if the corresponding element of the vector is an
2362 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
2363 // zero. Return true if this is not an array of constants, false if it is.
2365 static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
2366 uint64_t UndefBits[2]) {
2367 // Start with zero'd results.
2368 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0;
2370 unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType());
2371 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
2372 SDOperand OpVal = BV->getOperand(i);
2374 unsigned PartNo = i >= e/2; // In the upper 128 bits?
2375 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t.
2377 uint64_t EltBits = 0;
2378 if (OpVal.getOpcode() == ISD::UNDEF) {
2379 uint64_t EltUndefBits = ~0U >> (32-EltBitSize);
2380 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize);
2382 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
2383 EltBits = CN->getValue() & (~0U >> (32-EltBitSize));
2384 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
2385 assert(CN->getValueType(0) == MVT::f32 &&
2386 "Only one legal FP vector type!");
2387 EltBits = FloatToBits(CN->getValueAPF().convertToFloat());
2389 // Nonconstant element.
2393 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize);
2396 //printf("%llx %llx %llx %llx\n",
2397 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]);
2401 // If this is a splat (repetition) of a value across the whole vector, return
2402 // the smallest size that splats it. For example, "0x01010101010101..." is a
2403 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
2404 // SplatSize = 1 byte.
2405 static bool isConstantSplat(const uint64_t Bits128[2],
2406 const uint64_t Undef128[2],
2407 unsigned &SplatBits, unsigned &SplatUndef,
2408 unsigned &SplatSize) {
2410 // Don't let undefs prevent splats from matching. See if the top 64-bits are
2411 // the same as the lower 64-bits, ignoring undefs.
2412 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0]))
2413 return false; // Can't be a splat if two pieces don't match.
2415 uint64_t Bits64 = Bits128[0] | Bits128[1];
2416 uint64_t Undef64 = Undef128[0] & Undef128[1];
2418 // Check that the top 32-bits are the same as the lower 32-bits, ignoring
2420 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64))
2421 return false; // Can't be a splat if two pieces don't match.
2423 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32);
2424 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32);
2426 // If the top 16-bits are different than the lower 16-bits, ignoring
2427 // undefs, we have an i32 splat.
2428 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) {
2430 SplatUndef = Undef32;
2435 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16);
2436 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16);
2438 // If the top 8-bits are different than the lower 8-bits, ignoring
2439 // undefs, we have an i16 splat.
2440 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) {
2442 SplatUndef = Undef16;
2447 // Otherwise, we have an 8-bit splat.
2448 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8);
2449 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8);
2454 /// BuildSplatI - Build a canonical splati of Val with an element size of
2455 /// SplatSize. Cast the result to VT.
2456 static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT,
2457 SelectionDAG &DAG) {
2458 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
2460 static const MVT::ValueType VTys[] = { // canonical VT to use for each size.
2461 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
2464 MVT::ValueType ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
2466 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
2470 MVT::ValueType CanonicalVT = VTys[SplatSize-1];
2472 // Build a canonical splat for this value.
2473 SDOperand Elt = DAG.getConstant(Val, MVT::getVectorElementType(CanonicalVT));
2474 SmallVector<SDOperand, 8> Ops;
2475 Ops.assign(MVT::getVectorNumElements(CanonicalVT), Elt);
2476 SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT,
2477 &Ops[0], Ops.size());
2478 return DAG.getNode(ISD::BIT_CONVERT, ReqVT, Res);
2481 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
2482 /// specified intrinsic ID.
2483 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS,
2485 MVT::ValueType DestVT = MVT::Other) {
2486 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
2487 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
2488 DAG.getConstant(IID, MVT::i32), LHS, RHS);
2491 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
2492 /// specified intrinsic ID.
2493 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1,
2494 SDOperand Op2, SelectionDAG &DAG,
2495 MVT::ValueType DestVT = MVT::Other) {
2496 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
2497 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
2498 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
2502 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
2503 /// amount. The result has the specified value type.
2504 static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt,
2505 MVT::ValueType VT, SelectionDAG &DAG) {
2506 // Force LHS/RHS to be the right type.
2507 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS);
2508 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS);
2511 for (unsigned i = 0; i != 16; ++i)
2512 Ops[i] = DAG.getConstant(i+Amt, MVT::i32);
2513 SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS,
2514 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16));
2515 return DAG.getNode(ISD::BIT_CONVERT, VT, T);
2518 // If this is a case we can't handle, return null and let the default
2519 // expansion code take care of it. If we CAN select this case, and if it
2520 // selects to a single instruction, return Op. Otherwise, if we can codegen
2521 // this case more efficiently than a constant pool load, lower it to the
2522 // sequence of ops that should be used.
2523 static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2524 // If this is a vector of constants or undefs, get the bits. A bit in
2525 // UndefBits is set if the corresponding element of the vector is an
2526 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
2528 uint64_t VectorBits[2];
2529 uint64_t UndefBits[2];
2530 if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits))
2531 return SDOperand(); // Not a constant vector.
2533 // If this is a splat (repetition) of a value across the whole vector, return
2534 // the smallest size that splats it. For example, "0x01010101010101..." is a
2535 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
2536 // SplatSize = 1 byte.
2537 unsigned SplatBits, SplatUndef, SplatSize;
2538 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){
2539 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0;
2541 // First, handle single instruction cases.
2544 if (SplatBits == 0) {
2545 // Canonicalize all zero vectors to be v4i32.
2546 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
2547 SDOperand Z = DAG.getConstant(0, MVT::i32);
2548 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z);
2549 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z);
2554 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
2555 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize);
2556 if (SextVal >= -16 && SextVal <= 15)
2557 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG);
2560 // Two instruction sequences.
2562 // If this value is in the range [-32,30] and is even, use:
2563 // tmp = VSPLTI[bhw], result = add tmp, tmp
2564 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
2565 Op = BuildSplatI(SextVal >> 1, SplatSize, Op.getValueType(), DAG);
2566 return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op);
2569 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
2570 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
2572 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
2573 // Make -1 and vspltisw -1:
2574 SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG);
2576 // Make the VSLW intrinsic, computing 0x8000_0000.
2577 SDOperand Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
2580 // xor by OnesV to invert it.
2581 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV);
2582 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2585 // Check to see if this is a wide variety of vsplti*, binop self cases.
2586 unsigned SplatBitSize = SplatSize*8;
2587 static const signed char SplatCsts[] = {
2588 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
2589 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
2592 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
2593 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
2594 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
2595 int i = SplatCsts[idx];
2597 // Figure out what shift amount will be used by altivec if shifted by i in
2599 unsigned TypeShiftAmt = i & (SplatBitSize-1);
2601 // vsplti + shl self.
2602 if (SextVal == (i << (int)TypeShiftAmt)) {
2603 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2604 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2605 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
2606 Intrinsic::ppc_altivec_vslw
2608 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2609 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2612 // vsplti + srl self.
2613 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
2614 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2615 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2616 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
2617 Intrinsic::ppc_altivec_vsrw
2619 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2620 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2623 // vsplti + sra self.
2624 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
2625 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2626 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2627 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
2628 Intrinsic::ppc_altivec_vsraw
2630 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2631 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2634 // vsplti + rol self.
2635 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
2636 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
2637 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2638 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2639 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
2640 Intrinsic::ppc_altivec_vrlw
2642 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2643 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2646 // t = vsplti c, result = vsldoi t, t, 1
2647 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
2648 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2649 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG);
2651 // t = vsplti c, result = vsldoi t, t, 2
2652 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
2653 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2654 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG);
2656 // t = vsplti c, result = vsldoi t, t, 3
2657 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
2658 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2659 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG);
2663 // Three instruction sequences.
2665 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
2666 if (SextVal >= 0 && SextVal <= 31) {
2667 SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG);
2668 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
2669 LHS = DAG.getNode(ISD::SUB, LHS.getValueType(), LHS, RHS);
2670 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
2672 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
2673 if (SextVal >= -31 && SextVal <= 0) {
2674 SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG);
2675 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
2676 LHS = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS);
2677 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
2684 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
2685 /// the specified operations to build the shuffle.
2686 static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS,
2687 SDOperand RHS, SelectionDAG &DAG) {
2688 unsigned OpNum = (PFEntry >> 26) & 0x0F;
2689 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
2690 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
2693 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
2705 if (OpNum == OP_COPY) {
2706 if (LHSID == (1*9+2)*9+3) return LHS;
2707 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
2711 SDOperand OpLHS, OpRHS;
2712 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG);
2713 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG);
2715 unsigned ShufIdxs[16];
2717 default: assert(0 && "Unknown i32 permute!");
2719 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
2720 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
2721 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
2722 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
2725 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
2726 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
2727 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
2728 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
2731 for (unsigned i = 0; i != 16; ++i)
2732 ShufIdxs[i] = (i&3)+0;
2735 for (unsigned i = 0; i != 16; ++i)
2736 ShufIdxs[i] = (i&3)+4;
2739 for (unsigned i = 0; i != 16; ++i)
2740 ShufIdxs[i] = (i&3)+8;
2743 for (unsigned i = 0; i != 16; ++i)
2744 ShufIdxs[i] = (i&3)+12;
2747 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG);
2749 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG);
2751 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG);
2754 for (unsigned i = 0; i != 16; ++i)
2755 Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i32);
2757 return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS,
2758 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
2761 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
2762 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
2763 /// return the code it can be lowered into. Worst case, it can always be
2764 /// lowered into a vperm.
2765 static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
2766 SDOperand V1 = Op.getOperand(0);
2767 SDOperand V2 = Op.getOperand(1);
2768 SDOperand PermMask = Op.getOperand(2);
2770 // Cases that are handled by instructions that take permute immediates
2771 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
2772 // selected by the instruction selector.
2773 if (V2.getOpcode() == ISD::UNDEF) {
2774 if (PPC::isSplatShuffleMask(PermMask.Val, 1) ||
2775 PPC::isSplatShuffleMask(PermMask.Val, 2) ||
2776 PPC::isSplatShuffleMask(PermMask.Val, 4) ||
2777 PPC::isVPKUWUMShuffleMask(PermMask.Val, true) ||
2778 PPC::isVPKUHUMShuffleMask(PermMask.Val, true) ||
2779 PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 ||
2780 PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) ||
2781 PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) ||
2782 PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) ||
2783 PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) ||
2784 PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) ||
2785 PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) {
2790 // Altivec has a variety of "shuffle immediates" that take two vector inputs
2791 // and produce a fixed permutation. If any of these match, do not lower to
2793 if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) ||
2794 PPC::isVPKUHUMShuffleMask(PermMask.Val, false) ||
2795 PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 ||
2796 PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) ||
2797 PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) ||
2798 PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) ||
2799 PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) ||
2800 PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) ||
2801 PPC::isVMRGHShuffleMask(PermMask.Val, 4, false))
2804 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
2805 // perfect shuffle table to emit an optimal matching sequence.
2806 unsigned PFIndexes[4];
2807 bool isFourElementShuffle = true;
2808 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
2809 unsigned EltNo = 8; // Start out undef.
2810 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
2811 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF)
2812 continue; // Undef, ignore it.
2814 unsigned ByteSource =
2815 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue();
2816 if ((ByteSource & 3) != j) {
2817 isFourElementShuffle = false;
2822 EltNo = ByteSource/4;
2823 } else if (EltNo != ByteSource/4) {
2824 isFourElementShuffle = false;
2828 PFIndexes[i] = EltNo;
2831 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
2832 // perfect shuffle vector to determine if it is cost effective to do this as
2833 // discrete instructions, or whether we should use a vperm.
2834 if (isFourElementShuffle) {
2835 // Compute the index in the perfect shuffle table.
2836 unsigned PFTableIndex =
2837 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
2839 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
2840 unsigned Cost = (PFEntry >> 30);
2842 // Determining when to avoid vperm is tricky. Many things affect the cost
2843 // of vperm, particularly how many times the perm mask needs to be computed.
2844 // For example, if the perm mask can be hoisted out of a loop or is already
2845 // used (perhaps because there are multiple permutes with the same shuffle
2846 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
2847 // the loop requires an extra register.
2849 // As a compromise, we only emit discrete instructions if the shuffle can be
2850 // generated in 3 or fewer operations. When we have loop information
2851 // available, if this block is within a loop, we should avoid using vperm
2852 // for 3-operation perms and use a constant pool load instead.
2854 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG);
2857 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
2858 // vector that will get spilled to the constant pool.
2859 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
2861 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
2862 // that it is in input element units, not in bytes. Convert now.
2863 MVT::ValueType EltVT = MVT::getVectorElementType(V1.getValueType());
2864 unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8;
2866 SmallVector<SDOperand, 16> ResultMask;
2867 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
2869 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
2872 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue();
2874 for (unsigned j = 0; j != BytesPerElement; ++j)
2875 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
2879 SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8,
2880 &ResultMask[0], ResultMask.size());
2881 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
2884 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
2885 /// altivec comparison. If it is, return true and fill in Opc/isDot with
2886 /// information about the intrinsic.
2887 static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc,
2889 unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue();
2892 switch (IntrinsicID) {
2893 default: return false;
2894 // Comparison predicates.
2895 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
2896 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
2897 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
2898 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
2899 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
2900 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
2901 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
2902 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
2903 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
2904 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
2905 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
2906 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
2907 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
2909 // Normal Comparisons.
2910 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
2911 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
2912 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
2913 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
2914 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
2915 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
2916 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
2917 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
2918 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
2919 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
2920 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
2921 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
2922 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
2927 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
2928 /// lower, do it, otherwise return null.
2929 static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
2930 // If this is a lowered altivec predicate compare, CompareOpc is set to the
2931 // opcode number of the comparison.
2934 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
2935 return SDOperand(); // Don't custom lower most intrinsics.
2937 // If this is a non-dot comparison, make the VCMP node and we are done.
2939 SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(),
2940 Op.getOperand(1), Op.getOperand(2),
2941 DAG.getConstant(CompareOpc, MVT::i32));
2942 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp);
2945 // Create the PPCISD altivec 'dot' comparison node.
2947 Op.getOperand(2), // LHS
2948 Op.getOperand(3), // RHS
2949 DAG.getConstant(CompareOpc, MVT::i32)
2951 std::vector<MVT::ValueType> VTs;
2952 VTs.push_back(Op.getOperand(2).getValueType());
2953 VTs.push_back(MVT::Flag);
2954 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
2956 // Now that we have the comparison, emit a copy from the CR to a GPR.
2957 // This is flagged to the above dot comparison.
2958 SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32,
2959 DAG.getRegister(PPC::CR6, MVT::i32),
2960 CompNode.getValue(1));
2962 // Unpack the result based on how the target uses it.
2963 unsigned BitNo; // Bit # of CR6.
2964 bool InvertBit; // Invert result?
2965 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
2966 default: // Can't happen, don't crash on invalid number though.
2967 case 0: // Return the value of the EQ bit of CR6.
2968 BitNo = 0; InvertBit = false;
2970 case 1: // Return the inverted value of the EQ bit of CR6.
2971 BitNo = 0; InvertBit = true;
2973 case 2: // Return the value of the LT bit of CR6.
2974 BitNo = 2; InvertBit = false;
2976 case 3: // Return the inverted value of the LT bit of CR6.
2977 BitNo = 2; InvertBit = true;
2981 // Shift the bit into the low position.
2982 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags,
2983 DAG.getConstant(8-(3-BitNo), MVT::i32));
2985 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags,
2986 DAG.getConstant(1, MVT::i32));
2988 // If we are supposed to, toggle the bit.
2990 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags,
2991 DAG.getConstant(1, MVT::i32));
2995 static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2996 // Create a stack slot that is 16-byte aligned.
2997 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
2998 int FrameIdx = FrameInfo->CreateStackObject(16, 16);
2999 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3000 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
3002 // Store the input value into Value#0 of the stack slot.
3003 SDOperand Store = DAG.getStore(DAG.getEntryNode(),
3004 Op.getOperand(0), FIdx, NULL, 0);
3006 return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0);
3009 static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) {
3010 if (Op.getValueType() == MVT::v4i32) {
3011 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3013 SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG);
3014 SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt.
3016 SDOperand RHSSwap = // = vrlw RHS, 16
3017 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG);
3019 // Shrinkify inputs to v8i16.
3020 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS);
3021 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS);
3022 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap);
3024 // Low parts multiplied together, generating 32-bit results (we ignore the
3026 SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
3027 LHS, RHS, DAG, MVT::v4i32);
3029 SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
3030 LHS, RHSSwap, Zero, DAG, MVT::v4i32);
3031 // Shift the high parts up 16 bits.
3032 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG);
3033 return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd);
3034 } else if (Op.getValueType() == MVT::v8i16) {
3035 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3037 SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG);
3039 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
3040 LHS, RHS, Zero, DAG);
3041 } else if (Op.getValueType() == MVT::v16i8) {
3042 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3044 // Multiply the even 8-bit parts, producing 16-bit sums.
3045 SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
3046 LHS, RHS, DAG, MVT::v8i16);
3047 EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts);
3049 // Multiply the odd 8-bit parts, producing 16-bit sums.
3050 SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
3051 LHS, RHS, DAG, MVT::v8i16);
3052 OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts);
3054 // Merge the results together.
3056 for (unsigned i = 0; i != 8; ++i) {
3057 Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8);
3058 Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8);
3060 return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts,
3061 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
3063 assert(0 && "Unknown mul to lower!");
3068 /// LowerOperation - Provide custom lowering hooks for some operations.
3070 SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
3071 switch (Op.getOpcode()) {
3072 default: assert(0 && "Wasn't expecting to be able to lower this!");
3073 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3074 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
3075 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3076 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
3077 case ISD::SETCC: return LowerSETCC(Op, DAG);
3079 return LowerVASTART(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
3080 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
3083 return LowerVAARG(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
3084 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
3086 case ISD::FORMAL_ARGUMENTS:
3087 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex,
3088 VarArgsStackOffset, VarArgsNumGPR,
3089 VarArgsNumFPR, PPCSubTarget);
3091 case ISD::CALL: return LowerCALL(Op, DAG, PPCSubTarget);
3092 case ISD::RET: return LowerRET(Op, DAG, getTargetMachine());
3093 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
3094 case ISD::DYNAMIC_STACKALLOC:
3095 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
3097 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
3098 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
3099 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
3100 case ISD::FP_ROUND_INREG: return LowerFP_ROUND_INREG(Op, DAG);
3101 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
3103 // Lower 64-bit shifts.
3104 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
3105 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
3106 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
3108 // Vector-related lowering.
3109 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
3110 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
3111 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
3112 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
3113 case ISD::MUL: return LowerMUL(Op, DAG);
3115 // Frame & Return address.
3116 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
3117 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
3122 SDNode *PPCTargetLowering::ExpandOperationResult(SDNode *N, SelectionDAG &DAG) {
3123 switch (N->getOpcode()) {
3124 default: assert(0 && "Wasn't expecting to be able to lower this!");
3125 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(SDOperand(N, 0), DAG).Val;
3130 //===----------------------------------------------------------------------===//
3131 // Other Lowering Code
3132 //===----------------------------------------------------------------------===//
3135 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
3136 MachineBasicBlock *BB) {
3137 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3138 assert((MI->getOpcode() == PPC::SELECT_CC_I4 ||
3139 MI->getOpcode() == PPC::SELECT_CC_I8 ||
3140 MI->getOpcode() == PPC::SELECT_CC_F4 ||
3141 MI->getOpcode() == PPC::SELECT_CC_F8 ||
3142 MI->getOpcode() == PPC::SELECT_CC_VRRC) &&
3143 "Unexpected instr type to insert");
3145 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
3146 // control-flow pattern. The incoming instruction knows the destination vreg
3147 // to set, the condition code register to branch on, the true/false values to
3148 // select between, and a branch opcode to use.
3149 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3150 ilist<MachineBasicBlock>::iterator It = BB;
3156 // cmpTY ccX, r1, r2
3158 // fallthrough --> copy0MBB
3159 MachineBasicBlock *thisMBB = BB;
3160 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
3161 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
3162 unsigned SelectPred = MI->getOperand(4).getImm();
3163 BuildMI(BB, TII->get(PPC::BCC))
3164 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
3165 MachineFunction *F = BB->getParent();
3166 F->getBasicBlockList().insert(It, copy0MBB);
3167 F->getBasicBlockList().insert(It, sinkMBB);
3168 // Update machine-CFG edges by first adding all successors of the current
3169 // block to the new block which will contain the Phi node for the select.
3170 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
3171 e = BB->succ_end(); i != e; ++i)
3172 sinkMBB->addSuccessor(*i);
3173 // Next, remove all successors of the current block, and add the true
3174 // and fallthrough blocks as its successors.
3175 while(!BB->succ_empty())
3176 BB->removeSuccessor(BB->succ_begin());
3177 BB->addSuccessor(copy0MBB);
3178 BB->addSuccessor(sinkMBB);
3181 // %FalseValue = ...
3182 // # fallthrough to sinkMBB
3185 // Update machine-CFG edges
3186 BB->addSuccessor(sinkMBB);
3189 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
3192 BuildMI(BB, TII->get(PPC::PHI), MI->getOperand(0).getReg())
3193 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
3194 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
3196 delete MI; // The pseudo instruction is gone now.
3200 //===----------------------------------------------------------------------===//
3201 // Target Optimization Hooks
3202 //===----------------------------------------------------------------------===//
3204 SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
3205 DAGCombinerInfo &DCI) const {
3206 TargetMachine &TM = getTargetMachine();
3207 SelectionDAG &DAG = DCI.DAG;
3208 switch (N->getOpcode()) {
3211 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
3212 if (C->getValue() == 0) // 0 << V -> 0.
3213 return N->getOperand(0);
3217 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
3218 if (C->getValue() == 0) // 0 >>u V -> 0.
3219 return N->getOperand(0);
3223 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
3224 if (C->getValue() == 0 || // 0 >>s V -> 0.
3225 C->isAllOnesValue()) // -1 >>s V -> -1.
3226 return N->getOperand(0);
3230 case ISD::SINT_TO_FP:
3231 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
3232 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
3233 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
3234 // We allow the src/dst to be either f32/f64, but the intermediate
3235 // type must be i64.
3236 if (N->getOperand(0).getValueType() == MVT::i64 &&
3237 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
3238 SDOperand Val = N->getOperand(0).getOperand(0);
3239 if (Val.getValueType() == MVT::f32) {
3240 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
3241 DCI.AddToWorklist(Val.Val);
3244 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val);
3245 DCI.AddToWorklist(Val.Val);
3246 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val);
3247 DCI.AddToWorklist(Val.Val);
3248 if (N->getValueType(0) == MVT::f32) {
3249 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val,
3250 DAG.getIntPtrConstant(0));
3251 DCI.AddToWorklist(Val.Val);
3254 } else if (N->getOperand(0).getValueType() == MVT::i32) {
3255 // If the intermediate type is i32, we can avoid the load/store here
3262 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
3263 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
3264 !cast<StoreSDNode>(N)->isTruncatingStore() &&
3265 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
3266 N->getOperand(1).getValueType() == MVT::i32 &&
3267 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
3268 SDOperand Val = N->getOperand(1).getOperand(0);
3269 if (Val.getValueType() == MVT::f32) {
3270 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
3271 DCI.AddToWorklist(Val.Val);
3273 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val);
3274 DCI.AddToWorklist(Val.Val);
3276 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val,
3277 N->getOperand(2), N->getOperand(3));
3278 DCI.AddToWorklist(Val.Val);
3282 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
3283 if (N->getOperand(1).getOpcode() == ISD::BSWAP &&
3284 N->getOperand(1).Val->hasOneUse() &&
3285 (N->getOperand(1).getValueType() == MVT::i32 ||
3286 N->getOperand(1).getValueType() == MVT::i16)) {
3287 SDOperand BSwapOp = N->getOperand(1).getOperand(0);
3288 // Do an any-extend to 32-bits if this is a half-word input.
3289 if (BSwapOp.getValueType() == MVT::i16)
3290 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp);
3292 return DAG.getNode(PPCISD::STBRX, MVT::Other, N->getOperand(0), BSwapOp,
3293 N->getOperand(2), N->getOperand(3),
3294 DAG.getValueType(N->getOperand(1).getValueType()));
3298 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
3299 if (ISD::isNON_EXTLoad(N->getOperand(0).Val) &&
3300 N->getOperand(0).hasOneUse() &&
3301 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
3302 SDOperand Load = N->getOperand(0);
3303 LoadSDNode *LD = cast<LoadSDNode>(Load);
3304 // Create the byte-swapping load.
3305 std::vector<MVT::ValueType> VTs;
3306 VTs.push_back(MVT::i32);
3307 VTs.push_back(MVT::Other);
3308 SDOperand MO = DAG.getMemOperand(LD->getMemOperand());
3310 LD->getChain(), // Chain
3311 LD->getBasePtr(), // Ptr
3313 DAG.getValueType(N->getValueType(0)) // VT
3315 SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4);
3317 // If this is an i16 load, insert the truncate.
3318 SDOperand ResVal = BSLoad;
3319 if (N->getValueType(0) == MVT::i16)
3320 ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad);
3322 // First, combine the bswap away. This makes the value produced by the
3324 DCI.CombineTo(N, ResVal);
3326 // Next, combine the load away, we give it a bogus result value but a real
3327 // chain result. The result value is dead because the bswap is dead.
3328 DCI.CombineTo(Load.Val, ResVal, BSLoad.getValue(1));
3330 // Return N so it doesn't get rechecked!
3331 return SDOperand(N, 0);
3335 case PPCISD::VCMP: {
3336 // If a VCMPo node already exists with exactly the same operands as this
3337 // node, use its result instead of this node (VCMPo computes both a CR6 and
3338 // a normal output).
3340 if (!N->getOperand(0).hasOneUse() &&
3341 !N->getOperand(1).hasOneUse() &&
3342 !N->getOperand(2).hasOneUse()) {
3344 // Scan all of the users of the LHS, looking for VCMPo's that match.
3345 SDNode *VCMPoNode = 0;
3347 SDNode *LHSN = N->getOperand(0).Val;
3348 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
3350 if ((*UI)->getOpcode() == PPCISD::VCMPo &&
3351 (*UI)->getOperand(1) == N->getOperand(1) &&
3352 (*UI)->getOperand(2) == N->getOperand(2) &&
3353 (*UI)->getOperand(0) == N->getOperand(0)) {
3358 // If there is no VCMPo node, or if the flag value has a single use, don't
3360 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
3363 // Look at the (necessarily single) use of the flag value. If it has a
3364 // chain, this transformation is more complex. Note that multiple things
3365 // could use the value result, which we should ignore.
3366 SDNode *FlagUser = 0;
3367 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
3368 FlagUser == 0; ++UI) {
3369 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
3371 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
3372 if (User->getOperand(i) == SDOperand(VCMPoNode, 1)) {
3379 // If the user is a MFCR instruction, we know this is safe. Otherwise we
3380 // give up for right now.
3381 if (FlagUser->getOpcode() == PPCISD::MFCR)
3382 return SDOperand(VCMPoNode, 0);
3387 // If this is a branch on an altivec predicate comparison, lower this so
3388 // that we don't have to do a MFCR: instead, branch directly on CR6. This
3389 // lowering is done pre-legalize, because the legalizer lowers the predicate
3390 // compare down to code that is difficult to reassemble.
3391 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
3392 SDOperand LHS = N->getOperand(2), RHS = N->getOperand(3);
3396 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
3397 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
3398 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
3399 assert(isDot && "Can't compare against a vector result!");
3401 // If this is a comparison against something other than 0/1, then we know
3402 // that the condition is never/always true.
3403 unsigned Val = cast<ConstantSDNode>(RHS)->getValue();
3404 if (Val != 0 && Val != 1) {
3405 if (CC == ISD::SETEQ) // Cond never true, remove branch.
3406 return N->getOperand(0);
3407 // Always !=, turn it into an unconditional branch.
3408 return DAG.getNode(ISD::BR, MVT::Other,
3409 N->getOperand(0), N->getOperand(4));
3412 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
3414 // Create the PPCISD altivec 'dot' comparison node.
3415 std::vector<MVT::ValueType> VTs;
3417 LHS.getOperand(2), // LHS of compare
3418 LHS.getOperand(3), // RHS of compare
3419 DAG.getConstant(CompareOpc, MVT::i32)
3421 VTs.push_back(LHS.getOperand(2).getValueType());
3422 VTs.push_back(MVT::Flag);
3423 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
3425 // Unpack the result based on how the target uses it.
3426 PPC::Predicate CompOpc;
3427 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) {
3428 default: // Can't happen, don't crash on invalid number though.
3429 case 0: // Branch on the value of the EQ bit of CR6.
3430 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
3432 case 1: // Branch on the inverted value of the EQ bit of CR6.
3433 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
3435 case 2: // Branch on the value of the LT bit of CR6.
3436 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
3438 case 3: // Branch on the inverted value of the LT bit of CR6.
3439 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
3443 return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0),
3444 DAG.getConstant(CompOpc, MVT::i32),
3445 DAG.getRegister(PPC::CR6, MVT::i32),
3446 N->getOperand(4), CompNode.getValue(1));
3455 //===----------------------------------------------------------------------===//
3456 // Inline Assembly Support
3457 //===----------------------------------------------------------------------===//
3459 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
3463 const SelectionDAG &DAG,
3464 unsigned Depth) const {
3465 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
3466 switch (Op.getOpcode()) {
3468 case PPCISD::LBRX: {
3469 // lhbrx is known to have the top bits cleared out.
3470 if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16)
3471 KnownZero = 0xFFFF0000;
3474 case ISD::INTRINSIC_WO_CHAIN: {
3475 switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) {
3477 case Intrinsic::ppc_altivec_vcmpbfp_p:
3478 case Intrinsic::ppc_altivec_vcmpeqfp_p:
3479 case Intrinsic::ppc_altivec_vcmpequb_p:
3480 case Intrinsic::ppc_altivec_vcmpequh_p:
3481 case Intrinsic::ppc_altivec_vcmpequw_p:
3482 case Intrinsic::ppc_altivec_vcmpgefp_p:
3483 case Intrinsic::ppc_altivec_vcmpgtfp_p:
3484 case Intrinsic::ppc_altivec_vcmpgtsb_p:
3485 case Intrinsic::ppc_altivec_vcmpgtsh_p:
3486 case Intrinsic::ppc_altivec_vcmpgtsw_p:
3487 case Intrinsic::ppc_altivec_vcmpgtub_p:
3488 case Intrinsic::ppc_altivec_vcmpgtuh_p:
3489 case Intrinsic::ppc_altivec_vcmpgtuw_p:
3490 KnownZero = ~1U; // All bits but the low one are known to be zero.
3498 /// getConstraintType - Given a constraint, return the type of
3499 /// constraint it is for this target.
3500 PPCTargetLowering::ConstraintType
3501 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
3502 if (Constraint.size() == 1) {
3503 switch (Constraint[0]) {
3510 return C_RegisterClass;
3513 return TargetLowering::getConstraintType(Constraint);
3516 std::pair<unsigned, const TargetRegisterClass*>
3517 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
3518 MVT::ValueType VT) const {
3519 if (Constraint.size() == 1) {
3520 // GCC RS6000 Constraint Letters
3521 switch (Constraint[0]) {
3524 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
3525 return std::make_pair(0U, PPC::G8RCRegisterClass);
3526 return std::make_pair(0U, PPC::GPRCRegisterClass);
3529 return std::make_pair(0U, PPC::F4RCRegisterClass);
3530 else if (VT == MVT::f64)
3531 return std::make_pair(0U, PPC::F8RCRegisterClass);
3534 return std::make_pair(0U, PPC::VRRCRegisterClass);
3536 return std::make_pair(0U, PPC::CRRCRegisterClass);
3540 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3544 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3545 /// vector. If it is invalid, don't add anything to Ops.
3546 void PPCTargetLowering::LowerAsmOperandForConstraint(SDOperand Op, char Letter,
3547 std::vector<SDOperand>&Ops,
3548 SelectionDAG &DAG) {
3549 SDOperand Result(0,0);
3560 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
3561 if (!CST) return; // Must be an immediate to match.
3562 unsigned Value = CST->getValue();
3564 default: assert(0 && "Unknown constraint letter!");
3565 case 'I': // "I" is a signed 16-bit constant.
3566 if ((short)Value == (int)Value)
3567 Result = DAG.getTargetConstant(Value, Op.getValueType());
3569 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
3570 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
3571 if ((short)Value == 0)
3572 Result = DAG.getTargetConstant(Value, Op.getValueType());
3574 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
3575 if ((Value >> 16) == 0)
3576 Result = DAG.getTargetConstant(Value, Op.getValueType());
3578 case 'M': // "M" is a constant that is greater than 31.
3580 Result = DAG.getTargetConstant(Value, Op.getValueType());
3582 case 'N': // "N" is a positive constant that is an exact power of two.
3583 if ((int)Value > 0 && isPowerOf2_32(Value))
3584 Result = DAG.getTargetConstant(Value, Op.getValueType());
3586 case 'O': // "O" is the constant zero.
3588 Result = DAG.getTargetConstant(Value, Op.getValueType());
3590 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
3591 if ((short)-Value == (int)-Value)
3592 Result = DAG.getTargetConstant(Value, Op.getValueType());
3600 Ops.push_back(Result);
3604 // Handle standard constraint letters.
3605 TargetLowering::LowerAsmOperandForConstraint(Op, Letter, Ops, DAG);
3608 // isLegalAddressingMode - Return true if the addressing mode represented
3609 // by AM is legal for this target, for a load/store of the specified type.
3610 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
3611 const Type *Ty) const {
3612 // FIXME: PPC does not allow r+i addressing modes for vectors!
3614 // PPC allows a sign-extended 16-bit immediate field.
3615 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
3618 // No global is ever allowed as a base.
3622 // PPC only support r+r,
3624 case 0: // "r+i" or just "i", depending on HasBaseReg.
3627 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
3629 // Otherwise we have r+r or r+i.
3632 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
3634 // Allow 2*r as r+r.
3637 // No other scales are supported.
3644 /// isLegalAddressImmediate - Return true if the integer value can be used
3645 /// as the offset of the target addressing mode for load / store of the
3647 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{
3648 // PPC allows a sign-extended 16-bit immediate field.
3649 return (V > -(1 << 16) && V < (1 << 16)-1);
3652 bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
3656 SDOperand PPCTargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) {
3657 // Depths > 0 not supported yet!
3658 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
3661 MachineFunction &MF = DAG.getMachineFunction();
3662 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3663 int RAIdx = FuncInfo->getReturnAddrSaveIndex();
3665 bool isPPC64 = PPCSubTarget.isPPC64();
3667 PPCFrameInfo::getReturnSaveOffset(isPPC64, PPCSubTarget.isMachoABI());
3669 // Set up a frame object for the return address.
3670 RAIdx = MF.getFrameInfo()->CreateFixedObject(isPPC64 ? 8 : 4, Offset);
3672 // Remember it for next time.
3673 FuncInfo->setReturnAddrSaveIndex(RAIdx);
3675 // Make sure the function really does not optimize away the store of the RA
3677 FuncInfo->setLRStoreRequired();
3680 // Just load the return address off the stack.
3681 SDOperand RetAddrFI = DAG.getFrameIndex(RAIdx, getPointerTy());
3682 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
3685 SDOperand PPCTargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) {
3686 // Depths > 0 not supported yet!
3687 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
3690 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3691 bool isPPC64 = PtrVT == MVT::i64;
3693 MachineFunction &MF = DAG.getMachineFunction();
3694 MachineFrameInfo *MFI = MF.getFrameInfo();
3695 bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects())
3696 && MFI->getStackSize();
3699 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::X31 : PPC::X1,
3702 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::R31 : PPC::R1,