1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCTargetMachine.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/CodeGen/SSARegMap.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
25 PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
26 : TargetLowering(TM) {
28 // Fold away setcc operations if possible.
29 setSetCCIsExpensive();
32 // Use _setjmp/_longjmp instead of setjmp/longjmp.
33 setUseUnderscoreSetJmpLongJmp(true);
35 // Set up the register classes.
36 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
37 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
38 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
40 // PowerPC has no intrinsics for these particular operations
41 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
42 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
43 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
45 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
46 setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
47 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
49 // PowerPC has no SREM/UREM instructions
50 setOperationAction(ISD::SREM, MVT::i32, Expand);
51 setOperationAction(ISD::UREM, MVT::i32, Expand);
53 // We don't support sin/cos/sqrt/fmod
54 setOperationAction(ISD::FSIN , MVT::f64, Expand);
55 setOperationAction(ISD::FCOS , MVT::f64, Expand);
56 setOperationAction(ISD::FREM , MVT::f64, Expand);
57 setOperationAction(ISD::FSIN , MVT::f32, Expand);
58 setOperationAction(ISD::FCOS , MVT::f32, Expand);
59 setOperationAction(ISD::FREM , MVT::f32, Expand);
61 // If we're enabling GP optimizations, use hardware square root
62 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
63 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
64 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
67 // PowerPC does not have CTPOP or CTTZ
68 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
69 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
71 // PowerPC does not have Select
72 setOperationAction(ISD::SELECT, MVT::i32, Expand);
73 setOperationAction(ISD::SELECT, MVT::f32, Expand);
74 setOperationAction(ISD::SELECT, MVT::f64, Expand);
76 // PowerPC wants to turn select_cc of FP into fsel when possible.
77 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
78 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
80 // PowerPC does not have BRCOND* which requires SetCC
81 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
82 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
84 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
85 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
87 // PowerPC does not have [U|S]INT_TO_FP
88 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
89 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
91 // PowerPC does not have truncstore for i1.
92 setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
94 if (TM.getSubtarget<PPCSubtarget>().is64Bit()) {
95 // They also have instructions for converting between i64 and fp.
96 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
97 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
98 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
99 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
101 // PowerPC does not have FP_TO_UINT on 32 bit implementations.
102 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
105 if (TM.getSubtarget<PPCSubtarget>().has64BitRegs()) {
106 // 64 bit PowerPC implementations can support i64 types directly
107 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
108 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
109 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
111 // 32 bit PowerPC wants to expand i64 shifts itself.
112 setOperationAction(ISD::SHL, MVT::i64, Custom);
113 setOperationAction(ISD::SRL, MVT::i64, Custom);
114 setOperationAction(ISD::SRA, MVT::i64, Custom);
117 setSetCCResultContents(ZeroOrOneSetCCResult);
119 computeRegisterProperties();
122 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
123 static bool isFloatingPointZero(SDOperand Op) {
124 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
125 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
126 else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) {
127 // Maybe this has already been legalized into the constant pool?
128 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
129 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->get()))
130 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
135 /// LowerOperation - Provide custom lowering hooks for some operations.
137 SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
138 switch (Op.getOpcode()) {
139 default: assert(0 && "Wasn't expecting to be able to lower this!");
140 case ISD::FP_TO_SINT: {
141 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType()));
142 SDOperand Src = Op.getOperand(0);
143 if (Src.getValueType() == MVT::f32)
144 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src);
146 switch (Op.getValueType()) {
147 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
149 Op = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src);
152 Op = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src);
157 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
158 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i32);
159 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
160 Op, FI, DAG.getSrcValue(0));
161 if (Op.getOpcode() == PPCISD::FCTIDZ) {
162 Op = DAG.getLoad(MVT::i64, ST, FI, DAG.getSrcValue(0));
164 FI = DAG.getNode(ISD::ADD, MVT::i32, FI, DAG.getConstant(4, MVT::i32));
165 Op = DAG.getLoad(MVT::i32, ST, FI, DAG.getSrcValue(0));
169 case ISD::SINT_TO_FP: {
170 assert(MVT::i64 == Op.getOperand(0).getValueType() &&
171 "Unhandled SINT_TO_FP type in custom expander!");
173 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
174 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i32);
175 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
176 Op.getOperand(0), FI, DAG.getSrcValue(0));
177 SDOperand LD = DAG.getLoad(MVT::f64, ST, FI, DAG.getSrcValue(0));
178 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, LD);
179 if (MVT::f32 == Op.getValueType())
180 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
183 case ISD::SELECT_CC: {
184 // Turn FP only select_cc's into fsel instructions.
185 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) ||
186 !MVT::isFloatingPoint(Op.getOperand(2).getValueType()))
189 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
191 // Cannot handle SETEQ/SETNE.
192 if (CC == ISD::SETEQ || CC == ISD::SETNE) break;
194 MVT::ValueType ResVT = Op.getValueType();
195 MVT::ValueType CmpVT = Op.getOperand(0).getValueType();
196 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
197 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3);
199 // If the RHS of the comparison is a 0.0, we don't need to do the
200 // subtraction at all.
201 if (isFloatingPointZero(RHS))
203 default: assert(0 && "Invalid FSEL condition"); abort();
206 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
209 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
210 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
211 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
214 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
217 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
218 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
219 return DAG.getNode(PPCISD::FSEL, ResVT,
220 DAG.getNode(ISD::FNEG, ResVT, LHS), TV, FV);
225 default: assert(0 && "Invalid FSEL condition"); abort();
228 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
229 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
230 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
231 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
234 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
235 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
236 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
237 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
240 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
241 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
242 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
243 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
246 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
247 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
248 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
249 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
254 assert(Op.getValueType() == MVT::i64 &&
255 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
256 // The generic code does a fine job expanding shift by a constant.
257 if (isa<ConstantSDNode>(Op.getOperand(1))) break;
259 // Otherwise, expand into a bunch of logical ops. Note that these ops
260 // depend on the PPC behavior for oversized shift amounts.
261 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
262 DAG.getConstant(0, MVT::i32));
263 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
264 DAG.getConstant(1, MVT::i32));
265 SDOperand Amt = Op.getOperand(1);
267 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
268 DAG.getConstant(32, MVT::i32), Amt);
269 SDOperand Tmp2 = DAG.getNode(ISD::SHL, MVT::i32, Hi, Amt);
270 SDOperand Tmp3 = DAG.getNode(ISD::SRL, MVT::i32, Lo, Tmp1);
271 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
272 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
273 DAG.getConstant(-32U, MVT::i32));
274 SDOperand Tmp6 = DAG.getNode(ISD::SHL, MVT::i32, Lo, Tmp5);
275 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
276 SDOperand OutLo = DAG.getNode(ISD::SHL, MVT::i32, Lo, Amt);
277 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
280 assert(Op.getValueType() == MVT::i64 &&
281 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
282 // The generic code does a fine job expanding shift by a constant.
283 if (isa<ConstantSDNode>(Op.getOperand(1))) break;
285 // Otherwise, expand into a bunch of logical ops. Note that these ops
286 // depend on the PPC behavior for oversized shift amounts.
287 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
288 DAG.getConstant(0, MVT::i32));
289 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
290 DAG.getConstant(1, MVT::i32));
291 SDOperand Amt = Op.getOperand(1);
293 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
294 DAG.getConstant(32, MVT::i32), Amt);
295 SDOperand Tmp2 = DAG.getNode(ISD::SRL, MVT::i32, Lo, Amt);
296 SDOperand Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, Hi, Tmp1);
297 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
298 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
299 DAG.getConstant(-32U, MVT::i32));
300 SDOperand Tmp6 = DAG.getNode(ISD::SRL, MVT::i32, Hi, Tmp5);
301 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
302 SDOperand OutHi = DAG.getNode(ISD::SRL, MVT::i32, Hi, Amt);
303 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
306 assert(Op.getValueType() == MVT::i64 &&
307 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!");
308 // The generic code does a fine job expanding shift by a constant.
309 if (isa<ConstantSDNode>(Op.getOperand(1))) break;
311 // Otherwise, expand into a bunch of logical ops, followed by a select_cc.
312 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
313 DAG.getConstant(0, MVT::i32));
314 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
315 DAG.getConstant(1, MVT::i32));
316 SDOperand Amt = Op.getOperand(1);
318 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
319 DAG.getConstant(32, MVT::i32), Amt);
320 SDOperand Tmp2 = DAG.getNode(ISD::SRL, MVT::i32, Lo, Amt);
321 SDOperand Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, Hi, Tmp1);
322 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
323 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
324 DAG.getConstant(-32U, MVT::i32));
325 SDOperand Tmp6 = DAG.getNode(ISD::SRA, MVT::i32, Hi, Tmp5);
326 SDOperand OutHi = DAG.getNode(ISD::SRA, MVT::i32, Hi, Amt);
327 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32),
328 Tmp4, Tmp6, ISD::SETLE);
329 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
335 std::vector<SDOperand>
336 PPCTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
338 // add beautiful description of PPC stack frame format, or at least some docs
340 MachineFunction &MF = DAG.getMachineFunction();
341 MachineFrameInfo *MFI = MF.getFrameInfo();
342 MachineBasicBlock& BB = MF.front();
343 SSARegMap *RegMap = MF.getSSARegMap();
344 std::vector<SDOperand> ArgValues;
346 unsigned ArgOffset = 24;
347 unsigned GPR_remaining = 8;
348 unsigned FPR_remaining = 13;
349 unsigned GPR_idx = 0, FPR_idx = 0;
350 static const unsigned GPR[] = {
351 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
352 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
354 static const unsigned FPR[] = {
355 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
356 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
359 // Add DAG nodes to load the arguments... On entry to a function on PPC,
360 // the arguments start at offset 24, although they are likely to be passed
362 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
363 SDOperand newroot, argt;
365 bool needsLoad = false;
366 bool ArgLive = !I->use_empty();
367 MVT::ValueType ObjectVT = getValueType(I->getType());
370 default: assert(0 && "Unhandled argument type!");
377 if (GPR_remaining > 0) {
378 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
379 MF.addLiveIn(GPR[GPR_idx], VReg);
380 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
381 if (ObjectVT != MVT::i32) {
382 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
384 argt = DAG.getNode(AssertOp, MVT::i32, argt,
385 DAG.getValueType(ObjectVT));
386 argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, argt);
392 case MVT::i64: ObjSize = 8;
394 if (GPR_remaining > 0) {
395 SDOperand argHi, argLo;
396 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
397 MF.addLiveIn(GPR[GPR_idx], VReg);
398 argHi = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
399 // If we have two or more remaining argument registers, then both halves
400 // of the i64 can be sourced from there. Otherwise, the lower half will
401 // have to come off the stack. This can happen when an i64 is preceded
402 // by 28 bytes of arguments.
403 if (GPR_remaining > 1) {
404 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
405 MF.addLiveIn(GPR[GPR_idx+1], VReg);
406 argLo = DAG.getCopyFromReg(argHi, VReg, MVT::i32);
408 int FI = MFI->CreateFixedObject(4, ArgOffset+4);
409 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
410 argLo = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
411 DAG.getSrcValue(NULL));
413 // Build the outgoing arg thingy
414 argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi);
422 ObjSize = (ObjectVT == MVT::f64) ? 8 : 4;
424 if (FPR_remaining > 0) {
426 if (ObjectVT == MVT::f32)
427 VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass);
429 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass);
430 MF.addLiveIn(FPR[FPR_idx], VReg);
431 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, ObjectVT);
440 // We need to load the argument to a virtual register if we determined above
441 // that we ran out of physical registers of the appropriate type
443 unsigned SubregOffset = 0;
444 if (ObjectVT == MVT::i8 || ObjectVT == MVT::i1) SubregOffset = 3;
445 if (ObjectVT == MVT::i16) SubregOffset = 2;
446 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
447 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
448 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN,
449 DAG.getConstant(SubregOffset, MVT::i32));
450 argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
451 DAG.getSrcValue(NULL));
454 // Every 4 bytes of argument space consumes one of the GPRs available for
456 if (GPR_remaining > 0) {
457 unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1;
458 GPR_remaining -= delta;
461 ArgOffset += ObjSize;
463 DAG.setRoot(newroot.getValue(1));
465 ArgValues.push_back(argt);
468 // If the function takes variable number of arguments, make a frame index for
469 // the start of the first vararg value... for expansion of llvm.va_start.
471 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
472 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
473 // If this function is vararg, store any remaining integer argument regs
474 // to their spots on the stack so that they may be loaded by deferencing the
475 // result of va_next.
476 std::vector<SDOperand> MemOps;
477 for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) {
478 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
479 MF.addLiveIn(GPR[GPR_idx], VReg);
480 SDOperand Val = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
481 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
482 Val, FIN, DAG.getSrcValue(NULL));
483 MemOps.push_back(Store);
484 // Increment the address by four for the next argument to store
485 SDOperand PtrOff = DAG.getConstant(4, getPointerTy());
486 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, PtrOff);
488 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps));
491 // Finally, inform the code generator which regs we return values in.
492 switch (getValueType(F.getReturnType())) {
493 default: assert(0 && "Unknown type!");
494 case MVT::isVoid: break;
499 MF.addLiveOut(PPC::R3);
502 MF.addLiveOut(PPC::R3);
503 MF.addLiveOut(PPC::R4);
507 MF.addLiveOut(PPC::F1);
514 std::pair<SDOperand, SDOperand>
515 PPCTargetLowering::LowerCallTo(SDOperand Chain,
516 const Type *RetTy, bool isVarArg,
517 unsigned CallingConv, bool isTailCall,
518 SDOperand Callee, ArgListTy &Args,
520 // args_to_use will accumulate outgoing args for the ISD::CALL case in
521 // SelectExpr to use to put the arguments in the appropriate registers.
522 std::vector<SDOperand> args_to_use;
524 // Count how many bytes are to be pushed on the stack, including the linkage
525 // area, and parameter passing area.
526 unsigned NumBytes = 24;
529 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
530 DAG.getConstant(NumBytes, getPointerTy()));
532 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
533 switch (getValueType(Args[i].second)) {
534 default: assert(0 && "Unknown value type!");
549 // Just to be safe, we'll always reserve the full 24 bytes of linkage area
550 // plus 32 bytes of argument space in case any called code gets funky on us.
551 // (Required by ABI to support var arg)
552 if (NumBytes < 56) NumBytes = 56;
554 // Adjust the stack pointer for the new arguments...
555 // These operations are automatically eliminated by the prolog/epilog pass
556 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
557 DAG.getConstant(NumBytes, getPointerTy()));
559 // Set up a copy of the stack pointer for use loading and storing any
560 // arguments that may not fit in the registers available for argument
562 SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
565 // Figure out which arguments are going to go in registers, and which in
566 // memory. Also, if this is a vararg function, floating point operations
567 // must be stored to our stack, and loaded into integer regs as well, if
568 // any integer regs are available for argument passing.
569 unsigned ArgOffset = 24;
570 unsigned GPR_remaining = 8;
571 unsigned FPR_remaining = 13;
573 std::vector<SDOperand> MemOps;
574 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
575 // PtrOff will be used to store the current argument to the stack if a
576 // register cannot be found for it.
577 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
578 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
579 MVT::ValueType ArgVT = getValueType(Args[i].second);
582 default: assert(0 && "Unexpected ValueType for argument!");
586 // Promote the integer to 32 bits. If the input type is signed use a
587 // sign extend, otherwise use a zero extend.
588 if (Args[i].second->isSigned())
589 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
591 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
594 if (GPR_remaining > 0) {
595 args_to_use.push_back(Args[i].first);
598 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
599 Args[i].first, PtrOff,
600 DAG.getSrcValue(NULL)));
605 // If we have one free GPR left, we can place the upper half of the i64
606 // in it, and store the other half to the stack. If we have two or more
607 // free GPRs, then we can pass both halves of the i64 in registers.
608 if (GPR_remaining > 0) {
609 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
610 Args[i].first, DAG.getConstant(1, MVT::i32));
611 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
612 Args[i].first, DAG.getConstant(0, MVT::i32));
613 args_to_use.push_back(Hi);
615 if (GPR_remaining > 0) {
616 args_to_use.push_back(Lo);
619 SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
620 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
621 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
622 Lo, PtrOff, DAG.getSrcValue(NULL)));
625 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
626 Args[i].first, PtrOff,
627 DAG.getSrcValue(NULL)));
633 if (FPR_remaining > 0) {
634 args_to_use.push_back(Args[i].first);
637 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
638 Args[i].first, PtrOff,
639 DAG.getSrcValue(NULL));
640 MemOps.push_back(Store);
641 // Float varargs are always shadowed in available integer registers
642 if (GPR_remaining > 0) {
643 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
644 DAG.getSrcValue(NULL));
645 MemOps.push_back(Load);
646 args_to_use.push_back(Load);
649 if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
650 SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
651 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
652 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
653 DAG.getSrcValue(NULL));
654 MemOps.push_back(Load);
655 args_to_use.push_back(Load);
659 // If we have any FPRs remaining, we may also have GPRs remaining.
660 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
662 if (GPR_remaining > 0) {
663 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
666 if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
667 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
672 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
673 Args[i].first, PtrOff,
674 DAG.getSrcValue(NULL)));
676 ArgOffset += (ArgVT == MVT::f32) ? 4 : 8;
681 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps);
684 std::vector<MVT::ValueType> RetVals;
685 MVT::ValueType RetTyVT = getValueType(RetTy);
686 MVT::ValueType ActualRetTyVT = RetTyVT;
687 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i16)
688 ActualRetTyVT = MVT::i32; // Promote result to i32.
690 if (RetTyVT != MVT::isVoid)
691 RetVals.push_back(ActualRetTyVT);
692 RetVals.push_back(MVT::Other);
694 SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
695 Chain, Callee, args_to_use), 0);
696 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
697 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
698 DAG.getConstant(NumBytes, getPointerTy()));
699 SDOperand RetVal = TheCall;
701 // If the result is a small value, add a note so that we keep track of the
702 // information about whether it is sign or zero extended.
703 if (RetTyVT != ActualRetTyVT) {
704 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext,
705 MVT::i32, RetVal, DAG.getValueType(RetTyVT));
706 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
709 return std::make_pair(RetVal, Chain);
712 SDOperand PPCTargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op,
714 if (Op.getValueType() == MVT::i64) {
715 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
716 DAG.getConstant(1, MVT::i32));
717 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
718 DAG.getConstant(0, MVT::i32));
719 return DAG.getNode(ISD::RET, MVT::Other, Chain, Lo, Hi);
721 return DAG.getNode(ISD::RET, MVT::Other, Chain, Op);
725 SDOperand PPCTargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
726 Value *VAListV, SelectionDAG &DAG) {
727 // vastart just stores the address of the VarArgsFrameIndex slot into the
728 // memory location argument.
729 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
730 return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
731 DAG.getSrcValue(VAListV));
734 std::pair<SDOperand,SDOperand>
735 PPCTargetLowering::LowerVAArg(SDOperand Chain,
736 SDOperand VAListP, Value *VAListV,
737 const Type *ArgTy, SelectionDAG &DAG) {
738 MVT::ValueType ArgVT = getValueType(ArgTy);
741 DAG.getLoad(MVT::i32, Chain, VAListP, DAG.getSrcValue(VAListV));
742 SDOperand Result = DAG.getLoad(ArgVT, Chain, VAList, DAG.getSrcValue(NULL));
744 if (ArgVT == MVT::i32 || ArgVT == MVT::f32)
747 assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
748 "Other types should have been promoted for varargs!");
751 VAList = DAG.getNode(ISD::ADD, VAList.getValueType(), VAList,
752 DAG.getConstant(Amt, VAList.getValueType()));
753 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
754 VAList, VAListP, DAG.getSrcValue(VAListV));
755 return std::make_pair(Result, Chain);
759 std::pair<SDOperand, SDOperand> PPCTargetLowering::
760 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
762 assert(0 && "LowerFrameReturnAddress unimplemented");
767 PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
768 MachineBasicBlock *BB) {
769 assert((MI->getOpcode() == PPC::SELECT_CC_Int ||
770 MI->getOpcode() == PPC::SELECT_CC_F4 ||
771 MI->getOpcode() == PPC::SELECT_CC_F8) &&
772 "Unexpected instr type to insert");
774 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
775 // control-flow pattern. The incoming instruction knows the destination vreg
776 // to set, the condition code register to branch on, the true/false values to
777 // select between, and a branch opcode to use.
778 const BasicBlock *LLVM_BB = BB->getBasicBlock();
779 ilist<MachineBasicBlock>::iterator It = BB;
787 // fallthrough --> copy0MBB
788 MachineBasicBlock *thisMBB = BB;
789 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
790 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
791 BuildMI(BB, MI->getOperand(4).getImmedValue(), 2)
792 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
793 MachineFunction *F = BB->getParent();
794 F->getBasicBlockList().insert(It, copy0MBB);
795 F->getBasicBlockList().insert(It, sinkMBB);
796 // Update machine-CFG edges
797 BB->addSuccessor(copy0MBB);
798 BB->addSuccessor(sinkMBB);
802 // # fallthrough to sinkMBB
805 // Update machine-CFG edges
806 BB->addSuccessor(sinkMBB);
809 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
812 BuildMI(BB, PPC::PHI, 4, MI->getOperand(0).getReg())
813 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
814 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
816 delete MI; // The pseudo instruction is gone now.