1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCMachineFunctionInfo.h"
16 #include "PPCPredicates.h"
17 #include "PPCTargetMachine.h"
18 #include "PPCPerfectShuffle.h"
19 #include "llvm/ADT/VectorExtras.h"
20 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/CodeGen/SSARegMap.h"
27 #include "llvm/Constants.h"
28 #include "llvm/Function.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/Support/MathExtras.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Support/CommandLine.h"
35 static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc");
37 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
38 : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) {
42 // Use _setjmp/_longjmp instead of setjmp/longjmp.
43 setUseUnderscoreSetJmp(true);
44 setUseUnderscoreLongJmp(true);
46 // Set up the register classes.
47 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
48 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
49 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
51 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
52 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand);
53 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand);
55 // PowerPC does not have truncstore for i1.
56 setStoreXAction(MVT::i1, Promote);
58 // PowerPC has pre-inc load and store's.
59 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
60 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
61 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
62 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
63 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
64 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
65 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
66 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
67 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
68 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
70 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
71 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
73 // PowerPC has no intrinsics for these particular operations
74 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
75 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
76 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
78 // PowerPC has no SREM/UREM instructions
79 setOperationAction(ISD::SREM, MVT::i32, Expand);
80 setOperationAction(ISD::UREM, MVT::i32, Expand);
81 setOperationAction(ISD::SREM, MVT::i64, Expand);
82 setOperationAction(ISD::UREM, MVT::i64, Expand);
84 // We don't support sin/cos/sqrt/fmod
85 setOperationAction(ISD::FSIN , MVT::f64, Expand);
86 setOperationAction(ISD::FCOS , MVT::f64, Expand);
87 setOperationAction(ISD::FREM , MVT::f64, Expand);
88 setOperationAction(ISD::FSIN , MVT::f32, Expand);
89 setOperationAction(ISD::FCOS , MVT::f32, Expand);
90 setOperationAction(ISD::FREM , MVT::f32, Expand);
92 // If we're enabling GP optimizations, use hardware square root
93 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
94 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
95 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
98 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
99 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
101 // PowerPC does not have BSWAP, CTPOP or CTTZ
102 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
103 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
104 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
105 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
106 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
107 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
109 // PowerPC does not have ROTR
110 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
112 // PowerPC does not have Select
113 setOperationAction(ISD::SELECT, MVT::i32, Expand);
114 setOperationAction(ISD::SELECT, MVT::i64, Expand);
115 setOperationAction(ISD::SELECT, MVT::f32, Expand);
116 setOperationAction(ISD::SELECT, MVT::f64, Expand);
118 // PowerPC wants to turn select_cc of FP into fsel when possible.
119 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
120 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
122 // PowerPC wants to optimize integer setcc a bit
123 setOperationAction(ISD::SETCC, MVT::i32, Custom);
125 // PowerPC does not have BRCOND which requires SetCC
126 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
128 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
130 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
131 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
133 // PowerPC does not have [U|S]INT_TO_FP
134 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
135 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
137 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
138 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
139 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
140 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
142 // We cannot sextinreg(i1). Expand to shifts.
143 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
145 // Support label based line numbers.
146 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
147 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
148 if (!TM.getSubtarget<PPCSubtarget>().isDarwin()) {
149 setOperationAction(ISD::LABEL, MVT::Other, Expand);
151 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
152 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
153 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
154 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
157 // We want to legalize GlobalAddress and ConstantPool nodes into the
158 // appropriate instructions to materialize the address.
159 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
160 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
161 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
162 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
163 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
164 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
166 // RET must be custom lowered, to meet ABI requirements
167 setOperationAction(ISD::RET , MVT::Other, Custom);
169 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
170 setOperationAction(ISD::VASTART , MVT::Other, Custom);
172 // Use the default implementation.
173 setOperationAction(ISD::VAARG , MVT::Other, Expand);
174 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
175 setOperationAction(ISD::VAEND , MVT::Other, Expand);
176 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
177 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
178 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
179 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
181 // We want to custom lower some of our intrinsics.
182 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
184 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
185 // They also have instructions for converting between i64 and fp.
186 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
187 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
188 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
189 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
190 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
192 // FIXME: disable this lowered code. This generates 64-bit register values,
193 // and we don't model the fact that the top part is clobbered by calls. We
194 // need to flag these together so that the value isn't live across a call.
195 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
197 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
198 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
200 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
201 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
204 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
205 // 64 bit PowerPC implementations can support i64 types directly
206 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
207 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
208 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
210 // 32 bit PowerPC wants to expand i64 shifts itself.
211 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
212 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
213 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
216 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
217 // First set operation action for all vector types to expand. Then we
218 // will selectively turn on ones that can be effectively codegen'd.
219 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
220 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
221 // add/sub are legal for all supported vector VT's.
222 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal);
223 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal);
225 // We promote all shuffles to v16i8.
226 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote);
227 AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8);
229 // We promote all non-typed operations to v4i32.
230 setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote);
231 AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32);
232 setOperationAction(ISD::OR , (MVT::ValueType)VT, Promote);
233 AddPromotedToType (ISD::OR , (MVT::ValueType)VT, MVT::v4i32);
234 setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote);
235 AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32);
236 setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote);
237 AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32);
238 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
239 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32);
240 setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote);
241 AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32);
243 // No other operations are legal.
244 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
245 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
246 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
247 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
248 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
249 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
250 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
251 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
252 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
254 setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand);
257 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
258 // with merges, splats, etc.
259 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
261 setOperationAction(ISD::AND , MVT::v4i32, Legal);
262 setOperationAction(ISD::OR , MVT::v4i32, Legal);
263 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
264 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
265 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
266 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
268 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
269 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
270 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
271 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
273 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
274 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
275 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
276 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
278 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
279 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
281 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
282 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
283 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
284 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
287 setSetCCResultType(MVT::i32);
288 setShiftAmountType(MVT::i32);
289 setSetCCResultContents(ZeroOrOneSetCCResult);
291 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
292 setStackPointerRegisterToSaveRestore(PPC::X1);
293 setExceptionPointerRegister(PPC::X3);
294 setExceptionSelectorRegister(PPC::X4);
296 setStackPointerRegisterToSaveRestore(PPC::R1);
297 setExceptionPointerRegister(PPC::R3);
298 setExceptionSelectorRegister(PPC::R4);
301 // We have target-specific dag combine patterns for the following nodes:
302 setTargetDAGCombine(ISD::SINT_TO_FP);
303 setTargetDAGCombine(ISD::STORE);
304 setTargetDAGCombine(ISD::BR_CC);
305 setTargetDAGCombine(ISD::BSWAP);
307 computeRegisterProperties();
310 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
313 case PPCISD::FSEL: return "PPCISD::FSEL";
314 case PPCISD::FCFID: return "PPCISD::FCFID";
315 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
316 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
317 case PPCISD::STFIWX: return "PPCISD::STFIWX";
318 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
319 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
320 case PPCISD::VPERM: return "PPCISD::VPERM";
321 case PPCISD::Hi: return "PPCISD::Hi";
322 case PPCISD::Lo: return "PPCISD::Lo";
323 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
324 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
325 case PPCISD::SRL: return "PPCISD::SRL";
326 case PPCISD::SRA: return "PPCISD::SRA";
327 case PPCISD::SHL: return "PPCISD::SHL";
328 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
329 case PPCISD::STD_32: return "PPCISD::STD_32";
330 case PPCISD::CALL_ELF: return "PPCISD::CALL_ELF";
331 case PPCISD::CALL_Macho: return "PPCISD::CALL_Macho";
332 case PPCISD::MTCTR: return "PPCISD::MTCTR";
333 case PPCISD::BCTRL_Macho: return "PPCISD::BCTRL_Macho";
334 case PPCISD::BCTRL_ELF: return "PPCISD::BCTRL_ELF";
335 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
336 case PPCISD::MFCR: return "PPCISD::MFCR";
337 case PPCISD::VCMP: return "PPCISD::VCMP";
338 case PPCISD::VCMPo: return "PPCISD::VCMPo";
339 case PPCISD::LBRX: return "PPCISD::LBRX";
340 case PPCISD::STBRX: return "PPCISD::STBRX";
341 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
345 //===----------------------------------------------------------------------===//
346 // Node matching predicates, for use by the tblgen matching code.
347 //===----------------------------------------------------------------------===//
349 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
350 static bool isFloatingPointZero(SDOperand Op) {
351 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
352 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
353 else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
354 // Maybe this has already been legalized into the constant pool?
355 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
356 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
357 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
362 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
363 /// true if Op is undef or if it matches the specified value.
364 static bool isConstantOrUndef(SDOperand Op, unsigned Val) {
365 return Op.getOpcode() == ISD::UNDEF ||
366 cast<ConstantSDNode>(Op)->getValue() == Val;
369 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
370 /// VPKUHUM instruction.
371 bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) {
373 for (unsigned i = 0; i != 16; ++i)
374 if (!isConstantOrUndef(N->getOperand(i), i*2+1))
377 for (unsigned i = 0; i != 8; ++i)
378 if (!isConstantOrUndef(N->getOperand(i), i*2+1) ||
379 !isConstantOrUndef(N->getOperand(i+8), i*2+1))
385 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
386 /// VPKUWUM instruction.
387 bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) {
389 for (unsigned i = 0; i != 16; i += 2)
390 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
391 !isConstantOrUndef(N->getOperand(i+1), i*2+3))
394 for (unsigned i = 0; i != 8; i += 2)
395 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
396 !isConstantOrUndef(N->getOperand(i+1), i*2+3) ||
397 !isConstantOrUndef(N->getOperand(i+8), i*2+2) ||
398 !isConstantOrUndef(N->getOperand(i+9), i*2+3))
404 /// isVMerge - Common function, used to match vmrg* shuffles.
406 static bool isVMerge(SDNode *N, unsigned UnitSize,
407 unsigned LHSStart, unsigned RHSStart) {
408 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
409 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
410 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
411 "Unsupported merge size!");
413 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
414 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
415 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j),
416 LHSStart+j+i*UnitSize) ||
417 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j),
418 RHSStart+j+i*UnitSize))
424 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
425 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
426 bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
428 return isVMerge(N, UnitSize, 8, 24);
429 return isVMerge(N, UnitSize, 8, 8);
432 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
433 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
434 bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
436 return isVMerge(N, UnitSize, 0, 16);
437 return isVMerge(N, UnitSize, 0, 0);
441 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
442 /// amount, otherwise return -1.
443 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
444 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
445 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
446 // Find the first non-undef value in the shuffle mask.
448 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i)
451 if (i == 16) return -1; // all undef.
453 // Otherwise, check to see if the rest of the elements are consequtively
454 // numbered from this value.
455 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue();
456 if (ShiftAmt < i) return -1;
460 // Check the rest of the elements to see if they are consequtive.
461 for (++i; i != 16; ++i)
462 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i))
465 // Check the rest of the elements to see if they are consequtive.
466 for (++i; i != 16; ++i)
467 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15))
474 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
475 /// specifies a splat of a single element that is suitable for input to
476 /// VSPLTB/VSPLTH/VSPLTW.
477 bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) {
478 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
479 N->getNumOperands() == 16 &&
480 (EltSize == 1 || EltSize == 2 || EltSize == 4));
482 // This is a splat operation if each element of the permute is the same, and
483 // if the value doesn't reference the second vector.
484 unsigned ElementBase = 0;
485 SDOperand Elt = N->getOperand(0);
486 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt))
487 ElementBase = EltV->getValue();
489 return false; // FIXME: Handle UNDEF elements too!
491 if (cast<ConstantSDNode>(Elt)->getValue() >= 16)
494 // Check that they are consequtive.
495 for (unsigned i = 1; i != EltSize; ++i) {
496 if (!isa<ConstantSDNode>(N->getOperand(i)) ||
497 cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase)
501 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
502 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
503 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
504 assert(isa<ConstantSDNode>(N->getOperand(i)) &&
505 "Invalid VECTOR_SHUFFLE mask!");
506 for (unsigned j = 0; j != EltSize; ++j)
507 if (N->getOperand(i+j) != N->getOperand(j))
514 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
515 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
516 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
517 assert(isSplatShuffleMask(N, EltSize));
518 return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize;
521 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
522 /// by using a vspltis[bhw] instruction of the specified element size, return
523 /// the constant being splatted. The ByteSize field indicates the number of
524 /// bytes of each element [124] -> [bhw].
525 SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
526 SDOperand OpVal(0, 0);
528 // If ByteSize of the splat is bigger than the element size of the
529 // build_vector, then we have a case where we are checking for a splat where
530 // multiple elements of the buildvector are folded together into a single
531 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
532 unsigned EltSize = 16/N->getNumOperands();
533 if (EltSize < ByteSize) {
534 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
535 SDOperand UniquedVals[4];
536 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
538 // See if all of the elements in the buildvector agree across.
539 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
540 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
541 // If the element isn't a constant, bail fully out.
542 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand();
545 if (UniquedVals[i&(Multiple-1)].Val == 0)
546 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
547 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
548 return SDOperand(); // no match.
551 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
552 // either constant or undef values that are identical for each chunk. See
553 // if these chunks can form into a larger vspltis*.
555 // Check to see if all of the leading entries are either 0 or -1. If
556 // neither, then this won't fit into the immediate field.
557 bool LeadingZero = true;
558 bool LeadingOnes = true;
559 for (unsigned i = 0; i != Multiple-1; ++i) {
560 if (UniquedVals[i].Val == 0) continue; // Must have been undefs.
562 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
563 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
565 // Finally, check the least significant entry.
567 if (UniquedVals[Multiple-1].Val == 0)
568 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
569 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue();
571 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
574 if (UniquedVals[Multiple-1].Val == 0)
575 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
576 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended();
577 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
578 return DAG.getTargetConstant(Val, MVT::i32);
584 // Check to see if this buildvec has a single non-undef value in its elements.
585 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
586 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
588 OpVal = N->getOperand(i);
589 else if (OpVal != N->getOperand(i))
593 if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def.
595 unsigned ValSizeInBytes = 0;
597 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
598 Value = CN->getValue();
599 ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8;
600 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
601 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
602 Value = FloatToBits(CN->getValue());
606 // If the splat value is larger than the element value, then we can never do
607 // this splat. The only case that we could fit the replicated bits into our
608 // immediate field for would be zero, and we prefer to use vxor for it.
609 if (ValSizeInBytes < ByteSize) return SDOperand();
611 // If the element value is larger than the splat value, cut it in half and
612 // check to see if the two halves are equal. Continue doing this until we
613 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
614 while (ValSizeInBytes > ByteSize) {
615 ValSizeInBytes >>= 1;
617 // If the top half equals the bottom half, we're still ok.
618 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
619 (Value & ((1 << (8*ValSizeInBytes))-1)))
623 // Properly sign extend the value.
624 int ShAmt = (4-ByteSize)*8;
625 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
627 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
628 if (MaskVal == 0) return SDOperand();
630 // Finally, if this value fits in a 5 bit sext field, return it
631 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
632 return DAG.getTargetConstant(MaskVal, MVT::i32);
636 //===----------------------------------------------------------------------===//
637 // Addressing Mode Selection
638 //===----------------------------------------------------------------------===//
640 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
641 /// or 64-bit immediate, and if the value can be accurately represented as a
642 /// sign extension from a 16-bit value. If so, this returns true and the
644 static bool isIntS16Immediate(SDNode *N, short &Imm) {
645 if (N->getOpcode() != ISD::Constant)
648 Imm = (short)cast<ConstantSDNode>(N)->getValue();
649 if (N->getValueType(0) == MVT::i32)
650 return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue();
652 return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue();
654 static bool isIntS16Immediate(SDOperand Op, short &Imm) {
655 return isIntS16Immediate(Op.Val, Imm);
659 /// SelectAddressRegReg - Given the specified addressed, check to see if it
660 /// can be represented as an indexed [r+r] operation. Returns false if it
661 /// can be more efficiently represented with [r+imm].
662 bool PPCTargetLowering::SelectAddressRegReg(SDOperand N, SDOperand &Base,
666 if (N.getOpcode() == ISD::ADD) {
667 if (isIntS16Immediate(N.getOperand(1), imm))
669 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
672 Base = N.getOperand(0);
673 Index = N.getOperand(1);
675 } else if (N.getOpcode() == ISD::OR) {
676 if (isIntS16Immediate(N.getOperand(1), imm))
677 return false; // r+i can fold it if we can.
679 // If this is an or of disjoint bitfields, we can codegen this as an add
680 // (for better address arithmetic) if the LHS and RHS of the OR are provably
682 uint64_t LHSKnownZero, LHSKnownOne;
683 uint64_t RHSKnownZero, RHSKnownOne;
684 ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne);
687 ComputeMaskedBits(N.getOperand(1), ~0U, RHSKnownZero, RHSKnownOne);
688 // If all of the bits are known zero on the LHS or RHS, the add won't
690 if ((LHSKnownZero | RHSKnownZero) == ~0U) {
691 Base = N.getOperand(0);
692 Index = N.getOperand(1);
701 /// Returns true if the address N can be represented by a base register plus
702 /// a signed 16-bit displacement [r+imm], and if it is not better
703 /// represented as reg+reg.
704 bool PPCTargetLowering::SelectAddressRegImm(SDOperand N, SDOperand &Disp,
705 SDOperand &Base, SelectionDAG &DAG){
706 // If this can be more profitably realized as r+r, fail.
707 if (SelectAddressRegReg(N, Disp, Base, DAG))
710 if (N.getOpcode() == ISD::ADD) {
712 if (isIntS16Immediate(N.getOperand(1), imm)) {
713 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
714 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
715 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
717 Base = N.getOperand(0);
719 return true; // [r+i]
720 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
721 // Match LOAD (ADD (X, Lo(G))).
722 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
723 && "Cannot handle constant offsets yet!");
724 Disp = N.getOperand(1).getOperand(0); // The global address.
725 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
726 Disp.getOpcode() == ISD::TargetConstantPool ||
727 Disp.getOpcode() == ISD::TargetJumpTable);
728 Base = N.getOperand(0);
729 return true; // [&g+r]
731 } else if (N.getOpcode() == ISD::OR) {
733 if (isIntS16Immediate(N.getOperand(1), imm)) {
734 // If this is an or of disjoint bitfields, we can codegen this as an add
735 // (for better address arithmetic) if the LHS and RHS of the OR are
736 // provably disjoint.
737 uint64_t LHSKnownZero, LHSKnownOne;
738 ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne);
739 if ((LHSKnownZero|~(unsigned)imm) == ~0U) {
740 // If all of the bits are known zero on the LHS or RHS, the add won't
742 Base = N.getOperand(0);
743 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
747 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
748 // Loading from a constant address.
750 // If this address fits entirely in a 16-bit sext immediate field, codegen
753 if (isIntS16Immediate(CN, Imm)) {
754 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
755 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
759 // Handle 32-bit sext immediates with LIS + addr mode.
760 if (CN->getValueType(0) == MVT::i32 ||
761 (int64_t)CN->getValue() == (int)CN->getValue()) {
762 int Addr = (int)CN->getValue();
764 // Otherwise, break this down into an LIS + disp.
765 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
767 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
768 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
769 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
774 Disp = DAG.getTargetConstant(0, getPointerTy());
775 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
776 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
779 return true; // [r+0]
782 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
783 /// represented as an indexed [r+r] operation.
784 bool PPCTargetLowering::SelectAddressRegRegOnly(SDOperand N, SDOperand &Base,
787 // Check to see if we can easily represent this as an [r+r] address. This
788 // will fail if it thinks that the address is more profitably represented as
789 // reg+imm, e.g. where imm = 0.
790 if (SelectAddressRegReg(N, Base, Index, DAG))
793 // If the operand is an addition, always emit this as [r+r], since this is
794 // better (for code size, and execution, as the memop does the add for free)
795 // than emitting an explicit add.
796 if (N.getOpcode() == ISD::ADD) {
797 Base = N.getOperand(0);
798 Index = N.getOperand(1);
802 // Otherwise, do it the hard way, using R0 as the base register.
803 Base = DAG.getRegister(PPC::R0, N.getValueType());
808 /// SelectAddressRegImmShift - Returns true if the address N can be
809 /// represented by a base register plus a signed 14-bit displacement
810 /// [r+imm*4]. Suitable for use by STD and friends.
811 bool PPCTargetLowering::SelectAddressRegImmShift(SDOperand N, SDOperand &Disp,
814 // If this can be more profitably realized as r+r, fail.
815 if (SelectAddressRegReg(N, Disp, Base, DAG))
818 if (N.getOpcode() == ISD::ADD) {
820 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
821 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
822 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
823 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
825 Base = N.getOperand(0);
827 return true; // [r+i]
828 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
829 // Match LOAD (ADD (X, Lo(G))).
830 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
831 && "Cannot handle constant offsets yet!");
832 Disp = N.getOperand(1).getOperand(0); // The global address.
833 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
834 Disp.getOpcode() == ISD::TargetConstantPool ||
835 Disp.getOpcode() == ISD::TargetJumpTable);
836 Base = N.getOperand(0);
837 return true; // [&g+r]
839 } else if (N.getOpcode() == ISD::OR) {
841 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
842 // If this is an or of disjoint bitfields, we can codegen this as an add
843 // (for better address arithmetic) if the LHS and RHS of the OR are
844 // provably disjoint.
845 uint64_t LHSKnownZero, LHSKnownOne;
846 ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne);
847 if ((LHSKnownZero|~(unsigned)imm) == ~0U) {
848 // If all of the bits are known zero on the LHS or RHS, the add won't
850 Base = N.getOperand(0);
851 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
855 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
856 // Loading from a constant address. Verify low two bits are clear.
857 if ((CN->getValue() & 3) == 0) {
858 // If this address fits entirely in a 14-bit sext immediate field, codegen
861 if (isIntS16Immediate(CN, Imm)) {
862 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
863 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
867 // Fold the low-part of 32-bit absolute addresses into addr mode.
868 if (CN->getValueType(0) == MVT::i32 ||
869 (int64_t)CN->getValue() == (int)CN->getValue()) {
870 int Addr = (int)CN->getValue();
872 // Otherwise, break this down into an LIS + disp.
873 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
875 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
876 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
877 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
883 Disp = DAG.getTargetConstant(0, getPointerTy());
884 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
885 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
888 return true; // [r+0]
892 /// getPreIndexedAddressParts - returns true by value, base pointer and
893 /// offset pointer and addressing mode by reference if the node's address
894 /// can be legally represented as pre-indexed load / store address.
895 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
897 ISD::MemIndexedMode &AM,
899 // Disabled by default for now.
900 if (!EnablePPCPreinc) return false;
904 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
905 Ptr = LD->getBasePtr();
906 VT = LD->getLoadedVT();
908 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
910 Ptr = ST->getBasePtr();
911 VT = ST->getStoredVT();
915 // PowerPC doesn't have preinc load/store instructions for vectors.
916 if (MVT::isVector(VT))
919 // TODO: Check reg+reg first.
921 // LDU/STU use reg+imm*4, others use reg+imm.
922 if (VT != MVT::i64) {
924 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
928 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
932 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
933 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
934 // sext i32 to i64 when addr mode is r+i.
935 if (LD->getValueType(0) == MVT::i64 && LD->getLoadedVT() == MVT::i32 &&
936 LD->getExtensionType() == ISD::SEXTLOAD &&
937 isa<ConstantSDNode>(Offset))
945 //===----------------------------------------------------------------------===//
946 // LowerOperation implementation
947 //===----------------------------------------------------------------------===//
949 static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
950 MVT::ValueType PtrVT = Op.getValueType();
951 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
952 Constant *C = CP->getConstVal();
953 SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
954 SDOperand Zero = DAG.getConstant(0, PtrVT);
956 const TargetMachine &TM = DAG.getTarget();
958 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero);
959 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero);
961 // If this is a non-darwin platform, we don't support non-static relo models
963 if (TM.getRelocationModel() == Reloc::Static ||
964 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
965 // Generate non-pic code that has direct accesses to the constant pool.
966 // The address of the global is just (hi(&g)+lo(&g)).
967 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
970 if (TM.getRelocationModel() == Reloc::PIC_) {
971 // With PIC, the first instruction is actually "GR+hi(&G)".
972 Hi = DAG.getNode(ISD::ADD, PtrVT,
973 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
976 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
980 static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
981 MVT::ValueType PtrVT = Op.getValueType();
982 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
983 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
984 SDOperand Zero = DAG.getConstant(0, PtrVT);
986 const TargetMachine &TM = DAG.getTarget();
988 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero);
989 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero);
991 // If this is a non-darwin platform, we don't support non-static relo models
993 if (TM.getRelocationModel() == Reloc::Static ||
994 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
995 // Generate non-pic code that has direct accesses to the constant pool.
996 // The address of the global is just (hi(&g)+lo(&g)).
997 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1000 if (TM.getRelocationModel() == Reloc::PIC_) {
1001 // With PIC, the first instruction is actually "GR+hi(&G)".
1002 Hi = DAG.getNode(ISD::ADD, PtrVT,
1003 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1006 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1010 static SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
1011 MVT::ValueType PtrVT = Op.getValueType();
1012 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1013 GlobalValue *GV = GSDN->getGlobal();
1014 SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
1015 SDOperand Zero = DAG.getConstant(0, PtrVT);
1017 const TargetMachine &TM = DAG.getTarget();
1019 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero);
1020 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero);
1022 // If this is a non-darwin platform, we don't support non-static relo models
1024 if (TM.getRelocationModel() == Reloc::Static ||
1025 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1026 // Generate non-pic code that has direct accesses to globals.
1027 // The address of the global is just (hi(&g)+lo(&g)).
1028 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1031 if (TM.getRelocationModel() == Reloc::PIC_) {
1032 // With PIC, the first instruction is actually "GR+hi(&G)".
1033 Hi = DAG.getNode(ISD::ADD, PtrVT,
1034 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1037 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1039 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV))
1042 // If the global is weak or external, we have to go through the lazy
1044 return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0);
1047 static SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
1048 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1050 // If we're comparing for equality to zero, expose the fact that this is
1051 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1052 // fold the new nodes.
1053 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1054 if (C->isNullValue() && CC == ISD::SETEQ) {
1055 MVT::ValueType VT = Op.getOperand(0).getValueType();
1056 SDOperand Zext = Op.getOperand(0);
1057 if (VT < MVT::i32) {
1059 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0));
1061 unsigned Log2b = Log2_32(MVT::getSizeInBits(VT));
1062 SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext);
1063 SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz,
1064 DAG.getConstant(Log2b, MVT::i32));
1065 return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc);
1067 // Leave comparisons against 0 and -1 alone for now, since they're usually
1068 // optimized. FIXME: revisit this when we can custom lower all setcc
1070 if (C->isAllOnesValue() || C->isNullValue())
1074 // If we have an integer seteq/setne, turn it into a compare against zero
1075 // by xor'ing the rhs with the lhs, which is faster than setting a
1076 // condition register, reading it back out, and masking the correct bit. The
1077 // normal approach here uses sub to do this instead of xor. Using xor exposes
1078 // the result to other bit-twiddling opportunities.
1079 MVT::ValueType LHSVT = Op.getOperand(0).getValueType();
1080 if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1081 MVT::ValueType VT = Op.getValueType();
1082 SDOperand Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0),
1084 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC);
1089 static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
1090 unsigned VarArgsFrameIndex) {
1091 // vastart just stores the address of the VarArgsFrameIndex slot into the
1092 // memory location argument.
1093 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1094 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1095 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
1096 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(),
1100 #include "PPCGenCallingConv.inc"
1102 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1103 /// depending on which subtarget is selected.
1104 static const unsigned *GetFPR(const PPCSubtarget &Subtarget) {
1105 if (Subtarget.isMachoABI()) {
1106 static const unsigned FPR[] = {
1107 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1108 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1114 static const unsigned FPR[] = {
1115 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1116 PPC::F8, PPC::F9, PPC::F10
1121 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
1122 int &VarArgsFrameIndex,
1123 const PPCSubtarget &Subtarget) {
1124 // TODO: add description of PPC stack frame format, or at least some docs.
1126 MachineFunction &MF = DAG.getMachineFunction();
1127 MachineFrameInfo *MFI = MF.getFrameInfo();
1128 SSARegMap *RegMap = MF.getSSARegMap();
1129 SmallVector<SDOperand, 8> ArgValues;
1130 SDOperand Root = Op.getOperand(0);
1132 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1133 bool isPPC64 = PtrVT == MVT::i64;
1134 bool isMachoABI = Subtarget.isMachoABI();
1135 bool isELF_ABI = Subtarget.isELF_ABI();
1136 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1138 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1140 static const unsigned GPR_32[] = { // 32-bit registers.
1141 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1142 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1144 static const unsigned GPR_64[] = { // 64-bit registers.
1145 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1146 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1149 static const unsigned *FPR = GetFPR(Subtarget);
1151 static const unsigned VR[] = {
1152 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1153 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1156 const unsigned Num_GPR_Regs = sizeof(GPR_32)/sizeof(GPR_32[0]);
1157 const unsigned Num_FPR_Regs = isMachoABI ? 13 : 10;
1158 const unsigned Num_VR_Regs = sizeof( VR)/sizeof( VR[0]);
1160 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1162 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1164 // Add DAG nodes to load the arguments or copy them out of registers. On
1165 // entry to a function on PPC, the arguments start after the linkage area,
1166 // although the first ones are often in registers.
1168 // In the ELF ABI, GPRs and stack are double word align: an argument
1169 // represented with two words (long long or double) must be copied to an
1170 // even GPR_idx value or to an even ArgOffset value.
1172 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
1174 bool needsLoad = false;
1175 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
1176 unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8;
1177 unsigned ArgSize = ObjSize;
1178 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(ArgNo+3))->getValue();
1179 unsigned AlignFlag = 1 << ISD::ParamFlags::OrigAlignmentOffs;
1180 // See if next argument requires stack alignment in ELF
1181 bool Expand = (ObjectVT == MVT::f64) || ((ArgNo + 1 < e) &&
1182 (cast<ConstantSDNode>(Op.getOperand(ArgNo+4))->getValue() & AlignFlag) &&
1183 (!(Flags & AlignFlag)));
1185 unsigned CurArgOffset = ArgOffset;
1187 default: assert(0 && "Unhandled argument type!");
1189 // Double word align in ELF
1190 if (Expand && isELF_ABI && !isPPC64) GPR_idx += (GPR_idx % 2);
1191 if (GPR_idx != Num_GPR_Regs) {
1192 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
1193 MF.addLiveIn(GPR[GPR_idx], VReg);
1194 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32);
1198 ArgSize = PtrByteSize;
1200 // Stack align in ELF
1201 if (needsLoad && Expand && isELF_ABI && !isPPC64)
1202 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1203 // All int arguments reserve stack space in Macho ABI.
1204 if (isMachoABI || needsLoad) ArgOffset += PtrByteSize;
1207 case MVT::i64: // PPC64
1208 if (GPR_idx != Num_GPR_Regs) {
1209 unsigned VReg = RegMap->createVirtualRegister(&PPC::G8RCRegClass);
1210 MF.addLiveIn(GPR[GPR_idx], VReg);
1211 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1216 // All int arguments reserve stack space in Macho ABI.
1217 if (isMachoABI || needsLoad) ArgOffset += 8;
1222 // Every 4 bytes of argument space consumes one of the GPRs available for
1223 // argument passing.
1224 if (GPR_idx != Num_GPR_Regs && isMachoABI) {
1226 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
1229 if (FPR_idx != Num_FPR_Regs) {
1231 if (ObjectVT == MVT::f32)
1232 VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass);
1234 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass);
1235 MF.addLiveIn(FPR[FPR_idx], VReg);
1236 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
1242 // Stack align in ELF
1243 if (needsLoad && Expand && isELF_ABI && !isPPC64)
1244 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1245 // All FP arguments reserve stack space in Macho ABI.
1246 if (isMachoABI || needsLoad) ArgOffset += isPPC64 ? 8 : ObjSize;
1252 // Note that vector arguments in registers don't reserve stack space.
1253 if (VR_idx != Num_VR_Regs) {
1254 unsigned VReg = RegMap->createVirtualRegister(&PPC::VRRCRegClass);
1255 MF.addLiveIn(VR[VR_idx], VReg);
1256 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
1259 // This should be simple, but requires getting 16-byte aligned stack
1261 assert(0 && "Loading VR argument not implemented yet!");
1267 // We need to load the argument to a virtual register if we determined above
1268 // that we ran out of physical registers of the appropriate type
1270 // If the argument is actually used, emit a load from the right stack
1272 if (!Op.Val->hasNUsesOfValue(0, ArgNo)) {
1273 int FI = MFI->CreateFixedObject(ObjSize,
1274 CurArgOffset + (ArgSize - ObjSize));
1275 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
1276 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
1278 // Don't emit a dead load.
1279 ArgVal = DAG.getNode(ISD::UNDEF, ObjectVT);
1283 ArgValues.push_back(ArgVal);
1286 // If the function takes variable number of arguments, make a frame index for
1287 // the start of the first vararg value... for expansion of llvm.va_start.
1288 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1290 VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8,
1292 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1293 // If this function is vararg, store any remaining integer argument regs
1294 // to their spots on the stack so that they may be loaded by deferencing the
1295 // result of va_next.
1296 SmallVector<SDOperand, 8> MemOps;
1297 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
1300 VReg = RegMap->createVirtualRegister(&PPC::G8RCRegClass);
1302 VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
1304 MF.addLiveIn(GPR[GPR_idx], VReg);
1305 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
1306 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1307 MemOps.push_back(Store);
1308 // Increment the address by four for the next argument to store
1309 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT);
1310 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1312 if (!MemOps.empty())
1313 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size());
1316 ArgValues.push_back(Root);
1318 // Return the new list of results.
1319 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
1320 Op.Val->value_end());
1321 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
1324 /// isCallCompatibleAddress - Return the immediate to use if the specified
1325 /// 32-bit value is representable in the immediate field of a BxA instruction.
1326 static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) {
1327 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
1330 int Addr = C->getValue();
1331 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
1332 (Addr << 6 >> 6) != Addr)
1333 return 0; // Top 6 bits have to be sext of immediate.
1335 return DAG.getConstant((int)C->getValue() >> 2, MVT::i32).Val;
1339 static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG,
1340 const PPCSubtarget &Subtarget) {
1341 SDOperand Chain = Op.getOperand(0);
1342 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1343 SDOperand Callee = Op.getOperand(4);
1344 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
1346 bool isMachoABI = Subtarget.isMachoABI();
1347 bool isELF_ABI = Subtarget.isELF_ABI();
1349 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1350 bool isPPC64 = PtrVT == MVT::i64;
1351 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1353 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in
1354 // SelectExpr to use to put the arguments in the appropriate registers.
1355 std::vector<SDOperand> args_to_use;
1357 // Count how many bytes are to be pushed on the stack, including the linkage
1358 // area, and parameter passing area. We start with 24/48 bytes, which is
1359 // prereserved space for [SP][CR][LR][3 x unused].
1360 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1362 // Add up all the space actually used.
1363 for (unsigned i = 0; i != NumOps; ++i) {
1364 unsigned ArgSize =MVT::getSizeInBits(Op.getOperand(5+2*i).getValueType())/8;
1365 ArgSize = std::max(ArgSize, PtrByteSize);
1366 NumBytes += ArgSize;
1369 // The prolog code of the callee may store up to 8 GPR argument registers to
1370 // the stack, allowing va_start to index over them in memory if its varargs.
1371 // Because we cannot tell if this is needed on the caller side, we have to
1372 // conservatively assume that it is needed. As such, make sure we have at
1373 // least enough stack space for the caller to store the 8 GPRs.
1374 NumBytes = std::max(NumBytes,
1375 PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI));
1377 // Adjust the stack pointer for the new arguments...
1378 // These operations are automatically eliminated by the prolog/epilog pass
1379 Chain = DAG.getCALLSEQ_START(Chain,
1380 DAG.getConstant(NumBytes, PtrVT));
1382 // Set up a copy of the stack pointer for use loading and storing any
1383 // arguments that may not fit in the registers available for argument
1387 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
1389 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
1391 // Figure out which arguments are going to go in registers, and which in
1392 // memory. Also, if this is a vararg function, floating point operations
1393 // must be stored to our stack, and loaded into integer regs as well, if
1394 // any integer regs are available for argument passing.
1395 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1396 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1398 static const unsigned GPR_32[] = { // 32-bit registers.
1399 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1400 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1402 static const unsigned GPR_64[] = { // 64-bit registers.
1403 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1404 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1406 static const unsigned *FPR = GetFPR(Subtarget);
1408 static const unsigned VR[] = {
1409 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1410 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1412 const unsigned NumGPRs = sizeof(GPR_32)/sizeof(GPR_32[0]);
1413 const unsigned NumFPRs = isMachoABI ? 13 : 10;
1414 const unsigned NumVRs = sizeof( VR)/sizeof( VR[0]);
1416 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1418 std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
1419 SmallVector<SDOperand, 8> MemOpChains;
1420 for (unsigned i = 0; i != NumOps; ++i) {
1422 SDOperand Arg = Op.getOperand(5+2*i);
1423 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue();
1424 unsigned AlignFlag = 1 << ISD::ParamFlags::OrigAlignmentOffs;
1425 // See if next argument requires stack alignment in ELF
1426 unsigned next = 5+2*(i+1)+1;
1427 bool Expand = (Arg.getValueType() == MVT::f64) || ((i + 1 < NumOps) &&
1428 (cast<ConstantSDNode>(Op.getOperand(next))->getValue() & AlignFlag) &&
1429 (!(Flags & AlignFlag)));
1431 // PtrOff will be used to store the current argument to the stack if a
1432 // register cannot be found for it.
1435 // Stack align in ELF
1436 if (isELF_ABI && Expand && !isPPC64)
1437 PtrOff = DAG.getConstant(ArgOffset + ((ArgOffset/4) % 2) * PtrByteSize,
1438 StackPtr.getValueType());
1440 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
1442 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff);
1444 // On PPC64, promote integers to 64-bit values.
1445 if (isPPC64 && Arg.getValueType() == MVT::i32) {
1446 unsigned ExtOp = (Flags & 1) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1448 Arg = DAG.getNode(ExtOp, MVT::i64, Arg);
1451 switch (Arg.getValueType()) {
1452 default: assert(0 && "Unexpected ValueType for argument!");
1455 // Double word align in ELF
1456 if (isELF_ABI && Expand && !isPPC64) GPR_idx += (GPR_idx % 2);
1457 if (GPR_idx != NumGPRs) {
1458 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
1460 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1463 if (inMem || isMachoABI) {
1464 // Stack align in ELF
1465 if (isELF_ABI && Expand && !isPPC64)
1466 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1468 ArgOffset += PtrByteSize;
1474 // Float varargs need to be promoted to double.
1475 if (Arg.getValueType() == MVT::f32)
1476 Arg = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Arg);
1479 if (FPR_idx != NumFPRs) {
1480 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
1483 SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
1484 MemOpChains.push_back(Store);
1486 // Float varargs are always shadowed in available integer registers
1487 if (GPR_idx != NumGPRs) {
1488 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
1489 MemOpChains.push_back(Load.getValue(1));
1490 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
1493 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
1494 SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType());
1495 PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour);
1496 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
1497 MemOpChains.push_back(Load.getValue(1));
1498 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
1502 // If we have any FPRs remaining, we may also have GPRs remaining.
1503 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
1506 if (GPR_idx != NumGPRs)
1508 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
1509 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
1514 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1517 if (inMem || isMachoABI) {
1518 // Stack align in ELF
1519 if (isELF_ABI && Expand && !isPPC64)
1520 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1524 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
1531 assert(!isVarArg && "Don't support passing vectors to varargs yet!");
1532 assert(VR_idx != NumVRs &&
1533 "Don't support passing more than 12 vector args yet!");
1534 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
1538 if (!MemOpChains.empty())
1539 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1540 &MemOpChains[0], MemOpChains.size());
1542 // Build a sequence of copy-to-reg nodes chained together with token chain
1543 // and flag operands which copy the outgoing args into the appropriate regs.
1545 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1546 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1548 InFlag = Chain.getValue(1);
1551 // With the ELF ABI, set CR6 to true if this is a vararg call.
1552 if (isVarArg && isELF_ABI) {
1553 SDOperand SetCR(DAG.getTargetNode(PPC::SETCR, MVT::i32), 0);
1554 Chain = DAG.getCopyToReg(Chain, PPC::CR6, SetCR, InFlag);
1555 InFlag = Chain.getValue(1);
1558 std::vector<MVT::ValueType> NodeTys;
1559 NodeTys.push_back(MVT::Other); // Returns a chain
1560 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
1562 SmallVector<SDOperand, 8> Ops;
1563 unsigned CallOpc = isMachoABI? PPCISD::CALL_Macho : PPCISD::CALL_ELF;
1565 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1566 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1567 // node so that legalize doesn't hack it.
1568 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1569 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
1570 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1571 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType());
1572 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
1573 // If this is an absolute destination address, use the munged value.
1574 Callee = SDOperand(Dest, 0);
1576 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
1577 // to do the call, we can't use PPCISD::CALL.
1578 SDOperand MTCTROps[] = {Chain, Callee, InFlag};
1579 Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+(InFlag.Val!=0));
1580 InFlag = Chain.getValue(1);
1582 // Copy the callee address into R12 on darwin.
1584 Chain = DAG.getCopyToReg(Chain, PPC::R12, Callee, InFlag);
1585 InFlag = Chain.getValue(1);
1589 NodeTys.push_back(MVT::Other);
1590 NodeTys.push_back(MVT::Flag);
1591 Ops.push_back(Chain);
1592 CallOpc = isMachoABI ? PPCISD::BCTRL_Macho : PPCISD::BCTRL_ELF;
1596 // If this is a direct call, pass the chain and the callee.
1598 Ops.push_back(Chain);
1599 Ops.push_back(Callee);
1602 // Add argument registers to the end of the list so that they are known live
1604 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1605 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1606 RegsToPass[i].second.getValueType()));
1609 Ops.push_back(InFlag);
1610 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
1611 InFlag = Chain.getValue(1);
1613 SDOperand ResultVals[3];
1614 unsigned NumResults = 0;
1617 // If the call has results, copy the values out of the ret val registers.
1618 switch (Op.Val->getValueType(0)) {
1619 default: assert(0 && "Unexpected ret value!");
1620 case MVT::Other: break;
1622 if (Op.Val->getValueType(1) == MVT::i32) {
1623 Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32, InFlag).getValue(1);
1624 ResultVals[0] = Chain.getValue(0);
1625 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32,
1626 Chain.getValue(2)).getValue(1);
1627 ResultVals[1] = Chain.getValue(0);
1629 NodeTys.push_back(MVT::i32);
1631 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1);
1632 ResultVals[0] = Chain.getValue(0);
1635 NodeTys.push_back(MVT::i32);
1638 Chain = DAG.getCopyFromReg(Chain, PPC::X3, MVT::i64, InFlag).getValue(1);
1639 ResultVals[0] = Chain.getValue(0);
1641 NodeTys.push_back(MVT::i64);
1645 Chain = DAG.getCopyFromReg(Chain, PPC::F1, Op.Val->getValueType(0),
1646 InFlag).getValue(1);
1647 ResultVals[0] = Chain.getValue(0);
1649 NodeTys.push_back(Op.Val->getValueType(0));
1655 Chain = DAG.getCopyFromReg(Chain, PPC::V2, Op.Val->getValueType(0),
1656 InFlag).getValue(1);
1657 ResultVals[0] = Chain.getValue(0);
1659 NodeTys.push_back(Op.Val->getValueType(0));
1663 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
1664 DAG.getConstant(NumBytes, PtrVT));
1665 NodeTys.push_back(MVT::Other);
1667 // If the function returns void, just return the chain.
1668 if (NumResults == 0)
1671 // Otherwise, merge everything together with a MERGE_VALUES node.
1672 ResultVals[NumResults++] = Chain;
1673 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys,
1674 ResultVals, NumResults);
1675 return Res.getValue(Op.ResNo);
1678 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG, TargetMachine &TM) {
1679 SmallVector<CCValAssign, 16> RVLocs;
1680 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
1681 CCState CCInfo(CC, TM, RVLocs);
1682 CCInfo.AnalyzeReturn(Op.Val, RetCC_PPC);
1684 // If this is the first return lowered for this function, add the regs to the
1685 // liveout set for the function.
1686 if (DAG.getMachineFunction().liveout_empty()) {
1687 for (unsigned i = 0; i != RVLocs.size(); ++i)
1688 DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg());
1691 SDOperand Chain = Op.getOperand(0);
1694 // Copy the result values into the output registers.
1695 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1696 CCValAssign &VA = RVLocs[i];
1697 assert(VA.isRegLoc() && "Can only return in registers!");
1698 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
1699 Flag = Chain.getValue(1);
1703 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain, Flag);
1705 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain);
1708 static SDOperand LowerSTACKRESTORE(SDOperand Op, SelectionDAG &DAG,
1709 const PPCSubtarget &Subtarget) {
1710 // When we pop the dynamic allocation we need to restore the SP link.
1712 // Get the corect type for pointers.
1713 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1715 // Construct the stack pointer operand.
1716 bool IsPPC64 = Subtarget.isPPC64();
1717 unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1;
1718 SDOperand StackPtr = DAG.getRegister(SP, PtrVT);
1720 // Get the operands for the STACKRESTORE.
1721 SDOperand Chain = Op.getOperand(0);
1722 SDOperand SaveSP = Op.getOperand(1);
1724 // Load the old link SP.
1725 SDOperand LoadLinkSP = DAG.getLoad(PtrVT, Chain, StackPtr, NULL, 0);
1727 // Restore the stack pointer.
1728 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), SP, SaveSP);
1730 // Store the old link SP.
1731 return DAG.getStore(Chain, LoadLinkSP, StackPtr, NULL, 0);
1734 static SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG,
1735 const PPCSubtarget &Subtarget) {
1736 MachineFunction &MF = DAG.getMachineFunction();
1737 bool IsPPC64 = Subtarget.isPPC64();
1738 bool isMachoABI = Subtarget.isMachoABI();
1740 // Get current frame pointer save index. The users of this index will be
1741 // primarily DYNALLOC instructions.
1742 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1743 int FPSI = FI->getFramePointerSaveIndex();
1745 // If the frame pointer save index hasn't been defined yet.
1747 // Find out what the fix offset of the frame pointer save area.
1748 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isMachoABI);
1750 // Allocate the frame index for frame pointer save area.
1751 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
1753 FI->setFramePointerSaveIndex(FPSI);
1757 SDOperand Chain = Op.getOperand(0);
1758 SDOperand Size = Op.getOperand(1);
1760 // Get the corect type for pointers.
1761 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1763 SDOperand NegSize = DAG.getNode(ISD::SUB, PtrVT,
1764 DAG.getConstant(0, PtrVT), Size);
1765 // Construct a node for the frame pointer save index.
1766 SDOperand FPSIdx = DAG.getFrameIndex(FPSI, PtrVT);
1767 // Build a DYNALLOC node.
1768 SDOperand Ops[3] = { Chain, NegSize, FPSIdx };
1769 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
1770 return DAG.getNode(PPCISD::DYNALLOC, VTs, Ops, 3);
1774 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
1776 static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
1777 // Not FP? Not a fsel.
1778 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) ||
1779 !MVT::isFloatingPoint(Op.getOperand(2).getValueType()))
1782 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1784 // Cannot handle SETEQ/SETNE.
1785 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand();
1787 MVT::ValueType ResVT = Op.getValueType();
1788 MVT::ValueType CmpVT = Op.getOperand(0).getValueType();
1789 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
1790 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3);
1792 // If the RHS of the comparison is a 0.0, we don't need to do the
1793 // subtraction at all.
1794 if (isFloatingPointZero(RHS))
1796 default: break; // SETUO etc aren't handled by fsel.
1800 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
1804 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
1805 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
1806 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
1810 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
1814 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
1815 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
1816 return DAG.getNode(PPCISD::FSEL, ResVT,
1817 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV);
1822 default: break; // SETUO etc aren't handled by fsel.
1826 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
1827 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1828 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1829 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
1833 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
1834 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1835 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1836 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
1840 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
1841 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1842 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1843 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
1847 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
1848 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1849 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1850 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
1855 static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
1856 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType()));
1857 SDOperand Src = Op.getOperand(0);
1858 if (Src.getValueType() == MVT::f32)
1859 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src);
1862 switch (Op.getValueType()) {
1863 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
1865 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src);
1868 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src);
1872 // Convert the FP value to an int value through memory.
1873 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Tmp);
1874 if (Op.getValueType() == MVT::i32)
1875 Bits = DAG.getNode(ISD::TRUNCATE, MVT::i32, Bits);
1879 static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
1880 if (Op.getOperand(0).getValueType() == MVT::i64) {
1881 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
1882 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
1883 if (Op.getValueType() == MVT::f32)
1884 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
1888 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
1889 "Unhandled SINT_TO_FP type in custom expander!");
1890 // Since we only generate this in 64-bit mode, we can take advantage of
1891 // 64-bit registers. In particular, sign extend the input value into the
1892 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
1893 // then lfd it and fcfid it.
1894 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
1895 int FrameIdx = FrameInfo->CreateStackObject(8, 8);
1896 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1897 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
1899 SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32,
1902 // STD the extended value into the stack slot.
1903 SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other,
1904 DAG.getEntryNode(), Ext64, FIdx,
1905 DAG.getSrcValue(NULL));
1906 // Load the value as a double.
1907 SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0);
1909 // FCFID it and return it.
1910 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld);
1911 if (Op.getValueType() == MVT::f32)
1912 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
1916 static SDOperand LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) {
1917 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
1918 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
1920 // Expand into a bunch of logical ops. Note that these ops
1921 // depend on the PPC behavior for oversized shift amounts.
1922 SDOperand Lo = Op.getOperand(0);
1923 SDOperand Hi = Op.getOperand(1);
1924 SDOperand Amt = Op.getOperand(2);
1926 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
1927 DAG.getConstant(32, MVT::i32), Amt);
1928 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt);
1929 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1);
1930 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
1931 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
1932 DAG.getConstant(-32U, MVT::i32));
1933 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5);
1934 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
1935 SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt);
1936 SDOperand OutOps[] = { OutLo, OutHi };
1937 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
1941 static SDOperand LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) {
1942 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
1943 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRL!");
1945 // Otherwise, expand into a bunch of logical ops. Note that these ops
1946 // depend on the PPC behavior for oversized shift amounts.
1947 SDOperand Lo = Op.getOperand(0);
1948 SDOperand Hi = Op.getOperand(1);
1949 SDOperand Amt = Op.getOperand(2);
1951 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
1952 DAG.getConstant(32, MVT::i32), Amt);
1953 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
1954 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
1955 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
1956 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
1957 DAG.getConstant(-32U, MVT::i32));
1958 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5);
1959 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
1960 SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt);
1961 SDOperand OutOps[] = { OutLo, OutHi };
1962 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
1966 static SDOperand LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) {
1967 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
1968 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!");
1970 // Otherwise, expand into a bunch of logical ops, followed by a select_cc.
1971 SDOperand Lo = Op.getOperand(0);
1972 SDOperand Hi = Op.getOperand(1);
1973 SDOperand Amt = Op.getOperand(2);
1975 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
1976 DAG.getConstant(32, MVT::i32), Amt);
1977 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
1978 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
1979 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
1980 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
1981 DAG.getConstant(-32U, MVT::i32));
1982 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5);
1983 SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt);
1984 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32),
1985 Tmp4, Tmp6, ISD::SETLE);
1986 SDOperand OutOps[] = { OutLo, OutHi };
1987 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
1991 //===----------------------------------------------------------------------===//
1992 // Vector related lowering.
1995 // If this is a vector of constants or undefs, get the bits. A bit in
1996 // UndefBits is set if the corresponding element of the vector is an
1997 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
1998 // zero. Return true if this is not an array of constants, false if it is.
2000 static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
2001 uint64_t UndefBits[2]) {
2002 // Start with zero'd results.
2003 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0;
2005 unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType());
2006 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
2007 SDOperand OpVal = BV->getOperand(i);
2009 unsigned PartNo = i >= e/2; // In the upper 128 bits?
2010 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t.
2012 uint64_t EltBits = 0;
2013 if (OpVal.getOpcode() == ISD::UNDEF) {
2014 uint64_t EltUndefBits = ~0U >> (32-EltBitSize);
2015 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize);
2017 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
2018 EltBits = CN->getValue() & (~0U >> (32-EltBitSize));
2019 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
2020 assert(CN->getValueType(0) == MVT::f32 &&
2021 "Only one legal FP vector type!");
2022 EltBits = FloatToBits(CN->getValue());
2024 // Nonconstant element.
2028 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize);
2031 //printf("%llx %llx %llx %llx\n",
2032 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]);
2036 // If this is a splat (repetition) of a value across the whole vector, return
2037 // the smallest size that splats it. For example, "0x01010101010101..." is a
2038 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
2039 // SplatSize = 1 byte.
2040 static bool isConstantSplat(const uint64_t Bits128[2],
2041 const uint64_t Undef128[2],
2042 unsigned &SplatBits, unsigned &SplatUndef,
2043 unsigned &SplatSize) {
2045 // Don't let undefs prevent splats from matching. See if the top 64-bits are
2046 // the same as the lower 64-bits, ignoring undefs.
2047 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0]))
2048 return false; // Can't be a splat if two pieces don't match.
2050 uint64_t Bits64 = Bits128[0] | Bits128[1];
2051 uint64_t Undef64 = Undef128[0] & Undef128[1];
2053 // Check that the top 32-bits are the same as the lower 32-bits, ignoring
2055 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64))
2056 return false; // Can't be a splat if two pieces don't match.
2058 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32);
2059 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32);
2061 // If the top 16-bits are different than the lower 16-bits, ignoring
2062 // undefs, we have an i32 splat.
2063 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) {
2065 SplatUndef = Undef32;
2070 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16);
2071 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16);
2073 // If the top 8-bits are different than the lower 8-bits, ignoring
2074 // undefs, we have an i16 splat.
2075 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) {
2077 SplatUndef = Undef16;
2082 // Otherwise, we have an 8-bit splat.
2083 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8);
2084 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8);
2089 /// BuildSplatI - Build a canonical splati of Val with an element size of
2090 /// SplatSize. Cast the result to VT.
2091 static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT,
2092 SelectionDAG &DAG) {
2093 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
2095 static const MVT::ValueType VTys[] = { // canonical VT to use for each size.
2096 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
2099 MVT::ValueType ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
2101 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
2105 MVT::ValueType CanonicalVT = VTys[SplatSize-1];
2107 // Build a canonical splat for this value.
2108 SDOperand Elt = DAG.getConstant(Val, MVT::getVectorBaseType(CanonicalVT));
2109 SmallVector<SDOperand, 8> Ops;
2110 Ops.assign(MVT::getVectorNumElements(CanonicalVT), Elt);
2111 SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT,
2112 &Ops[0], Ops.size());
2113 return DAG.getNode(ISD::BIT_CONVERT, ReqVT, Res);
2116 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
2117 /// specified intrinsic ID.
2118 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS,
2120 MVT::ValueType DestVT = MVT::Other) {
2121 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
2122 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
2123 DAG.getConstant(IID, MVT::i32), LHS, RHS);
2126 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
2127 /// specified intrinsic ID.
2128 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1,
2129 SDOperand Op2, SelectionDAG &DAG,
2130 MVT::ValueType DestVT = MVT::Other) {
2131 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
2132 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
2133 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
2137 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
2138 /// amount. The result has the specified value type.
2139 static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt,
2140 MVT::ValueType VT, SelectionDAG &DAG) {
2141 // Force LHS/RHS to be the right type.
2142 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS);
2143 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS);
2146 for (unsigned i = 0; i != 16; ++i)
2147 Ops[i] = DAG.getConstant(i+Amt, MVT::i32);
2148 SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS,
2149 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16));
2150 return DAG.getNode(ISD::BIT_CONVERT, VT, T);
2153 // If this is a case we can't handle, return null and let the default
2154 // expansion code take care of it. If we CAN select this case, and if it
2155 // selects to a single instruction, return Op. Otherwise, if we can codegen
2156 // this case more efficiently than a constant pool load, lower it to the
2157 // sequence of ops that should be used.
2158 static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2159 // If this is a vector of constants or undefs, get the bits. A bit in
2160 // UndefBits is set if the corresponding element of the vector is an
2161 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
2163 uint64_t VectorBits[2];
2164 uint64_t UndefBits[2];
2165 if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits))
2166 return SDOperand(); // Not a constant vector.
2168 // If this is a splat (repetition) of a value across the whole vector, return
2169 // the smallest size that splats it. For example, "0x01010101010101..." is a
2170 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
2171 // SplatSize = 1 byte.
2172 unsigned SplatBits, SplatUndef, SplatSize;
2173 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){
2174 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0;
2176 // First, handle single instruction cases.
2179 if (SplatBits == 0) {
2180 // Canonicalize all zero vectors to be v4i32.
2181 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
2182 SDOperand Z = DAG.getConstant(0, MVT::i32);
2183 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z);
2184 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z);
2189 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
2190 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize);
2191 if (SextVal >= -16 && SextVal <= 15)
2192 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG);
2195 // Two instruction sequences.
2197 // If this value is in the range [-32,30] and is even, use:
2198 // tmp = VSPLTI[bhw], result = add tmp, tmp
2199 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
2200 Op = BuildSplatI(SextVal >> 1, SplatSize, Op.getValueType(), DAG);
2201 return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op);
2204 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
2205 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
2207 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
2208 // Make -1 and vspltisw -1:
2209 SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG);
2211 // Make the VSLW intrinsic, computing 0x8000_0000.
2212 SDOperand Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
2215 // xor by OnesV to invert it.
2216 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV);
2217 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2220 // Check to see if this is a wide variety of vsplti*, binop self cases.
2221 unsigned SplatBitSize = SplatSize*8;
2222 static const char SplatCsts[] = {
2223 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
2224 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
2227 for (unsigned idx = 0; idx < sizeof(SplatCsts)/sizeof(SplatCsts[0]); ++idx){
2228 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
2229 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
2230 int i = SplatCsts[idx];
2232 // Figure out what shift amount will be used by altivec if shifted by i in
2234 unsigned TypeShiftAmt = i & (SplatBitSize-1);
2236 // vsplti + shl self.
2237 if (SextVal == (i << (int)TypeShiftAmt)) {
2238 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2239 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2240 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
2241 Intrinsic::ppc_altivec_vslw
2243 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2244 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2247 // vsplti + srl self.
2248 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
2249 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2250 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2251 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
2252 Intrinsic::ppc_altivec_vsrw
2254 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2255 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2258 // vsplti + sra self.
2259 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
2260 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2261 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2262 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
2263 Intrinsic::ppc_altivec_vsraw
2265 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2266 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2269 // vsplti + rol self.
2270 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
2271 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
2272 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2273 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2274 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
2275 Intrinsic::ppc_altivec_vrlw
2277 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2278 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2281 // t = vsplti c, result = vsldoi t, t, 1
2282 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
2283 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2284 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG);
2286 // t = vsplti c, result = vsldoi t, t, 2
2287 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
2288 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2289 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG);
2291 // t = vsplti c, result = vsldoi t, t, 3
2292 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
2293 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2294 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG);
2298 // Three instruction sequences.
2300 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
2301 if (SextVal >= 0 && SextVal <= 31) {
2302 SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG);
2303 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
2304 LHS = DAG.getNode(ISD::SUB, Op.getValueType(), LHS, RHS);
2305 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
2307 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
2308 if (SextVal >= -31 && SextVal <= 0) {
2309 SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG);
2310 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
2311 LHS = DAG.getNode(ISD::ADD, Op.getValueType(), LHS, RHS);
2312 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
2319 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
2320 /// the specified operations to build the shuffle.
2321 static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS,
2322 SDOperand RHS, SelectionDAG &DAG) {
2323 unsigned OpNum = (PFEntry >> 26) & 0x0F;
2324 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
2325 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
2328 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
2340 if (OpNum == OP_COPY) {
2341 if (LHSID == (1*9+2)*9+3) return LHS;
2342 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
2346 SDOperand OpLHS, OpRHS;
2347 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG);
2348 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG);
2350 unsigned ShufIdxs[16];
2352 default: assert(0 && "Unknown i32 permute!");
2354 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
2355 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
2356 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
2357 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
2360 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
2361 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
2362 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
2363 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
2366 for (unsigned i = 0; i != 16; ++i)
2367 ShufIdxs[i] = (i&3)+0;
2370 for (unsigned i = 0; i != 16; ++i)
2371 ShufIdxs[i] = (i&3)+4;
2374 for (unsigned i = 0; i != 16; ++i)
2375 ShufIdxs[i] = (i&3)+8;
2378 for (unsigned i = 0; i != 16; ++i)
2379 ShufIdxs[i] = (i&3)+12;
2382 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG);
2384 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG);
2386 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG);
2389 for (unsigned i = 0; i != 16; ++i)
2390 Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i32);
2392 return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS,
2393 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
2396 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
2397 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
2398 /// return the code it can be lowered into. Worst case, it can always be
2399 /// lowered into a vperm.
2400 static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
2401 SDOperand V1 = Op.getOperand(0);
2402 SDOperand V2 = Op.getOperand(1);
2403 SDOperand PermMask = Op.getOperand(2);
2405 // Cases that are handled by instructions that take permute immediates
2406 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
2407 // selected by the instruction selector.
2408 if (V2.getOpcode() == ISD::UNDEF) {
2409 if (PPC::isSplatShuffleMask(PermMask.Val, 1) ||
2410 PPC::isSplatShuffleMask(PermMask.Val, 2) ||
2411 PPC::isSplatShuffleMask(PermMask.Val, 4) ||
2412 PPC::isVPKUWUMShuffleMask(PermMask.Val, true) ||
2413 PPC::isVPKUHUMShuffleMask(PermMask.Val, true) ||
2414 PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 ||
2415 PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) ||
2416 PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) ||
2417 PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) ||
2418 PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) ||
2419 PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) ||
2420 PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) {
2425 // Altivec has a variety of "shuffle immediates" that take two vector inputs
2426 // and produce a fixed permutation. If any of these match, do not lower to
2428 if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) ||
2429 PPC::isVPKUHUMShuffleMask(PermMask.Val, false) ||
2430 PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 ||
2431 PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) ||
2432 PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) ||
2433 PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) ||
2434 PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) ||
2435 PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) ||
2436 PPC::isVMRGHShuffleMask(PermMask.Val, 4, false))
2439 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
2440 // perfect shuffle table to emit an optimal matching sequence.
2441 unsigned PFIndexes[4];
2442 bool isFourElementShuffle = true;
2443 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
2444 unsigned EltNo = 8; // Start out undef.
2445 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
2446 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF)
2447 continue; // Undef, ignore it.
2449 unsigned ByteSource =
2450 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue();
2451 if ((ByteSource & 3) != j) {
2452 isFourElementShuffle = false;
2457 EltNo = ByteSource/4;
2458 } else if (EltNo != ByteSource/4) {
2459 isFourElementShuffle = false;
2463 PFIndexes[i] = EltNo;
2466 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
2467 // perfect shuffle vector to determine if it is cost effective to do this as
2468 // discrete instructions, or whether we should use a vperm.
2469 if (isFourElementShuffle) {
2470 // Compute the index in the perfect shuffle table.
2471 unsigned PFTableIndex =
2472 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
2474 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
2475 unsigned Cost = (PFEntry >> 30);
2477 // Determining when to avoid vperm is tricky. Many things affect the cost
2478 // of vperm, particularly how many times the perm mask needs to be computed.
2479 // For example, if the perm mask can be hoisted out of a loop or is already
2480 // used (perhaps because there are multiple permutes with the same shuffle
2481 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
2482 // the loop requires an extra register.
2484 // As a compromise, we only emit discrete instructions if the shuffle can be
2485 // generated in 3 or fewer operations. When we have loop information
2486 // available, if this block is within a loop, we should avoid using vperm
2487 // for 3-operation perms and use a constant pool load instead.
2489 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG);
2492 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
2493 // vector that will get spilled to the constant pool.
2494 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
2496 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
2497 // that it is in input element units, not in bytes. Convert now.
2498 MVT::ValueType EltVT = MVT::getVectorBaseType(V1.getValueType());
2499 unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8;
2501 SmallVector<SDOperand, 16> ResultMask;
2502 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
2504 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
2507 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue();
2509 for (unsigned j = 0; j != BytesPerElement; ++j)
2510 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
2514 SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8,
2515 &ResultMask[0], ResultMask.size());
2516 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
2519 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
2520 /// altivec comparison. If it is, return true and fill in Opc/isDot with
2521 /// information about the intrinsic.
2522 static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc,
2524 unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue();
2527 switch (IntrinsicID) {
2528 default: return false;
2529 // Comparison predicates.
2530 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
2531 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
2532 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
2533 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
2534 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
2535 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
2536 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
2537 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
2538 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
2539 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
2540 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
2541 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
2542 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
2544 // Normal Comparisons.
2545 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
2546 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
2547 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
2548 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
2549 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
2550 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
2551 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
2552 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
2553 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
2554 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
2555 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
2556 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
2557 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
2562 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
2563 /// lower, do it, otherwise return null.
2564 static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
2565 // If this is a lowered altivec predicate compare, CompareOpc is set to the
2566 // opcode number of the comparison.
2569 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
2570 return SDOperand(); // Don't custom lower most intrinsics.
2572 // If this is a non-dot comparison, make the VCMP node and we are done.
2574 SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(),
2575 Op.getOperand(1), Op.getOperand(2),
2576 DAG.getConstant(CompareOpc, MVT::i32));
2577 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp);
2580 // Create the PPCISD altivec 'dot' comparison node.
2582 Op.getOperand(2), // LHS
2583 Op.getOperand(3), // RHS
2584 DAG.getConstant(CompareOpc, MVT::i32)
2586 std::vector<MVT::ValueType> VTs;
2587 VTs.push_back(Op.getOperand(2).getValueType());
2588 VTs.push_back(MVT::Flag);
2589 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
2591 // Now that we have the comparison, emit a copy from the CR to a GPR.
2592 // This is flagged to the above dot comparison.
2593 SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32,
2594 DAG.getRegister(PPC::CR6, MVT::i32),
2595 CompNode.getValue(1));
2597 // Unpack the result based on how the target uses it.
2598 unsigned BitNo; // Bit # of CR6.
2599 bool InvertBit; // Invert result?
2600 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
2601 default: // Can't happen, don't crash on invalid number though.
2602 case 0: // Return the value of the EQ bit of CR6.
2603 BitNo = 0; InvertBit = false;
2605 case 1: // Return the inverted value of the EQ bit of CR6.
2606 BitNo = 0; InvertBit = true;
2608 case 2: // Return the value of the LT bit of CR6.
2609 BitNo = 2; InvertBit = false;
2611 case 3: // Return the inverted value of the LT bit of CR6.
2612 BitNo = 2; InvertBit = true;
2616 // Shift the bit into the low position.
2617 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags,
2618 DAG.getConstant(8-(3-BitNo), MVT::i32));
2620 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags,
2621 DAG.getConstant(1, MVT::i32));
2623 // If we are supposed to, toggle the bit.
2625 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags,
2626 DAG.getConstant(1, MVT::i32));
2630 static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2631 // Create a stack slot that is 16-byte aligned.
2632 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
2633 int FrameIdx = FrameInfo->CreateStackObject(16, 16);
2634 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2635 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
2637 // Store the input value into Value#0 of the stack slot.
2638 SDOperand Store = DAG.getStore(DAG.getEntryNode(),
2639 Op.getOperand(0), FIdx, NULL, 0);
2641 return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0);
2644 static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) {
2645 if (Op.getValueType() == MVT::v4i32) {
2646 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2648 SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG);
2649 SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt.
2651 SDOperand RHSSwap = // = vrlw RHS, 16
2652 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG);
2654 // Shrinkify inputs to v8i16.
2655 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS);
2656 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS);
2657 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap);
2659 // Low parts multiplied together, generating 32-bit results (we ignore the
2661 SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
2662 LHS, RHS, DAG, MVT::v4i32);
2664 SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
2665 LHS, RHSSwap, Zero, DAG, MVT::v4i32);
2666 // Shift the high parts up 16 bits.
2667 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG);
2668 return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd);
2669 } else if (Op.getValueType() == MVT::v8i16) {
2670 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2672 SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG);
2674 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
2675 LHS, RHS, Zero, DAG);
2676 } else if (Op.getValueType() == MVT::v16i8) {
2677 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2679 // Multiply the even 8-bit parts, producing 16-bit sums.
2680 SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
2681 LHS, RHS, DAG, MVT::v8i16);
2682 EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts);
2684 // Multiply the odd 8-bit parts, producing 16-bit sums.
2685 SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
2686 LHS, RHS, DAG, MVT::v8i16);
2687 OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts);
2689 // Merge the results together.
2691 for (unsigned i = 0; i != 8; ++i) {
2692 Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8);
2693 Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8);
2695 return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts,
2696 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
2698 assert(0 && "Unknown mul to lower!");
2703 /// LowerOperation - Provide custom lowering hooks for some operations.
2705 SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
2706 switch (Op.getOpcode()) {
2707 default: assert(0 && "Wasn't expecting to be able to lower this!");
2708 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2709 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
2710 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
2711 case ISD::SETCC: return LowerSETCC(Op, DAG);
2712 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
2713 case ISD::FORMAL_ARGUMENTS:
2714 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex, PPCSubTarget);
2715 case ISD::CALL: return LowerCALL(Op, DAG, PPCSubTarget);
2716 case ISD::RET: return LowerRET(Op, DAG, getTargetMachine());
2717 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
2718 case ISD::DYNAMIC_STACKALLOC:
2719 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
2721 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
2722 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
2723 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
2725 // Lower 64-bit shifts.
2726 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
2727 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
2728 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
2730 // Vector-related lowering.
2731 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
2732 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2733 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2734 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
2735 case ISD::MUL: return LowerMUL(Op, DAG);
2737 // Frame & Return address. Currently unimplemented
2738 case ISD::RETURNADDR: break;
2739 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
2744 //===----------------------------------------------------------------------===//
2745 // Other Lowering Code
2746 //===----------------------------------------------------------------------===//
2749 PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
2750 MachineBasicBlock *BB) {
2751 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2752 assert((MI->getOpcode() == PPC::SELECT_CC_I4 ||
2753 MI->getOpcode() == PPC::SELECT_CC_I8 ||
2754 MI->getOpcode() == PPC::SELECT_CC_F4 ||
2755 MI->getOpcode() == PPC::SELECT_CC_F8 ||
2756 MI->getOpcode() == PPC::SELECT_CC_VRRC) &&
2757 "Unexpected instr type to insert");
2759 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
2760 // control-flow pattern. The incoming instruction knows the destination vreg
2761 // to set, the condition code register to branch on, the true/false values to
2762 // select between, and a branch opcode to use.
2763 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2764 ilist<MachineBasicBlock>::iterator It = BB;
2770 // cmpTY ccX, r1, r2
2772 // fallthrough --> copy0MBB
2773 MachineBasicBlock *thisMBB = BB;
2774 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
2775 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
2776 unsigned SelectPred = MI->getOperand(4).getImm();
2777 BuildMI(BB, TII->get(PPC::BCC))
2778 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
2779 MachineFunction *F = BB->getParent();
2780 F->getBasicBlockList().insert(It, copy0MBB);
2781 F->getBasicBlockList().insert(It, sinkMBB);
2782 // Update machine-CFG edges by first adding all successors of the current
2783 // block to the new block which will contain the Phi node for the select.
2784 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
2785 e = BB->succ_end(); i != e; ++i)
2786 sinkMBB->addSuccessor(*i);
2787 // Next, remove all successors of the current block, and add the true
2788 // and fallthrough blocks as its successors.
2789 while(!BB->succ_empty())
2790 BB->removeSuccessor(BB->succ_begin());
2791 BB->addSuccessor(copy0MBB);
2792 BB->addSuccessor(sinkMBB);
2795 // %FalseValue = ...
2796 // # fallthrough to sinkMBB
2799 // Update machine-CFG edges
2800 BB->addSuccessor(sinkMBB);
2803 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
2806 BuildMI(BB, TII->get(PPC::PHI), MI->getOperand(0).getReg())
2807 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
2808 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
2810 delete MI; // The pseudo instruction is gone now.
2814 //===----------------------------------------------------------------------===//
2815 // Target Optimization Hooks
2816 //===----------------------------------------------------------------------===//
2818 SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
2819 DAGCombinerInfo &DCI) const {
2820 TargetMachine &TM = getTargetMachine();
2821 SelectionDAG &DAG = DCI.DAG;
2822 switch (N->getOpcode()) {
2825 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
2826 if (C->getValue() == 0) // 0 << V -> 0.
2827 return N->getOperand(0);
2831 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
2832 if (C->getValue() == 0) // 0 >>u V -> 0.
2833 return N->getOperand(0);
2837 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
2838 if (C->getValue() == 0 || // 0 >>s V -> 0.
2839 C->isAllOnesValue()) // -1 >>s V -> -1.
2840 return N->getOperand(0);
2844 case ISD::SINT_TO_FP:
2845 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
2846 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
2847 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
2848 // We allow the src/dst to be either f32/f64, but the intermediate
2849 // type must be i64.
2850 if (N->getOperand(0).getValueType() == MVT::i64) {
2851 SDOperand Val = N->getOperand(0).getOperand(0);
2852 if (Val.getValueType() == MVT::f32) {
2853 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
2854 DCI.AddToWorklist(Val.Val);
2857 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val);
2858 DCI.AddToWorklist(Val.Val);
2859 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val);
2860 DCI.AddToWorklist(Val.Val);
2861 if (N->getValueType(0) == MVT::f32) {
2862 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val);
2863 DCI.AddToWorklist(Val.Val);
2866 } else if (N->getOperand(0).getValueType() == MVT::i32) {
2867 // If the intermediate type is i32, we can avoid the load/store here
2874 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
2875 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
2876 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
2877 N->getOperand(1).getValueType() == MVT::i32) {
2878 SDOperand Val = N->getOperand(1).getOperand(0);
2879 if (Val.getValueType() == MVT::f32) {
2880 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
2881 DCI.AddToWorklist(Val.Val);
2883 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val);
2884 DCI.AddToWorklist(Val.Val);
2886 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val,
2887 N->getOperand(2), N->getOperand(3));
2888 DCI.AddToWorklist(Val.Val);
2892 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
2893 if (N->getOperand(1).getOpcode() == ISD::BSWAP &&
2894 N->getOperand(1).Val->hasOneUse() &&
2895 (N->getOperand(1).getValueType() == MVT::i32 ||
2896 N->getOperand(1).getValueType() == MVT::i16)) {
2897 SDOperand BSwapOp = N->getOperand(1).getOperand(0);
2898 // Do an any-extend to 32-bits if this is a half-word input.
2899 if (BSwapOp.getValueType() == MVT::i16)
2900 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp);
2902 return DAG.getNode(PPCISD::STBRX, MVT::Other, N->getOperand(0), BSwapOp,
2903 N->getOperand(2), N->getOperand(3),
2904 DAG.getValueType(N->getOperand(1).getValueType()));
2908 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
2909 if (ISD::isNON_EXTLoad(N->getOperand(0).Val) &&
2910 N->getOperand(0).hasOneUse() &&
2911 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
2912 SDOperand Load = N->getOperand(0);
2913 LoadSDNode *LD = cast<LoadSDNode>(Load);
2914 // Create the byte-swapping load.
2915 std::vector<MVT::ValueType> VTs;
2916 VTs.push_back(MVT::i32);
2917 VTs.push_back(MVT::Other);
2918 SDOperand SV = DAG.getSrcValue(LD->getSrcValue(), LD->getSrcValueOffset());
2920 LD->getChain(), // Chain
2921 LD->getBasePtr(), // Ptr
2923 DAG.getValueType(N->getValueType(0)) // VT
2925 SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4);
2927 // If this is an i16 load, insert the truncate.
2928 SDOperand ResVal = BSLoad;
2929 if (N->getValueType(0) == MVT::i16)
2930 ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad);
2932 // First, combine the bswap away. This makes the value produced by the
2934 DCI.CombineTo(N, ResVal);
2936 // Next, combine the load away, we give it a bogus result value but a real
2937 // chain result. The result value is dead because the bswap is dead.
2938 DCI.CombineTo(Load.Val, ResVal, BSLoad.getValue(1));
2940 // Return N so it doesn't get rechecked!
2941 return SDOperand(N, 0);
2945 case PPCISD::VCMP: {
2946 // If a VCMPo node already exists with exactly the same operands as this
2947 // node, use its result instead of this node (VCMPo computes both a CR6 and
2948 // a normal output).
2950 if (!N->getOperand(0).hasOneUse() &&
2951 !N->getOperand(1).hasOneUse() &&
2952 !N->getOperand(2).hasOneUse()) {
2954 // Scan all of the users of the LHS, looking for VCMPo's that match.
2955 SDNode *VCMPoNode = 0;
2957 SDNode *LHSN = N->getOperand(0).Val;
2958 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
2960 if ((*UI)->getOpcode() == PPCISD::VCMPo &&
2961 (*UI)->getOperand(1) == N->getOperand(1) &&
2962 (*UI)->getOperand(2) == N->getOperand(2) &&
2963 (*UI)->getOperand(0) == N->getOperand(0)) {
2968 // If there is no VCMPo node, or if the flag value has a single use, don't
2970 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
2973 // Look at the (necessarily single) use of the flag value. If it has a
2974 // chain, this transformation is more complex. Note that multiple things
2975 // could use the value result, which we should ignore.
2976 SDNode *FlagUser = 0;
2977 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
2978 FlagUser == 0; ++UI) {
2979 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
2981 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
2982 if (User->getOperand(i) == SDOperand(VCMPoNode, 1)) {
2989 // If the user is a MFCR instruction, we know this is safe. Otherwise we
2990 // give up for right now.
2991 if (FlagUser->getOpcode() == PPCISD::MFCR)
2992 return SDOperand(VCMPoNode, 0);
2997 // If this is a branch on an altivec predicate comparison, lower this so
2998 // that we don't have to do a MFCR: instead, branch directly on CR6. This
2999 // lowering is done pre-legalize, because the legalizer lowers the predicate
3000 // compare down to code that is difficult to reassemble.
3001 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
3002 SDOperand LHS = N->getOperand(2), RHS = N->getOperand(3);
3006 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
3007 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
3008 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
3009 assert(isDot && "Can't compare against a vector result!");
3011 // If this is a comparison against something other than 0/1, then we know
3012 // that the condition is never/always true.
3013 unsigned Val = cast<ConstantSDNode>(RHS)->getValue();
3014 if (Val != 0 && Val != 1) {
3015 if (CC == ISD::SETEQ) // Cond never true, remove branch.
3016 return N->getOperand(0);
3017 // Always !=, turn it into an unconditional branch.
3018 return DAG.getNode(ISD::BR, MVT::Other,
3019 N->getOperand(0), N->getOperand(4));
3022 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
3024 // Create the PPCISD altivec 'dot' comparison node.
3025 std::vector<MVT::ValueType> VTs;
3027 LHS.getOperand(2), // LHS of compare
3028 LHS.getOperand(3), // RHS of compare
3029 DAG.getConstant(CompareOpc, MVT::i32)
3031 VTs.push_back(LHS.getOperand(2).getValueType());
3032 VTs.push_back(MVT::Flag);
3033 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
3035 // Unpack the result based on how the target uses it.
3036 PPC::Predicate CompOpc;
3037 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) {
3038 default: // Can't happen, don't crash on invalid number though.
3039 case 0: // Branch on the value of the EQ bit of CR6.
3040 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
3042 case 1: // Branch on the inverted value of the EQ bit of CR6.
3043 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
3045 case 2: // Branch on the value of the LT bit of CR6.
3046 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
3048 case 3: // Branch on the inverted value of the LT bit of CR6.
3049 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
3053 return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0),
3054 DAG.getConstant(CompOpc, MVT::i32),
3055 DAG.getRegister(PPC::CR6, MVT::i32),
3056 N->getOperand(4), CompNode.getValue(1));
3065 //===----------------------------------------------------------------------===//
3066 // Inline Assembly Support
3067 //===----------------------------------------------------------------------===//
3069 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
3071 uint64_t &KnownZero,
3073 unsigned Depth) const {
3076 switch (Op.getOpcode()) {
3078 case PPCISD::LBRX: {
3079 // lhbrx is known to have the top bits cleared out.
3080 if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16)
3081 KnownZero = 0xFFFF0000;
3084 case ISD::INTRINSIC_WO_CHAIN: {
3085 switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) {
3087 case Intrinsic::ppc_altivec_vcmpbfp_p:
3088 case Intrinsic::ppc_altivec_vcmpeqfp_p:
3089 case Intrinsic::ppc_altivec_vcmpequb_p:
3090 case Intrinsic::ppc_altivec_vcmpequh_p:
3091 case Intrinsic::ppc_altivec_vcmpequw_p:
3092 case Intrinsic::ppc_altivec_vcmpgefp_p:
3093 case Intrinsic::ppc_altivec_vcmpgtfp_p:
3094 case Intrinsic::ppc_altivec_vcmpgtsb_p:
3095 case Intrinsic::ppc_altivec_vcmpgtsh_p:
3096 case Intrinsic::ppc_altivec_vcmpgtsw_p:
3097 case Intrinsic::ppc_altivec_vcmpgtub_p:
3098 case Intrinsic::ppc_altivec_vcmpgtuh_p:
3099 case Intrinsic::ppc_altivec_vcmpgtuw_p:
3100 KnownZero = ~1U; // All bits but the low one are known to be zero.
3108 /// getConstraintType - Given a constraint letter, return the type of
3109 /// constraint it is for this target.
3110 PPCTargetLowering::ConstraintType
3111 PPCTargetLowering::getConstraintType(char ConstraintLetter) const {
3112 switch (ConstraintLetter) {
3119 return C_RegisterClass;
3121 return TargetLowering::getConstraintType(ConstraintLetter);
3124 std::pair<unsigned, const TargetRegisterClass*>
3125 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
3126 MVT::ValueType VT) const {
3127 if (Constraint.size() == 1) {
3128 // GCC RS6000 Constraint Letters
3129 switch (Constraint[0]) {
3132 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
3133 return std::make_pair(0U, PPC::G8RCRegisterClass);
3134 return std::make_pair(0U, PPC::GPRCRegisterClass);
3137 return std::make_pair(0U, PPC::F4RCRegisterClass);
3138 else if (VT == MVT::f64)
3139 return std::make_pair(0U, PPC::F8RCRegisterClass);
3142 return std::make_pair(0U, PPC::VRRCRegisterClass);
3144 return std::make_pair(0U, PPC::CRRCRegisterClass);
3148 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3152 // isOperandValidForConstraint
3153 SDOperand PPCTargetLowering::
3154 isOperandValidForConstraint(SDOperand Op, char Letter, SelectionDAG &DAG) {
3165 if (!isa<ConstantSDNode>(Op)) return SDOperand(0,0);// Must be an immediate.
3166 unsigned Value = cast<ConstantSDNode>(Op)->getValue();
3168 default: assert(0 && "Unknown constraint letter!");
3169 case 'I': // "I" is a signed 16-bit constant.
3170 if ((short)Value == (int)Value) return Op;
3172 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
3173 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
3174 if ((short)Value == 0) return Op;
3176 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
3177 if ((Value >> 16) == 0) return Op;
3179 case 'M': // "M" is a constant that is greater than 31.
3180 if (Value > 31) return Op;
3182 case 'N': // "N" is a positive constant that is an exact power of two.
3183 if ((int)Value > 0 && isPowerOf2_32(Value)) return Op;
3185 case 'O': // "O" is the constant zero.
3186 if (Value == 0) return Op;
3188 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
3189 if ((short)-Value == (int)-Value) return Op;
3196 // Handle standard constraint letters.
3197 return TargetLowering::isOperandValidForConstraint(Op, Letter, DAG);
3200 /// isLegalAddressImmediate - Return true if the integer value can be used
3201 /// as the offset of the target addressing mode for load / store of the
3203 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{
3204 // PPC allows a sign-extended 16-bit immediate field.
3205 return (V > -(1 << 16) && V < (1 << 16)-1);
3208 bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
3209 return TargetLowering::isLegalAddressImmediate(GV);
3212 SDOperand PPCTargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG)
3214 // Depths > 0 not supported yet!
3215 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
3218 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3219 bool isPPC64 = PtrVT == MVT::i64;
3221 MachineFunction &MF = DAG.getMachineFunction();
3222 MachineFrameInfo *MFI = MF.getFrameInfo();
3223 bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects())
3224 && MFI->getStackSize();
3227 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::X31 : PPC::X1,
3230 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::R31 : PPC::R1,