1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCCallingConv.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCPerfectShuffle.h"
19 #include "PPCTargetMachine.h"
20 #include "PPCTargetObjectFile.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringSwitch.h"
23 #include "llvm/ADT/Triple.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineLoopInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAG.h"
31 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/Constants.h"
34 #include "llvm/IR/DerivedTypes.h"
35 #include "llvm/IR/Function.h"
36 #include "llvm/IR/Intrinsics.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/Target/TargetOptions.h"
45 // FIXME: Remove this once soft-float is supported.
46 static cl::opt<bool> DisablePPCFloatInVariadic("disable-ppc-float-in-variadic",
47 cl::desc("disable saving float registers for va_start on PPC"), cl::Hidden);
49 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
50 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
52 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
53 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
55 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
56 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
58 // FIXME: Remove this once the bug has been fixed!
59 extern cl::opt<bool> ANDIGlueBug;
61 PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
62 const PPCSubtarget &STI)
63 : TargetLowering(TM), Subtarget(STI) {
64 // Use _setjmp/_longjmp instead of setjmp/longjmp.
65 setUseUnderscoreSetJmp(true);
66 setUseUnderscoreLongJmp(true);
68 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
69 // arguments are at least 4/8 bytes aligned.
70 bool isPPC64 = Subtarget.isPPC64();
71 setMinStackArgumentAlignment(isPPC64 ? 8:4);
73 // Set up the register classes.
74 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
75 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
76 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
78 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
79 for (MVT VT : MVT::integer_valuetypes()) {
80 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
81 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
84 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
86 // PowerPC has pre-inc load and store's.
87 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
91 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
92 setIndexedLoadAction(ISD::PRE_INC, MVT::f32, Legal);
93 setIndexedLoadAction(ISD::PRE_INC, MVT::f64, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
99 setIndexedStoreAction(ISD::PRE_INC, MVT::f32, Legal);
100 setIndexedStoreAction(ISD::PRE_INC, MVT::f64, Legal);
102 if (Subtarget.useCRBits()) {
103 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
105 if (isPPC64 || Subtarget.hasFPCVT()) {
106 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
107 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
108 isPPC64 ? MVT::i64 : MVT::i32);
109 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
110 AddPromotedToType (ISD::UINT_TO_FP, MVT::i1,
111 isPPC64 ? MVT::i64 : MVT::i32);
113 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
114 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
117 // PowerPC does not support direct load / store of condition registers
118 setOperationAction(ISD::LOAD, MVT::i1, Custom);
119 setOperationAction(ISD::STORE, MVT::i1, Custom);
121 // FIXME: Remove this once the ANDI glue bug is fixed:
123 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
125 for (MVT VT : MVT::integer_valuetypes()) {
126 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
127 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
128 setTruncStoreAction(VT, MVT::i1, Expand);
131 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
134 // This is used in the ppcf128->int sequence. Note it has different semantics
135 // from FP_ROUND: that rounds to nearest, this rounds to zero.
136 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
138 // We do not currently implement these libm ops for PowerPC.
139 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
140 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
141 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
142 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
143 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
144 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
146 // PowerPC has no SREM/UREM instructions
147 setOperationAction(ISD::SREM, MVT::i32, Expand);
148 setOperationAction(ISD::UREM, MVT::i32, Expand);
149 setOperationAction(ISD::SREM, MVT::i64, Expand);
150 setOperationAction(ISD::UREM, MVT::i64, Expand);
152 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
153 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
154 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
155 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
156 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
157 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
158 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
159 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
160 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
162 // We don't support sin/cos/sqrt/fmod/pow
163 setOperationAction(ISD::FSIN , MVT::f64, Expand);
164 setOperationAction(ISD::FCOS , MVT::f64, Expand);
165 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
166 setOperationAction(ISD::FREM , MVT::f64, Expand);
167 setOperationAction(ISD::FPOW , MVT::f64, Expand);
168 setOperationAction(ISD::FMA , MVT::f64, Legal);
169 setOperationAction(ISD::FSIN , MVT::f32, Expand);
170 setOperationAction(ISD::FCOS , MVT::f32, Expand);
171 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
172 setOperationAction(ISD::FREM , MVT::f32, Expand);
173 setOperationAction(ISD::FPOW , MVT::f32, Expand);
174 setOperationAction(ISD::FMA , MVT::f32, Legal);
176 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
178 // If we're enabling GP optimizations, use hardware square root
179 if (!Subtarget.hasFSQRT() &&
180 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() &&
182 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
184 if (!Subtarget.hasFSQRT() &&
185 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTES() &&
186 Subtarget.hasFRES()))
187 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
189 if (Subtarget.hasFCPSGN()) {
190 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
191 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
193 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
194 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
197 if (Subtarget.hasFPRND()) {
198 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
199 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
200 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
201 setOperationAction(ISD::FROUND, MVT::f64, Legal);
203 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
204 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
205 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
206 setOperationAction(ISD::FROUND, MVT::f32, Legal);
209 // PowerPC does not have BSWAP, CTPOP or CTTZ
210 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
211 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
212 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
213 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
214 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
215 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
216 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
217 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
219 if (Subtarget.hasPOPCNTD()) {
220 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
221 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
223 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
224 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
227 // PowerPC does not have ROTR
228 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
229 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
231 if (!Subtarget.useCRBits()) {
232 // PowerPC does not have Select
233 setOperationAction(ISD::SELECT, MVT::i32, Expand);
234 setOperationAction(ISD::SELECT, MVT::i64, Expand);
235 setOperationAction(ISD::SELECT, MVT::f32, Expand);
236 setOperationAction(ISD::SELECT, MVT::f64, Expand);
239 // PowerPC wants to turn select_cc of FP into fsel when possible.
240 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
241 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
243 // PowerPC wants to optimize integer setcc a bit
244 if (!Subtarget.useCRBits())
245 setOperationAction(ISD::SETCC, MVT::i32, Custom);
247 // PowerPC does not have BRCOND which requires SetCC
248 if (!Subtarget.useCRBits())
249 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
251 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
253 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
254 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
256 // PowerPC does not have [U|S]INT_TO_FP
257 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
258 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
260 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
261 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
262 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
263 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
265 // We cannot sextinreg(i1). Expand to shifts.
266 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
268 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
269 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
270 // support continuation, user-level threading, and etc.. As a result, no
271 // other SjLj exception interfaces are implemented and please don't build
272 // your own exception handling based on them.
273 // LLVM/Clang supports zero-cost DWARF exception handling.
274 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
275 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
277 // We want to legalize GlobalAddress and ConstantPool nodes into the
278 // appropriate instructions to materialize the address.
279 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
280 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
281 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
282 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
283 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
284 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
285 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
286 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
287 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
288 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
291 setOperationAction(ISD::TRAP, MVT::Other, Legal);
293 // TRAMPOLINE is custom lowered.
294 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
295 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
297 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
298 setOperationAction(ISD::VASTART , MVT::Other, Custom);
300 if (Subtarget.isSVR4ABI()) {
302 // VAARG always uses double-word chunks, so promote anything smaller.
303 setOperationAction(ISD::VAARG, MVT::i1, Promote);
304 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
305 setOperationAction(ISD::VAARG, MVT::i8, Promote);
306 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
307 setOperationAction(ISD::VAARG, MVT::i16, Promote);
308 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
309 setOperationAction(ISD::VAARG, MVT::i32, Promote);
310 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
311 setOperationAction(ISD::VAARG, MVT::Other, Expand);
313 // VAARG is custom lowered with the 32-bit SVR4 ABI.
314 setOperationAction(ISD::VAARG, MVT::Other, Custom);
315 setOperationAction(ISD::VAARG, MVT::i64, Custom);
318 setOperationAction(ISD::VAARG, MVT::Other, Expand);
320 if (Subtarget.isSVR4ABI() && !isPPC64)
321 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
322 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
324 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
326 // Use the default implementation.
327 setOperationAction(ISD::VAEND , MVT::Other, Expand);
328 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
329 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
330 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
331 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
333 // We want to custom lower some of our intrinsics.
334 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
336 // To handle counter-based loop conditions.
337 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
339 // Comparisons that require checking two conditions.
340 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
341 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
342 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
343 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
344 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
345 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
346 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
347 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
348 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
349 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
350 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
351 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
353 if (Subtarget.has64BitSupport()) {
354 // They also have instructions for converting between i64 and fp.
355 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
356 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
357 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
358 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
359 // This is just the low 32 bits of a (signed) fp->i64 conversion.
360 // We cannot do this with Promote because i64 is not a legal type.
361 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
363 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
364 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
366 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
367 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
370 // With the instructions enabled under FPCVT, we can do everything.
371 if (Subtarget.hasFPCVT()) {
372 if (Subtarget.has64BitSupport()) {
373 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
374 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
375 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
376 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
379 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
380 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
381 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
382 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
385 if (Subtarget.use64BitRegs()) {
386 // 64-bit PowerPC implementations can support i64 types directly
387 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
388 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
389 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
390 // 64-bit PowerPC wants to expand i128 shifts itself.
391 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
392 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
393 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
395 // 32-bit PowerPC wants to expand i64 shifts itself.
396 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
397 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
398 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
401 if (Subtarget.hasAltivec()) {
402 // First set operation action for all vector types to expand. Then we
403 // will selectively turn on ones that can be effectively codegen'd.
404 for (MVT VT : MVT::vector_valuetypes()) {
405 // add/sub are legal for all supported vector VT's.
406 setOperationAction(ISD::ADD , VT, Legal);
407 setOperationAction(ISD::SUB , VT, Legal);
409 // Vector instructions introduced in P8
410 if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) {
411 setOperationAction(ISD::CTPOP, VT, Legal);
412 setOperationAction(ISD::CTLZ, VT, Legal);
415 setOperationAction(ISD::CTPOP, VT, Expand);
416 setOperationAction(ISD::CTLZ, VT, Expand);
419 // We promote all shuffles to v16i8.
420 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
421 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
423 // We promote all non-typed operations to v4i32.
424 setOperationAction(ISD::AND , VT, Promote);
425 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
426 setOperationAction(ISD::OR , VT, Promote);
427 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
428 setOperationAction(ISD::XOR , VT, Promote);
429 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
430 setOperationAction(ISD::LOAD , VT, Promote);
431 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
432 setOperationAction(ISD::SELECT, VT, Promote);
433 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
434 setOperationAction(ISD::STORE, VT, Promote);
435 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
437 // No other operations are legal.
438 setOperationAction(ISD::MUL , VT, Expand);
439 setOperationAction(ISD::SDIV, VT, Expand);
440 setOperationAction(ISD::SREM, VT, Expand);
441 setOperationAction(ISD::UDIV, VT, Expand);
442 setOperationAction(ISD::UREM, VT, Expand);
443 setOperationAction(ISD::FDIV, VT, Expand);
444 setOperationAction(ISD::FREM, VT, Expand);
445 setOperationAction(ISD::FNEG, VT, Expand);
446 setOperationAction(ISD::FSQRT, VT, Expand);
447 setOperationAction(ISD::FLOG, VT, Expand);
448 setOperationAction(ISD::FLOG10, VT, Expand);
449 setOperationAction(ISD::FLOG2, VT, Expand);
450 setOperationAction(ISD::FEXP, VT, Expand);
451 setOperationAction(ISD::FEXP2, VT, Expand);
452 setOperationAction(ISD::FSIN, VT, Expand);
453 setOperationAction(ISD::FCOS, VT, Expand);
454 setOperationAction(ISD::FABS, VT, Expand);
455 setOperationAction(ISD::FPOWI, VT, Expand);
456 setOperationAction(ISD::FFLOOR, VT, Expand);
457 setOperationAction(ISD::FCEIL, VT, Expand);
458 setOperationAction(ISD::FTRUNC, VT, Expand);
459 setOperationAction(ISD::FRINT, VT, Expand);
460 setOperationAction(ISD::FNEARBYINT, VT, Expand);
461 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
462 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
463 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
464 setOperationAction(ISD::MULHU, VT, Expand);
465 setOperationAction(ISD::MULHS, VT, Expand);
466 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
467 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
468 setOperationAction(ISD::UDIVREM, VT, Expand);
469 setOperationAction(ISD::SDIVREM, VT, Expand);
470 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
471 setOperationAction(ISD::FPOW, VT, Expand);
472 setOperationAction(ISD::BSWAP, VT, Expand);
473 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
474 setOperationAction(ISD::CTTZ, VT, Expand);
475 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
476 setOperationAction(ISD::VSELECT, VT, Expand);
477 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
479 for (MVT InnerVT : MVT::vector_valuetypes()) {
480 setTruncStoreAction(VT, InnerVT, Expand);
481 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
482 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
483 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
487 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
488 // with merges, splats, etc.
489 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
491 setOperationAction(ISD::AND , MVT::v4i32, Legal);
492 setOperationAction(ISD::OR , MVT::v4i32, Legal);
493 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
494 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
495 setOperationAction(ISD::SELECT, MVT::v4i32,
496 Subtarget.useCRBits() ? Legal : Expand);
497 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
498 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
499 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
500 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
501 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
502 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
503 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
504 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
505 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
507 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
508 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
509 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
510 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
512 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
513 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
515 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
516 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
517 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
521 if (Subtarget.hasP8Altivec())
522 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
524 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
526 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
527 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
529 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
530 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
532 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
533 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
534 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
535 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
537 // Altivec does not contain unordered floating-point compare instructions
538 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
539 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
540 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
541 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
543 if (Subtarget.hasVSX()) {
544 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
545 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
547 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
548 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
549 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
550 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
551 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
553 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
555 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
556 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
558 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
559 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
561 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
562 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
563 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
564 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
565 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
567 // Share the Altivec comparison restrictions.
568 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
569 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
570 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
571 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
573 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
574 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
576 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
578 if (Subtarget.hasP8Vector())
579 addRegisterClass(MVT::f32, &PPC::VSSRCRegClass);
581 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
583 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
584 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
586 if (Subtarget.hasP8Altivec()) {
587 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
588 setOperationAction(ISD::SRA, MVT::v2i64, Legal);
589 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
591 setOperationAction(ISD::SETCC, MVT::v2i64, Legal);
594 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
595 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
596 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
598 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
600 // VSX v2i64 only supports non-arithmetic operations.
601 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
602 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
605 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
606 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
607 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
608 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
610 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
612 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
613 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
614 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
615 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
617 // Vector operation legalization checks the result type of
618 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
619 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
620 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
621 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
622 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
624 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
627 if (Subtarget.hasP8Altivec()) {
628 addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass);
629 addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass);
633 if (Subtarget.hasQPX()) {
634 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
635 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
636 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
637 setOperationAction(ISD::FREM, MVT::v4f64, Expand);
639 setOperationAction(ISD::FCOPYSIGN, MVT::v4f64, Legal);
640 setOperationAction(ISD::FGETSIGN, MVT::v4f64, Expand);
642 setOperationAction(ISD::LOAD , MVT::v4f64, Custom);
643 setOperationAction(ISD::STORE , MVT::v4f64, Custom);
645 setTruncStoreAction(MVT::v4f64, MVT::v4f32, Custom);
646 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Custom);
648 if (!Subtarget.useCRBits())
649 setOperationAction(ISD::SELECT, MVT::v4f64, Expand);
650 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
652 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f64, Legal);
653 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f64, Expand);
654 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f64, Expand);
655 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f64, Expand);
656 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f64, Custom);
657 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f64, Legal);
658 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
660 setOperationAction(ISD::FP_TO_SINT , MVT::v4f64, Legal);
661 setOperationAction(ISD::FP_TO_UINT , MVT::v4f64, Expand);
663 setOperationAction(ISD::FP_ROUND , MVT::v4f32, Legal);
664 setOperationAction(ISD::FP_ROUND_INREG , MVT::v4f32, Expand);
665 setOperationAction(ISD::FP_EXTEND, MVT::v4f64, Legal);
667 setOperationAction(ISD::FNEG , MVT::v4f64, Legal);
668 setOperationAction(ISD::FABS , MVT::v4f64, Legal);
669 setOperationAction(ISD::FSIN , MVT::v4f64, Expand);
670 setOperationAction(ISD::FCOS , MVT::v4f64, Expand);
671 setOperationAction(ISD::FPOWI , MVT::v4f64, Expand);
672 setOperationAction(ISD::FPOW , MVT::v4f64, Expand);
673 setOperationAction(ISD::FLOG , MVT::v4f64, Expand);
674 setOperationAction(ISD::FLOG2 , MVT::v4f64, Expand);
675 setOperationAction(ISD::FLOG10 , MVT::v4f64, Expand);
676 setOperationAction(ISD::FEXP , MVT::v4f64, Expand);
677 setOperationAction(ISD::FEXP2 , MVT::v4f64, Expand);
679 setOperationAction(ISD::FMINNUM, MVT::v4f64, Legal);
680 setOperationAction(ISD::FMAXNUM, MVT::v4f64, Legal);
682 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f64, Legal);
683 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f64, Legal);
685 addRegisterClass(MVT::v4f64, &PPC::QFRCRegClass);
687 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
688 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
689 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
690 setOperationAction(ISD::FREM, MVT::v4f32, Expand);
692 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Legal);
693 setOperationAction(ISD::FGETSIGN, MVT::v4f32, Expand);
695 setOperationAction(ISD::LOAD , MVT::v4f32, Custom);
696 setOperationAction(ISD::STORE , MVT::v4f32, Custom);
698 if (!Subtarget.useCRBits())
699 setOperationAction(ISD::SELECT, MVT::v4f32, Expand);
700 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
702 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f32, Legal);
703 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f32, Expand);
704 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f32, Expand);
705 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f32, Expand);
706 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f32, Custom);
707 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
708 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
710 setOperationAction(ISD::FP_TO_SINT , MVT::v4f32, Legal);
711 setOperationAction(ISD::FP_TO_UINT , MVT::v4f32, Expand);
713 setOperationAction(ISD::FNEG , MVT::v4f32, Legal);
714 setOperationAction(ISD::FABS , MVT::v4f32, Legal);
715 setOperationAction(ISD::FSIN , MVT::v4f32, Expand);
716 setOperationAction(ISD::FCOS , MVT::v4f32, Expand);
717 setOperationAction(ISD::FPOWI , MVT::v4f32, Expand);
718 setOperationAction(ISD::FPOW , MVT::v4f32, Expand);
719 setOperationAction(ISD::FLOG , MVT::v4f32, Expand);
720 setOperationAction(ISD::FLOG2 , MVT::v4f32, Expand);
721 setOperationAction(ISD::FLOG10 , MVT::v4f32, Expand);
722 setOperationAction(ISD::FEXP , MVT::v4f32, Expand);
723 setOperationAction(ISD::FEXP2 , MVT::v4f32, Expand);
725 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
726 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
728 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f32, Legal);
729 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f32, Legal);
731 addRegisterClass(MVT::v4f32, &PPC::QSRCRegClass);
733 setOperationAction(ISD::AND , MVT::v4i1, Legal);
734 setOperationAction(ISD::OR , MVT::v4i1, Legal);
735 setOperationAction(ISD::XOR , MVT::v4i1, Legal);
737 if (!Subtarget.useCRBits())
738 setOperationAction(ISD::SELECT, MVT::v4i1, Expand);
739 setOperationAction(ISD::VSELECT, MVT::v4i1, Legal);
741 setOperationAction(ISD::LOAD , MVT::v4i1, Custom);
742 setOperationAction(ISD::STORE , MVT::v4i1, Custom);
744 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4i1, Custom);
745 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4i1, Expand);
746 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4i1, Expand);
747 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4i1, Expand);
748 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4i1, Custom);
749 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i1, Expand);
750 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
752 setOperationAction(ISD::SINT_TO_FP, MVT::v4i1, Custom);
753 setOperationAction(ISD::UINT_TO_FP, MVT::v4i1, Custom);
755 addRegisterClass(MVT::v4i1, &PPC::QBRCRegClass);
757 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
758 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
759 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
760 setOperationAction(ISD::FROUND, MVT::v4f64, Legal);
762 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
763 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
764 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
765 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
767 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Expand);
768 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
770 // These need to set FE_INEXACT, and so cannot be vectorized here.
771 setOperationAction(ISD::FRINT, MVT::v4f64, Expand);
772 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
774 if (TM.Options.UnsafeFPMath) {
775 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
776 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
778 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
779 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
781 setOperationAction(ISD::FDIV, MVT::v4f64, Expand);
782 setOperationAction(ISD::FSQRT, MVT::v4f64, Expand);
784 setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
785 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
789 if (Subtarget.has64BitSupport())
790 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
792 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
795 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
796 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
799 setBooleanContents(ZeroOrOneBooleanContent);
801 if (Subtarget.hasAltivec()) {
802 // Altivec instructions set fields to all zeros or all ones.
803 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
807 // These libcalls are not available in 32-bit.
808 setLibcallName(RTLIB::SHL_I128, nullptr);
809 setLibcallName(RTLIB::SRL_I128, nullptr);
810 setLibcallName(RTLIB::SRA_I128, nullptr);
814 setStackPointerRegisterToSaveRestore(PPC::X1);
815 setExceptionPointerRegister(PPC::X3);
816 setExceptionSelectorRegister(PPC::X4);
818 setStackPointerRegisterToSaveRestore(PPC::R1);
819 setExceptionPointerRegister(PPC::R3);
820 setExceptionSelectorRegister(PPC::R4);
823 // We have target-specific dag combine patterns for the following nodes:
824 setTargetDAGCombine(ISD::SINT_TO_FP);
825 if (Subtarget.hasFPCVT())
826 setTargetDAGCombine(ISD::UINT_TO_FP);
827 setTargetDAGCombine(ISD::LOAD);
828 setTargetDAGCombine(ISD::STORE);
829 setTargetDAGCombine(ISD::BR_CC);
830 if (Subtarget.useCRBits())
831 setTargetDAGCombine(ISD::BRCOND);
832 setTargetDAGCombine(ISD::BSWAP);
833 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
834 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
835 setTargetDAGCombine(ISD::INTRINSIC_VOID);
837 setTargetDAGCombine(ISD::SIGN_EXTEND);
838 setTargetDAGCombine(ISD::ZERO_EXTEND);
839 setTargetDAGCombine(ISD::ANY_EXTEND);
841 if (Subtarget.useCRBits()) {
842 setTargetDAGCombine(ISD::TRUNCATE);
843 setTargetDAGCombine(ISD::SETCC);
844 setTargetDAGCombine(ISD::SELECT_CC);
847 // Use reciprocal estimates.
848 if (TM.Options.UnsafeFPMath) {
849 setTargetDAGCombine(ISD::FDIV);
850 setTargetDAGCombine(ISD::FSQRT);
853 // Darwin long double math library functions have $LDBL128 appended.
854 if (Subtarget.isDarwin()) {
855 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
856 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
857 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
858 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
859 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
860 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
861 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
862 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
863 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
864 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
867 // With 32 condition bits, we don't need to sink (and duplicate) compares
868 // aggressively in CodeGenPrep.
869 if (Subtarget.useCRBits()) {
870 setHasMultipleConditionRegisters();
871 setJumpIsExpensive();
874 setMinFunctionAlignment(2);
875 if (Subtarget.isDarwin())
876 setPrefFunctionAlignment(4);
878 switch (Subtarget.getDarwinDirective()) {
882 case PPC::DIR_E500mc:
891 setPrefFunctionAlignment(4);
892 setPrefLoopAlignment(4);
896 setInsertFencesForAtomic(true);
898 if (Subtarget.enableMachineScheduler())
899 setSchedulingPreference(Sched::Source);
901 setSchedulingPreference(Sched::Hybrid);
903 computeRegisterProperties(STI.getRegisterInfo());
905 // The Freescale cores do better with aggressive inlining of memcpy and
906 // friends. GCC uses same threshold of 128 bytes (= 32 word stores).
907 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
908 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
909 MaxStoresPerMemset = 32;
910 MaxStoresPerMemsetOptSize = 16;
911 MaxStoresPerMemcpy = 32;
912 MaxStoresPerMemcpyOptSize = 8;
913 MaxStoresPerMemmove = 32;
914 MaxStoresPerMemmoveOptSize = 8;
915 } else if (Subtarget.getDarwinDirective() == PPC::DIR_A2) {
916 // The A2 also benefits from (very) aggressive inlining of memcpy and
917 // friends. The overhead of a the function call, even when warm, can be
918 // over one hundred cycles.
919 MaxStoresPerMemset = 128;
920 MaxStoresPerMemcpy = 128;
921 MaxStoresPerMemmove = 128;
925 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
926 /// the desired ByVal argument alignment.
927 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
928 unsigned MaxMaxAlign) {
929 if (MaxAlign == MaxMaxAlign)
931 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
932 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
934 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
936 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
937 unsigned EltAlign = 0;
938 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
939 if (EltAlign > MaxAlign)
941 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
942 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
943 unsigned EltAlign = 0;
944 getMaxByValAlign(STy->getElementType(i), EltAlign, MaxMaxAlign);
945 if (EltAlign > MaxAlign)
947 if (MaxAlign == MaxMaxAlign)
953 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
954 /// function arguments in the caller parameter area.
955 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
956 // Darwin passes everything on 4 byte boundary.
957 if (Subtarget.isDarwin())
960 // 16byte and wider vectors are passed on 16byte boundary.
961 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
962 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
963 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
964 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
968 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
969 switch ((PPCISD::NodeType)Opcode) {
970 case PPCISD::FIRST_NUMBER: break;
971 case PPCISD::FSEL: return "PPCISD::FSEL";
972 case PPCISD::FCFID: return "PPCISD::FCFID";
973 case PPCISD::FCFIDU: return "PPCISD::FCFIDU";
974 case PPCISD::FCFIDS: return "PPCISD::FCFIDS";
975 case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS";
976 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
977 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
978 case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ";
979 case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ";
980 case PPCISD::FRE: return "PPCISD::FRE";
981 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
982 case PPCISD::STFIWX: return "PPCISD::STFIWX";
983 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
984 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
985 case PPCISD::VPERM: return "PPCISD::VPERM";
986 case PPCISD::CMPB: return "PPCISD::CMPB";
987 case PPCISD::Hi: return "PPCISD::Hi";
988 case PPCISD::Lo: return "PPCISD::Lo";
989 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
990 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
991 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
992 case PPCISD::SRL: return "PPCISD::SRL";
993 case PPCISD::SRA: return "PPCISD::SRA";
994 case PPCISD::SHL: return "PPCISD::SHL";
995 case PPCISD::SRA_ADDZE: return "PPCISD::SRA_ADDZE";
996 case PPCISD::CALL: return "PPCISD::CALL";
997 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
998 case PPCISD::MTCTR: return "PPCISD::MTCTR";
999 case PPCISD::BCTRL: return "PPCISD::BCTRL";
1000 case PPCISD::BCTRL_LOAD_TOC: return "PPCISD::BCTRL_LOAD_TOC";
1001 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
1002 case PPCISD::READ_TIME_BASE: return "PPCISD::READ_TIME_BASE";
1003 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
1004 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
1005 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
1006 case PPCISD::MFVSR: return "PPCISD::MFVSR";
1007 case PPCISD::MTVSRA: return "PPCISD::MTVSRA";
1008 case PPCISD::MTVSRZ: return "PPCISD::MTVSRZ";
1009 case PPCISD::ANDIo_1_EQ_BIT: return "PPCISD::ANDIo_1_EQ_BIT";
1010 case PPCISD::ANDIo_1_GT_BIT: return "PPCISD::ANDIo_1_GT_BIT";
1011 case PPCISD::VCMP: return "PPCISD::VCMP";
1012 case PPCISD::VCMPo: return "PPCISD::VCMPo";
1013 case PPCISD::LBRX: return "PPCISD::LBRX";
1014 case PPCISD::STBRX: return "PPCISD::STBRX";
1015 case PPCISD::LFIWAX: return "PPCISD::LFIWAX";
1016 case PPCISD::LFIWZX: return "PPCISD::LFIWZX";
1017 case PPCISD::LXVD2X: return "PPCISD::LXVD2X";
1018 case PPCISD::STXVD2X: return "PPCISD::STXVD2X";
1019 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
1020 case PPCISD::BDNZ: return "PPCISD::BDNZ";
1021 case PPCISD::BDZ: return "PPCISD::BDZ";
1022 case PPCISD::MFFS: return "PPCISD::MFFS";
1023 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
1024 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
1025 case PPCISD::CR6SET: return "PPCISD::CR6SET";
1026 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
1027 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
1028 case PPCISD::PPC32_PICGOT: return "PPCISD::PPC32_PICGOT";
1029 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
1030 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
1031 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
1032 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
1033 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
1034 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
1035 case PPCISD::ADDI_TLSGD_L_ADDR: return "PPCISD::ADDI_TLSGD_L_ADDR";
1036 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
1037 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
1038 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
1039 case PPCISD::ADDI_TLSLD_L_ADDR: return "PPCISD::ADDI_TLSLD_L_ADDR";
1040 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
1041 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
1042 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
1043 case PPCISD::SC: return "PPCISD::SC";
1044 case PPCISD::CLRBHRB: return "PPCISD::CLRBHRB";
1045 case PPCISD::MFBHRBE: return "PPCISD::MFBHRBE";
1046 case PPCISD::RFEBB: return "PPCISD::RFEBB";
1047 case PPCISD::XXSWAPD: return "PPCISD::XXSWAPD";
1048 case PPCISD::QVFPERM: return "PPCISD::QVFPERM";
1049 case PPCISD::QVGPCI: return "PPCISD::QVGPCI";
1050 case PPCISD::QVALIGNI: return "PPCISD::QVALIGNI";
1051 case PPCISD::QVESPLATI: return "PPCISD::QVESPLATI";
1052 case PPCISD::QBFLT: return "PPCISD::QBFLT";
1053 case PPCISD::QVLFSb: return "PPCISD::QVLFSb";
1058 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &C, EVT VT) const {
1060 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
1062 if (Subtarget.hasQPX())
1063 return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements());
1065 return VT.changeVectorElementTypeToInteger();
1068 bool PPCTargetLowering::enableAggressiveFMAFusion(EVT VT) const {
1069 assert(VT.isFloatingPoint() && "Non-floating-point FMA?");
1073 //===----------------------------------------------------------------------===//
1074 // Node matching predicates, for use by the tblgen matching code.
1075 //===----------------------------------------------------------------------===//
1077 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
1078 static bool isFloatingPointZero(SDValue Op) {
1079 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1080 return CFP->getValueAPF().isZero();
1081 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1082 // Maybe this has already been legalized into the constant pool?
1083 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
1084 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1085 return CFP->getValueAPF().isZero();
1090 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
1091 /// true if Op is undef or if it matches the specified value.
1092 static bool isConstantOrUndef(int Op, int Val) {
1093 return Op < 0 || Op == Val;
1096 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
1097 /// VPKUHUM instruction.
1098 /// The ShuffleKind distinguishes between big-endian operations with
1099 /// two different inputs (0), either-endian operations with two identical
1100 /// inputs (1), and little-endian operations with two different inputs (2).
1101 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1102 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1103 SelectionDAG &DAG) {
1104 bool IsLE = DAG.getTarget().getDataLayout()->isLittleEndian();
1105 if (ShuffleKind == 0) {
1108 for (unsigned i = 0; i != 16; ++i)
1109 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
1111 } else if (ShuffleKind == 2) {
1114 for (unsigned i = 0; i != 16; ++i)
1115 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
1117 } else if (ShuffleKind == 1) {
1118 unsigned j = IsLE ? 0 : 1;
1119 for (unsigned i = 0; i != 8; ++i)
1120 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
1121 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
1127 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
1128 /// VPKUWUM instruction.
1129 /// The ShuffleKind distinguishes between big-endian operations with
1130 /// two different inputs (0), either-endian operations with two identical
1131 /// inputs (1), and little-endian operations with two different inputs (2).
1132 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1133 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1134 SelectionDAG &DAG) {
1135 bool IsLE = DAG.getTarget().getDataLayout()->isLittleEndian();
1136 if (ShuffleKind == 0) {
1139 for (unsigned i = 0; i != 16; i += 2)
1140 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
1141 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
1143 } else if (ShuffleKind == 2) {
1146 for (unsigned i = 0; i != 16; i += 2)
1147 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1148 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
1150 } else if (ShuffleKind == 1) {
1151 unsigned j = IsLE ? 0 : 2;
1152 for (unsigned i = 0; i != 8; i += 2)
1153 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1154 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1155 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1156 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
1162 /// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
1163 /// VPKUDUM instruction, AND the VPKUDUM instruction exists for the
1164 /// current subtarget.
1166 /// The ShuffleKind distinguishes between big-endian operations with
1167 /// two different inputs (0), either-endian operations with two identical
1168 /// inputs (1), and little-endian operations with two different inputs (2).
1169 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1170 bool PPC::isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1171 SelectionDAG &DAG) {
1172 const PPCSubtarget& Subtarget =
1173 static_cast<const PPCSubtarget&>(DAG.getSubtarget());
1174 if (!Subtarget.hasP8Vector())
1177 bool IsLE = DAG.getTarget().getDataLayout()->isLittleEndian();
1178 if (ShuffleKind == 0) {
1181 for (unsigned i = 0; i != 16; i += 4)
1182 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+4) ||
1183 !isConstantOrUndef(N->getMaskElt(i+1), i*2+5) ||
1184 !isConstantOrUndef(N->getMaskElt(i+2), i*2+6) ||
1185 !isConstantOrUndef(N->getMaskElt(i+3), i*2+7))
1187 } else if (ShuffleKind == 2) {
1190 for (unsigned i = 0; i != 16; i += 4)
1191 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1192 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1) ||
1193 !isConstantOrUndef(N->getMaskElt(i+2), i*2+2) ||
1194 !isConstantOrUndef(N->getMaskElt(i+3), i*2+3))
1196 } else if (ShuffleKind == 1) {
1197 unsigned j = IsLE ? 0 : 4;
1198 for (unsigned i = 0; i != 8; i += 4)
1199 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1200 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1201 !isConstantOrUndef(N->getMaskElt(i+2), i*2+j+2) ||
1202 !isConstantOrUndef(N->getMaskElt(i+3), i*2+j+3) ||
1203 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1204 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1) ||
1205 !isConstantOrUndef(N->getMaskElt(i+10), i*2+j+2) ||
1206 !isConstantOrUndef(N->getMaskElt(i+11), i*2+j+3))
1212 /// isVMerge - Common function, used to match vmrg* shuffles.
1214 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
1215 unsigned LHSStart, unsigned RHSStart) {
1216 if (N->getValueType(0) != MVT::v16i8)
1218 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
1219 "Unsupported merge size!");
1221 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
1222 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
1223 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
1224 LHSStart+j+i*UnitSize) ||
1225 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
1226 RHSStart+j+i*UnitSize))
1232 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
1233 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
1234 /// The ShuffleKind distinguishes between big-endian merges with two
1235 /// different inputs (0), either-endian merges with two identical inputs (1),
1236 /// and little-endian merges with two different inputs (2). For the latter,
1237 /// the input operands are swapped (see PPCInstrAltivec.td).
1238 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1239 unsigned ShuffleKind, SelectionDAG &DAG) {
1240 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
1241 if (ShuffleKind == 1) // unary
1242 return isVMerge(N, UnitSize, 0, 0);
1243 else if (ShuffleKind == 2) // swapped
1244 return isVMerge(N, UnitSize, 0, 16);
1248 if (ShuffleKind == 1) // unary
1249 return isVMerge(N, UnitSize, 8, 8);
1250 else if (ShuffleKind == 0) // normal
1251 return isVMerge(N, UnitSize, 8, 24);
1257 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
1258 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
1259 /// The ShuffleKind distinguishes between big-endian merges with two
1260 /// different inputs (0), either-endian merges with two identical inputs (1),
1261 /// and little-endian merges with two different inputs (2). For the latter,
1262 /// the input operands are swapped (see PPCInstrAltivec.td).
1263 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1264 unsigned ShuffleKind, SelectionDAG &DAG) {
1265 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
1266 if (ShuffleKind == 1) // unary
1267 return isVMerge(N, UnitSize, 8, 8);
1268 else if (ShuffleKind == 2) // swapped
1269 return isVMerge(N, UnitSize, 8, 24);
1273 if (ShuffleKind == 1) // unary
1274 return isVMerge(N, UnitSize, 0, 0);
1275 else if (ShuffleKind == 0) // normal
1276 return isVMerge(N, UnitSize, 0, 16);
1283 * \brief Common function used to match vmrgew and vmrgow shuffles
1285 * The indexOffset determines whether to look for even or odd words in
1286 * the shuffle mask. This is based on the of the endianness of the target
1289 * - Use offset of 0 to check for odd elements
1290 * - Use offset of 4 to check for even elements
1292 * - Use offset of 0 to check for even elements
1293 * - Use offset of 4 to check for odd elements
1294 * A detailed description of the vector element ordering for little endian and
1295 * big endian can be found at
1296 * http://www.ibm.com/developerworks/library/l-ibm-xl-c-cpp-compiler/index.html
1297 * Targeting your applications - what little endian and big endian IBM XL C/C++
1298 * compiler differences mean to you
1300 * The mask to the shuffle vector instruction specifies the indices of the
1301 * elements from the two input vectors to place in the result. The elements are
1302 * numbered in array-access order, starting with the first vector. These vectors
1303 * are always of type v16i8, thus each vector will contain 16 elements of size
1304 * 8. More info on the shuffle vector can be found in the
1305 * http://llvm.org/docs/LangRef.html#shufflevector-instruction
1306 * Language Reference.
1308 * The RHSStartValue indicates whether the same input vectors are used (unary)
1309 * or two different input vectors are used, based on the following:
1310 * - If the instruction uses the same vector for both inputs, the range of the
1311 * indices will be 0 to 15. In this case, the RHSStart value passed should
1313 * - If the instruction has two different vectors then the range of the
1314 * indices will be 0 to 31. In this case, the RHSStart value passed should
1315 * be 16 (indices 0-15 specify elements in the first vector while indices 16
1316 * to 31 specify elements in the second vector).
1318 * \param[in] N The shuffle vector SD Node to analyze
1319 * \param[in] IndexOffset Specifies whether to look for even or odd elements
1320 * \param[in] RHSStartValue Specifies the starting index for the righthand input
1321 * vector to the shuffle_vector instruction
1322 * \return true iff this shuffle vector represents an even or odd word merge
1324 static bool isVMerge(ShuffleVectorSDNode *N, unsigned IndexOffset,
1325 unsigned RHSStartValue) {
1326 if (N->getValueType(0) != MVT::v16i8)
1329 for (unsigned i = 0; i < 2; ++i)
1330 for (unsigned j = 0; j < 4; ++j)
1331 if (!isConstantOrUndef(N->getMaskElt(i*4+j),
1332 i*RHSStartValue+j+IndexOffset) ||
1333 !isConstantOrUndef(N->getMaskElt(i*4+j+8),
1334 i*RHSStartValue+j+IndexOffset+8))
1340 * \brief Determine if the specified shuffle mask is suitable for the vmrgew or
1341 * vmrgow instructions.
1343 * \param[in] N The shuffle vector SD Node to analyze
1344 * \param[in] CheckEven Check for an even merge (true) or an odd merge (false)
1345 * \param[in] ShuffleKind Identify the type of merge:
1346 * - 0 = big-endian merge with two different inputs;
1347 * - 1 = either-endian merge with two identical inputs;
1348 * - 2 = little-endian merge with two different inputs (inputs are swapped for
1349 * little-endian merges).
1350 * \param[in] DAG The current SelectionDAG
1351 * \return true iff this shuffle mask
1353 bool PPC::isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven,
1354 unsigned ShuffleKind, SelectionDAG &DAG) {
1355 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
1356 unsigned indexOffset = CheckEven ? 4 : 0;
1357 if (ShuffleKind == 1) // Unary
1358 return isVMerge(N, indexOffset, 0);
1359 else if (ShuffleKind == 2) // swapped
1360 return isVMerge(N, indexOffset, 16);
1365 unsigned indexOffset = CheckEven ? 0 : 4;
1366 if (ShuffleKind == 1) // Unary
1367 return isVMerge(N, indexOffset, 0);
1368 else if (ShuffleKind == 0) // Normal
1369 return isVMerge(N, indexOffset, 16);
1376 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
1377 /// amount, otherwise return -1.
1378 /// The ShuffleKind distinguishes between big-endian operations with two
1379 /// different inputs (0), either-endian operations with two identical inputs
1380 /// (1), and little-endian operations with two different inputs (2). For the
1381 /// latter, the input operands are swapped (see PPCInstrAltivec.td).
1382 int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
1383 SelectionDAG &DAG) {
1384 if (N->getValueType(0) != MVT::v16i8)
1387 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1389 // Find the first non-undef value in the shuffle mask.
1391 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
1394 if (i == 16) return -1; // all undef.
1396 // Otherwise, check to see if the rest of the elements are consecutively
1397 // numbered from this value.
1398 unsigned ShiftAmt = SVOp->getMaskElt(i);
1399 if (ShiftAmt < i) return -1;
1402 bool isLE = DAG.getTarget().getDataLayout()->isLittleEndian();
1404 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
1405 // Check the rest of the elements to see if they are consecutive.
1406 for (++i; i != 16; ++i)
1407 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1409 } else if (ShuffleKind == 1) {
1410 // Check the rest of the elements to see if they are consecutive.
1411 for (++i; i != 16; ++i)
1412 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1417 if (ShuffleKind == 2 && isLE)
1418 ShiftAmt = 16 - ShiftAmt;
1423 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1424 /// specifies a splat of a single element that is suitable for input to
1425 /// VSPLTB/VSPLTH/VSPLTW.
1426 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1427 assert(N->getValueType(0) == MVT::v16i8 &&
1428 (EltSize == 1 || EltSize == 2 || EltSize == 4));
1430 // This is a splat operation if each element of the permute is the same, and
1431 // if the value doesn't reference the second vector.
1432 unsigned ElementBase = N->getMaskElt(0);
1434 // FIXME: Handle UNDEF elements too!
1435 if (ElementBase >= 16)
1438 // Check that the indices are consecutive, in the case of a multi-byte element
1439 // splatted with a v16i8 mask.
1440 for (unsigned i = 1; i != EltSize; ++i)
1441 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1444 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1445 if (N->getMaskElt(i) < 0) continue;
1446 for (unsigned j = 0; j != EltSize; ++j)
1447 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1453 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1454 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1455 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1456 SelectionDAG &DAG) {
1457 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1458 assert(isSplatShuffleMask(SVOp, EltSize));
1459 if (DAG.getTarget().getDataLayout()->isLittleEndian())
1460 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1462 return SVOp->getMaskElt(0) / EltSize;
1465 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1466 /// by using a vspltis[bhw] instruction of the specified element size, return
1467 /// the constant being splatted. The ByteSize field indicates the number of
1468 /// bytes of each element [124] -> [bhw].
1469 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1470 SDValue OpVal(nullptr, 0);
1472 // If ByteSize of the splat is bigger than the element size of the
1473 // build_vector, then we have a case where we are checking for a splat where
1474 // multiple elements of the buildvector are folded together into a single
1475 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1476 unsigned EltSize = 16/N->getNumOperands();
1477 if (EltSize < ByteSize) {
1478 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1479 SDValue UniquedVals[4];
1480 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1482 // See if all of the elements in the buildvector agree across.
1483 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1484 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1485 // If the element isn't a constant, bail fully out.
1486 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1489 if (!UniquedVals[i&(Multiple-1)].getNode())
1490 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1491 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1492 return SDValue(); // no match.
1495 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1496 // either constant or undef values that are identical for each chunk. See
1497 // if these chunks can form into a larger vspltis*.
1499 // Check to see if all of the leading entries are either 0 or -1. If
1500 // neither, then this won't fit into the immediate field.
1501 bool LeadingZero = true;
1502 bool LeadingOnes = true;
1503 for (unsigned i = 0; i != Multiple-1; ++i) {
1504 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1506 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
1507 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
1509 // Finally, check the least significant entry.
1511 if (!UniquedVals[Multiple-1].getNode())
1512 return DAG.getTargetConstant(0, SDLoc(N), MVT::i32); // 0,0,0,undef
1513 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1514 if (Val < 16) // 0,0,0,4 -> vspltisw(4)
1515 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
1518 if (!UniquedVals[Multiple-1].getNode())
1519 return DAG.getTargetConstant(~0U, SDLoc(N), MVT::i32); // -1,-1,-1,undef
1520 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1521 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1522 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
1528 // Check to see if this buildvec has a single non-undef value in its elements.
1529 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1530 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1531 if (!OpVal.getNode())
1532 OpVal = N->getOperand(i);
1533 else if (OpVal != N->getOperand(i))
1537 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1539 unsigned ValSizeInBytes = EltSize;
1541 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1542 Value = CN->getZExtValue();
1543 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1544 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1545 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1548 // If the splat value is larger than the element value, then we can never do
1549 // this splat. The only case that we could fit the replicated bits into our
1550 // immediate field for would be zero, and we prefer to use vxor for it.
1551 if (ValSizeInBytes < ByteSize) return SDValue();
1553 // If the element value is larger than the splat value, check if it consists
1554 // of a repeated bit pattern of size ByteSize.
1555 if (!APInt(ValSizeInBytes * 8, Value).isSplat(ByteSize * 8))
1558 // Properly sign extend the value.
1559 int MaskVal = SignExtend32(Value, ByteSize * 8);
1561 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1562 if (MaskVal == 0) return SDValue();
1564 // Finally, if this value fits in a 5 bit sext field, return it
1565 if (SignExtend32<5>(MaskVal) == MaskVal)
1566 return DAG.getTargetConstant(MaskVal, SDLoc(N), MVT::i32);
1570 /// isQVALIGNIShuffleMask - If this is a qvaligni shuffle mask, return the shift
1571 /// amount, otherwise return -1.
1572 int PPC::isQVALIGNIShuffleMask(SDNode *N) {
1573 EVT VT = N->getValueType(0);
1574 if (VT != MVT::v4f64 && VT != MVT::v4f32 && VT != MVT::v4i1)
1577 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1579 // Find the first non-undef value in the shuffle mask.
1581 for (i = 0; i != 4 && SVOp->getMaskElt(i) < 0; ++i)
1584 if (i == 4) return -1; // all undef.
1586 // Otherwise, check to see if the rest of the elements are consecutively
1587 // numbered from this value.
1588 unsigned ShiftAmt = SVOp->getMaskElt(i);
1589 if (ShiftAmt < i) return -1;
1592 // Check the rest of the elements to see if they are consecutive.
1593 for (++i; i != 4; ++i)
1594 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1600 //===----------------------------------------------------------------------===//
1601 // Addressing Mode Selection
1602 //===----------------------------------------------------------------------===//
1604 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1605 /// or 64-bit immediate, and if the value can be accurately represented as a
1606 /// sign extension from a 16-bit value. If so, this returns true and the
1608 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1609 if (!isa<ConstantSDNode>(N))
1612 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1613 if (N->getValueType(0) == MVT::i32)
1614 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1616 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1618 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1619 return isIntS16Immediate(Op.getNode(), Imm);
1623 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1624 /// can be represented as an indexed [r+r] operation. Returns false if it
1625 /// can be more efficiently represented with [r+imm].
1626 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1628 SelectionDAG &DAG) const {
1630 if (N.getOpcode() == ISD::ADD) {
1631 if (isIntS16Immediate(N.getOperand(1), imm))
1632 return false; // r+i
1633 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1634 return false; // r+i
1636 Base = N.getOperand(0);
1637 Index = N.getOperand(1);
1639 } else if (N.getOpcode() == ISD::OR) {
1640 if (isIntS16Immediate(N.getOperand(1), imm))
1641 return false; // r+i can fold it if we can.
1643 // If this is an or of disjoint bitfields, we can codegen this as an add
1644 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1646 APInt LHSKnownZero, LHSKnownOne;
1647 APInt RHSKnownZero, RHSKnownOne;
1648 DAG.computeKnownBits(N.getOperand(0),
1649 LHSKnownZero, LHSKnownOne);
1651 if (LHSKnownZero.getBoolValue()) {
1652 DAG.computeKnownBits(N.getOperand(1),
1653 RHSKnownZero, RHSKnownOne);
1654 // If all of the bits are known zero on the LHS or RHS, the add won't
1656 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1657 Base = N.getOperand(0);
1658 Index = N.getOperand(1);
1667 // If we happen to be doing an i64 load or store into a stack slot that has
1668 // less than a 4-byte alignment, then the frame-index elimination may need to
1669 // use an indexed load or store instruction (because the offset may not be a
1670 // multiple of 4). The extra register needed to hold the offset comes from the
1671 // register scavenger, and it is possible that the scavenger will need to use
1672 // an emergency spill slot. As a result, we need to make sure that a spill slot
1673 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1675 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1676 // FIXME: This does not handle the LWA case.
1680 // NOTE: We'll exclude negative FIs here, which come from argument
1681 // lowering, because there are no known test cases triggering this problem
1682 // using packed structures (or similar). We can remove this exclusion if
1683 // we find such a test case. The reason why this is so test-case driven is
1684 // because this entire 'fixup' is only to prevent crashes (from the
1685 // register scavenger) on not-really-valid inputs. For example, if we have:
1687 // %b = bitcast i1* %a to i64*
1688 // store i64* a, i64 b
1689 // then the store should really be marked as 'align 1', but is not. If it
1690 // were marked as 'align 1' then the indexed form would have been
1691 // instruction-selected initially, and the problem this 'fixup' is preventing
1692 // won't happen regardless.
1696 MachineFunction &MF = DAG.getMachineFunction();
1697 MachineFrameInfo *MFI = MF.getFrameInfo();
1699 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1703 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1704 FuncInfo->setHasNonRISpills();
1707 /// Returns true if the address N can be represented by a base register plus
1708 /// a signed 16-bit displacement [r+imm], and if it is not better
1709 /// represented as reg+reg. If Aligned is true, only accept displacements
1710 /// suitable for STD and friends, i.e. multiples of 4.
1711 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1714 bool Aligned) const {
1715 // FIXME dl should come from parent load or store, not from address
1717 // If this can be more profitably realized as r+r, fail.
1718 if (SelectAddressRegReg(N, Disp, Base, DAG))
1721 if (N.getOpcode() == ISD::ADD) {
1723 if (isIntS16Immediate(N.getOperand(1), imm) &&
1724 (!Aligned || (imm & 3) == 0)) {
1725 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
1726 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1727 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1728 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1730 Base = N.getOperand(0);
1732 return true; // [r+i]
1733 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1734 // Match LOAD (ADD (X, Lo(G))).
1735 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1736 && "Cannot handle constant offsets yet!");
1737 Disp = N.getOperand(1).getOperand(0); // The global address.
1738 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1739 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1740 Disp.getOpcode() == ISD::TargetConstantPool ||
1741 Disp.getOpcode() == ISD::TargetJumpTable);
1742 Base = N.getOperand(0);
1743 return true; // [&g+r]
1745 } else if (N.getOpcode() == ISD::OR) {
1747 if (isIntS16Immediate(N.getOperand(1), imm) &&
1748 (!Aligned || (imm & 3) == 0)) {
1749 // If this is an or of disjoint bitfields, we can codegen this as an add
1750 // (for better address arithmetic) if the LHS and RHS of the OR are
1751 // provably disjoint.
1752 APInt LHSKnownZero, LHSKnownOne;
1753 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1755 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1756 // If all of the bits are known zero on the LHS or RHS, the add won't
1758 if (FrameIndexSDNode *FI =
1759 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1760 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1761 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1763 Base = N.getOperand(0);
1765 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
1769 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1770 // Loading from a constant address.
1772 // If this address fits entirely in a 16-bit sext immediate field, codegen
1775 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1776 Disp = DAG.getTargetConstant(Imm, dl, CN->getValueType(0));
1777 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1778 CN->getValueType(0));
1782 // Handle 32-bit sext immediates with LIS + addr mode.
1783 if ((CN->getValueType(0) == MVT::i32 ||
1784 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1785 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1786 int Addr = (int)CN->getZExtValue();
1788 // Otherwise, break this down into an LIS + disp.
1789 Disp = DAG.getTargetConstant((short)Addr, dl, MVT::i32);
1791 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, dl,
1793 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1794 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1799 Disp = DAG.getTargetConstant(0, dl, getPointerTy());
1800 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1801 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1802 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1805 return true; // [r+0]
1808 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1809 /// represented as an indexed [r+r] operation.
1810 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1812 SelectionDAG &DAG) const {
1813 // Check to see if we can easily represent this as an [r+r] address. This
1814 // will fail if it thinks that the address is more profitably represented as
1815 // reg+imm, e.g. where imm = 0.
1816 if (SelectAddressRegReg(N, Base, Index, DAG))
1819 // If the operand is an addition, always emit this as [r+r], since this is
1820 // better (for code size, and execution, as the memop does the add for free)
1821 // than emitting an explicit add.
1822 if (N.getOpcode() == ISD::ADD) {
1823 Base = N.getOperand(0);
1824 Index = N.getOperand(1);
1828 // Otherwise, do it the hard way, using R0 as the base register.
1829 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1835 /// getPreIndexedAddressParts - returns true by value, base pointer and
1836 /// offset pointer and addressing mode by reference if the node's address
1837 /// can be legally represented as pre-indexed load / store address.
1838 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1840 ISD::MemIndexedMode &AM,
1841 SelectionDAG &DAG) const {
1842 if (DisablePPCPreinc) return false;
1848 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1849 Ptr = LD->getBasePtr();
1850 VT = LD->getMemoryVT();
1851 Alignment = LD->getAlignment();
1852 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1853 Ptr = ST->getBasePtr();
1854 VT = ST->getMemoryVT();
1855 Alignment = ST->getAlignment();
1860 // PowerPC doesn't have preinc load/store instructions for vectors (except
1861 // for QPX, which does have preinc r+r forms).
1862 if (VT.isVector()) {
1863 if (!Subtarget.hasQPX() || (VT != MVT::v4f64 && VT != MVT::v4f32)) {
1865 } else if (SelectAddressRegRegOnly(Ptr, Offset, Base, DAG)) {
1871 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1873 // Common code will reject creating a pre-inc form if the base pointer
1874 // is a frame index, or if N is a store and the base pointer is either
1875 // the same as or a predecessor of the value being stored. Check for
1876 // those situations here, and try with swapped Base/Offset instead.
1879 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1882 SDValue Val = cast<StoreSDNode>(N)->getValue();
1883 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1888 std::swap(Base, Offset);
1894 // LDU/STU can only handle immediates that are a multiple of 4.
1895 if (VT != MVT::i64) {
1896 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1899 // LDU/STU need an address with at least 4-byte alignment.
1903 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1907 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1908 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1909 // sext i32 to i64 when addr mode is r+i.
1910 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1911 LD->getExtensionType() == ISD::SEXTLOAD &&
1912 isa<ConstantSDNode>(Offset))
1920 //===----------------------------------------------------------------------===//
1921 // LowerOperation implementation
1922 //===----------------------------------------------------------------------===//
1924 /// GetLabelAccessInfo - Return true if we should reference labels using a
1925 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1926 static bool GetLabelAccessInfo(const TargetMachine &TM,
1927 const PPCSubtarget &Subtarget,
1928 unsigned &HiOpFlags, unsigned &LoOpFlags,
1929 const GlobalValue *GV = nullptr) {
1930 HiOpFlags = PPCII::MO_HA;
1931 LoOpFlags = PPCII::MO_LO;
1933 // Don't use the pic base if not in PIC relocation model.
1934 bool isPIC = TM.getRelocationModel() == Reloc::PIC_;
1937 HiOpFlags |= PPCII::MO_PIC_FLAG;
1938 LoOpFlags |= PPCII::MO_PIC_FLAG;
1941 // If this is a reference to a global value that requires a non-lazy-ptr, make
1942 // sure that instruction lowering adds it.
1943 if (GV && Subtarget.hasLazyResolverStub(GV)) {
1944 HiOpFlags |= PPCII::MO_NLP_FLAG;
1945 LoOpFlags |= PPCII::MO_NLP_FLAG;
1947 if (GV->hasHiddenVisibility()) {
1948 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1949 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1956 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1957 SelectionDAG &DAG) {
1959 EVT PtrVT = HiPart.getValueType();
1960 SDValue Zero = DAG.getConstant(0, DL, PtrVT);
1962 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1963 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1965 // With PIC, the first instruction is actually "GR+hi(&G)".
1967 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1968 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1970 // Generate non-pic code that has direct accesses to the constant pool.
1971 // The address of the global is just (hi(&g)+lo(&g)).
1972 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1975 static void setUsesTOCBasePtr(MachineFunction &MF) {
1976 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1977 FuncInfo->setUsesTOCBasePtr();
1980 static void setUsesTOCBasePtr(SelectionDAG &DAG) {
1981 setUsesTOCBasePtr(DAG.getMachineFunction());
1984 static SDValue getTOCEntry(SelectionDAG &DAG, SDLoc dl, bool Is64Bit,
1986 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1987 SDValue Reg = Is64Bit ? DAG.getRegister(PPC::X2, VT) :
1988 DAG.getNode(PPCISD::GlobalBaseReg, dl, VT);
1990 SDValue Ops[] = { GA, Reg };
1991 return DAG.getMemIntrinsicNode(PPCISD::TOC_ENTRY, dl,
1992 DAG.getVTList(VT, MVT::Other), Ops, VT,
1993 MachinePointerInfo::getGOT(), 0, false, true,
1997 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1998 SelectionDAG &DAG) const {
1999 EVT PtrVT = Op.getValueType();
2000 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2001 const Constant *C = CP->getConstVal();
2003 // 64-bit SVR4 ABI code is always position-independent.
2004 // The actual address of the GlobalValue is stored in the TOC.
2005 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2006 setUsesTOCBasePtr(DAG);
2007 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
2008 return getTOCEntry(DAG, SDLoc(CP), true, GA);
2011 unsigned MOHiFlag, MOLoFlag;
2013 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
2015 if (isPIC && Subtarget.isSVR4ABI()) {
2016 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
2017 PPCII::MO_PIC_FLAG);
2018 return getTOCEntry(DAG, SDLoc(CP), false, GA);
2022 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
2024 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
2025 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
2028 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
2029 EVT PtrVT = Op.getValueType();
2030 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
2032 // 64-bit SVR4 ABI code is always position-independent.
2033 // The actual address of the GlobalValue is stored in the TOC.
2034 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2035 setUsesTOCBasePtr(DAG);
2036 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
2037 return getTOCEntry(DAG, SDLoc(JT), true, GA);
2040 unsigned MOHiFlag, MOLoFlag;
2042 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
2044 if (isPIC && Subtarget.isSVR4ABI()) {
2045 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
2046 PPCII::MO_PIC_FLAG);
2047 return getTOCEntry(DAG, SDLoc(GA), false, GA);
2050 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
2051 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
2052 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
2055 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
2056 SelectionDAG &DAG) const {
2057 EVT PtrVT = Op.getValueType();
2058 BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
2059 const BlockAddress *BA = BASDN->getBlockAddress();
2061 // 64-bit SVR4 ABI code is always position-independent.
2062 // The actual BlockAddress is stored in the TOC.
2063 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2064 setUsesTOCBasePtr(DAG);
2065 SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
2066 return getTOCEntry(DAG, SDLoc(BASDN), true, GA);
2069 unsigned MOHiFlag, MOLoFlag;
2071 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
2072 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
2073 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
2074 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
2077 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
2078 SelectionDAG &DAG) const {
2080 // FIXME: TLS addresses currently use medium model code sequences,
2081 // which is the most useful form. Eventually support for small and
2082 // large models could be added if users need it, at the cost of
2083 // additional complexity.
2084 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2086 const GlobalValue *GV = GA->getGlobal();
2087 EVT PtrVT = getPointerTy();
2088 bool is64bit = Subtarget.isPPC64();
2089 const Module *M = DAG.getMachineFunction().getFunction()->getParent();
2090 PICLevel::Level picLevel = M->getPICLevel();
2092 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
2094 if (Model == TLSModel::LocalExec) {
2095 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2096 PPCII::MO_TPREL_HA);
2097 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2098 PPCII::MO_TPREL_LO);
2099 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
2100 is64bit ? MVT::i64 : MVT::i32);
2101 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
2102 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
2105 if (Model == TLSModel::InitialExec) {
2106 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2107 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2111 setUsesTOCBasePtr(DAG);
2112 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2113 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
2114 PtrVT, GOTReg, TGA);
2116 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
2117 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
2118 PtrVT, TGA, GOTPtr);
2119 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
2122 if (Model == TLSModel::GeneralDynamic) {
2123 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2126 setUsesTOCBasePtr(DAG);
2127 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2128 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
2131 if (picLevel == PICLevel::Small)
2132 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
2134 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
2136 return DAG.getNode(PPCISD::ADDI_TLSGD_L_ADDR, dl, PtrVT,
2140 if (Model == TLSModel::LocalDynamic) {
2141 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2144 setUsesTOCBasePtr(DAG);
2145 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2146 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
2149 if (picLevel == PICLevel::Small)
2150 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
2152 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
2154 SDValue TLSAddr = DAG.getNode(PPCISD::ADDI_TLSLD_L_ADDR, dl,
2155 PtrVT, GOTPtr, TGA, TGA);
2156 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl,
2157 PtrVT, TLSAddr, TGA);
2158 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
2161 llvm_unreachable("Unknown TLS model!");
2164 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
2165 SelectionDAG &DAG) const {
2166 EVT PtrVT = Op.getValueType();
2167 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
2169 const GlobalValue *GV = GSDN->getGlobal();
2171 // 64-bit SVR4 ABI code is always position-independent.
2172 // The actual address of the GlobalValue is stored in the TOC.
2173 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2174 setUsesTOCBasePtr(DAG);
2175 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
2176 return getTOCEntry(DAG, DL, true, GA);
2179 unsigned MOHiFlag, MOLoFlag;
2181 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag, GV);
2183 if (isPIC && Subtarget.isSVR4ABI()) {
2184 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
2186 PPCII::MO_PIC_FLAG);
2187 return getTOCEntry(DAG, DL, false, GA);
2191 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
2193 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
2195 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
2197 // If the global reference is actually to a non-lazy-pointer, we have to do an
2198 // extra load to get the address of the global.
2199 if (MOHiFlag & PPCII::MO_NLP_FLAG)
2200 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
2201 false, false, false, 0);
2205 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
2206 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2209 if (Op.getValueType() == MVT::v2i64) {
2210 // When the operands themselves are v2i64 values, we need to do something
2211 // special because VSX has no underlying comparison operations for these.
2212 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
2213 // Equality can be handled by casting to the legal type for Altivec
2214 // comparisons, everything else needs to be expanded.
2215 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
2216 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
2217 DAG.getSetCC(dl, MVT::v4i32,
2218 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
2219 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
2226 // We handle most of these in the usual way.
2230 // If we're comparing for equality to zero, expose the fact that this is
2231 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
2232 // fold the new nodes.
2233 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
2234 if (C->isNullValue() && CC == ISD::SETEQ) {
2235 EVT VT = Op.getOperand(0).getValueType();
2236 SDValue Zext = Op.getOperand(0);
2237 if (VT.bitsLT(MVT::i32)) {
2239 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
2241 unsigned Log2b = Log2_32(VT.getSizeInBits());
2242 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
2243 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
2244 DAG.getConstant(Log2b, dl, MVT::i32));
2245 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
2247 // Leave comparisons against 0 and -1 alone for now, since they're usually
2248 // optimized. FIXME: revisit this when we can custom lower all setcc
2250 if (C->isAllOnesValue() || C->isNullValue())
2254 // If we have an integer seteq/setne, turn it into a compare against zero
2255 // by xor'ing the rhs with the lhs, which is faster than setting a
2256 // condition register, reading it back out, and masking the correct bit. The
2257 // normal approach here uses sub to do this instead of xor. Using xor exposes
2258 // the result to other bit-twiddling opportunities.
2259 EVT LHSVT = Op.getOperand(0).getValueType();
2260 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
2261 EVT VT = Op.getValueType();
2262 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
2264 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, dl, LHSVT), CC);
2269 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
2270 const PPCSubtarget &Subtarget) const {
2271 SDNode *Node = Op.getNode();
2272 EVT VT = Node->getValueType(0);
2273 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2274 SDValue InChain = Node->getOperand(0);
2275 SDValue VAListPtr = Node->getOperand(1);
2276 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2279 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
2282 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
2283 VAListPtr, MachinePointerInfo(SV), MVT::i8,
2284 false, false, false, 0);
2285 InChain = GprIndex.getValue(1);
2287 if (VT == MVT::i64) {
2288 // Check if GprIndex is even
2289 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
2290 DAG.getConstant(1, dl, MVT::i32));
2291 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
2292 DAG.getConstant(0, dl, MVT::i32), ISD::SETNE);
2293 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
2294 DAG.getConstant(1, dl, MVT::i32));
2295 // Align GprIndex to be even if it isn't
2296 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
2300 // fpr index is 1 byte after gpr
2301 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2302 DAG.getConstant(1, dl, MVT::i32));
2305 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
2306 FprPtr, MachinePointerInfo(SV), MVT::i8,
2307 false, false, false, 0);
2308 InChain = FprIndex.getValue(1);
2310 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2311 DAG.getConstant(8, dl, MVT::i32));
2313 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2314 DAG.getConstant(4, dl, MVT::i32));
2317 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
2318 MachinePointerInfo(), false, false,
2320 InChain = OverflowArea.getValue(1);
2322 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
2323 MachinePointerInfo(), false, false,
2325 InChain = RegSaveArea.getValue(1);
2327 // select overflow_area if index > 8
2328 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
2329 DAG.getConstant(8, dl, MVT::i32), ISD::SETLT);
2331 // adjustment constant gpr_index * 4/8
2332 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
2333 VT.isInteger() ? GprIndex : FprIndex,
2334 DAG.getConstant(VT.isInteger() ? 4 : 8, dl,
2337 // OurReg = RegSaveArea + RegConstant
2338 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
2341 // Floating types are 32 bytes into RegSaveArea
2342 if (VT.isFloatingPoint())
2343 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
2344 DAG.getConstant(32, dl, MVT::i32));
2346 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
2347 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
2348 VT.isInteger() ? GprIndex : FprIndex,
2349 DAG.getConstant(VT == MVT::i64 ? 2 : 1, dl,
2352 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
2353 VT.isInteger() ? VAListPtr : FprPtr,
2354 MachinePointerInfo(SV),
2355 MVT::i8, false, false, 0);
2357 // determine if we should load from reg_save_area or overflow_area
2358 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
2360 // increase overflow_area by 4/8 if gpr/fpr > 8
2361 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
2362 DAG.getConstant(VT.isInteger() ? 4 : 8,
2365 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
2368 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
2370 MachinePointerInfo(),
2371 MVT::i32, false, false, 0);
2373 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
2374 false, false, false, 0);
2377 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
2378 const PPCSubtarget &Subtarget) const {
2379 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
2381 // We have to copy the entire va_list struct:
2382 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
2383 return DAG.getMemcpy(Op.getOperand(0), Op,
2384 Op.getOperand(1), Op.getOperand(2),
2385 DAG.getConstant(12, SDLoc(Op), MVT::i32), 8, false, true,
2386 false, MachinePointerInfo(), MachinePointerInfo());
2389 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
2390 SelectionDAG &DAG) const {
2391 return Op.getOperand(0);
2394 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
2395 SelectionDAG &DAG) const {
2396 SDValue Chain = Op.getOperand(0);
2397 SDValue Trmp = Op.getOperand(1); // trampoline
2398 SDValue FPtr = Op.getOperand(2); // nested function
2399 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
2402 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2403 bool isPPC64 = (PtrVT == MVT::i64);
2405 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
2408 TargetLowering::ArgListTy Args;
2409 TargetLowering::ArgListEntry Entry;
2411 Entry.Ty = IntPtrTy;
2412 Entry.Node = Trmp; Args.push_back(Entry);
2414 // TrampSize == (isPPC64 ? 48 : 40);
2415 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, dl,
2416 isPPC64 ? MVT::i64 : MVT::i32);
2417 Args.push_back(Entry);
2419 Entry.Node = FPtr; Args.push_back(Entry);
2420 Entry.Node = Nest; Args.push_back(Entry);
2422 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
2423 TargetLowering::CallLoweringInfo CLI(DAG);
2424 CLI.setDebugLoc(dl).setChain(Chain)
2425 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
2426 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
2427 std::move(Args), 0);
2429 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2430 return CallResult.second;
2433 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
2434 const PPCSubtarget &Subtarget) const {
2435 MachineFunction &MF = DAG.getMachineFunction();
2436 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2440 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
2441 // vastart just stores the address of the VarArgsFrameIndex slot into the
2442 // memory location argument.
2443 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2444 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2445 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2446 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2447 MachinePointerInfo(SV),
2451 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
2452 // We suppose the given va_list is already allocated.
2455 // char gpr; /* index into the array of 8 GPRs
2456 // * stored in the register save area
2457 // * gpr=0 corresponds to r3,
2458 // * gpr=1 to r4, etc.
2460 // char fpr; /* index into the array of 8 FPRs
2461 // * stored in the register save area
2462 // * fpr=0 corresponds to f1,
2463 // * fpr=1 to f2, etc.
2465 // char *overflow_arg_area;
2466 // /* location on stack that holds
2467 // * the next overflow argument
2469 // char *reg_save_area;
2470 // /* where r3:r10 and f1:f8 (if saved)
2476 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), dl, MVT::i32);
2477 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), dl, MVT::i32);
2480 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2482 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
2484 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2487 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2488 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, dl, PtrVT);
2490 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2491 SDValue ConstStackOffset = DAG.getConstant(StackOffset, dl, PtrVT);
2493 uint64_t FPROffset = 1;
2494 SDValue ConstFPROffset = DAG.getConstant(FPROffset, dl, PtrVT);
2496 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2498 // Store first byte : number of int regs
2499 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
2501 MachinePointerInfo(SV),
2502 MVT::i8, false, false, 0);
2503 uint64_t nextOffset = FPROffset;
2504 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2507 // Store second byte : number of float regs
2508 SDValue secondStore =
2509 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2510 MachinePointerInfo(SV, nextOffset), MVT::i8,
2512 nextOffset += StackOffset;
2513 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2515 // Store second word : arguments given on stack
2516 SDValue thirdStore =
2517 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2518 MachinePointerInfo(SV, nextOffset),
2520 nextOffset += FrameOffset;
2521 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2523 // Store third word : arguments given in registers
2524 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2525 MachinePointerInfo(SV, nextOffset),
2530 #include "PPCGenCallingConv.inc"
2532 // Function whose sole purpose is to kill compiler warnings
2533 // stemming from unused functions included from PPCGenCallingConv.inc.
2534 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2535 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2538 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2539 CCValAssign::LocInfo &LocInfo,
2540 ISD::ArgFlagsTy &ArgFlags,
2545 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2547 CCValAssign::LocInfo &LocInfo,
2548 ISD::ArgFlagsTy &ArgFlags,
2550 static const MCPhysReg ArgRegs[] = {
2551 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2552 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2554 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2556 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
2558 // Skip one register if the first unallocated register has an even register
2559 // number and there are still argument registers available which have not been
2560 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2561 // need to skip a register if RegNum is odd.
2562 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2563 State.AllocateReg(ArgRegs[RegNum]);
2566 // Always return false here, as this function only makes sure that the first
2567 // unallocated register has an odd register number and does not actually
2568 // allocate a register for the current argument.
2572 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2574 CCValAssign::LocInfo &LocInfo,
2575 ISD::ArgFlagsTy &ArgFlags,
2577 static const MCPhysReg ArgRegs[] = {
2578 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2582 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2584 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
2586 // If there is only one Floating-point register left we need to put both f64
2587 // values of a split ppc_fp128 value on the stack.
2588 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2589 State.AllocateReg(ArgRegs[RegNum]);
2592 // Always return false here, as this function only makes sure that the two f64
2593 // values a ppc_fp128 value is split into are both passed in registers or both
2594 // passed on the stack and does not actually allocate a register for the
2595 // current argument.
2599 /// FPR - The set of FP registers that should be allocated for arguments,
2601 static const MCPhysReg FPR[] = {PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5,
2602 PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10,
2603 PPC::F11, PPC::F12, PPC::F13};
2605 /// QFPR - The set of QPX registers that should be allocated for arguments.
2606 static const MCPhysReg QFPR[] = {
2607 PPC::QF1, PPC::QF2, PPC::QF3, PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7,
2608 PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11, PPC::QF12, PPC::QF13};
2610 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2612 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2613 unsigned PtrByteSize) {
2614 unsigned ArgSize = ArgVT.getStoreSize();
2615 if (Flags.isByVal())
2616 ArgSize = Flags.getByValSize();
2618 // Round up to multiples of the pointer size, except for array members,
2619 // which are always packed.
2620 if (!Flags.isInConsecutiveRegs())
2621 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2626 /// CalculateStackSlotAlignment - Calculates the alignment of this argument
2628 static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
2629 ISD::ArgFlagsTy Flags,
2630 unsigned PtrByteSize) {
2631 unsigned Align = PtrByteSize;
2633 // Altivec parameters are padded to a 16 byte boundary.
2634 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2635 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2636 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
2637 ArgVT == MVT::v1i128)
2639 // QPX vector types stored in double-precision are padded to a 32 byte
2641 else if (ArgVT == MVT::v4f64 || ArgVT == MVT::v4i1)
2644 // ByVal parameters are aligned as requested.
2645 if (Flags.isByVal()) {
2646 unsigned BVAlign = Flags.getByValAlign();
2647 if (BVAlign > PtrByteSize) {
2648 if (BVAlign % PtrByteSize != 0)
2650 "ByVal alignment is not a multiple of the pointer size");
2656 // Array members are always packed to their original alignment.
2657 if (Flags.isInConsecutiveRegs()) {
2658 // If the array member was split into multiple registers, the first
2659 // needs to be aligned to the size of the full type. (Except for
2660 // ppcf128, which is only aligned as its f64 components.)
2661 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
2662 Align = OrigVT.getStoreSize();
2664 Align = ArgVT.getStoreSize();
2670 /// CalculateStackSlotUsed - Return whether this argument will use its
2671 /// stack slot (instead of being passed in registers). ArgOffset,
2672 /// AvailableFPRs, and AvailableVRs must hold the current argument
2673 /// position, and will be updated to account for this argument.
2674 static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT,
2675 ISD::ArgFlagsTy Flags,
2676 unsigned PtrByteSize,
2677 unsigned LinkageSize,
2678 unsigned ParamAreaSize,
2679 unsigned &ArgOffset,
2680 unsigned &AvailableFPRs,
2681 unsigned &AvailableVRs, bool HasQPX) {
2682 bool UseMemory = false;
2684 // Respect alignment of argument on the stack.
2686 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
2687 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2688 // If there's no space left in the argument save area, we must
2689 // use memory (this check also catches zero-sized arguments).
2690 if (ArgOffset >= LinkageSize + ParamAreaSize)
2693 // Allocate argument on the stack.
2694 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2695 if (Flags.isInConsecutiveRegsLast())
2696 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2697 // If we overran the argument save area, we must use memory
2698 // (this check catches arguments passed partially in memory)
2699 if (ArgOffset > LinkageSize + ParamAreaSize)
2702 // However, if the argument is actually passed in an FPR or a VR,
2703 // we don't use memory after all.
2704 if (!Flags.isByVal()) {
2705 if (ArgVT == MVT::f32 || ArgVT == MVT::f64 ||
2706 // QPX registers overlap with the scalar FP registers.
2707 (HasQPX && (ArgVT == MVT::v4f32 ||
2708 ArgVT == MVT::v4f64 ||
2709 ArgVT == MVT::v4i1)))
2710 if (AvailableFPRs > 0) {
2714 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2715 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2716 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
2717 ArgVT == MVT::v1i128)
2718 if (AvailableVRs > 0) {
2727 /// EnsureStackAlignment - Round stack frame size up from NumBytes to
2728 /// ensure minimum alignment required for target.
2729 static unsigned EnsureStackAlignment(const PPCFrameLowering *Lowering,
2730 unsigned NumBytes) {
2731 unsigned TargetAlign = Lowering->getStackAlignment();
2732 unsigned AlignMask = TargetAlign - 1;
2733 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2738 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
2739 CallingConv::ID CallConv, bool isVarArg,
2740 const SmallVectorImpl<ISD::InputArg>
2742 SDLoc dl, SelectionDAG &DAG,
2743 SmallVectorImpl<SDValue> &InVals)
2745 if (Subtarget.isSVR4ABI()) {
2746 if (Subtarget.isPPC64())
2747 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2750 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2753 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2759 PPCTargetLowering::LowerFormalArguments_32SVR4(
2761 CallingConv::ID CallConv, bool isVarArg,
2762 const SmallVectorImpl<ISD::InputArg>
2764 SDLoc dl, SelectionDAG &DAG,
2765 SmallVectorImpl<SDValue> &InVals) const {
2767 // 32-bit SVR4 ABI Stack Frame Layout:
2768 // +-----------------------------------+
2769 // +--> | Back chain |
2770 // | +-----------------------------------+
2771 // | | Floating-point register save area |
2772 // | +-----------------------------------+
2773 // | | General register save area |
2774 // | +-----------------------------------+
2775 // | | CR save word |
2776 // | +-----------------------------------+
2777 // | | VRSAVE save word |
2778 // | +-----------------------------------+
2779 // | | Alignment padding |
2780 // | +-----------------------------------+
2781 // | | Vector register save area |
2782 // | +-----------------------------------+
2783 // | | Local variable space |
2784 // | +-----------------------------------+
2785 // | | Parameter list area |
2786 // | +-----------------------------------+
2787 // | | LR save word |
2788 // | +-----------------------------------+
2789 // SP--> +--- | Back chain |
2790 // +-----------------------------------+
2793 // System V Application Binary Interface PowerPC Processor Supplement
2794 // AltiVec Technology Programming Interface Manual
2796 MachineFunction &MF = DAG.getMachineFunction();
2797 MachineFrameInfo *MFI = MF.getFrameInfo();
2798 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2800 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2801 // Potential tail calls could cause overwriting of argument stack slots.
2802 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2803 (CallConv == CallingConv::Fast));
2804 unsigned PtrByteSize = 4;
2806 // Assign locations to all of the incoming arguments.
2807 SmallVector<CCValAssign, 16> ArgLocs;
2808 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2811 // Reserve space for the linkage area on the stack.
2812 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
2813 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
2815 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2817 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2818 CCValAssign &VA = ArgLocs[i];
2820 // Arguments stored in registers.
2821 if (VA.isRegLoc()) {
2822 const TargetRegisterClass *RC;
2823 EVT ValVT = VA.getValVT();
2825 switch (ValVT.getSimpleVT().SimpleTy) {
2827 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2830 RC = &PPC::GPRCRegClass;
2833 if (Subtarget.hasP8Vector())
2834 RC = &PPC::VSSRCRegClass;
2836 RC = &PPC::F4RCRegClass;
2839 if (Subtarget.hasVSX())
2840 RC = &PPC::VSFRCRegClass;
2842 RC = &PPC::F8RCRegClass;
2847 RC = &PPC::VRRCRegClass;
2850 RC = Subtarget.hasQPX() ? &PPC::QSRCRegClass : &PPC::VRRCRegClass;
2854 RC = &PPC::VSHRCRegClass;
2857 RC = &PPC::QFRCRegClass;
2860 RC = &PPC::QBRCRegClass;
2864 // Transform the arguments stored in physical registers into virtual ones.
2865 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2866 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2867 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2869 if (ValVT == MVT::i1)
2870 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2872 InVals.push_back(ArgValue);
2874 // Argument stored in memory.
2875 assert(VA.isMemLoc());
2877 unsigned ArgSize = VA.getLocVT().getStoreSize();
2878 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2881 // Create load nodes to retrieve arguments from the stack.
2882 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2883 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2884 MachinePointerInfo(),
2885 false, false, false, 0));
2889 // Assign locations to all of the incoming aggregate by value arguments.
2890 // Aggregates passed by value are stored in the local variable space of the
2891 // caller's stack frame, right above the parameter list area.
2892 SmallVector<CCValAssign, 16> ByValArgLocs;
2893 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2894 ByValArgLocs, *DAG.getContext());
2896 // Reserve stack space for the allocations in CCInfo.
2897 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2899 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2901 // Area that is at least reserved in the caller of this function.
2902 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2903 MinReservedArea = std::max(MinReservedArea, LinkageSize);
2905 // Set the size that is at least reserved in caller of this function. Tail
2906 // call optimized function's reserved stack space needs to be aligned so that
2907 // taking the difference between two stack areas will result in an aligned
2910 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
2911 FuncInfo->setMinReservedArea(MinReservedArea);
2913 SmallVector<SDValue, 8> MemOps;
2915 // If the function takes variable number of arguments, make a frame index for
2916 // the start of the first vararg value... for expansion of llvm.va_start.
2918 static const MCPhysReg GPArgRegs[] = {
2919 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2920 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2922 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2924 static const MCPhysReg FPArgRegs[] = {
2925 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2928 unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2929 if (DisablePPCFloatInVariadic)
2932 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs));
2933 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs));
2935 // Make room for NumGPArgRegs and NumFPArgRegs.
2936 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2937 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8;
2939 FuncInfo->setVarArgsStackOffset(
2940 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2941 CCInfo.getNextStackOffset(), true));
2943 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2944 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2946 // The fixed integer arguments of a variadic function are stored to the
2947 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2948 // the result of va_next.
2949 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2950 // Get an existing live-in vreg, or add a new one.
2951 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2953 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2955 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2956 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2957 MachinePointerInfo(), false, false, 0);
2958 MemOps.push_back(Store);
2959 // Increment the address by four for the next argument to store
2960 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
2961 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2964 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2966 // The double arguments are stored to the VarArgsFrameIndex
2968 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2969 // Get an existing live-in vreg, or add a new one.
2970 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2972 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2974 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2975 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2976 MachinePointerInfo(), false, false, 0);
2977 MemOps.push_back(Store);
2978 // Increment the address by eight for the next argument to store
2979 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, dl,
2981 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2985 if (!MemOps.empty())
2986 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2991 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2992 // value to MVT::i64 and then truncate to the correct register size.
2994 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2995 SelectionDAG &DAG, SDValue ArgVal,
2998 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2999 DAG.getValueType(ObjectVT));
3000 else if (Flags.isZExt())
3001 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
3002 DAG.getValueType(ObjectVT));
3004 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
3008 PPCTargetLowering::LowerFormalArguments_64SVR4(
3010 CallingConv::ID CallConv, bool isVarArg,
3011 const SmallVectorImpl<ISD::InputArg>
3013 SDLoc dl, SelectionDAG &DAG,
3014 SmallVectorImpl<SDValue> &InVals) const {
3015 // TODO: add description of PPC stack frame format, or at least some docs.
3017 bool isELFv2ABI = Subtarget.isELFv2ABI();
3018 bool isLittleEndian = Subtarget.isLittleEndian();
3019 MachineFunction &MF = DAG.getMachineFunction();
3020 MachineFrameInfo *MFI = MF.getFrameInfo();
3021 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3023 assert(!(CallConv == CallingConv::Fast && isVarArg) &&
3024 "fastcc not supported on varargs functions");
3026 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3027 // Potential tail calls could cause overwriting of argument stack slots.
3028 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3029 (CallConv == CallingConv::Fast));
3030 unsigned PtrByteSize = 8;
3031 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3033 static const MCPhysReg GPR[] = {
3034 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3035 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3037 static const MCPhysReg VR[] = {
3038 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3039 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3041 static const MCPhysReg VSRH[] = {
3042 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
3043 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
3046 const unsigned Num_GPR_Regs = array_lengthof(GPR);
3047 const unsigned Num_FPR_Regs = 13;
3048 const unsigned Num_VR_Regs = array_lengthof(VR);
3049 const unsigned Num_QFPR_Regs = Num_FPR_Regs;
3051 // Do a first pass over the arguments to determine whether the ABI
3052 // guarantees that our caller has allocated the parameter save area
3053 // on its stack frame. In the ELFv1 ABI, this is always the case;
3054 // in the ELFv2 ABI, it is true if this is a vararg function or if
3055 // any parameter is located in a stack slot.
3057 bool HasParameterArea = !isELFv2ABI || isVarArg;
3058 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
3059 unsigned NumBytes = LinkageSize;
3060 unsigned AvailableFPRs = Num_FPR_Regs;
3061 unsigned AvailableVRs = Num_VR_Regs;
3062 for (unsigned i = 0, e = Ins.size(); i != e; ++i)
3063 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
3064 PtrByteSize, LinkageSize, ParamAreaSize,
3065 NumBytes, AvailableFPRs, AvailableVRs,
3066 Subtarget.hasQPX()))
3067 HasParameterArea = true;
3069 // Add DAG nodes to load the arguments or copy them out of registers. On
3070 // entry to a function on PPC, the arguments start after the linkage area,
3071 // although the first ones are often in registers.
3073 unsigned ArgOffset = LinkageSize;
3074 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3075 unsigned &QFPR_idx = FPR_idx;
3076 SmallVector<SDValue, 8> MemOps;
3077 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3078 unsigned CurArgIdx = 0;
3079 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3081 bool needsLoad = false;
3082 EVT ObjectVT = Ins[ArgNo].VT;
3083 EVT OrigVT = Ins[ArgNo].ArgVT;
3084 unsigned ObjSize = ObjectVT.getStoreSize();
3085 unsigned ArgSize = ObjSize;
3086 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3087 if (Ins[ArgNo].isOrigArg()) {
3088 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
3089 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
3091 // We re-align the argument offset for each argument, except when using the
3092 // fast calling convention, when we need to make sure we do that only when
3093 // we'll actually use a stack slot.
3094 unsigned CurArgOffset, Align;
3095 auto ComputeArgOffset = [&]() {
3096 /* Respect alignment of argument on the stack. */
3097 Align = CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
3098 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
3099 CurArgOffset = ArgOffset;
3102 if (CallConv != CallingConv::Fast) {
3105 /* Compute GPR index associated with argument offset. */
3106 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
3107 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
3110 // FIXME the codegen can be much improved in some cases.
3111 // We do not have to keep everything in memory.
3112 if (Flags.isByVal()) {
3113 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit");
3115 if (CallConv == CallingConv::Fast)
3118 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3119 ObjSize = Flags.getByValSize();
3120 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3121 // Empty aggregate parameters do not take up registers. Examples:
3125 // etc. However, we have to provide a place-holder in InVals, so
3126 // pretend we have an 8-byte item at the current address for that
3129 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3130 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3131 InVals.push_back(FIN);
3135 // Create a stack object covering all stack doublewords occupied
3136 // by the argument. If the argument is (fully or partially) on
3137 // the stack, or if the argument is fully in registers but the
3138 // caller has allocated the parameter save anyway, we can refer
3139 // directly to the caller's stack frame. Otherwise, create a
3140 // local copy in our own frame.
3142 if (HasParameterArea ||
3143 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
3144 FI = MFI->CreateFixedObject(ArgSize, ArgOffset, false, true);
3146 FI = MFI->CreateStackObject(ArgSize, Align, false);
3147 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3149 // Handle aggregates smaller than 8 bytes.
3150 if (ObjSize < PtrByteSize) {
3151 // The value of the object is its address, which differs from the
3152 // address of the enclosing doubleword on big-endian systems.
3154 if (!isLittleEndian) {
3155 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, dl, PtrVT);
3156 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
3158 InVals.push_back(Arg);
3160 if (GPR_idx != Num_GPR_Regs) {
3161 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3162 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3165 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
3166 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
3167 (ObjSize == 2 ? MVT::i16 : MVT::i32));
3168 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
3169 MachinePointerInfo(FuncArg),
3170 ObjType, false, false, 0);
3172 // For sizes that don't fit a truncating store (3, 5, 6, 7),
3173 // store the whole register as-is to the parameter save area
3175 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3176 MachinePointerInfo(FuncArg),
3180 MemOps.push_back(Store);
3182 // Whether we copied from a register or not, advance the offset
3183 // into the parameter save area by a full doubleword.
3184 ArgOffset += PtrByteSize;
3188 // The value of the object is its address, which is the address of
3189 // its first stack doubleword.
3190 InVals.push_back(FIN);
3192 // Store whatever pieces of the object are in registers to memory.
3193 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3194 if (GPR_idx == Num_GPR_Regs)
3197 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3198 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3201 SDValue Off = DAG.getConstant(j, dl, PtrVT);
3202 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
3204 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
3205 MachinePointerInfo(FuncArg, j),
3207 MemOps.push_back(Store);
3210 ArgOffset += ArgSize;
3214 switch (ObjectVT.getSimpleVT().SimpleTy) {
3215 default: llvm_unreachable("Unhandled argument type!");
3219 // These can be scalar arguments or elements of an integer array type
3220 // passed directly. Clang may use those instead of "byval" aggregate
3221 // types to avoid forcing arguments to memory unnecessarily.
3222 if (GPR_idx != Num_GPR_Regs) {
3223 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3224 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3226 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3227 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3228 // value to MVT::i64 and then truncate to the correct register size.
3229 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3231 if (CallConv == CallingConv::Fast)
3235 ArgSize = PtrByteSize;
3237 if (CallConv != CallingConv::Fast || needsLoad)
3243 // These can be scalar arguments or elements of a float array type
3244 // passed directly. The latter are used to implement ELFv2 homogenous
3245 // float aggregates.
3246 if (FPR_idx != Num_FPR_Regs) {
3249 if (ObjectVT == MVT::f32)
3250 VReg = MF.addLiveIn(FPR[FPR_idx],
3251 Subtarget.hasP8Vector()
3252 ? &PPC::VSSRCRegClass
3253 : &PPC::F4RCRegClass);
3255 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX()
3256 ? &PPC::VSFRCRegClass
3257 : &PPC::F8RCRegClass);
3259 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3261 } else if (GPR_idx != Num_GPR_Regs && CallConv != CallingConv::Fast) {
3262 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
3263 // once we support fp <-> gpr moves.
3265 // This can only ever happen in the presence of f32 array types,
3266 // since otherwise we never run out of FPRs before running out
3268 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3269 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3271 if (ObjectVT == MVT::f32) {
3272 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
3273 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
3274 DAG.getConstant(32, dl, MVT::i32));
3275 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
3278 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
3280 if (CallConv == CallingConv::Fast)
3286 // When passing an array of floats, the array occupies consecutive
3287 // space in the argument area; only round up to the next doubleword
3288 // at the end of the array. Otherwise, each float takes 8 bytes.
3289 if (CallConv != CallingConv::Fast || needsLoad) {
3290 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
3291 ArgOffset += ArgSize;
3292 if (Flags.isInConsecutiveRegsLast())
3293 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3303 if (!Subtarget.hasQPX()) {
3304 // These can be scalar arguments or elements of a vector array type
3305 // passed directly. The latter are used to implement ELFv2 homogenous
3306 // vector aggregates.
3307 if (VR_idx != Num_VR_Regs) {
3308 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
3309 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
3310 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3311 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3314 if (CallConv == CallingConv::Fast)
3319 if (CallConv != CallingConv::Fast || needsLoad)
3324 assert(ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 &&
3325 "Invalid QPX parameter type");
3330 // QPX vectors are treated like their scalar floating-point subregisters
3331 // (except that they're larger).
3332 unsigned Sz = ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 ? 16 : 32;
3333 if (QFPR_idx != Num_QFPR_Regs) {
3334 const TargetRegisterClass *RC;
3335 switch (ObjectVT.getSimpleVT().SimpleTy) {
3336 case MVT::v4f64: RC = &PPC::QFRCRegClass; break;
3337 case MVT::v4f32: RC = &PPC::QSRCRegClass; break;
3338 default: RC = &PPC::QBRCRegClass; break;
3341 unsigned VReg = MF.addLiveIn(QFPR[QFPR_idx], RC);
3342 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3345 if (CallConv == CallingConv::Fast)
3349 if (CallConv != CallingConv::Fast || needsLoad)
3354 // We need to load the argument to a virtual register if we determined
3355 // above that we ran out of physical registers of the appropriate type.
3357 if (ObjSize < ArgSize && !isLittleEndian)
3358 CurArgOffset += ArgSize - ObjSize;
3359 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
3360 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3361 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3362 false, false, false, 0);
3365 InVals.push_back(ArgVal);
3368 // Area that is at least reserved in the caller of this function.
3369 unsigned MinReservedArea;
3370 if (HasParameterArea)
3371 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
3373 MinReservedArea = LinkageSize;
3375 // Set the size that is at least reserved in caller of this function. Tail
3376 // call optimized functions' reserved stack space needs to be aligned so that
3377 // taking the difference between two stack areas will result in an aligned
3380 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3381 FuncInfo->setMinReservedArea(MinReservedArea);
3383 // If the function takes variable number of arguments, make a frame index for
3384 // the start of the first vararg value... for expansion of llvm.va_start.
3386 int Depth = ArgOffset;
3388 FuncInfo->setVarArgsFrameIndex(
3389 MFI->CreateFixedObject(PtrByteSize, Depth, true));
3390 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3392 // If this function is vararg, store any remaining integer argument regs
3393 // to their spots on the stack so that they may be loaded by deferencing the
3394 // result of va_next.
3395 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
3396 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
3397 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3398 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3399 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3400 MachinePointerInfo(), false, false, 0);
3401 MemOps.push_back(Store);
3402 // Increment the address by four for the next argument to store
3403 SDValue PtrOff = DAG.getConstant(PtrByteSize, dl, PtrVT);
3404 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3408 if (!MemOps.empty())
3409 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3415 PPCTargetLowering::LowerFormalArguments_Darwin(
3417 CallingConv::ID CallConv, bool isVarArg,
3418 const SmallVectorImpl<ISD::InputArg>
3420 SDLoc dl, SelectionDAG &DAG,
3421 SmallVectorImpl<SDValue> &InVals) const {
3422 // TODO: add description of PPC stack frame format, or at least some docs.
3424 MachineFunction &MF = DAG.getMachineFunction();
3425 MachineFrameInfo *MFI = MF.getFrameInfo();
3426 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3428 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3429 bool isPPC64 = PtrVT == MVT::i64;
3430 // Potential tail calls could cause overwriting of argument stack slots.
3431 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3432 (CallConv == CallingConv::Fast));
3433 unsigned PtrByteSize = isPPC64 ? 8 : 4;
3434 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3435 unsigned ArgOffset = LinkageSize;
3436 // Area that is at least reserved in caller of this function.
3437 unsigned MinReservedArea = ArgOffset;
3439 static const MCPhysReg GPR_32[] = { // 32-bit registers.
3440 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3441 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3443 static const MCPhysReg GPR_64[] = { // 64-bit registers.
3444 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3445 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3447 static const MCPhysReg VR[] = {
3448 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3449 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3452 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
3453 const unsigned Num_FPR_Regs = 13;
3454 const unsigned Num_VR_Regs = array_lengthof( VR);
3456 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3458 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
3460 // In 32-bit non-varargs functions, the stack space for vectors is after the
3461 // stack space for non-vectors. We do not use this space unless we have
3462 // too many vectors to fit in registers, something that only occurs in
3463 // constructed examples:), but we have to walk the arglist to figure
3464 // that out...for the pathological case, compute VecArgOffset as the
3465 // start of the vector parameter area. Computing VecArgOffset is the
3466 // entire point of the following loop.
3467 unsigned VecArgOffset = ArgOffset;
3468 if (!isVarArg && !isPPC64) {
3469 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
3471 EVT ObjectVT = Ins[ArgNo].VT;
3472 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3474 if (Flags.isByVal()) {
3475 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
3476 unsigned ObjSize = Flags.getByValSize();
3478 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3479 VecArgOffset += ArgSize;
3483 switch(ObjectVT.getSimpleVT().SimpleTy) {
3484 default: llvm_unreachable("Unhandled argument type!");
3490 case MVT::i64: // PPC64
3492 // FIXME: We are guaranteed to be !isPPC64 at this point.
3493 // Does MVT::i64 apply?
3500 // Nothing to do, we're only looking at Nonvector args here.
3505 // We've found where the vector parameter area in memory is. Skip the
3506 // first 12 parameters; these don't use that memory.
3507 VecArgOffset = ((VecArgOffset+15)/16)*16;
3508 VecArgOffset += 12*16;
3510 // Add DAG nodes to load the arguments or copy them out of registers. On
3511 // entry to a function on PPC, the arguments start after the linkage area,
3512 // although the first ones are often in registers.
3514 SmallVector<SDValue, 8> MemOps;
3515 unsigned nAltivecParamsAtEnd = 0;
3516 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3517 unsigned CurArgIdx = 0;
3518 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3520 bool needsLoad = false;
3521 EVT ObjectVT = Ins[ArgNo].VT;
3522 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
3523 unsigned ArgSize = ObjSize;
3524 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3525 if (Ins[ArgNo].isOrigArg()) {
3526 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
3527 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
3529 unsigned CurArgOffset = ArgOffset;
3531 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
3532 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
3533 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
3534 if (isVarArg || isPPC64) {
3535 MinReservedArea = ((MinReservedArea+15)/16)*16;
3536 MinReservedArea += CalculateStackSlotSize(ObjectVT,
3539 } else nAltivecParamsAtEnd++;
3541 // Calculate min reserved area.
3542 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
3546 // FIXME the codegen can be much improved in some cases.
3547 // We do not have to keep everything in memory.
3548 if (Flags.isByVal()) {
3549 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit");
3551 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3552 ObjSize = Flags.getByValSize();
3553 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3554 // Objects of size 1 and 2 are right justified, everything else is
3555 // left justified. This means the memory address is adjusted forwards.
3556 if (ObjSize==1 || ObjSize==2) {
3557 CurArgOffset = CurArgOffset + (4 - ObjSize);
3559 // The value of the object is its address.
3560 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, false, true);
3561 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3562 InVals.push_back(FIN);
3563 if (ObjSize==1 || ObjSize==2) {
3564 if (GPR_idx != Num_GPR_Regs) {
3567 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3569 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3570 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3571 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
3572 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
3573 MachinePointerInfo(FuncArg),
3574 ObjType, false, false, 0);
3575 MemOps.push_back(Store);
3579 ArgOffset += PtrByteSize;
3583 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3584 // Store whatever pieces of the object are in registers
3585 // to memory. ArgOffset will be the address of the beginning
3587 if (GPR_idx != Num_GPR_Regs) {
3590 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3592 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3593 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3594 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3595 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3596 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3597 MachinePointerInfo(FuncArg, j),
3599 MemOps.push_back(Store);
3601 ArgOffset += PtrByteSize;
3603 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
3610 switch (ObjectVT.getSimpleVT().SimpleTy) {
3611 default: llvm_unreachable("Unhandled argument type!");
3615 if (GPR_idx != Num_GPR_Regs) {
3616 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3617 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3619 if (ObjectVT == MVT::i1)
3620 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
3625 ArgSize = PtrByteSize;
3627 // All int arguments reserve stack space in the Darwin ABI.
3628 ArgOffset += PtrByteSize;
3632 case MVT::i64: // PPC64
3633 if (GPR_idx != Num_GPR_Regs) {
3634 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3635 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3637 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3638 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3639 // value to MVT::i64 and then truncate to the correct register size.
3640 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3645 ArgSize = PtrByteSize;
3647 // All int arguments reserve stack space in the Darwin ABI.
3653 // Every 4 bytes of argument space consumes one of the GPRs available for
3654 // argument passing.
3655 if (GPR_idx != Num_GPR_Regs) {
3657 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
3660 if (FPR_idx != Num_FPR_Regs) {
3663 if (ObjectVT == MVT::f32)
3664 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
3666 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
3668 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3674 // All FP arguments reserve stack space in the Darwin ABI.
3675 ArgOffset += isPPC64 ? 8 : ObjSize;
3681 // Note that vector arguments in registers don't reserve stack space,
3682 // except in varargs functions.
3683 if (VR_idx != Num_VR_Regs) {
3684 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3685 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3687 while ((ArgOffset % 16) != 0) {
3688 ArgOffset += PtrByteSize;
3689 if (GPR_idx != Num_GPR_Regs)
3693 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
3697 if (!isVarArg && !isPPC64) {
3698 // Vectors go after all the nonvectors.
3699 CurArgOffset = VecArgOffset;
3702 // Vectors are aligned.
3703 ArgOffset = ((ArgOffset+15)/16)*16;
3704 CurArgOffset = ArgOffset;
3712 // We need to load the argument to a virtual register if we determined above
3713 // that we ran out of physical registers of the appropriate type.
3715 int FI = MFI->CreateFixedObject(ObjSize,
3716 CurArgOffset + (ArgSize - ObjSize),
3718 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3719 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3720 false, false, false, 0);
3723 InVals.push_back(ArgVal);
3726 // Allow for Altivec parameters at the end, if needed.
3727 if (nAltivecParamsAtEnd) {
3728 MinReservedArea = ((MinReservedArea+15)/16)*16;
3729 MinReservedArea += 16*nAltivecParamsAtEnd;
3732 // Area that is at least reserved in the caller of this function.
3733 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
3735 // Set the size that is at least reserved in caller of this function. Tail
3736 // call optimized functions' reserved stack space needs to be aligned so that
3737 // taking the difference between two stack areas will result in an aligned
3740 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3741 FuncInfo->setMinReservedArea(MinReservedArea);
3743 // If the function takes variable number of arguments, make a frame index for
3744 // the start of the first vararg value... for expansion of llvm.va_start.
3746 int Depth = ArgOffset;
3748 FuncInfo->setVarArgsFrameIndex(
3749 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3751 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3753 // If this function is vararg, store any remaining integer argument regs
3754 // to their spots on the stack so that they may be loaded by deferencing the
3755 // result of va_next.
3756 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3760 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3762 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3764 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3765 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3766 MachinePointerInfo(), false, false, 0);
3767 MemOps.push_back(Store);
3768 // Increment the address by four for the next argument to store
3769 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
3770 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3774 if (!MemOps.empty())
3775 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3780 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3781 /// adjusted to accommodate the arguments for the tailcall.
3782 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3783 unsigned ParamSize) {
3785 if (!isTailCall) return 0;
3787 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3788 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3789 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3790 // Remember only if the new adjustement is bigger.
3791 if (SPDiff < FI->getTailCallSPDelta())
3792 FI->setTailCallSPDelta(SPDiff);
3797 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3798 /// for tail call optimization. Targets which want to do tail call
3799 /// optimization should implement this function.
3801 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3802 CallingConv::ID CalleeCC,
3804 const SmallVectorImpl<ISD::InputArg> &Ins,
3805 SelectionDAG& DAG) const {
3806 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3809 // Variable argument functions are not supported.
3813 MachineFunction &MF = DAG.getMachineFunction();
3814 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3815 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3816 // Functions containing by val parameters are not supported.
3817 for (unsigned i = 0; i != Ins.size(); i++) {
3818 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3819 if (Flags.isByVal()) return false;
3822 // Non-PIC/GOT tail calls are supported.
3823 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3826 // At the moment we can only do local tail calls (in same module, hidden
3827 // or protected) if we are generating PIC.
3828 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3829 return G->getGlobal()->hasHiddenVisibility()
3830 || G->getGlobal()->hasProtectedVisibility();
3836 /// isCallCompatibleAddress - Return the immediate to use if the specified
3837 /// 32-bit value is representable in the immediate field of a BxA instruction.
3838 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3839 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3840 if (!C) return nullptr;
3842 int Addr = C->getZExtValue();
3843 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3844 SignExtend32<26>(Addr) != Addr)
3845 return nullptr; // Top 6 bits have to be sext of immediate.
3847 return DAG.getConstant((int)C->getZExtValue() >> 2, SDLoc(Op),
3848 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
3853 struct TailCallArgumentInfo {
3858 TailCallArgumentInfo() : FrameIdx(0) {}
3863 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3865 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3867 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3868 SmallVectorImpl<SDValue> &MemOpChains,
3870 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3871 SDValue Arg = TailCallArgs[i].Arg;
3872 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3873 int FI = TailCallArgs[i].FrameIdx;
3874 // Store relative to framepointer.
3875 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
3876 MachinePointerInfo::getFixedStack(FI),
3881 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3882 /// the appropriate stack slot for the tail call optimized function call.
3883 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3884 MachineFunction &MF,
3893 // Calculate the new stack slot for the return address.
3894 int SlotSize = isPPC64 ? 8 : 4;
3895 const PPCFrameLowering *FL =
3896 MF.getSubtarget<PPCSubtarget>().getFrameLowering();
3897 int NewRetAddrLoc = SPDiff + FL->getReturnSaveOffset();
3898 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3899 NewRetAddrLoc, true);
3900 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3901 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3902 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3903 MachinePointerInfo::getFixedStack(NewRetAddr),
3906 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3907 // slot as the FP is never overwritten.
3909 int NewFPLoc = SPDiff + FL->getFramePointerSaveOffset();
3910 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3912 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3913 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3914 MachinePointerInfo::getFixedStack(NewFPIdx),
3921 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3922 /// the position of the argument.
3924 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3925 SDValue Arg, int SPDiff, unsigned ArgOffset,
3926 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3927 int Offset = ArgOffset + SPDiff;
3928 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3929 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3930 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3931 SDValue FIN = DAG.getFrameIndex(FI, VT);
3932 TailCallArgumentInfo Info;
3934 Info.FrameIdxOp = FIN;
3936 TailCallArguments.push_back(Info);
3939 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3940 /// stack slot. Returns the chain as result and the loaded frame pointers in
3941 /// LROpOut/FPOpout. Used when tail calling.
3942 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3950 // Load the LR and FP stack slot for later adjusting.
3951 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
3952 LROpOut = getReturnAddrFrameIndex(DAG);
3953 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3954 false, false, false, 0);
3955 Chain = SDValue(LROpOut.getNode(), 1);
3957 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3958 // slot as the FP is never overwritten.
3960 FPOpOut = getFramePointerFrameIndex(DAG);
3961 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3962 false, false, false, 0);
3963 Chain = SDValue(FPOpOut.getNode(), 1);
3969 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3970 /// by "Src" to address "Dst" of size "Size". Alignment information is
3971 /// specified by the specific parameter attribute. The copy will be passed as
3972 /// a byval function parameter.
3973 /// Sometimes what we are copying is the end of a larger object, the part that
3974 /// does not fit in registers.
3976 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3977 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3979 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
3980 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3981 false, false, false, MachinePointerInfo(),
3982 MachinePointerInfo());
3985 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3988 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3989 SDValue Arg, SDValue PtrOff, int SPDiff,
3990 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3991 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
3992 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
3994 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3999 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4001 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4002 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4003 DAG.getConstant(ArgOffset, dl, PtrVT));
4005 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4006 MachinePointerInfo(), false, false, 0));
4007 // Calculate and remember argument location.
4008 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
4013 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
4014 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
4015 SDValue LROp, SDValue FPOp, bool isDarwinABI,
4016 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
4017 MachineFunction &MF = DAG.getMachineFunction();
4019 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
4020 // might overwrite each other in case of tail call optimization.
4021 SmallVector<SDValue, 8> MemOpChains2;
4022 // Do not flag preceding copytoreg stuff together with the following stuff.
4024 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
4026 if (!MemOpChains2.empty())
4027 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
4029 // Store the return address to the appropriate stack slot.
4030 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
4031 isPPC64, isDarwinABI, dl);
4033 // Emit callseq_end just before tailcall node.
4034 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4035 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
4036 InFlag = Chain.getValue(1);
4039 // Is this global address that of a function that can be called by name? (as
4040 // opposed to something that must hold a descriptor for an indirect call).
4041 static bool isFunctionGlobalAddress(SDValue Callee) {
4042 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
4043 if (Callee.getOpcode() == ISD::GlobalTLSAddress ||
4044 Callee.getOpcode() == ISD::TargetGlobalTLSAddress)
4047 return G->getGlobal()->getType()->getElementType()->isFunctionTy();
4054 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
4055 SDValue &Chain, SDValue CallSeqStart, SDLoc dl, int SPDiff,
4056 bool isTailCall, bool IsPatchPoint,
4057 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
4058 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
4059 ImmutableCallSite *CS, const PPCSubtarget &Subtarget) {
4061 bool isPPC64 = Subtarget.isPPC64();
4062 bool isSVR4ABI = Subtarget.isSVR4ABI();
4063 bool isELFv2ABI = Subtarget.isELFv2ABI();
4065 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4066 NodeTys.push_back(MVT::Other); // Returns a chain
4067 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
4069 unsigned CallOpc = PPCISD::CALL;
4071 bool needIndirectCall = true;
4072 if (!isSVR4ABI || !isPPC64)
4073 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
4074 // If this is an absolute destination address, use the munged value.
4075 Callee = SDValue(Dest, 0);
4076 needIndirectCall = false;
4079 if (isFunctionGlobalAddress(Callee)) {
4080 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Callee);
4081 // A call to a TLS address is actually an indirect call to a
4082 // thread-specific pointer.
4083 unsigned OpFlags = 0;
4084 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
4085 (Subtarget.getTargetTriple().isMacOSX() &&
4086 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
4087 (G->getGlobal()->isDeclaration() ||
4088 G->getGlobal()->isWeakForLinker())) ||
4089 (Subtarget.isTargetELF() && !isPPC64 &&
4090 !G->getGlobal()->hasLocalLinkage() &&
4091 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
4092 // PC-relative references to external symbols should go through $stub,
4093 // unless we're building with the leopard linker or later, which
4094 // automatically synthesizes these stubs.
4095 OpFlags = PPCII::MO_PLT_OR_STUB;
4098 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
4099 // every direct call is) turn it into a TargetGlobalAddress /
4100 // TargetExternalSymbol node so that legalize doesn't hack it.
4101 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
4102 Callee.getValueType(), 0, OpFlags);
4103 needIndirectCall = false;
4106 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
4107 unsigned char OpFlags = 0;
4109 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
4110 (Subtarget.getTargetTriple().isMacOSX() &&
4111 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) ||
4112 (Subtarget.isTargetELF() && !isPPC64 &&
4113 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
4114 // PC-relative references to external symbols should go through $stub,
4115 // unless we're building with the leopard linker or later, which
4116 // automatically synthesizes these stubs.
4117 OpFlags = PPCII::MO_PLT_OR_STUB;
4120 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
4122 needIndirectCall = false;
4126 // We'll form an invalid direct call when lowering a patchpoint; the full
4127 // sequence for an indirect call is complicated, and many of the
4128 // instructions introduced might have side effects (and, thus, can't be
4129 // removed later). The call itself will be removed as soon as the
4130 // argument/return lowering is complete, so the fact that it has the wrong
4131 // kind of operands should not really matter.
4132 needIndirectCall = false;
4135 if (needIndirectCall) {
4136 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
4137 // to do the call, we can't use PPCISD::CALL.
4138 SDValue MTCTROps[] = {Chain, Callee, InFlag};
4140 if (isSVR4ABI && isPPC64 && !isELFv2ABI) {
4141 // Function pointers in the 64-bit SVR4 ABI do not point to the function
4142 // entry point, but to the function descriptor (the function entry point
4143 // address is part of the function descriptor though).
4144 // The function descriptor is a three doubleword structure with the
4145 // following fields: function entry point, TOC base address and
4146 // environment pointer.
4147 // Thus for a call through a function pointer, the following actions need
4149 // 1. Save the TOC of the caller in the TOC save area of its stack
4150 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
4151 // 2. Load the address of the function entry point from the function
4153 // 3. Load the TOC of the callee from the function descriptor into r2.
4154 // 4. Load the environment pointer from the function descriptor into
4156 // 5. Branch to the function entry point address.
4157 // 6. On return of the callee, the TOC of the caller needs to be
4158 // restored (this is done in FinishCall()).
4160 // The loads are scheduled at the beginning of the call sequence, and the
4161 // register copies are flagged together to ensure that no other
4162 // operations can be scheduled in between. E.g. without flagging the
4163 // copies together, a TOC access in the caller could be scheduled between
4164 // the assignment of the callee TOC and the branch to the callee, which
4165 // results in the TOC access going through the TOC of the callee instead
4166 // of going through the TOC of the caller, which leads to incorrect code.
4168 // Load the address of the function entry point from the function
4170 SDValue LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-1);
4171 if (LDChain.getValueType() == MVT::Glue)
4172 LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-2);
4174 bool LoadsInv = Subtarget.hasInvariantFunctionDescriptors();
4176 MachinePointerInfo MPI(CS ? CS->getCalledValue() : nullptr);
4177 SDValue LoadFuncPtr = DAG.getLoad(MVT::i64, dl, LDChain, Callee, MPI,
4178 false, false, LoadsInv, 8);
4180 // Load environment pointer into r11.
4181 SDValue PtrOff = DAG.getIntPtrConstant(16, dl);
4182 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
4183 SDValue LoadEnvPtr = DAG.getLoad(MVT::i64, dl, LDChain, AddPtr,
4184 MPI.getWithOffset(16), false, false,
4187 SDValue TOCOff = DAG.getIntPtrConstant(8, dl);
4188 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
4189 SDValue TOCPtr = DAG.getLoad(MVT::i64, dl, LDChain, AddTOC,
4190 MPI.getWithOffset(8), false, false,
4193 setUsesTOCBasePtr(DAG);
4194 SDValue TOCVal = DAG.getCopyToReg(Chain, dl, PPC::X2, TOCPtr,
4196 Chain = TOCVal.getValue(0);
4197 InFlag = TOCVal.getValue(1);
4199 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
4202 Chain = EnvVal.getValue(0);
4203 InFlag = EnvVal.getValue(1);
4205 MTCTROps[0] = Chain;
4206 MTCTROps[1] = LoadFuncPtr;
4207 MTCTROps[2] = InFlag;
4210 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
4211 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
4212 InFlag = Chain.getValue(1);
4215 NodeTys.push_back(MVT::Other);
4216 NodeTys.push_back(MVT::Glue);
4217 Ops.push_back(Chain);
4218 CallOpc = PPCISD::BCTRL;
4219 Callee.setNode(nullptr);
4220 // Add use of X11 (holding environment pointer)
4221 if (isSVR4ABI && isPPC64 && !isELFv2ABI)
4222 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
4223 // Add CTR register as callee so a bctr can be emitted later.
4225 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
4228 // If this is a direct call, pass the chain and the callee.
4229 if (Callee.getNode()) {
4230 Ops.push_back(Chain);
4231 Ops.push_back(Callee);
4233 // If this is a tail call add stack pointer delta.
4235 Ops.push_back(DAG.getConstant(SPDiff, dl, MVT::i32));
4237 // Add argument registers to the end of the list so that they are known live
4239 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
4240 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
4241 RegsToPass[i].second.getValueType()));
4243 // All calls, in both the ELF V1 and V2 ABIs, need the TOC register live
4245 if (isSVR4ABI && isPPC64 && !IsPatchPoint) {
4246 setUsesTOCBasePtr(DAG);
4247 Ops.push_back(DAG.getRegister(PPC::X2, PtrVT));
4254 bool isLocalCall(const SDValue &Callee)
4256 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
4257 return !G->getGlobal()->isDeclaration() &&
4258 !G->getGlobal()->isWeakForLinker();
4263 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
4264 CallingConv::ID CallConv, bool isVarArg,
4265 const SmallVectorImpl<ISD::InputArg> &Ins,
4266 SDLoc dl, SelectionDAG &DAG,
4267 SmallVectorImpl<SDValue> &InVals) const {
4269 SmallVector<CCValAssign, 16> RVLocs;
4270 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
4272 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
4274 // Copy all of the result registers out of their specified physreg.
4275 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
4276 CCValAssign &VA = RVLocs[i];
4277 assert(VA.isRegLoc() && "Can only return in registers!");
4279 SDValue Val = DAG.getCopyFromReg(Chain, dl,
4280 VA.getLocReg(), VA.getLocVT(), InFlag);
4281 Chain = Val.getValue(1);
4282 InFlag = Val.getValue(2);
4284 switch (VA.getLocInfo()) {
4285 default: llvm_unreachable("Unknown loc info!");
4286 case CCValAssign::Full: break;
4287 case CCValAssign::AExt:
4288 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4290 case CCValAssign::ZExt:
4291 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
4292 DAG.getValueType(VA.getValVT()));
4293 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4295 case CCValAssign::SExt:
4296 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
4297 DAG.getValueType(VA.getValVT()));
4298 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4302 InVals.push_back(Val);
4309 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
4310 bool isTailCall, bool isVarArg, bool IsPatchPoint,
4312 SmallVector<std::pair<unsigned, SDValue>, 8>
4314 SDValue InFlag, SDValue Chain,
4315 SDValue CallSeqStart, SDValue &Callee,
4316 int SPDiff, unsigned NumBytes,
4317 const SmallVectorImpl<ISD::InputArg> &Ins,
4318 SmallVectorImpl<SDValue> &InVals,
4319 ImmutableCallSite *CS) const {
4321 std::vector<EVT> NodeTys;
4322 SmallVector<SDValue, 8> Ops;
4323 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, CallSeqStart, dl,
4324 SPDiff, isTailCall, IsPatchPoint, RegsToPass,
4325 Ops, NodeTys, CS, Subtarget);
4327 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
4328 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
4329 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
4331 // When performing tail call optimization the callee pops its arguments off
4332 // the stack. Account for this here so these bytes can be pushed back on in
4333 // PPCFrameLowering::eliminateCallFramePseudoInstr.
4334 int BytesCalleePops =
4335 (CallConv == CallingConv::Fast &&
4336 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
4338 // Add a register mask operand representing the call-preserved registers.
4339 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
4340 const uint32_t *Mask =
4341 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
4342 assert(Mask && "Missing call preserved mask for calling convention");
4343 Ops.push_back(DAG.getRegisterMask(Mask));
4345 if (InFlag.getNode())
4346 Ops.push_back(InFlag);
4350 assert(((Callee.getOpcode() == ISD::Register &&
4351 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
4352 Callee.getOpcode() == ISD::TargetExternalSymbol ||
4353 Callee.getOpcode() == ISD::TargetGlobalAddress ||
4354 isa<ConstantSDNode>(Callee)) &&
4355 "Expecting an global address, external symbol, absolute value or register");
4357 DAG.getMachineFunction().getFrameInfo()->setHasTailCall();
4358 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
4361 // Add a NOP immediately after the branch instruction when using the 64-bit
4362 // SVR4 ABI. At link time, if caller and callee are in a different module and
4363 // thus have a different TOC, the call will be replaced with a call to a stub
4364 // function which saves the current TOC, loads the TOC of the callee and
4365 // branches to the callee. The NOP will be replaced with a load instruction
4366 // which restores the TOC of the caller from the TOC save slot of the current
4367 // stack frame. If caller and callee belong to the same module (and have the
4368 // same TOC), the NOP will remain unchanged.
4370 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64() &&
4372 if (CallOpc == PPCISD::BCTRL) {
4373 // This is a call through a function pointer.
4374 // Restore the caller TOC from the save area into R2.
4375 // See PrepareCall() for more information about calls through function
4376 // pointers in the 64-bit SVR4 ABI.
4377 // We are using a target-specific load with r2 hard coded, because the
4378 // result of a target-independent load would never go directly into r2,
4379 // since r2 is a reserved register (which prevents the register allocator
4380 // from allocating it), resulting in an additional register being
4381 // allocated and an unnecessary move instruction being generated.
4382 CallOpc = PPCISD::BCTRL_LOAD_TOC;
4384 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4385 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
4386 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
4387 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset, dl);
4388 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
4390 // The address needs to go after the chain input but before the flag (or
4391 // any other variadic arguments).
4392 Ops.insert(std::next(Ops.begin()), AddTOC);
4393 } else if ((CallOpc == PPCISD::CALL) &&
4394 (!isLocalCall(Callee) ||
4395 DAG.getTarget().getRelocationModel() == Reloc::PIC_))
4396 // Otherwise insert NOP for non-local calls.
4397 CallOpc = PPCISD::CALL_NOP;
4400 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
4401 InFlag = Chain.getValue(1);
4403 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4404 DAG.getIntPtrConstant(BytesCalleePops, dl, true),
4407 InFlag = Chain.getValue(1);
4409 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
4410 Ins, dl, DAG, InVals);
4414 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
4415 SmallVectorImpl<SDValue> &InVals) const {
4416 SelectionDAG &DAG = CLI.DAG;
4418 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
4419 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
4420 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
4421 SDValue Chain = CLI.Chain;
4422 SDValue Callee = CLI.Callee;
4423 bool &isTailCall = CLI.IsTailCall;
4424 CallingConv::ID CallConv = CLI.CallConv;
4425 bool isVarArg = CLI.IsVarArg;
4426 bool IsPatchPoint = CLI.IsPatchPoint;
4427 ImmutableCallSite *CS = CLI.CS;
4430 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
4433 if (!isTailCall && CS && CS->isMustTailCall())
4434 report_fatal_error("failed to perform tail call elimination on a call "
4435 "site marked musttail");
4437 if (Subtarget.isSVR4ABI()) {
4438 if (Subtarget.isPPC64())
4439 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
4440 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4441 dl, DAG, InVals, CS);
4443 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
4444 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4445 dl, DAG, InVals, CS);
4448 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
4449 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4450 dl, DAG, InVals, CS);
4454 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
4455 CallingConv::ID CallConv, bool isVarArg,
4456 bool isTailCall, bool IsPatchPoint,
4457 const SmallVectorImpl<ISD::OutputArg> &Outs,
4458 const SmallVectorImpl<SDValue> &OutVals,
4459 const SmallVectorImpl<ISD::InputArg> &Ins,
4460 SDLoc dl, SelectionDAG &DAG,
4461 SmallVectorImpl<SDValue> &InVals,
4462 ImmutableCallSite *CS) const {
4463 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
4464 // of the 32-bit SVR4 ABI stack frame layout.
4466 assert((CallConv == CallingConv::C ||
4467 CallConv == CallingConv::Fast) && "Unknown calling convention!");
4469 unsigned PtrByteSize = 4;
4471 MachineFunction &MF = DAG.getMachineFunction();
4473 // Mark this function as potentially containing a function that contains a
4474 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4475 // and restoring the callers stack pointer in this functions epilog. This is
4476 // done because by tail calling the called function might overwrite the value
4477 // in this function's (MF) stack pointer stack slot 0(SP).
4478 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4479 CallConv == CallingConv::Fast)
4480 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4482 // Count how many bytes are to be pushed on the stack, including the linkage
4483 // area, parameter list area and the part of the local variable space which
4484 // contains copies of aggregates which are passed by value.
4486 // Assign locations to all of the outgoing arguments.
4487 SmallVector<CCValAssign, 16> ArgLocs;
4488 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
4491 // Reserve space for the linkage area on the stack.
4492 CCInfo.AllocateStack(Subtarget.getFrameLowering()->getLinkageSize(),
4496 // Handle fixed and variable vector arguments differently.
4497 // Fixed vector arguments go into registers as long as registers are
4498 // available. Variable vector arguments always go into memory.
4499 unsigned NumArgs = Outs.size();
4501 for (unsigned i = 0; i != NumArgs; ++i) {
4502 MVT ArgVT = Outs[i].VT;
4503 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
4506 if (Outs[i].IsFixed) {
4507 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
4510 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
4516 errs() << "Call operand #" << i << " has unhandled type "
4517 << EVT(ArgVT).getEVTString() << "\n";
4519 llvm_unreachable(nullptr);
4523 // All arguments are treated the same.
4524 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
4527 // Assign locations to all of the outgoing aggregate by value arguments.
4528 SmallVector<CCValAssign, 16> ByValArgLocs;
4529 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4530 ByValArgLocs, *DAG.getContext());
4532 // Reserve stack space for the allocations in CCInfo.
4533 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
4535 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
4537 // Size of the linkage area, parameter list area and the part of the local
4538 // space variable where copies of aggregates which are passed by value are
4540 unsigned NumBytes = CCByValInfo.getNextStackOffset();
4542 // Calculate by how many bytes the stack has to be adjusted in case of tail
4543 // call optimization.
4544 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4546 // Adjust the stack pointer for the new arguments...
4547 // These operations are automatically eliminated by the prolog/epilog pass
4548 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4550 SDValue CallSeqStart = Chain;
4552 // Load the return address and frame pointer so it can be moved somewhere else
4555 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
4558 // Set up a copy of the stack pointer for use loading and storing any
4559 // arguments that may not fit in the registers available for argument
4561 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4563 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4564 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4565 SmallVector<SDValue, 8> MemOpChains;
4567 bool seenFloatArg = false;
4568 // Walk the register/memloc assignments, inserting copies/loads.
4569 for (unsigned i = 0, j = 0, e = ArgLocs.size();
4572 CCValAssign &VA = ArgLocs[i];
4573 SDValue Arg = OutVals[i];
4574 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4576 if (Flags.isByVal()) {
4577 // Argument is an aggregate which is passed by value, thus we need to
4578 // create a copy of it in the local variable space of the current stack
4579 // frame (which is the stack frame of the caller) and pass the address of
4580 // this copy to the callee.
4581 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
4582 CCValAssign &ByValVA = ByValArgLocs[j++];
4583 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
4585 // Memory reserved in the local variable space of the callers stack frame.
4586 unsigned LocMemOffset = ByValVA.getLocMemOffset();
4588 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
4589 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4591 // Create a copy of the argument in the local area of the current
4593 SDValue MemcpyCall =
4594 CreateCopyOfByValArgument(Arg, PtrOff,
4595 CallSeqStart.getNode()->getOperand(0),
4598 // This must go outside the CALLSEQ_START..END.
4599 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4600 CallSeqStart.getNode()->getOperand(1),
4602 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4603 NewCallSeqStart.getNode());
4604 Chain = CallSeqStart = NewCallSeqStart;
4606 // Pass the address of the aggregate copy on the stack either in a
4607 // physical register or in the parameter list area of the current stack
4608 // frame to the callee.
4612 if (VA.isRegLoc()) {
4613 if (Arg.getValueType() == MVT::i1)
4614 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
4616 seenFloatArg |= VA.getLocVT().isFloatingPoint();
4617 // Put argument in a physical register.
4618 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
4620 // Put argument in the parameter list area of the current stack frame.
4621 assert(VA.isMemLoc());
4622 unsigned LocMemOffset = VA.getLocMemOffset();
4625 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
4626 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4628 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4629 MachinePointerInfo(),
4632 // Calculate and remember argument location.
4633 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
4639 if (!MemOpChains.empty())
4640 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4642 // Build a sequence of copy-to-reg nodes chained together with token chain
4643 // and flag operands which copy the outgoing args into the appropriate regs.
4645 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4646 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4647 RegsToPass[i].second, InFlag);
4648 InFlag = Chain.getValue(1);
4651 // Set CR bit 6 to true if this is a vararg call with floating args passed in
4654 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
4655 SDValue Ops[] = { Chain, InFlag };
4657 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
4658 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
4660 InFlag = Chain.getValue(1);
4664 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
4665 false, TailCallArguments);
4667 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint, DAG,
4668 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
4669 NumBytes, Ins, InVals, CS);
4672 // Copy an argument into memory, being careful to do this outside the
4673 // call sequence for the call to which the argument belongs.
4675 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
4676 SDValue CallSeqStart,
4677 ISD::ArgFlagsTy Flags,
4680 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
4681 CallSeqStart.getNode()->getOperand(0),
4683 // The MEMCPY must go outside the CALLSEQ_START..END.
4684 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4685 CallSeqStart.getNode()->getOperand(1),
4687 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4688 NewCallSeqStart.getNode());
4689 return NewCallSeqStart;
4693 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
4694 CallingConv::ID CallConv, bool isVarArg,
4695 bool isTailCall, bool IsPatchPoint,
4696 const SmallVectorImpl<ISD::OutputArg> &Outs,
4697 const SmallVectorImpl<SDValue> &OutVals,
4698 const SmallVectorImpl<ISD::InputArg> &Ins,
4699 SDLoc dl, SelectionDAG &DAG,
4700 SmallVectorImpl<SDValue> &InVals,
4701 ImmutableCallSite *CS) const {
4703 bool isELFv2ABI = Subtarget.isELFv2ABI();
4704 bool isLittleEndian = Subtarget.isLittleEndian();
4705 unsigned NumOps = Outs.size();
4707 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4708 unsigned PtrByteSize = 8;
4710 MachineFunction &MF = DAG.getMachineFunction();
4712 // Mark this function as potentially containing a function that contains a
4713 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4714 // and restoring the callers stack pointer in this functions epilog. This is
4715 // done because by tail calling the called function might overwrite the value
4716 // in this function's (MF) stack pointer stack slot 0(SP).
4717 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4718 CallConv == CallingConv::Fast)
4719 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4721 assert(!(CallConv == CallingConv::Fast && isVarArg) &&
4722 "fastcc not supported on varargs functions");
4724 // Count how many bytes are to be pushed on the stack, including the linkage
4725 // area, and parameter passing area. On ELFv1, the linkage area is 48 bytes
4726 // reserved space for [SP][CR][LR][2 x unused][TOC]; on ELFv2, the linkage
4727 // area is 32 bytes reserved space for [SP][CR][LR][TOC].
4728 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
4729 unsigned NumBytes = LinkageSize;
4730 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4731 unsigned &QFPR_idx = FPR_idx;
4733 static const MCPhysReg GPR[] = {
4734 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4735 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4737 static const MCPhysReg VR[] = {
4738 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4739 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4741 static const MCPhysReg VSRH[] = {
4742 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4743 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4746 const unsigned NumGPRs = array_lengthof(GPR);
4747 const unsigned NumFPRs = 13;
4748 const unsigned NumVRs = array_lengthof(VR);
4749 const unsigned NumQFPRs = NumFPRs;
4751 // When using the fast calling convention, we don't provide backing for
4752 // arguments that will be in registers.
4753 unsigned NumGPRsUsed = 0, NumFPRsUsed = 0, NumVRsUsed = 0;
4755 // Add up all the space actually used.
4756 for (unsigned i = 0; i != NumOps; ++i) {
4757 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4758 EVT ArgVT = Outs[i].VT;
4759 EVT OrigVT = Outs[i].ArgVT;
4761 if (CallConv == CallingConv::Fast) {
4762 if (Flags.isByVal())
4763 NumGPRsUsed += (Flags.getByValSize()+7)/8;
4765 switch (ArgVT.getSimpleVT().SimpleTy) {
4766 default: llvm_unreachable("Unexpected ValueType for argument!");
4770 if (++NumGPRsUsed <= NumGPRs)
4779 if (++NumVRsUsed <= NumVRs)
4783 // When using QPX, this is handled like a FP register, otherwise, it
4784 // is an Altivec register.
4785 if (Subtarget.hasQPX()) {
4786 if (++NumFPRsUsed <= NumFPRs)
4789 if (++NumVRsUsed <= NumVRs)
4795 case MVT::v4f64: // QPX
4796 case MVT::v4i1: // QPX
4797 if (++NumFPRsUsed <= NumFPRs)
4803 /* Respect alignment of argument on the stack. */
4805 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4806 NumBytes = ((NumBytes + Align - 1) / Align) * Align;
4808 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4809 if (Flags.isInConsecutiveRegsLast())
4810 NumBytes = ((NumBytes + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4813 unsigned NumBytesActuallyUsed = NumBytes;
4815 // The prolog code of the callee may store up to 8 GPR argument registers to
4816 // the stack, allowing va_start to index over them in memory if its varargs.
4817 // Because we cannot tell if this is needed on the caller side, we have to
4818 // conservatively assume that it is needed. As such, make sure we have at
4819 // least enough stack space for the caller to store the 8 GPRs.
4820 // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
4821 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4823 // Tail call needs the stack to be aligned.
4824 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4825 CallConv == CallingConv::Fast)
4826 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes);
4828 // Calculate by how many bytes the stack has to be adjusted in case of tail
4829 // call optimization.
4830 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4832 // To protect arguments on the stack from being clobbered in a tail call,
4833 // force all the loads to happen before doing any other lowering.
4835 Chain = DAG.getStackArgumentTokenFactor(Chain);
4837 // Adjust the stack pointer for the new arguments...
4838 // These operations are automatically eliminated by the prolog/epilog pass
4839 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4841 SDValue CallSeqStart = Chain;
4843 // Load the return address and frame pointer so it can be move somewhere else
4846 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4849 // Set up a copy of the stack pointer for use loading and storing any
4850 // arguments that may not fit in the registers available for argument
4852 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4854 // Figure out which arguments are going to go in registers, and which in
4855 // memory. Also, if this is a vararg function, floating point operations
4856 // must be stored to our stack, and loaded into integer regs as well, if
4857 // any integer regs are available for argument passing.
4858 unsigned ArgOffset = LinkageSize;
4860 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4861 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4863 SmallVector<SDValue, 8> MemOpChains;
4864 for (unsigned i = 0; i != NumOps; ++i) {
4865 SDValue Arg = OutVals[i];
4866 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4867 EVT ArgVT = Outs[i].VT;
4868 EVT OrigVT = Outs[i].ArgVT;
4870 // PtrOff will be used to store the current argument to the stack if a
4871 // register cannot be found for it.
4874 // We re-align the argument offset for each argument, except when using the
4875 // fast calling convention, when we need to make sure we do that only when
4876 // we'll actually use a stack slot.
4877 auto ComputePtrOff = [&]() {
4878 /* Respect alignment of argument on the stack. */
4880 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4881 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
4883 PtrOff = DAG.getConstant(ArgOffset, dl, StackPtr.getValueType());
4885 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4888 if (CallConv != CallingConv::Fast) {
4891 /* Compute GPR index associated with argument offset. */
4892 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4893 GPR_idx = std::min(GPR_idx, NumGPRs);
4896 // Promote integers to 64-bit values.
4897 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4898 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4899 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4900 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4903 // FIXME memcpy is used way more than necessary. Correctness first.
4904 // Note: "by value" is code for passing a structure by value, not
4906 if (Flags.isByVal()) {
4907 // Note: Size includes alignment padding, so
4908 // struct x { short a; char b; }
4909 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4910 // These are the proper values we need for right-justifying the
4911 // aggregate in a parameter register.
4912 unsigned Size = Flags.getByValSize();
4914 // An empty aggregate parameter takes up no storage and no
4919 if (CallConv == CallingConv::Fast)
4922 // All aggregates smaller than 8 bytes must be passed right-justified.
4923 if (Size==1 || Size==2 || Size==4) {
4924 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4925 if (GPR_idx != NumGPRs) {
4926 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4927 MachinePointerInfo(), VT,
4928 false, false, false, 0);
4929 MemOpChains.push_back(Load.getValue(1));
4930 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4932 ArgOffset += PtrByteSize;
4937 if (GPR_idx == NumGPRs && Size < 8) {
4938 SDValue AddPtr = PtrOff;
4939 if (!isLittleEndian) {
4940 SDValue Const = DAG.getConstant(PtrByteSize - Size, dl,
4941 PtrOff.getValueType());
4942 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4944 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4947 ArgOffset += PtrByteSize;
4950 // Copy entire object into memory. There are cases where gcc-generated
4951 // code assumes it is there, even if it could be put entirely into
4952 // registers. (This is not what the doc says.)
4954 // FIXME: The above statement is likely due to a misunderstanding of the
4955 // documents. All arguments must be copied into the parameter area BY
4956 // THE CALLEE in the event that the callee takes the address of any
4957 // formal argument. That has not yet been implemented. However, it is
4958 // reasonable to use the stack area as a staging area for the register
4961 // Skip this for small aggregates, as we will use the same slot for a
4962 // right-justified copy, below.
4964 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4968 // When a register is available, pass a small aggregate right-justified.
4969 if (Size < 8 && GPR_idx != NumGPRs) {
4970 // The easiest way to get this right-justified in a register
4971 // is to copy the structure into the rightmost portion of a
4972 // local variable slot, then load the whole slot into the
4974 // FIXME: The memcpy seems to produce pretty awful code for
4975 // small aggregates, particularly for packed ones.
4976 // FIXME: It would be preferable to use the slot in the
4977 // parameter save area instead of a new local variable.
4978 SDValue AddPtr = PtrOff;
4979 if (!isLittleEndian) {
4980 SDValue Const = DAG.getConstant(8 - Size, dl, PtrOff.getValueType());
4981 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4983 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4987 // Load the slot into the register.
4988 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
4989 MachinePointerInfo(),
4990 false, false, false, 0);
4991 MemOpChains.push_back(Load.getValue(1));
4992 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4994 // Done with this argument.
4995 ArgOffset += PtrByteSize;
4999 // For aggregates larger than PtrByteSize, copy the pieces of the
5000 // object that fit into registers from the parameter save area.
5001 for (unsigned j=0; j<Size; j+=PtrByteSize) {
5002 SDValue Const = DAG.getConstant(j, dl, PtrOff.getValueType());
5003 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
5004 if (GPR_idx != NumGPRs) {
5005 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
5006 MachinePointerInfo(),
5007 false, false, false, 0);
5008 MemOpChains.push_back(Load.getValue(1));
5009 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5010 ArgOffset += PtrByteSize;
5012 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
5019 switch (Arg.getSimpleValueType().SimpleTy) {
5020 default: llvm_unreachable("Unexpected ValueType for argument!");
5024 // These can be scalar arguments or elements of an integer array type
5025 // passed directly. Clang may use those instead of "byval" aggregate
5026 // types to avoid forcing arguments to memory unnecessarily.
5027 if (GPR_idx != NumGPRs) {
5028 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
5030 if (CallConv == CallingConv::Fast)
5033 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5034 true, isTailCall, false, MemOpChains,
5035 TailCallArguments, dl);
5036 if (CallConv == CallingConv::Fast)
5037 ArgOffset += PtrByteSize;
5039 if (CallConv != CallingConv::Fast)
5040 ArgOffset += PtrByteSize;
5044 // These can be scalar arguments or elements of a float array type
5045 // passed directly. The latter are used to implement ELFv2 homogenous
5046 // float aggregates.
5048 // Named arguments go into FPRs first, and once they overflow, the
5049 // remaining arguments go into GPRs and then the parameter save area.
5050 // Unnamed arguments for vararg functions always go to GPRs and
5051 // then the parameter save area. For now, put all arguments to vararg
5052 // routines always in both locations (FPR *and* GPR or stack slot).
5053 bool NeedGPROrStack = isVarArg || FPR_idx == NumFPRs;
5054 bool NeededLoad = false;
5056 // First load the argument into the next available FPR.
5057 if (FPR_idx != NumFPRs)
5058 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
5060 // Next, load the argument into GPR or stack slot if needed.
5061 if (!NeedGPROrStack)
5063 else if (GPR_idx != NumGPRs && CallConv != CallingConv::Fast) {
5064 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
5065 // once we support fp <-> gpr moves.
5067 // In the non-vararg case, this can only ever happen in the
5068 // presence of f32 array types, since otherwise we never run
5069 // out of FPRs before running out of GPRs.
5072 // Double values are always passed in a single GPR.
5073 if (Arg.getValueType() != MVT::f32) {
5074 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
5076 // Non-array float values are extended and passed in a GPR.
5077 } else if (!Flags.isInConsecutiveRegs()) {
5078 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
5079 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
5081 // If we have an array of floats, we collect every odd element
5082 // together with its predecessor into one GPR.
5083 } else if (ArgOffset % PtrByteSize != 0) {
5085 Lo = DAG.getNode(ISD::BITCAST, dl, MVT::i32, OutVals[i - 1]);
5086 Hi = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
5087 if (!isLittleEndian)
5089 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
5091 // The final element, if even, goes into the first half of a GPR.
5092 } else if (Flags.isInConsecutiveRegsLast()) {
5093 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
5094 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
5095 if (!isLittleEndian)
5096 ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal,
5097 DAG.getConstant(32, dl, MVT::i32));
5099 // Non-final even elements are skipped; they will be handled
5100 // together the with subsequent argument on the next go-around.
5104 if (ArgVal.getNode())
5105 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], ArgVal));
5107 if (CallConv == CallingConv::Fast)
5110 // Single-precision floating-point values are mapped to the
5111 // second (rightmost) word of the stack doubleword.
5112 if (Arg.getValueType() == MVT::f32 &&
5113 !isLittleEndian && !Flags.isInConsecutiveRegs()) {
5114 SDValue ConstFour = DAG.getConstant(4, dl, PtrOff.getValueType());
5115 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
5118 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5119 true, isTailCall, false, MemOpChains,
5120 TailCallArguments, dl);
5124 // When passing an array of floats, the array occupies consecutive
5125 // space in the argument area; only round up to the next doubleword
5126 // at the end of the array. Otherwise, each float takes 8 bytes.
5127 if (CallConv != CallingConv::Fast || NeededLoad) {
5128 ArgOffset += (Arg.getValueType() == MVT::f32 &&
5129 Flags.isInConsecutiveRegs()) ? 4 : 8;
5130 if (Flags.isInConsecutiveRegsLast())
5131 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
5142 if (!Subtarget.hasQPX()) {
5143 // These can be scalar arguments or elements of a vector array type
5144 // passed directly. The latter are used to implement ELFv2 homogenous
5145 // vector aggregates.
5147 // For a varargs call, named arguments go into VRs or on the stack as
5148 // usual; unnamed arguments always go to the stack or the corresponding
5149 // GPRs when within range. For now, we always put the value in both
5150 // locations (or even all three).
5152 // We could elide this store in the case where the object fits
5153 // entirely in R registers. Maybe later.
5154 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5155 MachinePointerInfo(), false, false, 0);
5156 MemOpChains.push_back(Store);
5157 if (VR_idx != NumVRs) {
5158 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
5159 MachinePointerInfo(),
5160 false, false, false, 0);
5161 MemOpChains.push_back(Load.getValue(1));
5163 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
5164 Arg.getSimpleValueType() == MVT::v2i64) ?
5165 VSRH[VR_idx] : VR[VR_idx];
5168 RegsToPass.push_back(std::make_pair(VReg, Load));
5171 for (unsigned i=0; i<16; i+=PtrByteSize) {
5172 if (GPR_idx == NumGPRs)
5174 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5175 DAG.getConstant(i, dl, PtrVT));
5176 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5177 false, false, false, 0);
5178 MemOpChains.push_back(Load.getValue(1));
5179 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5184 // Non-varargs Altivec params go into VRs or on the stack.
5185 if (VR_idx != NumVRs) {
5186 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
5187 Arg.getSimpleValueType() == MVT::v2i64) ?
5188 VSRH[VR_idx] : VR[VR_idx];
5191 RegsToPass.push_back(std::make_pair(VReg, Arg));
5193 if (CallConv == CallingConv::Fast)
5196 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5197 true, isTailCall, true, MemOpChains,
5198 TailCallArguments, dl);
5199 if (CallConv == CallingConv::Fast)
5203 if (CallConv != CallingConv::Fast)
5208 assert(Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32 &&
5209 "Invalid QPX parameter type");
5214 bool IsF32 = Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32;
5216 // We could elide this store in the case where the object fits
5217 // entirely in R registers. Maybe later.
5218 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5219 MachinePointerInfo(), false, false, 0);
5220 MemOpChains.push_back(Store);
5221 if (QFPR_idx != NumQFPRs) {
5222 SDValue Load = DAG.getLoad(IsF32 ? MVT::v4f32 : MVT::v4f64, dl,
5223 Store, PtrOff, MachinePointerInfo(),
5224 false, false, false, 0);
5225 MemOpChains.push_back(Load.getValue(1));
5226 RegsToPass.push_back(std::make_pair(QFPR[QFPR_idx++], Load));
5228 ArgOffset += (IsF32 ? 16 : 32);
5229 for (unsigned i = 0; i < (IsF32 ? 16U : 32U); i += PtrByteSize) {
5230 if (GPR_idx == NumGPRs)
5232 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5233 DAG.getConstant(i, dl, PtrVT));
5234 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5235 false, false, false, 0);
5236 MemOpChains.push_back(Load.getValue(1));
5237 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5242 // Non-varargs QPX params go into registers or on the stack.
5243 if (QFPR_idx != NumQFPRs) {
5244 RegsToPass.push_back(std::make_pair(QFPR[QFPR_idx++], Arg));
5246 if (CallConv == CallingConv::Fast)
5249 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5250 true, isTailCall, true, MemOpChains,
5251 TailCallArguments, dl);
5252 if (CallConv == CallingConv::Fast)
5253 ArgOffset += (IsF32 ? 16 : 32);
5256 if (CallConv != CallingConv::Fast)
5257 ArgOffset += (IsF32 ? 16 : 32);
5263 assert(NumBytesActuallyUsed == ArgOffset);
5264 (void)NumBytesActuallyUsed;
5266 if (!MemOpChains.empty())
5267 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5269 // Check if this is an indirect call (MTCTR/BCTRL).
5270 // See PrepareCall() for more information about calls through function
5271 // pointers in the 64-bit SVR4 ABI.
5272 if (!isTailCall && !IsPatchPoint &&
5273 !isFunctionGlobalAddress(Callee) &&
5274 !isa<ExternalSymbolSDNode>(Callee)) {
5275 // Load r2 into a virtual register and store it to the TOC save area.
5276 setUsesTOCBasePtr(DAG);
5277 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
5278 // TOC save area offset.
5279 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
5280 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset, dl);
5281 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
5282 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr,
5283 MachinePointerInfo::getStack(TOCSaveOffset),
5285 // In the ELFv2 ABI, R12 must contain the address of an indirect callee.
5286 // This does not mean the MTCTR instruction must use R12; it's easier
5287 // to model this as an extra parameter, so do that.
5288 if (isELFv2ABI && !IsPatchPoint)
5289 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
5292 // Build a sequence of copy-to-reg nodes chained together with token chain
5293 // and flag operands which copy the outgoing args into the appropriate regs.
5295 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5296 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5297 RegsToPass[i].second, InFlag);
5298 InFlag = Chain.getValue(1);
5302 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
5303 FPOp, true, TailCallArguments);
5305 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint, DAG,
5306 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
5307 NumBytes, Ins, InVals, CS);
5311 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
5312 CallingConv::ID CallConv, bool isVarArg,
5313 bool isTailCall, bool IsPatchPoint,
5314 const SmallVectorImpl<ISD::OutputArg> &Outs,
5315 const SmallVectorImpl<SDValue> &OutVals,
5316 const SmallVectorImpl<ISD::InputArg> &Ins,
5317 SDLoc dl, SelectionDAG &DAG,
5318 SmallVectorImpl<SDValue> &InVals,
5319 ImmutableCallSite *CS) const {
5321 unsigned NumOps = Outs.size();
5323 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5324 bool isPPC64 = PtrVT == MVT::i64;
5325 unsigned PtrByteSize = isPPC64 ? 8 : 4;
5327 MachineFunction &MF = DAG.getMachineFunction();
5329 // Mark this function as potentially containing a function that contains a
5330 // tail call. As a consequence the frame pointer will be used for dynamicalloc
5331 // and restoring the callers stack pointer in this functions epilog. This is
5332 // done because by tail calling the called function might overwrite the value
5333 // in this function's (MF) stack pointer stack slot 0(SP).
5334 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5335 CallConv == CallingConv::Fast)
5336 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
5338 // Count how many bytes are to be pushed on the stack, including the linkage
5339 // area, and parameter passing area. We start with 24/48 bytes, which is
5340 // prereserved space for [SP][CR][LR][3 x unused].
5341 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
5342 unsigned NumBytes = LinkageSize;
5344 // Add up all the space actually used.
5345 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
5346 // they all go in registers, but we must reserve stack space for them for
5347 // possible use by the caller. In varargs or 64-bit calls, parameters are
5348 // assigned stack space in order, with padding so Altivec parameters are
5350 unsigned nAltivecParamsAtEnd = 0;
5351 for (unsigned i = 0; i != NumOps; ++i) {
5352 ISD::ArgFlagsTy Flags = Outs[i].Flags;
5353 EVT ArgVT = Outs[i].VT;
5354 // Varargs Altivec parameters are padded to a 16 byte boundary.
5355 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
5356 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
5357 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) {
5358 if (!isVarArg && !isPPC64) {
5359 // Non-varargs Altivec parameters go after all the non-Altivec
5360 // parameters; handle those later so we know how much padding we need.
5361 nAltivecParamsAtEnd++;
5364 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
5365 NumBytes = ((NumBytes+15)/16)*16;
5367 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
5370 // Allow for Altivec parameters at the end, if needed.
5371 if (nAltivecParamsAtEnd) {
5372 NumBytes = ((NumBytes+15)/16)*16;
5373 NumBytes += 16*nAltivecParamsAtEnd;
5376 // The prolog code of the callee may store up to 8 GPR argument registers to
5377 // the stack, allowing va_start to index over them in memory if its varargs.
5378 // Because we cannot tell if this is needed on the caller side, we have to
5379 // conservatively assume that it is needed. As such, make sure we have at
5380 // least enough stack space for the caller to store the 8 GPRs.
5381 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
5383 // Tail call needs the stack to be aligned.
5384 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5385 CallConv == CallingConv::Fast)
5386 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes);
5388 // Calculate by how many bytes the stack has to be adjusted in case of tail
5389 // call optimization.
5390 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
5392 // To protect arguments on the stack from being clobbered in a tail call,
5393 // force all the loads to happen before doing any other lowering.
5395 Chain = DAG.getStackArgumentTokenFactor(Chain);
5397 // Adjust the stack pointer for the new arguments...
5398 // These operations are automatically eliminated by the prolog/epilog pass
5399 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
5401 SDValue CallSeqStart = Chain;
5403 // Load the return address and frame pointer so it can be move somewhere else
5406 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
5409 // Set up a copy of the stack pointer for use loading and storing any
5410 // arguments that may not fit in the registers available for argument
5414 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
5416 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
5418 // Figure out which arguments are going to go in registers, and which in
5419 // memory. Also, if this is a vararg function, floating point operations
5420 // must be stored to our stack, and loaded into integer regs as well, if
5421 // any integer regs are available for argument passing.
5422 unsigned ArgOffset = LinkageSize;
5423 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
5425 static const MCPhysReg GPR_32[] = { // 32-bit registers.
5426 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
5427 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
5429 static const MCPhysReg GPR_64[] = { // 64-bit registers.
5430 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
5431 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
5433 static const MCPhysReg VR[] = {
5434 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
5435 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
5437 const unsigned NumGPRs = array_lengthof(GPR_32);
5438 const unsigned NumFPRs = 13;
5439 const unsigned NumVRs = array_lengthof(VR);
5441 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
5443 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
5444 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
5446 SmallVector<SDValue, 8> MemOpChains;
5447 for (unsigned i = 0; i != NumOps; ++i) {
5448 SDValue Arg = OutVals[i];
5449 ISD::ArgFlagsTy Flags = Outs[i].Flags;
5451 // PtrOff will be used to store the current argument to the stack if a
5452 // register cannot be found for it.
5455 PtrOff = DAG.getConstant(ArgOffset, dl, StackPtr.getValueType());
5457 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
5459 // On PPC64, promote integers to 64-bit values.
5460 if (isPPC64 && Arg.getValueType() == MVT::i32) {
5461 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
5462 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
5463 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
5466 // FIXME memcpy is used way more than necessary. Correctness first.
5467 // Note: "by value" is code for passing a structure by value, not
5469 if (Flags.isByVal()) {
5470 unsigned Size = Flags.getByValSize();
5471 // Very small objects are passed right-justified. Everything else is
5472 // passed left-justified.
5473 if (Size==1 || Size==2) {
5474 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
5475 if (GPR_idx != NumGPRs) {
5476 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
5477 MachinePointerInfo(), VT,
5478 false, false, false, 0);
5479 MemOpChains.push_back(Load.getValue(1));
5480 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5482 ArgOffset += PtrByteSize;
5484 SDValue Const = DAG.getConstant(PtrByteSize - Size, dl,
5485 PtrOff.getValueType());
5486 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
5487 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
5490 ArgOffset += PtrByteSize;
5494 // Copy entire object into memory. There are cases where gcc-generated
5495 // code assumes it is there, even if it could be put entirely into
5496 // registers. (This is not what the doc says.)
5497 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
5501 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
5502 // copy the pieces of the object that fit into registers from the
5503 // parameter save area.
5504 for (unsigned j=0; j<Size; j+=PtrByteSize) {
5505 SDValue Const = DAG.getConstant(j, dl, PtrOff.getValueType());
5506 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
5507 if (GPR_idx != NumGPRs) {
5508 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
5509 MachinePointerInfo(),
5510 false, false, false, 0);
5511 MemOpChains.push_back(Load.getValue(1));
5512 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5513 ArgOffset += PtrByteSize;
5515 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
5522 switch (Arg.getSimpleValueType().SimpleTy) {
5523 default: llvm_unreachable("Unexpected ValueType for argument!");
5527 if (GPR_idx != NumGPRs) {
5528 if (Arg.getValueType() == MVT::i1)
5529 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
5531 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
5533 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5534 isPPC64, isTailCall, false, MemOpChains,
5535 TailCallArguments, dl);
5537 ArgOffset += PtrByteSize;
5541 if (FPR_idx != NumFPRs) {
5542 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
5545 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5546 MachinePointerInfo(), false, false, 0);
5547 MemOpChains.push_back(Store);
5549 // Float varargs are always shadowed in available integer registers
5550 if (GPR_idx != NumGPRs) {
5551 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
5552 MachinePointerInfo(), false, false,
5554 MemOpChains.push_back(Load.getValue(1));
5555 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5557 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
5558 SDValue ConstFour = DAG.getConstant(4, dl, PtrOff.getValueType());
5559 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
5560 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
5561 MachinePointerInfo(),
5562 false, false, false, 0);
5563 MemOpChains.push_back(Load.getValue(1));
5564 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5567 // If we have any FPRs remaining, we may also have GPRs remaining.
5568 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
5570 if (GPR_idx != NumGPRs)
5572 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
5573 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
5577 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5578 isPPC64, isTailCall, false, MemOpChains,
5579 TailCallArguments, dl);
5583 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
5590 // These go aligned on the stack, or in the corresponding R registers
5591 // when within range. The Darwin PPC ABI doc claims they also go in
5592 // V registers; in fact gcc does this only for arguments that are
5593 // prototyped, not for those that match the ... We do it for all
5594 // arguments, seems to work.
5595 while (ArgOffset % 16 !=0) {
5596 ArgOffset += PtrByteSize;
5597 if (GPR_idx != NumGPRs)
5600 // We could elide this store in the case where the object fits
5601 // entirely in R registers. Maybe later.
5602 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
5603 DAG.getConstant(ArgOffset, dl, PtrVT));
5604 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5605 MachinePointerInfo(), false, false, 0);
5606 MemOpChains.push_back(Store);
5607 if (VR_idx != NumVRs) {
5608 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
5609 MachinePointerInfo(),
5610 false, false, false, 0);
5611 MemOpChains.push_back(Load.getValue(1));
5612 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
5615 for (unsigned i=0; i<16; i+=PtrByteSize) {
5616 if (GPR_idx == NumGPRs)
5618 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5619 DAG.getConstant(i, dl, PtrVT));
5620 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5621 false, false, false, 0);
5622 MemOpChains.push_back(Load.getValue(1));
5623 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5628 // Non-varargs Altivec params generally go in registers, but have
5629 // stack space allocated at the end.
5630 if (VR_idx != NumVRs) {
5631 // Doesn't have GPR space allocated.
5632 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
5633 } else if (nAltivecParamsAtEnd==0) {
5634 // We are emitting Altivec params in order.
5635 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5636 isPPC64, isTailCall, true, MemOpChains,
5637 TailCallArguments, dl);
5643 // If all Altivec parameters fit in registers, as they usually do,
5644 // they get stack space following the non-Altivec parameters. We
5645 // don't track this here because nobody below needs it.
5646 // If there are more Altivec parameters than fit in registers emit
5648 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
5650 // Offset is aligned; skip 1st 12 params which go in V registers.
5651 ArgOffset = ((ArgOffset+15)/16)*16;
5653 for (unsigned i = 0; i != NumOps; ++i) {
5654 SDValue Arg = OutVals[i];
5655 EVT ArgType = Outs[i].VT;
5656 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
5657 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
5660 // We are emitting Altivec params in order.
5661 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5662 isPPC64, isTailCall, true, MemOpChains,
5663 TailCallArguments, dl);
5670 if (!MemOpChains.empty())
5671 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5673 // On Darwin, R12 must contain the address of an indirect callee. This does
5674 // not mean the MTCTR instruction must use R12; it's easier to model this as
5675 // an extra parameter, so do that.
5677 !isFunctionGlobalAddress(Callee) &&
5678 !isa<ExternalSymbolSDNode>(Callee) &&
5679 !isBLACompatibleAddress(Callee, DAG))
5680 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
5681 PPC::R12), Callee));
5683 // Build a sequence of copy-to-reg nodes chained together with token chain
5684 // and flag operands which copy the outgoing args into the appropriate regs.
5686 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5687 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5688 RegsToPass[i].second, InFlag);
5689 InFlag = Chain.getValue(1);
5693 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
5694 FPOp, true, TailCallArguments);
5696 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint, DAG,
5697 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
5698 NumBytes, Ins, InVals, CS);
5702 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
5703 MachineFunction &MF, bool isVarArg,
5704 const SmallVectorImpl<ISD::OutputArg> &Outs,
5705 LLVMContext &Context) const {
5706 SmallVector<CCValAssign, 16> RVLocs;
5707 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
5708 return CCInfo.CheckReturn(Outs, RetCC_PPC);
5712 PPCTargetLowering::LowerReturn(SDValue Chain,
5713 CallingConv::ID CallConv, bool isVarArg,
5714 const SmallVectorImpl<ISD::OutputArg> &Outs,
5715 const SmallVectorImpl<SDValue> &OutVals,
5716 SDLoc dl, SelectionDAG &DAG) const {
5718 SmallVector<CCValAssign, 16> RVLocs;
5719 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
5721 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
5724 SmallVector<SDValue, 4> RetOps(1, Chain);
5726 // Copy the result values into the output registers.
5727 for (unsigned i = 0; i != RVLocs.size(); ++i) {
5728 CCValAssign &VA = RVLocs[i];
5729 assert(VA.isRegLoc() && "Can only return in registers!");
5731 SDValue Arg = OutVals[i];
5733 switch (VA.getLocInfo()) {
5734 default: llvm_unreachable("Unknown loc info!");
5735 case CCValAssign::Full: break;
5736 case CCValAssign::AExt:
5737 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
5739 case CCValAssign::ZExt:
5740 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
5742 case CCValAssign::SExt:
5743 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
5747 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
5748 Flag = Chain.getValue(1);
5749 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
5752 RetOps[0] = Chain; // Update chain.
5754 // Add the flag if we have it.
5756 RetOps.push_back(Flag);
5758 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
5761 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
5762 const PPCSubtarget &Subtarget) const {
5763 // When we pop the dynamic allocation we need to restore the SP link.
5766 // Get the corect type for pointers.
5767 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5769 // Construct the stack pointer operand.
5770 bool isPPC64 = Subtarget.isPPC64();
5771 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
5772 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
5774 // Get the operands for the STACKRESTORE.
5775 SDValue Chain = Op.getOperand(0);
5776 SDValue SaveSP = Op.getOperand(1);
5778 // Load the old link SP.
5779 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
5780 MachinePointerInfo(),
5781 false, false, false, 0);
5783 // Restore the stack pointer.
5784 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
5786 // Store the old link SP.
5787 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
5794 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
5795 MachineFunction &MF = DAG.getMachineFunction();
5796 bool isPPC64 = Subtarget.isPPC64();
5797 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5799 // Get current frame pointer save index. The users of this index will be
5800 // primarily DYNALLOC instructions.
5801 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5802 int RASI = FI->getReturnAddrSaveIndex();
5804 // If the frame pointer save index hasn't been defined yet.
5806 // Find out what the fix offset of the frame pointer save area.
5807 int LROffset = Subtarget.getFrameLowering()->getReturnSaveOffset();
5808 // Allocate the frame index for frame pointer save area.
5809 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, false);
5811 FI->setReturnAddrSaveIndex(RASI);
5813 return DAG.getFrameIndex(RASI, PtrVT);
5817 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
5818 MachineFunction &MF = DAG.getMachineFunction();
5819 bool isPPC64 = Subtarget.isPPC64();
5820 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5822 // Get current frame pointer save index. The users of this index will be
5823 // primarily DYNALLOC instructions.
5824 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5825 int FPSI = FI->getFramePointerSaveIndex();
5827 // If the frame pointer save index hasn't been defined yet.
5829 // Find out what the fix offset of the frame pointer save area.
5830 int FPOffset = Subtarget.getFrameLowering()->getFramePointerSaveOffset();
5831 // Allocate the frame index for frame pointer save area.
5832 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
5834 FI->setFramePointerSaveIndex(FPSI);
5836 return DAG.getFrameIndex(FPSI, PtrVT);
5839 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5841 const PPCSubtarget &Subtarget) const {
5843 SDValue Chain = Op.getOperand(0);
5844 SDValue Size = Op.getOperand(1);
5847 // Get the corect type for pointers.
5848 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5850 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
5851 DAG.getConstant(0, dl, PtrVT), Size);
5852 // Construct a node for the frame pointer save index.
5853 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
5854 // Build a DYNALLOC node.
5855 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
5856 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
5857 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
5860 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
5861 SelectionDAG &DAG) const {
5863 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
5864 DAG.getVTList(MVT::i32, MVT::Other),
5865 Op.getOperand(0), Op.getOperand(1));
5868 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
5869 SelectionDAG &DAG) const {
5871 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
5872 Op.getOperand(0), Op.getOperand(1));
5875 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
5876 if (Op.getValueType().isVector())
5877 return LowerVectorLoad(Op, DAG);
5879 assert(Op.getValueType() == MVT::i1 &&
5880 "Custom lowering only for i1 loads");
5882 // First, load 8 bits into 32 bits, then truncate to 1 bit.
5885 LoadSDNode *LD = cast<LoadSDNode>(Op);
5887 SDValue Chain = LD->getChain();
5888 SDValue BasePtr = LD->getBasePtr();
5889 MachineMemOperand *MMO = LD->getMemOperand();
5891 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(), Chain,
5892 BasePtr, MVT::i8, MMO);
5893 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
5895 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
5896 return DAG.getMergeValues(Ops, dl);
5899 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
5900 if (Op.getOperand(1).getValueType().isVector())
5901 return LowerVectorStore(Op, DAG);
5903 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
5904 "Custom lowering only for i1 stores");
5906 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
5909 StoreSDNode *ST = cast<StoreSDNode>(Op);
5911 SDValue Chain = ST->getChain();
5912 SDValue BasePtr = ST->getBasePtr();
5913 SDValue Value = ST->getValue();
5914 MachineMemOperand *MMO = ST->getMemOperand();
5916 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(), Value);
5917 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
5920 // FIXME: Remove this once the ANDI glue bug is fixed:
5921 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
5922 assert(Op.getValueType() == MVT::i1 &&
5923 "Custom lowering only for i1 results");
5926 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
5930 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
5932 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5933 // Not FP? Not a fsel.
5934 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
5935 !Op.getOperand(2).getValueType().isFloatingPoint())
5938 // We might be able to do better than this under some circumstances, but in
5939 // general, fsel-based lowering of select is a finite-math-only optimization.
5940 // For more information, see section F.3 of the 2.06 ISA specification.
5941 if (!DAG.getTarget().Options.NoInfsFPMath ||
5942 !DAG.getTarget().Options.NoNaNsFPMath)
5945 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5947 EVT ResVT = Op.getValueType();
5948 EVT CmpVT = Op.getOperand(0).getValueType();
5949 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5950 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
5953 // If the RHS of the comparison is a 0.0, we don't need to do the
5954 // subtraction at all.
5956 if (isFloatingPointZero(RHS))
5958 default: break; // SETUO etc aren't handled by fsel.
5962 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5963 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5964 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5965 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5966 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5967 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5968 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
5971 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5974 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5975 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5976 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5979 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5982 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5983 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5984 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5985 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
5990 default: break; // SETUO etc aren't handled by fsel.
5994 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5995 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5996 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5997 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5998 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5999 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
6000 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
6001 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
6004 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
6005 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6006 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6007 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
6010 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
6011 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6012 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6013 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
6016 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
6017 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6018 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6019 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
6022 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
6023 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6024 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6025 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
6030 void PPCTargetLowering::LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
6033 assert(Op.getOperand(0).getValueType().isFloatingPoint());
6034 SDValue Src = Op.getOperand(0);
6035 if (Src.getValueType() == MVT::f32)
6036 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
6039 switch (Op.getSimpleValueType().SimpleTy) {
6040 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
6043 Op.getOpcode() == ISD::FP_TO_SINT
6045 : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ),
6049 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
6050 "i64 FP_TO_UINT is supported only with FPCVT");
6051 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
6057 // Convert the FP value to an int value through memory.
6058 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
6059 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
6060 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
6061 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
6062 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
6064 // Emit a store to the stack slot.
6067 MachineFunction &MF = DAG.getMachineFunction();
6068 MachineMemOperand *MMO =
6069 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
6070 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
6071 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
6072 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
6074 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
6075 MPI, false, false, 0);
6077 // Result is a load from the stack slot. If loading 4 bytes, make sure to
6079 if (Op.getValueType() == MVT::i32 && !i32Stack) {
6080 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
6081 DAG.getConstant(4, dl, FIPtr.getValueType()));
6082 MPI = MPI.getWithOffset(4);
6090 /// \brief Custom lowers floating point to integer conversions to use
6091 /// the direct move instructions available in ISA 2.07 to avoid the
6092 /// need for load/store combinations.
6093 SDValue PPCTargetLowering::LowerFP_TO_INTDirectMove(SDValue Op,
6096 assert(Op.getOperand(0).getValueType().isFloatingPoint());
6097 SDValue Src = Op.getOperand(0);
6099 if (Src.getValueType() == MVT::f32)
6100 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
6103 switch (Op.getSimpleValueType().SimpleTy) {
6104 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
6107 Op.getOpcode() == ISD::FP_TO_SINT
6109 : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ),
6111 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i32, Tmp);
6114 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
6115 "i64 FP_TO_UINT is supported only with FPCVT");
6116 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
6119 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i64, Tmp);
6125 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
6127 if (Subtarget.hasDirectMove() && Subtarget.isPPC64())
6128 return LowerFP_TO_INTDirectMove(Op, DAG, dl);
6131 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
6133 return DAG.getLoad(Op.getValueType(), dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
6134 false, RLI.IsInvariant, RLI.Alignment, RLI.AAInfo,
6138 // We're trying to insert a regular store, S, and then a load, L. If the
6139 // incoming value, O, is a load, we might just be able to have our load use the
6140 // address used by O. However, we don't know if anything else will store to
6141 // that address before we can load from it. To prevent this situation, we need
6142 // to insert our load, L, into the chain as a peer of O. To do this, we give L
6143 // the same chain operand as O, we create a token factor from the chain results
6144 // of O and L, and we replace all uses of O's chain result with that token
6145 // factor (see spliceIntoChain below for this last part).
6146 bool PPCTargetLowering::canReuseLoadAddress(SDValue Op, EVT MemVT,
6149 ISD::LoadExtType ET) const {
6151 if (ET == ISD::NON_EXTLOAD &&
6152 (Op.getOpcode() == ISD::FP_TO_UINT ||
6153 Op.getOpcode() == ISD::FP_TO_SINT) &&
6154 isOperationLegalOrCustom(Op.getOpcode(),
6155 Op.getOperand(0).getValueType())) {
6157 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
6161 LoadSDNode *LD = dyn_cast<LoadSDNode>(Op);
6162 if (!LD || LD->getExtensionType() != ET || LD->isVolatile() ||
6163 LD->isNonTemporal())
6165 if (LD->getMemoryVT() != MemVT)
6168 RLI.Ptr = LD->getBasePtr();
6169 if (LD->isIndexed() && LD->getOffset().getOpcode() != ISD::UNDEF) {
6170 assert(LD->getAddressingMode() == ISD::PRE_INC &&
6171 "Non-pre-inc AM on PPC?");
6172 RLI.Ptr = DAG.getNode(ISD::ADD, dl, RLI.Ptr.getValueType(), RLI.Ptr,
6176 RLI.Chain = LD->getChain();
6177 RLI.MPI = LD->getPointerInfo();
6178 RLI.IsInvariant = LD->isInvariant();
6179 RLI.Alignment = LD->getAlignment();
6180 RLI.AAInfo = LD->getAAInfo();
6181 RLI.Ranges = LD->getRanges();
6183 RLI.ResChain = SDValue(LD, LD->isIndexed() ? 2 : 1);
6187 // Given the head of the old chain, ResChain, insert a token factor containing
6188 // it and NewResChain, and make users of ResChain now be users of that token
6190 void PPCTargetLowering::spliceIntoChain(SDValue ResChain,
6191 SDValue NewResChain,
6192 SelectionDAG &DAG) const {
6196 SDLoc dl(NewResChain);
6198 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6199 NewResChain, DAG.getUNDEF(MVT::Other));
6200 assert(TF.getNode() != NewResChain.getNode() &&
6201 "A new TF really is required here");
6203 DAG.ReplaceAllUsesOfValueWith(ResChain, TF);
6204 DAG.UpdateNodeOperands(TF.getNode(), ResChain, NewResChain);
6207 /// \brief Custom lowers integer to floating point conversions to use
6208 /// the direct move instructions available in ISA 2.07 to avoid the
6209 /// need for load/store combinations.
6210 SDValue PPCTargetLowering::LowerINT_TO_FPDirectMove(SDValue Op,
6213 assert((Op.getValueType() == MVT::f32 ||
6214 Op.getValueType() == MVT::f64) &&
6215 "Invalid floating point type as target of conversion");
6216 assert(Subtarget.hasFPCVT() &&
6217 "Int to FP conversions with direct moves require FPCVT");
6219 SDValue Src = Op.getOperand(0);
6220 bool SinglePrec = Op.getValueType() == MVT::f32;
6221 bool WordInt = Src.getSimpleValueType().SimpleTy == MVT::i32;
6222 bool Signed = Op.getOpcode() == ISD::SINT_TO_FP;
6223 unsigned ConvOp = Signed ? (SinglePrec ? PPCISD::FCFIDS : PPCISD::FCFID) :
6224 (SinglePrec ? PPCISD::FCFIDUS : PPCISD::FCFIDU);
6227 FP = DAG.getNode(Signed ? PPCISD::MTVSRA : PPCISD::MTVSRZ,
6229 FP = DAG.getNode(ConvOp, dl, SinglePrec ? MVT::f32 : MVT::f64, FP);
6232 FP = DAG.getNode(PPCISD::MTVSRA, dl, MVT::f64, Src);
6233 FP = DAG.getNode(ConvOp, dl, SinglePrec ? MVT::f32 : MVT::f64, FP);
6239 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
6240 SelectionDAG &DAG) const {
6243 if (Subtarget.hasQPX() && Op.getOperand(0).getValueType() == MVT::v4i1) {
6244 if (Op.getValueType() != MVT::v4f32 && Op.getValueType() != MVT::v4f64)
6247 SDValue Value = Op.getOperand(0);
6248 // The values are now known to be -1 (false) or 1 (true). To convert this
6249 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
6250 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
6251 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
6253 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::f64);
6254 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
6255 FPHalfs, FPHalfs, FPHalfs, FPHalfs);
6257 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
6259 if (Op.getValueType() != MVT::v4f64)
6260 Value = DAG.getNode(ISD::FP_ROUND, dl,
6261 Op.getValueType(), Value,
6262 DAG.getIntPtrConstant(1, dl));
6266 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
6267 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
6270 if (Op.getOperand(0).getValueType() == MVT::i1)
6271 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
6272 DAG.getConstantFP(1.0, dl, Op.getValueType()),
6273 DAG.getConstantFP(0.0, dl, Op.getValueType()));
6275 // If we have direct moves, we can do all the conversion, skip the store/load
6276 // however, without FPCVT we can't do most conversions.
6277 if (Subtarget.hasDirectMove() && Subtarget.isPPC64() && Subtarget.hasFPCVT())
6278 return LowerINT_TO_FPDirectMove(Op, DAG, dl);
6280 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
6281 "UINT_TO_FP is supported only with FPCVT");
6283 // If we have FCFIDS, then use it when converting to single-precision.
6284 // Otherwise, convert to double-precision and then round.
6285 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
6286 ? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
6288 : (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
6290 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
6294 if (Op.getOperand(0).getValueType() == MVT::i64) {
6295 SDValue SINT = Op.getOperand(0);
6296 // When converting to single-precision, we actually need to convert
6297 // to double-precision first and then round to single-precision.
6298 // To avoid double-rounding effects during that operation, we have
6299 // to prepare the input operand. Bits that might be truncated when
6300 // converting to double-precision are replaced by a bit that won't
6301 // be lost at this stage, but is below the single-precision rounding
6304 // However, if -enable-unsafe-fp-math is in effect, accept double
6305 // rounding to avoid the extra overhead.
6306 if (Op.getValueType() == MVT::f32 &&
6307 !Subtarget.hasFPCVT() &&
6308 !DAG.getTarget().Options.UnsafeFPMath) {
6310 // Twiddle input to make sure the low 11 bits are zero. (If this
6311 // is the case, we are guaranteed the value will fit into the 53 bit
6312 // mantissa of an IEEE double-precision value without rounding.)
6313 // If any of those low 11 bits were not zero originally, make sure
6314 // bit 12 (value 2048) is set instead, so that the final rounding
6315 // to single-precision gets the correct result.
6316 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
6317 SINT, DAG.getConstant(2047, dl, MVT::i64));
6318 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
6319 Round, DAG.getConstant(2047, dl, MVT::i64));
6320 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
6321 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
6322 Round, DAG.getConstant(-2048, dl, MVT::i64));
6324 // However, we cannot use that value unconditionally: if the magnitude
6325 // of the input value is small, the bit-twiddling we did above might
6326 // end up visibly changing the output. Fortunately, in that case, we
6327 // don't need to twiddle bits since the original input will convert
6328 // exactly to double-precision floating-point already. Therefore,
6329 // construct a conditional to use the original value if the top 11
6330 // bits are all sign-bit copies, and use the rounded value computed
6332 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
6333 SINT, DAG.getConstant(53, dl, MVT::i32));
6334 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
6335 Cond, DAG.getConstant(1, dl, MVT::i64));
6336 Cond = DAG.getSetCC(dl, MVT::i32,
6337 Cond, DAG.getConstant(1, dl, MVT::i64), ISD::SETUGT);
6339 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
6345 MachineFunction &MF = DAG.getMachineFunction();
6346 if (canReuseLoadAddress(SINT, MVT::i64, RLI, DAG)) {
6347 Bits = DAG.getLoad(MVT::f64, dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
6348 false, RLI.IsInvariant, RLI.Alignment, RLI.AAInfo,
6350 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
6351 } else if (Subtarget.hasLFIWAX() &&
6352 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::SEXTLOAD)) {
6353 MachineMemOperand *MMO =
6354 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6355 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6356 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6357 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWAX, dl,
6358 DAG.getVTList(MVT::f64, MVT::Other),
6359 Ops, MVT::i32, MMO);
6360 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
6361 } else if (Subtarget.hasFPCVT() &&
6362 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::ZEXTLOAD)) {
6363 MachineMemOperand *MMO =
6364 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6365 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6366 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6367 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWZX, dl,
6368 DAG.getVTList(MVT::f64, MVT::Other),
6369 Ops, MVT::i32, MMO);
6370 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
6371 } else if (((Subtarget.hasLFIWAX() &&
6372 SINT.getOpcode() == ISD::SIGN_EXTEND) ||
6373 (Subtarget.hasFPCVT() &&
6374 SINT.getOpcode() == ISD::ZERO_EXTEND)) &&
6375 SINT.getOperand(0).getValueType() == MVT::i32) {
6376 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
6377 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
6379 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
6380 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6383 DAG.getStore(DAG.getEntryNode(), dl, SINT.getOperand(0), FIdx,
6384 MachinePointerInfo::getFixedStack(FrameIdx),
6387 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
6388 "Expected an i32 store");
6392 RLI.MPI = MachinePointerInfo::getFixedStack(FrameIdx);
6395 MachineMemOperand *MMO =
6396 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6397 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6398 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6399 Bits = DAG.getMemIntrinsicNode(SINT.getOpcode() == ISD::ZERO_EXTEND ?
6400 PPCISD::LFIWZX : PPCISD::LFIWAX,
6401 dl, DAG.getVTList(MVT::f64, MVT::Other),
6402 Ops, MVT::i32, MMO);
6404 Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
6406 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
6408 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
6409 FP = DAG.getNode(ISD::FP_ROUND, dl,
6410 MVT::f32, FP, DAG.getIntPtrConstant(0, dl));
6414 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
6415 "Unhandled INT_TO_FP type in custom expander!");
6416 // Since we only generate this in 64-bit mode, we can take advantage of
6417 // 64-bit registers. In particular, sign extend the input value into the
6418 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
6419 // then lfd it and fcfid it.
6420 MachineFunction &MF = DAG.getMachineFunction();
6421 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
6422 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
6425 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
6428 if (!(ReusingLoad = canReuseLoadAddress(Op.getOperand(0), MVT::i32, RLI,
6430 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
6431 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6433 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
6434 MachinePointerInfo::getFixedStack(FrameIdx),
6437 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
6438 "Expected an i32 store");
6442 RLI.MPI = MachinePointerInfo::getFixedStack(FrameIdx);
6446 MachineMemOperand *MMO =
6447 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6448 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6449 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6450 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
6451 PPCISD::LFIWZX : PPCISD::LFIWAX,
6452 dl, DAG.getVTList(MVT::f64, MVT::Other),
6453 Ops, MVT::i32, MMO);
6455 spliceIntoChain(RLI.ResChain, Ld.getValue(1), DAG);
6457 assert(Subtarget.isPPC64() &&
6458 "i32->FP without LFIWAX supported only on PPC64");
6460 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
6461 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6463 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
6466 // STD the extended value into the stack slot.
6467 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
6468 MachinePointerInfo::getFixedStack(FrameIdx),
6471 // Load the value as a double.
6472 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
6473 MachinePointerInfo::getFixedStack(FrameIdx),
6474 false, false, false, 0);
6477 // FCFID it and return it.
6478 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
6479 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
6480 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP,
6481 DAG.getIntPtrConstant(0, dl));
6485 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
6486 SelectionDAG &DAG) const {
6489 The rounding mode is in bits 30:31 of FPSR, and has the following
6496 FLT_ROUNDS, on the other hand, expects the following:
6503 To perform the conversion, we do:
6504 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
6507 MachineFunction &MF = DAG.getMachineFunction();
6508 EVT VT = Op.getValueType();
6509 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
6511 // Save FP Control Word to register
6513 MVT::f64, // return register
6514 MVT::Glue // unused in this context
6516 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
6518 // Save FP register to stack slot
6519 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
6520 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
6521 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
6522 StackSlot, MachinePointerInfo(), false, false,0);
6524 // Load FP Control Word from low 32 bits of stack slot.
6525 SDValue Four = DAG.getConstant(4, dl, PtrVT);
6526 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
6527 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
6528 false, false, false, 0);
6530 // Transform as necessary
6532 DAG.getNode(ISD::AND, dl, MVT::i32,
6533 CWD, DAG.getConstant(3, dl, MVT::i32));
6535 DAG.getNode(ISD::SRL, dl, MVT::i32,
6536 DAG.getNode(ISD::AND, dl, MVT::i32,
6537 DAG.getNode(ISD::XOR, dl, MVT::i32,
6538 CWD, DAG.getConstant(3, dl, MVT::i32)),
6539 DAG.getConstant(3, dl, MVT::i32)),
6540 DAG.getConstant(1, dl, MVT::i32));
6543 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
6545 return DAG.getNode((VT.getSizeInBits() < 16 ?
6546 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
6549 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
6550 EVT VT = Op.getValueType();
6551 unsigned BitWidth = VT.getSizeInBits();
6553 assert(Op.getNumOperands() == 3 &&
6554 VT == Op.getOperand(1).getValueType() &&
6557 // Expand into a bunch of logical ops. Note that these ops
6558 // depend on the PPC behavior for oversized shift amounts.
6559 SDValue Lo = Op.getOperand(0);
6560 SDValue Hi = Op.getOperand(1);
6561 SDValue Amt = Op.getOperand(2);
6562 EVT AmtVT = Amt.getValueType();
6564 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6565 DAG.getConstant(BitWidth, dl, AmtVT), Amt);
6566 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
6567 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
6568 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
6569 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6570 DAG.getConstant(-BitWidth, dl, AmtVT));
6571 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
6572 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
6573 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
6574 SDValue OutOps[] = { OutLo, OutHi };
6575 return DAG.getMergeValues(OutOps, dl);
6578 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
6579 EVT VT = Op.getValueType();
6581 unsigned BitWidth = VT.getSizeInBits();
6582 assert(Op.getNumOperands() == 3 &&
6583 VT == Op.getOperand(1).getValueType() &&
6586 // Expand into a bunch of logical ops. Note that these ops
6587 // depend on the PPC behavior for oversized shift amounts.
6588 SDValue Lo = Op.getOperand(0);
6589 SDValue Hi = Op.getOperand(1);
6590 SDValue Amt = Op.getOperand(2);
6591 EVT AmtVT = Amt.getValueType();
6593 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6594 DAG.getConstant(BitWidth, dl, AmtVT), Amt);
6595 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
6596 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
6597 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
6598 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6599 DAG.getConstant(-BitWidth, dl, AmtVT));
6600 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
6601 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
6602 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
6603 SDValue OutOps[] = { OutLo, OutHi };
6604 return DAG.getMergeValues(OutOps, dl);
6607 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
6609 EVT VT = Op.getValueType();
6610 unsigned BitWidth = VT.getSizeInBits();
6611 assert(Op.getNumOperands() == 3 &&
6612 VT == Op.getOperand(1).getValueType() &&
6615 // Expand into a bunch of logical ops, followed by a select_cc.
6616 SDValue Lo = Op.getOperand(0);
6617 SDValue Hi = Op.getOperand(1);
6618 SDValue Amt = Op.getOperand(2);
6619 EVT AmtVT = Amt.getValueType();
6621 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6622 DAG.getConstant(BitWidth, dl, AmtVT), Amt);
6623 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
6624 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
6625 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
6626 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6627 DAG.getConstant(-BitWidth, dl, AmtVT));
6628 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
6629 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
6630 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, dl, AmtVT),
6631 Tmp4, Tmp6, ISD::SETLE);
6632 SDValue OutOps[] = { OutLo, OutHi };
6633 return DAG.getMergeValues(OutOps, dl);
6636 //===----------------------------------------------------------------------===//
6637 // Vector related lowering.
6640 /// BuildSplatI - Build a canonical splati of Val with an element size of
6641 /// SplatSize. Cast the result to VT.
6642 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
6643 SelectionDAG &DAG, SDLoc dl) {
6644 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
6646 static const MVT VTys[] = { // canonical VT to use for each size.
6647 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
6650 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
6652 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
6656 EVT CanonicalVT = VTys[SplatSize-1];
6658 // Build a canonical splat for this value.
6659 SDValue Elt = DAG.getConstant(Val, dl, MVT::i32);
6660 SmallVector<SDValue, 8> Ops;
6661 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
6662 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
6663 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
6666 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
6667 /// specified intrinsic ID.
6668 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
6669 SelectionDAG &DAG, SDLoc dl,
6670 EVT DestVT = MVT::Other) {
6671 if (DestVT == MVT::Other) DestVT = Op.getValueType();
6672 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6673 DAG.getConstant(IID, dl, MVT::i32), Op);
6676 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
6677 /// specified intrinsic ID.
6678 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
6679 SelectionDAG &DAG, SDLoc dl,
6680 EVT DestVT = MVT::Other) {
6681 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
6682 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6683 DAG.getConstant(IID, dl, MVT::i32), LHS, RHS);
6686 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
6687 /// specified intrinsic ID.
6688 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
6689 SDValue Op2, SelectionDAG &DAG,
6690 SDLoc dl, EVT DestVT = MVT::Other) {
6691 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
6692 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6693 DAG.getConstant(IID, dl, MVT::i32), Op0, Op1, Op2);
6697 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
6698 /// amount. The result has the specified value type.
6699 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
6700 EVT VT, SelectionDAG &DAG, SDLoc dl) {
6701 // Force LHS/RHS to be the right type.
6702 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
6703 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
6706 for (unsigned i = 0; i != 16; ++i)
6708 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
6709 return DAG.getNode(ISD::BITCAST, dl, VT, T);
6712 // If this is a case we can't handle, return null and let the default
6713 // expansion code take care of it. If we CAN select this case, and if it
6714 // selects to a single instruction, return Op. Otherwise, if we can codegen
6715 // this case more efficiently than a constant pool load, lower it to the
6716 // sequence of ops that should be used.
6717 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
6718 SelectionDAG &DAG) const {
6720 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6721 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
6723 if (Subtarget.hasQPX() && Op.getValueType() == MVT::v4i1) {
6724 // We first build an i32 vector, load it into a QPX register,
6725 // then convert it to a floating-point vector and compare it
6726 // to a zero vector to get the boolean result.
6727 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6728 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
6729 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FrameIdx);
6730 EVT PtrVT = getPointerTy();
6731 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6733 assert(BVN->getNumOperands() == 4 &&
6734 "BUILD_VECTOR for v4i1 does not have 4 operands");
6736 bool IsConst = true;
6737 for (unsigned i = 0; i < 4; ++i) {
6738 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF) continue;
6739 if (!isa<ConstantSDNode>(BVN->getOperand(i))) {
6747 ConstantFP::get(Type::getFloatTy(*DAG.getContext()), 1.0);
6749 ConstantFP::get(Type::getFloatTy(*DAG.getContext()), -1.0);
6751 SmallVector<Constant*, 4> CV(4, NegOne);
6752 for (unsigned i = 0; i < 4; ++i) {
6753 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF)
6754 CV[i] = UndefValue::get(Type::getFloatTy(*DAG.getContext()));
6755 else if (cast<ConstantSDNode>(BVN->getOperand(i))->
6756 getConstantIntValue()->isZero())
6762 Constant *CP = ConstantVector::get(CV);
6763 SDValue CPIdx = DAG.getConstantPool(CP, getPointerTy(),
6764 16 /* alignment */);
6766 SmallVector<SDValue, 2> Ops;
6767 Ops.push_back(DAG.getEntryNode());
6768 Ops.push_back(CPIdx);
6770 SmallVector<EVT, 2> ValueVTs;
6771 ValueVTs.push_back(MVT::v4i1);
6772 ValueVTs.push_back(MVT::Other); // chain
6773 SDVTList VTs = DAG.getVTList(ValueVTs);
6775 return DAG.getMemIntrinsicNode(PPCISD::QVLFSb,
6776 dl, VTs, Ops, MVT::v4f32,
6777 MachinePointerInfo::getConstantPool());
6780 SmallVector<SDValue, 4> Stores;
6781 for (unsigned i = 0; i < 4; ++i) {
6782 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF) continue;
6784 unsigned Offset = 4*i;
6785 SDValue Idx = DAG.getConstant(Offset, dl, FIdx.getValueType());
6786 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
6788 unsigned StoreSize = BVN->getOperand(i).getValueType().getStoreSize();
6789 if (StoreSize > 4) {
6790 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
6791 BVN->getOperand(i), Idx,
6792 PtrInfo.getWithOffset(Offset),
6793 MVT::i32, false, false, 0));
6795 SDValue StoreValue = BVN->getOperand(i);
6797 StoreValue = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, StoreValue);
6799 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
6801 PtrInfo.getWithOffset(Offset),
6807 if (!Stores.empty())
6808 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
6810 StoreChain = DAG.getEntryNode();
6812 // Now load from v4i32 into the QPX register; this will extend it to
6813 // v4i64 but not yet convert it to a floating point. Nevertheless, this
6814 // is typed as v4f64 because the QPX register integer states are not
6815 // explicitly represented.
6817 SmallVector<SDValue, 2> Ops;
6818 Ops.push_back(StoreChain);
6819 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvlfiwz, dl, MVT::i32));
6820 Ops.push_back(FIdx);
6822 SmallVector<EVT, 2> ValueVTs;
6823 ValueVTs.push_back(MVT::v4f64);
6824 ValueVTs.push_back(MVT::Other); // chain
6825 SDVTList VTs = DAG.getVTList(ValueVTs);
6827 SDValue LoadedVect = DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN,
6828 dl, VTs, Ops, MVT::v4i32, PtrInfo);
6829 LoadedVect = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
6830 DAG.getConstant(Intrinsic::ppc_qpx_qvfcfidu, dl, MVT::i32),
6833 SDValue FPZeros = DAG.getConstantFP(0.0, dl, MVT::f64);
6834 FPZeros = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
6835 FPZeros, FPZeros, FPZeros, FPZeros);
6837 return DAG.getSetCC(dl, MVT::v4i1, LoadedVect, FPZeros, ISD::SETEQ);
6840 // All other QPX vectors are handled by generic code.
6841 if (Subtarget.hasQPX())
6844 // Check if this is a splat of a constant value.
6845 APInt APSplatBits, APSplatUndef;
6846 unsigned SplatBitSize;
6848 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
6849 HasAnyUndefs, 0, !Subtarget.isLittleEndian()) ||
6853 unsigned SplatBits = APSplatBits.getZExtValue();
6854 unsigned SplatUndef = APSplatUndef.getZExtValue();
6855 unsigned SplatSize = SplatBitSize / 8;
6857 // First, handle single instruction cases.
6860 if (SplatBits == 0) {
6861 // Canonicalize all zero vectors to be v4i32.
6862 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
6863 SDValue Z = DAG.getConstant(0, dl, MVT::i32);
6864 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
6865 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
6870 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
6871 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
6873 if (SextVal >= -16 && SextVal <= 15)
6874 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
6877 // Two instruction sequences.
6879 // If this value is in the range [-32,30] and is even, use:
6880 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
6881 // If this value is in the range [17,31] and is odd, use:
6882 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
6883 // If this value is in the range [-31,-17] and is odd, use:
6884 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
6885 // Note the last two are three-instruction sequences.
6886 if (SextVal >= -32 && SextVal <= 31) {
6887 // To avoid having these optimizations undone by constant folding,
6888 // we convert to a pseudo that will be expanded later into one of
6890 SDValue Elt = DAG.getConstant(SextVal, dl, MVT::i32);
6891 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
6892 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
6893 SDValue EltSize = DAG.getConstant(SplatSize, dl, MVT::i32);
6894 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
6895 if (VT == Op.getValueType())
6898 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
6901 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
6902 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
6904 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
6905 // Make -1 and vspltisw -1:
6906 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
6908 // Make the VSLW intrinsic, computing 0x8000_0000.
6909 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
6912 // xor by OnesV to invert it.
6913 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
6914 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6917 // Check to see if this is a wide variety of vsplti*, binop self cases.
6918 static const signed char SplatCsts[] = {
6919 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
6920 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
6923 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
6924 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
6925 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
6926 int i = SplatCsts[idx];
6928 // Figure out what shift amount will be used by altivec if shifted by i in
6930 unsigned TypeShiftAmt = i & (SplatBitSize-1);
6932 // vsplti + shl self.
6933 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
6934 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6935 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6936 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
6937 Intrinsic::ppc_altivec_vslw
6939 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6940 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6943 // vsplti + srl self.
6944 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
6945 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6946 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6947 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
6948 Intrinsic::ppc_altivec_vsrw
6950 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6951 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6954 // vsplti + sra self.
6955 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
6956 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6957 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6958 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
6959 Intrinsic::ppc_altivec_vsraw
6961 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6962 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6965 // vsplti + rol self.
6966 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
6967 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
6968 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6969 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6970 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
6971 Intrinsic::ppc_altivec_vrlw
6973 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6974 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6977 // t = vsplti c, result = vsldoi t, t, 1
6978 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
6979 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
6980 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
6982 // t = vsplti c, result = vsldoi t, t, 2
6983 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
6984 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
6985 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
6987 // t = vsplti c, result = vsldoi t, t, 3
6988 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
6989 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
6990 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
6997 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
6998 /// the specified operations to build the shuffle.
6999 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
7000 SDValue RHS, SelectionDAG &DAG,
7002 unsigned OpNum = (PFEntry >> 26) & 0x0F;
7003 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
7004 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
7007 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
7019 if (OpNum == OP_COPY) {
7020 if (LHSID == (1*9+2)*9+3) return LHS;
7021 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
7025 SDValue OpLHS, OpRHS;
7026 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
7027 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
7031 default: llvm_unreachable("Unknown i32 permute!");
7033 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
7034 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
7035 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
7036 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
7039 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
7040 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
7041 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
7042 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
7045 for (unsigned i = 0; i != 16; ++i)
7046 ShufIdxs[i] = (i&3)+0;
7049 for (unsigned i = 0; i != 16; ++i)
7050 ShufIdxs[i] = (i&3)+4;
7053 for (unsigned i = 0; i != 16; ++i)
7054 ShufIdxs[i] = (i&3)+8;
7057 for (unsigned i = 0; i != 16; ++i)
7058 ShufIdxs[i] = (i&3)+12;
7061 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
7063 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
7065 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
7067 EVT VT = OpLHS.getValueType();
7068 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
7069 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
7070 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
7071 return DAG.getNode(ISD::BITCAST, dl, VT, T);
7074 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
7075 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
7076 /// return the code it can be lowered into. Worst case, it can always be
7077 /// lowered into a vperm.
7078 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
7079 SelectionDAG &DAG) const {
7081 SDValue V1 = Op.getOperand(0);
7082 SDValue V2 = Op.getOperand(1);
7083 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7084 EVT VT = Op.getValueType();
7085 bool isLittleEndian = Subtarget.isLittleEndian();
7087 if (Subtarget.hasQPX()) {
7088 if (VT.getVectorNumElements() != 4)
7091 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
7093 int AlignIdx = PPC::isQVALIGNIShuffleMask(SVOp);
7094 if (AlignIdx != -1) {
7095 return DAG.getNode(PPCISD::QVALIGNI, dl, VT, V1, V2,
7096 DAG.getConstant(AlignIdx, dl, MVT::i32));
7097 } else if (SVOp->isSplat()) {
7098 int SplatIdx = SVOp->getSplatIndex();
7099 if (SplatIdx >= 4) {
7104 // FIXME: If SplatIdx == 0 and the input came from a load, then there is
7107 return DAG.getNode(PPCISD::QVESPLATI, dl, VT, V1,
7108 DAG.getConstant(SplatIdx, dl, MVT::i32));
7111 // Lower this into a qvgpci/qvfperm pair.
7113 // Compute the qvgpci literal
7115 for (unsigned i = 0; i < 4; ++i) {
7116 int m = SVOp->getMaskElt(i);
7117 unsigned mm = m >= 0 ? (unsigned) m : i;
7118 idx |= mm << (3-i)*3;
7121 SDValue V3 = DAG.getNode(PPCISD::QVGPCI, dl, MVT::v4f64,
7122 DAG.getConstant(idx, dl, MVT::i32));
7123 return DAG.getNode(PPCISD::QVFPERM, dl, VT, V1, V2, V3);
7126 // Cases that are handled by instructions that take permute immediates
7127 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
7128 // selected by the instruction selector.
7129 if (V2.getOpcode() == ISD::UNDEF) {
7130 if (PPC::isSplatShuffleMask(SVOp, 1) ||
7131 PPC::isSplatShuffleMask(SVOp, 2) ||
7132 PPC::isSplatShuffleMask(SVOp, 4) ||
7133 PPC::isVPKUWUMShuffleMask(SVOp, 1, DAG) ||
7134 PPC::isVPKUHUMShuffleMask(SVOp, 1, DAG) ||
7135 PPC::isVPKUDUMShuffleMask(SVOp, 1, DAG) ||
7136 PPC::isVSLDOIShuffleMask(SVOp, 1, DAG) != -1 ||
7137 PPC::isVMRGLShuffleMask(SVOp, 1, 1, DAG) ||
7138 PPC::isVMRGLShuffleMask(SVOp, 2, 1, DAG) ||
7139 PPC::isVMRGLShuffleMask(SVOp, 4, 1, DAG) ||
7140 PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) ||
7141 PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) ||
7142 PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG) ||
7143 PPC::isVMRGEOShuffleMask(SVOp, true, 1, DAG) ||
7144 PPC::isVMRGEOShuffleMask(SVOp, false, 1, DAG)) {
7149 // Altivec has a variety of "shuffle immediates" that take two vector inputs
7150 // and produce a fixed permutation. If any of these match, do not lower to
7152 unsigned int ShuffleKind = isLittleEndian ? 2 : 0;
7153 if (PPC::isVPKUWUMShuffleMask(SVOp, ShuffleKind, DAG) ||
7154 PPC::isVPKUHUMShuffleMask(SVOp, ShuffleKind, DAG) ||
7155 PPC::isVPKUDUMShuffleMask(SVOp, ShuffleKind, DAG) ||
7156 PPC::isVSLDOIShuffleMask(SVOp, ShuffleKind, DAG) != -1 ||
7157 PPC::isVMRGLShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
7158 PPC::isVMRGLShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
7159 PPC::isVMRGLShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
7160 PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
7161 PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
7162 PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
7163 PPC::isVMRGEOShuffleMask(SVOp, true, ShuffleKind, DAG) ||
7164 PPC::isVMRGEOShuffleMask(SVOp, false, ShuffleKind, DAG))
7167 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
7168 // perfect shuffle table to emit an optimal matching sequence.
7169 ArrayRef<int> PermMask = SVOp->getMask();
7171 unsigned PFIndexes[4];
7172 bool isFourElementShuffle = true;
7173 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
7174 unsigned EltNo = 8; // Start out undef.
7175 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
7176 if (PermMask[i*4+j] < 0)
7177 continue; // Undef, ignore it.
7179 unsigned ByteSource = PermMask[i*4+j];
7180 if ((ByteSource & 3) != j) {
7181 isFourElementShuffle = false;
7186 EltNo = ByteSource/4;
7187 } else if (EltNo != ByteSource/4) {
7188 isFourElementShuffle = false;
7192 PFIndexes[i] = EltNo;
7195 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
7196 // perfect shuffle vector to determine if it is cost effective to do this as
7197 // discrete instructions, or whether we should use a vperm.
7198 // For now, we skip this for little endian until such time as we have a
7199 // little-endian perfect shuffle table.
7200 if (isFourElementShuffle && !isLittleEndian) {
7201 // Compute the index in the perfect shuffle table.
7202 unsigned PFTableIndex =
7203 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
7205 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
7206 unsigned Cost = (PFEntry >> 30);
7208 // Determining when to avoid vperm is tricky. Many things affect the cost
7209 // of vperm, particularly how many times the perm mask needs to be computed.
7210 // For example, if the perm mask can be hoisted out of a loop or is already
7211 // used (perhaps because there are multiple permutes with the same shuffle
7212 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
7213 // the loop requires an extra register.
7215 // As a compromise, we only emit discrete instructions if the shuffle can be
7216 // generated in 3 or fewer operations. When we have loop information
7217 // available, if this block is within a loop, we should avoid using vperm
7218 // for 3-operation perms and use a constant pool load instead.
7220 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
7223 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
7224 // vector that will get spilled to the constant pool.
7225 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
7227 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
7228 // that it is in input element units, not in bytes. Convert now.
7230 // For little endian, the order of the input vectors is reversed, and
7231 // the permutation mask is complemented with respect to 31. This is
7232 // necessary to produce proper semantics with the big-endian-biased vperm
7234 EVT EltVT = V1.getValueType().getVectorElementType();
7235 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
7237 SmallVector<SDValue, 16> ResultMask;
7238 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
7239 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
7241 for (unsigned j = 0; j != BytesPerElement; ++j)
7243 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement + j),
7246 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement + j, dl,
7250 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
7253 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
7256 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
7260 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
7261 /// altivec comparison. If it is, return true and fill in Opc/isDot with
7262 /// information about the intrinsic.
7263 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
7264 bool &isDot, const PPCSubtarget &Subtarget) {
7265 unsigned IntrinsicID =
7266 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
7269 switch (IntrinsicID) {
7270 default: return false;
7271 // Comparison predicates.
7272 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
7273 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
7274 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
7275 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
7276 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
7277 case Intrinsic::ppc_altivec_vcmpequd_p:
7278 if (Subtarget.hasP8Altivec()) {
7286 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
7287 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
7288 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
7289 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
7290 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
7291 case Intrinsic::ppc_altivec_vcmpgtsd_p:
7292 if (Subtarget.hasP8Altivec()) {
7300 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
7301 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
7302 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
7303 case Intrinsic::ppc_altivec_vcmpgtud_p:
7304 if (Subtarget.hasP8Altivec()) {
7313 // Normal Comparisons.
7314 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
7315 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
7316 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
7317 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
7318 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
7319 case Intrinsic::ppc_altivec_vcmpequd:
7320 if (Subtarget.hasP8Altivec()) {
7328 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
7329 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
7330 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
7331 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
7332 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
7333 case Intrinsic::ppc_altivec_vcmpgtsd:
7334 if (Subtarget.hasP8Altivec()) {
7342 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
7343 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
7344 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
7345 case Intrinsic::ppc_altivec_vcmpgtud:
7346 if (Subtarget.hasP8Altivec()) {
7358 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
7359 /// lower, do it, otherwise return null.
7360 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
7361 SelectionDAG &DAG) const {
7362 // If this is a lowered altivec predicate compare, CompareOpc is set to the
7363 // opcode number of the comparison.
7367 if (!getAltivecCompareInfo(Op, CompareOpc, isDot, Subtarget))
7368 return SDValue(); // Don't custom lower most intrinsics.
7370 // If this is a non-dot comparison, make the VCMP node and we are done.
7372 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
7373 Op.getOperand(1), Op.getOperand(2),
7374 DAG.getConstant(CompareOpc, dl, MVT::i32));
7375 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
7378 // Create the PPCISD altivec 'dot' comparison node.
7380 Op.getOperand(2), // LHS
7381 Op.getOperand(3), // RHS
7382 DAG.getConstant(CompareOpc, dl, MVT::i32)
7384 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
7385 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
7387 // Now that we have the comparison, emit a copy from the CR to a GPR.
7388 // This is flagged to the above dot comparison.
7389 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
7390 DAG.getRegister(PPC::CR6, MVT::i32),
7391 CompNode.getValue(1));
7393 // Unpack the result based on how the target uses it.
7394 unsigned BitNo; // Bit # of CR6.
7395 bool InvertBit; // Invert result?
7396 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
7397 default: // Can't happen, don't crash on invalid number though.
7398 case 0: // Return the value of the EQ bit of CR6.
7399 BitNo = 0; InvertBit = false;
7401 case 1: // Return the inverted value of the EQ bit of CR6.
7402 BitNo = 0; InvertBit = true;
7404 case 2: // Return the value of the LT bit of CR6.
7405 BitNo = 2; InvertBit = false;
7407 case 3: // Return the inverted value of the LT bit of CR6.
7408 BitNo = 2; InvertBit = true;
7412 // Shift the bit into the low position.
7413 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
7414 DAG.getConstant(8 - (3 - BitNo), dl, MVT::i32));
7416 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
7417 DAG.getConstant(1, dl, MVT::i32));
7419 // If we are supposed to, toggle the bit.
7421 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
7422 DAG.getConstant(1, dl, MVT::i32));
7426 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
7427 SelectionDAG &DAG) const {
7429 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
7430 // instructions), but for smaller types, we need to first extend up to v2i32
7431 // before doing going farther.
7432 if (Op.getValueType() == MVT::v2i64) {
7433 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
7434 if (ExtVT != MVT::v2i32) {
7435 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
7436 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
7437 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
7438 ExtVT.getVectorElementType(), 4)));
7439 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
7440 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
7441 DAG.getValueType(MVT::v2i32));
7450 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
7451 SelectionDAG &DAG) const {
7453 // Create a stack slot that is 16-byte aligned.
7454 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
7455 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
7456 EVT PtrVT = getPointerTy();
7457 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
7459 // Store the input value into Value#0 of the stack slot.
7460 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
7461 Op.getOperand(0), FIdx, MachinePointerInfo(),
7464 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
7465 false, false, false, 0);
7468 SDValue PPCTargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
7469 SelectionDAG &DAG) const {
7471 SDNode *N = Op.getNode();
7473 assert(N->getOperand(0).getValueType() == MVT::v4i1 &&
7474 "Unknown extract_vector_elt type");
7476 SDValue Value = N->getOperand(0);
7478 // The first part of this is like the store lowering except that we don't
7479 // need to track the chain.
7481 // The values are now known to be -1 (false) or 1 (true). To convert this
7482 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
7483 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
7484 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
7486 // FIXME: We can make this an f32 vector, but the BUILD_VECTOR code needs to
7487 // understand how to form the extending load.
7488 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::f64);
7489 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
7490 FPHalfs, FPHalfs, FPHalfs, FPHalfs);
7492 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
7494 // Now convert to an integer and store.
7495 Value = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
7496 DAG.getConstant(Intrinsic::ppc_qpx_qvfctiwu, dl, MVT::i32),
7499 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
7500 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
7501 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FrameIdx);
7502 EVT PtrVT = getPointerTy();
7503 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
7505 SDValue StoreChain = DAG.getEntryNode();
7506 SmallVector<SDValue, 2> Ops;
7507 Ops.push_back(StoreChain);
7508 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvstfiw, dl, MVT::i32));
7509 Ops.push_back(Value);
7510 Ops.push_back(FIdx);
7512 SmallVector<EVT, 2> ValueVTs;
7513 ValueVTs.push_back(MVT::Other); // chain
7514 SDVTList VTs = DAG.getVTList(ValueVTs);
7516 StoreChain = DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID,
7517 dl, VTs, Ops, MVT::v4i32, PtrInfo);
7519 // Extract the value requested.
7520 unsigned Offset = 4*cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
7521 SDValue Idx = DAG.getConstant(Offset, dl, FIdx.getValueType());
7522 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
7524 SDValue IntVal = DAG.getLoad(MVT::i32, dl, StoreChain, Idx,
7525 PtrInfo.getWithOffset(Offset),
7526 false, false, false, 0);
7528 if (!Subtarget.useCRBits())
7531 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, IntVal);
7534 /// Lowering for QPX v4i1 loads
7535 SDValue PPCTargetLowering::LowerVectorLoad(SDValue Op,
7536 SelectionDAG &DAG) const {
7538 LoadSDNode *LN = cast<LoadSDNode>(Op.getNode());
7539 SDValue LoadChain = LN->getChain();
7540 SDValue BasePtr = LN->getBasePtr();
7542 if (Op.getValueType() == MVT::v4f64 ||
7543 Op.getValueType() == MVT::v4f32) {
7544 EVT MemVT = LN->getMemoryVT();
7545 unsigned Alignment = LN->getAlignment();
7547 // If this load is properly aligned, then it is legal.
7548 if (Alignment >= MemVT.getStoreSize())
7551 EVT ScalarVT = Op.getValueType().getScalarType(),
7552 ScalarMemVT = MemVT.getScalarType();
7553 unsigned Stride = ScalarMemVT.getStoreSize();
7555 SmallVector<SDValue, 8> Vals, LoadChains;
7556 for (unsigned Idx = 0; Idx < 4; ++Idx) {
7558 if (ScalarVT != ScalarMemVT)
7560 DAG.getExtLoad(LN->getExtensionType(), dl, ScalarVT, LoadChain,
7562 LN->getPointerInfo().getWithOffset(Idx*Stride),
7563 ScalarMemVT, LN->isVolatile(), LN->isNonTemporal(),
7564 LN->isInvariant(), MinAlign(Alignment, Idx*Stride),
7568 DAG.getLoad(ScalarVT, dl, LoadChain, BasePtr,
7569 LN->getPointerInfo().getWithOffset(Idx*Stride),
7570 LN->isVolatile(), LN->isNonTemporal(),
7571 LN->isInvariant(), MinAlign(Alignment, Idx*Stride),
7574 if (Idx == 0 && LN->isIndexed()) {
7575 assert(LN->getAddressingMode() == ISD::PRE_INC &&
7576 "Unknown addressing mode on vector load");
7577 Load = DAG.getIndexedLoad(Load, dl, BasePtr, LN->getOffset(),
7578 LN->getAddressingMode());
7581 Vals.push_back(Load);
7582 LoadChains.push_back(Load.getValue(1));
7584 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
7585 DAG.getConstant(Stride, dl,
7586 BasePtr.getValueType()));
7589 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
7590 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl,
7591 Op.getValueType(), Vals);
7593 if (LN->isIndexed()) {
7594 SDValue RetOps[] = { Value, Vals[0].getValue(1), TF };
7595 return DAG.getMergeValues(RetOps, dl);
7598 SDValue RetOps[] = { Value, TF };
7599 return DAG.getMergeValues(RetOps, dl);
7602 assert(Op.getValueType() == MVT::v4i1 && "Unknown load to lower");
7603 assert(LN->isUnindexed() && "Indexed v4i1 loads are not supported");
7605 // To lower v4i1 from a byte array, we load the byte elements of the
7606 // vector and then reuse the BUILD_VECTOR logic.
7608 SmallVector<SDValue, 4> VectElmts, VectElmtChains;
7609 for (unsigned i = 0; i < 4; ++i) {
7610 SDValue Idx = DAG.getConstant(i, dl, BasePtr.getValueType());
7611 Idx = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, Idx);
7613 VectElmts.push_back(DAG.getExtLoad(ISD::EXTLOAD,
7614 dl, MVT::i32, LoadChain, Idx,
7615 LN->getPointerInfo().getWithOffset(i),
7616 MVT::i8 /* memory type */,
7617 LN->isVolatile(), LN->isNonTemporal(),
7619 1 /* alignment */, LN->getAAInfo()));
7620 VectElmtChains.push_back(VectElmts[i].getValue(1));
7623 LoadChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, VectElmtChains);
7624 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i1, VectElmts);
7626 SDValue RVals[] = { Value, LoadChain };
7627 return DAG.getMergeValues(RVals, dl);
7630 /// Lowering for QPX v4i1 stores
7631 SDValue PPCTargetLowering::LowerVectorStore(SDValue Op,
7632 SelectionDAG &DAG) const {
7634 StoreSDNode *SN = cast<StoreSDNode>(Op.getNode());
7635 SDValue StoreChain = SN->getChain();
7636 SDValue BasePtr = SN->getBasePtr();
7637 SDValue Value = SN->getValue();
7639 if (Value.getValueType() == MVT::v4f64 ||
7640 Value.getValueType() == MVT::v4f32) {
7641 EVT MemVT = SN->getMemoryVT();
7642 unsigned Alignment = SN->getAlignment();
7644 // If this store is properly aligned, then it is legal.
7645 if (Alignment >= MemVT.getStoreSize())
7648 EVT ScalarVT = Value.getValueType().getScalarType(),
7649 ScalarMemVT = MemVT.getScalarType();
7650 unsigned Stride = ScalarMemVT.getStoreSize();
7652 SmallVector<SDValue, 8> Stores;
7653 for (unsigned Idx = 0; Idx < 4; ++Idx) {
7655 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, Value,
7656 DAG.getConstant(Idx, dl, getVectorIdxTy()));
7658 if (ScalarVT != ScalarMemVT)
7660 DAG.getTruncStore(StoreChain, dl, Ex, BasePtr,
7661 SN->getPointerInfo().getWithOffset(Idx*Stride),
7662 ScalarMemVT, SN->isVolatile(), SN->isNonTemporal(),
7663 MinAlign(Alignment, Idx*Stride), SN->getAAInfo());
7666 DAG.getStore(StoreChain, dl, Ex, BasePtr,
7667 SN->getPointerInfo().getWithOffset(Idx*Stride),
7668 SN->isVolatile(), SN->isNonTemporal(),
7669 MinAlign(Alignment, Idx*Stride), SN->getAAInfo());
7671 if (Idx == 0 && SN->isIndexed()) {
7672 assert(SN->getAddressingMode() == ISD::PRE_INC &&
7673 "Unknown addressing mode on vector store");
7674 Store = DAG.getIndexedStore(Store, dl, BasePtr, SN->getOffset(),
7675 SN->getAddressingMode());
7678 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
7679 DAG.getConstant(Stride, dl,
7680 BasePtr.getValueType()));
7681 Stores.push_back(Store);
7684 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
7686 if (SN->isIndexed()) {
7687 SDValue RetOps[] = { TF, Stores[0].getValue(1) };
7688 return DAG.getMergeValues(RetOps, dl);
7694 assert(SN->isUnindexed() && "Indexed v4i1 stores are not supported");
7695 assert(Value.getValueType() == MVT::v4i1 && "Unknown store to lower");
7697 // The values are now known to be -1 (false) or 1 (true). To convert this
7698 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
7699 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
7700 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
7702 // FIXME: We can make this an f32 vector, but the BUILD_VECTOR code needs to
7703 // understand how to form the extending load.
7704 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::f64);
7705 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
7706 FPHalfs, FPHalfs, FPHalfs, FPHalfs);
7708 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
7710 // Now convert to an integer and store.
7711 Value = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
7712 DAG.getConstant(Intrinsic::ppc_qpx_qvfctiwu, dl, MVT::i32),
7715 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
7716 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
7717 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FrameIdx);
7718 EVT PtrVT = getPointerTy();
7719 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
7721 SmallVector<SDValue, 2> Ops;
7722 Ops.push_back(StoreChain);
7723 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvstfiw, dl, MVT::i32));
7724 Ops.push_back(Value);
7725 Ops.push_back(FIdx);
7727 SmallVector<EVT, 2> ValueVTs;
7728 ValueVTs.push_back(MVT::Other); // chain
7729 SDVTList VTs = DAG.getVTList(ValueVTs);
7731 StoreChain = DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID,
7732 dl, VTs, Ops, MVT::v4i32, PtrInfo);
7734 // Move data into the byte array.
7735 SmallVector<SDValue, 4> Loads, LoadChains;
7736 for (unsigned i = 0; i < 4; ++i) {
7737 unsigned Offset = 4*i;
7738 SDValue Idx = DAG.getConstant(Offset, dl, FIdx.getValueType());
7739 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
7741 Loads.push_back(DAG.getLoad(MVT::i32, dl, StoreChain, Idx,
7742 PtrInfo.getWithOffset(Offset),
7743 false, false, false, 0));
7744 LoadChains.push_back(Loads[i].getValue(1));
7747 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
7749 SmallVector<SDValue, 4> Stores;
7750 for (unsigned i = 0; i < 4; ++i) {
7751 SDValue Idx = DAG.getConstant(i, dl, BasePtr.getValueType());
7752 Idx = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, Idx);
7754 Stores.push_back(DAG.getTruncStore(StoreChain, dl, Loads[i], Idx,
7755 SN->getPointerInfo().getWithOffset(i),
7756 MVT::i8 /* memory type */,
7757 SN->isNonTemporal(), SN->isVolatile(),
7758 1 /* alignment */, SN->getAAInfo()));
7761 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
7766 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
7768 if (Op.getValueType() == MVT::v4i32) {
7769 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
7771 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
7772 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
7774 SDValue RHSSwap = // = vrlw RHS, 16
7775 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
7777 // Shrinkify inputs to v8i16.
7778 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
7779 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
7780 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
7782 // Low parts multiplied together, generating 32-bit results (we ignore the
7784 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
7785 LHS, RHS, DAG, dl, MVT::v4i32);
7787 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
7788 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
7789 // Shift the high parts up 16 bits.
7790 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
7792 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
7793 } else if (Op.getValueType() == MVT::v8i16) {
7794 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
7796 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
7798 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
7799 LHS, RHS, Zero, DAG, dl);
7800 } else if (Op.getValueType() == MVT::v16i8) {
7801 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
7802 bool isLittleEndian = Subtarget.isLittleEndian();
7804 // Multiply the even 8-bit parts, producing 16-bit sums.
7805 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
7806 LHS, RHS, DAG, dl, MVT::v8i16);
7807 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
7809 // Multiply the odd 8-bit parts, producing 16-bit sums.
7810 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
7811 LHS, RHS, DAG, dl, MVT::v8i16);
7812 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
7814 // Merge the results together. Because vmuleub and vmuloub are
7815 // instructions with a big-endian bias, we must reverse the
7816 // element numbering and reverse the meaning of "odd" and "even"
7817 // when generating little endian code.
7819 for (unsigned i = 0; i != 8; ++i) {
7820 if (isLittleEndian) {
7822 Ops[i*2+1] = 2*i+16;
7825 Ops[i*2+1] = 2*i+1+16;
7829 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
7831 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
7833 llvm_unreachable("Unknown mul to lower!");
7837 /// LowerOperation - Provide custom lowering hooks for some operations.
7839 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7840 switch (Op.getOpcode()) {
7841 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
7842 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
7843 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
7844 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
7845 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
7846 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
7847 case ISD::SETCC: return LowerSETCC(Op, DAG);
7848 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
7849 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
7851 return LowerVASTART(Op, DAG, Subtarget);
7854 return LowerVAARG(Op, DAG, Subtarget);
7857 return LowerVACOPY(Op, DAG, Subtarget);
7859 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget);
7860 case ISD::DYNAMIC_STACKALLOC:
7861 return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget);
7863 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
7864 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
7866 case ISD::LOAD: return LowerLOAD(Op, DAG);
7867 case ISD::STORE: return LowerSTORE(Op, DAG);
7868 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
7869 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
7870 case ISD::FP_TO_UINT:
7871 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
7873 case ISD::UINT_TO_FP:
7874 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
7875 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
7877 // Lower 64-bit shifts.
7878 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
7879 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
7880 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
7882 // Vector-related lowering.
7883 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
7884 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
7885 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
7886 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
7887 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
7888 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
7889 case ISD::MUL: return LowerMUL(Op, DAG);
7891 // For counter-based loop handling.
7892 case ISD::INTRINSIC_W_CHAIN: return SDValue();
7894 // Frame & Return address.
7895 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
7896 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
7900 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
7901 SmallVectorImpl<SDValue>&Results,
7902 SelectionDAG &DAG) const {
7904 switch (N->getOpcode()) {
7906 llvm_unreachable("Do not know how to custom type legalize this operation!");
7907 case ISD::READCYCLECOUNTER: {
7908 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
7909 SDValue RTB = DAG.getNode(PPCISD::READ_TIME_BASE, dl, VTs, N->getOperand(0));
7911 Results.push_back(RTB);
7912 Results.push_back(RTB.getValue(1));
7913 Results.push_back(RTB.getValue(2));
7916 case ISD::INTRINSIC_W_CHAIN: {
7917 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
7918 Intrinsic::ppc_is_decremented_ctr_nonzero)
7921 assert(N->getValueType(0) == MVT::i1 &&
7922 "Unexpected result type for CTR decrement intrinsic");
7923 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
7924 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
7925 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
7928 Results.push_back(NewInt);
7929 Results.push_back(NewInt.getValue(1));
7933 if (!Subtarget.isSVR4ABI() || Subtarget.isPPC64())
7936 EVT VT = N->getValueType(0);
7938 if (VT == MVT::i64) {
7939 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget);
7941 Results.push_back(NewNode);
7942 Results.push_back(NewNode.getValue(1));
7946 case ISD::FP_ROUND_INREG: {
7947 assert(N->getValueType(0) == MVT::ppcf128);
7948 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
7949 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
7950 MVT::f64, N->getOperand(0),
7951 DAG.getIntPtrConstant(0, dl));
7952 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
7953 MVT::f64, N->getOperand(0),
7954 DAG.getIntPtrConstant(1, dl));
7956 // Add the two halves of the long double in round-to-zero mode.
7957 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
7959 // We know the low half is about to be thrown away, so just use something
7961 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
7965 case ISD::FP_TO_SINT:
7966 case ISD::FP_TO_UINT:
7967 // LowerFP_TO_INT() can only handle f32 and f64.
7968 if (N->getOperand(0).getValueType() == MVT::ppcf128)
7970 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
7976 //===----------------------------------------------------------------------===//
7977 // Other Lowering Code
7978 //===----------------------------------------------------------------------===//
7980 static Instruction* callIntrinsic(IRBuilder<> &Builder, Intrinsic::ID Id) {
7981 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
7982 Function *Func = Intrinsic::getDeclaration(M, Id);
7983 return Builder.CreateCall(Func, {});
7986 // The mappings for emitLeading/TrailingFence is taken from
7987 // http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
7988 Instruction* PPCTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
7989 AtomicOrdering Ord, bool IsStore,
7990 bool IsLoad) const {
7991 if (Ord == SequentiallyConsistent)
7992 return callIntrinsic(Builder, Intrinsic::ppc_sync);
7993 if (isAtLeastRelease(Ord))
7994 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
7998 Instruction* PPCTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
7999 AtomicOrdering Ord, bool IsStore,
8000 bool IsLoad) const {
8001 if (IsLoad && isAtLeastAcquire(Ord))
8002 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
8003 // FIXME: this is too conservative, a dependent branch + isync is enough.
8004 // See http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html and
8005 // http://www.rdrop.com/users/paulmck/scalability/paper/N2745r.2011.03.04a.html
8006 // and http://www.cl.cam.ac.uk/~pes20/cppppc/ for justification.
8011 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
8012 unsigned AtomicSize,
8013 unsigned BinOpcode) const {
8014 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
8015 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8017 auto LoadMnemonic = PPC::LDARX;
8018 auto StoreMnemonic = PPC::STDCX;
8019 switch (AtomicSize) {
8021 llvm_unreachable("Unexpected size of atomic entity");
8023 LoadMnemonic = PPC::LBARX;
8024 StoreMnemonic = PPC::STBCX;
8025 assert(Subtarget.hasPartwordAtomics() && "Call this only with size >=4");
8028 LoadMnemonic = PPC::LHARX;
8029 StoreMnemonic = PPC::STHCX;
8030 assert(Subtarget.hasPartwordAtomics() && "Call this only with size >=4");
8033 LoadMnemonic = PPC::LWARX;
8034 StoreMnemonic = PPC::STWCX;
8037 LoadMnemonic = PPC::LDARX;
8038 StoreMnemonic = PPC::STDCX;
8042 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8043 MachineFunction *F = BB->getParent();
8044 MachineFunction::iterator It = BB;
8047 unsigned dest = MI->getOperand(0).getReg();
8048 unsigned ptrA = MI->getOperand(1).getReg();
8049 unsigned ptrB = MI->getOperand(2).getReg();
8050 unsigned incr = MI->getOperand(3).getReg();
8051 DebugLoc dl = MI->getDebugLoc();
8053 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
8054 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8055 F->insert(It, loopMBB);
8056 F->insert(It, exitMBB);
8057 exitMBB->splice(exitMBB->begin(), BB,
8058 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8059 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8061 MachineRegisterInfo &RegInfo = F->getRegInfo();
8062 unsigned TmpReg = (!BinOpcode) ? incr :
8063 RegInfo.createVirtualRegister( AtomicSize == 8 ? &PPC::G8RCRegClass
8064 : &PPC::GPRCRegClass);
8068 // fallthrough --> loopMBB
8069 BB->addSuccessor(loopMBB);
8072 // l[wd]arx dest, ptr
8073 // add r0, dest, incr
8074 // st[wd]cx. r0, ptr
8076 // fallthrough --> exitMBB
8078 BuildMI(BB, dl, TII->get(LoadMnemonic), dest)
8079 .addReg(ptrA).addReg(ptrB);
8081 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
8082 BuildMI(BB, dl, TII->get(StoreMnemonic))
8083 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
8084 BuildMI(BB, dl, TII->get(PPC::BCC))
8085 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
8086 BB->addSuccessor(loopMBB);
8087 BB->addSuccessor(exitMBB);
8096 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
8097 MachineBasicBlock *BB,
8098 bool is8bit, // operation
8099 unsigned BinOpcode) const {
8100 // If we support part-word atomic mnemonics, just use them
8101 if (Subtarget.hasPartwordAtomics())
8102 return EmitAtomicBinary(MI, BB, is8bit ? 1 : 2, BinOpcode);
8104 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
8105 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8106 // In 64 bit mode we have to use 64 bits for addresses, even though the
8107 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
8108 // registers without caring whether they're 32 or 64, but here we're
8109 // doing actual arithmetic on the addresses.
8110 bool is64bit = Subtarget.isPPC64();
8111 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
8113 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8114 MachineFunction *F = BB->getParent();
8115 MachineFunction::iterator It = BB;
8118 unsigned dest = MI->getOperand(0).getReg();
8119 unsigned ptrA = MI->getOperand(1).getReg();
8120 unsigned ptrB = MI->getOperand(2).getReg();
8121 unsigned incr = MI->getOperand(3).getReg();
8122 DebugLoc dl = MI->getDebugLoc();
8124 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
8125 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8126 F->insert(It, loopMBB);
8127 F->insert(It, exitMBB);
8128 exitMBB->splice(exitMBB->begin(), BB,
8129 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8130 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8132 MachineRegisterInfo &RegInfo = F->getRegInfo();
8133 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
8134 : &PPC::GPRCRegClass;
8135 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
8136 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
8137 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
8138 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
8139 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
8140 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
8141 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
8142 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
8143 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
8144 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
8145 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
8147 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
8151 // fallthrough --> loopMBB
8152 BB->addSuccessor(loopMBB);
8154 // The 4-byte load must be aligned, while a char or short may be
8155 // anywhere in the word. Hence all this nasty bookkeeping code.
8156 // add ptr1, ptrA, ptrB [copy if ptrA==0]
8157 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
8158 // xori shift, shift1, 24 [16]
8159 // rlwinm ptr, ptr1, 0, 0, 29
8160 // slw incr2, incr, shift
8161 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
8162 // slw mask, mask2, shift
8164 // lwarx tmpDest, ptr
8165 // add tmp, tmpDest, incr2
8166 // andc tmp2, tmpDest, mask
8167 // and tmp3, tmp, mask
8168 // or tmp4, tmp3, tmp2
8171 // fallthrough --> exitMBB
8172 // srw dest, tmpDest, shift
8173 if (ptrA != ZeroReg) {
8174 Ptr1Reg = RegInfo.createVirtualRegister(RC);
8175 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
8176 .addReg(ptrA).addReg(ptrB);
8180 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
8181 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
8182 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
8183 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
8185 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
8186 .addReg(Ptr1Reg).addImm(0).addImm(61);
8188 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
8189 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
8190 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
8191 .addReg(incr).addReg(ShiftReg);
8193 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
8195 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
8196 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
8198 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
8199 .addReg(Mask2Reg).addReg(ShiftReg);
8202 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
8203 .addReg(ZeroReg).addReg(PtrReg);
8205 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
8206 .addReg(Incr2Reg).addReg(TmpDestReg);
8207 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
8208 .addReg(TmpDestReg).addReg(MaskReg);
8209 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
8210 .addReg(TmpReg).addReg(MaskReg);
8211 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
8212 .addReg(Tmp3Reg).addReg(Tmp2Reg);
8213 BuildMI(BB, dl, TII->get(PPC::STWCX))
8214 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
8215 BuildMI(BB, dl, TII->get(PPC::BCC))
8216 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
8217 BB->addSuccessor(loopMBB);
8218 BB->addSuccessor(exitMBB);
8223 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
8228 llvm::MachineBasicBlock*
8229 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
8230 MachineBasicBlock *MBB) const {
8231 DebugLoc DL = MI->getDebugLoc();
8232 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8234 MachineFunction *MF = MBB->getParent();
8235 MachineRegisterInfo &MRI = MF->getRegInfo();
8237 const BasicBlock *BB = MBB->getBasicBlock();
8238 MachineFunction::iterator I = MBB;
8242 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
8243 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
8245 unsigned DstReg = MI->getOperand(0).getReg();
8246 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
8247 assert(RC->hasType(MVT::i32) && "Invalid destination!");
8248 unsigned mainDstReg = MRI.createVirtualRegister(RC);
8249 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
8251 MVT PVT = getPointerTy();
8252 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
8253 "Invalid Pointer Size!");
8254 // For v = setjmp(buf), we generate
8257 // SjLjSetup mainMBB
8263 // buf[LabelOffset] = LR
8267 // v = phi(main, restore)
8270 MachineBasicBlock *thisMBB = MBB;
8271 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
8272 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
8273 MF->insert(I, mainMBB);
8274 MF->insert(I, sinkMBB);
8276 MachineInstrBuilder MIB;
8278 // Transfer the remainder of BB and its successor edges to sinkMBB.
8279 sinkMBB->splice(sinkMBB->begin(), MBB,
8280 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
8281 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
8283 // Note that the structure of the jmp_buf used here is not compatible
8284 // with that used by libc, and is not designed to be. Specifically, it
8285 // stores only those 'reserved' registers that LLVM does not otherwise
8286 // understand how to spill. Also, by convention, by the time this
8287 // intrinsic is called, Clang has already stored the frame address in the
8288 // first slot of the buffer and stack address in the third. Following the
8289 // X86 target code, we'll store the jump address in the second slot. We also
8290 // need to save the TOC pointer (R2) to handle jumps between shared
8291 // libraries, and that will be stored in the fourth slot. The thread
8292 // identifier (R13) is not affected.
8295 const int64_t LabelOffset = 1 * PVT.getStoreSize();
8296 const int64_t TOCOffset = 3 * PVT.getStoreSize();
8297 const int64_t BPOffset = 4 * PVT.getStoreSize();
8299 // Prepare IP either in reg.
8300 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
8301 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
8302 unsigned BufReg = MI->getOperand(1).getReg();
8304 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
8305 setUsesTOCBasePtr(*MBB->getParent());
8306 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
8310 MIB.setMemRefs(MMOBegin, MMOEnd);
8313 // Naked functions never have a base pointer, and so we use r1. For all
8314 // other functions, this decision must be delayed until during PEI.
8316 if (MF->getFunction()->hasFnAttribute(Attribute::Naked))
8317 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
8319 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
8321 MIB = BuildMI(*thisMBB, MI, DL,
8322 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
8326 MIB.setMemRefs(MMOBegin, MMOEnd);
8329 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
8330 const PPCRegisterInfo *TRI = Subtarget.getRegisterInfo();
8331 MIB.addRegMask(TRI->getNoPreservedMask());
8333 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
8335 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
8337 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
8339 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
8340 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
8345 BuildMI(mainMBB, DL,
8346 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
8349 if (Subtarget.isPPC64()) {
8350 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
8352 .addImm(LabelOffset)
8355 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
8357 .addImm(LabelOffset)
8361 MIB.setMemRefs(MMOBegin, MMOEnd);
8363 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
8364 mainMBB->addSuccessor(sinkMBB);
8367 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
8368 TII->get(PPC::PHI), DstReg)
8369 .addReg(mainDstReg).addMBB(mainMBB)
8370 .addReg(restoreDstReg).addMBB(thisMBB);
8372 MI->eraseFromParent();
8377 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
8378 MachineBasicBlock *MBB) const {
8379 DebugLoc DL = MI->getDebugLoc();
8380 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8382 MachineFunction *MF = MBB->getParent();
8383 MachineRegisterInfo &MRI = MF->getRegInfo();
8386 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
8387 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
8389 MVT PVT = getPointerTy();
8390 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
8391 "Invalid Pointer Size!");
8393 const TargetRegisterClass *RC =
8394 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
8395 unsigned Tmp = MRI.createVirtualRegister(RC);
8396 // Since FP is only updated here but NOT referenced, it's treated as GPR.
8397 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
8398 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
8402 : (Subtarget.isSVR4ABI() &&
8403 MF->getTarget().getRelocationModel() == Reloc::PIC_
8407 MachineInstrBuilder MIB;
8409 const int64_t LabelOffset = 1 * PVT.getStoreSize();
8410 const int64_t SPOffset = 2 * PVT.getStoreSize();
8411 const int64_t TOCOffset = 3 * PVT.getStoreSize();
8412 const int64_t BPOffset = 4 * PVT.getStoreSize();
8414 unsigned BufReg = MI->getOperand(0).getReg();
8416 // Reload FP (the jumped-to function may not have had a
8417 // frame pointer, and if so, then its r31 will be restored
8419 if (PVT == MVT::i64) {
8420 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
8424 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
8428 MIB.setMemRefs(MMOBegin, MMOEnd);
8431 if (PVT == MVT::i64) {
8432 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
8433 .addImm(LabelOffset)
8436 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
8437 .addImm(LabelOffset)
8440 MIB.setMemRefs(MMOBegin, MMOEnd);
8443 if (PVT == MVT::i64) {
8444 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
8448 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
8452 MIB.setMemRefs(MMOBegin, MMOEnd);
8455 if (PVT == MVT::i64) {
8456 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
8460 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
8464 MIB.setMemRefs(MMOBegin, MMOEnd);
8467 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
8468 setUsesTOCBasePtr(*MBB->getParent());
8469 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
8473 MIB.setMemRefs(MMOBegin, MMOEnd);
8477 BuildMI(*MBB, MI, DL,
8478 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
8479 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
8481 MI->eraseFromParent();
8486 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
8487 MachineBasicBlock *BB) const {
8488 if (MI->getOpcode() == TargetOpcode::STACKMAP ||
8489 MI->getOpcode() == TargetOpcode::PATCHPOINT) {
8490 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI() &&
8491 MI->getOpcode() == TargetOpcode::PATCHPOINT) {
8492 // Call lowering should have added an r2 operand to indicate a dependence
8493 // on the TOC base pointer value. It can't however, because there is no
8494 // way to mark the dependence as implicit there, and so the stackmap code
8495 // will confuse it with a regular operand. Instead, add the dependence
8497 setUsesTOCBasePtr(*BB->getParent());
8498 MI->addOperand(MachineOperand::CreateReg(PPC::X2, false, true));
8501 return emitPatchPoint(MI, BB);
8504 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
8505 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
8506 return emitEHSjLjSetJmp(MI, BB);
8507 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
8508 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
8509 return emitEHSjLjLongJmp(MI, BB);
8512 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8514 // To "insert" these instructions we actually have to insert their
8515 // control-flow patterns.
8516 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8517 MachineFunction::iterator It = BB;
8520 MachineFunction *F = BB->getParent();
8522 if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
8523 MI->getOpcode() == PPC::SELECT_CC_I8 ||
8524 MI->getOpcode() == PPC::SELECT_I4 ||
8525 MI->getOpcode() == PPC::SELECT_I8)) {
8526 SmallVector<MachineOperand, 2> Cond;
8527 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
8528 MI->getOpcode() == PPC::SELECT_CC_I8)
8529 Cond.push_back(MI->getOperand(4));
8531 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
8532 Cond.push_back(MI->getOperand(1));
8534 DebugLoc dl = MI->getDebugLoc();
8535 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
8536 Cond, MI->getOperand(2).getReg(),
8537 MI->getOperand(3).getReg());
8538 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
8539 MI->getOpcode() == PPC::SELECT_CC_I8 ||
8540 MI->getOpcode() == PPC::SELECT_CC_F4 ||
8541 MI->getOpcode() == PPC::SELECT_CC_F8 ||
8542 MI->getOpcode() == PPC::SELECT_CC_QFRC ||
8543 MI->getOpcode() == PPC::SELECT_CC_QSRC ||
8544 MI->getOpcode() == PPC::SELECT_CC_QBRC ||
8545 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
8546 MI->getOpcode() == PPC::SELECT_CC_VSFRC ||
8547 MI->getOpcode() == PPC::SELECT_CC_VSSRC ||
8548 MI->getOpcode() == PPC::SELECT_CC_VSRC ||
8549 MI->getOpcode() == PPC::SELECT_I4 ||
8550 MI->getOpcode() == PPC::SELECT_I8 ||
8551 MI->getOpcode() == PPC::SELECT_F4 ||
8552 MI->getOpcode() == PPC::SELECT_F8 ||
8553 MI->getOpcode() == PPC::SELECT_QFRC ||
8554 MI->getOpcode() == PPC::SELECT_QSRC ||
8555 MI->getOpcode() == PPC::SELECT_QBRC ||
8556 MI->getOpcode() == PPC::SELECT_VRRC ||
8557 MI->getOpcode() == PPC::SELECT_VSFRC ||
8558 MI->getOpcode() == PPC::SELECT_VSSRC ||
8559 MI->getOpcode() == PPC::SELECT_VSRC) {
8560 // The incoming instruction knows the destination vreg to set, the
8561 // condition code register to branch on, the true/false values to
8562 // select between, and a branch opcode to use.
8567 // cmpTY ccX, r1, r2
8569 // fallthrough --> copy0MBB
8570 MachineBasicBlock *thisMBB = BB;
8571 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
8572 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8573 DebugLoc dl = MI->getDebugLoc();
8574 F->insert(It, copy0MBB);
8575 F->insert(It, sinkMBB);
8577 // Transfer the remainder of BB and its successor edges to sinkMBB.
8578 sinkMBB->splice(sinkMBB->begin(), BB,
8579 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8580 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
8582 // Next, add the true and fallthrough blocks as its successors.
8583 BB->addSuccessor(copy0MBB);
8584 BB->addSuccessor(sinkMBB);
8586 if (MI->getOpcode() == PPC::SELECT_I4 ||
8587 MI->getOpcode() == PPC::SELECT_I8 ||
8588 MI->getOpcode() == PPC::SELECT_F4 ||
8589 MI->getOpcode() == PPC::SELECT_F8 ||
8590 MI->getOpcode() == PPC::SELECT_QFRC ||
8591 MI->getOpcode() == PPC::SELECT_QSRC ||
8592 MI->getOpcode() == PPC::SELECT_QBRC ||
8593 MI->getOpcode() == PPC::SELECT_VRRC ||
8594 MI->getOpcode() == PPC::SELECT_VSFRC ||
8595 MI->getOpcode() == PPC::SELECT_VSSRC ||
8596 MI->getOpcode() == PPC::SELECT_VSRC) {
8597 BuildMI(BB, dl, TII->get(PPC::BC))
8598 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
8600 unsigned SelectPred = MI->getOperand(4).getImm();
8601 BuildMI(BB, dl, TII->get(PPC::BCC))
8602 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
8606 // %FalseValue = ...
8607 // # fallthrough to sinkMBB
8610 // Update machine-CFG edges
8611 BB->addSuccessor(sinkMBB);
8614 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
8617 BuildMI(*BB, BB->begin(), dl,
8618 TII->get(PPC::PHI), MI->getOperand(0).getReg())
8619 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
8620 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
8621 } else if (MI->getOpcode() == PPC::ReadTB) {
8622 // To read the 64-bit time-base register on a 32-bit target, we read the
8623 // two halves. Should the counter have wrapped while it was being read, we
8624 // need to try again.
8627 // mfspr Rx,TBU # load from TBU
8628 // mfspr Ry,TB # load from TB
8629 // mfspr Rz,TBU # load from TBU
8630 // cmpw crX,Rx,Rz # check if ‘old’=’new’
8631 // bne readLoop # branch if they're not equal
8634 MachineBasicBlock *readMBB = F->CreateMachineBasicBlock(LLVM_BB);
8635 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8636 DebugLoc dl = MI->getDebugLoc();
8637 F->insert(It, readMBB);
8638 F->insert(It, sinkMBB);
8640 // Transfer the remainder of BB and its successor edges to sinkMBB.
8641 sinkMBB->splice(sinkMBB->begin(), BB,
8642 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8643 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
8645 BB->addSuccessor(readMBB);
8648 MachineRegisterInfo &RegInfo = F->getRegInfo();
8649 unsigned ReadAgainReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
8650 unsigned LoReg = MI->getOperand(0).getReg();
8651 unsigned HiReg = MI->getOperand(1).getReg();
8653 BuildMI(BB, dl, TII->get(PPC::MFSPR), HiReg).addImm(269);
8654 BuildMI(BB, dl, TII->get(PPC::MFSPR), LoReg).addImm(268);
8655 BuildMI(BB, dl, TII->get(PPC::MFSPR), ReadAgainReg).addImm(269);
8657 unsigned CmpReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
8659 BuildMI(BB, dl, TII->get(PPC::CMPW), CmpReg)
8660 .addReg(HiReg).addReg(ReadAgainReg);
8661 BuildMI(BB, dl, TII->get(PPC::BCC))
8662 .addImm(PPC::PRED_NE).addReg(CmpReg).addMBB(readMBB);
8664 BB->addSuccessor(readMBB);
8665 BB->addSuccessor(sinkMBB);
8667 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
8668 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
8669 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
8670 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
8671 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
8672 BB = EmitAtomicBinary(MI, BB, 4, PPC::ADD4);
8673 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
8674 BB = EmitAtomicBinary(MI, BB, 8, PPC::ADD8);
8676 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
8677 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
8678 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
8679 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
8680 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
8681 BB = EmitAtomicBinary(MI, BB, 4, PPC::AND);
8682 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
8683 BB = EmitAtomicBinary(MI, BB, 8, PPC::AND8);
8685 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
8686 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
8687 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
8688 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
8689 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
8690 BB = EmitAtomicBinary(MI, BB, 4, PPC::OR);
8691 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
8692 BB = EmitAtomicBinary(MI, BB, 8, PPC::OR8);
8694 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
8695 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
8696 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
8697 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
8698 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
8699 BB = EmitAtomicBinary(MI, BB, 4, PPC::XOR);
8700 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
8701 BB = EmitAtomicBinary(MI, BB, 8, PPC::XOR8);
8703 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
8704 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND);
8705 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
8706 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND);
8707 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
8708 BB = EmitAtomicBinary(MI, BB, 4, PPC::NAND);
8709 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
8710 BB = EmitAtomicBinary(MI, BB, 8, PPC::NAND8);
8712 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
8713 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
8714 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
8715 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
8716 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
8717 BB = EmitAtomicBinary(MI, BB, 4, PPC::SUBF);
8718 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
8719 BB = EmitAtomicBinary(MI, BB, 8, PPC::SUBF8);
8721 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
8722 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
8723 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
8724 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
8725 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
8726 BB = EmitAtomicBinary(MI, BB, 4, 0);
8727 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
8728 BB = EmitAtomicBinary(MI, BB, 8, 0);
8730 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
8731 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64 ||
8732 (Subtarget.hasPartwordAtomics() &&
8733 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8) ||
8734 (Subtarget.hasPartwordAtomics() &&
8735 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16)) {
8736 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
8738 auto LoadMnemonic = PPC::LDARX;
8739 auto StoreMnemonic = PPC::STDCX;
8740 switch(MI->getOpcode()) {
8742 llvm_unreachable("Compare and swap of unknown size");
8743 case PPC::ATOMIC_CMP_SWAP_I8:
8744 LoadMnemonic = PPC::LBARX;
8745 StoreMnemonic = PPC::STBCX;
8746 assert(Subtarget.hasPartwordAtomics() && "No support partword atomics.");
8748 case PPC::ATOMIC_CMP_SWAP_I16:
8749 LoadMnemonic = PPC::LHARX;
8750 StoreMnemonic = PPC::STHCX;
8751 assert(Subtarget.hasPartwordAtomics() && "No support partword atomics.");
8753 case PPC::ATOMIC_CMP_SWAP_I32:
8754 LoadMnemonic = PPC::LWARX;
8755 StoreMnemonic = PPC::STWCX;
8757 case PPC::ATOMIC_CMP_SWAP_I64:
8758 LoadMnemonic = PPC::LDARX;
8759 StoreMnemonic = PPC::STDCX;
8762 unsigned dest = MI->getOperand(0).getReg();
8763 unsigned ptrA = MI->getOperand(1).getReg();
8764 unsigned ptrB = MI->getOperand(2).getReg();
8765 unsigned oldval = MI->getOperand(3).getReg();
8766 unsigned newval = MI->getOperand(4).getReg();
8767 DebugLoc dl = MI->getDebugLoc();
8769 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
8770 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
8771 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
8772 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8773 F->insert(It, loop1MBB);
8774 F->insert(It, loop2MBB);
8775 F->insert(It, midMBB);
8776 F->insert(It, exitMBB);
8777 exitMBB->splice(exitMBB->begin(), BB,
8778 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8779 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8783 // fallthrough --> loopMBB
8784 BB->addSuccessor(loop1MBB);
8787 // l[bhwd]arx dest, ptr
8788 // cmp[wd] dest, oldval
8791 // st[bhwd]cx. newval, ptr
8795 // st[bhwd]cx. dest, ptr
8798 BuildMI(BB, dl, TII->get(LoadMnemonic), dest)
8799 .addReg(ptrA).addReg(ptrB);
8800 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
8801 .addReg(oldval).addReg(dest);
8802 BuildMI(BB, dl, TII->get(PPC::BCC))
8803 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
8804 BB->addSuccessor(loop2MBB);
8805 BB->addSuccessor(midMBB);
8808 BuildMI(BB, dl, TII->get(StoreMnemonic))
8809 .addReg(newval).addReg(ptrA).addReg(ptrB);
8810 BuildMI(BB, dl, TII->get(PPC::BCC))
8811 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
8812 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
8813 BB->addSuccessor(loop1MBB);
8814 BB->addSuccessor(exitMBB);
8817 BuildMI(BB, dl, TII->get(StoreMnemonic))
8818 .addReg(dest).addReg(ptrA).addReg(ptrB);
8819 BB->addSuccessor(exitMBB);
8824 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
8825 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
8826 // We must use 64-bit registers for addresses when targeting 64-bit,
8827 // since we're actually doing arithmetic on them. Other registers
8829 bool is64bit = Subtarget.isPPC64();
8830 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
8832 unsigned dest = MI->getOperand(0).getReg();
8833 unsigned ptrA = MI->getOperand(1).getReg();
8834 unsigned ptrB = MI->getOperand(2).getReg();
8835 unsigned oldval = MI->getOperand(3).getReg();
8836 unsigned newval = MI->getOperand(4).getReg();
8837 DebugLoc dl = MI->getDebugLoc();
8839 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
8840 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
8841 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
8842 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8843 F->insert(It, loop1MBB);
8844 F->insert(It, loop2MBB);
8845 F->insert(It, midMBB);
8846 F->insert(It, exitMBB);
8847 exitMBB->splice(exitMBB->begin(), BB,
8848 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8849 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8851 MachineRegisterInfo &RegInfo = F->getRegInfo();
8852 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
8853 : &PPC::GPRCRegClass;
8854 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
8855 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
8856 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
8857 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
8858 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
8859 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
8860 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
8861 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
8862 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
8863 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
8864 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
8865 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
8866 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
8868 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
8869 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
8872 // fallthrough --> loopMBB
8873 BB->addSuccessor(loop1MBB);
8875 // The 4-byte load must be aligned, while a char or short may be
8876 // anywhere in the word. Hence all this nasty bookkeeping code.
8877 // add ptr1, ptrA, ptrB [copy if ptrA==0]
8878 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
8879 // xori shift, shift1, 24 [16]
8880 // rlwinm ptr, ptr1, 0, 0, 29
8881 // slw newval2, newval, shift
8882 // slw oldval2, oldval,shift
8883 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
8884 // slw mask, mask2, shift
8885 // and newval3, newval2, mask
8886 // and oldval3, oldval2, mask
8888 // lwarx tmpDest, ptr
8889 // and tmp, tmpDest, mask
8890 // cmpw tmp, oldval3
8893 // andc tmp2, tmpDest, mask
8894 // or tmp4, tmp2, newval3
8899 // stwcx. tmpDest, ptr
8901 // srw dest, tmpDest, shift
8902 if (ptrA != ZeroReg) {
8903 Ptr1Reg = RegInfo.createVirtualRegister(RC);
8904 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
8905 .addReg(ptrA).addReg(ptrB);
8909 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
8910 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
8911 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
8912 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
8914 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
8915 .addReg(Ptr1Reg).addImm(0).addImm(61);
8917 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
8918 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
8919 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
8920 .addReg(newval).addReg(ShiftReg);
8921 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
8922 .addReg(oldval).addReg(ShiftReg);
8924 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
8926 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
8927 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
8928 .addReg(Mask3Reg).addImm(65535);
8930 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
8931 .addReg(Mask2Reg).addReg(ShiftReg);
8932 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
8933 .addReg(NewVal2Reg).addReg(MaskReg);
8934 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
8935 .addReg(OldVal2Reg).addReg(MaskReg);
8938 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
8939 .addReg(ZeroReg).addReg(PtrReg);
8940 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
8941 .addReg(TmpDestReg).addReg(MaskReg);
8942 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
8943 .addReg(TmpReg).addReg(OldVal3Reg);
8944 BuildMI(BB, dl, TII->get(PPC::BCC))
8945 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
8946 BB->addSuccessor(loop2MBB);
8947 BB->addSuccessor(midMBB);
8950 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
8951 .addReg(TmpDestReg).addReg(MaskReg);
8952 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
8953 .addReg(Tmp2Reg).addReg(NewVal3Reg);
8954 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
8955 .addReg(ZeroReg).addReg(PtrReg);
8956 BuildMI(BB, dl, TII->get(PPC::BCC))
8957 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
8958 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
8959 BB->addSuccessor(loop1MBB);
8960 BB->addSuccessor(exitMBB);
8963 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
8964 .addReg(ZeroReg).addReg(PtrReg);
8965 BB->addSuccessor(exitMBB);
8970 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
8972 } else if (MI->getOpcode() == PPC::FADDrtz) {
8973 // This pseudo performs an FADD with rounding mode temporarily forced
8974 // to round-to-zero. We emit this via custom inserter since the FPSCR
8975 // is not modeled at the SelectionDAG level.
8976 unsigned Dest = MI->getOperand(0).getReg();
8977 unsigned Src1 = MI->getOperand(1).getReg();
8978 unsigned Src2 = MI->getOperand(2).getReg();
8979 DebugLoc dl = MI->getDebugLoc();
8981 MachineRegisterInfo &RegInfo = F->getRegInfo();
8982 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
8984 // Save FPSCR value.
8985 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
8987 // Set rounding mode to round-to-zero.
8988 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
8989 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
8991 // Perform addition.
8992 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
8994 // Restore FPSCR value.
8995 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSFb)).addImm(1).addReg(MFFSReg);
8996 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
8997 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
8998 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
8999 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
9000 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
9001 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
9002 PPC::ANDIo8 : PPC::ANDIo;
9003 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
9004 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
9006 MachineRegisterInfo &RegInfo = F->getRegInfo();
9007 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
9008 &PPC::GPRCRegClass :
9009 &PPC::G8RCRegClass);
9011 DebugLoc dl = MI->getDebugLoc();
9012 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
9013 .addReg(MI->getOperand(1).getReg()).addImm(1);
9014 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
9015 MI->getOperand(0).getReg())
9016 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
9017 } else if (MI->getOpcode() == PPC::TCHECK_RET) {
9018 DebugLoc Dl = MI->getDebugLoc();
9019 MachineRegisterInfo &RegInfo = F->getRegInfo();
9020 unsigned CRReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
9021 BuildMI(*BB, MI, Dl, TII->get(PPC::TCHECK), CRReg);
9024 llvm_unreachable("Unexpected instr type to insert");
9027 MI->eraseFromParent(); // The pseudo instruction is gone now.
9031 //===----------------------------------------------------------------------===//
9032 // Target Optimization Hooks
9033 //===----------------------------------------------------------------------===//
9035 SDValue PPCTargetLowering::getRsqrtEstimate(SDValue Operand,
9036 DAGCombinerInfo &DCI,
9037 unsigned &RefinementSteps,
9038 bool &UseOneConstNR) const {
9039 EVT VT = Operand.getValueType();
9040 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
9041 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
9042 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
9043 (VT == MVT::v2f64 && Subtarget.hasVSX()) ||
9044 (VT == MVT::v4f32 && Subtarget.hasQPX()) ||
9045 (VT == MVT::v4f64 && Subtarget.hasQPX())) {
9046 // Convergence is quadratic, so we essentially double the number of digits
9047 // correct after every iteration. For both FRE and FRSQRTE, the minimum
9048 // architected relative accuracy is 2^-5. When hasRecipPrec(), this is
9049 // 2^-14. IEEE float has 23 digits and double has 52 digits.
9050 RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3;
9051 if (VT.getScalarType() == MVT::f64)
9053 UseOneConstNR = true;
9054 return DCI.DAG.getNode(PPCISD::FRSQRTE, SDLoc(Operand), VT, Operand);
9059 SDValue PPCTargetLowering::getRecipEstimate(SDValue Operand,
9060 DAGCombinerInfo &DCI,
9061 unsigned &RefinementSteps) const {
9062 EVT VT = Operand.getValueType();
9063 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
9064 (VT == MVT::f64 && Subtarget.hasFRE()) ||
9065 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
9066 (VT == MVT::v2f64 && Subtarget.hasVSX()) ||
9067 (VT == MVT::v4f32 && Subtarget.hasQPX()) ||
9068 (VT == MVT::v4f64 && Subtarget.hasQPX())) {
9069 // Convergence is quadratic, so we essentially double the number of digits
9070 // correct after every iteration. For both FRE and FRSQRTE, the minimum
9071 // architected relative accuracy is 2^-5. When hasRecipPrec(), this is
9072 // 2^-14. IEEE float has 23 digits and double has 52 digits.
9073 RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3;
9074 if (VT.getScalarType() == MVT::f64)
9076 return DCI.DAG.getNode(PPCISD::FRE, SDLoc(Operand), VT, Operand);
9081 bool PPCTargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
9082 // Note: This functionality is used only when unsafe-fp-math is enabled, and
9083 // on cores with reciprocal estimates (which are used when unsafe-fp-math is
9084 // enabled for division), this functionality is redundant with the default
9085 // combiner logic (once the division -> reciprocal/multiply transformation
9086 // has taken place). As a result, this matters more for older cores than for
9089 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
9090 // reciprocal if there are two or more FDIVs (for embedded cores with only
9091 // one FP pipeline) for three or more FDIVs (for generic OOO cores).
9092 switch (Subtarget.getDarwinDirective()) {
9094 return NumUsers > 2;
9097 case PPC::DIR_E500mc:
9098 case PPC::DIR_E5500:
9099 return NumUsers > 1;
9103 static bool isConsecutiveLSLoc(SDValue Loc, EVT VT, LSBaseSDNode *Base,
9104 unsigned Bytes, int Dist,
9105 SelectionDAG &DAG) {
9106 if (VT.getSizeInBits() / 8 != Bytes)
9109 SDValue BaseLoc = Base->getBasePtr();
9110 if (Loc.getOpcode() == ISD::FrameIndex) {
9111 if (BaseLoc.getOpcode() != ISD::FrameIndex)
9113 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9114 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
9115 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
9116 int FS = MFI->getObjectSize(FI);
9117 int BFS = MFI->getObjectSize(BFI);
9118 if (FS != BFS || FS != (int)Bytes) return false;
9119 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
9123 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
9124 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
9127 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9128 const GlobalValue *GV1 = nullptr;
9129 const GlobalValue *GV2 = nullptr;
9130 int64_t Offset1 = 0;
9131 int64_t Offset2 = 0;
9132 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
9133 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
9134 if (isGA1 && isGA2 && GV1 == GV2)
9135 return Offset1 == (Offset2 + Dist*Bytes);
9139 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
9140 // not enforce equality of the chain operands.
9141 static bool isConsecutiveLS(SDNode *N, LSBaseSDNode *Base,
9142 unsigned Bytes, int Dist,
9143 SelectionDAG &DAG) {
9144 if (LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(N)) {
9145 EVT VT = LS->getMemoryVT();
9146 SDValue Loc = LS->getBasePtr();
9147 return isConsecutiveLSLoc(Loc, VT, Base, Bytes, Dist, DAG);
9150 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
9152 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9153 default: return false;
9154 case Intrinsic::ppc_qpx_qvlfd:
9155 case Intrinsic::ppc_qpx_qvlfda:
9158 case Intrinsic::ppc_qpx_qvlfs:
9159 case Intrinsic::ppc_qpx_qvlfsa:
9162 case Intrinsic::ppc_qpx_qvlfcd:
9163 case Intrinsic::ppc_qpx_qvlfcda:
9166 case Intrinsic::ppc_qpx_qvlfcs:
9167 case Intrinsic::ppc_qpx_qvlfcsa:
9170 case Intrinsic::ppc_qpx_qvlfiwa:
9171 case Intrinsic::ppc_qpx_qvlfiwz:
9172 case Intrinsic::ppc_altivec_lvx:
9173 case Intrinsic::ppc_altivec_lvxl:
9174 case Intrinsic::ppc_vsx_lxvw4x:
9177 case Intrinsic::ppc_vsx_lxvd2x:
9180 case Intrinsic::ppc_altivec_lvebx:
9183 case Intrinsic::ppc_altivec_lvehx:
9186 case Intrinsic::ppc_altivec_lvewx:
9191 return isConsecutiveLSLoc(N->getOperand(2), VT, Base, Bytes, Dist, DAG);
9194 if (N->getOpcode() == ISD::INTRINSIC_VOID) {
9196 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9197 default: return false;
9198 case Intrinsic::ppc_qpx_qvstfd:
9199 case Intrinsic::ppc_qpx_qvstfda:
9202 case Intrinsic::ppc_qpx_qvstfs:
9203 case Intrinsic::ppc_qpx_qvstfsa:
9206 case Intrinsic::ppc_qpx_qvstfcd:
9207 case Intrinsic::ppc_qpx_qvstfcda:
9210 case Intrinsic::ppc_qpx_qvstfcs:
9211 case Intrinsic::ppc_qpx_qvstfcsa:
9214 case Intrinsic::ppc_qpx_qvstfiw:
9215 case Intrinsic::ppc_qpx_qvstfiwa:
9216 case Intrinsic::ppc_altivec_stvx:
9217 case Intrinsic::ppc_altivec_stvxl:
9218 case Intrinsic::ppc_vsx_stxvw4x:
9221 case Intrinsic::ppc_vsx_stxvd2x:
9224 case Intrinsic::ppc_altivec_stvebx:
9227 case Intrinsic::ppc_altivec_stvehx:
9230 case Intrinsic::ppc_altivec_stvewx:
9235 return isConsecutiveLSLoc(N->getOperand(3), VT, Base, Bytes, Dist, DAG);
9241 // Return true is there is a nearyby consecutive load to the one provided
9242 // (regardless of alignment). We search up and down the chain, looking though
9243 // token factors and other loads (but nothing else). As a result, a true result
9244 // indicates that it is safe to create a new consecutive load adjacent to the
9246 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
9247 SDValue Chain = LD->getChain();
9248 EVT VT = LD->getMemoryVT();
9250 SmallSet<SDNode *, 16> LoadRoots;
9251 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
9252 SmallSet<SDNode *, 16> Visited;
9254 // First, search up the chain, branching to follow all token-factor operands.
9255 // If we find a consecutive load, then we're done, otherwise, record all
9256 // nodes just above the top-level loads and token factors.
9257 while (!Queue.empty()) {
9258 SDNode *ChainNext = Queue.pop_back_val();
9259 if (!Visited.insert(ChainNext).second)
9262 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(ChainNext)) {
9263 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
9266 if (!Visited.count(ChainLD->getChain().getNode()))
9267 Queue.push_back(ChainLD->getChain().getNode());
9268 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
9269 for (const SDUse &O : ChainNext->ops())
9270 if (!Visited.count(O.getNode()))
9271 Queue.push_back(O.getNode());
9273 LoadRoots.insert(ChainNext);
9276 // Second, search down the chain, starting from the top-level nodes recorded
9277 // in the first phase. These top-level nodes are the nodes just above all
9278 // loads and token factors. Starting with their uses, recursively look though
9279 // all loads (just the chain uses) and token factors to find a consecutive
9284 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
9285 IE = LoadRoots.end(); I != IE; ++I) {
9286 Queue.push_back(*I);
9288 while (!Queue.empty()) {
9289 SDNode *LoadRoot = Queue.pop_back_val();
9290 if (!Visited.insert(LoadRoot).second)
9293 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(LoadRoot))
9294 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
9297 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
9298 UE = LoadRoot->use_end(); UI != UE; ++UI)
9299 if (((isa<MemSDNode>(*UI) &&
9300 cast<MemSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
9301 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
9302 Queue.push_back(*UI);
9309 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
9310 DAGCombinerInfo &DCI) const {
9311 SelectionDAG &DAG = DCI.DAG;
9314 assert(Subtarget.useCRBits() && "Expecting to be tracking CR bits");
9315 // If we're tracking CR bits, we need to be careful that we don't have:
9316 // trunc(binary-ops(zext(x), zext(y)))
9318 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
9319 // such that we're unnecessarily moving things into GPRs when it would be
9320 // better to keep them in CR bits.
9322 // Note that trunc here can be an actual i1 trunc, or can be the effective
9323 // truncation that comes from a setcc or select_cc.
9324 if (N->getOpcode() == ISD::TRUNCATE &&
9325 N->getValueType(0) != MVT::i1)
9328 if (N->getOperand(0).getValueType() != MVT::i32 &&
9329 N->getOperand(0).getValueType() != MVT::i64)
9332 if (N->getOpcode() == ISD::SETCC ||
9333 N->getOpcode() == ISD::SELECT_CC) {
9334 // If we're looking at a comparison, then we need to make sure that the
9335 // high bits (all except for the first) don't matter the result.
9337 cast<CondCodeSDNode>(N->getOperand(
9338 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
9339 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
9341 if (ISD::isSignedIntSetCC(CC)) {
9342 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
9343 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
9345 } else if (ISD::isUnsignedIntSetCC(CC)) {
9346 if (!DAG.MaskedValueIsZero(N->getOperand(0),
9347 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
9348 !DAG.MaskedValueIsZero(N->getOperand(1),
9349 APInt::getHighBitsSet(OpBits, OpBits-1)))
9352 // This is neither a signed nor an unsigned comparison, just make sure
9353 // that the high bits are equal.
9354 APInt Op1Zero, Op1One;
9355 APInt Op2Zero, Op2One;
9356 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
9357 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
9359 // We don't really care about what is known about the first bit (if
9360 // anything), so clear it in all masks prior to comparing them.
9361 Op1Zero.clearBit(0); Op1One.clearBit(0);
9362 Op2Zero.clearBit(0); Op2One.clearBit(0);
9364 if (Op1Zero != Op2Zero || Op1One != Op2One)
9369 // We now know that the higher-order bits are irrelevant, we just need to
9370 // make sure that all of the intermediate operations are bit operations, and
9371 // all inputs are extensions.
9372 if (N->getOperand(0).getOpcode() != ISD::AND &&
9373 N->getOperand(0).getOpcode() != ISD::OR &&
9374 N->getOperand(0).getOpcode() != ISD::XOR &&
9375 N->getOperand(0).getOpcode() != ISD::SELECT &&
9376 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
9377 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
9378 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
9379 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
9380 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
9383 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
9384 N->getOperand(1).getOpcode() != ISD::AND &&
9385 N->getOperand(1).getOpcode() != ISD::OR &&
9386 N->getOperand(1).getOpcode() != ISD::XOR &&
9387 N->getOperand(1).getOpcode() != ISD::SELECT &&
9388 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
9389 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
9390 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
9391 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
9392 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
9395 SmallVector<SDValue, 4> Inputs;
9396 SmallVector<SDValue, 8> BinOps, PromOps;
9397 SmallPtrSet<SDNode *, 16> Visited;
9399 for (unsigned i = 0; i < 2; ++i) {
9400 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
9401 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
9402 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
9403 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
9404 isa<ConstantSDNode>(N->getOperand(i)))
9405 Inputs.push_back(N->getOperand(i));
9407 BinOps.push_back(N->getOperand(i));
9409 if (N->getOpcode() == ISD::TRUNCATE)
9413 // Visit all inputs, collect all binary operations (and, or, xor and
9414 // select) that are all fed by extensions.
9415 while (!BinOps.empty()) {
9416 SDValue BinOp = BinOps.back();
9419 if (!Visited.insert(BinOp.getNode()).second)
9422 PromOps.push_back(BinOp);
9424 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
9425 // The condition of the select is not promoted.
9426 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
9428 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
9431 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
9432 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
9433 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
9434 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
9435 isa<ConstantSDNode>(BinOp.getOperand(i))) {
9436 Inputs.push_back(BinOp.getOperand(i));
9437 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
9438 BinOp.getOperand(i).getOpcode() == ISD::OR ||
9439 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
9440 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
9441 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
9442 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
9443 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
9444 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
9445 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
9446 BinOps.push_back(BinOp.getOperand(i));
9448 // We have an input that is not an extension or another binary
9449 // operation; we'll abort this transformation.
9455 // Make sure that this is a self-contained cluster of operations (which
9456 // is not quite the same thing as saying that everything has only one
9458 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9459 if (isa<ConstantSDNode>(Inputs[i]))
9462 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
9463 UE = Inputs[i].getNode()->use_end();
9466 if (User != N && !Visited.count(User))
9469 // Make sure that we're not going to promote the non-output-value
9470 // operand(s) or SELECT or SELECT_CC.
9471 // FIXME: Although we could sometimes handle this, and it does occur in
9472 // practice that one of the condition inputs to the select is also one of
9473 // the outputs, we currently can't deal with this.
9474 if (User->getOpcode() == ISD::SELECT) {
9475 if (User->getOperand(0) == Inputs[i])
9477 } else if (User->getOpcode() == ISD::SELECT_CC) {
9478 if (User->getOperand(0) == Inputs[i] ||
9479 User->getOperand(1) == Inputs[i])
9485 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
9486 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
9487 UE = PromOps[i].getNode()->use_end();
9490 if (User != N && !Visited.count(User))
9493 // Make sure that we're not going to promote the non-output-value
9494 // operand(s) or SELECT or SELECT_CC.
9495 // FIXME: Although we could sometimes handle this, and it does occur in
9496 // practice that one of the condition inputs to the select is also one of
9497 // the outputs, we currently can't deal with this.
9498 if (User->getOpcode() == ISD::SELECT) {
9499 if (User->getOperand(0) == PromOps[i])
9501 } else if (User->getOpcode() == ISD::SELECT_CC) {
9502 if (User->getOperand(0) == PromOps[i] ||
9503 User->getOperand(1) == PromOps[i])
9509 // Replace all inputs with the extension operand.
9510 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9511 // Constants may have users outside the cluster of to-be-promoted nodes,
9512 // and so we need to replace those as we do the promotions.
9513 if (isa<ConstantSDNode>(Inputs[i]))
9516 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
9519 // Replace all operations (these are all the same, but have a different
9520 // (i1) return type). DAG.getNode will validate that the types of
9521 // a binary operator match, so go through the list in reverse so that
9522 // we've likely promoted both operands first. Any intermediate truncations or
9523 // extensions disappear.
9524 while (!PromOps.empty()) {
9525 SDValue PromOp = PromOps.back();
9528 if (PromOp.getOpcode() == ISD::TRUNCATE ||
9529 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
9530 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
9531 PromOp.getOpcode() == ISD::ANY_EXTEND) {
9532 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
9533 PromOp.getOperand(0).getValueType() != MVT::i1) {
9534 // The operand is not yet ready (see comment below).
9535 PromOps.insert(PromOps.begin(), PromOp);
9539 SDValue RepValue = PromOp.getOperand(0);
9540 if (isa<ConstantSDNode>(RepValue))
9541 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
9543 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
9548 switch (PromOp.getOpcode()) {
9549 default: C = 0; break;
9550 case ISD::SELECT: C = 1; break;
9551 case ISD::SELECT_CC: C = 2; break;
9554 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
9555 PromOp.getOperand(C).getValueType() != MVT::i1) ||
9556 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
9557 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
9558 // The to-be-promoted operands of this node have not yet been
9559 // promoted (this should be rare because we're going through the
9560 // list backward, but if one of the operands has several users in
9561 // this cluster of to-be-promoted nodes, it is possible).
9562 PromOps.insert(PromOps.begin(), PromOp);
9566 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
9567 PromOp.getNode()->op_end());
9569 // If there are any constant inputs, make sure they're replaced now.
9570 for (unsigned i = 0; i < 2; ++i)
9571 if (isa<ConstantSDNode>(Ops[C+i]))
9572 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
9574 DAG.ReplaceAllUsesOfValueWith(PromOp,
9575 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
9578 // Now we're left with the initial truncation itself.
9579 if (N->getOpcode() == ISD::TRUNCATE)
9580 return N->getOperand(0);
9582 // Otherwise, this is a comparison. The operands to be compared have just
9583 // changed type (to i1), but everything else is the same.
9584 return SDValue(N, 0);
9587 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
9588 DAGCombinerInfo &DCI) const {
9589 SelectionDAG &DAG = DCI.DAG;
9592 // If we're tracking CR bits, we need to be careful that we don't have:
9593 // zext(binary-ops(trunc(x), trunc(y)))
9595 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
9596 // such that we're unnecessarily moving things into CR bits that can more
9597 // efficiently stay in GPRs. Note that if we're not certain that the high
9598 // bits are set as required by the final extension, we still may need to do
9599 // some masking to get the proper behavior.
9601 // This same functionality is important on PPC64 when dealing with
9602 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
9603 // the return values of functions. Because it is so similar, it is handled
9606 if (N->getValueType(0) != MVT::i32 &&
9607 N->getValueType(0) != MVT::i64)
9610 if (!((N->getOperand(0).getValueType() == MVT::i1 && Subtarget.useCRBits()) ||
9611 (N->getOperand(0).getValueType() == MVT::i32 && Subtarget.isPPC64())))
9614 if (N->getOperand(0).getOpcode() != ISD::AND &&
9615 N->getOperand(0).getOpcode() != ISD::OR &&
9616 N->getOperand(0).getOpcode() != ISD::XOR &&
9617 N->getOperand(0).getOpcode() != ISD::SELECT &&
9618 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
9621 SmallVector<SDValue, 4> Inputs;
9622 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
9623 SmallPtrSet<SDNode *, 16> Visited;
9625 // Visit all inputs, collect all binary operations (and, or, xor and
9626 // select) that are all fed by truncations.
9627 while (!BinOps.empty()) {
9628 SDValue BinOp = BinOps.back();
9631 if (!Visited.insert(BinOp.getNode()).second)
9634 PromOps.push_back(BinOp);
9636 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
9637 // The condition of the select is not promoted.
9638 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
9640 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
9643 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
9644 isa<ConstantSDNode>(BinOp.getOperand(i))) {
9645 Inputs.push_back(BinOp.getOperand(i));
9646 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
9647 BinOp.getOperand(i).getOpcode() == ISD::OR ||
9648 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
9649 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
9650 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
9651 BinOps.push_back(BinOp.getOperand(i));
9653 // We have an input that is not a truncation or another binary
9654 // operation; we'll abort this transformation.
9660 // The operands of a select that must be truncated when the select is
9661 // promoted because the operand is actually part of the to-be-promoted set.
9662 DenseMap<SDNode *, EVT> SelectTruncOp[2];
9664 // Make sure that this is a self-contained cluster of operations (which
9665 // is not quite the same thing as saying that everything has only one
9667 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9668 if (isa<ConstantSDNode>(Inputs[i]))
9671 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
9672 UE = Inputs[i].getNode()->use_end();
9675 if (User != N && !Visited.count(User))
9678 // If we're going to promote the non-output-value operand(s) or SELECT or
9679 // SELECT_CC, record them for truncation.
9680 if (User->getOpcode() == ISD::SELECT) {
9681 if (User->getOperand(0) == Inputs[i])
9682 SelectTruncOp[0].insert(std::make_pair(User,
9683 User->getOperand(0).getValueType()));
9684 } else if (User->getOpcode() == ISD::SELECT_CC) {
9685 if (User->getOperand(0) == Inputs[i])
9686 SelectTruncOp[0].insert(std::make_pair(User,
9687 User->getOperand(0).getValueType()));
9688 if (User->getOperand(1) == Inputs[i])
9689 SelectTruncOp[1].insert(std::make_pair(User,
9690 User->getOperand(1).getValueType()));
9695 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
9696 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
9697 UE = PromOps[i].getNode()->use_end();
9700 if (User != N && !Visited.count(User))
9703 // If we're going to promote the non-output-value operand(s) or SELECT or
9704 // SELECT_CC, record them for truncation.
9705 if (User->getOpcode() == ISD::SELECT) {
9706 if (User->getOperand(0) == PromOps[i])
9707 SelectTruncOp[0].insert(std::make_pair(User,
9708 User->getOperand(0).getValueType()));
9709 } else if (User->getOpcode() == ISD::SELECT_CC) {
9710 if (User->getOperand(0) == PromOps[i])
9711 SelectTruncOp[0].insert(std::make_pair(User,
9712 User->getOperand(0).getValueType()));
9713 if (User->getOperand(1) == PromOps[i])
9714 SelectTruncOp[1].insert(std::make_pair(User,
9715 User->getOperand(1).getValueType()));
9720 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
9721 bool ReallyNeedsExt = false;
9722 if (N->getOpcode() != ISD::ANY_EXTEND) {
9723 // If all of the inputs are not already sign/zero extended, then
9724 // we'll still need to do that at the end.
9725 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9726 if (isa<ConstantSDNode>(Inputs[i]))
9730 Inputs[i].getOperand(0).getValueSizeInBits();
9731 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
9733 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
9734 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
9735 APInt::getHighBitsSet(OpBits,
9736 OpBits-PromBits))) ||
9737 (N->getOpcode() == ISD::SIGN_EXTEND &&
9738 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
9739 (OpBits-(PromBits-1)))) {
9740 ReallyNeedsExt = true;
9746 // Replace all inputs, either with the truncation operand, or a
9747 // truncation or extension to the final output type.
9748 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9749 // Constant inputs need to be replaced with the to-be-promoted nodes that
9750 // use them because they might have users outside of the cluster of
9752 if (isa<ConstantSDNode>(Inputs[i]))
9755 SDValue InSrc = Inputs[i].getOperand(0);
9756 if (Inputs[i].getValueType() == N->getValueType(0))
9757 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
9758 else if (N->getOpcode() == ISD::SIGN_EXTEND)
9759 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
9760 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
9761 else if (N->getOpcode() == ISD::ZERO_EXTEND)
9762 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
9763 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
9765 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
9766 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
9769 // Replace all operations (these are all the same, but have a different
9770 // (promoted) return type). DAG.getNode will validate that the types of
9771 // a binary operator match, so go through the list in reverse so that
9772 // we've likely promoted both operands first.
9773 while (!PromOps.empty()) {
9774 SDValue PromOp = PromOps.back();
9778 switch (PromOp.getOpcode()) {
9779 default: C = 0; break;
9780 case ISD::SELECT: C = 1; break;
9781 case ISD::SELECT_CC: C = 2; break;
9784 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
9785 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
9786 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
9787 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
9788 // The to-be-promoted operands of this node have not yet been
9789 // promoted (this should be rare because we're going through the
9790 // list backward, but if one of the operands has several users in
9791 // this cluster of to-be-promoted nodes, it is possible).
9792 PromOps.insert(PromOps.begin(), PromOp);
9796 // For SELECT and SELECT_CC nodes, we do a similar check for any
9797 // to-be-promoted comparison inputs.
9798 if (PromOp.getOpcode() == ISD::SELECT ||
9799 PromOp.getOpcode() == ISD::SELECT_CC) {
9800 if ((SelectTruncOp[0].count(PromOp.getNode()) &&
9801 PromOp.getOperand(0).getValueType() != N->getValueType(0)) ||
9802 (SelectTruncOp[1].count(PromOp.getNode()) &&
9803 PromOp.getOperand(1).getValueType() != N->getValueType(0))) {
9804 PromOps.insert(PromOps.begin(), PromOp);
9809 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
9810 PromOp.getNode()->op_end());
9812 // If this node has constant inputs, then they'll need to be promoted here.
9813 for (unsigned i = 0; i < 2; ++i) {
9814 if (!isa<ConstantSDNode>(Ops[C+i]))
9816 if (Ops[C+i].getValueType() == N->getValueType(0))
9819 if (N->getOpcode() == ISD::SIGN_EXTEND)
9820 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
9821 else if (N->getOpcode() == ISD::ZERO_EXTEND)
9822 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
9824 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
9827 // If we've promoted the comparison inputs of a SELECT or SELECT_CC,
9828 // truncate them again to the original value type.
9829 if (PromOp.getOpcode() == ISD::SELECT ||
9830 PromOp.getOpcode() == ISD::SELECT_CC) {
9831 auto SI0 = SelectTruncOp[0].find(PromOp.getNode());
9832 if (SI0 != SelectTruncOp[0].end())
9833 Ops[0] = DAG.getNode(ISD::TRUNCATE, dl, SI0->second, Ops[0]);
9834 auto SI1 = SelectTruncOp[1].find(PromOp.getNode());
9835 if (SI1 != SelectTruncOp[1].end())
9836 Ops[1] = DAG.getNode(ISD::TRUNCATE, dl, SI1->second, Ops[1]);
9839 DAG.ReplaceAllUsesOfValueWith(PromOp,
9840 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
9843 // Now we're left with the initial extension itself.
9844 if (!ReallyNeedsExt)
9845 return N->getOperand(0);
9847 // To zero extend, just mask off everything except for the first bit (in the
9849 if (N->getOpcode() == ISD::ZERO_EXTEND)
9850 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
9851 DAG.getConstant(APInt::getLowBitsSet(
9852 N->getValueSizeInBits(0), PromBits),
9853 dl, N->getValueType(0)));
9855 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
9856 "Invalid extension type");
9857 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0));
9859 DAG.getConstant(N->getValueSizeInBits(0) - PromBits, dl, ShiftAmountTy);
9860 return DAG.getNode(ISD::SRA, dl, N->getValueType(0),
9861 DAG.getNode(ISD::SHL, dl, N->getValueType(0),
9862 N->getOperand(0), ShiftCst), ShiftCst);
9865 SDValue PPCTargetLowering::combineFPToIntToFP(SDNode *N,
9866 DAGCombinerInfo &DCI) const {
9867 assert((N->getOpcode() == ISD::SINT_TO_FP ||
9868 N->getOpcode() == ISD::UINT_TO_FP) &&
9869 "Need an int -> FP conversion node here");
9871 if (!Subtarget.has64BitSupport())
9874 SelectionDAG &DAG = DCI.DAG;
9878 // Don't handle ppc_fp128 here or i1 conversions.
9879 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
9881 if (Op.getOperand(0).getValueType() == MVT::i1)
9884 // For i32 intermediate values, unfortunately, the conversion functions
9885 // leave the upper 32 bits of the value are undefined. Within the set of
9886 // scalar instructions, we have no method for zero- or sign-extending the
9887 // value. Thus, we cannot handle i32 intermediate values here.
9888 if (Op.getOperand(0).getValueType() == MVT::i32)
9891 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
9892 "UINT_TO_FP is supported only with FPCVT");
9894 // If we have FCFIDS, then use it when converting to single-precision.
9895 // Otherwise, convert to double-precision and then round.
9896 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
9897 ? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
9899 : (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
9901 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
9905 // If we're converting from a float, to an int, and back to a float again,
9906 // then we don't need the store/load pair at all.
9907 if ((Op.getOperand(0).getOpcode() == ISD::FP_TO_UINT &&
9908 Subtarget.hasFPCVT()) ||
9909 (Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT)) {
9910 SDValue Src = Op.getOperand(0).getOperand(0);
9911 if (Src.getValueType() == MVT::f32) {
9912 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
9913 DCI.AddToWorklist(Src.getNode());
9917 Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
9920 SDValue Tmp = DAG.getNode(FCTOp, dl, MVT::f64, Src);
9921 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Tmp);
9923 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) {
9924 FP = DAG.getNode(ISD::FP_ROUND, dl,
9925 MVT::f32, FP, DAG.getIntPtrConstant(0, dl));
9926 DCI.AddToWorklist(FP.getNode());
9935 // expandVSXLoadForLE - Convert VSX loads (which may be intrinsics for
9936 // builtins) into loads with swaps.
9937 SDValue PPCTargetLowering::expandVSXLoadForLE(SDNode *N,
9938 DAGCombinerInfo &DCI) const {
9939 SelectionDAG &DAG = DCI.DAG;
9943 MachineMemOperand *MMO;
9945 switch (N->getOpcode()) {
9947 llvm_unreachable("Unexpected opcode for little endian VSX load");
9949 LoadSDNode *LD = cast<LoadSDNode>(N);
9950 Chain = LD->getChain();
9951 Base = LD->getBasePtr();
9952 MMO = LD->getMemOperand();
9953 // If the MMO suggests this isn't a load of a full vector, leave
9954 // things alone. For a built-in, we have to make the change for
9955 // correctness, so if there is a size problem that will be a bug.
9956 if (MMO->getSize() < 16)
9960 case ISD::INTRINSIC_W_CHAIN: {
9961 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
9962 Chain = Intrin->getChain();
9963 // Similarly to the store case below, Intrin->getBasePtr() doesn't get
9964 // us what we want. Get operand 2 instead.
9965 Base = Intrin->getOperand(2);
9966 MMO = Intrin->getMemOperand();
9971 MVT VecTy = N->getValueType(0).getSimpleVT();
9972 SDValue LoadOps[] = { Chain, Base };
9973 SDValue Load = DAG.getMemIntrinsicNode(PPCISD::LXVD2X, dl,
9974 DAG.getVTList(VecTy, MVT::Other),
9975 LoadOps, VecTy, MMO);
9976 DCI.AddToWorklist(Load.getNode());
9977 Chain = Load.getValue(1);
9978 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
9979 DAG.getVTList(VecTy, MVT::Other), Chain, Load);
9980 DCI.AddToWorklist(Swap.getNode());
9984 // expandVSXStoreForLE - Convert VSX stores (which may be intrinsics for
9985 // builtins) into stores with swaps.
9986 SDValue PPCTargetLowering::expandVSXStoreForLE(SDNode *N,
9987 DAGCombinerInfo &DCI) const {
9988 SelectionDAG &DAG = DCI.DAG;
9993 MachineMemOperand *MMO;
9995 switch (N->getOpcode()) {
9997 llvm_unreachable("Unexpected opcode for little endian VSX store");
9999 StoreSDNode *ST = cast<StoreSDNode>(N);
10000 Chain = ST->getChain();
10001 Base = ST->getBasePtr();
10002 MMO = ST->getMemOperand();
10004 // If the MMO suggests this isn't a store of a full vector, leave
10005 // things alone. For a built-in, we have to make the change for
10006 // correctness, so if there is a size problem that will be a bug.
10007 if (MMO->getSize() < 16)
10011 case ISD::INTRINSIC_VOID: {
10012 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
10013 Chain = Intrin->getChain();
10014 // Intrin->getBasePtr() oddly does not get what we want.
10015 Base = Intrin->getOperand(3);
10016 MMO = Intrin->getMemOperand();
10022 SDValue Src = N->getOperand(SrcOpnd);
10023 MVT VecTy = Src.getValueType().getSimpleVT();
10024 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
10025 DAG.getVTList(VecTy, MVT::Other), Chain, Src);
10026 DCI.AddToWorklist(Swap.getNode());
10027 Chain = Swap.getValue(1);
10028 SDValue StoreOps[] = { Chain, Swap, Base };
10029 SDValue Store = DAG.getMemIntrinsicNode(PPCISD::STXVD2X, dl,
10030 DAG.getVTList(MVT::Other),
10031 StoreOps, VecTy, MMO);
10032 DCI.AddToWorklist(Store.getNode());
10036 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
10037 DAGCombinerInfo &DCI) const {
10038 SelectionDAG &DAG = DCI.DAG;
10040 switch (N->getOpcode()) {
10043 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
10044 if (C->isNullValue()) // 0 << V -> 0.
10045 return N->getOperand(0);
10049 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
10050 if (C->isNullValue()) // 0 >>u V -> 0.
10051 return N->getOperand(0);
10055 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
10056 if (C->isNullValue() || // 0 >>s V -> 0.
10057 C->isAllOnesValue()) // -1 >>s V -> -1.
10058 return N->getOperand(0);
10061 case ISD::SIGN_EXTEND:
10062 case ISD::ZERO_EXTEND:
10063 case ISD::ANY_EXTEND:
10064 return DAGCombineExtBoolTrunc(N, DCI);
10065 case ISD::TRUNCATE:
10067 case ISD::SELECT_CC:
10068 return DAGCombineTruncBoolExt(N, DCI);
10069 case ISD::SINT_TO_FP:
10070 case ISD::UINT_TO_FP:
10071 return combineFPToIntToFP(N, DCI);
10073 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
10074 if (Subtarget.hasSTFIWX() && !cast<StoreSDNode>(N)->isTruncatingStore() &&
10075 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
10076 N->getOperand(1).getValueType() == MVT::i32 &&
10077 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
10078 SDValue Val = N->getOperand(1).getOperand(0);
10079 if (Val.getValueType() == MVT::f32) {
10080 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
10081 DCI.AddToWorklist(Val.getNode());
10083 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
10084 DCI.AddToWorklist(Val.getNode());
10087 N->getOperand(0), Val, N->getOperand(2),
10088 DAG.getValueType(N->getOperand(1).getValueType())
10091 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
10092 DAG.getVTList(MVT::Other), Ops,
10093 cast<StoreSDNode>(N)->getMemoryVT(),
10094 cast<StoreSDNode>(N)->getMemOperand());
10095 DCI.AddToWorklist(Val.getNode());
10099 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
10100 if (cast<StoreSDNode>(N)->isUnindexed() &&
10101 N->getOperand(1).getOpcode() == ISD::BSWAP &&
10102 N->getOperand(1).getNode()->hasOneUse() &&
10103 (N->getOperand(1).getValueType() == MVT::i32 ||
10104 N->getOperand(1).getValueType() == MVT::i16 ||
10105 (Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
10106 N->getOperand(1).getValueType() == MVT::i64))) {
10107 SDValue BSwapOp = N->getOperand(1).getOperand(0);
10108 // Do an any-extend to 32-bits if this is a half-word input.
10109 if (BSwapOp.getValueType() == MVT::i16)
10110 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
10113 N->getOperand(0), BSwapOp, N->getOperand(2),
10114 DAG.getValueType(N->getOperand(1).getValueType())
10117 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
10118 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
10119 cast<StoreSDNode>(N)->getMemOperand());
10122 // For little endian, VSX stores require generating xxswapd/lxvd2x.
10123 EVT VT = N->getOperand(1).getValueType();
10124 if (VT.isSimple()) {
10125 MVT StoreVT = VT.getSimpleVT();
10126 if (Subtarget.hasVSX() && Subtarget.isLittleEndian() &&
10127 (StoreVT == MVT::v2f64 || StoreVT == MVT::v2i64 ||
10128 StoreVT == MVT::v4f32 || StoreVT == MVT::v4i32))
10129 return expandVSXStoreForLE(N, DCI);
10134 LoadSDNode *LD = cast<LoadSDNode>(N);
10135 EVT VT = LD->getValueType(0);
10137 // For little endian, VSX loads require generating lxvd2x/xxswapd.
10138 if (VT.isSimple()) {
10139 MVT LoadVT = VT.getSimpleVT();
10140 if (Subtarget.hasVSX() && Subtarget.isLittleEndian() &&
10141 (LoadVT == MVT::v2f64 || LoadVT == MVT::v2i64 ||
10142 LoadVT == MVT::v4f32 || LoadVT == MVT::v4i32))
10143 return expandVSXLoadForLE(N, DCI);
10146 EVT MemVT = LD->getMemoryVT();
10147 Type *Ty = MemVT.getTypeForEVT(*DAG.getContext());
10148 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
10149 Type *STy = MemVT.getScalarType().getTypeForEVT(*DAG.getContext());
10150 unsigned ScalarABIAlignment = getDataLayout()->getABITypeAlignment(STy);
10151 if (LD->isUnindexed() && VT.isVector() &&
10152 ((Subtarget.hasAltivec() && ISD::isNON_EXTLoad(N) &&
10153 // P8 and later hardware should just use LOAD.
10154 !Subtarget.hasP8Vector() && (VT == MVT::v16i8 || VT == MVT::v8i16 ||
10155 VT == MVT::v4i32 || VT == MVT::v4f32)) ||
10156 (Subtarget.hasQPX() && (VT == MVT::v4f64 || VT == MVT::v4f32) &&
10157 LD->getAlignment() >= ScalarABIAlignment)) &&
10158 LD->getAlignment() < ABIAlignment) {
10159 // This is a type-legal unaligned Altivec or QPX load.
10160 SDValue Chain = LD->getChain();
10161 SDValue Ptr = LD->getBasePtr();
10162 bool isLittleEndian = Subtarget.isLittleEndian();
10164 // This implements the loading of unaligned vectors as described in
10165 // the venerable Apple Velocity Engine overview. Specifically:
10166 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
10167 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
10169 // The general idea is to expand a sequence of one or more unaligned
10170 // loads into an alignment-based permutation-control instruction (lvsl
10171 // or lvsr), a series of regular vector loads (which always truncate
10172 // their input address to an aligned address), and a series of
10173 // permutations. The results of these permutations are the requested
10174 // loaded values. The trick is that the last "extra" load is not taken
10175 // from the address you might suspect (sizeof(vector) bytes after the
10176 // last requested load), but rather sizeof(vector) - 1 bytes after the
10177 // last requested vector. The point of this is to avoid a page fault if
10178 // the base address happened to be aligned. This works because if the
10179 // base address is aligned, then adding less than a full vector length
10180 // will cause the last vector in the sequence to be (re)loaded.
10181 // Otherwise, the next vector will be fetched as you might suspect was
10184 // We might be able to reuse the permutation generation from
10185 // a different base address offset from this one by an aligned amount.
10186 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
10187 // optimization later.
10188 Intrinsic::ID Intr, IntrLD, IntrPerm;
10189 MVT PermCntlTy, PermTy, LDTy;
10190 if (Subtarget.hasAltivec()) {
10191 Intr = isLittleEndian ? Intrinsic::ppc_altivec_lvsr :
10192 Intrinsic::ppc_altivec_lvsl;
10193 IntrLD = Intrinsic::ppc_altivec_lvx;
10194 IntrPerm = Intrinsic::ppc_altivec_vperm;
10195 PermCntlTy = MVT::v16i8;
10196 PermTy = MVT::v4i32;
10199 Intr = MemVT == MVT::v4f64 ? Intrinsic::ppc_qpx_qvlpcld :
10200 Intrinsic::ppc_qpx_qvlpcls;
10201 IntrLD = MemVT == MVT::v4f64 ? Intrinsic::ppc_qpx_qvlfd :
10202 Intrinsic::ppc_qpx_qvlfs;
10203 IntrPerm = Intrinsic::ppc_qpx_qvfperm;
10204 PermCntlTy = MVT::v4f64;
10205 PermTy = MVT::v4f64;
10206 LDTy = MemVT.getSimpleVT();
10209 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, PermCntlTy);
10211 // Create the new MMO for the new base load. It is like the original MMO,
10212 // but represents an area in memory almost twice the vector size centered
10213 // on the original address. If the address is unaligned, we might start
10214 // reading up to (sizeof(vector)-1) bytes below the address of the
10215 // original unaligned load.
10216 MachineFunction &MF = DAG.getMachineFunction();
10217 MachineMemOperand *BaseMMO =
10218 MF.getMachineMemOperand(LD->getMemOperand(), -MemVT.getStoreSize()+1,
10219 2*MemVT.getStoreSize()-1);
10221 // Create the new base load.
10222 SDValue LDXIntID = DAG.getTargetConstant(IntrLD, dl, getPointerTy());
10223 SDValue BaseLoadOps[] = { Chain, LDXIntID, Ptr };
10225 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
10226 DAG.getVTList(PermTy, MVT::Other),
10227 BaseLoadOps, LDTy, BaseMMO);
10229 // Note that the value of IncOffset (which is provided to the next
10230 // load's pointer info offset value, and thus used to calculate the
10231 // alignment), and the value of IncValue (which is actually used to
10232 // increment the pointer value) are different! This is because we
10233 // require the next load to appear to be aligned, even though it
10234 // is actually offset from the base pointer by a lesser amount.
10235 int IncOffset = VT.getSizeInBits() / 8;
10236 int IncValue = IncOffset;
10238 // Walk (both up and down) the chain looking for another load at the real
10239 // (aligned) offset (the alignment of the other load does not matter in
10240 // this case). If found, then do not use the offset reduction trick, as
10241 // that will prevent the loads from being later combined (as they would
10242 // otherwise be duplicates).
10243 if (!findConsecutiveLoad(LD, DAG))
10246 SDValue Increment = DAG.getConstant(IncValue, dl, getPointerTy());
10247 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
10249 MachineMemOperand *ExtraMMO =
10250 MF.getMachineMemOperand(LD->getMemOperand(),
10251 1, 2*MemVT.getStoreSize()-1);
10252 SDValue ExtraLoadOps[] = { Chain, LDXIntID, Ptr };
10253 SDValue ExtraLoad =
10254 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
10255 DAG.getVTList(PermTy, MVT::Other),
10256 ExtraLoadOps, LDTy, ExtraMMO);
10258 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
10259 BaseLoad.getValue(1), ExtraLoad.getValue(1));
10261 // Because vperm has a big-endian bias, we must reverse the order
10262 // of the input vectors and complement the permute control vector
10263 // when generating little endian code. We have already handled the
10264 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
10265 // and ExtraLoad here.
10267 if (isLittleEndian)
10268 Perm = BuildIntrinsicOp(IntrPerm,
10269 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
10271 Perm = BuildIntrinsicOp(IntrPerm,
10272 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
10275 Perm = Subtarget.hasAltivec() ?
10276 DAG.getNode(ISD::BITCAST, dl, VT, Perm) :
10277 DAG.getNode(ISD::FP_ROUND, dl, VT, Perm, // QPX
10278 DAG.getTargetConstant(1, dl, MVT::i64));
10279 // second argument is 1 because this rounding
10280 // is always exact.
10282 // The output of the permutation is our loaded result, the TokenFactor is
10284 DCI.CombineTo(N, Perm, TF);
10285 return SDValue(N, 0);
10289 case ISD::INTRINSIC_WO_CHAIN: {
10290 bool isLittleEndian = Subtarget.isLittleEndian();
10291 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
10292 Intrinsic::ID Intr = (isLittleEndian ? Intrinsic::ppc_altivec_lvsr
10293 : Intrinsic::ppc_altivec_lvsl);
10294 if ((IID == Intr ||
10295 IID == Intrinsic::ppc_qpx_qvlpcld ||
10296 IID == Intrinsic::ppc_qpx_qvlpcls) &&
10297 N->getOperand(1)->getOpcode() == ISD::ADD) {
10298 SDValue Add = N->getOperand(1);
10300 int Bits = IID == Intrinsic::ppc_qpx_qvlpcld ?
10301 5 /* 32 byte alignment */ : 4 /* 16 byte alignment */;
10303 if (DAG.MaskedValueIsZero(
10304 Add->getOperand(1),
10305 APInt::getAllOnesValue(Bits /* alignment */)
10307 Add.getValueType().getScalarType().getSizeInBits()))) {
10308 SDNode *BasePtr = Add->getOperand(0).getNode();
10309 for (SDNode::use_iterator UI = BasePtr->use_begin(),
10310 UE = BasePtr->use_end();
10312 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
10313 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() == IID) {
10314 // We've found another LVSL/LVSR, and this address is an aligned
10315 // multiple of that one. The results will be the same, so use the
10316 // one we've just found instead.
10318 return SDValue(*UI, 0);
10323 if (isa<ConstantSDNode>(Add->getOperand(1))) {
10324 SDNode *BasePtr = Add->getOperand(0).getNode();
10325 for (SDNode::use_iterator UI = BasePtr->use_begin(),
10326 UE = BasePtr->use_end(); UI != UE; ++UI) {
10327 if (UI->getOpcode() == ISD::ADD &&
10328 isa<ConstantSDNode>(UI->getOperand(1)) &&
10329 (cast<ConstantSDNode>(Add->getOperand(1))->getZExtValue() -
10330 cast<ConstantSDNode>(UI->getOperand(1))->getZExtValue()) %
10331 (1ULL << Bits) == 0) {
10332 SDNode *OtherAdd = *UI;
10333 for (SDNode::use_iterator VI = OtherAdd->use_begin(),
10334 VE = OtherAdd->use_end(); VI != VE; ++VI) {
10335 if (VI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
10336 cast<ConstantSDNode>(VI->getOperand(0))->getZExtValue() == IID) {
10337 return SDValue(*VI, 0);
10347 case ISD::INTRINSIC_W_CHAIN: {
10348 // For little endian, VSX loads require generating lxvd2x/xxswapd.
10349 if (Subtarget.hasVSX() && Subtarget.isLittleEndian()) {
10350 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
10353 case Intrinsic::ppc_vsx_lxvw4x:
10354 case Intrinsic::ppc_vsx_lxvd2x:
10355 return expandVSXLoadForLE(N, DCI);
10360 case ISD::INTRINSIC_VOID: {
10361 // For little endian, VSX stores require generating xxswapd/stxvd2x.
10362 if (Subtarget.hasVSX() && Subtarget.isLittleEndian()) {
10363 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
10366 case Intrinsic::ppc_vsx_stxvw4x:
10367 case Intrinsic::ppc_vsx_stxvd2x:
10368 return expandVSXStoreForLE(N, DCI);
10374 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
10375 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
10376 N->getOperand(0).hasOneUse() &&
10377 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
10378 (Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
10379 N->getValueType(0) == MVT::i64))) {
10380 SDValue Load = N->getOperand(0);
10381 LoadSDNode *LD = cast<LoadSDNode>(Load);
10382 // Create the byte-swapping load.
10384 LD->getChain(), // Chain
10385 LD->getBasePtr(), // Ptr
10386 DAG.getValueType(N->getValueType(0)) // VT
10389 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
10390 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
10391 MVT::i64 : MVT::i32, MVT::Other),
10392 Ops, LD->getMemoryVT(), LD->getMemOperand());
10394 // If this is an i16 load, insert the truncate.
10395 SDValue ResVal = BSLoad;
10396 if (N->getValueType(0) == MVT::i16)
10397 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
10399 // First, combine the bswap away. This makes the value produced by the
10401 DCI.CombineTo(N, ResVal);
10403 // Next, combine the load away, we give it a bogus result value but a real
10404 // chain result. The result value is dead because the bswap is dead.
10405 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
10407 // Return N so it doesn't get rechecked!
10408 return SDValue(N, 0);
10412 case PPCISD::VCMP: {
10413 // If a VCMPo node already exists with exactly the same operands as this
10414 // node, use its result instead of this node (VCMPo computes both a CR6 and
10415 // a normal output).
10417 if (!N->getOperand(0).hasOneUse() &&
10418 !N->getOperand(1).hasOneUse() &&
10419 !N->getOperand(2).hasOneUse()) {
10421 // Scan all of the users of the LHS, looking for VCMPo's that match.
10422 SDNode *VCMPoNode = nullptr;
10424 SDNode *LHSN = N->getOperand(0).getNode();
10425 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
10427 if (UI->getOpcode() == PPCISD::VCMPo &&
10428 UI->getOperand(1) == N->getOperand(1) &&
10429 UI->getOperand(2) == N->getOperand(2) &&
10430 UI->getOperand(0) == N->getOperand(0)) {
10435 // If there is no VCMPo node, or if the flag value has a single use, don't
10437 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
10440 // Look at the (necessarily single) use of the flag value. If it has a
10441 // chain, this transformation is more complex. Note that multiple things
10442 // could use the value result, which we should ignore.
10443 SDNode *FlagUser = nullptr;
10444 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
10445 FlagUser == nullptr; ++UI) {
10446 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
10447 SDNode *User = *UI;
10448 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
10449 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
10456 // If the user is a MFOCRF instruction, we know this is safe.
10457 // Otherwise we give up for right now.
10458 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
10459 return SDValue(VCMPoNode, 0);
10463 case ISD::BRCOND: {
10464 SDValue Cond = N->getOperand(1);
10465 SDValue Target = N->getOperand(2);
10467 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
10468 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
10469 Intrinsic::ppc_is_decremented_ctr_nonzero) {
10471 // We now need to make the intrinsic dead (it cannot be instruction
10473 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
10474 assert(Cond.getNode()->hasOneUse() &&
10475 "Counter decrement has more than one use");
10477 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
10478 N->getOperand(0), Target);
10483 // If this is a branch on an altivec predicate comparison, lower this so
10484 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
10485 // lowering is done pre-legalize, because the legalizer lowers the predicate
10486 // compare down to code that is difficult to reassemble.
10487 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
10488 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
10490 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
10491 // value. If so, pass-through the AND to get to the intrinsic.
10492 if (LHS.getOpcode() == ISD::AND &&
10493 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
10494 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
10495 Intrinsic::ppc_is_decremented_ctr_nonzero &&
10496 isa<ConstantSDNode>(LHS.getOperand(1)) &&
10497 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
10499 LHS = LHS.getOperand(0);
10501 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
10502 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
10503 Intrinsic::ppc_is_decremented_ctr_nonzero &&
10504 isa<ConstantSDNode>(RHS)) {
10505 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
10506 "Counter decrement comparison is not EQ or NE");
10508 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
10509 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
10510 (CC == ISD::SETNE && !Val);
10512 // We now need to make the intrinsic dead (it cannot be instruction
10514 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
10515 assert(LHS.getNode()->hasOneUse() &&
10516 "Counter decrement has more than one use");
10518 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
10519 N->getOperand(0), N->getOperand(4));
10525 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
10526 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
10527 getAltivecCompareInfo(LHS, CompareOpc, isDot, Subtarget)) {
10528 assert(isDot && "Can't compare against a vector result!");
10530 // If this is a comparison against something other than 0/1, then we know
10531 // that the condition is never/always true.
10532 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
10533 if (Val != 0 && Val != 1) {
10534 if (CC == ISD::SETEQ) // Cond never true, remove branch.
10535 return N->getOperand(0);
10536 // Always !=, turn it into an unconditional branch.
10537 return DAG.getNode(ISD::BR, dl, MVT::Other,
10538 N->getOperand(0), N->getOperand(4));
10541 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
10543 // Create the PPCISD altivec 'dot' comparison node.
10545 LHS.getOperand(2), // LHS of compare
10546 LHS.getOperand(3), // RHS of compare
10547 DAG.getConstant(CompareOpc, dl, MVT::i32)
10549 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
10550 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
10552 // Unpack the result based on how the target uses it.
10553 PPC::Predicate CompOpc;
10554 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
10555 default: // Can't happen, don't crash on invalid number though.
10556 case 0: // Branch on the value of the EQ bit of CR6.
10557 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
10559 case 1: // Branch on the inverted value of the EQ bit of CR6.
10560 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
10562 case 2: // Branch on the value of the LT bit of CR6.
10563 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
10565 case 3: // Branch on the inverted value of the LT bit of CR6.
10566 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
10570 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
10571 DAG.getConstant(CompOpc, dl, MVT::i32),
10572 DAG.getRegister(PPC::CR6, MVT::i32),
10573 N->getOperand(4), CompNode.getValue(1));
10583 PPCTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
10585 std::vector<SDNode *> *Created) const {
10586 // fold (sdiv X, pow2)
10587 EVT VT = N->getValueType(0);
10588 if (VT == MVT::i64 && !Subtarget.isPPC64())
10590 if ((VT != MVT::i32 && VT != MVT::i64) ||
10591 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
10595 SDValue N0 = N->getOperand(0);
10597 bool IsNegPow2 = (-Divisor).isPowerOf2();
10598 unsigned Lg2 = (IsNegPow2 ? -Divisor : Divisor).countTrailingZeros();
10599 SDValue ShiftAmt = DAG.getConstant(Lg2, DL, VT);
10601 SDValue Op = DAG.getNode(PPCISD::SRA_ADDZE, DL, VT, N0, ShiftAmt);
10603 Created->push_back(Op.getNode());
10606 Op = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Op);
10608 Created->push_back(Op.getNode());
10614 //===----------------------------------------------------------------------===//
10615 // Inline Assembly Support
10616 //===----------------------------------------------------------------------===//
10618 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
10621 const SelectionDAG &DAG,
10622 unsigned Depth) const {
10623 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
10624 switch (Op.getOpcode()) {
10626 case PPCISD::LBRX: {
10627 // lhbrx is known to have the top bits cleared out.
10628 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
10629 KnownZero = 0xFFFF0000;
10632 case ISD::INTRINSIC_WO_CHAIN: {
10633 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
10635 case Intrinsic::ppc_altivec_vcmpbfp_p:
10636 case Intrinsic::ppc_altivec_vcmpeqfp_p:
10637 case Intrinsic::ppc_altivec_vcmpequb_p:
10638 case Intrinsic::ppc_altivec_vcmpequh_p:
10639 case Intrinsic::ppc_altivec_vcmpequw_p:
10640 case Intrinsic::ppc_altivec_vcmpequd_p:
10641 case Intrinsic::ppc_altivec_vcmpgefp_p:
10642 case Intrinsic::ppc_altivec_vcmpgtfp_p:
10643 case Intrinsic::ppc_altivec_vcmpgtsb_p:
10644 case Intrinsic::ppc_altivec_vcmpgtsh_p:
10645 case Intrinsic::ppc_altivec_vcmpgtsw_p:
10646 case Intrinsic::ppc_altivec_vcmpgtsd_p:
10647 case Intrinsic::ppc_altivec_vcmpgtub_p:
10648 case Intrinsic::ppc_altivec_vcmpgtuh_p:
10649 case Intrinsic::ppc_altivec_vcmpgtuw_p:
10650 case Intrinsic::ppc_altivec_vcmpgtud_p:
10651 KnownZero = ~1U; // All bits but the low one are known to be zero.
10658 unsigned PPCTargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
10659 switch (Subtarget.getDarwinDirective()) {
10662 case PPC::DIR_PWR4:
10663 case PPC::DIR_PWR5:
10664 case PPC::DIR_PWR5X:
10665 case PPC::DIR_PWR6:
10666 case PPC::DIR_PWR6X:
10667 case PPC::DIR_PWR7:
10668 case PPC::DIR_PWR8: {
10672 const PPCInstrInfo *TII = Subtarget.getInstrInfo();
10674 // For small loops (between 5 and 8 instructions), align to a 32-byte
10675 // boundary so that the entire loop fits in one instruction-cache line.
10676 uint64_t LoopSize = 0;
10677 for (auto I = ML->block_begin(), IE = ML->block_end(); I != IE; ++I)
10678 for (auto J = (*I)->begin(), JE = (*I)->end(); J != JE; ++J)
10679 LoopSize += TII->GetInstSizeInBytes(J);
10681 if (LoopSize > 16 && LoopSize <= 32)
10688 return TargetLowering::getPrefLoopAlignment(ML);
10691 /// getConstraintType - Given a constraint, return the type of
10692 /// constraint it is for this target.
10693 PPCTargetLowering::ConstraintType
10694 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
10695 if (Constraint.size() == 1) {
10696 switch (Constraint[0]) {
10703 return C_RegisterClass;
10705 // FIXME: While Z does indicate a memory constraint, it specifically
10706 // indicates an r+r address (used in conjunction with the 'y' modifier
10707 // in the replacement string). Currently, we're forcing the base
10708 // register to be r0 in the asm printer (which is interpreted as zero)
10709 // and forming the complete address in the second register. This is
10713 } else if (Constraint == "wc") { // individual CR bits.
10714 return C_RegisterClass;
10715 } else if (Constraint == "wa" || Constraint == "wd" ||
10716 Constraint == "wf" || Constraint == "ws") {
10717 return C_RegisterClass; // VSX registers.
10719 return TargetLowering::getConstraintType(Constraint);
10722 /// Examine constraint type and operand type and determine a weight value.
10723 /// This object must already have been set up with the operand type
10724 /// and the current alternative constraint selected.
10725 TargetLowering::ConstraintWeight
10726 PPCTargetLowering::getSingleConstraintMatchWeight(
10727 AsmOperandInfo &info, const char *constraint) const {
10728 ConstraintWeight weight = CW_Invalid;
10729 Value *CallOperandVal = info.CallOperandVal;
10730 // If we don't have a value, we can't do a match,
10731 // but allow it at the lowest weight.
10732 if (!CallOperandVal)
10734 Type *type = CallOperandVal->getType();
10736 // Look at the constraint type.
10737 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
10738 return CW_Register; // an individual CR bit.
10739 else if ((StringRef(constraint) == "wa" ||
10740 StringRef(constraint) == "wd" ||
10741 StringRef(constraint) == "wf") &&
10742 type->isVectorTy())
10743 return CW_Register;
10744 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
10745 return CW_Register;
10747 switch (*constraint) {
10749 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
10752 if (type->isIntegerTy())
10753 weight = CW_Register;
10756 if (type->isFloatTy())
10757 weight = CW_Register;
10760 if (type->isDoubleTy())
10761 weight = CW_Register;
10764 if (type->isVectorTy())
10765 weight = CW_Register;
10768 weight = CW_Register;
10771 weight = CW_Memory;
10777 std::pair<unsigned, const TargetRegisterClass *>
10778 PPCTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
10779 const std::string &Constraint,
10781 if (Constraint.size() == 1) {
10782 // GCC RS6000 Constraint Letters
10783 switch (Constraint[0]) {
10784 case 'b': // R1-R31
10785 if (VT == MVT::i64 && Subtarget.isPPC64())
10786 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
10787 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
10788 case 'r': // R0-R31
10789 if (VT == MVT::i64 && Subtarget.isPPC64())
10790 return std::make_pair(0U, &PPC::G8RCRegClass);
10791 return std::make_pair(0U, &PPC::GPRCRegClass);
10793 if (VT == MVT::f32 || VT == MVT::i32)
10794 return std::make_pair(0U, &PPC::F4RCRegClass);
10795 if (VT == MVT::f64 || VT == MVT::i64)
10796 return std::make_pair(0U, &PPC::F8RCRegClass);
10797 if (VT == MVT::v4f64 && Subtarget.hasQPX())
10798 return std::make_pair(0U, &PPC::QFRCRegClass);
10799 if (VT == MVT::v4f32 && Subtarget.hasQPX())
10800 return std::make_pair(0U, &PPC::QSRCRegClass);
10803 if (VT == MVT::v4f64 && Subtarget.hasQPX())
10804 return std::make_pair(0U, &PPC::QFRCRegClass);
10805 if (VT == MVT::v4f32 && Subtarget.hasQPX())
10806 return std::make_pair(0U, &PPC::QSRCRegClass);
10807 return std::make_pair(0U, &PPC::VRRCRegClass);
10809 return std::make_pair(0U, &PPC::CRRCRegClass);
10811 } else if (Constraint == "wc") { // an individual CR bit.
10812 return std::make_pair(0U, &PPC::CRBITRCRegClass);
10813 } else if (Constraint == "wa" || Constraint == "wd" ||
10814 Constraint == "wf") {
10815 return std::make_pair(0U, &PPC::VSRCRegClass);
10816 } else if (Constraint == "ws") {
10817 if (VT == MVT::f32)
10818 return std::make_pair(0U, &PPC::VSSRCRegClass);
10820 return std::make_pair(0U, &PPC::VSFRCRegClass);
10823 std::pair<unsigned, const TargetRegisterClass *> R =
10824 TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
10826 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
10827 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
10828 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
10830 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
10831 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
10832 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
10833 PPC::GPRCRegClass.contains(R.first))
10834 return std::make_pair(TRI->getMatchingSuperReg(R.first,
10835 PPC::sub_32, &PPC::G8RCRegClass),
10836 &PPC::G8RCRegClass);
10838 // GCC accepts 'cc' as an alias for 'cr0', and we need to do the same.
10839 if (!R.second && StringRef("{cc}").equals_lower(Constraint)) {
10840 R.first = PPC::CR0;
10841 R.second = &PPC::CRRCRegClass;
10848 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
10849 /// vector. If it is invalid, don't add anything to Ops.
10850 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
10851 std::string &Constraint,
10852 std::vector<SDValue>&Ops,
10853 SelectionDAG &DAG) const {
10856 // Only support length 1 constraints.
10857 if (Constraint.length() > 1) return;
10859 char Letter = Constraint[0];
10870 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
10871 if (!CST) return; // Must be an immediate to match.
10873 int64_t Value = CST->getSExtValue();
10874 EVT TCVT = MVT::i64; // All constants taken to be 64 bits so that negative
10875 // numbers are printed as such.
10877 default: llvm_unreachable("Unknown constraint letter!");
10878 case 'I': // "I" is a signed 16-bit constant.
10879 if (isInt<16>(Value))
10880 Result = DAG.getTargetConstant(Value, dl, TCVT);
10882 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
10883 if (isShiftedUInt<16, 16>(Value))
10884 Result = DAG.getTargetConstant(Value, dl, TCVT);
10886 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
10887 if (isShiftedInt<16, 16>(Value))
10888 Result = DAG.getTargetConstant(Value, dl, TCVT);
10890 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
10891 if (isUInt<16>(Value))
10892 Result = DAG.getTargetConstant(Value, dl, TCVT);
10894 case 'M': // "M" is a constant that is greater than 31.
10896 Result = DAG.getTargetConstant(Value, dl, TCVT);
10898 case 'N': // "N" is a positive constant that is an exact power of two.
10899 if (Value > 0 && isPowerOf2_64(Value))
10900 Result = DAG.getTargetConstant(Value, dl, TCVT);
10902 case 'O': // "O" is the constant zero.
10904 Result = DAG.getTargetConstant(Value, dl, TCVT);
10906 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
10907 if (isInt<16>(-Value))
10908 Result = DAG.getTargetConstant(Value, dl, TCVT);
10915 if (Result.getNode()) {
10916 Ops.push_back(Result);
10920 // Handle standard constraint letters.
10921 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
10924 // isLegalAddressingMode - Return true if the addressing mode represented
10925 // by AM is legal for this target, for a load/store of the specified type.
10926 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
10928 unsigned AS) const {
10929 // PPC does not allow r+i addressing modes for vectors!
10930 if (Ty->isVectorTy() && AM.BaseOffs != 0)
10933 // PPC allows a sign-extended 16-bit immediate field.
10934 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
10937 // No global is ever allowed as a base.
10941 // PPC only support r+r,
10942 switch (AM.Scale) {
10943 case 0: // "r+i" or just "i", depending on HasBaseReg.
10946 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
10948 // Otherwise we have r+r or r+i.
10951 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
10953 // Allow 2*r as r+r.
10956 // No other scales are supported.
10963 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
10964 SelectionDAG &DAG) const {
10965 MachineFunction &MF = DAG.getMachineFunction();
10966 MachineFrameInfo *MFI = MF.getFrameInfo();
10967 MFI->setReturnAddressIsTaken(true);
10969 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
10973 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
10975 // Make sure the function does not optimize away the store of the RA to
10977 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
10978 FuncInfo->setLRStoreRequired();
10979 bool isPPC64 = Subtarget.isPPC64();
10982 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
10984 DAG.getConstant(Subtarget.getFrameLowering()->getReturnSaveOffset(), dl,
10985 isPPC64 ? MVT::i64 : MVT::i32);
10986 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
10987 DAG.getNode(ISD::ADD, dl, getPointerTy(),
10988 FrameAddr, Offset),
10989 MachinePointerInfo(), false, false, false, 0);
10992 // Just load the return address off the stack.
10993 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
10994 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
10995 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
10998 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
10999 SelectionDAG &DAG) const {
11001 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11003 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
11004 bool isPPC64 = PtrVT == MVT::i64;
11006 MachineFunction &MF = DAG.getMachineFunction();
11007 MachineFrameInfo *MFI = MF.getFrameInfo();
11008 MFI->setFrameAddressIsTaken(true);
11010 // Naked functions never have a frame pointer, and so we use r1. For all
11011 // other functions, this decision must be delayed until during PEI.
11013 if (MF.getFunction()->hasFnAttribute(Attribute::Naked))
11014 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
11016 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
11018 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
11021 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
11022 FrameAddr, MachinePointerInfo(), false, false,
11027 // FIXME? Maybe this could be a TableGen attribute on some registers and
11028 // this table could be generated automatically from RegInfo.
11029 unsigned PPCTargetLowering::getRegisterByName(const char* RegName,
11031 bool isPPC64 = Subtarget.isPPC64();
11032 bool isDarwinABI = Subtarget.isDarwinABI();
11034 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
11035 (!isPPC64 && VT != MVT::i32))
11036 report_fatal_error("Invalid register global variable type");
11038 bool is64Bit = isPPC64 && VT == MVT::i64;
11039 unsigned Reg = StringSwitch<unsigned>(RegName)
11040 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
11041 .Case("r2", (isDarwinABI || isPPC64) ? 0 : PPC::R2)
11042 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
11043 (is64Bit ? PPC::X13 : PPC::R13))
11048 report_fatal_error("Invalid register name global variable");
11052 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
11053 // The PowerPC target isn't yet aware of offsets.
11057 bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
11059 unsigned Intrinsic) const {
11061 switch (Intrinsic) {
11062 case Intrinsic::ppc_qpx_qvlfd:
11063 case Intrinsic::ppc_qpx_qvlfs:
11064 case Intrinsic::ppc_qpx_qvlfcd:
11065 case Intrinsic::ppc_qpx_qvlfcs:
11066 case Intrinsic::ppc_qpx_qvlfiwa:
11067 case Intrinsic::ppc_qpx_qvlfiwz:
11068 case Intrinsic::ppc_altivec_lvx:
11069 case Intrinsic::ppc_altivec_lvxl:
11070 case Intrinsic::ppc_altivec_lvebx:
11071 case Intrinsic::ppc_altivec_lvehx:
11072 case Intrinsic::ppc_altivec_lvewx:
11073 case Intrinsic::ppc_vsx_lxvd2x:
11074 case Intrinsic::ppc_vsx_lxvw4x: {
11076 switch (Intrinsic) {
11077 case Intrinsic::ppc_altivec_lvebx:
11080 case Intrinsic::ppc_altivec_lvehx:
11083 case Intrinsic::ppc_altivec_lvewx:
11086 case Intrinsic::ppc_vsx_lxvd2x:
11089 case Intrinsic::ppc_qpx_qvlfd:
11092 case Intrinsic::ppc_qpx_qvlfs:
11095 case Intrinsic::ppc_qpx_qvlfcd:
11098 case Intrinsic::ppc_qpx_qvlfcs:
11106 Info.opc = ISD::INTRINSIC_W_CHAIN;
11108 Info.ptrVal = I.getArgOperand(0);
11109 Info.offset = -VT.getStoreSize()+1;
11110 Info.size = 2*VT.getStoreSize()-1;
11113 Info.readMem = true;
11114 Info.writeMem = false;
11117 case Intrinsic::ppc_qpx_qvlfda:
11118 case Intrinsic::ppc_qpx_qvlfsa:
11119 case Intrinsic::ppc_qpx_qvlfcda:
11120 case Intrinsic::ppc_qpx_qvlfcsa:
11121 case Intrinsic::ppc_qpx_qvlfiwaa:
11122 case Intrinsic::ppc_qpx_qvlfiwza: {
11124 switch (Intrinsic) {
11125 case Intrinsic::ppc_qpx_qvlfda:
11128 case Intrinsic::ppc_qpx_qvlfsa:
11131 case Intrinsic::ppc_qpx_qvlfcda:
11134 case Intrinsic::ppc_qpx_qvlfcsa:
11142 Info.opc = ISD::INTRINSIC_W_CHAIN;
11144 Info.ptrVal = I.getArgOperand(0);
11146 Info.size = VT.getStoreSize();
11149 Info.readMem = true;
11150 Info.writeMem = false;
11153 case Intrinsic::ppc_qpx_qvstfd:
11154 case Intrinsic::ppc_qpx_qvstfs:
11155 case Intrinsic::ppc_qpx_qvstfcd:
11156 case Intrinsic::ppc_qpx_qvstfcs:
11157 case Intrinsic::ppc_qpx_qvstfiw:
11158 case Intrinsic::ppc_altivec_stvx:
11159 case Intrinsic::ppc_altivec_stvxl:
11160 case Intrinsic::ppc_altivec_stvebx:
11161 case Intrinsic::ppc_altivec_stvehx:
11162 case Intrinsic::ppc_altivec_stvewx:
11163 case Intrinsic::ppc_vsx_stxvd2x:
11164 case Intrinsic::ppc_vsx_stxvw4x: {
11166 switch (Intrinsic) {
11167 case Intrinsic::ppc_altivec_stvebx:
11170 case Intrinsic::ppc_altivec_stvehx:
11173 case Intrinsic::ppc_altivec_stvewx:
11176 case Intrinsic::ppc_vsx_stxvd2x:
11179 case Intrinsic::ppc_qpx_qvstfd:
11182 case Intrinsic::ppc_qpx_qvstfs:
11185 case Intrinsic::ppc_qpx_qvstfcd:
11188 case Intrinsic::ppc_qpx_qvstfcs:
11196 Info.opc = ISD::INTRINSIC_VOID;
11198 Info.ptrVal = I.getArgOperand(1);
11199 Info.offset = -VT.getStoreSize()+1;
11200 Info.size = 2*VT.getStoreSize()-1;
11203 Info.readMem = false;
11204 Info.writeMem = true;
11207 case Intrinsic::ppc_qpx_qvstfda:
11208 case Intrinsic::ppc_qpx_qvstfsa:
11209 case Intrinsic::ppc_qpx_qvstfcda:
11210 case Intrinsic::ppc_qpx_qvstfcsa:
11211 case Intrinsic::ppc_qpx_qvstfiwa: {
11213 switch (Intrinsic) {
11214 case Intrinsic::ppc_qpx_qvstfda:
11217 case Intrinsic::ppc_qpx_qvstfsa:
11220 case Intrinsic::ppc_qpx_qvstfcda:
11223 case Intrinsic::ppc_qpx_qvstfcsa:
11231 Info.opc = ISD::INTRINSIC_VOID;
11233 Info.ptrVal = I.getArgOperand(1);
11235 Info.size = VT.getStoreSize();
11238 Info.readMem = false;
11239 Info.writeMem = true;
11249 /// getOptimalMemOpType - Returns the target specific optimal type for load
11250 /// and store operations as a result of memset, memcpy, and memmove
11251 /// lowering. If DstAlign is zero that means it's safe to destination
11252 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
11253 /// means there isn't a need to check it against alignment requirement,
11254 /// probably because the source does not need to be loaded. If 'IsMemset' is
11255 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
11256 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
11257 /// source is constant so it does not need to be loaded.
11258 /// It returns EVT::Other if the type should be determined using generic
11259 /// target-independent logic.
11260 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
11261 unsigned DstAlign, unsigned SrcAlign,
11262 bool IsMemset, bool ZeroMemset,
11264 MachineFunction &MF) const {
11265 if (getTargetMachine().getOptLevel() != CodeGenOpt::None) {
11266 const Function *F = MF.getFunction();
11267 // When expanding a memset, require at least two QPX instructions to cover
11268 // the cost of loading the value to be stored from the constant pool.
11269 if (Subtarget.hasQPX() && Size >= 32 && (!IsMemset || Size >= 64) &&
11270 (!SrcAlign || SrcAlign >= 32) && (!DstAlign || DstAlign >= 32) &&
11271 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
11275 // We should use Altivec/VSX loads and stores when available. For unaligned
11276 // addresses, unaligned VSX loads are only fast starting with the P8.
11277 if (Subtarget.hasAltivec() && Size >= 16 &&
11278 (((!SrcAlign || SrcAlign >= 16) && (!DstAlign || DstAlign >= 16)) ||
11279 ((IsMemset && Subtarget.hasVSX()) || Subtarget.hasP8Vector())))
11283 if (Subtarget.isPPC64()) {
11290 /// \brief Returns true if it is beneficial to convert a load of a constant
11291 /// to just the constant itself.
11292 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
11294 assert(Ty->isIntegerTy());
11296 unsigned BitSize = Ty->getPrimitiveSizeInBits();
11297 if (BitSize == 0 || BitSize > 64)
11302 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11303 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11305 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11306 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11307 return NumBits1 == 64 && NumBits2 == 32;
11310 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11311 if (!VT1.isInteger() || !VT2.isInteger())
11313 unsigned NumBits1 = VT1.getSizeInBits();
11314 unsigned NumBits2 = VT2.getSizeInBits();
11315 return NumBits1 == 64 && NumBits2 == 32;
11318 bool PPCTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
11319 // Generally speaking, zexts are not free, but they are free when they can be
11320 // folded with other operations.
11321 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Val)) {
11322 EVT MemVT = LD->getMemoryVT();
11323 if ((MemVT == MVT::i1 || MemVT == MVT::i8 || MemVT == MVT::i16 ||
11324 (Subtarget.isPPC64() && MemVT == MVT::i32)) &&
11325 (LD->getExtensionType() == ISD::NON_EXTLOAD ||
11326 LD->getExtensionType() == ISD::ZEXTLOAD))
11330 // FIXME: Add other cases...
11331 // - 32-bit shifts with a zext to i64
11332 // - zext after ctlz, bswap, etc.
11333 // - zext after and by a constant mask
11335 return TargetLowering::isZExtFree(Val, VT2);
11338 bool PPCTargetLowering::isFPExtFree(EVT VT) const {
11339 assert(VT.isFloatingPoint());
11343 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
11344 return isInt<16>(Imm) || isUInt<16>(Imm);
11347 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
11348 return isInt<16>(Imm) || isUInt<16>(Imm);
11351 bool PPCTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
11354 bool *Fast) const {
11355 if (DisablePPCUnaligned)
11358 // PowerPC supports unaligned memory access for simple non-vector types.
11359 // Although accessing unaligned addresses is not as efficient as accessing
11360 // aligned addresses, it is generally more efficient than manual expansion,
11361 // and generally only traps for software emulation when crossing page
11364 if (!VT.isSimple())
11367 if (VT.getSimpleVT().isVector()) {
11368 if (Subtarget.hasVSX()) {
11369 if (VT != MVT::v2f64 && VT != MVT::v2i64 &&
11370 VT != MVT::v4f32 && VT != MVT::v4i32)
11377 if (VT == MVT::ppcf128)
11386 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
11387 VT = VT.getScalarType();
11389 if (!VT.isSimple())
11392 switch (VT.getSimpleVT().SimpleTy) {
11404 PPCTargetLowering::getScratchRegisters(CallingConv::ID) const {
11405 // LR is a callee-save register, but we must treat it as clobbered by any call
11406 // site. Hence we include LR in the scratch registers, which are in turn added
11407 // as implicit-defs for stackmaps and patchpoints. The same reasoning applies
11408 // to CTR, which is used by any indirect call.
11409 static const MCPhysReg ScratchRegs[] = {
11410 PPC::X12, PPC::LR8, PPC::CTR8, 0
11413 return ScratchRegs;
11417 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
11418 EVT VT , unsigned DefinedValues) const {
11419 if (VT == MVT::v2i64)
11422 if (Subtarget.hasQPX()) {
11423 if (VT == MVT::v4f32 || VT == MVT::v4f64 || VT == MVT::v4i1)
11427 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
11430 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
11431 if (DisableILPPref || Subtarget.enableMachineScheduler())
11432 return TargetLowering::getSchedulingPreference(N);
11437 // Create a fast isel object.
11439 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
11440 const TargetLibraryInfo *LibInfo) const {
11441 return PPC::createFastISel(FuncInfo, LibInfo);