1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCMachineFunctionInfo.h"
16 #include "PPCPredicates.h"
17 #include "PPCTargetMachine.h"
18 #include "PPCPerfectShuffle.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/VectorExtras.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/PseudoSourceValue.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CallingConv.h"
29 #include "llvm/Constants.h"
30 #include "llvm/Function.h"
31 #include "llvm/Intrinsics.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/DerivedTypes.h"
40 static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
41 CCValAssign::LocInfo &LocInfo,
42 ISD::ArgFlagsTy &ArgFlags,
44 static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
46 CCValAssign::LocInfo &LocInfo,
47 ISD::ArgFlagsTy &ArgFlags,
49 static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
51 CCValAssign::LocInfo &LocInfo,
52 ISD::ArgFlagsTy &ArgFlags,
55 static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc",
56 cl::desc("enable preincrement load/store generation on PPC (experimental)"),
59 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
60 : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) {
64 // Use _setjmp/_longjmp instead of setjmp/longjmp.
65 setUseUnderscoreSetJmp(true);
66 setUseUnderscoreLongJmp(true);
68 // Set up the register classes.
69 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
70 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
71 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
73 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
74 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
75 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
77 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
79 // PowerPC has pre-inc load and store's.
80 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
81 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
82 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
83 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
84 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
85 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
86 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
87 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
88 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
89 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
91 // This is used in the ppcf128->int sequence. Note it has different semantics
92 // from FP_ROUND: that rounds to nearest, this rounds to zero.
93 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
95 // PowerPC has no SREM/UREM instructions
96 setOperationAction(ISD::SREM, MVT::i32, Expand);
97 setOperationAction(ISD::UREM, MVT::i32, Expand);
98 setOperationAction(ISD::SREM, MVT::i64, Expand);
99 setOperationAction(ISD::UREM, MVT::i64, Expand);
101 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
102 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
103 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
104 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
105 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
106 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
107 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
108 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
109 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
111 // We don't support sin/cos/sqrt/fmod/pow
112 setOperationAction(ISD::FSIN , MVT::f64, Expand);
113 setOperationAction(ISD::FCOS , MVT::f64, Expand);
114 setOperationAction(ISD::FREM , MVT::f64, Expand);
115 setOperationAction(ISD::FPOW , MVT::f64, Expand);
116 setOperationAction(ISD::FSIN , MVT::f32, Expand);
117 setOperationAction(ISD::FCOS , MVT::f32, Expand);
118 setOperationAction(ISD::FREM , MVT::f32, Expand);
119 setOperationAction(ISD::FPOW , MVT::f32, Expand);
121 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
123 // If we're enabling GP optimizations, use hardware square root
124 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
125 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
126 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
129 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
130 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
132 // PowerPC does not have BSWAP, CTPOP or CTTZ
133 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
134 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
135 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
136 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
137 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
138 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
140 // PowerPC does not have ROTR
141 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
142 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
144 // PowerPC does not have Select
145 setOperationAction(ISD::SELECT, MVT::i32, Expand);
146 setOperationAction(ISD::SELECT, MVT::i64, Expand);
147 setOperationAction(ISD::SELECT, MVT::f32, Expand);
148 setOperationAction(ISD::SELECT, MVT::f64, Expand);
150 // PowerPC wants to turn select_cc of FP into fsel when possible.
151 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
152 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
154 // PowerPC wants to optimize integer setcc a bit
155 setOperationAction(ISD::SETCC, MVT::i32, Custom);
157 // PowerPC does not have BRCOND which requires SetCC
158 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
160 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
162 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
163 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
165 // PowerPC does not have [U|S]INT_TO_FP
166 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
167 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
169 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
170 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
171 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
172 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
174 // We cannot sextinreg(i1). Expand to shifts.
175 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
177 // Support label based line numbers.
178 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
179 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
181 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
182 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
183 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
184 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
187 // We want to legalize GlobalAddress and ConstantPool nodes into the
188 // appropriate instructions to materialize the address.
189 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
190 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
191 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
192 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
193 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
194 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
195 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
196 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
198 // RET must be custom lowered, to meet ABI requirements.
199 setOperationAction(ISD::RET , MVT::Other, Custom);
202 setOperationAction(ISD::TRAP, MVT::Other, Legal);
204 // TRAMPOLINE is custom lowered.
205 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
207 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
208 setOperationAction(ISD::VASTART , MVT::Other, Custom);
210 // VAARG is custom lowered with the SVR4 ABI
211 if (TM.getSubtarget<PPCSubtarget>().isSVR4ABI())
212 setOperationAction(ISD::VAARG, MVT::Other, Custom);
214 setOperationAction(ISD::VAARG, MVT::Other, Expand);
216 // Use the default implementation.
217 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
218 setOperationAction(ISD::VAEND , MVT::Other, Expand);
219 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
220 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
221 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
222 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
224 // We want to custom lower some of our intrinsics.
225 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
227 // Comparisons that require checking two conditions.
228 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
229 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
230 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
231 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
232 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
233 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
234 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
235 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
236 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
237 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
238 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
239 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
241 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
242 // They also have instructions for converting between i64 and fp.
243 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
244 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
245 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
246 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
247 // This is just the low 32 bits of a (signed) fp->i64 conversion.
248 // We cannot do this with Promote because i64 is not a legal type.
249 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
251 // FIXME: disable this lowered code. This generates 64-bit register values,
252 // and we don't model the fact that the top part is clobbered by calls. We
253 // need to flag these together so that the value isn't live across a call.
254 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
256 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
257 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
260 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
261 // 64-bit PowerPC implementations can support i64 types directly
262 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
263 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
264 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
265 // 64-bit PowerPC wants to expand i128 shifts itself.
266 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
267 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
268 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
270 // 32-bit PowerPC wants to expand i64 shifts itself.
271 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
272 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
273 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
276 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
277 // First set operation action for all vector types to expand. Then we
278 // will selectively turn on ones that can be effectively codegen'd.
279 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
280 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
281 MVT VT = (MVT::SimpleValueType)i;
283 // add/sub are legal for all supported vector VT's.
284 setOperationAction(ISD::ADD , VT, Legal);
285 setOperationAction(ISD::SUB , VT, Legal);
287 // We promote all shuffles to v16i8.
288 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
289 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
291 // We promote all non-typed operations to v4i32.
292 setOperationAction(ISD::AND , VT, Promote);
293 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
294 setOperationAction(ISD::OR , VT, Promote);
295 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
296 setOperationAction(ISD::XOR , VT, Promote);
297 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
298 setOperationAction(ISD::LOAD , VT, Promote);
299 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
300 setOperationAction(ISD::SELECT, VT, Promote);
301 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
302 setOperationAction(ISD::STORE, VT, Promote);
303 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
305 // No other operations are legal.
306 setOperationAction(ISD::MUL , VT, Expand);
307 setOperationAction(ISD::SDIV, VT, Expand);
308 setOperationAction(ISD::SREM, VT, Expand);
309 setOperationAction(ISD::UDIV, VT, Expand);
310 setOperationAction(ISD::UREM, VT, Expand);
311 setOperationAction(ISD::FDIV, VT, Expand);
312 setOperationAction(ISD::FNEG, VT, Expand);
313 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
314 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
315 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
316 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
317 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
318 setOperationAction(ISD::UDIVREM, VT, Expand);
319 setOperationAction(ISD::SDIVREM, VT, Expand);
320 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
321 setOperationAction(ISD::FPOW, VT, Expand);
322 setOperationAction(ISD::CTPOP, VT, Expand);
323 setOperationAction(ISD::CTLZ, VT, Expand);
324 setOperationAction(ISD::CTTZ, VT, Expand);
327 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
328 // with merges, splats, etc.
329 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
331 setOperationAction(ISD::AND , MVT::v4i32, Legal);
332 setOperationAction(ISD::OR , MVT::v4i32, Legal);
333 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
334 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
335 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
336 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
338 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
339 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
340 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
341 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
343 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
344 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
345 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
346 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
348 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
349 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
351 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
352 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
353 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
354 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
357 setShiftAmountType(MVT::i32);
358 setBooleanContents(ZeroOrOneBooleanContent);
360 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
361 setStackPointerRegisterToSaveRestore(PPC::X1);
362 setExceptionPointerRegister(PPC::X3);
363 setExceptionSelectorRegister(PPC::X4);
365 setStackPointerRegisterToSaveRestore(PPC::R1);
366 setExceptionPointerRegister(PPC::R3);
367 setExceptionSelectorRegister(PPC::R4);
370 // We have target-specific dag combine patterns for the following nodes:
371 setTargetDAGCombine(ISD::SINT_TO_FP);
372 setTargetDAGCombine(ISD::STORE);
373 setTargetDAGCombine(ISD::BR_CC);
374 setTargetDAGCombine(ISD::BSWAP);
376 // Darwin long double math library functions have $LDBL128 appended.
377 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) {
378 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
379 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
380 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
381 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
382 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
383 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
384 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
385 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
386 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
387 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
390 computeRegisterProperties();
393 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
394 /// function arguments in the caller parameter area.
395 unsigned PPCTargetLowering::getByValTypeAlignment(const Type *Ty) const {
396 TargetMachine &TM = getTargetMachine();
397 // Darwin passes everything on 4 byte boundary.
398 if (TM.getSubtarget<PPCSubtarget>().isDarwin())
404 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
407 case PPCISD::FSEL: return "PPCISD::FSEL";
408 case PPCISD::FCFID: return "PPCISD::FCFID";
409 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
410 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
411 case PPCISD::STFIWX: return "PPCISD::STFIWX";
412 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
413 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
414 case PPCISD::VPERM: return "PPCISD::VPERM";
415 case PPCISD::Hi: return "PPCISD::Hi";
416 case PPCISD::Lo: return "PPCISD::Lo";
417 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
418 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
419 case PPCISD::SRL: return "PPCISD::SRL";
420 case PPCISD::SRA: return "PPCISD::SRA";
421 case PPCISD::SHL: return "PPCISD::SHL";
422 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
423 case PPCISD::STD_32: return "PPCISD::STD_32";
424 case PPCISD::CALL_SVR4: return "PPCISD::CALL_SVR4";
425 case PPCISD::CALL_Darwin: return "PPCISD::CALL_Darwin";
426 case PPCISD::MTCTR: return "PPCISD::MTCTR";
427 case PPCISD::BCTRL_Darwin: return "PPCISD::BCTRL_Darwin";
428 case PPCISD::BCTRL_SVR4: return "PPCISD::BCTRL_SVR4";
429 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
430 case PPCISD::MFCR: return "PPCISD::MFCR";
431 case PPCISD::VCMP: return "PPCISD::VCMP";
432 case PPCISD::VCMPo: return "PPCISD::VCMPo";
433 case PPCISD::LBRX: return "PPCISD::LBRX";
434 case PPCISD::STBRX: return "PPCISD::STBRX";
435 case PPCISD::LARX: return "PPCISD::LARX";
436 case PPCISD::STCX: return "PPCISD::STCX";
437 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
438 case PPCISD::MFFS: return "PPCISD::MFFS";
439 case PPCISD::MTFSB0: return "PPCISD::MTFSB0";
440 case PPCISD::MTFSB1: return "PPCISD::MTFSB1";
441 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
442 case PPCISD::MTFSF: return "PPCISD::MTFSF";
443 case PPCISD::TAILCALL: return "PPCISD::TAILCALL";
444 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
448 MVT PPCTargetLowering::getSetCCResultType(MVT VT) const {
452 /// getFunctionAlignment - Return the Log2 alignment of this function.
453 unsigned PPCTargetLowering::getFunctionAlignment(const Function *F) const {
454 if (getTargetMachine().getSubtarget<PPCSubtarget>().isDarwin())
455 return F->hasFnAttr(Attribute::OptimizeForSize) ? 2 : 4;
460 //===----------------------------------------------------------------------===//
461 // Node matching predicates, for use by the tblgen matching code.
462 //===----------------------------------------------------------------------===//
464 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
465 static bool isFloatingPointZero(SDValue Op) {
466 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
467 return CFP->getValueAPF().isZero();
468 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
469 // Maybe this has already been legalized into the constant pool?
470 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
471 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
472 return CFP->getValueAPF().isZero();
477 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
478 /// true if Op is undef or if it matches the specified value.
479 static bool isConstantOrUndef(int Op, int Val) {
480 return Op < 0 || Op == Val;
483 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
484 /// VPKUHUM instruction.
485 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
487 for (unsigned i = 0; i != 16; ++i)
488 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
491 for (unsigned i = 0; i != 8; ++i)
492 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) ||
493 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1))
499 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
500 /// VPKUWUM instruction.
501 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
503 for (unsigned i = 0; i != 16; i += 2)
504 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
505 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
508 for (unsigned i = 0; i != 8; i += 2)
509 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
510 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) ||
511 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) ||
512 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3))
518 /// isVMerge - Common function, used to match vmrg* shuffles.
520 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
521 unsigned LHSStart, unsigned RHSStart) {
522 assert(N->getValueType(0) == MVT::v16i8 &&
523 "PPC only supports shuffles by bytes!");
524 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
525 "Unsupported merge size!");
527 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
528 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
529 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
530 LHSStart+j+i*UnitSize) ||
531 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
532 RHSStart+j+i*UnitSize))
538 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
539 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
540 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
543 return isVMerge(N, UnitSize, 8, 24);
544 return isVMerge(N, UnitSize, 8, 8);
547 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
548 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
549 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
552 return isVMerge(N, UnitSize, 0, 16);
553 return isVMerge(N, UnitSize, 0, 0);
557 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
558 /// amount, otherwise return -1.
559 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
560 assert(N->getValueType(0) == MVT::v16i8 &&
561 "PPC only supports shuffles by bytes!");
563 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
565 // Find the first non-undef value in the shuffle mask.
567 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
570 if (i == 16) return -1; // all undef.
572 // Otherwise, check to see if the rest of the elements are consecutively
573 // numbered from this value.
574 unsigned ShiftAmt = SVOp->getMaskElt(i);
575 if (ShiftAmt < i) return -1;
579 // Check the rest of the elements to see if they are consecutive.
580 for (++i; i != 16; ++i)
581 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
584 // Check the rest of the elements to see if they are consecutive.
585 for (++i; i != 16; ++i)
586 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
592 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
593 /// specifies a splat of a single element that is suitable for input to
594 /// VSPLTB/VSPLTH/VSPLTW.
595 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
596 assert(N->getValueType(0) == MVT::v16i8 &&
597 (EltSize == 1 || EltSize == 2 || EltSize == 4));
599 // This is a splat operation if each element of the permute is the same, and
600 // if the value doesn't reference the second vector.
601 unsigned ElementBase = N->getMaskElt(0);
603 // FIXME: Handle UNDEF elements too!
604 if (ElementBase >= 16)
607 // Check that the indices are consecutive, in the case of a multi-byte element
608 // splatted with a v16i8 mask.
609 for (unsigned i = 1; i != EltSize; ++i)
610 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
613 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
614 if (N->getMaskElt(i) < 0) continue;
615 for (unsigned j = 0; j != EltSize; ++j)
616 if (N->getMaskElt(i+j) != N->getMaskElt(j))
622 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
624 bool PPC::isAllNegativeZeroVector(SDNode *N) {
625 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
627 APInt APVal, APUndef;
631 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32))
632 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
633 return CFP->getValueAPF().isNegZero();
638 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
639 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
640 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
641 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
642 assert(isSplatShuffleMask(SVOp, EltSize));
643 return SVOp->getMaskElt(0) / EltSize;
646 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
647 /// by using a vspltis[bhw] instruction of the specified element size, return
648 /// the constant being splatted. The ByteSize field indicates the number of
649 /// bytes of each element [124] -> [bhw].
650 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
653 // If ByteSize of the splat is bigger than the element size of the
654 // build_vector, then we have a case where we are checking for a splat where
655 // multiple elements of the buildvector are folded together into a single
656 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
657 unsigned EltSize = 16/N->getNumOperands();
658 if (EltSize < ByteSize) {
659 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
660 SDValue UniquedVals[4];
661 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
663 // See if all of the elements in the buildvector agree across.
664 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
665 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
666 // If the element isn't a constant, bail fully out.
667 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
670 if (UniquedVals[i&(Multiple-1)].getNode() == 0)
671 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
672 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
673 return SDValue(); // no match.
676 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
677 // either constant or undef values that are identical for each chunk. See
678 // if these chunks can form into a larger vspltis*.
680 // Check to see if all of the leading entries are either 0 or -1. If
681 // neither, then this won't fit into the immediate field.
682 bool LeadingZero = true;
683 bool LeadingOnes = true;
684 for (unsigned i = 0; i != Multiple-1; ++i) {
685 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs.
687 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
688 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
690 // Finally, check the least significant entry.
692 if (UniquedVals[Multiple-1].getNode() == 0)
693 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
694 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
696 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
699 if (UniquedVals[Multiple-1].getNode() == 0)
700 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
701 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
702 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
703 return DAG.getTargetConstant(Val, MVT::i32);
709 // Check to see if this buildvec has a single non-undef value in its elements.
710 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
711 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
712 if (OpVal.getNode() == 0)
713 OpVal = N->getOperand(i);
714 else if (OpVal != N->getOperand(i))
718 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def.
720 unsigned ValSizeInBytes = EltSize;
722 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
723 Value = CN->getZExtValue();
724 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
725 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
726 Value = FloatToBits(CN->getValueAPF().convertToFloat());
729 // If the splat value is larger than the element value, then we can never do
730 // this splat. The only case that we could fit the replicated bits into our
731 // immediate field for would be zero, and we prefer to use vxor for it.
732 if (ValSizeInBytes < ByteSize) return SDValue();
734 // If the element value is larger than the splat value, cut it in half and
735 // check to see if the two halves are equal. Continue doing this until we
736 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
737 while (ValSizeInBytes > ByteSize) {
738 ValSizeInBytes >>= 1;
740 // If the top half equals the bottom half, we're still ok.
741 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
742 (Value & ((1 << (8*ValSizeInBytes))-1)))
746 // Properly sign extend the value.
747 int ShAmt = (4-ByteSize)*8;
748 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
750 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
751 if (MaskVal == 0) return SDValue();
753 // Finally, if this value fits in a 5 bit sext field, return it
754 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
755 return DAG.getTargetConstant(MaskVal, MVT::i32);
759 //===----------------------------------------------------------------------===//
760 // Addressing Mode Selection
761 //===----------------------------------------------------------------------===//
763 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
764 /// or 64-bit immediate, and if the value can be accurately represented as a
765 /// sign extension from a 16-bit value. If so, this returns true and the
767 static bool isIntS16Immediate(SDNode *N, short &Imm) {
768 if (N->getOpcode() != ISD::Constant)
771 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
772 if (N->getValueType(0) == MVT::i32)
773 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
775 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
777 static bool isIntS16Immediate(SDValue Op, short &Imm) {
778 return isIntS16Immediate(Op.getNode(), Imm);
782 /// SelectAddressRegReg - Given the specified addressed, check to see if it
783 /// can be represented as an indexed [r+r] operation. Returns false if it
784 /// can be more efficiently represented with [r+imm].
785 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
787 SelectionDAG &DAG) const {
789 if (N.getOpcode() == ISD::ADD) {
790 if (isIntS16Immediate(N.getOperand(1), imm))
792 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
795 Base = N.getOperand(0);
796 Index = N.getOperand(1);
798 } else if (N.getOpcode() == ISD::OR) {
799 if (isIntS16Immediate(N.getOperand(1), imm))
800 return false; // r+i can fold it if we can.
802 // If this is an or of disjoint bitfields, we can codegen this as an add
803 // (for better address arithmetic) if the LHS and RHS of the OR are provably
805 APInt LHSKnownZero, LHSKnownOne;
806 APInt RHSKnownZero, RHSKnownOne;
807 DAG.ComputeMaskedBits(N.getOperand(0),
808 APInt::getAllOnesValue(N.getOperand(0)
809 .getValueSizeInBits()),
810 LHSKnownZero, LHSKnownOne);
812 if (LHSKnownZero.getBoolValue()) {
813 DAG.ComputeMaskedBits(N.getOperand(1),
814 APInt::getAllOnesValue(N.getOperand(1)
815 .getValueSizeInBits()),
816 RHSKnownZero, RHSKnownOne);
817 // If all of the bits are known zero on the LHS or RHS, the add won't
819 if (~(LHSKnownZero | RHSKnownZero) == 0) {
820 Base = N.getOperand(0);
821 Index = N.getOperand(1);
830 /// Returns true if the address N can be represented by a base register plus
831 /// a signed 16-bit displacement [r+imm], and if it is not better
832 /// represented as reg+reg.
833 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
835 SelectionDAG &DAG) const {
836 // FIXME dl should come from parent load or store, not from address
837 DebugLoc dl = N.getDebugLoc();
838 // If this can be more profitably realized as r+r, fail.
839 if (SelectAddressRegReg(N, Disp, Base, DAG))
842 if (N.getOpcode() == ISD::ADD) {
844 if (isIntS16Immediate(N.getOperand(1), imm)) {
845 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
846 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
847 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
849 Base = N.getOperand(0);
851 return true; // [r+i]
852 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
853 // Match LOAD (ADD (X, Lo(G))).
854 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
855 && "Cannot handle constant offsets yet!");
856 Disp = N.getOperand(1).getOperand(0); // The global address.
857 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
858 Disp.getOpcode() == ISD::TargetConstantPool ||
859 Disp.getOpcode() == ISD::TargetJumpTable);
860 Base = N.getOperand(0);
861 return true; // [&g+r]
863 } else if (N.getOpcode() == ISD::OR) {
865 if (isIntS16Immediate(N.getOperand(1), imm)) {
866 // If this is an or of disjoint bitfields, we can codegen this as an add
867 // (for better address arithmetic) if the LHS and RHS of the OR are
868 // provably disjoint.
869 APInt LHSKnownZero, LHSKnownOne;
870 DAG.ComputeMaskedBits(N.getOperand(0),
871 APInt::getAllOnesValue(N.getOperand(0)
872 .getValueSizeInBits()),
873 LHSKnownZero, LHSKnownOne);
875 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
876 // If all of the bits are known zero on the LHS or RHS, the add won't
878 Base = N.getOperand(0);
879 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
883 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
884 // Loading from a constant address.
886 // If this address fits entirely in a 16-bit sext immediate field, codegen
889 if (isIntS16Immediate(CN, Imm)) {
890 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
891 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
895 // Handle 32-bit sext immediates with LIS + addr mode.
896 if (CN->getValueType(0) == MVT::i32 ||
897 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
898 int Addr = (int)CN->getZExtValue();
900 // Otherwise, break this down into an LIS + disp.
901 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
903 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
904 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
905 Base = SDValue(DAG.getTargetNode(Opc, dl, CN->getValueType(0), Base), 0);
910 Disp = DAG.getTargetConstant(0, getPointerTy());
911 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
912 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
915 return true; // [r+0]
918 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
919 /// represented as an indexed [r+r] operation.
920 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
922 SelectionDAG &DAG) const {
923 // Check to see if we can easily represent this as an [r+r] address. This
924 // will fail if it thinks that the address is more profitably represented as
925 // reg+imm, e.g. where imm = 0.
926 if (SelectAddressRegReg(N, Base, Index, DAG))
929 // If the operand is an addition, always emit this as [r+r], since this is
930 // better (for code size, and execution, as the memop does the add for free)
931 // than emitting an explicit add.
932 if (N.getOpcode() == ISD::ADD) {
933 Base = N.getOperand(0);
934 Index = N.getOperand(1);
938 // Otherwise, do it the hard way, using R0 as the base register.
939 Base = DAG.getRegister(PPC::R0, N.getValueType());
944 /// SelectAddressRegImmShift - Returns true if the address N can be
945 /// represented by a base register plus a signed 14-bit displacement
946 /// [r+imm*4]. Suitable for use by STD and friends.
947 bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp,
949 SelectionDAG &DAG) const {
950 // FIXME dl should come from the parent load or store, not the address
951 DebugLoc dl = N.getDebugLoc();
952 // If this can be more profitably realized as r+r, fail.
953 if (SelectAddressRegReg(N, Disp, Base, DAG))
956 if (N.getOpcode() == ISD::ADD) {
958 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
959 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
960 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
961 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
963 Base = N.getOperand(0);
965 return true; // [r+i]
966 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
967 // Match LOAD (ADD (X, Lo(G))).
968 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
969 && "Cannot handle constant offsets yet!");
970 Disp = N.getOperand(1).getOperand(0); // The global address.
971 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
972 Disp.getOpcode() == ISD::TargetConstantPool ||
973 Disp.getOpcode() == ISD::TargetJumpTable);
974 Base = N.getOperand(0);
975 return true; // [&g+r]
977 } else if (N.getOpcode() == ISD::OR) {
979 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
980 // If this is an or of disjoint bitfields, we can codegen this as an add
981 // (for better address arithmetic) if the LHS and RHS of the OR are
982 // provably disjoint.
983 APInt LHSKnownZero, LHSKnownOne;
984 DAG.ComputeMaskedBits(N.getOperand(0),
985 APInt::getAllOnesValue(N.getOperand(0)
986 .getValueSizeInBits()),
987 LHSKnownZero, LHSKnownOne);
988 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
989 // If all of the bits are known zero on the LHS or RHS, the add won't
991 Base = N.getOperand(0);
992 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
996 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
997 // Loading from a constant address. Verify low two bits are clear.
998 if ((CN->getZExtValue() & 3) == 0) {
999 // If this address fits entirely in a 14-bit sext immediate field, codegen
1002 if (isIntS16Immediate(CN, Imm)) {
1003 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
1004 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
1008 // Fold the low-part of 32-bit absolute addresses into addr mode.
1009 if (CN->getValueType(0) == MVT::i32 ||
1010 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
1011 int Addr = (int)CN->getZExtValue();
1013 // Otherwise, break this down into an LIS + disp.
1014 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
1015 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
1016 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1017 Base = SDValue(DAG.getTargetNode(Opc, dl, CN->getValueType(0), Base),0);
1023 Disp = DAG.getTargetConstant(0, getPointerTy());
1024 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
1025 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1028 return true; // [r+0]
1032 /// getPreIndexedAddressParts - returns true by value, base pointer and
1033 /// offset pointer and addressing mode by reference if the node's address
1034 /// can be legally represented as pre-indexed load / store address.
1035 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1037 ISD::MemIndexedMode &AM,
1038 SelectionDAG &DAG) const {
1039 // Disabled by default for now.
1040 if (!EnablePPCPreinc) return false;
1044 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1045 Ptr = LD->getBasePtr();
1046 VT = LD->getMemoryVT();
1048 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1050 Ptr = ST->getBasePtr();
1051 VT = ST->getMemoryVT();
1055 // PowerPC doesn't have preinc load/store instructions for vectors.
1059 // TODO: Check reg+reg first.
1061 // LDU/STU use reg+imm*4, others use reg+imm.
1062 if (VT != MVT::i64) {
1064 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
1068 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
1072 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1073 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1074 // sext i32 to i64 when addr mode is r+i.
1075 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1076 LD->getExtensionType() == ISD::SEXTLOAD &&
1077 isa<ConstantSDNode>(Offset))
1085 //===----------------------------------------------------------------------===//
1086 // LowerOperation implementation
1087 //===----------------------------------------------------------------------===//
1089 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1090 SelectionDAG &DAG) {
1091 MVT PtrVT = Op.getValueType();
1092 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1093 Constant *C = CP->getConstVal();
1094 SDValue CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
1095 SDValue Zero = DAG.getConstant(0, PtrVT);
1096 // FIXME there isn't really any debug info here
1097 DebugLoc dl = Op.getDebugLoc();
1099 const TargetMachine &TM = DAG.getTarget();
1101 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, CPI, Zero);
1102 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, CPI, Zero);
1104 // If this is a non-darwin platform, we don't support non-static relo models
1106 if (TM.getRelocationModel() == Reloc::Static ||
1107 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1108 // Generate non-pic code that has direct accesses to the constant pool.
1109 // The address of the global is just (hi(&g)+lo(&g)).
1110 return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1113 if (TM.getRelocationModel() == Reloc::PIC_) {
1114 // With PIC, the first instruction is actually "GR+hi(&G)".
1115 Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
1116 DAG.getNode(PPCISD::GlobalBaseReg,
1117 DebugLoc::getUnknownLoc(), PtrVT), Hi);
1120 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1124 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
1125 MVT PtrVT = Op.getValueType();
1126 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1127 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1128 SDValue Zero = DAG.getConstant(0, PtrVT);
1129 // FIXME there isn't really any debug loc here
1130 DebugLoc dl = Op.getDebugLoc();
1132 const TargetMachine &TM = DAG.getTarget();
1134 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, JTI, Zero);
1135 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, JTI, Zero);
1137 // If this is a non-darwin platform, we don't support non-static relo models
1139 if (TM.getRelocationModel() == Reloc::Static ||
1140 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1141 // Generate non-pic code that has direct accesses to the constant pool.
1142 // The address of the global is just (hi(&g)+lo(&g)).
1143 return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1146 if (TM.getRelocationModel() == Reloc::PIC_) {
1147 // With PIC, the first instruction is actually "GR+hi(&G)".
1148 Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
1149 DAG.getNode(PPCISD::GlobalBaseReg,
1150 DebugLoc::getUnknownLoc(), PtrVT), Hi);
1153 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1157 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1158 SelectionDAG &DAG) {
1159 llvm_unreachable("TLS not implemented for PPC.");
1160 return SDValue(); // Not reached
1163 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1164 SelectionDAG &DAG) {
1165 MVT PtrVT = Op.getValueType();
1166 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1167 GlobalValue *GV = GSDN->getGlobal();
1168 SDValue GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
1169 SDValue Zero = DAG.getConstant(0, PtrVT);
1170 // FIXME there isn't really any debug info here
1171 DebugLoc dl = GSDN->getDebugLoc();
1173 const TargetMachine &TM = DAG.getTarget();
1175 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, GA, Zero);
1176 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, GA, Zero);
1178 // If this is a non-darwin platform, we don't support non-static relo models
1180 if (TM.getRelocationModel() == Reloc::Static ||
1181 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1182 // Generate non-pic code that has direct accesses to globals.
1183 // The address of the global is just (hi(&g)+lo(&g)).
1184 return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1187 if (TM.getRelocationModel() == Reloc::PIC_) {
1188 // With PIC, the first instruction is actually "GR+hi(&G)".
1189 Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
1190 DAG.getNode(PPCISD::GlobalBaseReg,
1191 DebugLoc::getUnknownLoc(), PtrVT), Hi);
1194 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1196 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV))
1199 // If the global is weak or external, we have to go through the lazy
1201 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Lo, NULL, 0);
1204 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
1205 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1206 DebugLoc dl = Op.getDebugLoc();
1208 // If we're comparing for equality to zero, expose the fact that this is
1209 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1210 // fold the new nodes.
1211 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1212 if (C->isNullValue() && CC == ISD::SETEQ) {
1213 MVT VT = Op.getOperand(0).getValueType();
1214 SDValue Zext = Op.getOperand(0);
1215 if (VT.bitsLT(MVT::i32)) {
1217 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1219 unsigned Log2b = Log2_32(VT.getSizeInBits());
1220 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1221 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1222 DAG.getConstant(Log2b, MVT::i32));
1223 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1225 // Leave comparisons against 0 and -1 alone for now, since they're usually
1226 // optimized. FIXME: revisit this when we can custom lower all setcc
1228 if (C->isAllOnesValue() || C->isNullValue())
1232 // If we have an integer seteq/setne, turn it into a compare against zero
1233 // by xor'ing the rhs with the lhs, which is faster than setting a
1234 // condition register, reading it back out, and masking the correct bit. The
1235 // normal approach here uses sub to do this instead of xor. Using xor exposes
1236 // the result to other bit-twiddling opportunities.
1237 MVT LHSVT = Op.getOperand(0).getValueType();
1238 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1239 MVT VT = Op.getValueType();
1240 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1242 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1247 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1248 int VarArgsFrameIndex,
1249 int VarArgsStackOffset,
1250 unsigned VarArgsNumGPR,
1251 unsigned VarArgsNumFPR,
1252 const PPCSubtarget &Subtarget) {
1254 llvm_unreachable("VAARG not yet implemented for the SVR4 ABI!");
1255 return SDValue(); // Not reached
1258 SDValue PPCTargetLowering::LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
1259 SDValue Chain = Op.getOperand(0);
1260 SDValue Trmp = Op.getOperand(1); // trampoline
1261 SDValue FPtr = Op.getOperand(2); // nested function
1262 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1263 DebugLoc dl = Op.getDebugLoc();
1265 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1266 bool isPPC64 = (PtrVT == MVT::i64);
1267 const Type *IntPtrTy =
1268 DAG.getTargetLoweringInfo().getTargetData()->getIntPtrType();
1270 TargetLowering::ArgListTy Args;
1271 TargetLowering::ArgListEntry Entry;
1273 Entry.Ty = IntPtrTy;
1274 Entry.Node = Trmp; Args.push_back(Entry);
1276 // TrampSize == (isPPC64 ? 48 : 40);
1277 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1278 isPPC64 ? MVT::i64 : MVT::i32);
1279 Args.push_back(Entry);
1281 Entry.Node = FPtr; Args.push_back(Entry);
1282 Entry.Node = Nest; Args.push_back(Entry);
1284 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1285 std::pair<SDValue, SDValue> CallResult =
1286 LowerCallTo(Chain, Op.getValueType().getTypeForMVT(*DAG.getContext()),
1287 false, false, false, false, 0, CallingConv::C, false,
1288 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1292 { CallResult.first, CallResult.second };
1294 return DAG.getMergeValues(Ops, 2, dl);
1297 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1298 int VarArgsFrameIndex,
1299 int VarArgsStackOffset,
1300 unsigned VarArgsNumGPR,
1301 unsigned VarArgsNumFPR,
1302 const PPCSubtarget &Subtarget) {
1303 DebugLoc dl = Op.getDebugLoc();
1305 if (Subtarget.isDarwinABI()) {
1306 // vastart just stores the address of the VarArgsFrameIndex slot into the
1307 // memory location argument.
1308 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1309 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1310 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1311 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
1314 // For the SVR4 ABI we follow the layout of the va_list struct.
1315 // We suppose the given va_list is already allocated.
1318 // char gpr; /* index into the array of 8 GPRs
1319 // * stored in the register save area
1320 // * gpr=0 corresponds to r3,
1321 // * gpr=1 to r4, etc.
1323 // char fpr; /* index into the array of 8 FPRs
1324 // * stored in the register save area
1325 // * fpr=0 corresponds to f1,
1326 // * fpr=1 to f2, etc.
1328 // char *overflow_arg_area;
1329 // /* location on stack that holds
1330 // * the next overflow argument
1332 // char *reg_save_area;
1333 // /* where r3:r10 and f1:f8 (if saved)
1339 SDValue ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i32);
1340 SDValue ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i32);
1343 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1345 SDValue StackOffsetFI = DAG.getFrameIndex(VarArgsStackOffset, PtrVT);
1346 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1348 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
1349 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1351 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
1352 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1354 uint64_t FPROffset = 1;
1355 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1357 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1359 // Store first byte : number of int regs
1360 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
1361 Op.getOperand(1), SV, 0, MVT::i8);
1362 uint64_t nextOffset = FPROffset;
1363 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
1366 // Store second byte : number of float regs
1367 SDValue secondStore =
1368 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr, SV, nextOffset, MVT::i8);
1369 nextOffset += StackOffset;
1370 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
1372 // Store second word : arguments given on stack
1373 SDValue thirdStore =
1374 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr, SV, nextOffset);
1375 nextOffset += FrameOffset;
1376 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
1378 // Store third word : arguments given in registers
1379 return DAG.getStore(thirdStore, dl, FR, nextPtr, SV, nextOffset);
1383 #include "PPCGenCallingConv.inc"
1385 static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
1386 CCValAssign::LocInfo &LocInfo,
1387 ISD::ArgFlagsTy &ArgFlags,
1392 static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
1394 CCValAssign::LocInfo &LocInfo,
1395 ISD::ArgFlagsTy &ArgFlags,
1397 static const unsigned ArgRegs[] = {
1398 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1399 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1401 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1403 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1405 // Skip one register if the first unallocated register has an even register
1406 // number and there are still argument registers available which have not been
1407 // allocated yet. RegNum is actually an index into ArgRegs, which means we
1408 // need to skip a register if RegNum is odd.
1409 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
1410 State.AllocateReg(ArgRegs[RegNum]);
1413 // Always return false here, as this function only makes sure that the first
1414 // unallocated register has an odd register number and does not actually
1415 // allocate a register for the current argument.
1419 static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
1421 CCValAssign::LocInfo &LocInfo,
1422 ISD::ArgFlagsTy &ArgFlags,
1424 static const unsigned ArgRegs[] = {
1425 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1429 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1431 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1433 // If there is only one Floating-point register left we need to put both f64
1434 // values of a split ppc_fp128 value on the stack.
1435 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
1436 State.AllocateReg(ArgRegs[RegNum]);
1439 // Always return false here, as this function only makes sure that the two f64
1440 // values a ppc_fp128 value is split into are both passed in registers or both
1441 // passed on the stack and does not actually allocate a register for the
1442 // current argument.
1446 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1447 /// depending on which subtarget is selected.
1448 static const unsigned *GetFPR(const PPCSubtarget &Subtarget) {
1449 if (Subtarget.isDarwinABI()) {
1450 static const unsigned FPR[] = {
1451 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1452 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1458 static const unsigned FPR[] = {
1459 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1465 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
1467 static unsigned CalculateStackSlotSize(SDValue Arg, ISD::ArgFlagsTy Flags,
1468 unsigned PtrByteSize) {
1469 MVT ArgVT = Arg.getValueType();
1470 unsigned ArgSize = ArgVT.getSizeInBits()/8;
1471 if (Flags.isByVal())
1472 ArgSize = Flags.getByValSize();
1473 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1479 PPCTargetLowering::LowerFORMAL_ARGUMENTS_SVR4(SDValue Op,
1481 int &VarArgsFrameIndex,
1482 int &VarArgsStackOffset,
1483 unsigned &VarArgsNumGPR,
1484 unsigned &VarArgsNumFPR,
1485 const PPCSubtarget &Subtarget) {
1486 // SVR4 ABI Stack Frame Layout:
1487 // +-----------------------------------+
1488 // +--> | Back chain |
1489 // | +-----------------------------------+
1490 // | | Floating-point register save area |
1491 // | +-----------------------------------+
1492 // | | General register save area |
1493 // | +-----------------------------------+
1494 // | | CR save word |
1495 // | +-----------------------------------+
1496 // | | VRSAVE save word |
1497 // | +-----------------------------------+
1498 // | | Alignment padding |
1499 // | +-----------------------------------+
1500 // | | Vector register save area |
1501 // | +-----------------------------------+
1502 // | | Local variable space |
1503 // | +-----------------------------------+
1504 // | | Parameter list area |
1505 // | +-----------------------------------+
1506 // | | LR save word |
1507 // | +-----------------------------------+
1508 // SP--> +--- | Back chain |
1509 // +-----------------------------------+
1512 // System V Application Binary Interface PowerPC Processor Supplement
1513 // AltiVec Technology Programming Interface Manual
1515 MachineFunction &MF = DAG.getMachineFunction();
1516 MachineFrameInfo *MFI = MF.getFrameInfo();
1517 SmallVector<SDValue, 8> ArgValues;
1518 SDValue Root = Op.getOperand(0);
1519 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
1520 DebugLoc dl = Op.getDebugLoc();
1522 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1523 // Potential tail calls could cause overwriting of argument stack slots.
1524 unsigned CC = MF.getFunction()->getCallingConv();
1525 bool isImmutable = !(PerformTailCallOpt && (CC==CallingConv::Fast));
1526 unsigned PtrByteSize = 4;
1528 // Assign locations to all of the incoming arguments.
1529 SmallVector<CCValAssign, 16> ArgLocs;
1530 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, DAG.getContext());
1532 // Reserve space for the linkage area on the stack.
1533 CCInfo.AllocateStack(PPCFrameInfo::getLinkageSize(false, false), PtrByteSize);
1535 CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_PPC_SVR4);
1537 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1538 CCValAssign &VA = ArgLocs[i];
1540 // Arguments stored in registers.
1541 if (VA.isRegLoc()) {
1542 TargetRegisterClass *RC;
1543 MVT ValVT = VA.getValVT();
1545 switch (ValVT.getSimpleVT()) {
1547 llvm_unreachable("ValVT not supported by FORMAL_ARGUMENTS Lowering");
1549 RC = PPC::GPRCRegisterClass;
1552 RC = PPC::F4RCRegisterClass;
1555 RC = PPC::F8RCRegisterClass;
1561 RC = PPC::VRRCRegisterClass;
1565 // Transform the arguments stored in physical registers into virtual ones.
1566 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1567 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, ValVT);
1569 ArgValues.push_back(ArgValue);
1571 // Argument stored in memory.
1572 assert(VA.isMemLoc());
1574 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
1575 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
1578 // Create load nodes to retrieve arguments from the stack.
1579 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1580 ArgValues.push_back(DAG.getLoad(VA.getValVT(), dl, Root, FIN, NULL, 0));
1584 // Assign locations to all of the incoming aggregate by value arguments.
1585 // Aggregates passed by value are stored in the local variable space of the
1586 // caller's stack frame, right above the parameter list area.
1587 SmallVector<CCValAssign, 16> ByValArgLocs;
1588 CCState CCByValInfo(CC, isVarArg, getTargetMachine(),
1589 ByValArgLocs, DAG.getContext());
1591 // Reserve stack space for the allocations in CCInfo.
1592 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
1594 CCByValInfo.AnalyzeFormalArguments(Op.getNode(), CC_PPC_SVR4_ByVal);
1596 // Area that is at least reserved in the caller of this function.
1597 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
1599 // Set the size that is at least reserved in caller of this function. Tail
1600 // call optimized function's reserved stack space needs to be aligned so that
1601 // taking the difference between two stack areas will result in an aligned
1603 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1606 std::max(MinReservedArea,
1607 PPCFrameInfo::getMinCallFrameSize(false, false));
1609 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
1610 getStackAlignment();
1611 unsigned AlignMask = TargetAlign-1;
1612 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
1614 FI->setMinReservedArea(MinReservedArea);
1616 SmallVector<SDValue, 8> MemOps;
1618 // If the function takes variable number of arguments, make a frame index for
1619 // the start of the first vararg value... for expansion of llvm.va_start.
1621 static const unsigned GPArgRegs[] = {
1622 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1623 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1625 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
1627 static const unsigned FPArgRegs[] = {
1628 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1631 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
1633 VarArgsNumGPR = CCInfo.getFirstUnallocated(GPArgRegs, NumGPArgRegs);
1634 VarArgsNumFPR = CCInfo.getFirstUnallocated(FPArgRegs, NumFPArgRegs);
1636 // Make room for NumGPArgRegs and NumFPArgRegs.
1637 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
1638 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8;
1640 VarArgsStackOffset = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
1641 CCInfo.getNextStackOffset());
1643 VarArgsFrameIndex = MFI->CreateStackObject(Depth, 8);
1644 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1646 // The fixed integer arguments of a variadic function are
1647 // stored to the VarArgsFrameIndex on the stack.
1648 unsigned GPRIndex = 0;
1649 for (; GPRIndex != VarArgsNumGPR; ++GPRIndex) {
1650 SDValue Val = DAG.getRegister(GPArgRegs[GPRIndex], PtrVT);
1651 SDValue Store = DAG.getStore(Root, dl, Val, FIN, NULL, 0);
1652 MemOps.push_back(Store);
1653 // Increment the address by four for the next argument to store
1654 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
1655 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1658 // If this function is vararg, store any remaining integer argument regs
1659 // to their spots on the stack so that they may be loaded by deferencing the
1660 // result of va_next.
1661 for (; GPRIndex != NumGPArgRegs; ++GPRIndex) {
1662 unsigned VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
1664 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, PtrVT);
1665 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
1666 MemOps.push_back(Store);
1667 // Increment the address by four for the next argument to store
1668 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
1669 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1672 // FIXME SVR4: We only need to save FP argument registers if CR bit 6 is
1675 // The double arguments are stored to the VarArgsFrameIndex
1677 unsigned FPRIndex = 0;
1678 for (FPRIndex = 0; FPRIndex != VarArgsNumFPR; ++FPRIndex) {
1679 SDValue Val = DAG.getRegister(FPArgRegs[FPRIndex], MVT::f64);
1680 SDValue Store = DAG.getStore(Root, dl, Val, FIN, NULL, 0);
1681 MemOps.push_back(Store);
1682 // Increment the address by eight for the next argument to store
1683 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8,
1685 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1688 for (; FPRIndex != NumFPArgRegs; ++FPRIndex) {
1689 unsigned VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
1691 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::f64);
1692 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
1693 MemOps.push_back(Store);
1694 // Increment the address by eight for the next argument to store
1695 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8,
1697 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1701 if (!MemOps.empty())
1702 Root = DAG.getNode(ISD::TokenFactor, dl,
1703 MVT::Other, &MemOps[0], MemOps.size());
1706 ArgValues.push_back(Root);
1708 // Return the new list of results.
1709 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
1710 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
1714 PPCTargetLowering::LowerFORMAL_ARGUMENTS_Darwin(SDValue Op,
1716 int &VarArgsFrameIndex,
1717 const PPCSubtarget &Subtarget) {
1718 // TODO: add description of PPC stack frame format, or at least some docs.
1720 MachineFunction &MF = DAG.getMachineFunction();
1721 MachineFrameInfo *MFI = MF.getFrameInfo();
1722 SmallVector<SDValue, 8> ArgValues;
1723 SDValue Root = Op.getOperand(0);
1724 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
1725 DebugLoc dl = Op.getDebugLoc();
1727 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1728 bool isPPC64 = PtrVT == MVT::i64;
1729 // Potential tail calls could cause overwriting of argument stack slots.
1730 unsigned CC = MF.getFunction()->getCallingConv();
1731 bool isImmutable = !(PerformTailCallOpt && (CC==CallingConv::Fast));
1732 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1734 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, true);
1735 // Area that is at least reserved in caller of this function.
1736 unsigned MinReservedArea = ArgOffset;
1738 static const unsigned GPR_32[] = { // 32-bit registers.
1739 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1740 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1742 static const unsigned GPR_64[] = { // 64-bit registers.
1743 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1744 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1747 static const unsigned *FPR = GetFPR(Subtarget);
1749 static const unsigned VR[] = {
1750 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1751 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1754 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
1755 const unsigned Num_FPR_Regs = 13;
1756 const unsigned Num_VR_Regs = array_lengthof( VR);
1758 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1760 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1762 // In 32-bit non-varargs functions, the stack space for vectors is after the
1763 // stack space for non-vectors. We do not use this space unless we have
1764 // too many vectors to fit in registers, something that only occurs in
1765 // constructed examples:), but we have to walk the arglist to figure
1766 // that out...for the pathological case, compute VecArgOffset as the
1767 // start of the vector parameter area. Computing VecArgOffset is the
1768 // entire point of the following loop.
1769 unsigned VecArgOffset = ArgOffset;
1770 if (!isVarArg && !isPPC64) {
1771 for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues()-1; ArgNo != e;
1773 MVT ObjectVT = Op.getValue(ArgNo).getValueType();
1774 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
1775 ISD::ArgFlagsTy Flags =
1776 cast<ARG_FLAGSSDNode>(Op.getOperand(ArgNo+3))->getArgFlags();
1778 if (Flags.isByVal()) {
1779 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
1780 ObjSize = Flags.getByValSize();
1782 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1783 VecArgOffset += ArgSize;
1787 switch(ObjectVT.getSimpleVT()) {
1788 default: llvm_unreachable("Unhandled argument type!");
1791 VecArgOffset += isPPC64 ? 8 : 4;
1793 case MVT::i64: // PPC64
1801 // Nothing to do, we're only looking at Nonvector args here.
1806 // We've found where the vector parameter area in memory is. Skip the
1807 // first 12 parameters; these don't use that memory.
1808 VecArgOffset = ((VecArgOffset+15)/16)*16;
1809 VecArgOffset += 12*16;
1811 // Add DAG nodes to load the arguments or copy them out of registers. On
1812 // entry to a function on PPC, the arguments start after the linkage area,
1813 // although the first ones are often in registers.
1815 SmallVector<SDValue, 8> MemOps;
1816 unsigned nAltivecParamsAtEnd = 0;
1817 for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues() - 1;
1818 ArgNo != e; ++ArgNo) {
1820 bool needsLoad = false;
1821 MVT ObjectVT = Op.getValue(ArgNo).getValueType();
1822 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
1823 unsigned ArgSize = ObjSize;
1824 ISD::ArgFlagsTy Flags =
1825 cast<ARG_FLAGSSDNode>(Op.getOperand(ArgNo+3))->getArgFlags();
1827 unsigned CurArgOffset = ArgOffset;
1829 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
1830 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
1831 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
1832 if (isVarArg || isPPC64) {
1833 MinReservedArea = ((MinReservedArea+15)/16)*16;
1834 MinReservedArea += CalculateStackSlotSize(Op.getValue(ArgNo),
1837 } else nAltivecParamsAtEnd++;
1839 // Calculate min reserved area.
1840 MinReservedArea += CalculateStackSlotSize(Op.getValue(ArgNo),
1844 // FIXME the codegen can be much improved in some cases.
1845 // We do not have to keep everything in memory.
1846 if (Flags.isByVal()) {
1847 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
1848 ObjSize = Flags.getByValSize();
1849 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1850 // Objects of size 1 and 2 are right justified, everything else is
1851 // left justified. This means the memory address is adjusted forwards.
1852 if (ObjSize==1 || ObjSize==2) {
1853 CurArgOffset = CurArgOffset + (4 - ObjSize);
1855 // The value of the object is its address.
1856 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset);
1857 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1858 ArgValues.push_back(FIN);
1859 if (ObjSize==1 || ObjSize==2) {
1860 if (GPR_idx != Num_GPR_Regs) {
1861 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
1862 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, PtrVT);
1863 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
1864 NULL, 0, ObjSize==1 ? MVT::i8 : MVT::i16 );
1865 MemOps.push_back(Store);
1869 ArgOffset += PtrByteSize;
1873 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
1874 // Store whatever pieces of the object are in registers
1875 // to memory. ArgVal will be address of the beginning of
1877 if (GPR_idx != Num_GPR_Regs) {
1878 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
1879 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset);
1880 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1881 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, PtrVT);
1882 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
1883 MemOps.push_back(Store);
1885 ArgOffset += PtrByteSize;
1887 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
1894 switch (ObjectVT.getSimpleVT()) {
1895 default: llvm_unreachable("Unhandled argument type!");
1898 if (GPR_idx != Num_GPR_Regs) {
1899 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
1900 ArgVal = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32);
1904 ArgSize = PtrByteSize;
1906 // All int arguments reserve stack space in the Darwin ABI.
1907 ArgOffset += PtrByteSize;
1911 case MVT::i64: // PPC64
1912 if (GPR_idx != Num_GPR_Regs) {
1913 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
1914 ArgVal = DAG.getCopyFromReg(Root, dl, VReg, MVT::i64);
1916 if (ObjectVT == MVT::i32) {
1917 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
1918 // value to MVT::i64 and then truncate to the correct register size.
1920 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
1921 DAG.getValueType(ObjectVT));
1922 else if (Flags.isZExt())
1923 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
1924 DAG.getValueType(ObjectVT));
1926 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
1932 ArgSize = PtrByteSize;
1934 // All int arguments reserve stack space in the Darwin ABI.
1940 // Every 4 bytes of argument space consumes one of the GPRs available for
1941 // argument passing.
1942 if (GPR_idx != Num_GPR_Regs) {
1944 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
1947 if (FPR_idx != Num_FPR_Regs) {
1950 if (ObjectVT == MVT::f32)
1951 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
1953 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
1955 ArgVal = DAG.getCopyFromReg(Root, dl, VReg, ObjectVT);
1961 // All FP arguments reserve stack space in the Darwin ABI.
1962 ArgOffset += isPPC64 ? 8 : ObjSize;
1968 // Note that vector arguments in registers don't reserve stack space,
1969 // except in varargs functions.
1970 if (VR_idx != Num_VR_Regs) {
1971 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
1972 ArgVal = DAG.getCopyFromReg(Root, dl, VReg, ObjectVT);
1974 while ((ArgOffset % 16) != 0) {
1975 ArgOffset += PtrByteSize;
1976 if (GPR_idx != Num_GPR_Regs)
1980 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs);
1984 if (!isVarArg && !isPPC64) {
1985 // Vectors go after all the nonvectors.
1986 CurArgOffset = VecArgOffset;
1989 // Vectors are aligned.
1990 ArgOffset = ((ArgOffset+15)/16)*16;
1991 CurArgOffset = ArgOffset;
1999 // We need to load the argument to a virtual register if we determined above
2000 // that we ran out of physical registers of the appropriate type.
2002 int FI = MFI->CreateFixedObject(ObjSize,
2003 CurArgOffset + (ArgSize - ObjSize),
2005 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2006 ArgVal = DAG.getLoad(ObjectVT, dl, Root, FIN, NULL, 0);
2009 ArgValues.push_back(ArgVal);
2012 // Set the size that is at least reserved in caller of this function. Tail
2013 // call optimized function's reserved stack space needs to be aligned so that
2014 // taking the difference between two stack areas will result in an aligned
2016 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2017 // Add the Altivec parameters at the end, if needed.
2018 if (nAltivecParamsAtEnd) {
2019 MinReservedArea = ((MinReservedArea+15)/16)*16;
2020 MinReservedArea += 16*nAltivecParamsAtEnd;
2023 std::max(MinReservedArea,
2024 PPCFrameInfo::getMinCallFrameSize(isPPC64, true));
2025 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
2026 getStackAlignment();
2027 unsigned AlignMask = TargetAlign-1;
2028 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2029 FI->setMinReservedArea(MinReservedArea);
2031 // If the function takes variable number of arguments, make a frame index for
2032 // the start of the first vararg value... for expansion of llvm.va_start.
2034 int Depth = ArgOffset;
2036 VarArgsFrameIndex = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2038 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
2040 // If this function is vararg, store any remaining integer argument regs
2041 // to their spots on the stack so that they may be loaded by deferencing the
2042 // result of va_next.
2043 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2047 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2049 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2051 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, PtrVT);
2052 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
2053 MemOps.push_back(Store);
2054 // Increment the address by four for the next argument to store
2055 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2056 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2060 if (!MemOps.empty())
2061 Root = DAG.getNode(ISD::TokenFactor, dl,
2062 MVT::Other, &MemOps[0], MemOps.size());
2064 ArgValues.push_back(Root);
2066 // Return the new list of results.
2067 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
2068 &ArgValues[0], ArgValues.size());
2071 /// CalculateParameterAndLinkageAreaSize - Get the size of the paramter plus
2072 /// linkage area for the Darwin ABI.
2074 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
2078 CallSDNode *TheCall,
2079 unsigned &nAltivecParamsAtEnd) {
2080 // Count how many bytes are to be pushed on the stack, including the linkage
2081 // area, and parameter passing area. We start with 24/48 bytes, which is
2082 // prereserved space for [SP][CR][LR][3 x unused].
2083 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, true);
2084 unsigned NumOps = TheCall->getNumArgs();
2085 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2087 // Add up all the space actually used.
2088 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
2089 // they all go in registers, but we must reserve stack space for them for
2090 // possible use by the caller. In varargs or 64-bit calls, parameters are
2091 // assigned stack space in order, with padding so Altivec parameters are
2093 nAltivecParamsAtEnd = 0;
2094 for (unsigned i = 0; i != NumOps; ++i) {
2095 SDValue Arg = TheCall->getArg(i);
2096 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
2097 MVT ArgVT = Arg.getValueType();
2098 // Varargs Altivec parameters are padded to a 16 byte boundary.
2099 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
2100 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
2101 if (!isVarArg && !isPPC64) {
2102 // Non-varargs Altivec parameters go after all the non-Altivec
2103 // parameters; handle those later so we know how much padding we need.
2104 nAltivecParamsAtEnd++;
2107 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
2108 NumBytes = ((NumBytes+15)/16)*16;
2110 NumBytes += CalculateStackSlotSize(Arg, Flags, PtrByteSize);
2113 // Allow for Altivec parameters at the end, if needed.
2114 if (nAltivecParamsAtEnd) {
2115 NumBytes = ((NumBytes+15)/16)*16;
2116 NumBytes += 16*nAltivecParamsAtEnd;
2119 // The prolog code of the callee may store up to 8 GPR argument registers to
2120 // the stack, allowing va_start to index over them in memory if its varargs.
2121 // Because we cannot tell if this is needed on the caller side, we have to
2122 // conservatively assume that it is needed. As such, make sure we have at
2123 // least enough stack space for the caller to store the 8 GPRs.
2124 NumBytes = std::max(NumBytes,
2125 PPCFrameInfo::getMinCallFrameSize(isPPC64, true));
2127 // Tail call needs the stack to be aligned.
2128 if (CC==CallingConv::Fast && PerformTailCallOpt) {
2129 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
2130 getStackAlignment();
2131 unsigned AlignMask = TargetAlign-1;
2132 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2138 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
2139 /// adjusted to accomodate the arguments for the tailcall.
2140 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool IsTailCall,
2141 unsigned ParamSize) {
2143 if (!IsTailCall) return 0;
2145 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
2146 unsigned CallerMinReservedArea = FI->getMinReservedArea();
2147 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
2148 // Remember only if the new adjustement is bigger.
2149 if (SPDiff < FI->getTailCallSPDelta())
2150 FI->setTailCallSPDelta(SPDiff);
2155 /// IsEligibleForTailCallElimination - Check to see whether the next instruction
2156 /// following the call is a return. A function is eligible if caller/callee
2157 /// calling conventions match, currently only fastcc supports tail calls, and
2158 /// the function CALL is immediatly followed by a RET.
2160 PPCTargetLowering::IsEligibleForTailCallOptimization(CallSDNode *TheCall,
2162 SelectionDAG& DAG) const {
2163 // Variable argument functions are not supported.
2164 if (!PerformTailCallOpt || TheCall->isVarArg())
2167 if (CheckTailCallReturnConstraints(TheCall, Ret)) {
2168 MachineFunction &MF = DAG.getMachineFunction();
2169 unsigned CallerCC = MF.getFunction()->getCallingConv();
2170 unsigned CalleeCC = TheCall->getCallingConv();
2171 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
2172 // Functions containing by val parameters are not supported.
2173 for (unsigned i = 0; i != TheCall->getNumArgs(); i++) {
2174 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
2175 if (Flags.isByVal()) return false;
2178 SDValue Callee = TheCall->getCallee();
2179 // Non PIC/GOT tail calls are supported.
2180 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
2183 // At the moment we can only do local tail calls (in same module, hidden
2184 // or protected) if we are generating PIC.
2185 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2186 return G->getGlobal()->hasHiddenVisibility()
2187 || G->getGlobal()->hasProtectedVisibility();
2194 /// isCallCompatibleAddress - Return the immediate to use if the specified
2195 /// 32-bit value is representable in the immediate field of a BxA instruction.
2196 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
2197 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2200 int Addr = C->getZExtValue();
2201 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
2202 (Addr << 6 >> 6) != Addr)
2203 return 0; // Top 6 bits have to be sext of immediate.
2205 return DAG.getConstant((int)C->getZExtValue() >> 2,
2206 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
2211 struct TailCallArgumentInfo {
2216 TailCallArgumentInfo() : FrameIdx(0) {}
2221 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
2223 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
2225 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs,
2226 SmallVector<SDValue, 8> &MemOpChains,
2228 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
2229 SDValue Arg = TailCallArgs[i].Arg;
2230 SDValue FIN = TailCallArgs[i].FrameIdxOp;
2231 int FI = TailCallArgs[i].FrameIdx;
2232 // Store relative to framepointer.
2233 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
2234 PseudoSourceValue::getFixedStack(FI),
2239 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
2240 /// the appropriate stack slot for the tail call optimized function call.
2241 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
2242 MachineFunction &MF,
2251 // Calculate the new stack slot for the return address.
2252 int SlotSize = isPPC64 ? 8 : 4;
2253 int NewRetAddrLoc = SPDiff + PPCFrameInfo::getReturnSaveOffset(isPPC64,
2255 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
2257 MVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2258 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
2259 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
2260 PseudoSourceValue::getFixedStack(NewRetAddr), 0);
2262 // When using the SVR4 ABI there is no need to move the FP stack slot
2263 // as the FP is never overwritten.
2266 SPDiff + PPCFrameInfo::getFramePointerSaveOffset(isPPC64, isDarwinABI);
2267 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc);
2268 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
2269 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
2270 PseudoSourceValue::getFixedStack(NewFPIdx), 0);
2276 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
2277 /// the position of the argument.
2279 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
2280 SDValue Arg, int SPDiff, unsigned ArgOffset,
2281 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
2282 int Offset = ArgOffset + SPDiff;
2283 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
2284 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
2285 MVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2286 SDValue FIN = DAG.getFrameIndex(FI, VT);
2287 TailCallArgumentInfo Info;
2289 Info.FrameIdxOp = FIN;
2291 TailCallArguments.push_back(Info);
2294 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
2295 /// stack slot. Returns the chain as result and the loaded frame pointers in
2296 /// LROpOut/FPOpout. Used when tail calling.
2297 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
2305 // Load the LR and FP stack slot for later adjusting.
2306 MVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
2307 LROpOut = getReturnAddrFrameIndex(DAG);
2308 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, NULL, 0);
2309 Chain = SDValue(LROpOut.getNode(), 1);
2311 // When using the SVR4 ABI there is no need to load the FP stack slot
2312 // as the FP is never overwritten.
2314 FPOpOut = getFramePointerFrameIndex(DAG);
2315 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, NULL, 0);
2316 Chain = SDValue(FPOpOut.getNode(), 1);
2322 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2323 /// by "Src" to address "Dst" of size "Size". Alignment information is
2324 /// specified by the specific parameter attribute. The copy will be passed as
2325 /// a byval function parameter.
2326 /// Sometimes what we are copying is the end of a larger object, the part that
2327 /// does not fit in registers.
2329 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2330 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2332 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2333 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2334 false, NULL, 0, NULL, 0);
2337 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
2340 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
2341 SDValue Arg, SDValue PtrOff, int SPDiff,
2342 unsigned ArgOffset, bool isPPC64, bool isTailCall,
2343 bool isVector, SmallVector<SDValue, 8> &MemOpChains,
2344 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments,
2346 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2351 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
2353 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2354 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
2355 DAG.getConstant(ArgOffset, PtrVT));
2357 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0));
2358 // Calculate and remember argument location.
2359 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
2364 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
2365 DebugLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
2366 SDValue LROp, SDValue FPOp, bool isDarwinABI,
2367 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments) {
2368 MachineFunction &MF = DAG.getMachineFunction();
2370 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
2371 // might overwrite each other in case of tail call optimization.
2372 SmallVector<SDValue, 8> MemOpChains2;
2373 // Do not flag preceeding copytoreg stuff together with the following stuff.
2375 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
2377 if (!MemOpChains2.empty())
2378 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2379 &MemOpChains2[0], MemOpChains2.size());
2381 // Store the return address to the appropriate stack slot.
2382 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
2383 isPPC64, isDarwinABI, dl);
2385 // Emit callseq_end just before tailcall node.
2386 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2387 DAG.getIntPtrConstant(0, true), InFlag);
2388 InFlag = Chain.getValue(1);
2392 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
2393 SDValue &Chain, DebugLoc dl, int SPDiff, bool isTailCall,
2394 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
2395 SmallVector<SDValue, 8> &Ops, std::vector<MVT> &NodeTys,
2397 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2398 NodeTys.push_back(MVT::Other); // Returns a chain
2399 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
2401 unsigned CallOpc = isSVR4ABI ? PPCISD::CALL_SVR4 : PPCISD::CALL_Darwin;
2403 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2404 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2405 // node so that legalize doesn't hack it.
2406 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2407 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
2408 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
2409 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType());
2410 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
2411 // If this is an absolute destination address, use the munged value.
2412 Callee = SDValue(Dest, 0);
2414 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
2415 // to do the call, we can't use PPCISD::CALL.
2416 SDValue MTCTROps[] = {Chain, Callee, InFlag};
2417 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps,
2418 2 + (InFlag.getNode() != 0));
2419 InFlag = Chain.getValue(1);
2422 NodeTys.push_back(MVT::Other);
2423 NodeTys.push_back(MVT::Flag);
2424 Ops.push_back(Chain);
2425 CallOpc = isSVR4ABI ? PPCISD::BCTRL_SVR4 : PPCISD::BCTRL_Darwin;
2427 // Add CTR register as callee so a bctr can be emitted later.
2429 Ops.push_back(DAG.getRegister(PPC::CTR, PtrVT));
2432 // If this is a direct call, pass the chain and the callee.
2433 if (Callee.getNode()) {
2434 Ops.push_back(Chain);
2435 Ops.push_back(Callee);
2437 // If this is a tail call add stack pointer delta.
2439 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
2441 // Add argument registers to the end of the list so that they are known live
2443 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2444 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2445 RegsToPass[i].second.getValueType()));
2450 static SDValue LowerCallReturn(SDValue Op, SelectionDAG &DAG, TargetMachine &TM,
2451 CallSDNode *TheCall, SDValue Chain,
2453 bool isVarArg = TheCall->isVarArg();
2454 DebugLoc dl = TheCall->getDebugLoc();
2455 SmallVector<SDValue, 16> ResultVals;
2456 SmallVector<CCValAssign, 16> RVLocs;
2457 unsigned CallerCC = DAG.getMachineFunction().getFunction()->getCallingConv();
2458 CCState CCRetInfo(CallerCC, isVarArg, TM, RVLocs, DAG.getContext());
2459 CCRetInfo.AnalyzeCallResult(TheCall, RetCC_PPC);
2461 // Copy all of the result registers out of their specified physreg.
2462 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2463 CCValAssign &VA = RVLocs[i];
2464 MVT VT = VA.getValVT();
2465 assert(VA.isRegLoc() && "Can only return in registers!");
2466 Chain = DAG.getCopyFromReg(Chain, dl,
2467 VA.getLocReg(), VT, InFlag).getValue(1);
2468 ResultVals.push_back(Chain.getValue(0));
2469 InFlag = Chain.getValue(2);
2472 // If the function returns void, just return the chain.
2476 // Otherwise, merge everything together with a MERGE_VALUES node.
2477 ResultVals.push_back(Chain);
2478 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
2479 &ResultVals[0], ResultVals.size());
2480 return Res.getValue(Op.getResNo());
2484 SDValue FinishCall(SelectionDAG &DAG, CallSDNode *TheCall, TargetMachine &TM,
2485 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
2486 SDValue Op, SDValue InFlag, SDValue Chain, SDValue &Callee,
2487 int SPDiff, unsigned NumBytes) {
2488 unsigned CC = TheCall->getCallingConv();
2489 DebugLoc dl = TheCall->getDebugLoc();
2490 bool isTailCall = TheCall->isTailCall()
2491 && CC == CallingConv::Fast && PerformTailCallOpt;
2493 std::vector<MVT> NodeTys;
2494 SmallVector<SDValue, 8> Ops;
2495 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
2496 isTailCall, RegsToPass, Ops, NodeTys,
2497 TM.getSubtarget<PPCSubtarget>().isSVR4ABI());
2499 // When performing tail call optimization the callee pops its arguments off
2500 // the stack. Account for this here so these bytes can be pushed back on in
2501 // PPCRegisterInfo::eliminateCallFramePseudoInstr.
2502 int BytesCalleePops =
2503 (CC==CallingConv::Fast && PerformTailCallOpt) ? NumBytes : 0;
2505 if (InFlag.getNode())
2506 Ops.push_back(InFlag);
2510 assert(InFlag.getNode() &&
2511 "Flag must be set. Depend on flag being set in LowerRET");
2512 Chain = DAG.getNode(PPCISD::TAILCALL, dl,
2513 TheCall->getVTList(), &Ops[0], Ops.size());
2514 return SDValue(Chain.getNode(), Op.getResNo());
2517 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
2518 InFlag = Chain.getValue(1);
2520 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2521 DAG.getIntPtrConstant(BytesCalleePops, true),
2523 if (TheCall->getValueType(0) != MVT::Other)
2524 InFlag = Chain.getValue(1);
2526 return LowerCallReturn(Op, DAG, TM, TheCall, Chain, InFlag);
2529 SDValue PPCTargetLowering::LowerCALL_SVR4(SDValue Op, SelectionDAG &DAG,
2530 const PPCSubtarget &Subtarget,
2531 TargetMachine &TM) {
2532 // See PPCTargetLowering::LowerFORMAL_ARGUMENTS_SVR4() for a description
2533 // of the SVR4 ABI stack frame layout.
2534 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
2535 SDValue Chain = TheCall->getChain();
2536 bool isVarArg = TheCall->isVarArg();
2537 unsigned CC = TheCall->getCallingConv();
2538 assert((CC == CallingConv::C ||
2539 CC == CallingConv::Fast) && "Unknown calling convention!");
2540 bool isTailCall = TheCall->isTailCall()
2541 && CC == CallingConv::Fast && PerformTailCallOpt;
2542 SDValue Callee = TheCall->getCallee();
2543 DebugLoc dl = TheCall->getDebugLoc();
2545 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2546 unsigned PtrByteSize = 4;
2548 MachineFunction &MF = DAG.getMachineFunction();
2550 // Mark this function as potentially containing a function that contains a
2551 // tail call. As a consequence the frame pointer will be used for dynamicalloc
2552 // and restoring the callers stack pointer in this functions epilog. This is
2553 // done because by tail calling the called function might overwrite the value
2554 // in this function's (MF) stack pointer stack slot 0(SP).
2555 if (PerformTailCallOpt && CC==CallingConv::Fast)
2556 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
2558 // Count how many bytes are to be pushed on the stack, including the linkage
2559 // area, parameter list area and the part of the local variable space which
2560 // contains copies of aggregates which are passed by value.
2562 // Assign locations to all of the outgoing arguments.
2563 SmallVector<CCValAssign, 16> ArgLocs;
2564 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, DAG.getContext());
2566 // Reserve space for the linkage area on the stack.
2567 CCInfo.AllocateStack(PPCFrameInfo::getLinkageSize(false, false), PtrByteSize);
2570 // Handle fixed and variable vector arguments differently.
2571 // Fixed vector arguments go into registers as long as registers are
2572 // available. Variable vector arguments always go into memory.
2573 unsigned NumArgs = TheCall->getNumArgs();
2574 unsigned NumFixedArgs = TheCall->getNumFixedArgs();
2576 for (unsigned i = 0; i != NumArgs; ++i) {
2577 MVT ArgVT = TheCall->getArg(i).getValueType();
2578 ISD::ArgFlagsTy ArgFlags = TheCall->getArgFlags(i);
2581 if (i < NumFixedArgs) {
2582 Result = CC_PPC_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
2585 Result = CC_PPC_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
2591 cerr << "Call operand #" << i << " has unhandled type "
2592 << ArgVT.getMVTString() << "\n";
2594 llvm_unreachable(0);
2598 // All arguments are treated the same.
2599 CCInfo.AnalyzeCallOperands(TheCall, CC_PPC_SVR4);
2602 // Assign locations to all of the outgoing aggregate by value arguments.
2603 SmallVector<CCValAssign, 16> ByValArgLocs;
2604 CCState CCByValInfo(CC, isVarArg, getTargetMachine(), ByValArgLocs,
2607 // Reserve stack space for the allocations in CCInfo.
2608 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2610 CCByValInfo.AnalyzeCallOperands(TheCall, CC_PPC_SVR4_ByVal);
2612 // Size of the linkage area, parameter list area and the part of the local
2613 // space variable where copies of aggregates which are passed by value are
2615 unsigned NumBytes = CCByValInfo.getNextStackOffset();
2617 // Calculate by how many bytes the stack has to be adjusted in case of tail
2618 // call optimization.
2619 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
2621 // Adjust the stack pointer for the new arguments...
2622 // These operations are automatically eliminated by the prolog/epilog pass
2623 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2624 SDValue CallSeqStart = Chain;
2626 // Load the return address and frame pointer so it can be moved somewhere else
2629 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
2632 // Set up a copy of the stack pointer for use loading and storing any
2633 // arguments that may not fit in the registers available for argument
2635 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2637 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2638 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
2639 SmallVector<SDValue, 8> MemOpChains;
2641 // Walk the register/memloc assignments, inserting copies/loads.
2642 for (unsigned i = 0, j = 0, e = ArgLocs.size();
2645 CCValAssign &VA = ArgLocs[i];
2646 SDValue Arg = TheCall->getArg(i);
2647 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
2649 if (Flags.isByVal()) {
2650 // Argument is an aggregate which is passed by value, thus we need to
2651 // create a copy of it in the local variable space of the current stack
2652 // frame (which is the stack frame of the caller) and pass the address of
2653 // this copy to the callee.
2654 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
2655 CCValAssign &ByValVA = ByValArgLocs[j++];
2656 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
2658 // Memory reserved in the local variable space of the callers stack frame.
2659 unsigned LocMemOffset = ByValVA.getLocMemOffset();
2661 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2662 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2664 // Create a copy of the argument in the local area of the current
2666 SDValue MemcpyCall =
2667 CreateCopyOfByValArgument(Arg, PtrOff,
2668 CallSeqStart.getNode()->getOperand(0),
2671 // This must go outside the CALLSEQ_START..END.
2672 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
2673 CallSeqStart.getNode()->getOperand(1));
2674 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
2675 NewCallSeqStart.getNode());
2676 Chain = CallSeqStart = NewCallSeqStart;
2678 // Pass the address of the aggregate copy on the stack either in a
2679 // physical register or in the parameter list area of the current stack
2680 // frame to the callee.
2684 if (VA.isRegLoc()) {
2685 // Put argument in a physical register.
2686 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2688 // Put argument in the parameter list area of the current stack frame.
2689 assert(VA.isMemLoc());
2690 unsigned LocMemOffset = VA.getLocMemOffset();
2693 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2694 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2696 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
2697 PseudoSourceValue::getStack(), LocMemOffset));
2699 // Calculate and remember argument location.
2700 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
2706 if (!MemOpChains.empty())
2707 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2708 &MemOpChains[0], MemOpChains.size());
2710 // Build a sequence of copy-to-reg nodes chained together with token chain
2711 // and flag operands which copy the outgoing args into the appropriate regs.
2713 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2714 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2715 RegsToPass[i].second, InFlag);
2716 InFlag = Chain.getValue(1);
2719 // Set CR6 to true if this is a vararg call.
2721 SDValue SetCR(DAG.getTargetNode(PPC::CRSET, dl, MVT::i32), 0);
2722 Chain = DAG.getCopyToReg(Chain, dl, PPC::CR1EQ, SetCR, InFlag);
2723 InFlag = Chain.getValue(1);
2727 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
2728 false, TailCallArguments);
2731 return FinishCall(DAG, TheCall, TM, RegsToPass, Op, InFlag, Chain, Callee,
2735 SDValue PPCTargetLowering::LowerCALL_Darwin(SDValue Op, SelectionDAG &DAG,
2736 const PPCSubtarget &Subtarget,
2737 TargetMachine &TM) {
2738 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
2739 SDValue Chain = TheCall->getChain();
2740 bool isVarArg = TheCall->isVarArg();
2741 unsigned CC = TheCall->getCallingConv();
2742 bool isTailCall = TheCall->isTailCall()
2743 && CC == CallingConv::Fast && PerformTailCallOpt;
2744 SDValue Callee = TheCall->getCallee();
2745 unsigned NumOps = TheCall->getNumArgs();
2746 DebugLoc dl = TheCall->getDebugLoc();
2748 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2749 bool isPPC64 = PtrVT == MVT::i64;
2750 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2752 MachineFunction &MF = DAG.getMachineFunction();
2754 // Mark this function as potentially containing a function that contains a
2755 // tail call. As a consequence the frame pointer will be used for dynamicalloc
2756 // and restoring the callers stack pointer in this functions epilog. This is
2757 // done because by tail calling the called function might overwrite the value
2758 // in this function's (MF) stack pointer stack slot 0(SP).
2759 if (PerformTailCallOpt && CC==CallingConv::Fast)
2760 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
2762 unsigned nAltivecParamsAtEnd = 0;
2764 // Count how many bytes are to be pushed on the stack, including the linkage
2765 // area, and parameter passing area. We start with 24/48 bytes, which is
2766 // prereserved space for [SP][CR][LR][3 x unused].
2768 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CC, TheCall,
2769 nAltivecParamsAtEnd);
2771 // Calculate by how many bytes the stack has to be adjusted in case of tail
2772 // call optimization.
2773 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
2775 // Adjust the stack pointer for the new arguments...
2776 // These operations are automatically eliminated by the prolog/epilog pass
2777 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2778 SDValue CallSeqStart = Chain;
2780 // Load the return address and frame pointer so it can be move somewhere else
2783 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
2786 // Set up a copy of the stack pointer for use loading and storing any
2787 // arguments that may not fit in the registers available for argument
2791 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
2793 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2795 // Figure out which arguments are going to go in registers, and which in
2796 // memory. Also, if this is a vararg function, floating point operations
2797 // must be stored to our stack, and loaded into integer regs as well, if
2798 // any integer regs are available for argument passing.
2799 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, true);
2800 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2802 static const unsigned GPR_32[] = { // 32-bit registers.
2803 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2804 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2806 static const unsigned GPR_64[] = { // 64-bit registers.
2807 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2808 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2810 static const unsigned *FPR = GetFPR(Subtarget);
2812 static const unsigned VR[] = {
2813 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2814 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2816 const unsigned NumGPRs = array_lengthof(GPR_32);
2817 const unsigned NumFPRs = 13;
2818 const unsigned NumVRs = array_lengthof(VR);
2820 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
2822 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2823 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
2825 SmallVector<SDValue, 8> MemOpChains;
2826 for (unsigned i = 0; i != NumOps; ++i) {
2828 SDValue Arg = TheCall->getArg(i);
2829 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
2831 // PtrOff will be used to store the current argument to the stack if a
2832 // register cannot be found for it.
2835 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
2837 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
2839 // On PPC64, promote integers to 64-bit values.
2840 if (isPPC64 && Arg.getValueType() == MVT::i32) {
2841 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
2842 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
2843 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
2846 // FIXME memcpy is used way more than necessary. Correctness first.
2847 if (Flags.isByVal()) {
2848 unsigned Size = Flags.getByValSize();
2849 if (Size==1 || Size==2) {
2850 // Very small objects are passed right-justified.
2851 // Everything else is passed left-justified.
2852 MVT VT = (Size==1) ? MVT::i8 : MVT::i16;
2853 if (GPR_idx != NumGPRs) {
2854 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
2856 MemOpChains.push_back(Load.getValue(1));
2857 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
2859 ArgOffset += PtrByteSize;
2861 SDValue Const = DAG.getConstant(4 - Size, PtrOff.getValueType());
2862 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
2863 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr,
2864 CallSeqStart.getNode()->getOperand(0),
2866 // This must go outside the CALLSEQ_START..END.
2867 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
2868 CallSeqStart.getNode()->getOperand(1));
2869 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
2870 NewCallSeqStart.getNode());
2871 Chain = CallSeqStart = NewCallSeqStart;
2872 ArgOffset += PtrByteSize;
2876 // Copy entire object into memory. There are cases where gcc-generated
2877 // code assumes it is there, even if it could be put entirely into
2878 // registers. (This is not what the doc says.)
2879 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
2880 CallSeqStart.getNode()->getOperand(0),
2882 // This must go outside the CALLSEQ_START..END.
2883 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
2884 CallSeqStart.getNode()->getOperand(1));
2885 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), NewCallSeqStart.getNode());
2886 Chain = CallSeqStart = NewCallSeqStart;
2887 // And copy the pieces of it that fit into registers.
2888 for (unsigned j=0; j<Size; j+=PtrByteSize) {
2889 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
2890 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
2891 if (GPR_idx != NumGPRs) {
2892 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, NULL, 0);
2893 MemOpChains.push_back(Load.getValue(1));
2894 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
2895 ArgOffset += PtrByteSize;
2897 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
2904 switch (Arg.getValueType().getSimpleVT()) {
2905 default: llvm_unreachable("Unexpected ValueType for argument!");
2908 if (GPR_idx != NumGPRs) {
2909 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
2911 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
2912 isPPC64, isTailCall, false, MemOpChains,
2913 TailCallArguments, dl);
2916 ArgOffset += PtrByteSize;
2920 if (FPR_idx != NumFPRs) {
2921 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
2924 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0);
2925 MemOpChains.push_back(Store);
2927 // Float varargs are always shadowed in available integer registers
2928 if (GPR_idx != NumGPRs) {
2929 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, NULL, 0);
2930 MemOpChains.push_back(Load.getValue(1));
2931 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
2933 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
2934 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
2935 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
2936 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, NULL, 0);
2937 MemOpChains.push_back(Load.getValue(1));
2938 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
2941 // If we have any FPRs remaining, we may also have GPRs remaining.
2942 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
2944 if (GPR_idx != NumGPRs)
2946 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
2947 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
2951 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
2952 isPPC64, isTailCall, false, MemOpChains,
2953 TailCallArguments, dl);
2959 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
2966 // These go aligned on the stack, or in the corresponding R registers
2967 // when within range. The Darwin PPC ABI doc claims they also go in
2968 // V registers; in fact gcc does this only for arguments that are
2969 // prototyped, not for those that match the ... We do it for all
2970 // arguments, seems to work.
2971 while (ArgOffset % 16 !=0) {
2972 ArgOffset += PtrByteSize;
2973 if (GPR_idx != NumGPRs)
2976 // We could elide this store in the case where the object fits
2977 // entirely in R registers. Maybe later.
2978 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
2979 DAG.getConstant(ArgOffset, PtrVT));
2980 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0);
2981 MemOpChains.push_back(Store);
2982 if (VR_idx != NumVRs) {
2983 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, NULL, 0);
2984 MemOpChains.push_back(Load.getValue(1));
2985 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
2988 for (unsigned i=0; i<16; i+=PtrByteSize) {
2989 if (GPR_idx == NumGPRs)
2991 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
2992 DAG.getConstant(i, PtrVT));
2993 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, NULL, 0);
2994 MemOpChains.push_back(Load.getValue(1));
2995 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3000 // Non-varargs Altivec params generally go in registers, but have
3001 // stack space allocated at the end.
3002 if (VR_idx != NumVRs) {
3003 // Doesn't have GPR space allocated.
3004 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
3005 } else if (nAltivecParamsAtEnd==0) {
3006 // We are emitting Altivec params in order.
3007 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3008 isPPC64, isTailCall, true, MemOpChains,
3009 TailCallArguments, dl);
3015 // If all Altivec parameters fit in registers, as they usually do,
3016 // they get stack space following the non-Altivec parameters. We
3017 // don't track this here because nobody below needs it.
3018 // If there are more Altivec parameters than fit in registers emit
3020 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
3022 // Offset is aligned; skip 1st 12 params which go in V registers.
3023 ArgOffset = ((ArgOffset+15)/16)*16;
3025 for (unsigned i = 0; i != NumOps; ++i) {
3026 SDValue Arg = TheCall->getArg(i);
3027 MVT ArgType = Arg.getValueType();
3028 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
3029 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
3032 // We are emitting Altivec params in order.
3033 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3034 isPPC64, isTailCall, true, MemOpChains,
3035 TailCallArguments, dl);
3042 if (!MemOpChains.empty())
3043 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3044 &MemOpChains[0], MemOpChains.size());
3046 // Build a sequence of copy-to-reg nodes chained together with token chain
3047 // and flag operands which copy the outgoing args into the appropriate regs.
3049 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3050 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3051 RegsToPass[i].second, InFlag);
3052 InFlag = Chain.getValue(1);
3056 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
3057 FPOp, true, TailCallArguments);
3060 return FinishCall(DAG, TheCall, TM, RegsToPass, Op, InFlag, Chain, Callee,
3064 SDValue PPCTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG,
3065 TargetMachine &TM) {
3066 SmallVector<CCValAssign, 16> RVLocs;
3067 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
3068 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
3069 DebugLoc dl = Op.getDebugLoc();
3070 CCState CCInfo(CC, isVarArg, TM, RVLocs, DAG.getContext());
3071 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_PPC);
3073 // If this is the first return lowered for this function, add the regs to the
3074 // liveout set for the function.
3075 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
3076 for (unsigned i = 0; i != RVLocs.size(); ++i)
3077 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
3080 SDValue Chain = Op.getOperand(0);
3082 Chain = GetPossiblePreceedingTailCall(Chain, PPCISD::TAILCALL);
3083 if (Chain.getOpcode() == PPCISD::TAILCALL) {
3084 SDValue TailCall = Chain;
3085 SDValue TargetAddress = TailCall.getOperand(1);
3086 SDValue StackAdjustment = TailCall.getOperand(2);
3088 assert(((TargetAddress.getOpcode() == ISD::Register &&
3089 cast<RegisterSDNode>(TargetAddress)->getReg() == PPC::CTR) ||
3090 TargetAddress.getOpcode() == ISD::TargetExternalSymbol ||
3091 TargetAddress.getOpcode() == ISD::TargetGlobalAddress ||
3092 isa<ConstantSDNode>(TargetAddress)) &&
3093 "Expecting an global address, external symbol, absolute value or register");
3095 assert(StackAdjustment.getOpcode() == ISD::Constant &&
3096 "Expecting a const value");
3098 SmallVector<SDValue,8> Operands;
3099 Operands.push_back(Chain.getOperand(0));
3100 Operands.push_back(TargetAddress);
3101 Operands.push_back(StackAdjustment);
3102 // Copy registers used by the call. Last operand is a flag so it is not
3104 for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) {
3105 Operands.push_back(Chain.getOperand(i));
3107 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Operands[0],
3113 // Copy the result values into the output registers.
3114 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3115 CCValAssign &VA = RVLocs[i];
3116 assert(VA.isRegLoc() && "Can only return in registers!");
3117 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3118 Op.getOperand(i*2+1), Flag);
3119 Flag = Chain.getValue(1);
3123 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
3125 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain);
3128 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
3129 const PPCSubtarget &Subtarget) {
3130 // When we pop the dynamic allocation we need to restore the SP link.
3131 DebugLoc dl = Op.getDebugLoc();
3133 // Get the corect type for pointers.
3134 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3136 // Construct the stack pointer operand.
3137 bool IsPPC64 = Subtarget.isPPC64();
3138 unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1;
3139 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
3141 // Get the operands for the STACKRESTORE.
3142 SDValue Chain = Op.getOperand(0);
3143 SDValue SaveSP = Op.getOperand(1);
3145 // Load the old link SP.
3146 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr, NULL, 0);
3148 // Restore the stack pointer.
3149 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
3151 // Store the old link SP.
3152 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, NULL, 0);
3158 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
3159 MachineFunction &MF = DAG.getMachineFunction();
3160 bool IsPPC64 = PPCSubTarget.isPPC64();
3161 bool isDarwinABI = PPCSubTarget.isDarwinABI();
3162 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3164 // Get current frame pointer save index. The users of this index will be
3165 // primarily DYNALLOC instructions.
3166 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
3167 int RASI = FI->getReturnAddrSaveIndex();
3169 // If the frame pointer save index hasn't been defined yet.
3171 // Find out what the fix offset of the frame pointer save area.
3172 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, isDarwinABI);
3173 // Allocate the frame index for frame pointer save area.
3174 RASI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, LROffset);
3176 FI->setReturnAddrSaveIndex(RASI);
3178 return DAG.getFrameIndex(RASI, PtrVT);
3182 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
3183 MachineFunction &MF = DAG.getMachineFunction();
3184 bool IsPPC64 = PPCSubTarget.isPPC64();
3185 bool isDarwinABI = PPCSubTarget.isDarwinABI();
3186 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3188 // Get current frame pointer save index. The users of this index will be
3189 // primarily DYNALLOC instructions.
3190 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
3191 int FPSI = FI->getFramePointerSaveIndex();
3193 // If the frame pointer save index hasn't been defined yet.
3195 // Find out what the fix offset of the frame pointer save area.
3196 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64,
3199 // Allocate the frame index for frame pointer save area.
3200 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
3202 FI->setFramePointerSaveIndex(FPSI);
3204 return DAG.getFrameIndex(FPSI, PtrVT);
3207 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
3209 const PPCSubtarget &Subtarget) {
3211 SDValue Chain = Op.getOperand(0);
3212 SDValue Size = Op.getOperand(1);
3213 DebugLoc dl = Op.getDebugLoc();
3215 // Get the corect type for pointers.
3216 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3218 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
3219 DAG.getConstant(0, PtrVT), Size);
3220 // Construct a node for the frame pointer save index.
3221 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
3222 // Build a DYNALLOC node.
3223 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
3224 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
3225 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3);
3228 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
3230 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
3231 // Not FP? Not a fsel.
3232 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
3233 !Op.getOperand(2).getValueType().isFloatingPoint())
3236 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3238 // Cannot handle SETEQ/SETNE.
3239 if (CC == ISD::SETEQ || CC == ISD::SETNE) return Op;
3241 MVT ResVT = Op.getValueType();
3242 MVT CmpVT = Op.getOperand(0).getValueType();
3243 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3244 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
3245 DebugLoc dl = Op.getDebugLoc();
3247 // If the RHS of the comparison is a 0.0, we don't need to do the
3248 // subtraction at all.
3249 if (isFloatingPointZero(RHS))
3251 default: break; // SETUO etc aren't handled by fsel.
3254 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
3257 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
3258 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
3259 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
3262 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
3265 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
3266 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
3267 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
3268 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
3273 default: break; // SETUO etc aren't handled by fsel.
3276 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
3277 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3278 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3279 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
3282 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
3283 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3284 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3285 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
3288 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
3289 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3290 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3291 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
3294 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
3295 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3296 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3297 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
3302 // FIXME: Split this code up when LegalizeDAGTypes lands.
3303 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
3305 assert(Op.getOperand(0).getValueType().isFloatingPoint());
3306 SDValue Src = Op.getOperand(0);
3307 if (Src.getValueType() == MVT::f32)
3308 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
3311 switch (Op.getValueType().getSimpleVT()) {
3312 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
3314 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
3319 Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src);
3323 // Convert the FP value to an int value through memory.
3324 SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64);
3326 // Emit a store to the stack slot.
3327 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr, NULL, 0);
3329 // Result is a load from the stack slot. If loading 4 bytes, make sure to
3331 if (Op.getValueType() == MVT::i32)
3332 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
3333 DAG.getConstant(4, FIPtr.getValueType()));
3334 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, NULL, 0);
3337 SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
3338 DebugLoc dl = Op.getDebugLoc();
3339 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
3340 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
3343 if (Op.getOperand(0).getValueType() == MVT::i64) {
3344 SDValue Bits = DAG.getNode(ISD::BIT_CONVERT, dl,
3345 MVT::f64, Op.getOperand(0));
3346 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits);
3347 if (Op.getValueType() == MVT::f32)
3348 FP = DAG.getNode(ISD::FP_ROUND, dl,
3349 MVT::f32, FP, DAG.getIntPtrConstant(0));
3353 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
3354 "Unhandled SINT_TO_FP type in custom expander!");
3355 // Since we only generate this in 64-bit mode, we can take advantage of
3356 // 64-bit registers. In particular, sign extend the input value into the
3357 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
3358 // then lfd it and fcfid it.
3359 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
3360 int FrameIdx = FrameInfo->CreateStackObject(8, 8);
3361 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3362 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
3364 SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, MVT::i32,
3367 // STD the extended value into the stack slot.
3368 MachineMemOperand MO(PseudoSourceValue::getFixedStack(FrameIdx),
3369 MachineMemOperand::MOStore, 0, 8, 8);
3370 SDValue Store = DAG.getNode(PPCISD::STD_32, dl, MVT::Other,
3371 DAG.getEntryNode(), Ext64, FIdx,
3372 DAG.getMemOperand(MO));
3373 // Load the value as a double.
3374 SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, NULL, 0);
3376 // FCFID it and return it.
3377 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld);
3378 if (Op.getValueType() == MVT::f32)
3379 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
3383 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
3384 DebugLoc dl = Op.getDebugLoc();
3386 The rounding mode is in bits 30:31 of FPSR, and has the following
3393 FLT_ROUNDS, on the other hand, expects the following:
3400 To perform the conversion, we do:
3401 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
3404 MachineFunction &MF = DAG.getMachineFunction();
3405 MVT VT = Op.getValueType();
3406 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3407 std::vector<MVT> NodeTys;
3408 SDValue MFFSreg, InFlag;
3410 // Save FP Control Word to register
3411 NodeTys.push_back(MVT::f64); // return register
3412 NodeTys.push_back(MVT::Flag); // unused in this context
3413 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
3415 // Save FP register to stack slot
3416 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
3417 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
3418 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
3419 StackSlot, NULL, 0);
3421 // Load FP Control Word from low 32 bits of stack slot.
3422 SDValue Four = DAG.getConstant(4, PtrVT);
3423 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
3424 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, NULL, 0);
3426 // Transform as necessary
3428 DAG.getNode(ISD::AND, dl, MVT::i32,
3429 CWD, DAG.getConstant(3, MVT::i32));
3431 DAG.getNode(ISD::SRL, dl, MVT::i32,
3432 DAG.getNode(ISD::AND, dl, MVT::i32,
3433 DAG.getNode(ISD::XOR, dl, MVT::i32,
3434 CWD, DAG.getConstant(3, MVT::i32)),
3435 DAG.getConstant(3, MVT::i32)),
3436 DAG.getConstant(1, MVT::i32));
3439 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
3441 return DAG.getNode((VT.getSizeInBits() < 16 ?
3442 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
3445 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) {
3446 MVT VT = Op.getValueType();
3447 unsigned BitWidth = VT.getSizeInBits();
3448 DebugLoc dl = Op.getDebugLoc();
3449 assert(Op.getNumOperands() == 3 &&
3450 VT == Op.getOperand(1).getValueType() &&
3453 // Expand into a bunch of logical ops. Note that these ops
3454 // depend on the PPC behavior for oversized shift amounts.
3455 SDValue Lo = Op.getOperand(0);
3456 SDValue Hi = Op.getOperand(1);
3457 SDValue Amt = Op.getOperand(2);
3458 MVT AmtVT = Amt.getValueType();
3460 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3461 DAG.getConstant(BitWidth, AmtVT), Amt);
3462 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
3463 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
3464 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
3465 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3466 DAG.getConstant(-BitWidth, AmtVT));
3467 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
3468 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
3469 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
3470 SDValue OutOps[] = { OutLo, OutHi };
3471 return DAG.getMergeValues(OutOps, 2, dl);
3474 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) {
3475 MVT VT = Op.getValueType();
3476 DebugLoc dl = Op.getDebugLoc();
3477 unsigned BitWidth = VT.getSizeInBits();
3478 assert(Op.getNumOperands() == 3 &&
3479 VT == Op.getOperand(1).getValueType() &&
3482 // Expand into a bunch of logical ops. Note that these ops
3483 // depend on the PPC behavior for oversized shift amounts.
3484 SDValue Lo = Op.getOperand(0);
3485 SDValue Hi = Op.getOperand(1);
3486 SDValue Amt = Op.getOperand(2);
3487 MVT AmtVT = Amt.getValueType();
3489 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3490 DAG.getConstant(BitWidth, AmtVT), Amt);
3491 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
3492 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
3493 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
3494 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3495 DAG.getConstant(-BitWidth, AmtVT));
3496 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
3497 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
3498 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
3499 SDValue OutOps[] = { OutLo, OutHi };
3500 return DAG.getMergeValues(OutOps, 2, dl);
3503 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) {
3504 DebugLoc dl = Op.getDebugLoc();
3505 MVT VT = Op.getValueType();
3506 unsigned BitWidth = VT.getSizeInBits();
3507 assert(Op.getNumOperands() == 3 &&
3508 VT == Op.getOperand(1).getValueType() &&
3511 // Expand into a bunch of logical ops, followed by a select_cc.
3512 SDValue Lo = Op.getOperand(0);
3513 SDValue Hi = Op.getOperand(1);
3514 SDValue Amt = Op.getOperand(2);
3515 MVT AmtVT = Amt.getValueType();
3517 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3518 DAG.getConstant(BitWidth, AmtVT), Amt);
3519 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
3520 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
3521 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
3522 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3523 DAG.getConstant(-BitWidth, AmtVT));
3524 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
3525 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
3526 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
3527 Tmp4, Tmp6, ISD::SETLE);
3528 SDValue OutOps[] = { OutLo, OutHi };
3529 return DAG.getMergeValues(OutOps, 2, dl);
3532 //===----------------------------------------------------------------------===//
3533 // Vector related lowering.
3536 /// BuildSplatI - Build a canonical splati of Val with an element size of
3537 /// SplatSize. Cast the result to VT.
3538 static SDValue BuildSplatI(int Val, unsigned SplatSize, MVT VT,
3539 SelectionDAG &DAG, DebugLoc dl) {
3540 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
3542 static const MVT VTys[] = { // canonical VT to use for each size.
3543 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
3546 MVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
3548 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
3552 MVT CanonicalVT = VTys[SplatSize-1];
3554 // Build a canonical splat for this value.
3555 SDValue Elt = DAG.getConstant(Val, MVT::i32);
3556 SmallVector<SDValue, 8> Ops;
3557 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
3558 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
3559 &Ops[0], Ops.size());
3560 return DAG.getNode(ISD::BIT_CONVERT, dl, ReqVT, Res);
3563 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
3564 /// specified intrinsic ID.
3565 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
3566 SelectionDAG &DAG, DebugLoc dl,
3567 MVT DestVT = MVT::Other) {
3568 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
3569 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
3570 DAG.getConstant(IID, MVT::i32), LHS, RHS);
3573 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
3574 /// specified intrinsic ID.
3575 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
3576 SDValue Op2, SelectionDAG &DAG,
3577 DebugLoc dl, MVT DestVT = MVT::Other) {
3578 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
3579 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
3580 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
3584 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
3585 /// amount. The result has the specified value type.
3586 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
3587 MVT VT, SelectionDAG &DAG, DebugLoc dl) {
3588 // Force LHS/RHS to be the right type.
3589 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, LHS);
3590 RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, RHS);
3593 for (unsigned i = 0; i != 16; ++i)
3595 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
3596 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T);
3599 // If this is a case we can't handle, return null and let the default
3600 // expansion code take care of it. If we CAN select this case, and if it
3601 // selects to a single instruction, return Op. Otherwise, if we can codegen
3602 // this case more efficiently than a constant pool load, lower it to the
3603 // sequence of ops that should be used.
3604 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3605 DebugLoc dl = Op.getDebugLoc();
3606 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
3607 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
3609 // Check if this is a splat of a constant value.
3610 APInt APSplatBits, APSplatUndef;
3611 unsigned SplatBitSize;
3613 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
3614 HasAnyUndefs) || SplatBitSize > 32)
3617 unsigned SplatBits = APSplatBits.getZExtValue();
3618 unsigned SplatUndef = APSplatUndef.getZExtValue();
3619 unsigned SplatSize = SplatBitSize / 8;
3621 // First, handle single instruction cases.
3624 if (SplatBits == 0) {
3625 // Canonicalize all zero vectors to be v4i32.
3626 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
3627 SDValue Z = DAG.getConstant(0, MVT::i32);
3628 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
3629 Op = DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Z);
3634 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
3635 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
3637 if (SextVal >= -16 && SextVal <= 15)
3638 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
3641 // Two instruction sequences.
3643 // If this value is in the range [-32,30] and is even, use:
3644 // tmp = VSPLTI[bhw], result = add tmp, tmp
3645 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
3646 SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG, dl);
3647 Res = DAG.getNode(ISD::ADD, dl, Res.getValueType(), Res, Res);
3648 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3651 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
3652 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
3654 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
3655 // Make -1 and vspltisw -1:
3656 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
3658 // Make the VSLW intrinsic, computing 0x8000_0000.
3659 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
3662 // xor by OnesV to invert it.
3663 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
3664 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3667 // Check to see if this is a wide variety of vsplti*, binop self cases.
3668 static const signed char SplatCsts[] = {
3669 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
3670 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
3673 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
3674 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
3675 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
3676 int i = SplatCsts[idx];
3678 // Figure out what shift amount will be used by altivec if shifted by i in
3680 unsigned TypeShiftAmt = i & (SplatBitSize-1);
3682 // vsplti + shl self.
3683 if (SextVal == (i << (int)TypeShiftAmt)) {
3684 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3685 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3686 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
3687 Intrinsic::ppc_altivec_vslw
3689 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3690 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3693 // vsplti + srl self.
3694 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
3695 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3696 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3697 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
3698 Intrinsic::ppc_altivec_vsrw
3700 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3701 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3704 // vsplti + sra self.
3705 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
3706 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3707 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3708 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
3709 Intrinsic::ppc_altivec_vsraw
3711 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3712 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3715 // vsplti + rol self.
3716 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
3717 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
3718 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3719 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3720 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
3721 Intrinsic::ppc_altivec_vrlw
3723 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3724 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3727 // t = vsplti c, result = vsldoi t, t, 1
3728 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
3729 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3730 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
3732 // t = vsplti c, result = vsldoi t, t, 2
3733 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
3734 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3735 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
3737 // t = vsplti c, result = vsldoi t, t, 3
3738 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
3739 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3740 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
3744 // Three instruction sequences.
3746 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
3747 if (SextVal >= 0 && SextVal <= 31) {
3748 SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG, dl);
3749 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
3750 LHS = DAG.getNode(ISD::SUB, dl, LHS.getValueType(), LHS, RHS);
3751 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS);
3753 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
3754 if (SextVal >= -31 && SextVal <= 0) {
3755 SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG, dl);
3756 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
3757 LHS = DAG.getNode(ISD::ADD, dl, LHS.getValueType(), LHS, RHS);
3758 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS);
3764 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
3765 /// the specified operations to build the shuffle.
3766 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
3767 SDValue RHS, SelectionDAG &DAG,
3769 unsigned OpNum = (PFEntry >> 26) & 0x0F;
3770 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
3771 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
3774 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
3786 if (OpNum == OP_COPY) {
3787 if (LHSID == (1*9+2)*9+3) return LHS;
3788 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
3792 SDValue OpLHS, OpRHS;
3793 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
3794 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
3798 default: llvm_unreachable("Unknown i32 permute!");
3800 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
3801 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
3802 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
3803 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
3806 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
3807 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
3808 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
3809 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
3812 for (unsigned i = 0; i != 16; ++i)
3813 ShufIdxs[i] = (i&3)+0;
3816 for (unsigned i = 0; i != 16; ++i)
3817 ShufIdxs[i] = (i&3)+4;
3820 for (unsigned i = 0; i != 16; ++i)
3821 ShufIdxs[i] = (i&3)+8;
3824 for (unsigned i = 0; i != 16; ++i)
3825 ShufIdxs[i] = (i&3)+12;
3828 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
3830 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
3832 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
3834 MVT VT = OpLHS.getValueType();
3835 OpLHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OpLHS);
3836 OpRHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OpRHS);
3837 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
3838 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T);
3841 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
3842 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
3843 /// return the code it can be lowered into. Worst case, it can always be
3844 /// lowered into a vperm.
3845 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
3846 SelectionDAG &DAG) {
3847 DebugLoc dl = Op.getDebugLoc();
3848 SDValue V1 = Op.getOperand(0);
3849 SDValue V2 = Op.getOperand(1);
3850 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
3851 MVT VT = Op.getValueType();
3853 // Cases that are handled by instructions that take permute immediates
3854 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
3855 // selected by the instruction selector.
3856 if (V2.getOpcode() == ISD::UNDEF) {
3857 if (PPC::isSplatShuffleMask(SVOp, 1) ||
3858 PPC::isSplatShuffleMask(SVOp, 2) ||
3859 PPC::isSplatShuffleMask(SVOp, 4) ||
3860 PPC::isVPKUWUMShuffleMask(SVOp, true) ||
3861 PPC::isVPKUHUMShuffleMask(SVOp, true) ||
3862 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 ||
3863 PPC::isVMRGLShuffleMask(SVOp, 1, true) ||
3864 PPC::isVMRGLShuffleMask(SVOp, 2, true) ||
3865 PPC::isVMRGLShuffleMask(SVOp, 4, true) ||
3866 PPC::isVMRGHShuffleMask(SVOp, 1, true) ||
3867 PPC::isVMRGHShuffleMask(SVOp, 2, true) ||
3868 PPC::isVMRGHShuffleMask(SVOp, 4, true)) {
3873 // Altivec has a variety of "shuffle immediates" that take two vector inputs
3874 // and produce a fixed permutation. If any of these match, do not lower to
3876 if (PPC::isVPKUWUMShuffleMask(SVOp, false) ||
3877 PPC::isVPKUHUMShuffleMask(SVOp, false) ||
3878 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 ||
3879 PPC::isVMRGLShuffleMask(SVOp, 1, false) ||
3880 PPC::isVMRGLShuffleMask(SVOp, 2, false) ||
3881 PPC::isVMRGLShuffleMask(SVOp, 4, false) ||
3882 PPC::isVMRGHShuffleMask(SVOp, 1, false) ||
3883 PPC::isVMRGHShuffleMask(SVOp, 2, false) ||
3884 PPC::isVMRGHShuffleMask(SVOp, 4, false))
3887 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
3888 // perfect shuffle table to emit an optimal matching sequence.
3889 SmallVector<int, 16> PermMask;
3890 SVOp->getMask(PermMask);
3892 unsigned PFIndexes[4];
3893 bool isFourElementShuffle = true;
3894 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
3895 unsigned EltNo = 8; // Start out undef.
3896 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
3897 if (PermMask[i*4+j] < 0)
3898 continue; // Undef, ignore it.
3900 unsigned ByteSource = PermMask[i*4+j];
3901 if ((ByteSource & 3) != j) {
3902 isFourElementShuffle = false;
3907 EltNo = ByteSource/4;
3908 } else if (EltNo != ByteSource/4) {
3909 isFourElementShuffle = false;
3913 PFIndexes[i] = EltNo;
3916 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
3917 // perfect shuffle vector to determine if it is cost effective to do this as
3918 // discrete instructions, or whether we should use a vperm.
3919 if (isFourElementShuffle) {
3920 // Compute the index in the perfect shuffle table.
3921 unsigned PFTableIndex =
3922 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3924 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3925 unsigned Cost = (PFEntry >> 30);
3927 // Determining when to avoid vperm is tricky. Many things affect the cost
3928 // of vperm, particularly how many times the perm mask needs to be computed.
3929 // For example, if the perm mask can be hoisted out of a loop or is already
3930 // used (perhaps because there are multiple permutes with the same shuffle
3931 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
3932 // the loop requires an extra register.
3934 // As a compromise, we only emit discrete instructions if the shuffle can be
3935 // generated in 3 or fewer operations. When we have loop information
3936 // available, if this block is within a loop, we should avoid using vperm
3937 // for 3-operation perms and use a constant pool load instead.
3939 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
3942 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
3943 // vector that will get spilled to the constant pool.
3944 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
3946 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
3947 // that it is in input element units, not in bytes. Convert now.
3948 MVT EltVT = V1.getValueType().getVectorElementType();
3949 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
3951 SmallVector<SDValue, 16> ResultMask;
3952 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
3953 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
3955 for (unsigned j = 0; j != BytesPerElement; ++j)
3956 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
3960 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
3961 &ResultMask[0], ResultMask.size());
3962 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
3965 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
3966 /// altivec comparison. If it is, return true and fill in Opc/isDot with
3967 /// information about the intrinsic.
3968 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
3970 unsigned IntrinsicID =
3971 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
3974 switch (IntrinsicID) {
3975 default: return false;
3976 // Comparison predicates.
3977 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
3978 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
3979 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
3980 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
3981 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
3982 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
3983 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
3984 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
3985 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
3986 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
3987 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
3988 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
3989 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
3991 // Normal Comparisons.
3992 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
3993 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
3994 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
3995 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
3996 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
3997 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
3998 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
3999 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
4000 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
4001 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
4002 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
4003 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
4004 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
4009 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
4010 /// lower, do it, otherwise return null.
4011 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
4012 SelectionDAG &DAG) {
4013 // If this is a lowered altivec predicate compare, CompareOpc is set to the
4014 // opcode number of the comparison.
4015 DebugLoc dl = Op.getDebugLoc();
4018 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
4019 return SDValue(); // Don't custom lower most intrinsics.
4021 // If this is a non-dot comparison, make the VCMP node and we are done.
4023 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
4024 Op.getOperand(1), Op.getOperand(2),
4025 DAG.getConstant(CompareOpc, MVT::i32));
4026 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Tmp);
4029 // Create the PPCISD altivec 'dot' comparison node.
4031 Op.getOperand(2), // LHS
4032 Op.getOperand(3), // RHS
4033 DAG.getConstant(CompareOpc, MVT::i32)
4035 std::vector<MVT> VTs;
4036 VTs.push_back(Op.getOperand(2).getValueType());
4037 VTs.push_back(MVT::Flag);
4038 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
4040 // Now that we have the comparison, emit a copy from the CR to a GPR.
4041 // This is flagged to the above dot comparison.
4042 SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32,
4043 DAG.getRegister(PPC::CR6, MVT::i32),
4044 CompNode.getValue(1));
4046 // Unpack the result based on how the target uses it.
4047 unsigned BitNo; // Bit # of CR6.
4048 bool InvertBit; // Invert result?
4049 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
4050 default: // Can't happen, don't crash on invalid number though.
4051 case 0: // Return the value of the EQ bit of CR6.
4052 BitNo = 0; InvertBit = false;
4054 case 1: // Return the inverted value of the EQ bit of CR6.
4055 BitNo = 0; InvertBit = true;
4057 case 2: // Return the value of the LT bit of CR6.
4058 BitNo = 2; InvertBit = false;
4060 case 3: // Return the inverted value of the LT bit of CR6.
4061 BitNo = 2; InvertBit = true;
4065 // Shift the bit into the low position.
4066 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
4067 DAG.getConstant(8-(3-BitNo), MVT::i32));
4069 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
4070 DAG.getConstant(1, MVT::i32));
4072 // If we are supposed to, toggle the bit.
4074 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
4075 DAG.getConstant(1, MVT::i32));
4079 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
4080 SelectionDAG &DAG) {
4081 DebugLoc dl = Op.getDebugLoc();
4082 // Create a stack slot that is 16-byte aligned.
4083 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
4084 int FrameIdx = FrameInfo->CreateStackObject(16, 16);
4085 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4086 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4088 // Store the input value into Value#0 of the stack slot.
4089 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
4090 Op.getOperand(0), FIdx, NULL, 0);
4092 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, NULL, 0);
4095 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) {
4096 DebugLoc dl = Op.getDebugLoc();
4097 if (Op.getValueType() == MVT::v4i32) {
4098 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4100 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
4101 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
4103 SDValue RHSSwap = // = vrlw RHS, 16
4104 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
4106 // Shrinkify inputs to v8i16.
4107 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, LHS);
4108 RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHS);
4109 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHSSwap);
4111 // Low parts multiplied together, generating 32-bit results (we ignore the
4113 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
4114 LHS, RHS, DAG, dl, MVT::v4i32);
4116 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
4117 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
4118 // Shift the high parts up 16 bits.
4119 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
4121 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
4122 } else if (Op.getValueType() == MVT::v8i16) {
4123 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4125 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
4127 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
4128 LHS, RHS, Zero, DAG, dl);
4129 } else if (Op.getValueType() == MVT::v16i8) {
4130 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4132 // Multiply the even 8-bit parts, producing 16-bit sums.
4133 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
4134 LHS, RHS, DAG, dl, MVT::v8i16);
4135 EvenParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, EvenParts);
4137 // Multiply the odd 8-bit parts, producing 16-bit sums.
4138 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
4139 LHS, RHS, DAG, dl, MVT::v8i16);
4140 OddParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OddParts);
4142 // Merge the results together.
4144 for (unsigned i = 0; i != 8; ++i) {
4146 Ops[i*2+1] = 2*i+1+16;
4148 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
4150 llvm_unreachable("Unknown mul to lower!");
4154 /// LowerOperation - Provide custom lowering hooks for some operations.
4156 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
4157 switch (Op.getOpcode()) {
4158 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
4159 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
4160 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
4161 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
4162 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
4163 case ISD::SETCC: return LowerSETCC(Op, DAG);
4164 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
4166 return LowerVASTART(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
4167 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
4170 return LowerVAARG(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
4171 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
4173 case ISD::FORMAL_ARGUMENTS:
4174 if (PPCSubTarget.isSVR4ABI()) {
4175 return LowerFORMAL_ARGUMENTS_SVR4(Op, DAG, VarArgsFrameIndex,
4176 VarArgsStackOffset, VarArgsNumGPR,
4177 VarArgsNumFPR, PPCSubTarget);
4179 return LowerFORMAL_ARGUMENTS_Darwin(Op, DAG, VarArgsFrameIndex,
4184 if (PPCSubTarget.isSVR4ABI()) {
4185 return LowerCALL_SVR4(Op, DAG, PPCSubTarget, getTargetMachine());
4187 return LowerCALL_Darwin(Op, DAG, PPCSubTarget, getTargetMachine());
4190 case ISD::RET: return LowerRET(Op, DAG, getTargetMachine());
4191 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
4192 case ISD::DYNAMIC_STACKALLOC:
4193 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
4195 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
4196 case ISD::FP_TO_UINT:
4197 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
4199 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
4200 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
4202 // Lower 64-bit shifts.
4203 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
4204 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
4205 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
4207 // Vector-related lowering.
4208 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
4209 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
4210 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
4211 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
4212 case ISD::MUL: return LowerMUL(Op, DAG);
4214 // Frame & Return address.
4215 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4216 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
4221 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
4222 SmallVectorImpl<SDValue>&Results,
4223 SelectionDAG &DAG) {
4224 DebugLoc dl = N->getDebugLoc();
4225 switch (N->getOpcode()) {
4227 assert(false && "Do not know how to custom type legalize this operation!");
4229 case ISD::FP_ROUND_INREG: {
4230 assert(N->getValueType(0) == MVT::ppcf128);
4231 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
4232 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
4233 MVT::f64, N->getOperand(0),
4234 DAG.getIntPtrConstant(0));
4235 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
4236 MVT::f64, N->getOperand(0),
4237 DAG.getIntPtrConstant(1));
4239 // This sequence changes FPSCR to do round-to-zero, adds the two halves
4240 // of the long double, and puts FPSCR back the way it was. We do not
4241 // actually model FPSCR.
4242 std::vector<MVT> NodeTys;
4243 SDValue Ops[4], Result, MFFSreg, InFlag, FPreg;
4245 NodeTys.push_back(MVT::f64); // Return register
4246 NodeTys.push_back(MVT::Flag); // Returns a flag for later insns
4247 Result = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
4248 MFFSreg = Result.getValue(0);
4249 InFlag = Result.getValue(1);
4252 NodeTys.push_back(MVT::Flag); // Returns a flag
4253 Ops[0] = DAG.getConstant(31, MVT::i32);
4255 Result = DAG.getNode(PPCISD::MTFSB1, dl, NodeTys, Ops, 2);
4256 InFlag = Result.getValue(0);
4259 NodeTys.push_back(MVT::Flag); // Returns a flag
4260 Ops[0] = DAG.getConstant(30, MVT::i32);
4262 Result = DAG.getNode(PPCISD::MTFSB0, dl, NodeTys, Ops, 2);
4263 InFlag = Result.getValue(0);
4266 NodeTys.push_back(MVT::f64); // result of add
4267 NodeTys.push_back(MVT::Flag); // Returns a flag
4271 Result = DAG.getNode(PPCISD::FADDRTZ, dl, NodeTys, Ops, 3);
4272 FPreg = Result.getValue(0);
4273 InFlag = Result.getValue(1);
4276 NodeTys.push_back(MVT::f64);
4277 Ops[0] = DAG.getConstant(1, MVT::i32);
4281 Result = DAG.getNode(PPCISD::MTFSF, dl, NodeTys, Ops, 4);
4282 FPreg = Result.getValue(0);
4284 // We know the low half is about to be thrown away, so just use something
4286 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
4290 case ISD::FP_TO_SINT:
4291 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
4297 //===----------------------------------------------------------------------===//
4298 // Other Lowering Code
4299 //===----------------------------------------------------------------------===//
4302 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
4303 bool is64bit, unsigned BinOpcode) const {
4304 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4305 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4307 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4308 MachineFunction *F = BB->getParent();
4309 MachineFunction::iterator It = BB;
4312 unsigned dest = MI->getOperand(0).getReg();
4313 unsigned ptrA = MI->getOperand(1).getReg();
4314 unsigned ptrB = MI->getOperand(2).getReg();
4315 unsigned incr = MI->getOperand(3).getReg();
4316 DebugLoc dl = MI->getDebugLoc();
4318 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
4319 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4320 F->insert(It, loopMBB);
4321 F->insert(It, exitMBB);
4322 exitMBB->transferSuccessors(BB);
4324 MachineRegisterInfo &RegInfo = F->getRegInfo();
4325 unsigned TmpReg = (!BinOpcode) ? incr :
4326 RegInfo.createVirtualRegister(
4327 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4328 (const TargetRegisterClass *) &PPC::GPRCRegClass);
4332 // fallthrough --> loopMBB
4333 BB->addSuccessor(loopMBB);
4336 // l[wd]arx dest, ptr
4337 // add r0, dest, incr
4338 // st[wd]cx. r0, ptr
4340 // fallthrough --> exitMBB
4342 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
4343 .addReg(ptrA).addReg(ptrB);
4345 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
4346 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4347 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
4348 BuildMI(BB, dl, TII->get(PPC::BCC))
4349 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
4350 BB->addSuccessor(loopMBB);
4351 BB->addSuccessor(exitMBB);
4360 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
4361 MachineBasicBlock *BB,
4362 bool is8bit, // operation
4363 unsigned BinOpcode) const {
4364 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4365 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4366 // In 64 bit mode we have to use 64 bits for addresses, even though the
4367 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
4368 // registers without caring whether they're 32 or 64, but here we're
4369 // doing actual arithmetic on the addresses.
4370 bool is64bit = PPCSubTarget.isPPC64();
4372 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4373 MachineFunction *F = BB->getParent();
4374 MachineFunction::iterator It = BB;
4377 unsigned dest = MI->getOperand(0).getReg();
4378 unsigned ptrA = MI->getOperand(1).getReg();
4379 unsigned ptrB = MI->getOperand(2).getReg();
4380 unsigned incr = MI->getOperand(3).getReg();
4381 DebugLoc dl = MI->getDebugLoc();
4383 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
4384 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4385 F->insert(It, loopMBB);
4386 F->insert(It, exitMBB);
4387 exitMBB->transferSuccessors(BB);
4389 MachineRegisterInfo &RegInfo = F->getRegInfo();
4390 const TargetRegisterClass *RC =
4391 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4392 (const TargetRegisterClass *) &PPC::GPRCRegClass;
4393 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
4394 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
4395 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
4396 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
4397 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
4398 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
4399 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
4400 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
4401 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
4402 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
4403 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
4405 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
4409 // fallthrough --> loopMBB
4410 BB->addSuccessor(loopMBB);
4412 // The 4-byte load must be aligned, while a char or short may be
4413 // anywhere in the word. Hence all this nasty bookkeeping code.
4414 // add ptr1, ptrA, ptrB [copy if ptrA==0]
4415 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
4416 // xori shift, shift1, 24 [16]
4417 // rlwinm ptr, ptr1, 0, 0, 29
4418 // slw incr2, incr, shift
4419 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
4420 // slw mask, mask2, shift
4422 // lwarx tmpDest, ptr
4423 // add tmp, tmpDest, incr2
4424 // andc tmp2, tmpDest, mask
4425 // and tmp3, tmp, mask
4426 // or tmp4, tmp3, tmp2
4429 // fallthrough --> exitMBB
4430 // srw dest, tmpDest, shift
4432 if (ptrA!=PPC::R0) {
4433 Ptr1Reg = RegInfo.createVirtualRegister(RC);
4434 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
4435 .addReg(ptrA).addReg(ptrB);
4439 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
4440 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
4441 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
4442 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
4444 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
4445 .addReg(Ptr1Reg).addImm(0).addImm(61);
4447 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
4448 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
4449 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
4450 .addReg(incr).addReg(ShiftReg);
4452 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
4454 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
4455 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
4457 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
4458 .addReg(Mask2Reg).addReg(ShiftReg);
4461 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
4462 .addReg(PPC::R0).addReg(PtrReg);
4464 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
4465 .addReg(Incr2Reg).addReg(TmpDestReg);
4466 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
4467 .addReg(TmpDestReg).addReg(MaskReg);
4468 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
4469 .addReg(TmpReg).addReg(MaskReg);
4470 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
4471 .addReg(Tmp3Reg).addReg(Tmp2Reg);
4472 BuildMI(BB, dl, TII->get(PPC::STWCX))
4473 .addReg(Tmp4Reg).addReg(PPC::R0).addReg(PtrReg);
4474 BuildMI(BB, dl, TII->get(PPC::BCC))
4475 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
4476 BB->addSuccessor(loopMBB);
4477 BB->addSuccessor(exitMBB);
4482 BuildMI(BB, dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg).addReg(ShiftReg);
4487 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4488 MachineBasicBlock *BB) const {
4489 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4491 // To "insert" these instructions we actually have to insert their
4492 // control-flow patterns.
4493 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4494 MachineFunction::iterator It = BB;
4497 MachineFunction *F = BB->getParent();
4499 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
4500 MI->getOpcode() == PPC::SELECT_CC_I8 ||
4501 MI->getOpcode() == PPC::SELECT_CC_F4 ||
4502 MI->getOpcode() == PPC::SELECT_CC_F8 ||
4503 MI->getOpcode() == PPC::SELECT_CC_VRRC) {
4505 // The incoming instruction knows the destination vreg to set, the
4506 // condition code register to branch on, the true/false values to
4507 // select between, and a branch opcode to use.
4512 // cmpTY ccX, r1, r2
4514 // fallthrough --> copy0MBB
4515 MachineBasicBlock *thisMBB = BB;
4516 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4517 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4518 unsigned SelectPred = MI->getOperand(4).getImm();
4519 DebugLoc dl = MI->getDebugLoc();
4520 BuildMI(BB, dl, TII->get(PPC::BCC))
4521 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
4522 F->insert(It, copy0MBB);
4523 F->insert(It, sinkMBB);
4524 // Update machine-CFG edges by transferring all successors of the current
4525 // block to the new block which will contain the Phi node for the select.
4526 sinkMBB->transferSuccessors(BB);
4527 // Next, add the true and fallthrough blocks as its successors.
4528 BB->addSuccessor(copy0MBB);
4529 BB->addSuccessor(sinkMBB);
4532 // %FalseValue = ...
4533 // # fallthrough to sinkMBB
4536 // Update machine-CFG edges
4537 BB->addSuccessor(sinkMBB);
4540 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4543 BuildMI(BB, dl, TII->get(PPC::PHI), MI->getOperand(0).getReg())
4544 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
4545 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4547 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
4548 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
4549 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
4550 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
4551 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
4552 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
4553 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
4554 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
4556 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
4557 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
4558 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
4559 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
4560 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
4561 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
4562 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
4563 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
4565 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
4566 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
4567 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
4568 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
4569 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
4570 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
4571 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
4572 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
4574 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
4575 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
4576 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
4577 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
4578 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
4579 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
4580 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
4581 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
4583 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
4584 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
4585 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
4586 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
4587 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
4588 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
4589 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
4590 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
4592 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
4593 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
4594 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
4595 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
4596 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
4597 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
4598 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
4599 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
4601 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
4602 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
4603 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
4604 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
4605 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
4606 BB = EmitAtomicBinary(MI, BB, false, 0);
4607 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
4608 BB = EmitAtomicBinary(MI, BB, true, 0);
4610 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
4611 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
4612 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
4614 unsigned dest = MI->getOperand(0).getReg();
4615 unsigned ptrA = MI->getOperand(1).getReg();
4616 unsigned ptrB = MI->getOperand(2).getReg();
4617 unsigned oldval = MI->getOperand(3).getReg();
4618 unsigned newval = MI->getOperand(4).getReg();
4619 DebugLoc dl = MI->getDebugLoc();
4621 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
4622 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
4623 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
4624 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4625 F->insert(It, loop1MBB);
4626 F->insert(It, loop2MBB);
4627 F->insert(It, midMBB);
4628 F->insert(It, exitMBB);
4629 exitMBB->transferSuccessors(BB);
4633 // fallthrough --> loopMBB
4634 BB->addSuccessor(loop1MBB);
4637 // l[wd]arx dest, ptr
4638 // cmp[wd] dest, oldval
4641 // st[wd]cx. newval, ptr
4645 // st[wd]cx. dest, ptr
4648 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
4649 .addReg(ptrA).addReg(ptrB);
4650 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
4651 .addReg(oldval).addReg(dest);
4652 BuildMI(BB, dl, TII->get(PPC::BCC))
4653 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
4654 BB->addSuccessor(loop2MBB);
4655 BB->addSuccessor(midMBB);
4658 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4659 .addReg(newval).addReg(ptrA).addReg(ptrB);
4660 BuildMI(BB, dl, TII->get(PPC::BCC))
4661 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
4662 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
4663 BB->addSuccessor(loop1MBB);
4664 BB->addSuccessor(exitMBB);
4667 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4668 .addReg(dest).addReg(ptrA).addReg(ptrB);
4669 BB->addSuccessor(exitMBB);
4674 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
4675 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
4676 // We must use 64-bit registers for addresses when targeting 64-bit,
4677 // since we're actually doing arithmetic on them. Other registers
4679 bool is64bit = PPCSubTarget.isPPC64();
4680 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
4682 unsigned dest = MI->getOperand(0).getReg();
4683 unsigned ptrA = MI->getOperand(1).getReg();
4684 unsigned ptrB = MI->getOperand(2).getReg();
4685 unsigned oldval = MI->getOperand(3).getReg();
4686 unsigned newval = MI->getOperand(4).getReg();
4687 DebugLoc dl = MI->getDebugLoc();
4689 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
4690 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
4691 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
4692 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4693 F->insert(It, loop1MBB);
4694 F->insert(It, loop2MBB);
4695 F->insert(It, midMBB);
4696 F->insert(It, exitMBB);
4697 exitMBB->transferSuccessors(BB);
4699 MachineRegisterInfo &RegInfo = F->getRegInfo();
4700 const TargetRegisterClass *RC =
4701 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4702 (const TargetRegisterClass *) &PPC::GPRCRegClass;
4703 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
4704 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
4705 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
4706 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
4707 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
4708 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
4709 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
4710 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
4711 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
4712 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
4713 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
4714 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
4715 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
4717 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
4720 // fallthrough --> loopMBB
4721 BB->addSuccessor(loop1MBB);
4723 // The 4-byte load must be aligned, while a char or short may be
4724 // anywhere in the word. Hence all this nasty bookkeeping code.
4725 // add ptr1, ptrA, ptrB [copy if ptrA==0]
4726 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
4727 // xori shift, shift1, 24 [16]
4728 // rlwinm ptr, ptr1, 0, 0, 29
4729 // slw newval2, newval, shift
4730 // slw oldval2, oldval,shift
4731 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
4732 // slw mask, mask2, shift
4733 // and newval3, newval2, mask
4734 // and oldval3, oldval2, mask
4736 // lwarx tmpDest, ptr
4737 // and tmp, tmpDest, mask
4738 // cmpw tmp, oldval3
4741 // andc tmp2, tmpDest, mask
4742 // or tmp4, tmp2, newval3
4747 // stwcx. tmpDest, ptr
4749 // srw dest, tmpDest, shift
4750 if (ptrA!=PPC::R0) {
4751 Ptr1Reg = RegInfo.createVirtualRegister(RC);
4752 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
4753 .addReg(ptrA).addReg(ptrB);
4757 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
4758 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
4759 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
4760 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
4762 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
4763 .addReg(Ptr1Reg).addImm(0).addImm(61);
4765 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
4766 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
4767 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
4768 .addReg(newval).addReg(ShiftReg);
4769 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
4770 .addReg(oldval).addReg(ShiftReg);
4772 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
4774 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
4775 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
4776 .addReg(Mask3Reg).addImm(65535);
4778 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
4779 .addReg(Mask2Reg).addReg(ShiftReg);
4780 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
4781 .addReg(NewVal2Reg).addReg(MaskReg);
4782 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
4783 .addReg(OldVal2Reg).addReg(MaskReg);
4786 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
4787 .addReg(PPC::R0).addReg(PtrReg);
4788 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
4789 .addReg(TmpDestReg).addReg(MaskReg);
4790 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
4791 .addReg(TmpReg).addReg(OldVal3Reg);
4792 BuildMI(BB, dl, TII->get(PPC::BCC))
4793 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
4794 BB->addSuccessor(loop2MBB);
4795 BB->addSuccessor(midMBB);
4798 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
4799 .addReg(TmpDestReg).addReg(MaskReg);
4800 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
4801 .addReg(Tmp2Reg).addReg(NewVal3Reg);
4802 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
4803 .addReg(PPC::R0).addReg(PtrReg);
4804 BuildMI(BB, dl, TII->get(PPC::BCC))
4805 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
4806 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
4807 BB->addSuccessor(loop1MBB);
4808 BB->addSuccessor(exitMBB);
4811 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
4812 .addReg(PPC::R0).addReg(PtrReg);
4813 BB->addSuccessor(exitMBB);
4818 BuildMI(BB, dl, TII->get(PPC::SRW),dest).addReg(TmpReg).addReg(ShiftReg);
4820 llvm_unreachable("Unexpected instr type to insert");
4823 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
4827 //===----------------------------------------------------------------------===//
4828 // Target Optimization Hooks
4829 //===----------------------------------------------------------------------===//
4831 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
4832 DAGCombinerInfo &DCI) const {
4833 TargetMachine &TM = getTargetMachine();
4834 SelectionDAG &DAG = DCI.DAG;
4835 DebugLoc dl = N->getDebugLoc();
4836 switch (N->getOpcode()) {
4839 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
4840 if (C->getZExtValue() == 0) // 0 << V -> 0.
4841 return N->getOperand(0);
4845 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
4846 if (C->getZExtValue() == 0) // 0 >>u V -> 0.
4847 return N->getOperand(0);
4851 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
4852 if (C->getZExtValue() == 0 || // 0 >>s V -> 0.
4853 C->isAllOnesValue()) // -1 >>s V -> -1.
4854 return N->getOperand(0);
4858 case ISD::SINT_TO_FP:
4859 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
4860 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
4861 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
4862 // We allow the src/dst to be either f32/f64, but the intermediate
4863 // type must be i64.
4864 if (N->getOperand(0).getValueType() == MVT::i64 &&
4865 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
4866 SDValue Val = N->getOperand(0).getOperand(0);
4867 if (Val.getValueType() == MVT::f32) {
4868 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
4869 DCI.AddToWorklist(Val.getNode());
4872 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
4873 DCI.AddToWorklist(Val.getNode());
4874 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
4875 DCI.AddToWorklist(Val.getNode());
4876 if (N->getValueType(0) == MVT::f32) {
4877 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
4878 DAG.getIntPtrConstant(0));
4879 DCI.AddToWorklist(Val.getNode());
4882 } else if (N->getOperand(0).getValueType() == MVT::i32) {
4883 // If the intermediate type is i32, we can avoid the load/store here
4890 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
4891 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
4892 !cast<StoreSDNode>(N)->isTruncatingStore() &&
4893 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
4894 N->getOperand(1).getValueType() == MVT::i32 &&
4895 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
4896 SDValue Val = N->getOperand(1).getOperand(0);
4897 if (Val.getValueType() == MVT::f32) {
4898 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
4899 DCI.AddToWorklist(Val.getNode());
4901 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
4902 DCI.AddToWorklist(Val.getNode());
4904 Val = DAG.getNode(PPCISD::STFIWX, dl, MVT::Other, N->getOperand(0), Val,
4905 N->getOperand(2), N->getOperand(3));
4906 DCI.AddToWorklist(Val.getNode());
4910 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
4911 if (N->getOperand(1).getOpcode() == ISD::BSWAP &&
4912 N->getOperand(1).getNode()->hasOneUse() &&
4913 (N->getOperand(1).getValueType() == MVT::i32 ||
4914 N->getOperand(1).getValueType() == MVT::i16)) {
4915 SDValue BSwapOp = N->getOperand(1).getOperand(0);
4916 // Do an any-extend to 32-bits if this is a half-word input.
4917 if (BSwapOp.getValueType() == MVT::i16)
4918 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
4920 return DAG.getNode(PPCISD::STBRX, dl, MVT::Other, N->getOperand(0),
4921 BSwapOp, N->getOperand(2), N->getOperand(3),
4922 DAG.getValueType(N->getOperand(1).getValueType()));
4926 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
4927 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
4928 N->getOperand(0).hasOneUse() &&
4929 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
4930 SDValue Load = N->getOperand(0);
4931 LoadSDNode *LD = cast<LoadSDNode>(Load);
4932 // Create the byte-swapping load.
4933 std::vector<MVT> VTs;
4934 VTs.push_back(MVT::i32);
4935 VTs.push_back(MVT::Other);
4936 SDValue MO = DAG.getMemOperand(LD->getMemOperand());
4938 LD->getChain(), // Chain
4939 LD->getBasePtr(), // Ptr
4941 DAG.getValueType(N->getValueType(0)) // VT
4943 SDValue BSLoad = DAG.getNode(PPCISD::LBRX, dl, VTs, Ops, 4);
4945 // If this is an i16 load, insert the truncate.
4946 SDValue ResVal = BSLoad;
4947 if (N->getValueType(0) == MVT::i16)
4948 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
4950 // First, combine the bswap away. This makes the value produced by the
4952 DCI.CombineTo(N, ResVal);
4954 // Next, combine the load away, we give it a bogus result value but a real
4955 // chain result. The result value is dead because the bswap is dead.
4956 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
4958 // Return N so it doesn't get rechecked!
4959 return SDValue(N, 0);
4963 case PPCISD::VCMP: {
4964 // If a VCMPo node already exists with exactly the same operands as this
4965 // node, use its result instead of this node (VCMPo computes both a CR6 and
4966 // a normal output).
4968 if (!N->getOperand(0).hasOneUse() &&
4969 !N->getOperand(1).hasOneUse() &&
4970 !N->getOperand(2).hasOneUse()) {
4972 // Scan all of the users of the LHS, looking for VCMPo's that match.
4973 SDNode *VCMPoNode = 0;
4975 SDNode *LHSN = N->getOperand(0).getNode();
4976 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
4978 if (UI->getOpcode() == PPCISD::VCMPo &&
4979 UI->getOperand(1) == N->getOperand(1) &&
4980 UI->getOperand(2) == N->getOperand(2) &&
4981 UI->getOperand(0) == N->getOperand(0)) {
4986 // If there is no VCMPo node, or if the flag value has a single use, don't
4988 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
4991 // Look at the (necessarily single) use of the flag value. If it has a
4992 // chain, this transformation is more complex. Note that multiple things
4993 // could use the value result, which we should ignore.
4994 SDNode *FlagUser = 0;
4995 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
4996 FlagUser == 0; ++UI) {
4997 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
4999 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
5000 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
5007 // If the user is a MFCR instruction, we know this is safe. Otherwise we
5008 // give up for right now.
5009 if (FlagUser->getOpcode() == PPCISD::MFCR)
5010 return SDValue(VCMPoNode, 0);
5015 // If this is a branch on an altivec predicate comparison, lower this so
5016 // that we don't have to do a MFCR: instead, branch directly on CR6. This
5017 // lowering is done pre-legalize, because the legalizer lowers the predicate
5018 // compare down to code that is difficult to reassemble.
5019 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
5020 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
5024 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
5025 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
5026 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
5027 assert(isDot && "Can't compare against a vector result!");
5029 // If this is a comparison against something other than 0/1, then we know
5030 // that the condition is never/always true.
5031 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
5032 if (Val != 0 && Val != 1) {
5033 if (CC == ISD::SETEQ) // Cond never true, remove branch.
5034 return N->getOperand(0);
5035 // Always !=, turn it into an unconditional branch.
5036 return DAG.getNode(ISD::BR, dl, MVT::Other,
5037 N->getOperand(0), N->getOperand(4));
5040 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
5042 // Create the PPCISD altivec 'dot' comparison node.
5043 std::vector<MVT> VTs;
5045 LHS.getOperand(2), // LHS of compare
5046 LHS.getOperand(3), // RHS of compare
5047 DAG.getConstant(CompareOpc, MVT::i32)
5049 VTs.push_back(LHS.getOperand(2).getValueType());
5050 VTs.push_back(MVT::Flag);
5051 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
5053 // Unpack the result based on how the target uses it.
5054 PPC::Predicate CompOpc;
5055 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
5056 default: // Can't happen, don't crash on invalid number though.
5057 case 0: // Branch on the value of the EQ bit of CR6.
5058 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
5060 case 1: // Branch on the inverted value of the EQ bit of CR6.
5061 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
5063 case 2: // Branch on the value of the LT bit of CR6.
5064 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
5066 case 3: // Branch on the inverted value of the LT bit of CR6.
5067 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
5071 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
5072 DAG.getConstant(CompOpc, MVT::i32),
5073 DAG.getRegister(PPC::CR6, MVT::i32),
5074 N->getOperand(4), CompNode.getValue(1));
5083 //===----------------------------------------------------------------------===//
5084 // Inline Assembly Support
5085 //===----------------------------------------------------------------------===//
5087 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
5091 const SelectionDAG &DAG,
5092 unsigned Depth) const {
5093 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
5094 switch (Op.getOpcode()) {
5096 case PPCISD::LBRX: {
5097 // lhbrx is known to have the top bits cleared out.
5098 if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16)
5099 KnownZero = 0xFFFF0000;
5102 case ISD::INTRINSIC_WO_CHAIN: {
5103 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
5105 case Intrinsic::ppc_altivec_vcmpbfp_p:
5106 case Intrinsic::ppc_altivec_vcmpeqfp_p:
5107 case Intrinsic::ppc_altivec_vcmpequb_p:
5108 case Intrinsic::ppc_altivec_vcmpequh_p:
5109 case Intrinsic::ppc_altivec_vcmpequw_p:
5110 case Intrinsic::ppc_altivec_vcmpgefp_p:
5111 case Intrinsic::ppc_altivec_vcmpgtfp_p:
5112 case Intrinsic::ppc_altivec_vcmpgtsb_p:
5113 case Intrinsic::ppc_altivec_vcmpgtsh_p:
5114 case Intrinsic::ppc_altivec_vcmpgtsw_p:
5115 case Intrinsic::ppc_altivec_vcmpgtub_p:
5116 case Intrinsic::ppc_altivec_vcmpgtuh_p:
5117 case Intrinsic::ppc_altivec_vcmpgtuw_p:
5118 KnownZero = ~1U; // All bits but the low one are known to be zero.
5126 /// getConstraintType - Given a constraint, return the type of
5127 /// constraint it is for this target.
5128 PPCTargetLowering::ConstraintType
5129 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
5130 if (Constraint.size() == 1) {
5131 switch (Constraint[0]) {
5138 return C_RegisterClass;
5141 return TargetLowering::getConstraintType(Constraint);
5144 std::pair<unsigned, const TargetRegisterClass*>
5145 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
5147 if (Constraint.size() == 1) {
5148 // GCC RS6000 Constraint Letters
5149 switch (Constraint[0]) {
5152 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
5153 return std::make_pair(0U, PPC::G8RCRegisterClass);
5154 return std::make_pair(0U, PPC::GPRCRegisterClass);
5157 return std::make_pair(0U, PPC::F4RCRegisterClass);
5158 else if (VT == MVT::f64)
5159 return std::make_pair(0U, PPC::F8RCRegisterClass);
5162 return std::make_pair(0U, PPC::VRRCRegisterClass);
5164 return std::make_pair(0U, PPC::CRRCRegisterClass);
5168 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
5172 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
5173 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is true
5174 /// it means one of the asm constraint of the inline asm instruction being
5175 /// processed is 'm'.
5176 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, char Letter,
5178 std::vector<SDValue>&Ops,
5179 SelectionDAG &DAG) const {
5180 SDValue Result(0,0);
5191 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
5192 if (!CST) return; // Must be an immediate to match.
5193 unsigned Value = CST->getZExtValue();
5195 default: llvm_unreachable("Unknown constraint letter!");
5196 case 'I': // "I" is a signed 16-bit constant.
5197 if ((short)Value == (int)Value)
5198 Result = DAG.getTargetConstant(Value, Op.getValueType());
5200 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
5201 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
5202 if ((short)Value == 0)
5203 Result = DAG.getTargetConstant(Value, Op.getValueType());
5205 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
5206 if ((Value >> 16) == 0)
5207 Result = DAG.getTargetConstant(Value, Op.getValueType());
5209 case 'M': // "M" is a constant that is greater than 31.
5211 Result = DAG.getTargetConstant(Value, Op.getValueType());
5213 case 'N': // "N" is a positive constant that is an exact power of two.
5214 if ((int)Value > 0 && isPowerOf2_32(Value))
5215 Result = DAG.getTargetConstant(Value, Op.getValueType());
5217 case 'O': // "O" is the constant zero.
5219 Result = DAG.getTargetConstant(Value, Op.getValueType());
5221 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
5222 if ((short)-Value == (int)-Value)
5223 Result = DAG.getTargetConstant(Value, Op.getValueType());
5230 if (Result.getNode()) {
5231 Ops.push_back(Result);
5235 // Handle standard constraint letters.
5236 TargetLowering::LowerAsmOperandForConstraint(Op, Letter, hasMemory, Ops, DAG);
5239 // isLegalAddressingMode - Return true if the addressing mode represented
5240 // by AM is legal for this target, for a load/store of the specified type.
5241 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
5242 const Type *Ty) const {
5243 // FIXME: PPC does not allow r+i addressing modes for vectors!
5245 // PPC allows a sign-extended 16-bit immediate field.
5246 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
5249 // No global is ever allowed as a base.
5253 // PPC only support r+r,
5255 case 0: // "r+i" or just "i", depending on HasBaseReg.
5258 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
5260 // Otherwise we have r+r or r+i.
5263 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
5265 // Allow 2*r as r+r.
5268 // No other scales are supported.
5275 /// isLegalAddressImmediate - Return true if the integer value can be used
5276 /// as the offset of the target addressing mode for load / store of the
5278 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{
5279 // PPC allows a sign-extended 16-bit immediate field.
5280 return (V > -(1 << 16) && V < (1 << 16)-1);
5283 bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
5287 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
5288 DebugLoc dl = Op.getDebugLoc();
5289 // Depths > 0 not supported yet!
5290 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
5293 MachineFunction &MF = DAG.getMachineFunction();
5294 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
5296 // Just load the return address off the stack.
5297 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
5299 // Make sure the function really does not optimize away the store of the RA
5301 FuncInfo->setLRStoreRequired();
5302 return DAG.getLoad(getPointerTy(), dl,
5303 DAG.getEntryNode(), RetAddrFI, NULL, 0);
5306 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
5307 DebugLoc dl = Op.getDebugLoc();
5308 // Depths > 0 not supported yet!
5309 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
5312 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5313 bool isPPC64 = PtrVT == MVT::i64;
5315 MachineFunction &MF = DAG.getMachineFunction();
5316 MachineFrameInfo *MFI = MF.getFrameInfo();
5317 bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects())
5318 && MFI->getStackSize();
5321 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, is31 ? PPC::X31 : PPC::X1,
5324 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, is31 ? PPC::R31 : PPC::R1,
5329 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
5330 // The PowerPC target isn't yet aware of offsets.
5334 MVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
5335 bool isSrcConst, bool isSrcStr,
5336 SelectionDAG &DAG) const {
5337 if (this->PPCSubTarget.isPPC64()) {