1 //===-- PPC32ISelLowering.cpp - PPC32 DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPC32ISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPC32ISelLowering.h"
15 #include "PPC32TargetMachine.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/SelectionDAG.h"
19 #include "llvm/Function.h"
22 PPC32TargetLowering::PPC32TargetLowering(TargetMachine &TM)
23 : TargetLowering(TM) {
25 // Fold away setcc operations if possible.
26 setSetCCIsExpensive();
28 // Set up the register classes.
29 addRegisterClass(MVT::i32, PPC32::GPRCRegisterClass);
30 addRegisterClass(MVT::f32, PPC32::FPRCRegisterClass);
31 addRegisterClass(MVT::f64, PPC32::FPRCRegisterClass);
33 // PowerPC has no intrinsics for these particular operations
34 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
35 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
36 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
38 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
39 setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
40 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
42 // PowerPC has no SREM/UREM instructions
43 setOperationAction(ISD::SREM, MVT::i32, Expand);
44 setOperationAction(ISD::UREM, MVT::i32, Expand);
46 // We don't support sin/cos/sqrt/fmod
47 setOperationAction(ISD::FSIN , MVT::f64, Expand);
48 setOperationAction(ISD::FCOS , MVT::f64, Expand);
49 setOperationAction(ISD::SREM , MVT::f64, Expand);
50 setOperationAction(ISD::FSIN , MVT::f32, Expand);
51 setOperationAction(ISD::FCOS , MVT::f32, Expand);
52 setOperationAction(ISD::SREM , MVT::f32, Expand);
54 // If we're enabling GP optimizations, use hardware square root
55 if (!TM.getSubtarget<PPCSubtarget>().isGigaProcessor()) {
56 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
57 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
60 // PowerPC does not have CTPOP or CTTZ
61 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
62 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
64 // PowerPC does not have Select
65 setOperationAction(ISD::SELECT, MVT::i32, Expand);
66 setOperationAction(ISD::SELECT, MVT::f32, Expand);
67 setOperationAction(ISD::SELECT, MVT::f64, Expand);
69 // PowerPC does not have BRCOND* which requires SetCC
70 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
71 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
73 // PowerPC does not have FP_TO_UINT
74 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
76 // PowerPC does not have [U|S]INT_TO_FP
77 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
78 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
80 setSetCCResultContents(ZeroOrOneSetCCResult);
81 addLegalFPImmediate(+0.0); // Necessary for FSEL
82 addLegalFPImmediate(-0.0); //
84 computeRegisterProperties();
87 std::vector<SDOperand>
88 PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
90 // add beautiful description of PPC stack frame format, or at least some docs
92 MachineFunction &MF = DAG.getMachineFunction();
93 MachineFrameInfo *MFI = MF.getFrameInfo();
94 MachineBasicBlock& BB = MF.front();
95 std::vector<SDOperand> ArgValues;
97 // Due to the rather complicated nature of the PowerPC ABI, rather than a
98 // fixed size array of physical args, for the sake of simplicity let the STL
99 // handle tracking them for us.
100 std::vector<unsigned> argVR, argPR, argOp;
101 unsigned ArgOffset = 24;
102 unsigned GPR_remaining = 8;
103 unsigned FPR_remaining = 13;
104 unsigned GPR_idx = 0, FPR_idx = 0;
105 static const unsigned GPR[] = {
106 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
107 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
109 static const unsigned FPR[] = {
110 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
111 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
114 // Add DAG nodes to load the arguments... On entry to a function on PPC,
115 // the arguments start at offset 24, although they are likely to be passed
117 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
118 SDOperand newroot, argt;
120 bool needsLoad = false;
121 bool ArgLive = !I->use_empty();
122 MVT::ValueType ObjectVT = getValueType(I->getType());
125 default: assert(0 && "Unhandled argument type!");
132 if (GPR_remaining > 0) {
133 MF.addLiveIn(GPR[GPR_idx]);
134 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(),
135 GPR[GPR_idx], MVT::i32);
136 if (ObjectVT != MVT::i32)
137 argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, newroot);
142 case MVT::i64: ObjSize = 8;
144 if (GPR_remaining > 0) {
145 SDOperand argHi, argLo;
146 MF.addLiveIn(GPR[GPR_idx]);
147 argHi = DAG.getCopyFromReg(DAG.getRoot(), GPR[GPR_idx], MVT::i32);
148 // If we have two or more remaining argument registers, then both halves
149 // of the i64 can be sourced from there. Otherwise, the lower half will
150 // have to come off the stack. This can happen when an i64 is preceded
151 // by 28 bytes of arguments.
152 if (GPR_remaining > 1) {
153 MF.addLiveIn(GPR[GPR_idx+1]);
154 argLo = DAG.getCopyFromReg(argHi, GPR[GPR_idx+1], MVT::i32);
156 int FI = MFI->CreateFixedObject(4, ArgOffset+4);
157 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
158 argLo = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
159 DAG.getSrcValue(NULL));
161 // Build the outgoing arg thingy
162 argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi);
170 ObjSize = (ObjectVT == MVT::f64) ? 8 : 4;
172 if (FPR_remaining > 0) {
173 MF.addLiveIn(FPR[FPR_idx]);
174 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(),
175 FPR[FPR_idx], ObjectVT);
184 // We need to load the argument to a virtual register if we determined above
185 // that we ran out of physical registers of the appropriate type
187 unsigned SubregOffset = 0;
188 if (ObjectVT == MVT::i8 || ObjectVT == MVT::i1) SubregOffset = 3;
189 if (ObjectVT == MVT::i16) SubregOffset = 2;
190 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
191 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
192 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN,
193 DAG.getConstant(SubregOffset, MVT::i32));
194 argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
195 DAG.getSrcValue(NULL));
198 // Every 4 bytes of argument space consumes one of the GPRs available for
200 if (GPR_remaining > 0) {
201 unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1;
202 GPR_remaining -= delta;
205 ArgOffset += ObjSize;
207 DAG.setRoot(newroot.getValue(1));
209 ArgValues.push_back(argt);
212 // If the function takes variable number of arguments, make a frame index for
213 // the start of the first vararg value... for expansion of llvm.va_start.
215 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
216 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
217 // If this function is vararg, store any remaining integer argument regs
218 // to their spots on the stack so that they may be loaded by deferencing the
219 // result of va_next.
220 std::vector<SDOperand> MemOps;
221 for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) {
222 MF.addLiveIn(GPR[GPR_idx]);
223 SDOperand Val = DAG.getCopyFromReg(DAG.getRoot(), GPR[GPR_idx], MVT::i32);
224 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
225 Val, FIN, DAG.getSrcValue(NULL));
226 MemOps.push_back(Store);
227 // Increment the address by four for the next argument to store
228 SDOperand PtrOff = DAG.getConstant(4, getPointerTy());
229 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, PtrOff);
231 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps));
234 // Finally, inform the code generator which regs we return values in.
235 switch (getValueType(F.getReturnType())) {
236 default: assert(0 && "Unknown type!");
237 case MVT::isVoid: break;
242 MF.addLiveOut(PPC::R3);
245 MF.addLiveOut(PPC::R3);
246 MF.addLiveOut(PPC::R4);
250 MF.addLiveOut(PPC::F1);
257 std::pair<SDOperand, SDOperand>
258 PPC32TargetLowering::LowerCallTo(SDOperand Chain,
259 const Type *RetTy, bool isVarArg,
260 unsigned CallingConv, bool isTailCall,
261 SDOperand Callee, ArgListTy &Args,
263 // args_to_use will accumulate outgoing args for the ISD::CALL case in
264 // SelectExpr to use to put the arguments in the appropriate registers.
265 std::vector<SDOperand> args_to_use;
267 // Count how many bytes are to be pushed on the stack, including the linkage
268 // area, and parameter passing area.
269 unsigned NumBytes = 24;
272 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
273 DAG.getConstant(NumBytes, getPointerTy()));
275 for (unsigned i = 0, e = Args.size(); i != e; ++i)
276 switch (getValueType(Args[i].second)) {
277 default: assert(0 && "Unknown value type!");
291 // Just to be safe, we'll always reserve the full 24 bytes of linkage area
292 // plus 32 bytes of argument space in case any called code gets funky on us.
293 // (Required by ABI to support var arg)
294 if (NumBytes < 56) NumBytes = 56;
296 // Adjust the stack pointer for the new arguments...
297 // These operations are automatically eliminated by the prolog/epilog pass
298 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
299 DAG.getConstant(NumBytes, getPointerTy()));
301 // Set up a copy of the stack pointer for use loading and storing any
302 // arguments that may not fit in the registers available for argument
304 SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
307 // Figure out which arguments are going to go in registers, and which in
308 // memory. Also, if this is a vararg function, floating point operations
309 // must be stored to our stack, and loaded into integer regs as well, if
310 // any integer regs are available for argument passing.
311 unsigned ArgOffset = 24;
312 unsigned GPR_remaining = 8;
313 unsigned FPR_remaining = 13;
315 std::vector<SDOperand> MemOps;
316 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
317 // PtrOff will be used to store the current argument to the stack if a
318 // register cannot be found for it.
319 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
320 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
321 MVT::ValueType ArgVT = getValueType(Args[i].second);
324 default: assert(0 && "Unexpected ValueType for argument!");
328 // Promote the integer to 32 bits. If the input type is signed use a
329 // sign extend, otherwise use a zero extend.
330 if (Args[i].second->isSigned())
331 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
333 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
336 if (GPR_remaining > 0) {
337 args_to_use.push_back(Args[i].first);
340 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
341 Args[i].first, PtrOff,
342 DAG.getSrcValue(NULL)));
347 // If we have one free GPR left, we can place the upper half of the i64
348 // in it, and store the other half to the stack. If we have two or more
349 // free GPRs, then we can pass both halves of the i64 in registers.
350 if (GPR_remaining > 0) {
351 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
352 Args[i].first, DAG.getConstant(1, MVT::i32));
353 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
354 Args[i].first, DAG.getConstant(0, MVT::i32));
355 args_to_use.push_back(Hi);
357 if (GPR_remaining > 0) {
358 args_to_use.push_back(Lo);
361 SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
362 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
363 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
364 Lo, PtrOff, DAG.getSrcValue(NULL)));
367 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
368 Args[i].first, PtrOff,
369 DAG.getSrcValue(NULL)));
375 if (FPR_remaining > 0) {
376 args_to_use.push_back(Args[i].first);
379 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
380 Args[i].first, PtrOff,
381 DAG.getSrcValue(NULL));
382 MemOps.push_back(Store);
383 // Float varargs are always shadowed in available integer registers
384 if (GPR_remaining > 0) {
385 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
386 DAG.getSrcValue(NULL));
387 MemOps.push_back(Load);
388 args_to_use.push_back(Load);
391 if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
392 SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
393 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
394 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
395 DAG.getSrcValue(NULL));
396 MemOps.push_back(Load);
397 args_to_use.push_back(Load);
401 // If we have any FPRs remaining, we may also have GPRs remaining.
402 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
404 if (GPR_remaining > 0) {
405 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
408 if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
409 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
414 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
415 Args[i].first, PtrOff,
416 DAG.getSrcValue(NULL)));
418 ArgOffset += (ArgVT == MVT::f32) ? 4 : 8;
423 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps);
426 std::vector<MVT::ValueType> RetVals;
427 MVT::ValueType RetTyVT = getValueType(RetTy);
428 if (RetTyVT != MVT::isVoid)
429 RetVals.push_back(RetTyVT);
430 RetVals.push_back(MVT::Other);
432 SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
433 Chain, Callee, args_to_use), 0);
434 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
435 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
436 DAG.getConstant(NumBytes, getPointerTy()));
437 return std::make_pair(TheCall, Chain);
440 SDOperand PPC32TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
441 Value *VAListV, SelectionDAG &DAG) {
442 // vastart just stores the address of the VarArgsFrameIndex slot into the
443 // memory location argument.
444 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
445 return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
446 DAG.getSrcValue(VAListV));
449 std::pair<SDOperand,SDOperand>
450 PPC32TargetLowering::LowerVAArg(SDOperand Chain,
451 SDOperand VAListP, Value *VAListV,
452 const Type *ArgTy, SelectionDAG &DAG) {
453 MVT::ValueType ArgVT = getValueType(ArgTy);
456 DAG.getLoad(MVT::i32, Chain, VAListP, DAG.getSrcValue(VAListV));
457 SDOperand Result = DAG.getLoad(ArgVT, Chain, VAList, DAG.getSrcValue(NULL));
459 if (ArgVT == MVT::i32 || ArgVT == MVT::f32)
462 assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
463 "Other types should have been promoted for varargs!");
466 VAList = DAG.getNode(ISD::ADD, VAList.getValueType(), VAList,
467 DAG.getConstant(Amt, VAList.getValueType()));
468 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
469 VAList, VAListP, DAG.getSrcValue(VAListV));
470 return std::make_pair(Result, Chain);
474 std::pair<SDOperand, SDOperand> PPC32TargetLowering::
475 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
477 assert(0 && "LowerFrameReturnAddress unimplemented");