1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCMachineFunctionInfo.h"
16 #include "PPCPredicates.h"
17 #include "PPCTargetMachine.h"
18 #include "PPCPerfectShuffle.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/VectorExtras.h"
21 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/PseudoSourceValue.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/Constants.h"
30 #include "llvm/Function.h"
31 #include "llvm/Intrinsics.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/Support/CommandLine.h"
37 static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc",
38 cl::desc("enable preincrement load/store generation on PPC (experimental)"),
41 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
42 : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) {
46 // Use _setjmp/_longjmp instead of setjmp/longjmp.
47 setUseUnderscoreSetJmp(true);
48 setUseUnderscoreLongJmp(true);
50 // Set up the register classes.
51 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
52 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
53 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
55 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
56 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
57 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand);
59 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
61 // PowerPC has pre-inc load and store's.
62 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
63 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
64 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
65 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
66 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
67 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
68 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
69 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
70 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
71 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
73 // Shortening conversions involving ppcf128 get expanded (2 regs -> 1 reg)
74 setConvertAction(MVT::ppcf128, MVT::f64, Expand);
75 setConvertAction(MVT::ppcf128, MVT::f32, Expand);
76 // This is used in the ppcf128->int sequence. Note it has different semantics
77 // from FP_ROUND: that rounds to nearest, this rounds to zero.
78 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
80 // PowerPC has no intrinsics for these particular operations
81 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
82 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
83 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
84 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
86 // PowerPC has no SREM/UREM instructions
87 setOperationAction(ISD::SREM, MVT::i32, Expand);
88 setOperationAction(ISD::UREM, MVT::i32, Expand);
89 setOperationAction(ISD::SREM, MVT::i64, Expand);
90 setOperationAction(ISD::UREM, MVT::i64, Expand);
92 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
93 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
94 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
95 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
96 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
97 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
98 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
99 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
100 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
102 // We don't support sin/cos/sqrt/fmod/pow
103 setOperationAction(ISD::FSIN , MVT::f64, Expand);
104 setOperationAction(ISD::FCOS , MVT::f64, Expand);
105 setOperationAction(ISD::FREM , MVT::f64, Expand);
106 setOperationAction(ISD::FPOW , MVT::f64, Expand);
107 setOperationAction(ISD::FSIN , MVT::f32, Expand);
108 setOperationAction(ISD::FCOS , MVT::f32, Expand);
109 setOperationAction(ISD::FREM , MVT::f32, Expand);
110 setOperationAction(ISD::FPOW , MVT::f32, Expand);
112 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
114 // If we're enabling GP optimizations, use hardware square root
115 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
116 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
117 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
120 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
121 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
123 // PowerPC does not have BSWAP, CTPOP or CTTZ
124 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
125 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
126 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
127 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
128 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
129 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
131 // PowerPC does not have ROTR
132 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
134 // PowerPC does not have Select
135 setOperationAction(ISD::SELECT, MVT::i32, Expand);
136 setOperationAction(ISD::SELECT, MVT::i64, Expand);
137 setOperationAction(ISD::SELECT, MVT::f32, Expand);
138 setOperationAction(ISD::SELECT, MVT::f64, Expand);
140 // PowerPC wants to turn select_cc of FP into fsel when possible.
141 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
142 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
144 // PowerPC wants to optimize integer setcc a bit
145 setOperationAction(ISD::SETCC, MVT::i32, Custom);
147 // PowerPC does not have BRCOND which requires SetCC
148 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
150 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
152 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
153 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
155 // PowerPC does not have [U|S]INT_TO_FP
156 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
157 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
159 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
160 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
161 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
162 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
164 // We cannot sextinreg(i1). Expand to shifts.
165 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
167 // Support label based line numbers.
168 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
169 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
171 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
172 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
173 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
174 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
177 // We want to legalize GlobalAddress and ConstantPool nodes into the
178 // appropriate instructions to materialize the address.
179 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
180 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
181 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
182 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
183 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
184 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
185 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
186 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
188 // RET must be custom lowered, to meet ABI requirements
189 setOperationAction(ISD::RET , MVT::Other, Custom);
191 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
192 setOperationAction(ISD::VASTART , MVT::Other, Custom);
194 // VAARG is custom lowered with ELF 32 ABI
195 if (TM.getSubtarget<PPCSubtarget>().isELF32_ABI())
196 setOperationAction(ISD::VAARG, MVT::Other, Custom);
198 setOperationAction(ISD::VAARG, MVT::Other, Expand);
200 // Use the default implementation.
201 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
202 setOperationAction(ISD::VAEND , MVT::Other, Expand);
203 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
204 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
205 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
206 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
208 // We want to custom lower some of our intrinsics.
209 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
211 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
212 // They also have instructions for converting between i64 and fp.
213 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
214 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
215 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
216 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
217 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
219 // FIXME: disable this lowered code. This generates 64-bit register values,
220 // and we don't model the fact that the top part is clobbered by calls. We
221 // need to flag these together so that the value isn't live across a call.
222 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
224 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
225 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
227 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
228 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
231 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
232 // 64-bit PowerPC implementations can support i64 types directly
233 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
234 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
235 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
237 // 32-bit PowerPC wants to expand i64 shifts itself.
238 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
239 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
240 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
243 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
244 // First set operation action for all vector types to expand. Then we
245 // will selectively turn on ones that can be effectively codegen'd.
246 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
247 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
248 // add/sub are legal for all supported vector VT's.
249 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal);
250 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal);
252 // We promote all shuffles to v16i8.
253 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote);
254 AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8);
256 // We promote all non-typed operations to v4i32.
257 setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote);
258 AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32);
259 setOperationAction(ISD::OR , (MVT::ValueType)VT, Promote);
260 AddPromotedToType (ISD::OR , (MVT::ValueType)VT, MVT::v4i32);
261 setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote);
262 AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32);
263 setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote);
264 AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32);
265 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
266 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32);
267 setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote);
268 AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32);
270 // No other operations are legal.
271 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
272 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
273 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
274 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
275 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
276 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
277 setOperationAction(ISD::FNEG, (MVT::ValueType)VT, Expand);
278 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
279 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
280 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
281 setOperationAction(ISD::UMUL_LOHI, (MVT::ValueType)VT, Expand);
282 setOperationAction(ISD::SMUL_LOHI, (MVT::ValueType)VT, Expand);
283 setOperationAction(ISD::UDIVREM, (MVT::ValueType)VT, Expand);
284 setOperationAction(ISD::SDIVREM, (MVT::ValueType)VT, Expand);
285 setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand);
286 setOperationAction(ISD::FPOW, (MVT::ValueType)VT, Expand);
287 setOperationAction(ISD::CTPOP, (MVT::ValueType)VT, Expand);
288 setOperationAction(ISD::CTLZ, (MVT::ValueType)VT, Expand);
289 setOperationAction(ISD::CTTZ, (MVT::ValueType)VT, Expand);
292 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
293 // with merges, splats, etc.
294 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
296 setOperationAction(ISD::AND , MVT::v4i32, Legal);
297 setOperationAction(ISD::OR , MVT::v4i32, Legal);
298 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
299 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
300 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
301 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
303 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
304 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
305 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
306 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
308 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
309 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
310 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
311 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
313 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
314 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
316 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
317 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
318 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
319 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
322 setSetCCResultType(MVT::i32);
323 setShiftAmountType(MVT::i32);
324 setSetCCResultContents(ZeroOrOneSetCCResult);
326 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
327 setStackPointerRegisterToSaveRestore(PPC::X1);
328 setExceptionPointerRegister(PPC::X3);
329 setExceptionSelectorRegister(PPC::X4);
331 setStackPointerRegisterToSaveRestore(PPC::R1);
332 setExceptionPointerRegister(PPC::R3);
333 setExceptionSelectorRegister(PPC::R4);
336 // We have target-specific dag combine patterns for the following nodes:
337 setTargetDAGCombine(ISD::SINT_TO_FP);
338 setTargetDAGCombine(ISD::STORE);
339 setTargetDAGCombine(ISD::BR_CC);
340 setTargetDAGCombine(ISD::BSWAP);
342 // Darwin long double math library functions have $LDBL128 appended.
343 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) {
344 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
345 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
346 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
347 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
348 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
351 computeRegisterProperties();
354 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
355 /// function arguments in the caller parameter area.
356 unsigned PPCTargetLowering::getByValTypeAlignment(const Type *Ty) const {
357 TargetMachine &TM = getTargetMachine();
358 // Darwin passes everything on 4 byte boundary.
359 if (TM.getSubtarget<PPCSubtarget>().isDarwin())
365 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
368 case PPCISD::FSEL: return "PPCISD::FSEL";
369 case PPCISD::FCFID: return "PPCISD::FCFID";
370 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
371 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
372 case PPCISD::STFIWX: return "PPCISD::STFIWX";
373 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
374 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
375 case PPCISD::VPERM: return "PPCISD::VPERM";
376 case PPCISD::Hi: return "PPCISD::Hi";
377 case PPCISD::Lo: return "PPCISD::Lo";
378 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
379 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
380 case PPCISD::SRL: return "PPCISD::SRL";
381 case PPCISD::SRA: return "PPCISD::SRA";
382 case PPCISD::SHL: return "PPCISD::SHL";
383 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
384 case PPCISD::STD_32: return "PPCISD::STD_32";
385 case PPCISD::CALL_ELF: return "PPCISD::CALL_ELF";
386 case PPCISD::CALL_Macho: return "PPCISD::CALL_Macho";
387 case PPCISD::MTCTR: return "PPCISD::MTCTR";
388 case PPCISD::BCTRL_Macho: return "PPCISD::BCTRL_Macho";
389 case PPCISD::BCTRL_ELF: return "PPCISD::BCTRL_ELF";
390 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
391 case PPCISD::MFCR: return "PPCISD::MFCR";
392 case PPCISD::VCMP: return "PPCISD::VCMP";
393 case PPCISD::VCMPo: return "PPCISD::VCMPo";
394 case PPCISD::LBRX: return "PPCISD::LBRX";
395 case PPCISD::STBRX: return "PPCISD::STBRX";
396 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
397 case PPCISD::MFFS: return "PPCISD::MFFS";
398 case PPCISD::MTFSB0: return "PPCISD::MTFSB0";
399 case PPCISD::MTFSB1: return "PPCISD::MTFSB1";
400 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
401 case PPCISD::MTFSF: return "PPCISD::MTFSF";
405 //===----------------------------------------------------------------------===//
406 // Node matching predicates, for use by the tblgen matching code.
407 //===----------------------------------------------------------------------===//
409 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
410 static bool isFloatingPointZero(SDOperand Op) {
411 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
412 return CFP->getValueAPF().isZero();
413 else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
414 // Maybe this has already been legalized into the constant pool?
415 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
416 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
417 return CFP->getValueAPF().isZero();
422 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
423 /// true if Op is undef or if it matches the specified value.
424 static bool isConstantOrUndef(SDOperand Op, unsigned Val) {
425 return Op.getOpcode() == ISD::UNDEF ||
426 cast<ConstantSDNode>(Op)->getValue() == Val;
429 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
430 /// VPKUHUM instruction.
431 bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) {
433 for (unsigned i = 0; i != 16; ++i)
434 if (!isConstantOrUndef(N->getOperand(i), i*2+1))
437 for (unsigned i = 0; i != 8; ++i)
438 if (!isConstantOrUndef(N->getOperand(i), i*2+1) ||
439 !isConstantOrUndef(N->getOperand(i+8), i*2+1))
445 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
446 /// VPKUWUM instruction.
447 bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) {
449 for (unsigned i = 0; i != 16; i += 2)
450 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
451 !isConstantOrUndef(N->getOperand(i+1), i*2+3))
454 for (unsigned i = 0; i != 8; i += 2)
455 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
456 !isConstantOrUndef(N->getOperand(i+1), i*2+3) ||
457 !isConstantOrUndef(N->getOperand(i+8), i*2+2) ||
458 !isConstantOrUndef(N->getOperand(i+9), i*2+3))
464 /// isVMerge - Common function, used to match vmrg* shuffles.
466 static bool isVMerge(SDNode *N, unsigned UnitSize,
467 unsigned LHSStart, unsigned RHSStart) {
468 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
469 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
470 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
471 "Unsupported merge size!");
473 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
474 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
475 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j),
476 LHSStart+j+i*UnitSize) ||
477 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j),
478 RHSStart+j+i*UnitSize))
484 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
485 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
486 bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
488 return isVMerge(N, UnitSize, 8, 24);
489 return isVMerge(N, UnitSize, 8, 8);
492 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
493 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
494 bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
496 return isVMerge(N, UnitSize, 0, 16);
497 return isVMerge(N, UnitSize, 0, 0);
501 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
502 /// amount, otherwise return -1.
503 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
504 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
505 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
506 // Find the first non-undef value in the shuffle mask.
508 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i)
511 if (i == 16) return -1; // all undef.
513 // Otherwise, check to see if the rest of the elements are consequtively
514 // numbered from this value.
515 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue();
516 if (ShiftAmt < i) return -1;
520 // Check the rest of the elements to see if they are consequtive.
521 for (++i; i != 16; ++i)
522 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i))
525 // Check the rest of the elements to see if they are consequtive.
526 for (++i; i != 16; ++i)
527 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15))
534 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
535 /// specifies a splat of a single element that is suitable for input to
536 /// VSPLTB/VSPLTH/VSPLTW.
537 bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) {
538 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
539 N->getNumOperands() == 16 &&
540 (EltSize == 1 || EltSize == 2 || EltSize == 4));
542 // This is a splat operation if each element of the permute is the same, and
543 // if the value doesn't reference the second vector.
544 unsigned ElementBase = 0;
545 SDOperand Elt = N->getOperand(0);
546 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt))
547 ElementBase = EltV->getValue();
549 return false; // FIXME: Handle UNDEF elements too!
551 if (cast<ConstantSDNode>(Elt)->getValue() >= 16)
554 // Check that they are consequtive.
555 for (unsigned i = 1; i != EltSize; ++i) {
556 if (!isa<ConstantSDNode>(N->getOperand(i)) ||
557 cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase)
561 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
562 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
563 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
564 assert(isa<ConstantSDNode>(N->getOperand(i)) &&
565 "Invalid VECTOR_SHUFFLE mask!");
566 for (unsigned j = 0; j != EltSize; ++j)
567 if (N->getOperand(i+j) != N->getOperand(j))
574 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
576 bool PPC::isAllNegativeZeroVector(SDNode *N) {
577 assert(N->getOpcode() == ISD::BUILD_VECTOR);
578 if (PPC::isSplatShuffleMask(N, N->getNumOperands()))
579 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N))
580 return CFP->getValueAPF().isNegZero();
584 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
585 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
586 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
587 assert(isSplatShuffleMask(N, EltSize));
588 return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize;
591 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
592 /// by using a vspltis[bhw] instruction of the specified element size, return
593 /// the constant being splatted. The ByteSize field indicates the number of
594 /// bytes of each element [124] -> [bhw].
595 SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
596 SDOperand OpVal(0, 0);
598 // If ByteSize of the splat is bigger than the element size of the
599 // build_vector, then we have a case where we are checking for a splat where
600 // multiple elements of the buildvector are folded together into a single
601 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
602 unsigned EltSize = 16/N->getNumOperands();
603 if (EltSize < ByteSize) {
604 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
605 SDOperand UniquedVals[4];
606 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
608 // See if all of the elements in the buildvector agree across.
609 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
610 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
611 // If the element isn't a constant, bail fully out.
612 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand();
615 if (UniquedVals[i&(Multiple-1)].Val == 0)
616 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
617 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
618 return SDOperand(); // no match.
621 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
622 // either constant or undef values that are identical for each chunk. See
623 // if these chunks can form into a larger vspltis*.
625 // Check to see if all of the leading entries are either 0 or -1. If
626 // neither, then this won't fit into the immediate field.
627 bool LeadingZero = true;
628 bool LeadingOnes = true;
629 for (unsigned i = 0; i != Multiple-1; ++i) {
630 if (UniquedVals[i].Val == 0) continue; // Must have been undefs.
632 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
633 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
635 // Finally, check the least significant entry.
637 if (UniquedVals[Multiple-1].Val == 0)
638 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
639 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue();
641 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
644 if (UniquedVals[Multiple-1].Val == 0)
645 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
646 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended();
647 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
648 return DAG.getTargetConstant(Val, MVT::i32);
654 // Check to see if this buildvec has a single non-undef value in its elements.
655 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
656 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
658 OpVal = N->getOperand(i);
659 else if (OpVal != N->getOperand(i))
663 if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def.
665 unsigned ValSizeInBytes = 0;
667 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
668 Value = CN->getValue();
669 ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8;
670 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
671 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
672 Value = FloatToBits(CN->getValueAPF().convertToFloat());
676 // If the splat value is larger than the element value, then we can never do
677 // this splat. The only case that we could fit the replicated bits into our
678 // immediate field for would be zero, and we prefer to use vxor for it.
679 if (ValSizeInBytes < ByteSize) return SDOperand();
681 // If the element value is larger than the splat value, cut it in half and
682 // check to see if the two halves are equal. Continue doing this until we
683 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
684 while (ValSizeInBytes > ByteSize) {
685 ValSizeInBytes >>= 1;
687 // If the top half equals the bottom half, we're still ok.
688 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
689 (Value & ((1 << (8*ValSizeInBytes))-1)))
693 // Properly sign extend the value.
694 int ShAmt = (4-ByteSize)*8;
695 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
697 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
698 if (MaskVal == 0) return SDOperand();
700 // Finally, if this value fits in a 5 bit sext field, return it
701 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
702 return DAG.getTargetConstant(MaskVal, MVT::i32);
706 //===----------------------------------------------------------------------===//
707 // Addressing Mode Selection
708 //===----------------------------------------------------------------------===//
710 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
711 /// or 64-bit immediate, and if the value can be accurately represented as a
712 /// sign extension from a 16-bit value. If so, this returns true and the
714 static bool isIntS16Immediate(SDNode *N, short &Imm) {
715 if (N->getOpcode() != ISD::Constant)
718 Imm = (short)cast<ConstantSDNode>(N)->getValue();
719 if (N->getValueType(0) == MVT::i32)
720 return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue();
722 return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue();
724 static bool isIntS16Immediate(SDOperand Op, short &Imm) {
725 return isIntS16Immediate(Op.Val, Imm);
729 /// SelectAddressRegReg - Given the specified addressed, check to see if it
730 /// can be represented as an indexed [r+r] operation. Returns false if it
731 /// can be more efficiently represented with [r+imm].
732 bool PPCTargetLowering::SelectAddressRegReg(SDOperand N, SDOperand &Base,
736 if (N.getOpcode() == ISD::ADD) {
737 if (isIntS16Immediate(N.getOperand(1), imm))
739 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
742 Base = N.getOperand(0);
743 Index = N.getOperand(1);
745 } else if (N.getOpcode() == ISD::OR) {
746 if (isIntS16Immediate(N.getOperand(1), imm))
747 return false; // r+i can fold it if we can.
749 // If this is an or of disjoint bitfields, we can codegen this as an add
750 // (for better address arithmetic) if the LHS and RHS of the OR are provably
752 APInt LHSKnownZero, LHSKnownOne;
753 APInt RHSKnownZero, RHSKnownOne;
754 DAG.ComputeMaskedBits(N.getOperand(0),
755 APInt::getAllOnesValue(N.getOperand(0)
756 .getValueSizeInBits()),
757 LHSKnownZero, LHSKnownOne);
759 if (LHSKnownZero.getBoolValue()) {
760 DAG.ComputeMaskedBits(N.getOperand(1),
761 APInt::getAllOnesValue(N.getOperand(1)
762 .getValueSizeInBits()),
763 RHSKnownZero, RHSKnownOne);
764 // If all of the bits are known zero on the LHS or RHS, the add won't
766 if (~(LHSKnownZero | RHSKnownZero) == 0) {
767 Base = N.getOperand(0);
768 Index = N.getOperand(1);
777 /// Returns true if the address N can be represented by a base register plus
778 /// a signed 16-bit displacement [r+imm], and if it is not better
779 /// represented as reg+reg.
780 bool PPCTargetLowering::SelectAddressRegImm(SDOperand N, SDOperand &Disp,
781 SDOperand &Base, SelectionDAG &DAG){
782 // If this can be more profitably realized as r+r, fail.
783 if (SelectAddressRegReg(N, Disp, Base, DAG))
786 if (N.getOpcode() == ISD::ADD) {
788 if (isIntS16Immediate(N.getOperand(1), imm)) {
789 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
790 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
791 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
793 Base = N.getOperand(0);
795 return true; // [r+i]
796 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
797 // Match LOAD (ADD (X, Lo(G))).
798 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
799 && "Cannot handle constant offsets yet!");
800 Disp = N.getOperand(1).getOperand(0); // The global address.
801 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
802 Disp.getOpcode() == ISD::TargetConstantPool ||
803 Disp.getOpcode() == ISD::TargetJumpTable);
804 Base = N.getOperand(0);
805 return true; // [&g+r]
807 } else if (N.getOpcode() == ISD::OR) {
809 if (isIntS16Immediate(N.getOperand(1), imm)) {
810 // If this is an or of disjoint bitfields, we can codegen this as an add
811 // (for better address arithmetic) if the LHS and RHS of the OR are
812 // provably disjoint.
813 APInt LHSKnownZero, LHSKnownOne;
814 DAG.ComputeMaskedBits(N.getOperand(0),
815 APInt::getAllOnesValue(32),
816 LHSKnownZero, LHSKnownOne);
817 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
818 // If all of the bits are known zero on the LHS or RHS, the add won't
820 Base = N.getOperand(0);
821 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
825 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
826 // Loading from a constant address.
828 // If this address fits entirely in a 16-bit sext immediate field, codegen
831 if (isIntS16Immediate(CN, Imm)) {
832 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
833 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
837 // Handle 32-bit sext immediates with LIS + addr mode.
838 if (CN->getValueType(0) == MVT::i32 ||
839 (int64_t)CN->getValue() == (int)CN->getValue()) {
840 int Addr = (int)CN->getValue();
842 // Otherwise, break this down into an LIS + disp.
843 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
845 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
846 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
847 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
852 Disp = DAG.getTargetConstant(0, getPointerTy());
853 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
854 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
857 return true; // [r+0]
860 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
861 /// represented as an indexed [r+r] operation.
862 bool PPCTargetLowering::SelectAddressRegRegOnly(SDOperand N, SDOperand &Base,
865 // Check to see if we can easily represent this as an [r+r] address. This
866 // will fail if it thinks that the address is more profitably represented as
867 // reg+imm, e.g. where imm = 0.
868 if (SelectAddressRegReg(N, Base, Index, DAG))
871 // If the operand is an addition, always emit this as [r+r], since this is
872 // better (for code size, and execution, as the memop does the add for free)
873 // than emitting an explicit add.
874 if (N.getOpcode() == ISD::ADD) {
875 Base = N.getOperand(0);
876 Index = N.getOperand(1);
880 // Otherwise, do it the hard way, using R0 as the base register.
881 Base = DAG.getRegister(PPC::R0, N.getValueType());
886 /// SelectAddressRegImmShift - Returns true if the address N can be
887 /// represented by a base register plus a signed 14-bit displacement
888 /// [r+imm*4]. Suitable for use by STD and friends.
889 bool PPCTargetLowering::SelectAddressRegImmShift(SDOperand N, SDOperand &Disp,
892 // If this can be more profitably realized as r+r, fail.
893 if (SelectAddressRegReg(N, Disp, Base, DAG))
896 if (N.getOpcode() == ISD::ADD) {
898 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
899 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
900 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
901 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
903 Base = N.getOperand(0);
905 return true; // [r+i]
906 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
907 // Match LOAD (ADD (X, Lo(G))).
908 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
909 && "Cannot handle constant offsets yet!");
910 Disp = N.getOperand(1).getOperand(0); // The global address.
911 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
912 Disp.getOpcode() == ISD::TargetConstantPool ||
913 Disp.getOpcode() == ISD::TargetJumpTable);
914 Base = N.getOperand(0);
915 return true; // [&g+r]
917 } else if (N.getOpcode() == ISD::OR) {
919 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
920 // If this is an or of disjoint bitfields, we can codegen this as an add
921 // (for better address arithmetic) if the LHS and RHS of the OR are
922 // provably disjoint.
923 APInt LHSKnownZero, LHSKnownOne;
924 DAG.ComputeMaskedBits(N.getOperand(0),
925 APInt::getAllOnesValue(32),
926 LHSKnownZero, LHSKnownOne);
927 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
928 // If all of the bits are known zero on the LHS or RHS, the add won't
930 Base = N.getOperand(0);
931 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
935 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
936 // Loading from a constant address. Verify low two bits are clear.
937 if ((CN->getValue() & 3) == 0) {
938 // If this address fits entirely in a 14-bit sext immediate field, codegen
941 if (isIntS16Immediate(CN, Imm)) {
942 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
943 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
947 // Fold the low-part of 32-bit absolute addresses into addr mode.
948 if (CN->getValueType(0) == MVT::i32 ||
949 (int64_t)CN->getValue() == (int)CN->getValue()) {
950 int Addr = (int)CN->getValue();
952 // Otherwise, break this down into an LIS + disp.
953 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
955 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
956 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
957 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
963 Disp = DAG.getTargetConstant(0, getPointerTy());
964 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
965 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
968 return true; // [r+0]
972 /// getPreIndexedAddressParts - returns true by value, base pointer and
973 /// offset pointer and addressing mode by reference if the node's address
974 /// can be legally represented as pre-indexed load / store address.
975 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
977 ISD::MemIndexedMode &AM,
979 // Disabled by default for now.
980 if (!EnablePPCPreinc) return false;
984 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
985 Ptr = LD->getBasePtr();
986 VT = LD->getMemoryVT();
988 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
990 Ptr = ST->getBasePtr();
991 VT = ST->getMemoryVT();
995 // PowerPC doesn't have preinc load/store instructions for vectors.
996 if (MVT::isVector(VT))
999 // TODO: Check reg+reg first.
1001 // LDU/STU use reg+imm*4, others use reg+imm.
1002 if (VT != MVT::i64) {
1004 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
1008 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
1012 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1013 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1014 // sext i32 to i64 when addr mode is r+i.
1015 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1016 LD->getExtensionType() == ISD::SEXTLOAD &&
1017 isa<ConstantSDNode>(Offset))
1025 //===----------------------------------------------------------------------===//
1026 // LowerOperation implementation
1027 //===----------------------------------------------------------------------===//
1029 static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
1030 MVT::ValueType PtrVT = Op.getValueType();
1031 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1032 Constant *C = CP->getConstVal();
1033 SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
1034 SDOperand Zero = DAG.getConstant(0, PtrVT);
1036 const TargetMachine &TM = DAG.getTarget();
1038 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero);
1039 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero);
1041 // If this is a non-darwin platform, we don't support non-static relo models
1043 if (TM.getRelocationModel() == Reloc::Static ||
1044 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1045 // Generate non-pic code that has direct accesses to the constant pool.
1046 // The address of the global is just (hi(&g)+lo(&g)).
1047 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1050 if (TM.getRelocationModel() == Reloc::PIC_) {
1051 // With PIC, the first instruction is actually "GR+hi(&G)".
1052 Hi = DAG.getNode(ISD::ADD, PtrVT,
1053 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1056 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1060 static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
1061 MVT::ValueType PtrVT = Op.getValueType();
1062 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1063 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1064 SDOperand Zero = DAG.getConstant(0, PtrVT);
1066 const TargetMachine &TM = DAG.getTarget();
1068 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero);
1069 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero);
1071 // If this is a non-darwin platform, we don't support non-static relo models
1073 if (TM.getRelocationModel() == Reloc::Static ||
1074 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1075 // Generate non-pic code that has direct accesses to the constant pool.
1076 // The address of the global is just (hi(&g)+lo(&g)).
1077 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1080 if (TM.getRelocationModel() == Reloc::PIC_) {
1081 // With PIC, the first instruction is actually "GR+hi(&G)".
1082 Hi = DAG.getNode(ISD::ADD, PtrVT,
1083 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1086 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1090 static SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) {
1091 assert(0 && "TLS not implemented for PPC.");
1094 static SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
1095 MVT::ValueType PtrVT = Op.getValueType();
1096 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1097 GlobalValue *GV = GSDN->getGlobal();
1098 SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
1099 // If it's a debug information descriptor, don't mess with it.
1100 if (DAG.isVerifiedDebugInfoDesc(Op))
1102 SDOperand Zero = DAG.getConstant(0, PtrVT);
1104 const TargetMachine &TM = DAG.getTarget();
1106 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero);
1107 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero);
1109 // If this is a non-darwin platform, we don't support non-static relo models
1111 if (TM.getRelocationModel() == Reloc::Static ||
1112 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1113 // Generate non-pic code that has direct accesses to globals.
1114 // The address of the global is just (hi(&g)+lo(&g)).
1115 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1118 if (TM.getRelocationModel() == Reloc::PIC_) {
1119 // With PIC, the first instruction is actually "GR+hi(&G)".
1120 Hi = DAG.getNode(ISD::ADD, PtrVT,
1121 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1124 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1126 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV))
1129 // If the global is weak or external, we have to go through the lazy
1131 return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0);
1134 static SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
1135 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1137 // If we're comparing for equality to zero, expose the fact that this is
1138 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1139 // fold the new nodes.
1140 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1141 if (C->isNullValue() && CC == ISD::SETEQ) {
1142 MVT::ValueType VT = Op.getOperand(0).getValueType();
1143 SDOperand Zext = Op.getOperand(0);
1144 if (VT < MVT::i32) {
1146 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0));
1148 unsigned Log2b = Log2_32(MVT::getSizeInBits(VT));
1149 SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext);
1150 SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz,
1151 DAG.getConstant(Log2b, MVT::i32));
1152 return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc);
1154 // Leave comparisons against 0 and -1 alone for now, since they're usually
1155 // optimized. FIXME: revisit this when we can custom lower all setcc
1157 if (C->isAllOnesValue() || C->isNullValue())
1161 // If we have an integer seteq/setne, turn it into a compare against zero
1162 // by xor'ing the rhs with the lhs, which is faster than setting a
1163 // condition register, reading it back out, and masking the correct bit. The
1164 // normal approach here uses sub to do this instead of xor. Using xor exposes
1165 // the result to other bit-twiddling opportunities.
1166 MVT::ValueType LHSVT = Op.getOperand(0).getValueType();
1167 if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1168 MVT::ValueType VT = Op.getValueType();
1169 SDOperand Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0),
1171 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC);
1176 static SDOperand LowerVAARG(SDOperand Op, SelectionDAG &DAG,
1177 int VarArgsFrameIndex,
1178 int VarArgsStackOffset,
1179 unsigned VarArgsNumGPR,
1180 unsigned VarArgsNumFPR,
1181 const PPCSubtarget &Subtarget) {
1183 assert(0 && "VAARG in ELF32 ABI not implemented yet!");
1186 static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
1187 int VarArgsFrameIndex,
1188 int VarArgsStackOffset,
1189 unsigned VarArgsNumGPR,
1190 unsigned VarArgsNumFPR,
1191 const PPCSubtarget &Subtarget) {
1193 if (Subtarget.isMachoABI()) {
1194 // vastart just stores the address of the VarArgsFrameIndex slot into the
1195 // memory location argument.
1196 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1197 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1198 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1199 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0);
1202 // For ELF 32 ABI we follow the layout of the va_list struct.
1203 // We suppose the given va_list is already allocated.
1206 // char gpr; /* index into the array of 8 GPRs
1207 // * stored in the register save area
1208 // * gpr=0 corresponds to r3,
1209 // * gpr=1 to r4, etc.
1211 // char fpr; /* index into the array of 8 FPRs
1212 // * stored in the register save area
1213 // * fpr=0 corresponds to f1,
1214 // * fpr=1 to f2, etc.
1216 // char *overflow_arg_area;
1217 // /* location on stack that holds
1218 // * the next overflow argument
1220 // char *reg_save_area;
1221 // /* where r3:r10 and f1:f8 (if saved)
1227 SDOperand ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i8);
1228 SDOperand ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i8);
1231 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1233 SDOperand StackOffsetFI = DAG.getFrameIndex(VarArgsStackOffset, PtrVT);
1234 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1236 uint64_t FrameOffset = MVT::getSizeInBits(PtrVT)/8;
1237 SDOperand ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1239 uint64_t StackOffset = MVT::getSizeInBits(PtrVT)/8 - 1;
1240 SDOperand ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1242 uint64_t FPROffset = 1;
1243 SDOperand ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1245 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1247 // Store first byte : number of int regs
1248 SDOperand firstStore = DAG.getStore(Op.getOperand(0), ArgGPR,
1249 Op.getOperand(1), SV, 0);
1250 uint64_t nextOffset = FPROffset;
1251 SDOperand nextPtr = DAG.getNode(ISD::ADD, PtrVT, Op.getOperand(1),
1254 // Store second byte : number of float regs
1255 SDOperand secondStore =
1256 DAG.getStore(firstStore, ArgFPR, nextPtr, SV, nextOffset);
1257 nextOffset += StackOffset;
1258 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstStackOffset);
1260 // Store second word : arguments given on stack
1261 SDOperand thirdStore =
1262 DAG.getStore(secondStore, StackOffsetFI, nextPtr, SV, nextOffset);
1263 nextOffset += FrameOffset;
1264 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstFrameOffset);
1266 // Store third word : arguments given in registers
1267 return DAG.getStore(thirdStore, FR, nextPtr, SV, nextOffset);
1271 #include "PPCGenCallingConv.inc"
1273 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1274 /// depending on which subtarget is selected.
1275 static const unsigned *GetFPR(const PPCSubtarget &Subtarget) {
1276 if (Subtarget.isMachoABI()) {
1277 static const unsigned FPR[] = {
1278 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1279 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1285 static const unsigned FPR[] = {
1286 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1292 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
1293 int &VarArgsFrameIndex,
1294 int &VarArgsStackOffset,
1295 unsigned &VarArgsNumGPR,
1296 unsigned &VarArgsNumFPR,
1297 const PPCSubtarget &Subtarget) {
1298 // TODO: add description of PPC stack frame format, or at least some docs.
1300 MachineFunction &MF = DAG.getMachineFunction();
1301 MachineFrameInfo *MFI = MF.getFrameInfo();
1302 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1303 SmallVector<SDOperand, 8> ArgValues;
1304 SDOperand Root = Op.getOperand(0);
1306 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1307 bool isPPC64 = PtrVT == MVT::i64;
1308 bool isMachoABI = Subtarget.isMachoABI();
1309 bool isELF32_ABI = Subtarget.isELF32_ABI();
1310 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1312 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1314 static const unsigned GPR_32[] = { // 32-bit registers.
1315 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1316 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1318 static const unsigned GPR_64[] = { // 64-bit registers.
1319 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1320 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1323 static const unsigned *FPR = GetFPR(Subtarget);
1325 static const unsigned VR[] = {
1326 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1327 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1330 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
1331 const unsigned Num_FPR_Regs = isMachoABI ? 13 : 8;
1332 const unsigned Num_VR_Regs = array_lengthof( VR);
1334 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1336 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1338 // Add DAG nodes to load the arguments or copy them out of registers. On
1339 // entry to a function on PPC, the arguments start after the linkage area,
1340 // although the first ones are often in registers.
1342 // In the ELF 32 ABI, GPRs and stack are double word align: an argument
1343 // represented with two words (long long or double) must be copied to an
1344 // even GPR_idx value or to an even ArgOffset value.
1346 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
1348 bool needsLoad = false;
1349 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
1350 unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8;
1351 unsigned ArgSize = ObjSize;
1352 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(ArgNo+3))->getValue();
1353 unsigned AlignFlag = 1 << ISD::ParamFlags::OrigAlignmentOffs;
1354 // See if next argument requires stack alignment in ELF
1355 bool Expand = (ObjectVT == MVT::f64) || ((ArgNo + 1 < e) &&
1356 (cast<ConstantSDNode>(Op.getOperand(ArgNo+4))->getValue() & AlignFlag) &&
1357 (!(Flags & AlignFlag)));
1359 unsigned CurArgOffset = ArgOffset;
1361 default: assert(0 && "Unhandled argument type!");
1363 // Double word align in ELF
1364 if (Expand && isELF32_ABI) GPR_idx += (GPR_idx % 2);
1365 if (GPR_idx != Num_GPR_Regs) {
1366 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
1367 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1368 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32);
1372 ArgSize = PtrByteSize;
1374 // Stack align in ELF
1375 if (needsLoad && Expand && isELF32_ABI)
1376 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1377 // All int arguments reserve stack space in Macho ABI.
1378 if (isMachoABI || needsLoad) ArgOffset += PtrByteSize;
1381 case MVT::i64: // PPC64
1382 if (GPR_idx != Num_GPR_Regs) {
1383 unsigned VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
1384 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1385 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1390 // All int arguments reserve stack space in Macho ABI.
1391 if (isMachoABI || needsLoad) ArgOffset += 8;
1396 // Every 4 bytes of argument space consumes one of the GPRs available for
1397 // argument passing.
1398 if (GPR_idx != Num_GPR_Regs && isMachoABI) {
1400 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
1403 if (FPR_idx != Num_FPR_Regs) {
1405 if (ObjectVT == MVT::f32)
1406 VReg = RegInfo.createVirtualRegister(&PPC::F4RCRegClass);
1408 VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
1409 RegInfo.addLiveIn(FPR[FPR_idx], VReg);
1410 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
1416 // Stack align in ELF
1417 if (needsLoad && Expand && isELF32_ABI)
1418 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1419 // All FP arguments reserve stack space in Macho ABI.
1420 if (isMachoABI || needsLoad) ArgOffset += isPPC64 ? 8 : ObjSize;
1426 // Note that vector arguments in registers don't reserve stack space.
1427 if (VR_idx != Num_VR_Regs) {
1428 unsigned VReg = RegInfo.createVirtualRegister(&PPC::VRRCRegClass);
1429 RegInfo.addLiveIn(VR[VR_idx], VReg);
1430 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
1433 // This should be simple, but requires getting 16-byte aligned stack
1435 assert(0 && "Loading VR argument not implemented yet!");
1441 // We need to load the argument to a virtual register if we determined above
1442 // that we ran out of physical registers of the appropriate type.
1444 int FI = MFI->CreateFixedObject(ObjSize,
1445 CurArgOffset + (ArgSize - ObjSize));
1446 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
1447 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
1450 ArgValues.push_back(ArgVal);
1453 // If the function takes variable number of arguments, make a frame index for
1454 // the start of the first vararg value... for expansion of llvm.va_start.
1455 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1460 VarArgsNumGPR = GPR_idx;
1461 VarArgsNumFPR = FPR_idx;
1463 // Make room for Num_GPR_Regs, Num_FPR_Regs and for a possible frame
1465 depth = -(Num_GPR_Regs * MVT::getSizeInBits(PtrVT)/8 +
1466 Num_FPR_Regs * MVT::getSizeInBits(MVT::f64)/8 +
1467 MVT::getSizeInBits(PtrVT)/8);
1469 VarArgsStackOffset = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8,
1476 VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8,
1478 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1480 SmallVector<SDOperand, 8> MemOps;
1482 // In ELF 32 ABI, the fixed integer arguments of a variadic function are
1483 // stored to the VarArgsFrameIndex on the stack.
1485 for (GPR_idx = 0; GPR_idx != VarArgsNumGPR; ++GPR_idx) {
1486 SDOperand Val = DAG.getRegister(GPR[GPR_idx], PtrVT);
1487 SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0);
1488 MemOps.push_back(Store);
1489 // Increment the address by four for the next argument to store
1490 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT);
1491 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1495 // If this function is vararg, store any remaining integer argument regs
1496 // to their spots on the stack so that they may be loaded by deferencing the
1497 // result of va_next.
1498 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
1501 VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
1503 VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
1505 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1506 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
1507 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1508 MemOps.push_back(Store);
1509 // Increment the address by four for the next argument to store
1510 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT);
1511 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1514 // In ELF 32 ABI, the double arguments are stored to the VarArgsFrameIndex
1517 for (FPR_idx = 0; FPR_idx != VarArgsNumFPR; ++FPR_idx) {
1518 SDOperand Val = DAG.getRegister(FPR[FPR_idx], MVT::f64);
1519 SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0);
1520 MemOps.push_back(Store);
1521 // Increment the address by eight for the next argument to store
1522 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8,
1524 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1527 for (; FPR_idx != Num_FPR_Regs; ++FPR_idx) {
1529 VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
1531 RegInfo.addLiveIn(FPR[FPR_idx], VReg);
1532 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::f64);
1533 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1534 MemOps.push_back(Store);
1535 // Increment the address by eight for the next argument to store
1536 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8,
1538 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1542 if (!MemOps.empty())
1543 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size());
1546 ArgValues.push_back(Root);
1548 // Return the new list of results.
1549 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
1550 Op.Val->value_end());
1551 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
1554 /// isCallCompatibleAddress - Return the immediate to use if the specified
1555 /// 32-bit value is representable in the immediate field of a BxA instruction.
1556 static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) {
1557 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
1560 int Addr = C->getValue();
1561 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
1562 (Addr << 6 >> 6) != Addr)
1563 return 0; // Top 6 bits have to be sext of immediate.
1565 return DAG.getConstant((int)C->getValue() >> 2,
1566 DAG.getTargetLoweringInfo().getPointerTy()).Val;
1570 static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG,
1571 const PPCSubtarget &Subtarget) {
1572 SDOperand Chain = Op.getOperand(0);
1573 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1574 SDOperand Callee = Op.getOperand(4);
1575 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
1577 bool isMachoABI = Subtarget.isMachoABI();
1578 bool isELF32_ABI = Subtarget.isELF32_ABI();
1580 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1581 bool isPPC64 = PtrVT == MVT::i64;
1582 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1584 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in
1585 // SelectExpr to use to put the arguments in the appropriate registers.
1586 std::vector<SDOperand> args_to_use;
1588 // Count how many bytes are to be pushed on the stack, including the linkage
1589 // area, and parameter passing area. We start with 24/48 bytes, which is
1590 // prereserved space for [SP][CR][LR][3 x unused].
1591 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1593 // Add up all the space actually used.
1594 for (unsigned i = 0; i != NumOps; ++i) {
1595 unsigned ArgSize =MVT::getSizeInBits(Op.getOperand(5+2*i).getValueType())/8;
1596 ArgSize = std::max(ArgSize, PtrByteSize);
1597 NumBytes += ArgSize;
1600 // The prolog code of the callee may store up to 8 GPR argument registers to
1601 // the stack, allowing va_start to index over them in memory if its varargs.
1602 // Because we cannot tell if this is needed on the caller side, we have to
1603 // conservatively assume that it is needed. As such, make sure we have at
1604 // least enough stack space for the caller to store the 8 GPRs.
1605 NumBytes = std::max(NumBytes,
1606 PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI));
1608 // Adjust the stack pointer for the new arguments...
1609 // These operations are automatically eliminated by the prolog/epilog pass
1610 Chain = DAG.getCALLSEQ_START(Chain,
1611 DAG.getConstant(NumBytes, PtrVT));
1613 // Set up a copy of the stack pointer for use loading and storing any
1614 // arguments that may not fit in the registers available for argument
1618 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
1620 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
1622 // Figure out which arguments are going to go in registers, and which in
1623 // memory. Also, if this is a vararg function, floating point operations
1624 // must be stored to our stack, and loaded into integer regs as well, if
1625 // any integer regs are available for argument passing.
1626 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1627 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1629 static const unsigned GPR_32[] = { // 32-bit registers.
1630 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1631 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1633 static const unsigned GPR_64[] = { // 64-bit registers.
1634 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1635 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1637 static const unsigned *FPR = GetFPR(Subtarget);
1639 static const unsigned VR[] = {
1640 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1641 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1643 const unsigned NumGPRs = array_lengthof(GPR_32);
1644 const unsigned NumFPRs = isMachoABI ? 13 : 8;
1645 const unsigned NumVRs = array_lengthof( VR);
1647 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1649 std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
1650 SmallVector<SDOperand, 8> MemOpChains;
1651 for (unsigned i = 0; i != NumOps; ++i) {
1653 SDOperand Arg = Op.getOperand(5+2*i);
1654 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue();
1655 unsigned AlignFlag = 1 << ISD::ParamFlags::OrigAlignmentOffs;
1656 // See if next argument requires stack alignment in ELF
1657 unsigned next = 5+2*(i+1)+1;
1658 bool Expand = (Arg.getValueType() == MVT::f64) || ((i + 1 < NumOps) &&
1659 (cast<ConstantSDNode>(Op.getOperand(next))->getValue() & AlignFlag) &&
1660 (!(Flags & AlignFlag)));
1662 // PtrOff will be used to store the current argument to the stack if a
1663 // register cannot be found for it.
1666 // Stack align in ELF 32
1667 if (isELF32_ABI && Expand)
1668 PtrOff = DAG.getConstant(ArgOffset + ((ArgOffset/4) % 2) * PtrByteSize,
1669 StackPtr.getValueType());
1671 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
1673 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff);
1675 // On PPC64, promote integers to 64-bit values.
1676 if (isPPC64 && Arg.getValueType() == MVT::i32) {
1677 unsigned ExtOp = (Flags & 1) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1679 Arg = DAG.getNode(ExtOp, MVT::i64, Arg);
1682 switch (Arg.getValueType()) {
1683 default: assert(0 && "Unexpected ValueType for argument!");
1686 // Double word align in ELF
1687 if (isELF32_ABI && Expand) GPR_idx += (GPR_idx % 2);
1688 if (GPR_idx != NumGPRs) {
1689 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
1691 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1694 if (inMem || isMachoABI) {
1695 // Stack align in ELF
1696 if (isELF32_ABI && Expand)
1697 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1699 ArgOffset += PtrByteSize;
1705 // Float varargs need to be promoted to double.
1706 if (Arg.getValueType() == MVT::f32)
1707 Arg = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Arg);
1710 if (FPR_idx != NumFPRs) {
1711 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
1714 SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
1715 MemOpChains.push_back(Store);
1717 // Float varargs are always shadowed in available integer registers
1718 if (GPR_idx != NumGPRs) {
1719 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
1720 MemOpChains.push_back(Load.getValue(1));
1721 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
1724 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
1725 SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType());
1726 PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour);
1727 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
1728 MemOpChains.push_back(Load.getValue(1));
1729 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
1733 // If we have any FPRs remaining, we may also have GPRs remaining.
1734 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
1737 if (GPR_idx != NumGPRs)
1739 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
1740 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
1745 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1748 if (inMem || isMachoABI) {
1749 // Stack align in ELF
1750 if (isELF32_ABI && Expand)
1751 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1755 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
1762 assert(!isVarArg && "Don't support passing vectors to varargs yet!");
1763 assert(VR_idx != NumVRs &&
1764 "Don't support passing more than 12 vector args yet!");
1765 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
1769 if (!MemOpChains.empty())
1770 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1771 &MemOpChains[0], MemOpChains.size());
1773 // Build a sequence of copy-to-reg nodes chained together with token chain
1774 // and flag operands which copy the outgoing args into the appropriate regs.
1776 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1777 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1779 InFlag = Chain.getValue(1);
1782 // With the ELF 32 ABI, set CR6 to true if this is a vararg call.
1783 if (isVarArg && isELF32_ABI) {
1784 SDOperand SetCR(DAG.getTargetNode(PPC::SETCR, MVT::i32), 0);
1785 Chain = DAG.getCopyToReg(Chain, PPC::CR6, SetCR, InFlag);
1786 InFlag = Chain.getValue(1);
1789 std::vector<MVT::ValueType> NodeTys;
1790 NodeTys.push_back(MVT::Other); // Returns a chain
1791 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
1793 SmallVector<SDOperand, 8> Ops;
1794 unsigned CallOpc = isMachoABI? PPCISD::CALL_Macho : PPCISD::CALL_ELF;
1796 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1797 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1798 // node so that legalize doesn't hack it.
1799 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1800 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
1801 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1802 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType());
1803 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
1804 // If this is an absolute destination address, use the munged value.
1805 Callee = SDOperand(Dest, 0);
1807 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
1808 // to do the call, we can't use PPCISD::CALL.
1809 SDOperand MTCTROps[] = {Chain, Callee, InFlag};
1810 Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+(InFlag.Val!=0));
1811 InFlag = Chain.getValue(1);
1813 // Copy the callee address into R12 on darwin.
1815 Chain = DAG.getCopyToReg(Chain, PPC::R12, Callee, InFlag);
1816 InFlag = Chain.getValue(1);
1820 NodeTys.push_back(MVT::Other);
1821 NodeTys.push_back(MVT::Flag);
1822 Ops.push_back(Chain);
1823 CallOpc = isMachoABI ? PPCISD::BCTRL_Macho : PPCISD::BCTRL_ELF;
1827 // If this is a direct call, pass the chain and the callee.
1829 Ops.push_back(Chain);
1830 Ops.push_back(Callee);
1833 // Add argument registers to the end of the list so that they are known live
1835 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1836 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1837 RegsToPass[i].second.getValueType()));
1840 Ops.push_back(InFlag);
1841 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
1842 InFlag = Chain.getValue(1);
1844 Chain = DAG.getCALLSEQ_END(Chain,
1845 DAG.getConstant(NumBytes, PtrVT),
1846 DAG.getConstant(0, PtrVT),
1848 if (Op.Val->getValueType(0) != MVT::Other)
1849 InFlag = Chain.getValue(1);
1851 SDOperand ResultVals[3];
1852 unsigned NumResults = 0;
1855 // If the call has results, copy the values out of the ret val registers.
1856 switch (Op.Val->getValueType(0)) {
1857 default: assert(0 && "Unexpected ret value!");
1858 case MVT::Other: break;
1860 if (Op.Val->getValueType(1) == MVT::i32) {
1861 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1);
1862 ResultVals[0] = Chain.getValue(0);
1863 Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32,
1864 Chain.getValue(2)).getValue(1);
1865 ResultVals[1] = Chain.getValue(0);
1867 NodeTys.push_back(MVT::i32);
1869 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1);
1870 ResultVals[0] = Chain.getValue(0);
1873 NodeTys.push_back(MVT::i32);
1876 Chain = DAG.getCopyFromReg(Chain, PPC::X3, MVT::i64, InFlag).getValue(1);
1877 ResultVals[0] = Chain.getValue(0);
1879 NodeTys.push_back(MVT::i64);
1882 if (Op.Val->getValueType(1) == MVT::f64) {
1883 Chain = DAG.getCopyFromReg(Chain, PPC::F1, MVT::f64, InFlag).getValue(1);
1884 ResultVals[0] = Chain.getValue(0);
1885 Chain = DAG.getCopyFromReg(Chain, PPC::F2, MVT::f64,
1886 Chain.getValue(2)).getValue(1);
1887 ResultVals[1] = Chain.getValue(0);
1889 NodeTys.push_back(MVT::f64);
1890 NodeTys.push_back(MVT::f64);
1893 // else fall through
1895 Chain = DAG.getCopyFromReg(Chain, PPC::F1, Op.Val->getValueType(0),
1896 InFlag).getValue(1);
1897 ResultVals[0] = Chain.getValue(0);
1899 NodeTys.push_back(Op.Val->getValueType(0));
1905 Chain = DAG.getCopyFromReg(Chain, PPC::V2, Op.Val->getValueType(0),
1906 InFlag).getValue(1);
1907 ResultVals[0] = Chain.getValue(0);
1909 NodeTys.push_back(Op.Val->getValueType(0));
1913 NodeTys.push_back(MVT::Other);
1915 // If the function returns void, just return the chain.
1916 if (NumResults == 0)
1919 // Otherwise, merge everything together with a MERGE_VALUES node.
1920 ResultVals[NumResults++] = Chain;
1921 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys,
1922 ResultVals, NumResults);
1923 return Res.getValue(Op.ResNo);
1926 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG, TargetMachine &TM) {
1927 SmallVector<CCValAssign, 16> RVLocs;
1928 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
1929 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1930 CCState CCInfo(CC, isVarArg, TM, RVLocs);
1931 CCInfo.AnalyzeReturn(Op.Val, RetCC_PPC);
1933 // If this is the first return lowered for this function, add the regs to the
1934 // liveout set for the function.
1935 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1936 for (unsigned i = 0; i != RVLocs.size(); ++i)
1937 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1940 SDOperand Chain = Op.getOperand(0);
1943 // Copy the result values into the output registers.
1944 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1945 CCValAssign &VA = RVLocs[i];
1946 assert(VA.isRegLoc() && "Can only return in registers!");
1947 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
1948 Flag = Chain.getValue(1);
1952 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain, Flag);
1954 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain);
1957 static SDOperand LowerSTACKRESTORE(SDOperand Op, SelectionDAG &DAG,
1958 const PPCSubtarget &Subtarget) {
1959 // When we pop the dynamic allocation we need to restore the SP link.
1961 // Get the corect type for pointers.
1962 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1964 // Construct the stack pointer operand.
1965 bool IsPPC64 = Subtarget.isPPC64();
1966 unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1;
1967 SDOperand StackPtr = DAG.getRegister(SP, PtrVT);
1969 // Get the operands for the STACKRESTORE.
1970 SDOperand Chain = Op.getOperand(0);
1971 SDOperand SaveSP = Op.getOperand(1);
1973 // Load the old link SP.
1974 SDOperand LoadLinkSP = DAG.getLoad(PtrVT, Chain, StackPtr, NULL, 0);
1976 // Restore the stack pointer.
1977 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), SP, SaveSP);
1979 // Store the old link SP.
1980 return DAG.getStore(Chain, LoadLinkSP, StackPtr, NULL, 0);
1983 static SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG,
1984 const PPCSubtarget &Subtarget) {
1985 MachineFunction &MF = DAG.getMachineFunction();
1986 bool IsPPC64 = Subtarget.isPPC64();
1987 bool isMachoABI = Subtarget.isMachoABI();
1989 // Get current frame pointer save index. The users of this index will be
1990 // primarily DYNALLOC instructions.
1991 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1992 int FPSI = FI->getFramePointerSaveIndex();
1994 // If the frame pointer save index hasn't been defined yet.
1996 // Find out what the fix offset of the frame pointer save area.
1997 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isMachoABI);
1999 // Allocate the frame index for frame pointer save area.
2000 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
2002 FI->setFramePointerSaveIndex(FPSI);
2006 SDOperand Chain = Op.getOperand(0);
2007 SDOperand Size = Op.getOperand(1);
2009 // Get the corect type for pointers.
2010 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2012 SDOperand NegSize = DAG.getNode(ISD::SUB, PtrVT,
2013 DAG.getConstant(0, PtrVT), Size);
2014 // Construct a node for the frame pointer save index.
2015 SDOperand FPSIdx = DAG.getFrameIndex(FPSI, PtrVT);
2016 // Build a DYNALLOC node.
2017 SDOperand Ops[3] = { Chain, NegSize, FPSIdx };
2018 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
2019 return DAG.getNode(PPCISD::DYNALLOC, VTs, Ops, 3);
2023 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
2025 static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
2026 // Not FP? Not a fsel.
2027 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) ||
2028 !MVT::isFloatingPoint(Op.getOperand(2).getValueType()))
2031 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2033 // Cannot handle SETEQ/SETNE.
2034 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand();
2036 MVT::ValueType ResVT = Op.getValueType();
2037 MVT::ValueType CmpVT = Op.getOperand(0).getValueType();
2038 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2039 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3);
2041 // If the RHS of the comparison is a 0.0, we don't need to do the
2042 // subtraction at all.
2043 if (isFloatingPointZero(RHS))
2045 default: break; // SETUO etc aren't handled by fsel.
2049 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
2053 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
2054 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
2055 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
2059 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
2063 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
2064 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
2065 return DAG.getNode(PPCISD::FSEL, ResVT,
2066 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV);
2071 default: break; // SETUO etc aren't handled by fsel.
2075 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
2076 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2077 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2078 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
2082 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
2083 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2084 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2085 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
2089 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
2090 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2091 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2092 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
2096 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
2097 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2098 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2099 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
2104 // FIXME: Split this code up when LegalizeDAGTypes lands.
2105 static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
2106 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType()));
2107 SDOperand Src = Op.getOperand(0);
2108 if (Src.getValueType() == MVT::f32)
2109 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src);
2112 switch (Op.getValueType()) {
2113 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
2115 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src);
2118 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src);
2122 // Convert the FP value to an int value through memory.
2123 SDOperand FIPtr = DAG.CreateStackTemporary(MVT::f64);
2125 // Emit a store to the stack slot.
2126 SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Tmp, FIPtr, NULL, 0);
2128 // Result is a load from the stack slot. If loading 4 bytes, make sure to
2130 if (Op.getValueType() == MVT::i32)
2131 FIPtr = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr,
2132 DAG.getConstant(4, FIPtr.getValueType()));
2133 return DAG.getLoad(Op.getValueType(), Chain, FIPtr, NULL, 0);
2136 static SDOperand LowerFP_ROUND_INREG(SDOperand Op, SelectionDAG &DAG) {
2137 assert(Op.getValueType() == MVT::ppcf128);
2138 SDNode *Node = Op.Val;
2139 assert(Node->getOperand(0).getValueType() == MVT::ppcf128);
2140 assert(Node->getOperand(0).Val->getOpcode() == ISD::BUILD_PAIR);
2141 SDOperand Lo = Node->getOperand(0).Val->getOperand(0);
2142 SDOperand Hi = Node->getOperand(0).Val->getOperand(1);
2144 // This sequence changes FPSCR to do round-to-zero, adds the two halves
2145 // of the long double, and puts FPSCR back the way it was. We do not
2146 // actually model FPSCR.
2147 std::vector<MVT::ValueType> NodeTys;
2148 SDOperand Ops[4], Result, MFFSreg, InFlag, FPreg;
2150 NodeTys.push_back(MVT::f64); // Return register
2151 NodeTys.push_back(MVT::Flag); // Returns a flag for later insns
2152 Result = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0);
2153 MFFSreg = Result.getValue(0);
2154 InFlag = Result.getValue(1);
2157 NodeTys.push_back(MVT::Flag); // Returns a flag
2158 Ops[0] = DAG.getConstant(31, MVT::i32);
2160 Result = DAG.getNode(PPCISD::MTFSB1, NodeTys, Ops, 2);
2161 InFlag = Result.getValue(0);
2164 NodeTys.push_back(MVT::Flag); // Returns a flag
2165 Ops[0] = DAG.getConstant(30, MVT::i32);
2167 Result = DAG.getNode(PPCISD::MTFSB0, NodeTys, Ops, 2);
2168 InFlag = Result.getValue(0);
2171 NodeTys.push_back(MVT::f64); // result of add
2172 NodeTys.push_back(MVT::Flag); // Returns a flag
2176 Result = DAG.getNode(PPCISD::FADDRTZ, NodeTys, Ops, 3);
2177 FPreg = Result.getValue(0);
2178 InFlag = Result.getValue(1);
2181 NodeTys.push_back(MVT::f64);
2182 Ops[0] = DAG.getConstant(1, MVT::i32);
2186 Result = DAG.getNode(PPCISD::MTFSF, NodeTys, Ops, 4);
2187 FPreg = Result.getValue(0);
2189 // We know the low half is about to be thrown away, so just use something
2191 return DAG.getNode(ISD::BUILD_PAIR, Lo.getValueType(), FPreg, FPreg);
2194 static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
2195 if (Op.getOperand(0).getValueType() == MVT::i64) {
2196 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
2197 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
2198 if (Op.getValueType() == MVT::f32)
2199 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0));
2203 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
2204 "Unhandled SINT_TO_FP type in custom expander!");
2205 // Since we only generate this in 64-bit mode, we can take advantage of
2206 // 64-bit registers. In particular, sign extend the input value into the
2207 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
2208 // then lfd it and fcfid it.
2209 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
2210 int FrameIdx = FrameInfo->CreateStackObject(8, 8);
2211 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2212 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
2214 SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32,
2217 // STD the extended value into the stack slot.
2218 MemOperand MO(PseudoSourceValue::getFixedStack(),
2219 MemOperand::MOStore, FrameIdx, 8, 8);
2220 SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other,
2221 DAG.getEntryNode(), Ext64, FIdx,
2222 DAG.getMemOperand(MO));
2223 // Load the value as a double.
2224 SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0);
2226 // FCFID it and return it.
2227 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld);
2228 if (Op.getValueType() == MVT::f32)
2229 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0));
2233 static SDOperand LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG) {
2235 The rounding mode is in bits 30:31 of FPSR, and has the following
2242 FLT_ROUNDS, on the other hand, expects the following:
2249 To perform the conversion, we do:
2250 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
2253 MachineFunction &MF = DAG.getMachineFunction();
2254 MVT::ValueType VT = Op.getValueType();
2255 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2256 std::vector<MVT::ValueType> NodeTys;
2257 SDOperand MFFSreg, InFlag;
2259 // Save FP Control Word to register
2260 NodeTys.push_back(MVT::f64); // return register
2261 NodeTys.push_back(MVT::Flag); // unused in this context
2262 SDOperand Chain = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0);
2264 // Save FP register to stack slot
2265 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
2266 SDOperand StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
2267 SDOperand Store = DAG.getStore(DAG.getEntryNode(), Chain,
2268 StackSlot, NULL, 0);
2270 // Load FP Control Word from low 32 bits of stack slot.
2271 SDOperand Four = DAG.getConstant(4, PtrVT);
2272 SDOperand Addr = DAG.getNode(ISD::ADD, PtrVT, StackSlot, Four);
2273 SDOperand CWD = DAG.getLoad(MVT::i32, Store, Addr, NULL, 0);
2275 // Transform as necessary
2277 DAG.getNode(ISD::AND, MVT::i32,
2278 CWD, DAG.getConstant(3, MVT::i32));
2280 DAG.getNode(ISD::SRL, MVT::i32,
2281 DAG.getNode(ISD::AND, MVT::i32,
2282 DAG.getNode(ISD::XOR, MVT::i32,
2283 CWD, DAG.getConstant(3, MVT::i32)),
2284 DAG.getConstant(3, MVT::i32)),
2285 DAG.getConstant(1, MVT::i8));
2288 DAG.getNode(ISD::XOR, MVT::i32, CWD1, CWD2);
2290 return DAG.getNode((MVT::getSizeInBits(VT) < 16 ?
2291 ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal);
2294 static SDOperand LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) {
2295 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
2296 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
2298 // Expand into a bunch of logical ops. Note that these ops
2299 // depend on the PPC behavior for oversized shift amounts.
2300 SDOperand Lo = Op.getOperand(0);
2301 SDOperand Hi = Op.getOperand(1);
2302 SDOperand Amt = Op.getOperand(2);
2304 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
2305 DAG.getConstant(32, MVT::i32), Amt);
2306 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt);
2307 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1);
2308 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
2309 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
2310 DAG.getConstant(-32U, MVT::i32));
2311 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5);
2312 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
2313 SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt);
2314 SDOperand OutOps[] = { OutLo, OutHi };
2315 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
2319 static SDOperand LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) {
2320 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
2321 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRL!");
2323 // Otherwise, expand into a bunch of logical ops. Note that these ops
2324 // depend on the PPC behavior for oversized shift amounts.
2325 SDOperand Lo = Op.getOperand(0);
2326 SDOperand Hi = Op.getOperand(1);
2327 SDOperand Amt = Op.getOperand(2);
2329 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
2330 DAG.getConstant(32, MVT::i32), Amt);
2331 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
2332 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
2333 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
2334 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
2335 DAG.getConstant(-32U, MVT::i32));
2336 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5);
2337 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
2338 SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt);
2339 SDOperand OutOps[] = { OutLo, OutHi };
2340 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
2344 static SDOperand LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) {
2345 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
2346 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!");
2348 // Otherwise, expand into a bunch of logical ops, followed by a select_cc.
2349 SDOperand Lo = Op.getOperand(0);
2350 SDOperand Hi = Op.getOperand(1);
2351 SDOperand Amt = Op.getOperand(2);
2353 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
2354 DAG.getConstant(32, MVT::i32), Amt);
2355 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
2356 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
2357 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
2358 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
2359 DAG.getConstant(-32U, MVT::i32));
2360 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5);
2361 SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt);
2362 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32),
2363 Tmp4, Tmp6, ISD::SETLE);
2364 SDOperand OutOps[] = { OutLo, OutHi };
2365 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
2369 //===----------------------------------------------------------------------===//
2370 // Vector related lowering.
2373 // If this is a vector of constants or undefs, get the bits. A bit in
2374 // UndefBits is set if the corresponding element of the vector is an
2375 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
2376 // zero. Return true if this is not an array of constants, false if it is.
2378 static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
2379 uint64_t UndefBits[2]) {
2380 // Start with zero'd results.
2381 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0;
2383 unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType());
2384 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
2385 SDOperand OpVal = BV->getOperand(i);
2387 unsigned PartNo = i >= e/2; // In the upper 128 bits?
2388 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t.
2390 uint64_t EltBits = 0;
2391 if (OpVal.getOpcode() == ISD::UNDEF) {
2392 uint64_t EltUndefBits = ~0U >> (32-EltBitSize);
2393 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize);
2395 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
2396 EltBits = CN->getValue() & (~0U >> (32-EltBitSize));
2397 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
2398 assert(CN->getValueType(0) == MVT::f32 &&
2399 "Only one legal FP vector type!");
2400 EltBits = FloatToBits(CN->getValueAPF().convertToFloat());
2402 // Nonconstant element.
2406 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize);
2409 //printf("%llx %llx %llx %llx\n",
2410 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]);
2414 // If this is a splat (repetition) of a value across the whole vector, return
2415 // the smallest size that splats it. For example, "0x01010101010101..." is a
2416 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
2417 // SplatSize = 1 byte.
2418 static bool isConstantSplat(const uint64_t Bits128[2],
2419 const uint64_t Undef128[2],
2420 unsigned &SplatBits, unsigned &SplatUndef,
2421 unsigned &SplatSize) {
2423 // Don't let undefs prevent splats from matching. See if the top 64-bits are
2424 // the same as the lower 64-bits, ignoring undefs.
2425 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0]))
2426 return false; // Can't be a splat if two pieces don't match.
2428 uint64_t Bits64 = Bits128[0] | Bits128[1];
2429 uint64_t Undef64 = Undef128[0] & Undef128[1];
2431 // Check that the top 32-bits are the same as the lower 32-bits, ignoring
2433 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64))
2434 return false; // Can't be a splat if two pieces don't match.
2436 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32);
2437 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32);
2439 // If the top 16-bits are different than the lower 16-bits, ignoring
2440 // undefs, we have an i32 splat.
2441 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) {
2443 SplatUndef = Undef32;
2448 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16);
2449 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16);
2451 // If the top 8-bits are different than the lower 8-bits, ignoring
2452 // undefs, we have an i16 splat.
2453 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) {
2455 SplatUndef = Undef16;
2460 // Otherwise, we have an 8-bit splat.
2461 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8);
2462 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8);
2467 /// BuildSplatI - Build a canonical splati of Val with an element size of
2468 /// SplatSize. Cast the result to VT.
2469 static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT,
2470 SelectionDAG &DAG) {
2471 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
2473 static const MVT::ValueType VTys[] = { // canonical VT to use for each size.
2474 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
2477 MVT::ValueType ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
2479 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
2483 MVT::ValueType CanonicalVT = VTys[SplatSize-1];
2485 // Build a canonical splat for this value.
2486 SDOperand Elt = DAG.getConstant(Val, MVT::getVectorElementType(CanonicalVT));
2487 SmallVector<SDOperand, 8> Ops;
2488 Ops.assign(MVT::getVectorNumElements(CanonicalVT), Elt);
2489 SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT,
2490 &Ops[0], Ops.size());
2491 return DAG.getNode(ISD::BIT_CONVERT, ReqVT, Res);
2494 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
2495 /// specified intrinsic ID.
2496 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS,
2498 MVT::ValueType DestVT = MVT::Other) {
2499 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
2500 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
2501 DAG.getConstant(IID, MVT::i32), LHS, RHS);
2504 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
2505 /// specified intrinsic ID.
2506 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1,
2507 SDOperand Op2, SelectionDAG &DAG,
2508 MVT::ValueType DestVT = MVT::Other) {
2509 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
2510 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
2511 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
2515 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
2516 /// amount. The result has the specified value type.
2517 static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt,
2518 MVT::ValueType VT, SelectionDAG &DAG) {
2519 // Force LHS/RHS to be the right type.
2520 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS);
2521 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS);
2524 for (unsigned i = 0; i != 16; ++i)
2525 Ops[i] = DAG.getConstant(i+Amt, MVT::i32);
2526 SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS,
2527 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16));
2528 return DAG.getNode(ISD::BIT_CONVERT, VT, T);
2531 // If this is a case we can't handle, return null and let the default
2532 // expansion code take care of it. If we CAN select this case, and if it
2533 // selects to a single instruction, return Op. Otherwise, if we can codegen
2534 // this case more efficiently than a constant pool load, lower it to the
2535 // sequence of ops that should be used.
2536 static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2537 // If this is a vector of constants or undefs, get the bits. A bit in
2538 // UndefBits is set if the corresponding element of the vector is an
2539 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
2541 uint64_t VectorBits[2];
2542 uint64_t UndefBits[2];
2543 if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits))
2544 return SDOperand(); // Not a constant vector.
2546 // If this is a splat (repetition) of a value across the whole vector, return
2547 // the smallest size that splats it. For example, "0x01010101010101..." is a
2548 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
2549 // SplatSize = 1 byte.
2550 unsigned SplatBits, SplatUndef, SplatSize;
2551 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){
2552 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0;
2554 // First, handle single instruction cases.
2557 if (SplatBits == 0) {
2558 // Canonicalize all zero vectors to be v4i32.
2559 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
2560 SDOperand Z = DAG.getConstant(0, MVT::i32);
2561 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z);
2562 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z);
2567 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
2568 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize);
2569 if (SextVal >= -16 && SextVal <= 15)
2570 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG);
2573 // Two instruction sequences.
2575 // If this value is in the range [-32,30] and is even, use:
2576 // tmp = VSPLTI[bhw], result = add tmp, tmp
2577 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
2578 Op = BuildSplatI(SextVal >> 1, SplatSize, Op.getValueType(), DAG);
2579 return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op);
2582 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
2583 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
2585 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
2586 // Make -1 and vspltisw -1:
2587 SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG);
2589 // Make the VSLW intrinsic, computing 0x8000_0000.
2590 SDOperand Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
2593 // xor by OnesV to invert it.
2594 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV);
2595 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2598 // Check to see if this is a wide variety of vsplti*, binop self cases.
2599 unsigned SplatBitSize = SplatSize*8;
2600 static const signed char SplatCsts[] = {
2601 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
2602 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
2605 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
2606 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
2607 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
2608 int i = SplatCsts[idx];
2610 // Figure out what shift amount will be used by altivec if shifted by i in
2612 unsigned TypeShiftAmt = i & (SplatBitSize-1);
2614 // vsplti + shl self.
2615 if (SextVal == (i << (int)TypeShiftAmt)) {
2616 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2617 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2618 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
2619 Intrinsic::ppc_altivec_vslw
2621 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2622 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2625 // vsplti + srl self.
2626 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
2627 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2628 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2629 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
2630 Intrinsic::ppc_altivec_vsrw
2632 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2633 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2636 // vsplti + sra self.
2637 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
2638 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2639 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2640 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
2641 Intrinsic::ppc_altivec_vsraw
2643 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2644 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2647 // vsplti + rol self.
2648 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
2649 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
2650 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2651 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2652 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
2653 Intrinsic::ppc_altivec_vrlw
2655 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2656 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2659 // t = vsplti c, result = vsldoi t, t, 1
2660 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
2661 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2662 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG);
2664 // t = vsplti c, result = vsldoi t, t, 2
2665 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
2666 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2667 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG);
2669 // t = vsplti c, result = vsldoi t, t, 3
2670 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
2671 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2672 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG);
2676 // Three instruction sequences.
2678 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
2679 if (SextVal >= 0 && SextVal <= 31) {
2680 SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG);
2681 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
2682 LHS = DAG.getNode(ISD::SUB, LHS.getValueType(), LHS, RHS);
2683 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
2685 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
2686 if (SextVal >= -31 && SextVal <= 0) {
2687 SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG);
2688 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
2689 LHS = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS);
2690 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
2697 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
2698 /// the specified operations to build the shuffle.
2699 static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS,
2700 SDOperand RHS, SelectionDAG &DAG) {
2701 unsigned OpNum = (PFEntry >> 26) & 0x0F;
2702 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
2703 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
2706 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
2718 if (OpNum == OP_COPY) {
2719 if (LHSID == (1*9+2)*9+3) return LHS;
2720 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
2724 SDOperand OpLHS, OpRHS;
2725 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG);
2726 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG);
2728 unsigned ShufIdxs[16];
2730 default: assert(0 && "Unknown i32 permute!");
2732 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
2733 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
2734 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
2735 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
2738 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
2739 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
2740 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
2741 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
2744 for (unsigned i = 0; i != 16; ++i)
2745 ShufIdxs[i] = (i&3)+0;
2748 for (unsigned i = 0; i != 16; ++i)
2749 ShufIdxs[i] = (i&3)+4;
2752 for (unsigned i = 0; i != 16; ++i)
2753 ShufIdxs[i] = (i&3)+8;
2756 for (unsigned i = 0; i != 16; ++i)
2757 ShufIdxs[i] = (i&3)+12;
2760 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG);
2762 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG);
2764 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG);
2767 for (unsigned i = 0; i != 16; ++i)
2768 Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i32);
2770 return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS,
2771 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
2774 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
2775 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
2776 /// return the code it can be lowered into. Worst case, it can always be
2777 /// lowered into a vperm.
2778 static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
2779 SDOperand V1 = Op.getOperand(0);
2780 SDOperand V2 = Op.getOperand(1);
2781 SDOperand PermMask = Op.getOperand(2);
2783 // Cases that are handled by instructions that take permute immediates
2784 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
2785 // selected by the instruction selector.
2786 if (V2.getOpcode() == ISD::UNDEF) {
2787 if (PPC::isSplatShuffleMask(PermMask.Val, 1) ||
2788 PPC::isSplatShuffleMask(PermMask.Val, 2) ||
2789 PPC::isSplatShuffleMask(PermMask.Val, 4) ||
2790 PPC::isVPKUWUMShuffleMask(PermMask.Val, true) ||
2791 PPC::isVPKUHUMShuffleMask(PermMask.Val, true) ||
2792 PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 ||
2793 PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) ||
2794 PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) ||
2795 PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) ||
2796 PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) ||
2797 PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) ||
2798 PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) {
2803 // Altivec has a variety of "shuffle immediates" that take two vector inputs
2804 // and produce a fixed permutation. If any of these match, do not lower to
2806 if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) ||
2807 PPC::isVPKUHUMShuffleMask(PermMask.Val, false) ||
2808 PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 ||
2809 PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) ||
2810 PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) ||
2811 PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) ||
2812 PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) ||
2813 PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) ||
2814 PPC::isVMRGHShuffleMask(PermMask.Val, 4, false))
2817 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
2818 // perfect shuffle table to emit an optimal matching sequence.
2819 unsigned PFIndexes[4];
2820 bool isFourElementShuffle = true;
2821 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
2822 unsigned EltNo = 8; // Start out undef.
2823 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
2824 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF)
2825 continue; // Undef, ignore it.
2827 unsigned ByteSource =
2828 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue();
2829 if ((ByteSource & 3) != j) {
2830 isFourElementShuffle = false;
2835 EltNo = ByteSource/4;
2836 } else if (EltNo != ByteSource/4) {
2837 isFourElementShuffle = false;
2841 PFIndexes[i] = EltNo;
2844 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
2845 // perfect shuffle vector to determine if it is cost effective to do this as
2846 // discrete instructions, or whether we should use a vperm.
2847 if (isFourElementShuffle) {
2848 // Compute the index in the perfect shuffle table.
2849 unsigned PFTableIndex =
2850 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
2852 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
2853 unsigned Cost = (PFEntry >> 30);
2855 // Determining when to avoid vperm is tricky. Many things affect the cost
2856 // of vperm, particularly how many times the perm mask needs to be computed.
2857 // For example, if the perm mask can be hoisted out of a loop or is already
2858 // used (perhaps because there are multiple permutes with the same shuffle
2859 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
2860 // the loop requires an extra register.
2862 // As a compromise, we only emit discrete instructions if the shuffle can be
2863 // generated in 3 or fewer operations. When we have loop information
2864 // available, if this block is within a loop, we should avoid using vperm
2865 // for 3-operation perms and use a constant pool load instead.
2867 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG);
2870 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
2871 // vector that will get spilled to the constant pool.
2872 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
2874 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
2875 // that it is in input element units, not in bytes. Convert now.
2876 MVT::ValueType EltVT = MVT::getVectorElementType(V1.getValueType());
2877 unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8;
2879 SmallVector<SDOperand, 16> ResultMask;
2880 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
2882 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
2885 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue();
2887 for (unsigned j = 0; j != BytesPerElement; ++j)
2888 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
2892 SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8,
2893 &ResultMask[0], ResultMask.size());
2894 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
2897 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
2898 /// altivec comparison. If it is, return true and fill in Opc/isDot with
2899 /// information about the intrinsic.
2900 static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc,
2902 unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue();
2905 switch (IntrinsicID) {
2906 default: return false;
2907 // Comparison predicates.
2908 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
2909 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
2910 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
2911 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
2912 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
2913 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
2914 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
2915 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
2916 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
2917 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
2918 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
2919 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
2920 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
2922 // Normal Comparisons.
2923 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
2924 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
2925 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
2926 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
2927 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
2928 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
2929 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
2930 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
2931 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
2932 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
2933 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
2934 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
2935 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
2940 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
2941 /// lower, do it, otherwise return null.
2942 static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
2943 // If this is a lowered altivec predicate compare, CompareOpc is set to the
2944 // opcode number of the comparison.
2947 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
2948 return SDOperand(); // Don't custom lower most intrinsics.
2950 // If this is a non-dot comparison, make the VCMP node and we are done.
2952 SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(),
2953 Op.getOperand(1), Op.getOperand(2),
2954 DAG.getConstant(CompareOpc, MVT::i32));
2955 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp);
2958 // Create the PPCISD altivec 'dot' comparison node.
2960 Op.getOperand(2), // LHS
2961 Op.getOperand(3), // RHS
2962 DAG.getConstant(CompareOpc, MVT::i32)
2964 std::vector<MVT::ValueType> VTs;
2965 VTs.push_back(Op.getOperand(2).getValueType());
2966 VTs.push_back(MVT::Flag);
2967 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
2969 // Now that we have the comparison, emit a copy from the CR to a GPR.
2970 // This is flagged to the above dot comparison.
2971 SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32,
2972 DAG.getRegister(PPC::CR6, MVT::i32),
2973 CompNode.getValue(1));
2975 // Unpack the result based on how the target uses it.
2976 unsigned BitNo; // Bit # of CR6.
2977 bool InvertBit; // Invert result?
2978 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
2979 default: // Can't happen, don't crash on invalid number though.
2980 case 0: // Return the value of the EQ bit of CR6.
2981 BitNo = 0; InvertBit = false;
2983 case 1: // Return the inverted value of the EQ bit of CR6.
2984 BitNo = 0; InvertBit = true;
2986 case 2: // Return the value of the LT bit of CR6.
2987 BitNo = 2; InvertBit = false;
2989 case 3: // Return the inverted value of the LT bit of CR6.
2990 BitNo = 2; InvertBit = true;
2994 // Shift the bit into the low position.
2995 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags,
2996 DAG.getConstant(8-(3-BitNo), MVT::i32));
2998 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags,
2999 DAG.getConstant(1, MVT::i32));
3001 // If we are supposed to, toggle the bit.
3003 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags,
3004 DAG.getConstant(1, MVT::i32));
3008 static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
3009 // Create a stack slot that is 16-byte aligned.
3010 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
3011 int FrameIdx = FrameInfo->CreateStackObject(16, 16);
3012 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3013 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
3015 // Store the input value into Value#0 of the stack slot.
3016 SDOperand Store = DAG.getStore(DAG.getEntryNode(),
3017 Op.getOperand(0), FIdx, NULL, 0);
3019 return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0);
3022 static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) {
3023 if (Op.getValueType() == MVT::v4i32) {
3024 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3026 SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG);
3027 SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt.
3029 SDOperand RHSSwap = // = vrlw RHS, 16
3030 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG);
3032 // Shrinkify inputs to v8i16.
3033 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS);
3034 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS);
3035 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap);
3037 // Low parts multiplied together, generating 32-bit results (we ignore the
3039 SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
3040 LHS, RHS, DAG, MVT::v4i32);
3042 SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
3043 LHS, RHSSwap, Zero, DAG, MVT::v4i32);
3044 // Shift the high parts up 16 bits.
3045 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG);
3046 return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd);
3047 } else if (Op.getValueType() == MVT::v8i16) {
3048 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3050 SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG);
3052 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
3053 LHS, RHS, Zero, DAG);
3054 } else if (Op.getValueType() == MVT::v16i8) {
3055 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3057 // Multiply the even 8-bit parts, producing 16-bit sums.
3058 SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
3059 LHS, RHS, DAG, MVT::v8i16);
3060 EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts);
3062 // Multiply the odd 8-bit parts, producing 16-bit sums.
3063 SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
3064 LHS, RHS, DAG, MVT::v8i16);
3065 OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts);
3067 // Merge the results together.
3069 for (unsigned i = 0; i != 8; ++i) {
3070 Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8);
3071 Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8);
3073 return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts,
3074 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
3076 assert(0 && "Unknown mul to lower!");
3081 /// LowerOperation - Provide custom lowering hooks for some operations.
3083 SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
3084 switch (Op.getOpcode()) {
3085 default: assert(0 && "Wasn't expecting to be able to lower this!");
3086 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3087 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
3088 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3089 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
3090 case ISD::SETCC: return LowerSETCC(Op, DAG);
3092 return LowerVASTART(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
3093 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
3096 return LowerVAARG(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
3097 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
3099 case ISD::FORMAL_ARGUMENTS:
3100 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex,
3101 VarArgsStackOffset, VarArgsNumGPR,
3102 VarArgsNumFPR, PPCSubTarget);
3104 case ISD::CALL: return LowerCALL(Op, DAG, PPCSubTarget);
3105 case ISD::RET: return LowerRET(Op, DAG, getTargetMachine());
3106 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
3107 case ISD::DYNAMIC_STACKALLOC:
3108 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
3110 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
3111 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
3112 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
3113 case ISD::FP_ROUND_INREG: return LowerFP_ROUND_INREG(Op, DAG);
3114 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
3116 // Lower 64-bit shifts.
3117 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
3118 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
3119 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
3121 // Vector-related lowering.
3122 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
3123 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
3124 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
3125 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
3126 case ISD::MUL: return LowerMUL(Op, DAG);
3128 // Frame & Return address.
3129 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
3130 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
3135 SDNode *PPCTargetLowering::ExpandOperationResult(SDNode *N, SelectionDAG &DAG) {
3136 switch (N->getOpcode()) {
3137 default: assert(0 && "Wasn't expecting to be able to lower this!");
3138 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(SDOperand(N, 0), DAG).Val;
3143 //===----------------------------------------------------------------------===//
3144 // Other Lowering Code
3145 //===----------------------------------------------------------------------===//
3148 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
3149 MachineBasicBlock *BB) {
3150 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3151 assert((MI->getOpcode() == PPC::SELECT_CC_I4 ||
3152 MI->getOpcode() == PPC::SELECT_CC_I8 ||
3153 MI->getOpcode() == PPC::SELECT_CC_F4 ||
3154 MI->getOpcode() == PPC::SELECT_CC_F8 ||
3155 MI->getOpcode() == PPC::SELECT_CC_VRRC) &&
3156 "Unexpected instr type to insert");
3158 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
3159 // control-flow pattern. The incoming instruction knows the destination vreg
3160 // to set, the condition code register to branch on, the true/false values to
3161 // select between, and a branch opcode to use.
3162 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3163 ilist<MachineBasicBlock>::iterator It = BB;
3169 // cmpTY ccX, r1, r2
3171 // fallthrough --> copy0MBB
3172 MachineBasicBlock *thisMBB = BB;
3173 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
3174 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
3175 unsigned SelectPred = MI->getOperand(4).getImm();
3176 BuildMI(BB, TII->get(PPC::BCC))
3177 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
3178 MachineFunction *F = BB->getParent();
3179 F->getBasicBlockList().insert(It, copy0MBB);
3180 F->getBasicBlockList().insert(It, sinkMBB);
3181 // Update machine-CFG edges by first adding all successors of the current
3182 // block to the new block which will contain the Phi node for the select.
3183 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
3184 e = BB->succ_end(); i != e; ++i)
3185 sinkMBB->addSuccessor(*i);
3186 // Next, remove all successors of the current block, and add the true
3187 // and fallthrough blocks as its successors.
3188 while(!BB->succ_empty())
3189 BB->removeSuccessor(BB->succ_begin());
3190 BB->addSuccessor(copy0MBB);
3191 BB->addSuccessor(sinkMBB);
3194 // %FalseValue = ...
3195 // # fallthrough to sinkMBB
3198 // Update machine-CFG edges
3199 BB->addSuccessor(sinkMBB);
3202 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
3205 BuildMI(BB, TII->get(PPC::PHI), MI->getOperand(0).getReg())
3206 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
3207 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
3209 delete MI; // The pseudo instruction is gone now.
3213 //===----------------------------------------------------------------------===//
3214 // Target Optimization Hooks
3215 //===----------------------------------------------------------------------===//
3217 SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
3218 DAGCombinerInfo &DCI) const {
3219 TargetMachine &TM = getTargetMachine();
3220 SelectionDAG &DAG = DCI.DAG;
3221 switch (N->getOpcode()) {
3224 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
3225 if (C->getValue() == 0) // 0 << V -> 0.
3226 return N->getOperand(0);
3230 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
3231 if (C->getValue() == 0) // 0 >>u V -> 0.
3232 return N->getOperand(0);
3236 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
3237 if (C->getValue() == 0 || // 0 >>s V -> 0.
3238 C->isAllOnesValue()) // -1 >>s V -> -1.
3239 return N->getOperand(0);
3243 case ISD::SINT_TO_FP:
3244 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
3245 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
3246 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
3247 // We allow the src/dst to be either f32/f64, but the intermediate
3248 // type must be i64.
3249 if (N->getOperand(0).getValueType() == MVT::i64 &&
3250 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
3251 SDOperand Val = N->getOperand(0).getOperand(0);
3252 if (Val.getValueType() == MVT::f32) {
3253 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
3254 DCI.AddToWorklist(Val.Val);
3257 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val);
3258 DCI.AddToWorklist(Val.Val);
3259 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val);
3260 DCI.AddToWorklist(Val.Val);
3261 if (N->getValueType(0) == MVT::f32) {
3262 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val,
3263 DAG.getIntPtrConstant(0));
3264 DCI.AddToWorklist(Val.Val);
3267 } else if (N->getOperand(0).getValueType() == MVT::i32) {
3268 // If the intermediate type is i32, we can avoid the load/store here
3275 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
3276 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
3277 !cast<StoreSDNode>(N)->isTruncatingStore() &&
3278 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
3279 N->getOperand(1).getValueType() == MVT::i32 &&
3280 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
3281 SDOperand Val = N->getOperand(1).getOperand(0);
3282 if (Val.getValueType() == MVT::f32) {
3283 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
3284 DCI.AddToWorklist(Val.Val);
3286 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val);
3287 DCI.AddToWorklist(Val.Val);
3289 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val,
3290 N->getOperand(2), N->getOperand(3));
3291 DCI.AddToWorklist(Val.Val);
3295 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
3296 if (N->getOperand(1).getOpcode() == ISD::BSWAP &&
3297 N->getOperand(1).Val->hasOneUse() &&
3298 (N->getOperand(1).getValueType() == MVT::i32 ||
3299 N->getOperand(1).getValueType() == MVT::i16)) {
3300 SDOperand BSwapOp = N->getOperand(1).getOperand(0);
3301 // Do an any-extend to 32-bits if this is a half-word input.
3302 if (BSwapOp.getValueType() == MVT::i16)
3303 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp);
3305 return DAG.getNode(PPCISD::STBRX, MVT::Other, N->getOperand(0), BSwapOp,
3306 N->getOperand(2), N->getOperand(3),
3307 DAG.getValueType(N->getOperand(1).getValueType()));
3311 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
3312 if (ISD::isNON_EXTLoad(N->getOperand(0).Val) &&
3313 N->getOperand(0).hasOneUse() &&
3314 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
3315 SDOperand Load = N->getOperand(0);
3316 LoadSDNode *LD = cast<LoadSDNode>(Load);
3317 // Create the byte-swapping load.
3318 std::vector<MVT::ValueType> VTs;
3319 VTs.push_back(MVT::i32);
3320 VTs.push_back(MVT::Other);
3321 SDOperand MO = DAG.getMemOperand(LD->getMemOperand());
3323 LD->getChain(), // Chain
3324 LD->getBasePtr(), // Ptr
3326 DAG.getValueType(N->getValueType(0)) // VT
3328 SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4);
3330 // If this is an i16 load, insert the truncate.
3331 SDOperand ResVal = BSLoad;
3332 if (N->getValueType(0) == MVT::i16)
3333 ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad);
3335 // First, combine the bswap away. This makes the value produced by the
3337 DCI.CombineTo(N, ResVal);
3339 // Next, combine the load away, we give it a bogus result value but a real
3340 // chain result. The result value is dead because the bswap is dead.
3341 DCI.CombineTo(Load.Val, ResVal, BSLoad.getValue(1));
3343 // Return N so it doesn't get rechecked!
3344 return SDOperand(N, 0);
3348 case PPCISD::VCMP: {
3349 // If a VCMPo node already exists with exactly the same operands as this
3350 // node, use its result instead of this node (VCMPo computes both a CR6 and
3351 // a normal output).
3353 if (!N->getOperand(0).hasOneUse() &&
3354 !N->getOperand(1).hasOneUse() &&
3355 !N->getOperand(2).hasOneUse()) {
3357 // Scan all of the users of the LHS, looking for VCMPo's that match.
3358 SDNode *VCMPoNode = 0;
3360 SDNode *LHSN = N->getOperand(0).Val;
3361 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
3363 if ((*UI)->getOpcode() == PPCISD::VCMPo &&
3364 (*UI)->getOperand(1) == N->getOperand(1) &&
3365 (*UI)->getOperand(2) == N->getOperand(2) &&
3366 (*UI)->getOperand(0) == N->getOperand(0)) {
3371 // If there is no VCMPo node, or if the flag value has a single use, don't
3373 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
3376 // Look at the (necessarily single) use of the flag value. If it has a
3377 // chain, this transformation is more complex. Note that multiple things
3378 // could use the value result, which we should ignore.
3379 SDNode *FlagUser = 0;
3380 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
3381 FlagUser == 0; ++UI) {
3382 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
3384 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
3385 if (User->getOperand(i) == SDOperand(VCMPoNode, 1)) {
3392 // If the user is a MFCR instruction, we know this is safe. Otherwise we
3393 // give up for right now.
3394 if (FlagUser->getOpcode() == PPCISD::MFCR)
3395 return SDOperand(VCMPoNode, 0);
3400 // If this is a branch on an altivec predicate comparison, lower this so
3401 // that we don't have to do a MFCR: instead, branch directly on CR6. This
3402 // lowering is done pre-legalize, because the legalizer lowers the predicate
3403 // compare down to code that is difficult to reassemble.
3404 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
3405 SDOperand LHS = N->getOperand(2), RHS = N->getOperand(3);
3409 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
3410 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
3411 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
3412 assert(isDot && "Can't compare against a vector result!");
3414 // If this is a comparison against something other than 0/1, then we know
3415 // that the condition is never/always true.
3416 unsigned Val = cast<ConstantSDNode>(RHS)->getValue();
3417 if (Val != 0 && Val != 1) {
3418 if (CC == ISD::SETEQ) // Cond never true, remove branch.
3419 return N->getOperand(0);
3420 // Always !=, turn it into an unconditional branch.
3421 return DAG.getNode(ISD::BR, MVT::Other,
3422 N->getOperand(0), N->getOperand(4));
3425 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
3427 // Create the PPCISD altivec 'dot' comparison node.
3428 std::vector<MVT::ValueType> VTs;
3430 LHS.getOperand(2), // LHS of compare
3431 LHS.getOperand(3), // RHS of compare
3432 DAG.getConstant(CompareOpc, MVT::i32)
3434 VTs.push_back(LHS.getOperand(2).getValueType());
3435 VTs.push_back(MVT::Flag);
3436 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
3438 // Unpack the result based on how the target uses it.
3439 PPC::Predicate CompOpc;
3440 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) {
3441 default: // Can't happen, don't crash on invalid number though.
3442 case 0: // Branch on the value of the EQ bit of CR6.
3443 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
3445 case 1: // Branch on the inverted value of the EQ bit of CR6.
3446 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
3448 case 2: // Branch on the value of the LT bit of CR6.
3449 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
3451 case 3: // Branch on the inverted value of the LT bit of CR6.
3452 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
3456 return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0),
3457 DAG.getConstant(CompOpc, MVT::i32),
3458 DAG.getRegister(PPC::CR6, MVT::i32),
3459 N->getOperand(4), CompNode.getValue(1));
3468 //===----------------------------------------------------------------------===//
3469 // Inline Assembly Support
3470 //===----------------------------------------------------------------------===//
3472 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
3476 const SelectionDAG &DAG,
3477 unsigned Depth) const {
3478 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
3479 switch (Op.getOpcode()) {
3481 case PPCISD::LBRX: {
3482 // lhbrx is known to have the top bits cleared out.
3483 if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16)
3484 KnownZero = 0xFFFF0000;
3487 case ISD::INTRINSIC_WO_CHAIN: {
3488 switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) {
3490 case Intrinsic::ppc_altivec_vcmpbfp_p:
3491 case Intrinsic::ppc_altivec_vcmpeqfp_p:
3492 case Intrinsic::ppc_altivec_vcmpequb_p:
3493 case Intrinsic::ppc_altivec_vcmpequh_p:
3494 case Intrinsic::ppc_altivec_vcmpequw_p:
3495 case Intrinsic::ppc_altivec_vcmpgefp_p:
3496 case Intrinsic::ppc_altivec_vcmpgtfp_p:
3497 case Intrinsic::ppc_altivec_vcmpgtsb_p:
3498 case Intrinsic::ppc_altivec_vcmpgtsh_p:
3499 case Intrinsic::ppc_altivec_vcmpgtsw_p:
3500 case Intrinsic::ppc_altivec_vcmpgtub_p:
3501 case Intrinsic::ppc_altivec_vcmpgtuh_p:
3502 case Intrinsic::ppc_altivec_vcmpgtuw_p:
3503 KnownZero = ~1U; // All bits but the low one are known to be zero.
3511 /// getConstraintType - Given a constraint, return the type of
3512 /// constraint it is for this target.
3513 PPCTargetLowering::ConstraintType
3514 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
3515 if (Constraint.size() == 1) {
3516 switch (Constraint[0]) {
3523 return C_RegisterClass;
3526 return TargetLowering::getConstraintType(Constraint);
3529 std::pair<unsigned, const TargetRegisterClass*>
3530 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
3531 MVT::ValueType VT) const {
3532 if (Constraint.size() == 1) {
3533 // GCC RS6000 Constraint Letters
3534 switch (Constraint[0]) {
3537 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
3538 return std::make_pair(0U, PPC::G8RCRegisterClass);
3539 return std::make_pair(0U, PPC::GPRCRegisterClass);
3542 return std::make_pair(0U, PPC::F4RCRegisterClass);
3543 else if (VT == MVT::f64)
3544 return std::make_pair(0U, PPC::F8RCRegisterClass);
3547 return std::make_pair(0U, PPC::VRRCRegisterClass);
3549 return std::make_pair(0U, PPC::CRRCRegisterClass);
3553 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3557 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3558 /// vector. If it is invalid, don't add anything to Ops.
3559 void PPCTargetLowering::LowerAsmOperandForConstraint(SDOperand Op, char Letter,
3560 std::vector<SDOperand>&Ops,
3561 SelectionDAG &DAG) {
3562 SDOperand Result(0,0);
3573 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
3574 if (!CST) return; // Must be an immediate to match.
3575 unsigned Value = CST->getValue();
3577 default: assert(0 && "Unknown constraint letter!");
3578 case 'I': // "I" is a signed 16-bit constant.
3579 if ((short)Value == (int)Value)
3580 Result = DAG.getTargetConstant(Value, Op.getValueType());
3582 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
3583 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
3584 if ((short)Value == 0)
3585 Result = DAG.getTargetConstant(Value, Op.getValueType());
3587 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
3588 if ((Value >> 16) == 0)
3589 Result = DAG.getTargetConstant(Value, Op.getValueType());
3591 case 'M': // "M" is a constant that is greater than 31.
3593 Result = DAG.getTargetConstant(Value, Op.getValueType());
3595 case 'N': // "N" is a positive constant that is an exact power of two.
3596 if ((int)Value > 0 && isPowerOf2_32(Value))
3597 Result = DAG.getTargetConstant(Value, Op.getValueType());
3599 case 'O': // "O" is the constant zero.
3601 Result = DAG.getTargetConstant(Value, Op.getValueType());
3603 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
3604 if ((short)-Value == (int)-Value)
3605 Result = DAG.getTargetConstant(Value, Op.getValueType());
3613 Ops.push_back(Result);
3617 // Handle standard constraint letters.
3618 TargetLowering::LowerAsmOperandForConstraint(Op, Letter, Ops, DAG);
3621 // isLegalAddressingMode - Return true if the addressing mode represented
3622 // by AM is legal for this target, for a load/store of the specified type.
3623 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
3624 const Type *Ty) const {
3625 // FIXME: PPC does not allow r+i addressing modes for vectors!
3627 // PPC allows a sign-extended 16-bit immediate field.
3628 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
3631 // No global is ever allowed as a base.
3635 // PPC only support r+r,
3637 case 0: // "r+i" or just "i", depending on HasBaseReg.
3640 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
3642 // Otherwise we have r+r or r+i.
3645 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
3647 // Allow 2*r as r+r.
3650 // No other scales are supported.
3657 /// isLegalAddressImmediate - Return true if the integer value can be used
3658 /// as the offset of the target addressing mode for load / store of the
3660 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{
3661 // PPC allows a sign-extended 16-bit immediate field.
3662 return (V > -(1 << 16) && V < (1 << 16)-1);
3665 bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
3669 SDOperand PPCTargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) {
3670 // Depths > 0 not supported yet!
3671 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
3674 MachineFunction &MF = DAG.getMachineFunction();
3675 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3676 int RAIdx = FuncInfo->getReturnAddrSaveIndex();
3678 bool isPPC64 = PPCSubTarget.isPPC64();
3680 PPCFrameInfo::getReturnSaveOffset(isPPC64, PPCSubTarget.isMachoABI());
3682 // Set up a frame object for the return address.
3683 RAIdx = MF.getFrameInfo()->CreateFixedObject(isPPC64 ? 8 : 4, Offset);
3685 // Remember it for next time.
3686 FuncInfo->setReturnAddrSaveIndex(RAIdx);
3688 // Make sure the function really does not optimize away the store of the RA
3690 FuncInfo->setLRStoreRequired();
3693 // Just load the return address off the stack.
3694 SDOperand RetAddrFI = DAG.getFrameIndex(RAIdx, getPointerTy());
3695 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
3698 SDOperand PPCTargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) {
3699 // Depths > 0 not supported yet!
3700 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
3703 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3704 bool isPPC64 = PtrVT == MVT::i64;
3706 MachineFunction &MF = DAG.getMachineFunction();
3707 MachineFrameInfo *MFI = MF.getFrameInfo();
3708 bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects())
3709 && MFI->getStackSize();
3712 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::X31 : PPC::X1,
3715 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::R31 : PPC::R1,