1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPerfectShuffle.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCTargetObjectFile.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/StringSwitch.h"
22 #include "llvm/ADT/Triple.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineLoopInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/SelectionDAG.h"
30 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
31 #include "llvm/IR/CallingConv.h"
32 #include "llvm/IR/Constants.h"
33 #include "llvm/IR/DerivedTypes.h"
34 #include "llvm/IR/Function.h"
35 #include "llvm/IR/Intrinsics.h"
36 #include "llvm/Support/CommandLine.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/MathExtras.h"
39 #include "llvm/Support/raw_ostream.h"
40 #include "llvm/Target/TargetOptions.h"
43 // FIXME: Remove this once soft-float is supported.
44 static cl::opt<bool> DisablePPCFloatInVariadic("disable-ppc-float-in-variadic",
45 cl::desc("disable saving float registers for va_start on PPC"), cl::Hidden);
47 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
48 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
50 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
51 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
53 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
54 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
56 // FIXME: Remove this once the bug has been fixed!
57 extern cl::opt<bool> ANDIGlueBug;
59 PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM)
61 Subtarget(*TM.getSubtargetImpl()) {
62 // Use _setjmp/_longjmp instead of setjmp/longjmp.
63 setUseUnderscoreSetJmp(true);
64 setUseUnderscoreLongJmp(true);
66 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
67 // arguments are at least 4/8 bytes aligned.
68 bool isPPC64 = Subtarget.isPPC64();
69 setMinStackArgumentAlignment(isPPC64 ? 8:4);
71 // Set up the register classes.
72 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
73 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
74 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
76 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
77 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
78 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
80 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
82 // PowerPC has pre-inc load and store's.
83 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
84 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
85 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
86 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
87 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
88 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
89 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
90 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
91 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
92 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
94 if (Subtarget.useCRBits()) {
95 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
97 if (isPPC64 || Subtarget.hasFPCVT()) {
98 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
99 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
100 isPPC64 ? MVT::i64 : MVT::i32);
101 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
102 AddPromotedToType (ISD::UINT_TO_FP, MVT::i1,
103 isPPC64 ? MVT::i64 : MVT::i32);
105 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
106 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
109 // PowerPC does not support direct load / store of condition registers
110 setOperationAction(ISD::LOAD, MVT::i1, Custom);
111 setOperationAction(ISD::STORE, MVT::i1, Custom);
113 // FIXME: Remove this once the ANDI glue bug is fixed:
115 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
117 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
118 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
119 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
120 setTruncStoreAction(MVT::i32, MVT::i1, Expand);
121 setTruncStoreAction(MVT::i16, MVT::i1, Expand);
122 setTruncStoreAction(MVT::i8, MVT::i1, Expand);
124 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
127 // This is used in the ppcf128->int sequence. Note it has different semantics
128 // from FP_ROUND: that rounds to nearest, this rounds to zero.
129 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
131 // We do not currently implement these libm ops for PowerPC.
132 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
133 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
134 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
135 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
136 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
137 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
139 // PowerPC has no SREM/UREM instructions
140 setOperationAction(ISD::SREM, MVT::i32, Expand);
141 setOperationAction(ISD::UREM, MVT::i32, Expand);
142 setOperationAction(ISD::SREM, MVT::i64, Expand);
143 setOperationAction(ISD::UREM, MVT::i64, Expand);
145 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
146 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
147 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
148 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
149 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
150 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
151 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
152 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
153 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
155 // We don't support sin/cos/sqrt/fmod/pow
156 setOperationAction(ISD::FSIN , MVT::f64, Expand);
157 setOperationAction(ISD::FCOS , MVT::f64, Expand);
158 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
159 setOperationAction(ISD::FREM , MVT::f64, Expand);
160 setOperationAction(ISD::FPOW , MVT::f64, Expand);
161 setOperationAction(ISD::FMA , MVT::f64, Legal);
162 setOperationAction(ISD::FSIN , MVT::f32, Expand);
163 setOperationAction(ISD::FCOS , MVT::f32, Expand);
164 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
165 setOperationAction(ISD::FREM , MVT::f32, Expand);
166 setOperationAction(ISD::FPOW , MVT::f32, Expand);
167 setOperationAction(ISD::FMA , MVT::f32, Legal);
169 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
171 // If we're enabling GP optimizations, use hardware square root
172 if (!Subtarget.hasFSQRT() &&
173 !(TM.Options.UnsafeFPMath &&
174 Subtarget.hasFRSQRTE() && Subtarget.hasFRE()))
175 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
177 if (!Subtarget.hasFSQRT() &&
178 !(TM.Options.UnsafeFPMath &&
179 Subtarget.hasFRSQRTES() && Subtarget.hasFRES()))
180 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
182 if (Subtarget.hasFCPSGN()) {
183 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
184 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
186 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
187 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
190 if (Subtarget.hasFPRND()) {
191 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
192 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
193 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
194 setOperationAction(ISD::FROUND, MVT::f64, Legal);
196 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
197 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
198 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
199 setOperationAction(ISD::FROUND, MVT::f32, Legal);
202 // PowerPC does not have BSWAP, CTPOP or CTTZ
203 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
204 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
205 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
206 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
207 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
208 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
209 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
210 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
212 if (Subtarget.hasPOPCNTD()) {
213 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
214 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
216 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
217 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
220 // PowerPC does not have ROTR
221 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
222 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
224 if (!Subtarget.useCRBits()) {
225 // PowerPC does not have Select
226 setOperationAction(ISD::SELECT, MVT::i32, Expand);
227 setOperationAction(ISD::SELECT, MVT::i64, Expand);
228 setOperationAction(ISD::SELECT, MVT::f32, Expand);
229 setOperationAction(ISD::SELECT, MVT::f64, Expand);
232 // PowerPC wants to turn select_cc of FP into fsel when possible.
233 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
234 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
236 // PowerPC wants to optimize integer setcc a bit
237 if (!Subtarget.useCRBits())
238 setOperationAction(ISD::SETCC, MVT::i32, Custom);
240 // PowerPC does not have BRCOND which requires SetCC
241 if (!Subtarget.useCRBits())
242 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
244 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
246 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
247 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
249 // PowerPC does not have [U|S]INT_TO_FP
250 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
251 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
253 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
254 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
255 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
256 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
258 // We cannot sextinreg(i1). Expand to shifts.
259 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
261 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
262 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
263 // support continuation, user-level threading, and etc.. As a result, no
264 // other SjLj exception interfaces are implemented and please don't build
265 // your own exception handling based on them.
266 // LLVM/Clang supports zero-cost DWARF exception handling.
267 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
268 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
270 // We want to legalize GlobalAddress and ConstantPool nodes into the
271 // appropriate instructions to materialize the address.
272 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
273 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
274 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
275 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
276 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
277 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
278 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
279 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
280 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
281 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
284 setOperationAction(ISD::TRAP, MVT::Other, Legal);
286 // TRAMPOLINE is custom lowered.
287 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
288 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
290 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
291 setOperationAction(ISD::VASTART , MVT::Other, Custom);
293 if (Subtarget.isSVR4ABI()) {
295 // VAARG always uses double-word chunks, so promote anything smaller.
296 setOperationAction(ISD::VAARG, MVT::i1, Promote);
297 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
298 setOperationAction(ISD::VAARG, MVT::i8, Promote);
299 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
300 setOperationAction(ISD::VAARG, MVT::i16, Promote);
301 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
302 setOperationAction(ISD::VAARG, MVT::i32, Promote);
303 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
304 setOperationAction(ISD::VAARG, MVT::Other, Expand);
306 // VAARG is custom lowered with the 32-bit SVR4 ABI.
307 setOperationAction(ISD::VAARG, MVT::Other, Custom);
308 setOperationAction(ISD::VAARG, MVT::i64, Custom);
311 setOperationAction(ISD::VAARG, MVT::Other, Expand);
313 if (Subtarget.isSVR4ABI() && !isPPC64)
314 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
315 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
317 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
319 // Use the default implementation.
320 setOperationAction(ISD::VAEND , MVT::Other, Expand);
321 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
322 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
323 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
324 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
326 // We want to custom lower some of our intrinsics.
327 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
329 // To handle counter-based loop conditions.
330 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
332 // Comparisons that require checking two conditions.
333 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
334 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
335 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
336 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
337 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
338 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
339 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
340 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
341 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
342 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
343 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
344 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
346 if (Subtarget.has64BitSupport()) {
347 // They also have instructions for converting between i64 and fp.
348 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
349 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
350 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
351 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
352 // This is just the low 32 bits of a (signed) fp->i64 conversion.
353 // We cannot do this with Promote because i64 is not a legal type.
354 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
356 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
357 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
359 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
360 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
363 // With the instructions enabled under FPCVT, we can do everything.
364 if (Subtarget.hasFPCVT()) {
365 if (Subtarget.has64BitSupport()) {
366 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
367 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
368 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
369 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
372 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
373 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
374 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
375 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
378 if (Subtarget.use64BitRegs()) {
379 // 64-bit PowerPC implementations can support i64 types directly
380 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
381 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
382 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
383 // 64-bit PowerPC wants to expand i128 shifts itself.
384 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
385 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
386 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
388 // 32-bit PowerPC wants to expand i64 shifts itself.
389 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
390 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
391 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
394 if (Subtarget.hasAltivec()) {
395 // First set operation action for all vector types to expand. Then we
396 // will selectively turn on ones that can be effectively codegen'd.
397 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
398 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
399 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
401 // add/sub are legal for all supported vector VT's.
402 setOperationAction(ISD::ADD , VT, Legal);
403 setOperationAction(ISD::SUB , VT, Legal);
405 // We promote all shuffles to v16i8.
406 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
407 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
409 // We promote all non-typed operations to v4i32.
410 setOperationAction(ISD::AND , VT, Promote);
411 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
412 setOperationAction(ISD::OR , VT, Promote);
413 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
414 setOperationAction(ISD::XOR , VT, Promote);
415 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
416 setOperationAction(ISD::LOAD , VT, Promote);
417 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
418 setOperationAction(ISD::SELECT, VT, Promote);
419 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
420 setOperationAction(ISD::STORE, VT, Promote);
421 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
423 // No other operations are legal.
424 setOperationAction(ISD::MUL , VT, Expand);
425 setOperationAction(ISD::SDIV, VT, Expand);
426 setOperationAction(ISD::SREM, VT, Expand);
427 setOperationAction(ISD::UDIV, VT, Expand);
428 setOperationAction(ISD::UREM, VT, Expand);
429 setOperationAction(ISD::FDIV, VT, Expand);
430 setOperationAction(ISD::FREM, VT, Expand);
431 setOperationAction(ISD::FNEG, VT, Expand);
432 setOperationAction(ISD::FSQRT, VT, Expand);
433 setOperationAction(ISD::FLOG, VT, Expand);
434 setOperationAction(ISD::FLOG10, VT, Expand);
435 setOperationAction(ISD::FLOG2, VT, Expand);
436 setOperationAction(ISD::FEXP, VT, Expand);
437 setOperationAction(ISD::FEXP2, VT, Expand);
438 setOperationAction(ISD::FSIN, VT, Expand);
439 setOperationAction(ISD::FCOS, VT, Expand);
440 setOperationAction(ISD::FABS, VT, Expand);
441 setOperationAction(ISD::FPOWI, VT, Expand);
442 setOperationAction(ISD::FFLOOR, VT, Expand);
443 setOperationAction(ISD::FCEIL, VT, Expand);
444 setOperationAction(ISD::FTRUNC, VT, Expand);
445 setOperationAction(ISD::FRINT, VT, Expand);
446 setOperationAction(ISD::FNEARBYINT, VT, Expand);
447 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
448 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
449 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
450 setOperationAction(ISD::MULHU, VT, Expand);
451 setOperationAction(ISD::MULHS, VT, Expand);
452 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
453 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
454 setOperationAction(ISD::UDIVREM, VT, Expand);
455 setOperationAction(ISD::SDIVREM, VT, Expand);
456 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
457 setOperationAction(ISD::FPOW, VT, Expand);
458 setOperationAction(ISD::BSWAP, VT, Expand);
459 setOperationAction(ISD::CTPOP, VT, Expand);
460 setOperationAction(ISD::CTLZ, VT, Expand);
461 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
462 setOperationAction(ISD::CTTZ, VT, Expand);
463 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
464 setOperationAction(ISD::VSELECT, VT, Expand);
465 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
467 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
468 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
469 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
470 setTruncStoreAction(VT, InnerVT, Expand);
472 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
473 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
474 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
477 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
478 // with merges, splats, etc.
479 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
481 setOperationAction(ISD::AND , MVT::v4i32, Legal);
482 setOperationAction(ISD::OR , MVT::v4i32, Legal);
483 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
484 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
485 setOperationAction(ISD::SELECT, MVT::v4i32,
486 Subtarget.useCRBits() ? Legal : Expand);
487 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
488 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
489 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
490 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
491 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
492 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
493 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
494 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
495 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
497 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
498 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
499 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
500 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
502 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
503 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
505 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
506 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
507 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
510 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
511 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
512 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
514 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
515 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
517 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
518 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
519 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
520 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
522 // Altivec does not contain unordered floating-point compare instructions
523 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
524 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
525 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
526 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
528 if (Subtarget.hasVSX()) {
529 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
530 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
532 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
533 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
534 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
535 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
536 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
538 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
540 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
541 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
543 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
544 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
546 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
547 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
548 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
549 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
550 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
552 // Share the Altivec comparison restrictions.
553 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
554 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
555 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
556 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
558 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
559 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
561 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
563 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
565 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
566 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
568 // VSX v2i64 only supports non-arithmetic operations.
569 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
570 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
572 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
573 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
574 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
576 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
578 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
579 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
580 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
581 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
583 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
585 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
586 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
587 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
588 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
590 // Vector operation legalization checks the result type of
591 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
592 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
593 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
594 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
595 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
597 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
601 if (Subtarget.has64BitSupport())
602 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
604 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
607 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
608 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
611 setBooleanContents(ZeroOrOneBooleanContent);
612 // Altivec instructions set fields to all zeros or all ones.
613 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
616 // These libcalls are not available in 32-bit.
617 setLibcallName(RTLIB::SHL_I128, nullptr);
618 setLibcallName(RTLIB::SRL_I128, nullptr);
619 setLibcallName(RTLIB::SRA_I128, nullptr);
623 setStackPointerRegisterToSaveRestore(PPC::X1);
624 setExceptionPointerRegister(PPC::X3);
625 setExceptionSelectorRegister(PPC::X4);
627 setStackPointerRegisterToSaveRestore(PPC::R1);
628 setExceptionPointerRegister(PPC::R3);
629 setExceptionSelectorRegister(PPC::R4);
632 // We have target-specific dag combine patterns for the following nodes:
633 setTargetDAGCombine(ISD::SINT_TO_FP);
634 if (Subtarget.hasFPCVT())
635 setTargetDAGCombine(ISD::UINT_TO_FP);
636 setTargetDAGCombine(ISD::LOAD);
637 setTargetDAGCombine(ISD::STORE);
638 setTargetDAGCombine(ISD::BR_CC);
639 if (Subtarget.useCRBits())
640 setTargetDAGCombine(ISD::BRCOND);
641 setTargetDAGCombine(ISD::BSWAP);
642 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
643 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
644 setTargetDAGCombine(ISD::INTRINSIC_VOID);
646 setTargetDAGCombine(ISD::SIGN_EXTEND);
647 setTargetDAGCombine(ISD::ZERO_EXTEND);
648 setTargetDAGCombine(ISD::ANY_EXTEND);
650 if (Subtarget.useCRBits()) {
651 setTargetDAGCombine(ISD::TRUNCATE);
652 setTargetDAGCombine(ISD::SETCC);
653 setTargetDAGCombine(ISD::SELECT_CC);
656 // Use reciprocal estimates.
657 if (TM.Options.UnsafeFPMath) {
658 setTargetDAGCombine(ISD::FDIV);
659 setTargetDAGCombine(ISD::FSQRT);
662 // Darwin long double math library functions have $LDBL128 appended.
663 if (Subtarget.isDarwin()) {
664 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
665 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
666 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
667 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
668 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
669 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
670 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
671 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
672 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
673 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
676 // With 32 condition bits, we don't need to sink (and duplicate) compares
677 // aggressively in CodeGenPrep.
678 if (Subtarget.useCRBits())
679 setHasMultipleConditionRegisters();
681 setMinFunctionAlignment(2);
682 if (Subtarget.isDarwin())
683 setPrefFunctionAlignment(4);
685 switch (Subtarget.getDarwinDirective()) {
689 case PPC::DIR_E500mc:
698 setPrefFunctionAlignment(4);
699 setPrefLoopAlignment(4);
703 setInsertFencesForAtomic(true);
705 if (Subtarget.enableMachineScheduler())
706 setSchedulingPreference(Sched::Source);
708 setSchedulingPreference(Sched::Hybrid);
710 computeRegisterProperties();
712 // The Freescale cores do better with aggressive inlining of memcpy and
713 // friends. GCC uses same threshold of 128 bytes (= 32 word stores).
714 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
715 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
716 MaxStoresPerMemset = 32;
717 MaxStoresPerMemsetOptSize = 16;
718 MaxStoresPerMemcpy = 32;
719 MaxStoresPerMemcpyOptSize = 8;
720 MaxStoresPerMemmove = 32;
721 MaxStoresPerMemmoveOptSize = 8;
725 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
726 /// the desired ByVal argument alignment.
727 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
728 unsigned MaxMaxAlign) {
729 if (MaxAlign == MaxMaxAlign)
731 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
732 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
734 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
736 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
737 unsigned EltAlign = 0;
738 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
739 if (EltAlign > MaxAlign)
741 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
742 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
743 unsigned EltAlign = 0;
744 getMaxByValAlign(STy->getElementType(i), EltAlign, MaxMaxAlign);
745 if (EltAlign > MaxAlign)
747 if (MaxAlign == MaxMaxAlign)
753 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
754 /// function arguments in the caller parameter area.
755 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
756 // Darwin passes everything on 4 byte boundary.
757 if (Subtarget.isDarwin())
760 // 16byte and wider vectors are passed on 16byte boundary.
761 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
762 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
763 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
764 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
768 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
770 default: return nullptr;
771 case PPCISD::FSEL: return "PPCISD::FSEL";
772 case PPCISD::FCFID: return "PPCISD::FCFID";
773 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
774 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
775 case PPCISD::FRE: return "PPCISD::FRE";
776 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
777 case PPCISD::STFIWX: return "PPCISD::STFIWX";
778 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
779 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
780 case PPCISD::VPERM: return "PPCISD::VPERM";
781 case PPCISD::CMPB: return "PPCISD::CMPB";
782 case PPCISD::Hi: return "PPCISD::Hi";
783 case PPCISD::Lo: return "PPCISD::Lo";
784 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
785 case PPCISD::LOAD: return "PPCISD::LOAD";
786 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
787 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
788 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
789 case PPCISD::SRL: return "PPCISD::SRL";
790 case PPCISD::SRA: return "PPCISD::SRA";
791 case PPCISD::SHL: return "PPCISD::SHL";
792 case PPCISD::CALL: return "PPCISD::CALL";
793 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
794 case PPCISD::CALL_TLS: return "PPCISD::CALL_TLS";
795 case PPCISD::CALL_NOP_TLS: return "PPCISD::CALL_NOP_TLS";
796 case PPCISD::MTCTR: return "PPCISD::MTCTR";
797 case PPCISD::BCTRL: return "PPCISD::BCTRL";
798 case PPCISD::BCTRL_LOAD_TOC: return "PPCISD::BCTRL_LOAD_TOC";
799 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
800 case PPCISD::READ_TIME_BASE: return "PPCISD::READ_TIME_BASE";
801 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
802 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
803 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
804 case PPCISD::VCMP: return "PPCISD::VCMP";
805 case PPCISD::VCMPo: return "PPCISD::VCMPo";
806 case PPCISD::LBRX: return "PPCISD::LBRX";
807 case PPCISD::STBRX: return "PPCISD::STBRX";
808 case PPCISD::LARX: return "PPCISD::LARX";
809 case PPCISD::STCX: return "PPCISD::STCX";
810 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
811 case PPCISD::BDNZ: return "PPCISD::BDNZ";
812 case PPCISD::BDZ: return "PPCISD::BDZ";
813 case PPCISD::MFFS: return "PPCISD::MFFS";
814 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
815 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
816 case PPCISD::CR6SET: return "PPCISD::CR6SET";
817 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
818 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
819 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
820 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
821 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
822 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
823 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
824 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
825 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
826 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
827 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
828 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
829 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
830 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
831 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
832 case PPCISD::SC: return "PPCISD::SC";
836 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
838 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
839 return VT.changeVectorElementTypeToInteger();
842 bool PPCTargetLowering::enableAggressiveFMAFusion(EVT VT) const {
843 assert(VT.isFloatingPoint() && "Non-floating-point FMA?");
847 //===----------------------------------------------------------------------===//
848 // Node matching predicates, for use by the tblgen matching code.
849 //===----------------------------------------------------------------------===//
851 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
852 static bool isFloatingPointZero(SDValue Op) {
853 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
854 return CFP->getValueAPF().isZero();
855 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
856 // Maybe this has already been legalized into the constant pool?
857 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
858 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
859 return CFP->getValueAPF().isZero();
864 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
865 /// true if Op is undef or if it matches the specified value.
866 static bool isConstantOrUndef(int Op, int Val) {
867 return Op < 0 || Op == Val;
870 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
871 /// VPKUHUM instruction.
872 /// The ShuffleKind distinguishes between big-endian operations with
873 /// two different inputs (0), either-endian operations with two identical
874 /// inputs (1), and little-endian operantion with two different inputs (2).
875 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
876 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
878 bool IsLE = DAG.getSubtarget().getDataLayout()->isLittleEndian();
879 if (ShuffleKind == 0) {
882 for (unsigned i = 0; i != 16; ++i)
883 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
885 } else if (ShuffleKind == 2) {
888 for (unsigned i = 0; i != 16; ++i)
889 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
891 } else if (ShuffleKind == 1) {
892 unsigned j = IsLE ? 0 : 1;
893 for (unsigned i = 0; i != 8; ++i)
894 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
895 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
901 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
902 /// VPKUWUM instruction.
903 /// The ShuffleKind distinguishes between big-endian operations with
904 /// two different inputs (0), either-endian operations with two identical
905 /// inputs (1), and little-endian operantion with two different inputs (2).
906 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
907 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
909 bool IsLE = DAG.getSubtarget().getDataLayout()->isLittleEndian();
910 if (ShuffleKind == 0) {
913 for (unsigned i = 0; i != 16; i += 2)
914 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
915 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
917 } else if (ShuffleKind == 2) {
920 for (unsigned i = 0; i != 16; i += 2)
921 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
922 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
924 } else if (ShuffleKind == 1) {
925 unsigned j = IsLE ? 0 : 2;
926 for (unsigned i = 0; i != 8; i += 2)
927 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
928 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
929 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
930 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
936 /// isVMerge - Common function, used to match vmrg* shuffles.
938 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
939 unsigned LHSStart, unsigned RHSStart) {
940 if (N->getValueType(0) != MVT::v16i8)
942 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
943 "Unsupported merge size!");
945 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
946 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
947 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
948 LHSStart+j+i*UnitSize) ||
949 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
950 RHSStart+j+i*UnitSize))
956 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
957 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
958 /// The ShuffleKind distinguishes between big-endian merges with two
959 /// different inputs (0), either-endian merges with two identical inputs (1),
960 /// and little-endian merges with two different inputs (2). For the latter,
961 /// the input operands are swapped (see PPCInstrAltivec.td).
962 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
963 unsigned ShuffleKind, SelectionDAG &DAG) {
964 if (DAG.getSubtarget().getDataLayout()->isLittleEndian()) {
965 if (ShuffleKind == 1) // unary
966 return isVMerge(N, UnitSize, 0, 0);
967 else if (ShuffleKind == 2) // swapped
968 return isVMerge(N, UnitSize, 0, 16);
972 if (ShuffleKind == 1) // unary
973 return isVMerge(N, UnitSize, 8, 8);
974 else if (ShuffleKind == 0) // normal
975 return isVMerge(N, UnitSize, 8, 24);
981 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
982 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
983 /// The ShuffleKind distinguishes between big-endian merges with two
984 /// different inputs (0), either-endian merges with two identical inputs (1),
985 /// and little-endian merges with two different inputs (2). For the latter,
986 /// the input operands are swapped (see PPCInstrAltivec.td).
987 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
988 unsigned ShuffleKind, SelectionDAG &DAG) {
989 if (DAG.getSubtarget().getDataLayout()->isLittleEndian()) {
990 if (ShuffleKind == 1) // unary
991 return isVMerge(N, UnitSize, 8, 8);
992 else if (ShuffleKind == 2) // swapped
993 return isVMerge(N, UnitSize, 8, 24);
997 if (ShuffleKind == 1) // unary
998 return isVMerge(N, UnitSize, 0, 0);
999 else if (ShuffleKind == 0) // normal
1000 return isVMerge(N, UnitSize, 0, 16);
1007 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
1008 /// amount, otherwise return -1.
1009 /// The ShuffleKind distinguishes between big-endian operations with two
1010 /// different inputs (0), either-endian operations with two identical inputs
1011 /// (1), and little-endian operations with two different inputs (2). For the
1012 /// latter, the input operands are swapped (see PPCInstrAltivec.td).
1013 int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
1014 SelectionDAG &DAG) {
1015 if (N->getValueType(0) != MVT::v16i8)
1018 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1020 // Find the first non-undef value in the shuffle mask.
1022 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
1025 if (i == 16) return -1; // all undef.
1027 // Otherwise, check to see if the rest of the elements are consecutively
1028 // numbered from this value.
1029 unsigned ShiftAmt = SVOp->getMaskElt(i);
1030 if (ShiftAmt < i) return -1;
1033 bool isLE = DAG.getTarget().getSubtargetImpl()->getDataLayout()->
1036 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
1037 // Check the rest of the elements to see if they are consecutive.
1038 for (++i; i != 16; ++i)
1039 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1041 } else if (ShuffleKind == 1) {
1042 // Check the rest of the elements to see if they are consecutive.
1043 for (++i; i != 16; ++i)
1044 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1049 if (ShuffleKind == 2 && isLE)
1050 ShiftAmt = 16 - ShiftAmt;
1055 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1056 /// specifies a splat of a single element that is suitable for input to
1057 /// VSPLTB/VSPLTH/VSPLTW.
1058 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1059 assert(N->getValueType(0) == MVT::v16i8 &&
1060 (EltSize == 1 || EltSize == 2 || EltSize == 4));
1062 // This is a splat operation if each element of the permute is the same, and
1063 // if the value doesn't reference the second vector.
1064 unsigned ElementBase = N->getMaskElt(0);
1066 // FIXME: Handle UNDEF elements too!
1067 if (ElementBase >= 16)
1070 // Check that the indices are consecutive, in the case of a multi-byte element
1071 // splatted with a v16i8 mask.
1072 for (unsigned i = 1; i != EltSize; ++i)
1073 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1076 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1077 if (N->getMaskElt(i) < 0) continue;
1078 for (unsigned j = 0; j != EltSize; ++j)
1079 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1085 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
1087 bool PPC::isAllNegativeZeroVector(SDNode *N) {
1088 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
1090 APInt APVal, APUndef;
1094 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
1095 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
1096 return CFP->getValueAPF().isNegZero();
1101 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1102 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1103 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1104 SelectionDAG &DAG) {
1105 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1106 assert(isSplatShuffleMask(SVOp, EltSize));
1107 if (DAG.getSubtarget().getDataLayout()->isLittleEndian())
1108 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1110 return SVOp->getMaskElt(0) / EltSize;
1113 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1114 /// by using a vspltis[bhw] instruction of the specified element size, return
1115 /// the constant being splatted. The ByteSize field indicates the number of
1116 /// bytes of each element [124] -> [bhw].
1117 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1118 SDValue OpVal(nullptr, 0);
1120 // If ByteSize of the splat is bigger than the element size of the
1121 // build_vector, then we have a case where we are checking for a splat where
1122 // multiple elements of the buildvector are folded together into a single
1123 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1124 unsigned EltSize = 16/N->getNumOperands();
1125 if (EltSize < ByteSize) {
1126 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1127 SDValue UniquedVals[4];
1128 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1130 // See if all of the elements in the buildvector agree across.
1131 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1132 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1133 // If the element isn't a constant, bail fully out.
1134 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1137 if (!UniquedVals[i&(Multiple-1)].getNode())
1138 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1139 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1140 return SDValue(); // no match.
1143 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1144 // either constant or undef values that are identical for each chunk. See
1145 // if these chunks can form into a larger vspltis*.
1147 // Check to see if all of the leading entries are either 0 or -1. If
1148 // neither, then this won't fit into the immediate field.
1149 bool LeadingZero = true;
1150 bool LeadingOnes = true;
1151 for (unsigned i = 0; i != Multiple-1; ++i) {
1152 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1154 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
1155 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
1157 // Finally, check the least significant entry.
1159 if (!UniquedVals[Multiple-1].getNode())
1160 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
1161 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1163 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
1166 if (!UniquedVals[Multiple-1].getNode())
1167 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
1168 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1169 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1170 return DAG.getTargetConstant(Val, MVT::i32);
1176 // Check to see if this buildvec has a single non-undef value in its elements.
1177 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1178 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1179 if (!OpVal.getNode())
1180 OpVal = N->getOperand(i);
1181 else if (OpVal != N->getOperand(i))
1185 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1187 unsigned ValSizeInBytes = EltSize;
1189 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1190 Value = CN->getZExtValue();
1191 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1192 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1193 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1196 // If the splat value is larger than the element value, then we can never do
1197 // this splat. The only case that we could fit the replicated bits into our
1198 // immediate field for would be zero, and we prefer to use vxor for it.
1199 if (ValSizeInBytes < ByteSize) return SDValue();
1201 // If the element value is larger than the splat value, cut it in half and
1202 // check to see if the two halves are equal. Continue doing this until we
1203 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
1204 while (ValSizeInBytes > ByteSize) {
1205 ValSizeInBytes >>= 1;
1207 // If the top half equals the bottom half, we're still ok.
1208 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
1209 (Value & ((1 << (8*ValSizeInBytes))-1)))
1213 // Properly sign extend the value.
1214 int MaskVal = SignExtend32(Value, ByteSize * 8);
1216 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1217 if (MaskVal == 0) return SDValue();
1219 // Finally, if this value fits in a 5 bit sext field, return it
1220 if (SignExtend32<5>(MaskVal) == MaskVal)
1221 return DAG.getTargetConstant(MaskVal, MVT::i32);
1225 //===----------------------------------------------------------------------===//
1226 // Addressing Mode Selection
1227 //===----------------------------------------------------------------------===//
1229 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1230 /// or 64-bit immediate, and if the value can be accurately represented as a
1231 /// sign extension from a 16-bit value. If so, this returns true and the
1233 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1234 if (!isa<ConstantSDNode>(N))
1237 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1238 if (N->getValueType(0) == MVT::i32)
1239 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1241 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1243 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1244 return isIntS16Immediate(Op.getNode(), Imm);
1248 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1249 /// can be represented as an indexed [r+r] operation. Returns false if it
1250 /// can be more efficiently represented with [r+imm].
1251 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1253 SelectionDAG &DAG) const {
1255 if (N.getOpcode() == ISD::ADD) {
1256 if (isIntS16Immediate(N.getOperand(1), imm))
1257 return false; // r+i
1258 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1259 return false; // r+i
1261 Base = N.getOperand(0);
1262 Index = N.getOperand(1);
1264 } else if (N.getOpcode() == ISD::OR) {
1265 if (isIntS16Immediate(N.getOperand(1), imm))
1266 return false; // r+i can fold it if we can.
1268 // If this is an or of disjoint bitfields, we can codegen this as an add
1269 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1271 APInt LHSKnownZero, LHSKnownOne;
1272 APInt RHSKnownZero, RHSKnownOne;
1273 DAG.computeKnownBits(N.getOperand(0),
1274 LHSKnownZero, LHSKnownOne);
1276 if (LHSKnownZero.getBoolValue()) {
1277 DAG.computeKnownBits(N.getOperand(1),
1278 RHSKnownZero, RHSKnownOne);
1279 // If all of the bits are known zero on the LHS or RHS, the add won't
1281 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1282 Base = N.getOperand(0);
1283 Index = N.getOperand(1);
1292 // If we happen to be doing an i64 load or store into a stack slot that has
1293 // less than a 4-byte alignment, then the frame-index elimination may need to
1294 // use an indexed load or store instruction (because the offset may not be a
1295 // multiple of 4). The extra register needed to hold the offset comes from the
1296 // register scavenger, and it is possible that the scavenger will need to use
1297 // an emergency spill slot. As a result, we need to make sure that a spill slot
1298 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1300 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1301 // FIXME: This does not handle the LWA case.
1305 // NOTE: We'll exclude negative FIs here, which come from argument
1306 // lowering, because there are no known test cases triggering this problem
1307 // using packed structures (or similar). We can remove this exclusion if
1308 // we find such a test case. The reason why this is so test-case driven is
1309 // because this entire 'fixup' is only to prevent crashes (from the
1310 // register scavenger) on not-really-valid inputs. For example, if we have:
1312 // %b = bitcast i1* %a to i64*
1313 // store i64* a, i64 b
1314 // then the store should really be marked as 'align 1', but is not. If it
1315 // were marked as 'align 1' then the indexed form would have been
1316 // instruction-selected initially, and the problem this 'fixup' is preventing
1317 // won't happen regardless.
1321 MachineFunction &MF = DAG.getMachineFunction();
1322 MachineFrameInfo *MFI = MF.getFrameInfo();
1324 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1328 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1329 FuncInfo->setHasNonRISpills();
1332 /// Returns true if the address N can be represented by a base register plus
1333 /// a signed 16-bit displacement [r+imm], and if it is not better
1334 /// represented as reg+reg. If Aligned is true, only accept displacements
1335 /// suitable for STD and friends, i.e. multiples of 4.
1336 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1339 bool Aligned) const {
1340 // FIXME dl should come from parent load or store, not from address
1342 // If this can be more profitably realized as r+r, fail.
1343 if (SelectAddressRegReg(N, Disp, Base, DAG))
1346 if (N.getOpcode() == ISD::ADD) {
1348 if (isIntS16Immediate(N.getOperand(1), imm) &&
1349 (!Aligned || (imm & 3) == 0)) {
1350 Disp = DAG.getTargetConstant(imm, N.getValueType());
1351 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1352 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1353 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1355 Base = N.getOperand(0);
1357 return true; // [r+i]
1358 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1359 // Match LOAD (ADD (X, Lo(G))).
1360 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1361 && "Cannot handle constant offsets yet!");
1362 Disp = N.getOperand(1).getOperand(0); // The global address.
1363 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1364 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1365 Disp.getOpcode() == ISD::TargetConstantPool ||
1366 Disp.getOpcode() == ISD::TargetJumpTable);
1367 Base = N.getOperand(0);
1368 return true; // [&g+r]
1370 } else if (N.getOpcode() == ISD::OR) {
1372 if (isIntS16Immediate(N.getOperand(1), imm) &&
1373 (!Aligned || (imm & 3) == 0)) {
1374 // If this is an or of disjoint bitfields, we can codegen this as an add
1375 // (for better address arithmetic) if the LHS and RHS of the OR are
1376 // provably disjoint.
1377 APInt LHSKnownZero, LHSKnownOne;
1378 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1380 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1381 // If all of the bits are known zero on the LHS or RHS, the add won't
1383 if (FrameIndexSDNode *FI =
1384 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1385 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1386 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1388 Base = N.getOperand(0);
1390 Disp = DAG.getTargetConstant(imm, N.getValueType());
1394 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1395 // Loading from a constant address.
1397 // If this address fits entirely in a 16-bit sext immediate field, codegen
1400 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1401 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1402 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1403 CN->getValueType(0));
1407 // Handle 32-bit sext immediates with LIS + addr mode.
1408 if ((CN->getValueType(0) == MVT::i32 ||
1409 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1410 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1411 int Addr = (int)CN->getZExtValue();
1413 // Otherwise, break this down into an LIS + disp.
1414 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1416 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1417 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1418 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1423 Disp = DAG.getTargetConstant(0, getPointerTy());
1424 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1425 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1426 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1429 return true; // [r+0]
1432 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1433 /// represented as an indexed [r+r] operation.
1434 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1436 SelectionDAG &DAG) const {
1437 // Check to see if we can easily represent this as an [r+r] address. This
1438 // will fail if it thinks that the address is more profitably represented as
1439 // reg+imm, e.g. where imm = 0.
1440 if (SelectAddressRegReg(N, Base, Index, DAG))
1443 // If the operand is an addition, always emit this as [r+r], since this is
1444 // better (for code size, and execution, as the memop does the add for free)
1445 // than emitting an explicit add.
1446 if (N.getOpcode() == ISD::ADD) {
1447 Base = N.getOperand(0);
1448 Index = N.getOperand(1);
1452 // Otherwise, do it the hard way, using R0 as the base register.
1453 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1459 /// getPreIndexedAddressParts - returns true by value, base pointer and
1460 /// offset pointer and addressing mode by reference if the node's address
1461 /// can be legally represented as pre-indexed load / store address.
1462 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1464 ISD::MemIndexedMode &AM,
1465 SelectionDAG &DAG) const {
1466 if (DisablePPCPreinc) return false;
1472 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1473 Ptr = LD->getBasePtr();
1474 VT = LD->getMemoryVT();
1475 Alignment = LD->getAlignment();
1476 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1477 Ptr = ST->getBasePtr();
1478 VT = ST->getMemoryVT();
1479 Alignment = ST->getAlignment();
1484 // PowerPC doesn't have preinc load/store instructions for vectors.
1488 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1490 // Common code will reject creating a pre-inc form if the base pointer
1491 // is a frame index, or if N is a store and the base pointer is either
1492 // the same as or a predecessor of the value being stored. Check for
1493 // those situations here, and try with swapped Base/Offset instead.
1496 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1499 SDValue Val = cast<StoreSDNode>(N)->getValue();
1500 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1505 std::swap(Base, Offset);
1511 // LDU/STU can only handle immediates that are a multiple of 4.
1512 if (VT != MVT::i64) {
1513 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1516 // LDU/STU need an address with at least 4-byte alignment.
1520 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1524 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1525 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1526 // sext i32 to i64 when addr mode is r+i.
1527 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1528 LD->getExtensionType() == ISD::SEXTLOAD &&
1529 isa<ConstantSDNode>(Offset))
1537 //===----------------------------------------------------------------------===//
1538 // LowerOperation implementation
1539 //===----------------------------------------------------------------------===//
1541 /// GetLabelAccessInfo - Return true if we should reference labels using a
1542 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1543 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1544 unsigned &LoOpFlags,
1545 const GlobalValue *GV = nullptr) {
1546 HiOpFlags = PPCII::MO_HA;
1547 LoOpFlags = PPCII::MO_LO;
1549 // Don't use the pic base if not in PIC relocation model.
1550 bool isPIC = TM.getRelocationModel() == Reloc::PIC_;
1553 HiOpFlags |= PPCII::MO_PIC_FLAG;
1554 LoOpFlags |= PPCII::MO_PIC_FLAG;
1557 // If this is a reference to a global value that requires a non-lazy-ptr, make
1558 // sure that instruction lowering adds it.
1559 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1560 HiOpFlags |= PPCII::MO_NLP_FLAG;
1561 LoOpFlags |= PPCII::MO_NLP_FLAG;
1563 if (GV->hasHiddenVisibility()) {
1564 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1565 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1572 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1573 SelectionDAG &DAG) {
1574 EVT PtrVT = HiPart.getValueType();
1575 SDValue Zero = DAG.getConstant(0, PtrVT);
1578 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1579 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1581 // With PIC, the first instruction is actually "GR+hi(&G)".
1583 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1584 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1586 // Generate non-pic code that has direct accesses to the constant pool.
1587 // The address of the global is just (hi(&g)+lo(&g)).
1588 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1591 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1592 SelectionDAG &DAG) const {
1593 EVT PtrVT = Op.getValueType();
1594 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1595 const Constant *C = CP->getConstVal();
1597 // 64-bit SVR4 ABI code is always position-independent.
1598 // The actual address of the GlobalValue is stored in the TOC.
1599 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1600 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1601 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1602 DAG.getRegister(PPC::X2, MVT::i64));
1605 unsigned MOHiFlag, MOLoFlag;
1606 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1608 if (isPIC && Subtarget.isSVR4ABI()) {
1609 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
1610 PPCII::MO_PIC_FLAG);
1612 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1613 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1617 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1619 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1620 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1623 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1624 EVT PtrVT = Op.getValueType();
1625 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1627 // 64-bit SVR4 ABI code is always position-independent.
1628 // The actual address of the GlobalValue is stored in the TOC.
1629 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1630 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1631 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1632 DAG.getRegister(PPC::X2, MVT::i64));
1635 unsigned MOHiFlag, MOLoFlag;
1636 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1638 if (isPIC && Subtarget.isSVR4ABI()) {
1639 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
1640 PPCII::MO_PIC_FLAG);
1642 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), PtrVT, GA,
1643 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1646 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1647 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1648 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1651 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1652 SelectionDAG &DAG) const {
1653 EVT PtrVT = Op.getValueType();
1654 BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
1655 const BlockAddress *BA = BASDN->getBlockAddress();
1657 // 64-bit SVR4 ABI code is always position-independent.
1658 // The actual BlockAddress is stored in the TOC.
1659 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1660 SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
1661 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(BASDN), MVT::i64, GA,
1662 DAG.getRegister(PPC::X2, MVT::i64));
1665 unsigned MOHiFlag, MOLoFlag;
1666 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1667 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1668 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1669 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1672 // Generate a call to __tls_get_addr for the given GOT entry Op.
1673 std::pair<SDValue,SDValue>
1674 PPCTargetLowering::lowerTLSCall(SDValue Op, SDLoc dl,
1675 SelectionDAG &DAG) const {
1677 Type *IntPtrTy = getDataLayout()->getIntPtrType(*DAG.getContext());
1678 TargetLowering::ArgListTy Args;
1679 TargetLowering::ArgListEntry Entry;
1681 Entry.Ty = IntPtrTy;
1682 Args.push_back(Entry);
1684 TargetLowering::CallLoweringInfo CLI(DAG);
1685 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
1686 .setCallee(CallingConv::C, IntPtrTy,
1687 DAG.getTargetExternalSymbol("__tls_get_addr", getPointerTy()),
1688 std::move(Args), 0);
1690 return LowerCallTo(CLI);
1693 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1694 SelectionDAG &DAG) const {
1696 // FIXME: TLS addresses currently use medium model code sequences,
1697 // which is the most useful form. Eventually support for small and
1698 // large models could be added if users need it, at the cost of
1699 // additional complexity.
1700 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1702 const GlobalValue *GV = GA->getGlobal();
1703 EVT PtrVT = getPointerTy();
1704 bool is64bit = Subtarget.isPPC64();
1705 const Module *M = DAG.getMachineFunction().getFunction()->getParent();
1706 PICLevel::Level picLevel = M->getPICLevel();
1708 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1710 if (Model == TLSModel::LocalExec) {
1711 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1712 PPCII::MO_TPREL_HA);
1713 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1714 PPCII::MO_TPREL_LO);
1715 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1716 is64bit ? MVT::i64 : MVT::i32);
1717 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1718 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1721 if (Model == TLSModel::InitialExec) {
1722 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1723 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1727 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1728 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1729 PtrVT, GOTReg, TGA);
1731 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
1732 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1733 PtrVT, TGA, GOTPtr);
1734 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
1737 if (Model == TLSModel::GeneralDynamic) {
1738 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1742 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1743 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1746 if (picLevel == PICLevel::Small)
1747 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
1749 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
1751 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1753 std::pair<SDValue, SDValue> CallResult = lowerTLSCall(GOTEntry, dl, DAG);
1754 return CallResult.first;
1757 if (Model == TLSModel::LocalDynamic) {
1758 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1762 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1763 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1766 if (picLevel == PICLevel::Small)
1767 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
1769 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
1771 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1773 std::pair<SDValue, SDValue> CallResult = lowerTLSCall(GOTEntry, dl, DAG);
1774 SDValue TLSAddr = CallResult.first;
1775 SDValue Chain = CallResult.second;
1776 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1777 Chain, TLSAddr, TGA);
1778 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1781 llvm_unreachable("Unknown TLS model!");
1784 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1785 SelectionDAG &DAG) const {
1786 EVT PtrVT = Op.getValueType();
1787 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1789 const GlobalValue *GV = GSDN->getGlobal();
1791 // 64-bit SVR4 ABI code is always position-independent.
1792 // The actual address of the GlobalValue is stored in the TOC.
1793 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1794 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1795 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1796 DAG.getRegister(PPC::X2, MVT::i64));
1799 unsigned MOHiFlag, MOLoFlag;
1800 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1802 if (isPIC && Subtarget.isSVR4ABI()) {
1803 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
1805 PPCII::MO_PIC_FLAG);
1806 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1807 DAG.getNode(PPCISD::GlobalBaseReg, DL, MVT::i32));
1811 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1813 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1815 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1817 // If the global reference is actually to a non-lazy-pointer, we have to do an
1818 // extra load to get the address of the global.
1819 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1820 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1821 false, false, false, 0);
1825 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1826 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1829 if (Op.getValueType() == MVT::v2i64) {
1830 // When the operands themselves are v2i64 values, we need to do something
1831 // special because VSX has no underlying comparison operations for these.
1832 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
1833 // Equality can be handled by casting to the legal type for Altivec
1834 // comparisons, everything else needs to be expanded.
1835 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1836 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
1837 DAG.getSetCC(dl, MVT::v4i32,
1838 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
1839 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
1846 // We handle most of these in the usual way.
1850 // If we're comparing for equality to zero, expose the fact that this is
1851 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1852 // fold the new nodes.
1853 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1854 if (C->isNullValue() && CC == ISD::SETEQ) {
1855 EVT VT = Op.getOperand(0).getValueType();
1856 SDValue Zext = Op.getOperand(0);
1857 if (VT.bitsLT(MVT::i32)) {
1859 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1861 unsigned Log2b = Log2_32(VT.getSizeInBits());
1862 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1863 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1864 DAG.getConstant(Log2b, MVT::i32));
1865 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1867 // Leave comparisons against 0 and -1 alone for now, since they're usually
1868 // optimized. FIXME: revisit this when we can custom lower all setcc
1870 if (C->isAllOnesValue() || C->isNullValue())
1874 // If we have an integer seteq/setne, turn it into a compare against zero
1875 // by xor'ing the rhs with the lhs, which is faster than setting a
1876 // condition register, reading it back out, and masking the correct bit. The
1877 // normal approach here uses sub to do this instead of xor. Using xor exposes
1878 // the result to other bit-twiddling opportunities.
1879 EVT LHSVT = Op.getOperand(0).getValueType();
1880 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1881 EVT VT = Op.getValueType();
1882 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1884 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1889 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1890 const PPCSubtarget &Subtarget) const {
1891 SDNode *Node = Op.getNode();
1892 EVT VT = Node->getValueType(0);
1893 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1894 SDValue InChain = Node->getOperand(0);
1895 SDValue VAListPtr = Node->getOperand(1);
1896 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1899 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1902 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1903 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1904 false, false, false, 0);
1905 InChain = GprIndex.getValue(1);
1907 if (VT == MVT::i64) {
1908 // Check if GprIndex is even
1909 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1910 DAG.getConstant(1, MVT::i32));
1911 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1912 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1913 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1914 DAG.getConstant(1, MVT::i32));
1915 // Align GprIndex to be even if it isn't
1916 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1920 // fpr index is 1 byte after gpr
1921 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1922 DAG.getConstant(1, MVT::i32));
1925 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1926 FprPtr, MachinePointerInfo(SV), MVT::i8,
1927 false, false, false, 0);
1928 InChain = FprIndex.getValue(1);
1930 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1931 DAG.getConstant(8, MVT::i32));
1933 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1934 DAG.getConstant(4, MVT::i32));
1937 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1938 MachinePointerInfo(), false, false,
1940 InChain = OverflowArea.getValue(1);
1942 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1943 MachinePointerInfo(), false, false,
1945 InChain = RegSaveArea.getValue(1);
1947 // select overflow_area if index > 8
1948 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1949 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1951 // adjustment constant gpr_index * 4/8
1952 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1953 VT.isInteger() ? GprIndex : FprIndex,
1954 DAG.getConstant(VT.isInteger() ? 4 : 8,
1957 // OurReg = RegSaveArea + RegConstant
1958 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1961 // Floating types are 32 bytes into RegSaveArea
1962 if (VT.isFloatingPoint())
1963 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1964 DAG.getConstant(32, MVT::i32));
1966 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1967 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1968 VT.isInteger() ? GprIndex : FprIndex,
1969 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1972 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1973 VT.isInteger() ? VAListPtr : FprPtr,
1974 MachinePointerInfo(SV),
1975 MVT::i8, false, false, 0);
1977 // determine if we should load from reg_save_area or overflow_area
1978 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1980 // increase overflow_area by 4/8 if gpr/fpr > 8
1981 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1982 DAG.getConstant(VT.isInteger() ? 4 : 8,
1985 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1988 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1990 MachinePointerInfo(),
1991 MVT::i32, false, false, 0);
1993 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1994 false, false, false, 0);
1997 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
1998 const PPCSubtarget &Subtarget) const {
1999 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
2001 // We have to copy the entire va_list struct:
2002 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
2003 return DAG.getMemcpy(Op.getOperand(0), Op,
2004 Op.getOperand(1), Op.getOperand(2),
2005 DAG.getConstant(12, MVT::i32), 8, false, true,
2006 MachinePointerInfo(), MachinePointerInfo());
2009 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
2010 SelectionDAG &DAG) const {
2011 return Op.getOperand(0);
2014 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
2015 SelectionDAG &DAG) const {
2016 SDValue Chain = Op.getOperand(0);
2017 SDValue Trmp = Op.getOperand(1); // trampoline
2018 SDValue FPtr = Op.getOperand(2); // nested function
2019 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
2022 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2023 bool isPPC64 = (PtrVT == MVT::i64);
2025 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
2028 TargetLowering::ArgListTy Args;
2029 TargetLowering::ArgListEntry Entry;
2031 Entry.Ty = IntPtrTy;
2032 Entry.Node = Trmp; Args.push_back(Entry);
2034 // TrampSize == (isPPC64 ? 48 : 40);
2035 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
2036 isPPC64 ? MVT::i64 : MVT::i32);
2037 Args.push_back(Entry);
2039 Entry.Node = FPtr; Args.push_back(Entry);
2040 Entry.Node = Nest; Args.push_back(Entry);
2042 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
2043 TargetLowering::CallLoweringInfo CLI(DAG);
2044 CLI.setDebugLoc(dl).setChain(Chain)
2045 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
2046 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
2047 std::move(Args), 0);
2049 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2050 return CallResult.second;
2053 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
2054 const PPCSubtarget &Subtarget) const {
2055 MachineFunction &MF = DAG.getMachineFunction();
2056 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2060 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
2061 // vastart just stores the address of the VarArgsFrameIndex slot into the
2062 // memory location argument.
2063 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2064 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2065 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2066 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2067 MachinePointerInfo(SV),
2071 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
2072 // We suppose the given va_list is already allocated.
2075 // char gpr; /* index into the array of 8 GPRs
2076 // * stored in the register save area
2077 // * gpr=0 corresponds to r3,
2078 // * gpr=1 to r4, etc.
2080 // char fpr; /* index into the array of 8 FPRs
2081 // * stored in the register save area
2082 // * fpr=0 corresponds to f1,
2083 // * fpr=1 to f2, etc.
2085 // char *overflow_arg_area;
2086 // /* location on stack that holds
2087 // * the next overflow argument
2089 // char *reg_save_area;
2090 // /* where r3:r10 and f1:f8 (if saved)
2096 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
2097 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
2100 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2102 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
2104 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2107 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2108 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
2110 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2111 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
2113 uint64_t FPROffset = 1;
2114 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
2116 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2118 // Store first byte : number of int regs
2119 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
2121 MachinePointerInfo(SV),
2122 MVT::i8, false, false, 0);
2123 uint64_t nextOffset = FPROffset;
2124 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2127 // Store second byte : number of float regs
2128 SDValue secondStore =
2129 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2130 MachinePointerInfo(SV, nextOffset), MVT::i8,
2132 nextOffset += StackOffset;
2133 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2135 // Store second word : arguments given on stack
2136 SDValue thirdStore =
2137 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2138 MachinePointerInfo(SV, nextOffset),
2140 nextOffset += FrameOffset;
2141 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2143 // Store third word : arguments given in registers
2144 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2145 MachinePointerInfo(SV, nextOffset),
2150 #include "PPCGenCallingConv.inc"
2152 // Function whose sole purpose is to kill compiler warnings
2153 // stemming from unused functions included from PPCGenCallingConv.inc.
2154 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2155 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2158 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2159 CCValAssign::LocInfo &LocInfo,
2160 ISD::ArgFlagsTy &ArgFlags,
2165 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2167 CCValAssign::LocInfo &LocInfo,
2168 ISD::ArgFlagsTy &ArgFlags,
2170 static const MCPhysReg ArgRegs[] = {
2171 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2172 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2174 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2176 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2178 // Skip one register if the first unallocated register has an even register
2179 // number and there are still argument registers available which have not been
2180 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2181 // need to skip a register if RegNum is odd.
2182 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2183 State.AllocateReg(ArgRegs[RegNum]);
2186 // Always return false here, as this function only makes sure that the first
2187 // unallocated register has an odd register number and does not actually
2188 // allocate a register for the current argument.
2192 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2194 CCValAssign::LocInfo &LocInfo,
2195 ISD::ArgFlagsTy &ArgFlags,
2197 static const MCPhysReg ArgRegs[] = {
2198 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2202 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2204 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2206 // If there is only one Floating-point register left we need to put both f64
2207 // values of a split ppc_fp128 value on the stack.
2208 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2209 State.AllocateReg(ArgRegs[RegNum]);
2212 // Always return false here, as this function only makes sure that the two f64
2213 // values a ppc_fp128 value is split into are both passed in registers or both
2214 // passed on the stack and does not actually allocate a register for the
2215 // current argument.
2219 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
2221 static const MCPhysReg *GetFPR() {
2222 static const MCPhysReg FPR[] = {
2223 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2224 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
2230 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2232 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2233 unsigned PtrByteSize) {
2234 unsigned ArgSize = ArgVT.getStoreSize();
2235 if (Flags.isByVal())
2236 ArgSize = Flags.getByValSize();
2238 // Round up to multiples of the pointer size, except for array members,
2239 // which are always packed.
2240 if (!Flags.isInConsecutiveRegs())
2241 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2246 /// CalculateStackSlotAlignment - Calculates the alignment of this argument
2248 static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
2249 ISD::ArgFlagsTy Flags,
2250 unsigned PtrByteSize) {
2251 unsigned Align = PtrByteSize;
2253 // Altivec parameters are padded to a 16 byte boundary.
2254 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2255 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2256 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2259 // ByVal parameters are aligned as requested.
2260 if (Flags.isByVal()) {
2261 unsigned BVAlign = Flags.getByValAlign();
2262 if (BVAlign > PtrByteSize) {
2263 if (BVAlign % PtrByteSize != 0)
2265 "ByVal alignment is not a multiple of the pointer size");
2271 // Array members are always packed to their original alignment.
2272 if (Flags.isInConsecutiveRegs()) {
2273 // If the array member was split into multiple registers, the first
2274 // needs to be aligned to the size of the full type. (Except for
2275 // ppcf128, which is only aligned as its f64 components.)
2276 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
2277 Align = OrigVT.getStoreSize();
2279 Align = ArgVT.getStoreSize();
2285 /// CalculateStackSlotUsed - Return whether this argument will use its
2286 /// stack slot (instead of being passed in registers). ArgOffset,
2287 /// AvailableFPRs, and AvailableVRs must hold the current argument
2288 /// position, and will be updated to account for this argument.
2289 static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT,
2290 ISD::ArgFlagsTy Flags,
2291 unsigned PtrByteSize,
2292 unsigned LinkageSize,
2293 unsigned ParamAreaSize,
2294 unsigned &ArgOffset,
2295 unsigned &AvailableFPRs,
2296 unsigned &AvailableVRs) {
2297 bool UseMemory = false;
2299 // Respect alignment of argument on the stack.
2301 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
2302 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2303 // If there's no space left in the argument save area, we must
2304 // use memory (this check also catches zero-sized arguments).
2305 if (ArgOffset >= LinkageSize + ParamAreaSize)
2308 // Allocate argument on the stack.
2309 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2310 if (Flags.isInConsecutiveRegsLast())
2311 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2312 // If we overran the argument save area, we must use memory
2313 // (this check catches arguments passed partially in memory)
2314 if (ArgOffset > LinkageSize + ParamAreaSize)
2317 // However, if the argument is actually passed in an FPR or a VR,
2318 // we don't use memory after all.
2319 if (!Flags.isByVal()) {
2320 if (ArgVT == MVT::f32 || ArgVT == MVT::f64)
2321 if (AvailableFPRs > 0) {
2325 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2326 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2327 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2328 if (AvailableVRs > 0) {
2337 /// EnsureStackAlignment - Round stack frame size up from NumBytes to
2338 /// ensure minimum alignment required for target.
2339 static unsigned EnsureStackAlignment(const TargetMachine &Target,
2340 unsigned NumBytes) {
2341 unsigned TargetAlign =
2342 Target.getSubtargetImpl()->getFrameLowering()->getStackAlignment();
2343 unsigned AlignMask = TargetAlign - 1;
2344 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2349 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
2350 CallingConv::ID CallConv, bool isVarArg,
2351 const SmallVectorImpl<ISD::InputArg>
2353 SDLoc dl, SelectionDAG &DAG,
2354 SmallVectorImpl<SDValue> &InVals)
2356 if (Subtarget.isSVR4ABI()) {
2357 if (Subtarget.isPPC64())
2358 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2361 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2364 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2370 PPCTargetLowering::LowerFormalArguments_32SVR4(
2372 CallingConv::ID CallConv, bool isVarArg,
2373 const SmallVectorImpl<ISD::InputArg>
2375 SDLoc dl, SelectionDAG &DAG,
2376 SmallVectorImpl<SDValue> &InVals) const {
2378 // 32-bit SVR4 ABI Stack Frame Layout:
2379 // +-----------------------------------+
2380 // +--> | Back chain |
2381 // | +-----------------------------------+
2382 // | | Floating-point register save area |
2383 // | +-----------------------------------+
2384 // | | General register save area |
2385 // | +-----------------------------------+
2386 // | | CR save word |
2387 // | +-----------------------------------+
2388 // | | VRSAVE save word |
2389 // | +-----------------------------------+
2390 // | | Alignment padding |
2391 // | +-----------------------------------+
2392 // | | Vector register save area |
2393 // | +-----------------------------------+
2394 // | | Local variable space |
2395 // | +-----------------------------------+
2396 // | | Parameter list area |
2397 // | +-----------------------------------+
2398 // | | LR save word |
2399 // | +-----------------------------------+
2400 // SP--> +--- | Back chain |
2401 // +-----------------------------------+
2404 // System V Application Binary Interface PowerPC Processor Supplement
2405 // AltiVec Technology Programming Interface Manual
2407 MachineFunction &MF = DAG.getMachineFunction();
2408 MachineFrameInfo *MFI = MF.getFrameInfo();
2409 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2411 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2412 // Potential tail calls could cause overwriting of argument stack slots.
2413 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2414 (CallConv == CallingConv::Fast));
2415 unsigned PtrByteSize = 4;
2417 // Assign locations to all of the incoming arguments.
2418 SmallVector<CCValAssign, 16> ArgLocs;
2419 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2422 // Reserve space for the linkage area on the stack.
2423 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(false, false, false);
2424 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
2426 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2428 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2429 CCValAssign &VA = ArgLocs[i];
2431 // Arguments stored in registers.
2432 if (VA.isRegLoc()) {
2433 const TargetRegisterClass *RC;
2434 EVT ValVT = VA.getValVT();
2436 switch (ValVT.getSimpleVT().SimpleTy) {
2438 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2441 RC = &PPC::GPRCRegClass;
2444 RC = &PPC::F4RCRegClass;
2447 if (Subtarget.hasVSX())
2448 RC = &PPC::VSFRCRegClass;
2450 RC = &PPC::F8RCRegClass;
2456 RC = &PPC::VRRCRegClass;
2460 RC = &PPC::VSHRCRegClass;
2464 // Transform the arguments stored in physical registers into virtual ones.
2465 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2466 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2467 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2469 if (ValVT == MVT::i1)
2470 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2472 InVals.push_back(ArgValue);
2474 // Argument stored in memory.
2475 assert(VA.isMemLoc());
2477 unsigned ArgSize = VA.getLocVT().getStoreSize();
2478 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2481 // Create load nodes to retrieve arguments from the stack.
2482 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2483 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2484 MachinePointerInfo(),
2485 false, false, false, 0));
2489 // Assign locations to all of the incoming aggregate by value arguments.
2490 // Aggregates passed by value are stored in the local variable space of the
2491 // caller's stack frame, right above the parameter list area.
2492 SmallVector<CCValAssign, 16> ByValArgLocs;
2493 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2494 ByValArgLocs, *DAG.getContext());
2496 // Reserve stack space for the allocations in CCInfo.
2497 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2499 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2501 // Area that is at least reserved in the caller of this function.
2502 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2503 MinReservedArea = std::max(MinReservedArea, LinkageSize);
2505 // Set the size that is at least reserved in caller of this function. Tail
2506 // call optimized function's reserved stack space needs to be aligned so that
2507 // taking the difference between two stack areas will result in an aligned
2509 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2510 FuncInfo->setMinReservedArea(MinReservedArea);
2512 SmallVector<SDValue, 8> MemOps;
2514 // If the function takes variable number of arguments, make a frame index for
2515 // the start of the first vararg value... for expansion of llvm.va_start.
2517 static const MCPhysReg GPArgRegs[] = {
2518 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2519 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2521 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2523 static const MCPhysReg FPArgRegs[] = {
2524 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2527 unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2528 if (DisablePPCFloatInVariadic)
2531 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2533 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2536 // Make room for NumGPArgRegs and NumFPArgRegs.
2537 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2538 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8;
2540 FuncInfo->setVarArgsStackOffset(
2541 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2542 CCInfo.getNextStackOffset(), true));
2544 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2545 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2547 // The fixed integer arguments of a variadic function are stored to the
2548 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2549 // the result of va_next.
2550 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2551 // Get an existing live-in vreg, or add a new one.
2552 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2554 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2556 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2557 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2558 MachinePointerInfo(), false, false, 0);
2559 MemOps.push_back(Store);
2560 // Increment the address by four for the next argument to store
2561 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2562 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2565 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2567 // The double arguments are stored to the VarArgsFrameIndex
2569 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2570 // Get an existing live-in vreg, or add a new one.
2571 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2573 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2575 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2576 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2577 MachinePointerInfo(), false, false, 0);
2578 MemOps.push_back(Store);
2579 // Increment the address by eight for the next argument to store
2580 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8,
2582 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2586 if (!MemOps.empty())
2587 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2592 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2593 // value to MVT::i64 and then truncate to the correct register size.
2595 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2596 SelectionDAG &DAG, SDValue ArgVal,
2599 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2600 DAG.getValueType(ObjectVT));
2601 else if (Flags.isZExt())
2602 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2603 DAG.getValueType(ObjectVT));
2605 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
2609 PPCTargetLowering::LowerFormalArguments_64SVR4(
2611 CallingConv::ID CallConv, bool isVarArg,
2612 const SmallVectorImpl<ISD::InputArg>
2614 SDLoc dl, SelectionDAG &DAG,
2615 SmallVectorImpl<SDValue> &InVals) const {
2616 // TODO: add description of PPC stack frame format, or at least some docs.
2618 bool isELFv2ABI = Subtarget.isELFv2ABI();
2619 bool isLittleEndian = Subtarget.isLittleEndian();
2620 MachineFunction &MF = DAG.getMachineFunction();
2621 MachineFrameInfo *MFI = MF.getFrameInfo();
2622 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2624 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2625 // Potential tail calls could cause overwriting of argument stack slots.
2626 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2627 (CallConv == CallingConv::Fast));
2628 unsigned PtrByteSize = 8;
2630 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
2633 static const MCPhysReg GPR[] = {
2634 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2635 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2638 static const MCPhysReg *FPR = GetFPR();
2640 static const MCPhysReg VR[] = {
2641 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2642 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2644 static const MCPhysReg VSRH[] = {
2645 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
2646 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
2649 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2650 const unsigned Num_FPR_Regs = 13;
2651 const unsigned Num_VR_Regs = array_lengthof(VR);
2653 // Do a first pass over the arguments to determine whether the ABI
2654 // guarantees that our caller has allocated the parameter save area
2655 // on its stack frame. In the ELFv1 ABI, this is always the case;
2656 // in the ELFv2 ABI, it is true if this is a vararg function or if
2657 // any parameter is located in a stack slot.
2659 bool HasParameterArea = !isELFv2ABI || isVarArg;
2660 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
2661 unsigned NumBytes = LinkageSize;
2662 unsigned AvailableFPRs = Num_FPR_Regs;
2663 unsigned AvailableVRs = Num_VR_Regs;
2664 for (unsigned i = 0, e = Ins.size(); i != e; ++i)
2665 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
2666 PtrByteSize, LinkageSize, ParamAreaSize,
2667 NumBytes, AvailableFPRs, AvailableVRs))
2668 HasParameterArea = true;
2670 // Add DAG nodes to load the arguments or copy them out of registers. On
2671 // entry to a function on PPC, the arguments start after the linkage area,
2672 // although the first ones are often in registers.
2674 unsigned ArgOffset = LinkageSize;
2675 unsigned GPR_idx, FPR_idx = 0, VR_idx = 0;
2676 SmallVector<SDValue, 8> MemOps;
2677 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2678 unsigned CurArgIdx = 0;
2679 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2681 bool needsLoad = false;
2682 EVT ObjectVT = Ins[ArgNo].VT;
2683 EVT OrigVT = Ins[ArgNo].ArgVT;
2684 unsigned ObjSize = ObjectVT.getStoreSize();
2685 unsigned ArgSize = ObjSize;
2686 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2687 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2688 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2690 /* Respect alignment of argument on the stack. */
2692 CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
2693 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2694 unsigned CurArgOffset = ArgOffset;
2696 /* Compute GPR index associated with argument offset. */
2697 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2698 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
2700 // FIXME the codegen can be much improved in some cases.
2701 // We do not have to keep everything in memory.
2702 if (Flags.isByVal()) {
2703 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2704 ObjSize = Flags.getByValSize();
2705 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2706 // Empty aggregate parameters do not take up registers. Examples:
2710 // etc. However, we have to provide a place-holder in InVals, so
2711 // pretend we have an 8-byte item at the current address for that
2714 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2715 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2716 InVals.push_back(FIN);
2720 // Create a stack object covering all stack doublewords occupied
2721 // by the argument. If the argument is (fully or partially) on
2722 // the stack, or if the argument is fully in registers but the
2723 // caller has allocated the parameter save anyway, we can refer
2724 // directly to the caller's stack frame. Otherwise, create a
2725 // local copy in our own frame.
2727 if (HasParameterArea ||
2728 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
2729 FI = MFI->CreateFixedObject(ArgSize, ArgOffset, false, true);
2731 FI = MFI->CreateStackObject(ArgSize, Align, false);
2732 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2734 // Handle aggregates smaller than 8 bytes.
2735 if (ObjSize < PtrByteSize) {
2736 // The value of the object is its address, which differs from the
2737 // address of the enclosing doubleword on big-endian systems.
2739 if (!isLittleEndian) {
2740 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, PtrVT);
2741 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
2743 InVals.push_back(Arg);
2745 if (GPR_idx != Num_GPR_Regs) {
2746 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2747 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2750 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2751 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2752 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2753 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
2754 MachinePointerInfo(FuncArg),
2755 ObjType, false, false, 0);
2757 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2758 // store the whole register as-is to the parameter save area
2760 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2761 MachinePointerInfo(FuncArg),
2765 MemOps.push_back(Store);
2767 // Whether we copied from a register or not, advance the offset
2768 // into the parameter save area by a full doubleword.
2769 ArgOffset += PtrByteSize;
2773 // The value of the object is its address, which is the address of
2774 // its first stack doubleword.
2775 InVals.push_back(FIN);
2777 // Store whatever pieces of the object are in registers to memory.
2778 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2779 if (GPR_idx == Num_GPR_Regs)
2782 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2783 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2786 SDValue Off = DAG.getConstant(j, PtrVT);
2787 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
2789 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
2790 MachinePointerInfo(FuncArg, j),
2792 MemOps.push_back(Store);
2795 ArgOffset += ArgSize;
2799 switch (ObjectVT.getSimpleVT().SimpleTy) {
2800 default: llvm_unreachable("Unhandled argument type!");
2804 // These can be scalar arguments or elements of an integer array type
2805 // passed directly. Clang may use those instead of "byval" aggregate
2806 // types to avoid forcing arguments to memory unnecessarily.
2807 if (GPR_idx != Num_GPR_Regs) {
2808 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2809 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2811 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
2812 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2813 // value to MVT::i64 and then truncate to the correct register size.
2814 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2817 ArgSize = PtrByteSize;
2824 // These can be scalar arguments or elements of a float array type
2825 // passed directly. The latter are used to implement ELFv2 homogenous
2826 // float aggregates.
2827 if (FPR_idx != Num_FPR_Regs) {
2830 if (ObjectVT == MVT::f32)
2831 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2833 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX() ?
2834 &PPC::VSFRCRegClass :
2835 &PPC::F8RCRegClass);
2837 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2839 } else if (GPR_idx != Num_GPR_Regs) {
2840 // This can only ever happen in the presence of f32 array types,
2841 // since otherwise we never run out of FPRs before running out
2843 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2844 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2846 if (ObjectVT == MVT::f32) {
2847 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
2848 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
2849 DAG.getConstant(32, MVT::i32));
2850 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2853 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
2858 // When passing an array of floats, the array occupies consecutive
2859 // space in the argument area; only round up to the next doubleword
2860 // at the end of the array. Otherwise, each float takes 8 bytes.
2861 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
2862 ArgOffset += ArgSize;
2863 if (Flags.isInConsecutiveRegsLast())
2864 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2872 // These can be scalar arguments or elements of a vector array type
2873 // passed directly. The latter are used to implement ELFv2 homogenous
2874 // vector aggregates.
2875 if (VR_idx != Num_VR_Regs) {
2876 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
2877 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
2878 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2879 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2888 // We need to load the argument to a virtual register if we determined
2889 // above that we ran out of physical registers of the appropriate type.
2891 if (ObjSize < ArgSize && !isLittleEndian)
2892 CurArgOffset += ArgSize - ObjSize;
2893 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
2894 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2895 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2896 false, false, false, 0);
2899 InVals.push_back(ArgVal);
2902 // Area that is at least reserved in the caller of this function.
2903 unsigned MinReservedArea;
2904 if (HasParameterArea)
2905 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
2907 MinReservedArea = LinkageSize;
2909 // Set the size that is at least reserved in caller of this function. Tail
2910 // call optimized functions' reserved stack space needs to be aligned so that
2911 // taking the difference between two stack areas will result in an aligned
2913 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2914 FuncInfo->setMinReservedArea(MinReservedArea);
2916 // If the function takes variable number of arguments, make a frame index for
2917 // the start of the first vararg value... for expansion of llvm.va_start.
2919 int Depth = ArgOffset;
2921 FuncInfo->setVarArgsFrameIndex(
2922 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2923 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2925 // If this function is vararg, store any remaining integer argument regs
2926 // to their spots on the stack so that they may be loaded by deferencing the
2927 // result of va_next.
2928 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2929 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
2930 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2931 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2932 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2933 MachinePointerInfo(), false, false, 0);
2934 MemOps.push_back(Store);
2935 // Increment the address by four for the next argument to store
2936 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2937 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2941 if (!MemOps.empty())
2942 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2948 PPCTargetLowering::LowerFormalArguments_Darwin(
2950 CallingConv::ID CallConv, bool isVarArg,
2951 const SmallVectorImpl<ISD::InputArg>
2953 SDLoc dl, SelectionDAG &DAG,
2954 SmallVectorImpl<SDValue> &InVals) const {
2955 // TODO: add description of PPC stack frame format, or at least some docs.
2957 MachineFunction &MF = DAG.getMachineFunction();
2958 MachineFrameInfo *MFI = MF.getFrameInfo();
2959 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2961 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2962 bool isPPC64 = PtrVT == MVT::i64;
2963 // Potential tail calls could cause overwriting of argument stack slots.
2964 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2965 (CallConv == CallingConv::Fast));
2966 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2968 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true,
2970 unsigned ArgOffset = LinkageSize;
2971 // Area that is at least reserved in caller of this function.
2972 unsigned MinReservedArea = ArgOffset;
2974 static const MCPhysReg GPR_32[] = { // 32-bit registers.
2975 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2976 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2978 static const MCPhysReg GPR_64[] = { // 64-bit registers.
2979 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2980 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2983 static const MCPhysReg *FPR = GetFPR();
2985 static const MCPhysReg VR[] = {
2986 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2987 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2990 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2991 const unsigned Num_FPR_Regs = 13;
2992 const unsigned Num_VR_Regs = array_lengthof( VR);
2994 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2996 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
2998 // In 32-bit non-varargs functions, the stack space for vectors is after the
2999 // stack space for non-vectors. We do not use this space unless we have
3000 // too many vectors to fit in registers, something that only occurs in
3001 // constructed examples:), but we have to walk the arglist to figure
3002 // that out...for the pathological case, compute VecArgOffset as the
3003 // start of the vector parameter area. Computing VecArgOffset is the
3004 // entire point of the following loop.
3005 unsigned VecArgOffset = ArgOffset;
3006 if (!isVarArg && !isPPC64) {
3007 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
3009 EVT ObjectVT = Ins[ArgNo].VT;
3010 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3012 if (Flags.isByVal()) {
3013 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
3014 unsigned ObjSize = Flags.getByValSize();
3016 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3017 VecArgOffset += ArgSize;
3021 switch(ObjectVT.getSimpleVT().SimpleTy) {
3022 default: llvm_unreachable("Unhandled argument type!");
3028 case MVT::i64: // PPC64
3030 // FIXME: We are guaranteed to be !isPPC64 at this point.
3031 // Does MVT::i64 apply?
3038 // Nothing to do, we're only looking at Nonvector args here.
3043 // We've found where the vector parameter area in memory is. Skip the
3044 // first 12 parameters; these don't use that memory.
3045 VecArgOffset = ((VecArgOffset+15)/16)*16;
3046 VecArgOffset += 12*16;
3048 // Add DAG nodes to load the arguments or copy them out of registers. On
3049 // entry to a function on PPC, the arguments start after the linkage area,
3050 // although the first ones are often in registers.
3052 SmallVector<SDValue, 8> MemOps;
3053 unsigned nAltivecParamsAtEnd = 0;
3054 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3055 unsigned CurArgIdx = 0;
3056 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3058 bool needsLoad = false;
3059 EVT ObjectVT = Ins[ArgNo].VT;
3060 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
3061 unsigned ArgSize = ObjSize;
3062 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3063 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
3064 CurArgIdx = Ins[ArgNo].OrigArgIndex;
3066 unsigned CurArgOffset = ArgOffset;
3068 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
3069 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
3070 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
3071 if (isVarArg || isPPC64) {
3072 MinReservedArea = ((MinReservedArea+15)/16)*16;
3073 MinReservedArea += CalculateStackSlotSize(ObjectVT,
3076 } else nAltivecParamsAtEnd++;
3078 // Calculate min reserved area.
3079 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
3083 // FIXME the codegen can be much improved in some cases.
3084 // We do not have to keep everything in memory.
3085 if (Flags.isByVal()) {
3086 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3087 ObjSize = Flags.getByValSize();
3088 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3089 // Objects of size 1 and 2 are right justified, everything else is
3090 // left justified. This means the memory address is adjusted forwards.
3091 if (ObjSize==1 || ObjSize==2) {
3092 CurArgOffset = CurArgOffset + (4 - ObjSize);
3094 // The value of the object is its address.
3095 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, false, true);
3096 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3097 InVals.push_back(FIN);
3098 if (ObjSize==1 || ObjSize==2) {
3099 if (GPR_idx != Num_GPR_Regs) {
3102 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3104 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3105 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3106 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
3107 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
3108 MachinePointerInfo(FuncArg),
3109 ObjType, false, false, 0);
3110 MemOps.push_back(Store);
3114 ArgOffset += PtrByteSize;
3118 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3119 // Store whatever pieces of the object are in registers
3120 // to memory. ArgOffset will be the address of the beginning
3122 if (GPR_idx != Num_GPR_Regs) {
3125 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3127 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3128 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3129 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3130 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3131 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3132 MachinePointerInfo(FuncArg, j),
3134 MemOps.push_back(Store);
3136 ArgOffset += PtrByteSize;
3138 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
3145 switch (ObjectVT.getSimpleVT().SimpleTy) {
3146 default: llvm_unreachable("Unhandled argument type!");
3150 if (GPR_idx != Num_GPR_Regs) {
3151 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3152 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3154 if (ObjectVT == MVT::i1)
3155 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
3160 ArgSize = PtrByteSize;
3162 // All int arguments reserve stack space in the Darwin ABI.
3163 ArgOffset += PtrByteSize;
3167 case MVT::i64: // PPC64
3168 if (GPR_idx != Num_GPR_Regs) {
3169 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3170 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3172 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3173 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3174 // value to MVT::i64 and then truncate to the correct register size.
3175 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3180 ArgSize = PtrByteSize;
3182 // All int arguments reserve stack space in the Darwin ABI.
3188 // Every 4 bytes of argument space consumes one of the GPRs available for
3189 // argument passing.
3190 if (GPR_idx != Num_GPR_Regs) {
3192 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
3195 if (FPR_idx != Num_FPR_Regs) {
3198 if (ObjectVT == MVT::f32)
3199 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
3201 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
3203 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3209 // All FP arguments reserve stack space in the Darwin ABI.
3210 ArgOffset += isPPC64 ? 8 : ObjSize;
3216 // Note that vector arguments in registers don't reserve stack space,
3217 // except in varargs functions.
3218 if (VR_idx != Num_VR_Regs) {
3219 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3220 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3222 while ((ArgOffset % 16) != 0) {
3223 ArgOffset += PtrByteSize;
3224 if (GPR_idx != Num_GPR_Regs)
3228 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
3232 if (!isVarArg && !isPPC64) {
3233 // Vectors go after all the nonvectors.
3234 CurArgOffset = VecArgOffset;
3237 // Vectors are aligned.
3238 ArgOffset = ((ArgOffset+15)/16)*16;
3239 CurArgOffset = ArgOffset;
3247 // We need to load the argument to a virtual register if we determined above
3248 // that we ran out of physical registers of the appropriate type.
3250 int FI = MFI->CreateFixedObject(ObjSize,
3251 CurArgOffset + (ArgSize - ObjSize),
3253 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3254 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3255 false, false, false, 0);
3258 InVals.push_back(ArgVal);
3261 // Allow for Altivec parameters at the end, if needed.
3262 if (nAltivecParamsAtEnd) {
3263 MinReservedArea = ((MinReservedArea+15)/16)*16;
3264 MinReservedArea += 16*nAltivecParamsAtEnd;
3267 // Area that is at least reserved in the caller of this function.
3268 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
3270 // Set the size that is at least reserved in caller of this function. Tail
3271 // call optimized functions' reserved stack space needs to be aligned so that
3272 // taking the difference between two stack areas will result in an aligned
3274 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
3275 FuncInfo->setMinReservedArea(MinReservedArea);
3277 // If the function takes variable number of arguments, make a frame index for
3278 // the start of the first vararg value... for expansion of llvm.va_start.
3280 int Depth = ArgOffset;
3282 FuncInfo->setVarArgsFrameIndex(
3283 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3285 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3287 // If this function is vararg, store any remaining integer argument regs
3288 // to their spots on the stack so that they may be loaded by deferencing the
3289 // result of va_next.
3290 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3294 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3296 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3298 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3299 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3300 MachinePointerInfo(), false, false, 0);
3301 MemOps.push_back(Store);
3302 // Increment the address by four for the next argument to store
3303 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
3304 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3308 if (!MemOps.empty())
3309 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3314 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3315 /// adjusted to accommodate the arguments for the tailcall.
3316 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3317 unsigned ParamSize) {
3319 if (!isTailCall) return 0;
3321 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3322 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3323 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3324 // Remember only if the new adjustement is bigger.
3325 if (SPDiff < FI->getTailCallSPDelta())
3326 FI->setTailCallSPDelta(SPDiff);
3331 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3332 /// for tail call optimization. Targets which want to do tail call
3333 /// optimization should implement this function.
3335 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3336 CallingConv::ID CalleeCC,
3338 const SmallVectorImpl<ISD::InputArg> &Ins,
3339 SelectionDAG& DAG) const {
3340 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3343 // Variable argument functions are not supported.
3347 MachineFunction &MF = DAG.getMachineFunction();
3348 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3349 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3350 // Functions containing by val parameters are not supported.
3351 for (unsigned i = 0; i != Ins.size(); i++) {
3352 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3353 if (Flags.isByVal()) return false;
3356 // Non-PIC/GOT tail calls are supported.
3357 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3360 // At the moment we can only do local tail calls (in same module, hidden
3361 // or protected) if we are generating PIC.
3362 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3363 return G->getGlobal()->hasHiddenVisibility()
3364 || G->getGlobal()->hasProtectedVisibility();
3370 /// isCallCompatibleAddress - Return the immediate to use if the specified
3371 /// 32-bit value is representable in the immediate field of a BxA instruction.
3372 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3373 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3374 if (!C) return nullptr;
3376 int Addr = C->getZExtValue();
3377 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3378 SignExtend32<26>(Addr) != Addr)
3379 return nullptr; // Top 6 bits have to be sext of immediate.
3381 return DAG.getConstant((int)C->getZExtValue() >> 2,
3382 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
3387 struct TailCallArgumentInfo {
3392 TailCallArgumentInfo() : FrameIdx(0) {}
3397 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3399 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3401 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3402 SmallVectorImpl<SDValue> &MemOpChains,
3404 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3405 SDValue Arg = TailCallArgs[i].Arg;
3406 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3407 int FI = TailCallArgs[i].FrameIdx;
3408 // Store relative to framepointer.
3409 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
3410 MachinePointerInfo::getFixedStack(FI),
3415 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3416 /// the appropriate stack slot for the tail call optimized function call.
3417 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3418 MachineFunction &MF,
3427 // Calculate the new stack slot for the return address.
3428 int SlotSize = isPPC64 ? 8 : 4;
3429 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
3431 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3432 NewRetAddrLoc, true);
3433 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3434 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3435 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3436 MachinePointerInfo::getFixedStack(NewRetAddr),
3439 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3440 // slot as the FP is never overwritten.
3443 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
3444 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3446 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3447 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3448 MachinePointerInfo::getFixedStack(NewFPIdx),
3455 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3456 /// the position of the argument.
3458 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3459 SDValue Arg, int SPDiff, unsigned ArgOffset,
3460 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3461 int Offset = ArgOffset + SPDiff;
3462 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3463 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3464 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3465 SDValue FIN = DAG.getFrameIndex(FI, VT);
3466 TailCallArgumentInfo Info;
3468 Info.FrameIdxOp = FIN;
3470 TailCallArguments.push_back(Info);
3473 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3474 /// stack slot. Returns the chain as result and the loaded frame pointers in
3475 /// LROpOut/FPOpout. Used when tail calling.
3476 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3484 // Load the LR and FP stack slot for later adjusting.
3485 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
3486 LROpOut = getReturnAddrFrameIndex(DAG);
3487 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3488 false, false, false, 0);
3489 Chain = SDValue(LROpOut.getNode(), 1);
3491 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3492 // slot as the FP is never overwritten.
3494 FPOpOut = getFramePointerFrameIndex(DAG);
3495 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3496 false, false, false, 0);
3497 Chain = SDValue(FPOpOut.getNode(), 1);
3503 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3504 /// by "Src" to address "Dst" of size "Size". Alignment information is
3505 /// specified by the specific parameter attribute. The copy will be passed as
3506 /// a byval function parameter.
3507 /// Sometimes what we are copying is the end of a larger object, the part that
3508 /// does not fit in registers.
3510 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3511 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3513 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3514 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3515 false, false, MachinePointerInfo(),
3516 MachinePointerInfo());
3519 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3522 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3523 SDValue Arg, SDValue PtrOff, int SPDiff,
3524 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3525 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
3526 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
3528 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3533 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3535 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3536 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3537 DAG.getConstant(ArgOffset, PtrVT));
3539 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3540 MachinePointerInfo(), false, false, 0));
3541 // Calculate and remember argument location.
3542 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3547 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3548 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3549 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3550 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
3551 MachineFunction &MF = DAG.getMachineFunction();
3553 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3554 // might overwrite each other in case of tail call optimization.
3555 SmallVector<SDValue, 8> MemOpChains2;
3556 // Do not flag preceding copytoreg stuff together with the following stuff.
3558 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3560 if (!MemOpChains2.empty())
3561 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3563 // Store the return address to the appropriate stack slot.
3564 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3565 isPPC64, isDarwinABI, dl);
3567 // Emit callseq_end just before tailcall node.
3568 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3569 DAG.getIntPtrConstant(0, true), InFlag, dl);
3570 InFlag = Chain.getValue(1);
3574 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3575 SDValue &Chain, SDLoc dl, int SPDiff, bool isTailCall,
3576 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
3577 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
3578 const PPCSubtarget &Subtarget) {
3580 bool isPPC64 = Subtarget.isPPC64();
3581 bool isSVR4ABI = Subtarget.isSVR4ABI();
3582 bool isELFv2ABI = Subtarget.isELFv2ABI();
3584 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3585 NodeTys.push_back(MVT::Other); // Returns a chain
3586 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3588 unsigned CallOpc = PPCISD::CALL;
3590 bool needIndirectCall = true;
3591 if (!isSVR4ABI || !isPPC64)
3592 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3593 // If this is an absolute destination address, use the munged value.
3594 Callee = SDValue(Dest, 0);
3595 needIndirectCall = false;
3598 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3599 unsigned OpFlags = 0;
3600 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3601 (Subtarget.getTargetTriple().isMacOSX() &&
3602 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3603 (G->getGlobal()->isDeclaration() ||
3604 G->getGlobal()->isWeakForLinker())) ||
3605 (Subtarget.isTargetELF() && !isPPC64 &&
3606 !G->getGlobal()->hasLocalLinkage() &&
3607 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3608 // PC-relative references to external symbols should go through $stub,
3609 // unless we're building with the leopard linker or later, which
3610 // automatically synthesizes these stubs.
3611 OpFlags = PPCII::MO_PLT_OR_STUB;
3614 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3615 // every direct call is) turn it into a TargetGlobalAddress /
3616 // TargetExternalSymbol node so that legalize doesn't hack it.
3617 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3618 Callee.getValueType(), 0, OpFlags);
3619 needIndirectCall = false;
3622 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3623 unsigned char OpFlags = 0;
3625 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3626 (Subtarget.getTargetTriple().isMacOSX() &&
3627 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) ||
3628 (Subtarget.isTargetELF() && !isPPC64 &&
3629 DAG.getTarget().getRelocationModel() == Reloc::PIC_) ) {
3630 // PC-relative references to external symbols should go through $stub,
3631 // unless we're building with the leopard linker or later, which
3632 // automatically synthesizes these stubs.
3633 OpFlags = PPCII::MO_PLT_OR_STUB;
3636 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3638 needIndirectCall = false;
3641 if (needIndirectCall) {
3642 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3643 // to do the call, we can't use PPCISD::CALL.
3644 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3646 if (isSVR4ABI && isPPC64 && !isELFv2ABI) {
3647 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3648 // entry point, but to the function descriptor (the function entry point
3649 // address is part of the function descriptor though).
3650 // The function descriptor is a three doubleword structure with the
3651 // following fields: function entry point, TOC base address and
3652 // environment pointer.
3653 // Thus for a call through a function pointer, the following actions need
3655 // 1. Save the TOC of the caller in the TOC save area of its stack
3656 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3657 // 2. Load the address of the function entry point from the function
3659 // 3. Load the TOC of the callee from the function descriptor into r2.
3660 // 4. Load the environment pointer from the function descriptor into
3662 // 5. Branch to the function entry point address.
3663 // 6. On return of the callee, the TOC of the caller needs to be
3664 // restored (this is done in FinishCall()).
3666 // All those operations are flagged together to ensure that no other
3667 // operations can be scheduled in between. E.g. without flagging the
3668 // operations together, a TOC access in the caller could be scheduled
3669 // between the load of the callee TOC and the branch to the callee, which
3670 // results in the TOC access going through the TOC of the callee instead
3671 // of going through the TOC of the caller, which leads to incorrect code.
3673 // Load the address of the function entry point from the function
3675 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3676 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs,
3677 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3678 Chain = LoadFuncPtr.getValue(1);
3679 InFlag = LoadFuncPtr.getValue(2);
3681 // Load environment pointer into r11.
3682 // Offset of the environment pointer within the function descriptor.
3683 SDValue PtrOff = DAG.getIntPtrConstant(16);
3685 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3686 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
3688 Chain = LoadEnvPtr.getValue(1);
3689 InFlag = LoadEnvPtr.getValue(2);
3691 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3693 Chain = EnvVal.getValue(0);
3694 InFlag = EnvVal.getValue(1);
3696 // Load TOC of the callee into r2. We are using a target-specific load
3697 // with r2 hard coded, because the result of a target-independent load
3698 // would never go directly into r2, since r2 is a reserved register (which
3699 // prevents the register allocator from allocating it), resulting in an
3700 // additional register being allocated and an unnecessary move instruction
3702 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3703 SDValue TOCOff = DAG.getIntPtrConstant(8);
3704 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
3705 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
3707 Chain = LoadTOCPtr.getValue(0);
3708 InFlag = LoadTOCPtr.getValue(1);
3710 MTCTROps[0] = Chain;
3711 MTCTROps[1] = LoadFuncPtr;
3712 MTCTROps[2] = InFlag;
3715 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
3716 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3717 InFlag = Chain.getValue(1);
3720 NodeTys.push_back(MVT::Other);
3721 NodeTys.push_back(MVT::Glue);
3722 Ops.push_back(Chain);
3723 CallOpc = PPCISD::BCTRL;
3724 Callee.setNode(nullptr);
3725 // Add use of X11 (holding environment pointer)
3726 if (isSVR4ABI && isPPC64 && !isELFv2ABI)
3727 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3728 // Add CTR register as callee so a bctr can be emitted later.
3730 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3733 // If this is a direct call, pass the chain and the callee.
3734 if (Callee.getNode()) {
3735 Ops.push_back(Chain);
3736 Ops.push_back(Callee);
3738 // If this is a call to __tls_get_addr, find the symbol whose address
3739 // is to be taken and add it to the list. This will be used to
3740 // generate __tls_get_addr(<sym>@tlsgd) or __tls_get_addr(<sym>@tlsld).
3741 // We find the symbol by walking the chain to the CopyFromReg, walking
3742 // back from the CopyFromReg to the ADDI_TLSGD_L or ADDI_TLSLD_L, and
3743 // pulling the symbol from that node.
3744 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
3745 if (!strcmp(S->getSymbol(), "__tls_get_addr")) {
3746 assert(!needIndirectCall && "Indirect call to __tls_get_addr???");
3747 SDNode *AddI = Chain.getNode()->getOperand(2).getNode();
3748 SDValue TGTAddr = AddI->getOperand(1);
3749 assert(TGTAddr.getNode()->getOpcode() == ISD::TargetGlobalTLSAddress &&
3750 "Didn't find target global TLS address where we expected one");
3751 Ops.push_back(TGTAddr);
3752 CallOpc = PPCISD::CALL_TLS;
3755 // If this is a tail call add stack pointer delta.
3757 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3759 // Add argument registers to the end of the list so that they are known live
3761 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3762 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3763 RegsToPass[i].second.getValueType()));
3765 // Direct calls in the ELFv2 ABI need the TOC register live into the call.
3766 if (Callee.getNode() && isELFv2ABI)
3767 Ops.push_back(DAG.getRegister(PPC::X2, PtrVT));
3773 bool isLocalCall(const SDValue &Callee)
3775 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3776 return !G->getGlobal()->isDeclaration() &&
3777 !G->getGlobal()->isWeakForLinker();
3782 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3783 CallingConv::ID CallConv, bool isVarArg,
3784 const SmallVectorImpl<ISD::InputArg> &Ins,
3785 SDLoc dl, SelectionDAG &DAG,
3786 SmallVectorImpl<SDValue> &InVals) const {
3788 SmallVector<CCValAssign, 16> RVLocs;
3789 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
3791 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3793 // Copy all of the result registers out of their specified physreg.
3794 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3795 CCValAssign &VA = RVLocs[i];
3796 assert(VA.isRegLoc() && "Can only return in registers!");
3798 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3799 VA.getLocReg(), VA.getLocVT(), InFlag);
3800 Chain = Val.getValue(1);
3801 InFlag = Val.getValue(2);
3803 switch (VA.getLocInfo()) {
3804 default: llvm_unreachable("Unknown loc info!");
3805 case CCValAssign::Full: break;
3806 case CCValAssign::AExt:
3807 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3809 case CCValAssign::ZExt:
3810 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3811 DAG.getValueType(VA.getValVT()));
3812 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3814 case CCValAssign::SExt:
3815 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3816 DAG.getValueType(VA.getValVT()));
3817 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3821 InVals.push_back(Val);
3828 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
3829 bool isTailCall, bool isVarArg,
3831 SmallVector<std::pair<unsigned, SDValue>, 8>
3833 SDValue InFlag, SDValue Chain,
3835 int SPDiff, unsigned NumBytes,
3836 const SmallVectorImpl<ISD::InputArg> &Ins,
3837 SmallVectorImpl<SDValue> &InVals) const {
3839 bool isELFv2ABI = Subtarget.isELFv2ABI();
3840 std::vector<EVT> NodeTys;
3841 SmallVector<SDValue, 8> Ops;
3842 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
3843 isTailCall, RegsToPass, Ops, NodeTys,
3846 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3847 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
3848 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3850 // When performing tail call optimization the callee pops its arguments off
3851 // the stack. Account for this here so these bytes can be pushed back on in
3852 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3853 int BytesCalleePops =
3854 (CallConv == CallingConv::Fast &&
3855 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3857 // Add a register mask operand representing the call-preserved registers.
3858 const TargetRegisterInfo *TRI =
3859 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
3860 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3861 assert(Mask && "Missing call preserved mask for calling convention");
3862 Ops.push_back(DAG.getRegisterMask(Mask));
3864 if (InFlag.getNode())
3865 Ops.push_back(InFlag);
3869 assert(((Callee.getOpcode() == ISD::Register &&
3870 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3871 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3872 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3873 isa<ConstantSDNode>(Callee)) &&
3874 "Expecting an global address, external symbol, absolute value or register");
3876 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
3879 // Add a NOP immediately after the branch instruction when using the 64-bit
3880 // SVR4 ABI. At link time, if caller and callee are in a different module and
3881 // thus have a different TOC, the call will be replaced with a call to a stub
3882 // function which saves the current TOC, loads the TOC of the callee and
3883 // branches to the callee. The NOP will be replaced with a load instruction
3884 // which restores the TOC of the caller from the TOC save slot of the current
3885 // stack frame. If caller and callee belong to the same module (and have the
3886 // same TOC), the NOP will remain unchanged.
3888 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64()) {
3889 if (CallOpc == PPCISD::BCTRL) {
3890 // This is a call through a function pointer.
3891 // Restore the caller TOC from the save area into R2.
3892 // See PrepareCall() for more information about calls through function
3893 // pointers in the 64-bit SVR4 ABI.
3894 // We are using a target-specific load with r2 hard coded, because the
3895 // result of a target-independent load would never go directly into r2,
3896 // since r2 is a reserved register (which prevents the register allocator
3897 // from allocating it), resulting in an additional register being
3898 // allocated and an unnecessary move instruction being generated.
3899 CallOpc = PPCISD::BCTRL_LOAD_TOC;
3901 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3902 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
3903 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset(isELFv2ABI);
3904 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset);
3905 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
3907 // The address needs to go after the chain input but before the flag (or
3908 // any other variadic arguments).
3909 Ops.insert(std::next(Ops.begin()), AddTOC);
3910 } else if ((CallOpc == PPCISD::CALL) &&
3911 (!isLocalCall(Callee) ||
3912 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3913 // Otherwise insert NOP for non-local calls.
3914 CallOpc = PPCISD::CALL_NOP;
3915 } else if (CallOpc == PPCISD::CALL_TLS)
3916 // For 64-bit SVR4, TLS calls are always non-local.
3917 CallOpc = PPCISD::CALL_NOP_TLS;
3920 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
3921 InFlag = Chain.getValue(1);
3923 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3924 DAG.getIntPtrConstant(BytesCalleePops, true),
3927 InFlag = Chain.getValue(1);
3929 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3930 Ins, dl, DAG, InVals);
3934 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3935 SmallVectorImpl<SDValue> &InVals) const {
3936 SelectionDAG &DAG = CLI.DAG;
3938 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3939 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3940 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3941 SDValue Chain = CLI.Chain;
3942 SDValue Callee = CLI.Callee;
3943 bool &isTailCall = CLI.IsTailCall;
3944 CallingConv::ID CallConv = CLI.CallConv;
3945 bool isVarArg = CLI.IsVarArg;
3948 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3951 if (!isTailCall && CLI.CS && CLI.CS->isMustTailCall())
3952 report_fatal_error("failed to perform tail call elimination on a call "
3953 "site marked musttail");
3955 if (Subtarget.isSVR4ABI()) {
3956 if (Subtarget.isPPC64())
3957 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3958 isTailCall, Outs, OutVals, Ins,
3961 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3962 isTailCall, Outs, OutVals, Ins,
3966 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
3967 isTailCall, Outs, OutVals, Ins,
3972 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
3973 CallingConv::ID CallConv, bool isVarArg,
3975 const SmallVectorImpl<ISD::OutputArg> &Outs,
3976 const SmallVectorImpl<SDValue> &OutVals,
3977 const SmallVectorImpl<ISD::InputArg> &Ins,
3978 SDLoc dl, SelectionDAG &DAG,
3979 SmallVectorImpl<SDValue> &InVals) const {
3980 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
3981 // of the 32-bit SVR4 ABI stack frame layout.
3983 assert((CallConv == CallingConv::C ||
3984 CallConv == CallingConv::Fast) && "Unknown calling convention!");
3986 unsigned PtrByteSize = 4;
3988 MachineFunction &MF = DAG.getMachineFunction();
3990 // Mark this function as potentially containing a function that contains a
3991 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3992 // and restoring the callers stack pointer in this functions epilog. This is
3993 // done because by tail calling the called function might overwrite the value
3994 // in this function's (MF) stack pointer stack slot 0(SP).
3995 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3996 CallConv == CallingConv::Fast)
3997 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3999 // Count how many bytes are to be pushed on the stack, including the linkage
4000 // area, parameter list area and the part of the local variable space which
4001 // contains copies of aggregates which are passed by value.
4003 // Assign locations to all of the outgoing arguments.
4004 SmallVector<CCValAssign, 16> ArgLocs;
4005 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
4008 // Reserve space for the linkage area on the stack.
4009 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false, false),
4013 // Handle fixed and variable vector arguments differently.
4014 // Fixed vector arguments go into registers as long as registers are
4015 // available. Variable vector arguments always go into memory.
4016 unsigned NumArgs = Outs.size();
4018 for (unsigned i = 0; i != NumArgs; ++i) {
4019 MVT ArgVT = Outs[i].VT;
4020 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
4023 if (Outs[i].IsFixed) {
4024 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
4027 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
4033 errs() << "Call operand #" << i << " has unhandled type "
4034 << EVT(ArgVT).getEVTString() << "\n";
4036 llvm_unreachable(nullptr);
4040 // All arguments are treated the same.
4041 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
4044 // Assign locations to all of the outgoing aggregate by value arguments.
4045 SmallVector<CCValAssign, 16> ByValArgLocs;
4046 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4047 ByValArgLocs, *DAG.getContext());
4049 // Reserve stack space for the allocations in CCInfo.
4050 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
4052 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
4054 // Size of the linkage area, parameter list area and the part of the local
4055 // space variable where copies of aggregates which are passed by value are
4057 unsigned NumBytes = CCByValInfo.getNextStackOffset();
4059 // Calculate by how many bytes the stack has to be adjusted in case of tail
4060 // call optimization.
4061 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4063 // Adjust the stack pointer for the new arguments...
4064 // These operations are automatically eliminated by the prolog/epilog pass
4065 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4067 SDValue CallSeqStart = Chain;
4069 // Load the return address and frame pointer so it can be moved somewhere else
4072 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
4075 // Set up a copy of the stack pointer for use loading and storing any
4076 // arguments that may not fit in the registers available for argument
4078 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4080 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4081 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4082 SmallVector<SDValue, 8> MemOpChains;
4084 bool seenFloatArg = false;
4085 // Walk the register/memloc assignments, inserting copies/loads.
4086 for (unsigned i = 0, j = 0, e = ArgLocs.size();
4089 CCValAssign &VA = ArgLocs[i];
4090 SDValue Arg = OutVals[i];
4091 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4093 if (Flags.isByVal()) {
4094 // Argument is an aggregate which is passed by value, thus we need to
4095 // create a copy of it in the local variable space of the current stack
4096 // frame (which is the stack frame of the caller) and pass the address of
4097 // this copy to the callee.
4098 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
4099 CCValAssign &ByValVA = ByValArgLocs[j++];
4100 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
4102 // Memory reserved in the local variable space of the callers stack frame.
4103 unsigned LocMemOffset = ByValVA.getLocMemOffset();
4105 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4106 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4108 // Create a copy of the argument in the local area of the current
4110 SDValue MemcpyCall =
4111 CreateCopyOfByValArgument(Arg, PtrOff,
4112 CallSeqStart.getNode()->getOperand(0),
4115 // This must go outside the CALLSEQ_START..END.
4116 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4117 CallSeqStart.getNode()->getOperand(1),
4119 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4120 NewCallSeqStart.getNode());
4121 Chain = CallSeqStart = NewCallSeqStart;
4123 // Pass the address of the aggregate copy on the stack either in a
4124 // physical register or in the parameter list area of the current stack
4125 // frame to the callee.
4129 if (VA.isRegLoc()) {
4130 if (Arg.getValueType() == MVT::i1)
4131 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
4133 seenFloatArg |= VA.getLocVT().isFloatingPoint();
4134 // Put argument in a physical register.
4135 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
4137 // Put argument in the parameter list area of the current stack frame.
4138 assert(VA.isMemLoc());
4139 unsigned LocMemOffset = VA.getLocMemOffset();
4142 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4143 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4145 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4146 MachinePointerInfo(),
4149 // Calculate and remember argument location.
4150 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
4156 if (!MemOpChains.empty())
4157 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4159 // Build a sequence of copy-to-reg nodes chained together with token chain
4160 // and flag operands which copy the outgoing args into the appropriate regs.
4162 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4163 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4164 RegsToPass[i].second, InFlag);
4165 InFlag = Chain.getValue(1);
4168 // Set CR bit 6 to true if this is a vararg call with floating args passed in
4171 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
4172 SDValue Ops[] = { Chain, InFlag };
4174 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
4175 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
4177 InFlag = Chain.getValue(1);
4181 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
4182 false, TailCallArguments);
4184 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4185 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4189 // Copy an argument into memory, being careful to do this outside the
4190 // call sequence for the call to which the argument belongs.
4192 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
4193 SDValue CallSeqStart,
4194 ISD::ArgFlagsTy Flags,
4197 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
4198 CallSeqStart.getNode()->getOperand(0),
4200 // The MEMCPY must go outside the CALLSEQ_START..END.
4201 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4202 CallSeqStart.getNode()->getOperand(1),
4204 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4205 NewCallSeqStart.getNode());
4206 return NewCallSeqStart;
4210 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
4211 CallingConv::ID CallConv, bool isVarArg,
4213 const SmallVectorImpl<ISD::OutputArg> &Outs,
4214 const SmallVectorImpl<SDValue> &OutVals,
4215 const SmallVectorImpl<ISD::InputArg> &Ins,
4216 SDLoc dl, SelectionDAG &DAG,
4217 SmallVectorImpl<SDValue> &InVals) const {
4219 bool isELFv2ABI = Subtarget.isELFv2ABI();
4220 bool isLittleEndian = Subtarget.isLittleEndian();
4221 unsigned NumOps = Outs.size();
4223 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4224 unsigned PtrByteSize = 8;
4226 MachineFunction &MF = DAG.getMachineFunction();
4228 // Mark this function as potentially containing a function that contains a
4229 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4230 // and restoring the callers stack pointer in this functions epilog. This is
4231 // done because by tail calling the called function might overwrite the value
4232 // in this function's (MF) stack pointer stack slot 0(SP).
4233 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4234 CallConv == CallingConv::Fast)
4235 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4237 // Count how many bytes are to be pushed on the stack, including the linkage
4238 // area, and parameter passing area. On ELFv1, the linkage area is 48 bytes
4239 // reserved space for [SP][CR][LR][2 x unused][TOC]; on ELFv2, the linkage
4240 // area is 32 bytes reserved space for [SP][CR][LR][TOC].
4241 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
4243 unsigned NumBytes = LinkageSize;
4245 // Add up all the space actually used.
4246 for (unsigned i = 0; i != NumOps; ++i) {
4247 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4248 EVT ArgVT = Outs[i].VT;
4249 EVT OrigVT = Outs[i].ArgVT;
4251 /* Respect alignment of argument on the stack. */
4253 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4254 NumBytes = ((NumBytes + Align - 1) / Align) * Align;
4256 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4257 if (Flags.isInConsecutiveRegsLast())
4258 NumBytes = ((NumBytes + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4261 unsigned NumBytesActuallyUsed = NumBytes;
4263 // The prolog code of the callee may store up to 8 GPR argument registers to
4264 // the stack, allowing va_start to index over them in memory if its varargs.
4265 // Because we cannot tell if this is needed on the caller side, we have to
4266 // conservatively assume that it is needed. As such, make sure we have at
4267 // least enough stack space for the caller to store the 8 GPRs.
4268 // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
4269 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4271 // Tail call needs the stack to be aligned.
4272 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4273 CallConv == CallingConv::Fast)
4274 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
4276 // Calculate by how many bytes the stack has to be adjusted in case of tail
4277 // call optimization.
4278 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4280 // To protect arguments on the stack from being clobbered in a tail call,
4281 // force all the loads to happen before doing any other lowering.
4283 Chain = DAG.getStackArgumentTokenFactor(Chain);
4285 // Adjust the stack pointer for the new arguments...
4286 // These operations are automatically eliminated by the prolog/epilog pass
4287 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4289 SDValue CallSeqStart = Chain;
4291 // Load the return address and frame pointer so it can be move somewhere else
4294 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4297 // Set up a copy of the stack pointer for use loading and storing any
4298 // arguments that may not fit in the registers available for argument
4300 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4302 // Figure out which arguments are going to go in registers, and which in
4303 // memory. Also, if this is a vararg function, floating point operations
4304 // must be stored to our stack, and loaded into integer regs as well, if
4305 // any integer regs are available for argument passing.
4306 unsigned ArgOffset = LinkageSize;
4307 unsigned GPR_idx, FPR_idx = 0, VR_idx = 0;
4309 static const MCPhysReg GPR[] = {
4310 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4311 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4313 static const MCPhysReg *FPR = GetFPR();
4315 static const MCPhysReg VR[] = {
4316 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4317 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4319 static const MCPhysReg VSRH[] = {
4320 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4321 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4324 const unsigned NumGPRs = array_lengthof(GPR);
4325 const unsigned NumFPRs = 13;
4326 const unsigned NumVRs = array_lengthof(VR);
4328 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4329 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4331 SmallVector<SDValue, 8> MemOpChains;
4332 for (unsigned i = 0; i != NumOps; ++i) {
4333 SDValue Arg = OutVals[i];
4334 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4335 EVT ArgVT = Outs[i].VT;
4336 EVT OrigVT = Outs[i].ArgVT;
4338 /* Respect alignment of argument on the stack. */
4340 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4341 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
4343 /* Compute GPR index associated with argument offset. */
4344 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4345 GPR_idx = std::min(GPR_idx, NumGPRs);
4347 // PtrOff will be used to store the current argument to the stack if a
4348 // register cannot be found for it.
4351 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4353 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4355 // Promote integers to 64-bit values.
4356 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4357 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4358 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4359 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4362 // FIXME memcpy is used way more than necessary. Correctness first.
4363 // Note: "by value" is code for passing a structure by value, not
4365 if (Flags.isByVal()) {
4366 // Note: Size includes alignment padding, so
4367 // struct x { short a; char b; }
4368 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4369 // These are the proper values we need for right-justifying the
4370 // aggregate in a parameter register.
4371 unsigned Size = Flags.getByValSize();
4373 // An empty aggregate parameter takes up no storage and no
4378 // All aggregates smaller than 8 bytes must be passed right-justified.
4379 if (Size==1 || Size==2 || Size==4) {
4380 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4381 if (GPR_idx != NumGPRs) {
4382 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4383 MachinePointerInfo(), VT,
4384 false, false, false, 0);
4385 MemOpChains.push_back(Load.getValue(1));
4386 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Load));
4388 ArgOffset += PtrByteSize;
4393 if (GPR_idx == NumGPRs && Size < 8) {
4394 SDValue AddPtr = PtrOff;
4395 if (!isLittleEndian) {
4396 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4397 PtrOff.getValueType());
4398 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4400 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4403 ArgOffset += PtrByteSize;
4406 // Copy entire object into memory. There are cases where gcc-generated
4407 // code assumes it is there, even if it could be put entirely into
4408 // registers. (This is not what the doc says.)
4410 // FIXME: The above statement is likely due to a misunderstanding of the
4411 // documents. All arguments must be copied into the parameter area BY
4412 // THE CALLEE in the event that the callee takes the address of any
4413 // formal argument. That has not yet been implemented. However, it is
4414 // reasonable to use the stack area as a staging area for the register
4417 // Skip this for small aggregates, as we will use the same slot for a
4418 // right-justified copy, below.
4420 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4424 // When a register is available, pass a small aggregate right-justified.
4425 if (Size < 8 && GPR_idx != NumGPRs) {
4426 // The easiest way to get this right-justified in a register
4427 // is to copy the structure into the rightmost portion of a
4428 // local variable slot, then load the whole slot into the
4430 // FIXME: The memcpy seems to produce pretty awful code for
4431 // small aggregates, particularly for packed ones.
4432 // FIXME: It would be preferable to use the slot in the
4433 // parameter save area instead of a new local variable.
4434 SDValue AddPtr = PtrOff;
4435 if (!isLittleEndian) {
4436 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
4437 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4439 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4443 // Load the slot into the register.
4444 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
4445 MachinePointerInfo(),
4446 false, false, false, 0);
4447 MemOpChains.push_back(Load.getValue(1));
4448 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Load));
4450 // Done with this argument.
4451 ArgOffset += PtrByteSize;
4455 // For aggregates larger than PtrByteSize, copy the pieces of the
4456 // object that fit into registers from the parameter save area.
4457 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4458 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4459 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4460 if (GPR_idx != NumGPRs) {
4461 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4462 MachinePointerInfo(),
4463 false, false, false, 0);
4464 MemOpChains.push_back(Load.getValue(1));
4465 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4466 ArgOffset += PtrByteSize;
4468 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4475 switch (Arg.getSimpleValueType().SimpleTy) {
4476 default: llvm_unreachable("Unexpected ValueType for argument!");
4480 // These can be scalar arguments or elements of an integer array type
4481 // passed directly. Clang may use those instead of "byval" aggregate
4482 // types to avoid forcing arguments to memory unnecessarily.
4483 if (GPR_idx != NumGPRs) {
4484 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Arg));
4486 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4487 true, isTailCall, false, MemOpChains,
4488 TailCallArguments, dl);
4490 ArgOffset += PtrByteSize;
4494 // These can be scalar arguments or elements of a float array type
4495 // passed directly. The latter are used to implement ELFv2 homogenous
4496 // float aggregates.
4498 // Named arguments go into FPRs first, and once they overflow, the
4499 // remaining arguments go into GPRs and then the parameter save area.
4500 // Unnamed arguments for vararg functions always go to GPRs and
4501 // then the parameter save area. For now, put all arguments to vararg
4502 // routines always in both locations (FPR *and* GPR or stack slot).
4503 bool NeedGPROrStack = isVarArg || FPR_idx == NumFPRs;
4505 // First load the argument into the next available FPR.
4506 if (FPR_idx != NumFPRs)
4507 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4509 // Next, load the argument into GPR or stack slot if needed.
4510 if (!NeedGPROrStack)
4512 else if (GPR_idx != NumGPRs) {
4513 // In the non-vararg case, this can only ever happen in the
4514 // presence of f32 array types, since otherwise we never run
4515 // out of FPRs before running out of GPRs.
4518 // Double values are always passed in a single GPR.
4519 if (Arg.getValueType() != MVT::f32) {
4520 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
4522 // Non-array float values are extended and passed in a GPR.
4523 } else if (!Flags.isInConsecutiveRegs()) {
4524 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4525 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4527 // If we have an array of floats, we collect every odd element
4528 // together with its predecessor into one GPR.
4529 } else if (ArgOffset % PtrByteSize != 0) {
4531 Lo = DAG.getNode(ISD::BITCAST, dl, MVT::i32, OutVals[i - 1]);
4532 Hi = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4533 if (!isLittleEndian)
4535 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
4537 // The final element, if even, goes into the first half of a GPR.
4538 } else if (Flags.isInConsecutiveRegsLast()) {
4539 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4540 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4541 if (!isLittleEndian)
4542 ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal,
4543 DAG.getConstant(32, MVT::i32));
4545 // Non-final even elements are skipped; they will be handled
4546 // together the with subsequent argument on the next go-around.
4550 if (ArgVal.getNode())
4551 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], ArgVal));
4553 // Single-precision floating-point values are mapped to the
4554 // second (rightmost) word of the stack doubleword.
4555 if (Arg.getValueType() == MVT::f32 &&
4556 !isLittleEndian && !Flags.isInConsecutiveRegs()) {
4557 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4558 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4561 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4562 true, isTailCall, false, MemOpChains,
4563 TailCallArguments, dl);
4565 // When passing an array of floats, the array occupies consecutive
4566 // space in the argument area; only round up to the next doubleword
4567 // at the end of the array. Otherwise, each float takes 8 bytes.
4568 ArgOffset += (Arg.getValueType() == MVT::f32 &&
4569 Flags.isInConsecutiveRegs()) ? 4 : 8;
4570 if (Flags.isInConsecutiveRegsLast())
4571 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4580 // These can be scalar arguments or elements of a vector array type
4581 // passed directly. The latter are used to implement ELFv2 homogenous
4582 // vector aggregates.
4584 // For a varargs call, named arguments go into VRs or on the stack as
4585 // usual; unnamed arguments always go to the stack or the corresponding
4586 // GPRs when within range. For now, we always put the value in both
4587 // locations (or even all three).
4589 // We could elide this store in the case where the object fits
4590 // entirely in R registers. Maybe later.
4591 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4592 MachinePointerInfo(), false, false, 0);
4593 MemOpChains.push_back(Store);
4594 if (VR_idx != NumVRs) {
4595 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4596 MachinePointerInfo(),
4597 false, false, false, 0);
4598 MemOpChains.push_back(Load.getValue(1));
4600 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4601 Arg.getSimpleValueType() == MVT::v2i64) ?
4602 VSRH[VR_idx] : VR[VR_idx];
4605 RegsToPass.push_back(std::make_pair(VReg, Load));
4608 for (unsigned i=0; i<16; i+=PtrByteSize) {
4609 if (GPR_idx == NumGPRs)
4611 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4612 DAG.getConstant(i, PtrVT));
4613 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4614 false, false, false, 0);
4615 MemOpChains.push_back(Load.getValue(1));
4616 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4621 // Non-varargs Altivec params go into VRs or on the stack.
4622 if (VR_idx != NumVRs) {
4623 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4624 Arg.getSimpleValueType() == MVT::v2i64) ?
4625 VSRH[VR_idx] : VR[VR_idx];
4628 RegsToPass.push_back(std::make_pair(VReg, Arg));
4630 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4631 true, isTailCall, true, MemOpChains,
4632 TailCallArguments, dl);
4639 assert(NumBytesActuallyUsed == ArgOffset);
4640 (void)NumBytesActuallyUsed;
4642 if (!MemOpChains.empty())
4643 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4645 // Check if this is an indirect call (MTCTR/BCTRL).
4646 // See PrepareCall() for more information about calls through function
4647 // pointers in the 64-bit SVR4 ABI.
4649 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4650 !dyn_cast<ExternalSymbolSDNode>(Callee)) {
4651 // Load r2 into a virtual register and store it to the TOC save area.
4652 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4653 // TOC save area offset.
4654 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset(isELFv2ABI);
4655 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset);
4656 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4657 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
4659 // In the ELFv2 ABI, R12 must contain the address of an indirect callee.
4660 // This does not mean the MTCTR instruction must use R12; it's easier
4661 // to model this as an extra parameter, so do that.
4663 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
4666 // Build a sequence of copy-to-reg nodes chained together with token chain
4667 // and flag operands which copy the outgoing args into the appropriate regs.
4669 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4670 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4671 RegsToPass[i].second, InFlag);
4672 InFlag = Chain.getValue(1);
4676 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4677 FPOp, true, TailCallArguments);
4679 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4680 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4685 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4686 CallingConv::ID CallConv, bool isVarArg,
4688 const SmallVectorImpl<ISD::OutputArg> &Outs,
4689 const SmallVectorImpl<SDValue> &OutVals,
4690 const SmallVectorImpl<ISD::InputArg> &Ins,
4691 SDLoc dl, SelectionDAG &DAG,
4692 SmallVectorImpl<SDValue> &InVals) const {
4694 unsigned NumOps = Outs.size();
4696 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4697 bool isPPC64 = PtrVT == MVT::i64;
4698 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4700 MachineFunction &MF = DAG.getMachineFunction();
4702 // Mark this function as potentially containing a function that contains a
4703 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4704 // and restoring the callers stack pointer in this functions epilog. This is
4705 // done because by tail calling the called function might overwrite the value
4706 // in this function's (MF) stack pointer stack slot 0(SP).
4707 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4708 CallConv == CallingConv::Fast)
4709 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4711 // Count how many bytes are to be pushed on the stack, including the linkage
4712 // area, and parameter passing area. We start with 24/48 bytes, which is
4713 // prereserved space for [SP][CR][LR][3 x unused].
4714 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true,
4716 unsigned NumBytes = LinkageSize;
4718 // Add up all the space actually used.
4719 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
4720 // they all go in registers, but we must reserve stack space for them for
4721 // possible use by the caller. In varargs or 64-bit calls, parameters are
4722 // assigned stack space in order, with padding so Altivec parameters are
4724 unsigned nAltivecParamsAtEnd = 0;
4725 for (unsigned i = 0; i != NumOps; ++i) {
4726 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4727 EVT ArgVT = Outs[i].VT;
4728 // Varargs Altivec parameters are padded to a 16 byte boundary.
4729 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
4730 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
4731 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) {
4732 if (!isVarArg && !isPPC64) {
4733 // Non-varargs Altivec parameters go after all the non-Altivec
4734 // parameters; handle those later so we know how much padding we need.
4735 nAltivecParamsAtEnd++;
4738 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
4739 NumBytes = ((NumBytes+15)/16)*16;
4741 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4744 // Allow for Altivec parameters at the end, if needed.
4745 if (nAltivecParamsAtEnd) {
4746 NumBytes = ((NumBytes+15)/16)*16;
4747 NumBytes += 16*nAltivecParamsAtEnd;
4750 // The prolog code of the callee may store up to 8 GPR argument registers to
4751 // the stack, allowing va_start to index over them in memory if its varargs.
4752 // Because we cannot tell if this is needed on the caller side, we have to
4753 // conservatively assume that it is needed. As such, make sure we have at
4754 // least enough stack space for the caller to store the 8 GPRs.
4755 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4757 // Tail call needs the stack to be aligned.
4758 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4759 CallConv == CallingConv::Fast)
4760 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
4762 // Calculate by how many bytes the stack has to be adjusted in case of tail
4763 // call optimization.
4764 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4766 // To protect arguments on the stack from being clobbered in a tail call,
4767 // force all the loads to happen before doing any other lowering.
4769 Chain = DAG.getStackArgumentTokenFactor(Chain);
4771 // Adjust the stack pointer for the new arguments...
4772 // These operations are automatically eliminated by the prolog/epilog pass
4773 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4775 SDValue CallSeqStart = Chain;
4777 // Load the return address and frame pointer so it can be move somewhere else
4780 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4783 // Set up a copy of the stack pointer for use loading and storing any
4784 // arguments that may not fit in the registers available for argument
4788 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4790 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4792 // Figure out which arguments are going to go in registers, and which in
4793 // memory. Also, if this is a vararg function, floating point operations
4794 // must be stored to our stack, and loaded into integer regs as well, if
4795 // any integer regs are available for argument passing.
4796 unsigned ArgOffset = LinkageSize;
4797 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4799 static const MCPhysReg GPR_32[] = { // 32-bit registers.
4800 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4801 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4803 static const MCPhysReg GPR_64[] = { // 64-bit registers.
4804 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4805 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4807 static const MCPhysReg *FPR = GetFPR();
4809 static const MCPhysReg VR[] = {
4810 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4811 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4813 const unsigned NumGPRs = array_lengthof(GPR_32);
4814 const unsigned NumFPRs = 13;
4815 const unsigned NumVRs = array_lengthof(VR);
4817 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
4819 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4820 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4822 SmallVector<SDValue, 8> MemOpChains;
4823 for (unsigned i = 0; i != NumOps; ++i) {
4824 SDValue Arg = OutVals[i];
4825 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4827 // PtrOff will be used to store the current argument to the stack if a
4828 // register cannot be found for it.
4831 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4833 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4835 // On PPC64, promote integers to 64-bit values.
4836 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4837 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4838 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4839 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4842 // FIXME memcpy is used way more than necessary. Correctness first.
4843 // Note: "by value" is code for passing a structure by value, not
4845 if (Flags.isByVal()) {
4846 unsigned Size = Flags.getByValSize();
4847 // Very small objects are passed right-justified. Everything else is
4848 // passed left-justified.
4849 if (Size==1 || Size==2) {
4850 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4851 if (GPR_idx != NumGPRs) {
4852 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4853 MachinePointerInfo(), VT,
4854 false, false, false, 0);
4855 MemOpChains.push_back(Load.getValue(1));
4856 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4858 ArgOffset += PtrByteSize;
4860 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4861 PtrOff.getValueType());
4862 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4863 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4866 ArgOffset += PtrByteSize;
4870 // Copy entire object into memory. There are cases where gcc-generated
4871 // code assumes it is there, even if it could be put entirely into
4872 // registers. (This is not what the doc says.)
4873 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4877 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4878 // copy the pieces of the object that fit into registers from the
4879 // parameter save area.
4880 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4881 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4882 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4883 if (GPR_idx != NumGPRs) {
4884 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4885 MachinePointerInfo(),
4886 false, false, false, 0);
4887 MemOpChains.push_back(Load.getValue(1));
4888 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4889 ArgOffset += PtrByteSize;
4891 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4898 switch (Arg.getSimpleValueType().SimpleTy) {
4899 default: llvm_unreachable("Unexpected ValueType for argument!");
4903 if (GPR_idx != NumGPRs) {
4904 if (Arg.getValueType() == MVT::i1)
4905 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
4907 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4909 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4910 isPPC64, isTailCall, false, MemOpChains,
4911 TailCallArguments, dl);
4913 ArgOffset += PtrByteSize;
4917 if (FPR_idx != NumFPRs) {
4918 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4921 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4922 MachinePointerInfo(), false, false, 0);
4923 MemOpChains.push_back(Store);
4925 // Float varargs are always shadowed in available integer registers
4926 if (GPR_idx != NumGPRs) {
4927 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4928 MachinePointerInfo(), false, false,
4930 MemOpChains.push_back(Load.getValue(1));
4931 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4933 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4934 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4935 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4936 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4937 MachinePointerInfo(),
4938 false, false, false, 0);
4939 MemOpChains.push_back(Load.getValue(1));
4940 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4943 // If we have any FPRs remaining, we may also have GPRs remaining.
4944 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4946 if (GPR_idx != NumGPRs)
4948 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4949 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4953 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4954 isPPC64, isTailCall, false, MemOpChains,
4955 TailCallArguments, dl);
4959 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4966 // These go aligned on the stack, or in the corresponding R registers
4967 // when within range. The Darwin PPC ABI doc claims they also go in
4968 // V registers; in fact gcc does this only for arguments that are
4969 // prototyped, not for those that match the ... We do it for all
4970 // arguments, seems to work.
4971 while (ArgOffset % 16 !=0) {
4972 ArgOffset += PtrByteSize;
4973 if (GPR_idx != NumGPRs)
4976 // We could elide this store in the case where the object fits
4977 // entirely in R registers. Maybe later.
4978 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4979 DAG.getConstant(ArgOffset, PtrVT));
4980 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4981 MachinePointerInfo(), false, false, 0);
4982 MemOpChains.push_back(Store);
4983 if (VR_idx != NumVRs) {
4984 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4985 MachinePointerInfo(),
4986 false, false, false, 0);
4987 MemOpChains.push_back(Load.getValue(1));
4988 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4991 for (unsigned i=0; i<16; i+=PtrByteSize) {
4992 if (GPR_idx == NumGPRs)
4994 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4995 DAG.getConstant(i, PtrVT));
4996 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4997 false, false, false, 0);
4998 MemOpChains.push_back(Load.getValue(1));
4999 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5004 // Non-varargs Altivec params generally go in registers, but have
5005 // stack space allocated at the end.
5006 if (VR_idx != NumVRs) {
5007 // Doesn't have GPR space allocated.
5008 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
5009 } else if (nAltivecParamsAtEnd==0) {
5010 // We are emitting Altivec params in order.
5011 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5012 isPPC64, isTailCall, true, MemOpChains,
5013 TailCallArguments, dl);
5019 // If all Altivec parameters fit in registers, as they usually do,
5020 // they get stack space following the non-Altivec parameters. We
5021 // don't track this here because nobody below needs it.
5022 // If there are more Altivec parameters than fit in registers emit
5024 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
5026 // Offset is aligned; skip 1st 12 params which go in V registers.
5027 ArgOffset = ((ArgOffset+15)/16)*16;
5029 for (unsigned i = 0; i != NumOps; ++i) {
5030 SDValue Arg = OutVals[i];
5031 EVT ArgType = Outs[i].VT;
5032 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
5033 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
5036 // We are emitting Altivec params in order.
5037 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5038 isPPC64, isTailCall, true, MemOpChains,
5039 TailCallArguments, dl);
5046 if (!MemOpChains.empty())
5047 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5049 // On Darwin, R12 must contain the address of an indirect callee. This does
5050 // not mean the MTCTR instruction must use R12; it's easier to model this as
5051 // an extra parameter, so do that.
5053 !dyn_cast<GlobalAddressSDNode>(Callee) &&
5054 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
5055 !isBLACompatibleAddress(Callee, DAG))
5056 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
5057 PPC::R12), Callee));
5059 // Build a sequence of copy-to-reg nodes chained together with token chain
5060 // and flag operands which copy the outgoing args into the appropriate regs.
5062 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5063 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5064 RegsToPass[i].second, InFlag);
5065 InFlag = Chain.getValue(1);
5069 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
5070 FPOp, true, TailCallArguments);
5072 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
5073 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
5078 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
5079 MachineFunction &MF, bool isVarArg,
5080 const SmallVectorImpl<ISD::OutputArg> &Outs,
5081 LLVMContext &Context) const {
5082 SmallVector<CCValAssign, 16> RVLocs;
5083 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
5084 return CCInfo.CheckReturn(Outs, RetCC_PPC);
5088 PPCTargetLowering::LowerReturn(SDValue Chain,
5089 CallingConv::ID CallConv, bool isVarArg,
5090 const SmallVectorImpl<ISD::OutputArg> &Outs,
5091 const SmallVectorImpl<SDValue> &OutVals,
5092 SDLoc dl, SelectionDAG &DAG) const {
5094 SmallVector<CCValAssign, 16> RVLocs;
5095 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
5097 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
5100 SmallVector<SDValue, 4> RetOps(1, Chain);
5102 // Copy the result values into the output registers.
5103 for (unsigned i = 0; i != RVLocs.size(); ++i) {
5104 CCValAssign &VA = RVLocs[i];
5105 assert(VA.isRegLoc() && "Can only return in registers!");
5107 SDValue Arg = OutVals[i];
5109 switch (VA.getLocInfo()) {
5110 default: llvm_unreachable("Unknown loc info!");
5111 case CCValAssign::Full: break;
5112 case CCValAssign::AExt:
5113 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
5115 case CCValAssign::ZExt:
5116 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
5118 case CCValAssign::SExt:
5119 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
5123 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
5124 Flag = Chain.getValue(1);
5125 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
5128 RetOps[0] = Chain; // Update chain.
5130 // Add the flag if we have it.
5132 RetOps.push_back(Flag);
5134 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
5137 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
5138 const PPCSubtarget &Subtarget) const {
5139 // When we pop the dynamic allocation we need to restore the SP link.
5142 // Get the corect type for pointers.
5143 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5145 // Construct the stack pointer operand.
5146 bool isPPC64 = Subtarget.isPPC64();
5147 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
5148 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
5150 // Get the operands for the STACKRESTORE.
5151 SDValue Chain = Op.getOperand(0);
5152 SDValue SaveSP = Op.getOperand(1);
5154 // Load the old link SP.
5155 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
5156 MachinePointerInfo(),
5157 false, false, false, 0);
5159 // Restore the stack pointer.
5160 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
5162 // Store the old link SP.
5163 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
5170 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
5171 MachineFunction &MF = DAG.getMachineFunction();
5172 bool isPPC64 = Subtarget.isPPC64();
5173 bool isDarwinABI = Subtarget.isDarwinABI();
5174 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5176 // Get current frame pointer save index. The users of this index will be
5177 // primarily DYNALLOC instructions.
5178 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5179 int RASI = FI->getReturnAddrSaveIndex();
5181 // If the frame pointer save index hasn't been defined yet.
5183 // Find out what the fix offset of the frame pointer save area.
5184 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
5185 // Allocate the frame index for frame pointer save area.
5186 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, false);
5188 FI->setReturnAddrSaveIndex(RASI);
5190 return DAG.getFrameIndex(RASI, PtrVT);
5194 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
5195 MachineFunction &MF = DAG.getMachineFunction();
5196 bool isPPC64 = Subtarget.isPPC64();
5197 bool isDarwinABI = Subtarget.isDarwinABI();
5198 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5200 // Get current frame pointer save index. The users of this index will be
5201 // primarily DYNALLOC instructions.
5202 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5203 int FPSI = FI->getFramePointerSaveIndex();
5205 // If the frame pointer save index hasn't been defined yet.
5207 // Find out what the fix offset of the frame pointer save area.
5208 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
5211 // Allocate the frame index for frame pointer save area.
5212 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
5214 FI->setFramePointerSaveIndex(FPSI);
5216 return DAG.getFrameIndex(FPSI, PtrVT);
5219 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5221 const PPCSubtarget &Subtarget) const {
5223 SDValue Chain = Op.getOperand(0);
5224 SDValue Size = Op.getOperand(1);
5227 // Get the corect type for pointers.
5228 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5230 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
5231 DAG.getConstant(0, PtrVT), Size);
5232 // Construct a node for the frame pointer save index.
5233 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
5234 // Build a DYNALLOC node.
5235 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
5236 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
5237 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
5240 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
5241 SelectionDAG &DAG) const {
5243 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
5244 DAG.getVTList(MVT::i32, MVT::Other),
5245 Op.getOperand(0), Op.getOperand(1));
5248 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
5249 SelectionDAG &DAG) const {
5251 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
5252 Op.getOperand(0), Op.getOperand(1));
5255 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
5256 assert(Op.getValueType() == MVT::i1 &&
5257 "Custom lowering only for i1 loads");
5259 // First, load 8 bits into 32 bits, then truncate to 1 bit.
5262 LoadSDNode *LD = cast<LoadSDNode>(Op);
5264 SDValue Chain = LD->getChain();
5265 SDValue BasePtr = LD->getBasePtr();
5266 MachineMemOperand *MMO = LD->getMemOperand();
5268 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(), Chain,
5269 BasePtr, MVT::i8, MMO);
5270 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
5272 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
5273 return DAG.getMergeValues(Ops, dl);
5276 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
5277 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
5278 "Custom lowering only for i1 stores");
5280 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
5283 StoreSDNode *ST = cast<StoreSDNode>(Op);
5285 SDValue Chain = ST->getChain();
5286 SDValue BasePtr = ST->getBasePtr();
5287 SDValue Value = ST->getValue();
5288 MachineMemOperand *MMO = ST->getMemOperand();
5290 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(), Value);
5291 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
5294 // FIXME: Remove this once the ANDI glue bug is fixed:
5295 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
5296 assert(Op.getValueType() == MVT::i1 &&
5297 "Custom lowering only for i1 results");
5300 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
5304 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
5306 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5307 // Not FP? Not a fsel.
5308 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
5309 !Op.getOperand(2).getValueType().isFloatingPoint())
5312 // We might be able to do better than this under some circumstances, but in
5313 // general, fsel-based lowering of select is a finite-math-only optimization.
5314 // For more information, see section F.3 of the 2.06 ISA specification.
5315 if (!DAG.getTarget().Options.NoInfsFPMath ||
5316 !DAG.getTarget().Options.NoNaNsFPMath)
5319 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5321 EVT ResVT = Op.getValueType();
5322 EVT CmpVT = Op.getOperand(0).getValueType();
5323 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5324 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
5327 // If the RHS of the comparison is a 0.0, we don't need to do the
5328 // subtraction at all.
5330 if (isFloatingPointZero(RHS))
5332 default: break; // SETUO etc aren't handled by fsel.
5336 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5337 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5338 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5339 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5340 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5341 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5342 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
5345 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5348 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5349 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5350 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5353 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5356 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5357 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5358 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5359 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
5364 default: break; // SETUO etc aren't handled by fsel.
5368 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5369 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5370 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5371 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5372 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5373 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5374 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5375 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
5378 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5379 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5380 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5381 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5384 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5385 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5386 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5387 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5390 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5391 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5392 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5393 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5396 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5397 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5398 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5399 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5404 // FIXME: Split this code up when LegalizeDAGTypes lands.
5405 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
5407 assert(Op.getOperand(0).getValueType().isFloatingPoint());
5408 SDValue Src = Op.getOperand(0);
5409 if (Src.getValueType() == MVT::f32)
5410 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
5413 switch (Op.getSimpleValueType().SimpleTy) {
5414 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
5416 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
5417 (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ :
5422 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
5423 "i64 FP_TO_UINT is supported only with FPCVT");
5424 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
5430 // Convert the FP value to an int value through memory.
5431 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
5432 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
5433 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
5434 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
5435 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
5437 // Emit a store to the stack slot.
5440 MachineFunction &MF = DAG.getMachineFunction();
5441 MachineMemOperand *MMO =
5442 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
5443 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
5444 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
5445 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
5447 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
5448 MPI, false, false, 0);
5450 // Result is a load from the stack slot. If loading 4 bytes, make sure to
5452 if (Op.getValueType() == MVT::i32 && !i32Stack) {
5453 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
5454 DAG.getConstant(4, FIPtr.getValueType()));
5455 MPI = MachinePointerInfo();
5458 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MPI,
5459 false, false, false, 0);
5462 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
5463 SelectionDAG &DAG) const {
5465 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
5466 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
5469 if (Op.getOperand(0).getValueType() == MVT::i1)
5470 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
5471 DAG.getConstantFP(1.0, Op.getValueType()),
5472 DAG.getConstantFP(0.0, Op.getValueType()));
5474 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
5475 "UINT_TO_FP is supported only with FPCVT");
5477 // If we have FCFIDS, then use it when converting to single-precision.
5478 // Otherwise, convert to double-precision and then round.
5479 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5480 (Op.getOpcode() == ISD::UINT_TO_FP ?
5481 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
5482 (Op.getOpcode() == ISD::UINT_TO_FP ?
5483 PPCISD::FCFIDU : PPCISD::FCFID);
5484 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5485 MVT::f32 : MVT::f64;
5487 if (Op.getOperand(0).getValueType() == MVT::i64) {
5488 SDValue SINT = Op.getOperand(0);
5489 // When converting to single-precision, we actually need to convert
5490 // to double-precision first and then round to single-precision.
5491 // To avoid double-rounding effects during that operation, we have
5492 // to prepare the input operand. Bits that might be truncated when
5493 // converting to double-precision are replaced by a bit that won't
5494 // be lost at this stage, but is below the single-precision rounding
5497 // However, if -enable-unsafe-fp-math is in effect, accept double
5498 // rounding to avoid the extra overhead.
5499 if (Op.getValueType() == MVT::f32 &&
5500 !Subtarget.hasFPCVT() &&
5501 !DAG.getTarget().Options.UnsafeFPMath) {
5503 // Twiddle input to make sure the low 11 bits are zero. (If this
5504 // is the case, we are guaranteed the value will fit into the 53 bit
5505 // mantissa of an IEEE double-precision value without rounding.)
5506 // If any of those low 11 bits were not zero originally, make sure
5507 // bit 12 (value 2048) is set instead, so that the final rounding
5508 // to single-precision gets the correct result.
5509 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5510 SINT, DAG.getConstant(2047, MVT::i64));
5511 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
5512 Round, DAG.getConstant(2047, MVT::i64));
5513 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
5514 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5515 Round, DAG.getConstant(-2048, MVT::i64));
5517 // However, we cannot use that value unconditionally: if the magnitude
5518 // of the input value is small, the bit-twiddling we did above might
5519 // end up visibly changing the output. Fortunately, in that case, we
5520 // don't need to twiddle bits since the original input will convert
5521 // exactly to double-precision floating-point already. Therefore,
5522 // construct a conditional to use the original value if the top 11
5523 // bits are all sign-bit copies, and use the rounded value computed
5525 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
5526 SINT, DAG.getConstant(53, MVT::i32));
5527 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
5528 Cond, DAG.getConstant(1, MVT::i64));
5529 Cond = DAG.getSetCC(dl, MVT::i32,
5530 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
5532 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
5535 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
5536 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
5538 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5539 FP = DAG.getNode(ISD::FP_ROUND, dl,
5540 MVT::f32, FP, DAG.getIntPtrConstant(0));
5544 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
5545 "Unhandled INT_TO_FP type in custom expander!");
5546 // Since we only generate this in 64-bit mode, we can take advantage of
5547 // 64-bit registers. In particular, sign extend the input value into the
5548 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
5549 // then lfd it and fcfid it.
5550 MachineFunction &MF = DAG.getMachineFunction();
5551 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
5552 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5555 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
5556 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
5557 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5559 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
5560 MachinePointerInfo::getFixedStack(FrameIdx),
5563 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
5564 "Expected an i32 store");
5565 MachineMemOperand *MMO =
5566 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
5567 MachineMemOperand::MOLoad, 4, 4);
5568 SDValue Ops[] = { Store, FIdx };
5569 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
5570 PPCISD::LFIWZX : PPCISD::LFIWAX,
5571 dl, DAG.getVTList(MVT::f64, MVT::Other),
5572 Ops, MVT::i32, MMO);
5574 assert(Subtarget.isPPC64() &&
5575 "i32->FP without LFIWAX supported only on PPC64");
5577 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
5578 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5580 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
5583 // STD the extended value into the stack slot.
5584 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
5585 MachinePointerInfo::getFixedStack(FrameIdx),
5588 // Load the value as a double.
5589 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
5590 MachinePointerInfo::getFixedStack(FrameIdx),
5591 false, false, false, 0);
5594 // FCFID it and return it.
5595 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
5596 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5597 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
5601 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
5602 SelectionDAG &DAG) const {
5605 The rounding mode is in bits 30:31 of FPSR, and has the following
5612 FLT_ROUNDS, on the other hand, expects the following:
5619 To perform the conversion, we do:
5620 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
5623 MachineFunction &MF = DAG.getMachineFunction();
5624 EVT VT = Op.getValueType();
5625 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5627 // Save FP Control Word to register
5629 MVT::f64, // return register
5630 MVT::Glue // unused in this context
5632 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
5634 // Save FP register to stack slot
5635 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5636 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
5637 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
5638 StackSlot, MachinePointerInfo(), false, false,0);
5640 // Load FP Control Word from low 32 bits of stack slot.
5641 SDValue Four = DAG.getConstant(4, PtrVT);
5642 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
5643 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
5644 false, false, false, 0);
5646 // Transform as necessary
5648 DAG.getNode(ISD::AND, dl, MVT::i32,
5649 CWD, DAG.getConstant(3, MVT::i32));
5651 DAG.getNode(ISD::SRL, dl, MVT::i32,
5652 DAG.getNode(ISD::AND, dl, MVT::i32,
5653 DAG.getNode(ISD::XOR, dl, MVT::i32,
5654 CWD, DAG.getConstant(3, MVT::i32)),
5655 DAG.getConstant(3, MVT::i32)),
5656 DAG.getConstant(1, MVT::i32));
5659 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
5661 return DAG.getNode((VT.getSizeInBits() < 16 ?
5662 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
5665 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5666 EVT VT = Op.getValueType();
5667 unsigned BitWidth = VT.getSizeInBits();
5669 assert(Op.getNumOperands() == 3 &&
5670 VT == Op.getOperand(1).getValueType() &&
5673 // Expand into a bunch of logical ops. Note that these ops
5674 // depend on the PPC behavior for oversized shift amounts.
5675 SDValue Lo = Op.getOperand(0);
5676 SDValue Hi = Op.getOperand(1);
5677 SDValue Amt = Op.getOperand(2);
5678 EVT AmtVT = Amt.getValueType();
5680 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5681 DAG.getConstant(BitWidth, AmtVT), Amt);
5682 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
5683 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5684 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5685 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5686 DAG.getConstant(-BitWidth, AmtVT));
5687 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5688 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5689 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
5690 SDValue OutOps[] = { OutLo, OutHi };
5691 return DAG.getMergeValues(OutOps, dl);
5694 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5695 EVT VT = Op.getValueType();
5697 unsigned BitWidth = VT.getSizeInBits();
5698 assert(Op.getNumOperands() == 3 &&
5699 VT == Op.getOperand(1).getValueType() &&
5702 // Expand into a bunch of logical ops. Note that these ops
5703 // depend on the PPC behavior for oversized shift amounts.
5704 SDValue Lo = Op.getOperand(0);
5705 SDValue Hi = Op.getOperand(1);
5706 SDValue Amt = Op.getOperand(2);
5707 EVT AmtVT = Amt.getValueType();
5709 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5710 DAG.getConstant(BitWidth, AmtVT), Amt);
5711 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5712 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5713 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5714 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5715 DAG.getConstant(-BitWidth, AmtVT));
5716 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
5717 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5718 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
5719 SDValue OutOps[] = { OutLo, OutHi };
5720 return DAG.getMergeValues(OutOps, dl);
5723 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
5725 EVT VT = Op.getValueType();
5726 unsigned BitWidth = VT.getSizeInBits();
5727 assert(Op.getNumOperands() == 3 &&
5728 VT == Op.getOperand(1).getValueType() &&
5731 // Expand into a bunch of logical ops, followed by a select_cc.
5732 SDValue Lo = Op.getOperand(0);
5733 SDValue Hi = Op.getOperand(1);
5734 SDValue Amt = Op.getOperand(2);
5735 EVT AmtVT = Amt.getValueType();
5737 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5738 DAG.getConstant(BitWidth, AmtVT), Amt);
5739 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5740 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5741 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5742 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5743 DAG.getConstant(-BitWidth, AmtVT));
5744 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
5745 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
5746 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
5747 Tmp4, Tmp6, ISD::SETLE);
5748 SDValue OutOps[] = { OutLo, OutHi };
5749 return DAG.getMergeValues(OutOps, dl);
5752 //===----------------------------------------------------------------------===//
5753 // Vector related lowering.
5756 /// BuildSplatI - Build a canonical splati of Val with an element size of
5757 /// SplatSize. Cast the result to VT.
5758 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
5759 SelectionDAG &DAG, SDLoc dl) {
5760 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
5762 static const EVT VTys[] = { // canonical VT to use for each size.
5763 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
5766 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
5768 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
5772 EVT CanonicalVT = VTys[SplatSize-1];
5774 // Build a canonical splat for this value.
5775 SDValue Elt = DAG.getConstant(Val, MVT::i32);
5776 SmallVector<SDValue, 8> Ops;
5777 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
5778 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
5779 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
5782 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
5783 /// specified intrinsic ID.
5784 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
5785 SelectionDAG &DAG, SDLoc dl,
5786 EVT DestVT = MVT::Other) {
5787 if (DestVT == MVT::Other) DestVT = Op.getValueType();
5788 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5789 DAG.getConstant(IID, MVT::i32), Op);
5792 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
5793 /// specified intrinsic ID.
5794 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
5795 SelectionDAG &DAG, SDLoc dl,
5796 EVT DestVT = MVT::Other) {
5797 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
5798 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5799 DAG.getConstant(IID, MVT::i32), LHS, RHS);
5802 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
5803 /// specified intrinsic ID.
5804 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
5805 SDValue Op2, SelectionDAG &DAG,
5806 SDLoc dl, EVT DestVT = MVT::Other) {
5807 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
5808 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5809 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
5813 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
5814 /// amount. The result has the specified value type.
5815 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
5816 EVT VT, SelectionDAG &DAG, SDLoc dl) {
5817 // Force LHS/RHS to be the right type.
5818 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
5819 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
5822 for (unsigned i = 0; i != 16; ++i)
5824 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
5825 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5828 // If this is a case we can't handle, return null and let the default
5829 // expansion code take care of it. If we CAN select this case, and if it
5830 // selects to a single instruction, return Op. Otherwise, if we can codegen
5831 // this case more efficiently than a constant pool load, lower it to the
5832 // sequence of ops that should be used.
5833 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
5834 SelectionDAG &DAG) const {
5836 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5837 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
5839 // Check if this is a splat of a constant value.
5840 APInt APSplatBits, APSplatUndef;
5841 unsigned SplatBitSize;
5843 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
5844 HasAnyUndefs, 0, true) || SplatBitSize > 32)
5847 unsigned SplatBits = APSplatBits.getZExtValue();
5848 unsigned SplatUndef = APSplatUndef.getZExtValue();
5849 unsigned SplatSize = SplatBitSize / 8;
5851 // First, handle single instruction cases.
5854 if (SplatBits == 0) {
5855 // Canonicalize all zero vectors to be v4i32.
5856 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5857 SDValue Z = DAG.getConstant(0, MVT::i32);
5858 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5859 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
5864 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
5865 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
5867 if (SextVal >= -16 && SextVal <= 15)
5868 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
5871 // Two instruction sequences.
5873 // If this value is in the range [-32,30] and is even, use:
5874 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
5875 // If this value is in the range [17,31] and is odd, use:
5876 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
5877 // If this value is in the range [-31,-17] and is odd, use:
5878 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
5879 // Note the last two are three-instruction sequences.
5880 if (SextVal >= -32 && SextVal <= 31) {
5881 // To avoid having these optimizations undone by constant folding,
5882 // we convert to a pseudo that will be expanded later into one of
5884 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
5885 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
5886 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
5887 SDValue EltSize = DAG.getConstant(SplatSize, MVT::i32);
5888 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
5889 if (VT == Op.getValueType())
5892 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
5895 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
5896 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
5898 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
5899 // Make -1 and vspltisw -1:
5900 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
5902 // Make the VSLW intrinsic, computing 0x8000_0000.
5903 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
5906 // xor by OnesV to invert it.
5907 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5908 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5911 // The remaining cases assume either big endian element order or
5912 // a splat-size that equates to the element size of the vector
5913 // to be built. An example that doesn't work for little endian is
5914 // {0, -1, 0, -1, 0, -1, 0, -1} which has a splat size of 32 bits
5915 // and a vector element size of 16 bits. The code below will
5916 // produce the vector in big endian element order, which for little
5917 // endian is {-1, 0, -1, 0, -1, 0, -1, 0}.
5919 // For now, just avoid these optimizations in that case.
5920 // FIXME: Develop correct optimizations for LE with mismatched
5921 // splat and element sizes.
5923 if (Subtarget.isLittleEndian() &&
5924 SplatSize != Op.getValueType().getVectorElementType().getSizeInBits())
5927 // Check to see if this is a wide variety of vsplti*, binop self cases.
5928 static const signed char SplatCsts[] = {
5929 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
5930 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
5933 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
5934 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
5935 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
5936 int i = SplatCsts[idx];
5938 // Figure out what shift amount will be used by altivec if shifted by i in
5940 unsigned TypeShiftAmt = i & (SplatBitSize-1);
5942 // vsplti + shl self.
5943 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
5944 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5945 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5946 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
5947 Intrinsic::ppc_altivec_vslw
5949 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5950 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5953 // vsplti + srl self.
5954 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5955 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5956 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5957 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
5958 Intrinsic::ppc_altivec_vsrw
5960 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5961 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5964 // vsplti + sra self.
5965 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5966 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5967 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5968 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
5969 Intrinsic::ppc_altivec_vsraw
5971 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5972 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5975 // vsplti + rol self.
5976 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
5977 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
5978 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5979 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5980 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
5981 Intrinsic::ppc_altivec_vrlw
5983 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5984 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5987 // t = vsplti c, result = vsldoi t, t, 1
5988 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
5989 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5990 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
5992 // t = vsplti c, result = vsldoi t, t, 2
5993 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
5994 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5995 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
5997 // t = vsplti c, result = vsldoi t, t, 3
5998 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
5999 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
6000 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
6007 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
6008 /// the specified operations to build the shuffle.
6009 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
6010 SDValue RHS, SelectionDAG &DAG,
6012 unsigned OpNum = (PFEntry >> 26) & 0x0F;
6013 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
6014 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
6017 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
6029 if (OpNum == OP_COPY) {
6030 if (LHSID == (1*9+2)*9+3) return LHS;
6031 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
6035 SDValue OpLHS, OpRHS;
6036 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
6037 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
6041 default: llvm_unreachable("Unknown i32 permute!");
6043 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
6044 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
6045 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
6046 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
6049 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
6050 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
6051 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
6052 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
6055 for (unsigned i = 0; i != 16; ++i)
6056 ShufIdxs[i] = (i&3)+0;
6059 for (unsigned i = 0; i != 16; ++i)
6060 ShufIdxs[i] = (i&3)+4;
6063 for (unsigned i = 0; i != 16; ++i)
6064 ShufIdxs[i] = (i&3)+8;
6067 for (unsigned i = 0; i != 16; ++i)
6068 ShufIdxs[i] = (i&3)+12;
6071 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
6073 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
6075 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
6077 EVT VT = OpLHS.getValueType();
6078 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
6079 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
6080 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
6081 return DAG.getNode(ISD::BITCAST, dl, VT, T);
6084 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
6085 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
6086 /// return the code it can be lowered into. Worst case, it can always be
6087 /// lowered into a vperm.
6088 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
6089 SelectionDAG &DAG) const {
6091 SDValue V1 = Op.getOperand(0);
6092 SDValue V2 = Op.getOperand(1);
6093 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6094 EVT VT = Op.getValueType();
6095 bool isLittleEndian = Subtarget.isLittleEndian();
6097 // Cases that are handled by instructions that take permute immediates
6098 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
6099 // selected by the instruction selector.
6100 if (V2.getOpcode() == ISD::UNDEF) {
6101 if (PPC::isSplatShuffleMask(SVOp, 1) ||
6102 PPC::isSplatShuffleMask(SVOp, 2) ||
6103 PPC::isSplatShuffleMask(SVOp, 4) ||
6104 PPC::isVPKUWUMShuffleMask(SVOp, 1, DAG) ||
6105 PPC::isVPKUHUMShuffleMask(SVOp, 1, DAG) ||
6106 PPC::isVSLDOIShuffleMask(SVOp, 1, DAG) != -1 ||
6107 PPC::isVMRGLShuffleMask(SVOp, 1, 1, DAG) ||
6108 PPC::isVMRGLShuffleMask(SVOp, 2, 1, DAG) ||
6109 PPC::isVMRGLShuffleMask(SVOp, 4, 1, DAG) ||
6110 PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) ||
6111 PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) ||
6112 PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG)) {
6117 // Altivec has a variety of "shuffle immediates" that take two vector inputs
6118 // and produce a fixed permutation. If any of these match, do not lower to
6120 unsigned int ShuffleKind = isLittleEndian ? 2 : 0;
6121 if (PPC::isVPKUWUMShuffleMask(SVOp, ShuffleKind, DAG) ||
6122 PPC::isVPKUHUMShuffleMask(SVOp, ShuffleKind, DAG) ||
6123 PPC::isVSLDOIShuffleMask(SVOp, ShuffleKind, DAG) != -1 ||
6124 PPC::isVMRGLShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6125 PPC::isVMRGLShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6126 PPC::isVMRGLShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
6127 PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6128 PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6129 PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG))
6132 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
6133 // perfect shuffle table to emit an optimal matching sequence.
6134 ArrayRef<int> PermMask = SVOp->getMask();
6136 unsigned PFIndexes[4];
6137 bool isFourElementShuffle = true;
6138 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
6139 unsigned EltNo = 8; // Start out undef.
6140 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
6141 if (PermMask[i*4+j] < 0)
6142 continue; // Undef, ignore it.
6144 unsigned ByteSource = PermMask[i*4+j];
6145 if ((ByteSource & 3) != j) {
6146 isFourElementShuffle = false;
6151 EltNo = ByteSource/4;
6152 } else if (EltNo != ByteSource/4) {
6153 isFourElementShuffle = false;
6157 PFIndexes[i] = EltNo;
6160 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
6161 // perfect shuffle vector to determine if it is cost effective to do this as
6162 // discrete instructions, or whether we should use a vperm.
6163 // For now, we skip this for little endian until such time as we have a
6164 // little-endian perfect shuffle table.
6165 if (isFourElementShuffle && !isLittleEndian) {
6166 // Compute the index in the perfect shuffle table.
6167 unsigned PFTableIndex =
6168 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
6170 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6171 unsigned Cost = (PFEntry >> 30);
6173 // Determining when to avoid vperm is tricky. Many things affect the cost
6174 // of vperm, particularly how many times the perm mask needs to be computed.
6175 // For example, if the perm mask can be hoisted out of a loop or is already
6176 // used (perhaps because there are multiple permutes with the same shuffle
6177 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
6178 // the loop requires an extra register.
6180 // As a compromise, we only emit discrete instructions if the shuffle can be
6181 // generated in 3 or fewer operations. When we have loop information
6182 // available, if this block is within a loop, we should avoid using vperm
6183 // for 3-operation perms and use a constant pool load instead.
6185 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
6188 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
6189 // vector that will get spilled to the constant pool.
6190 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
6192 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
6193 // that it is in input element units, not in bytes. Convert now.
6195 // For little endian, the order of the input vectors is reversed, and
6196 // the permutation mask is complemented with respect to 31. This is
6197 // necessary to produce proper semantics with the big-endian-biased vperm
6199 EVT EltVT = V1.getValueType().getVectorElementType();
6200 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
6202 SmallVector<SDValue, 16> ResultMask;
6203 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
6204 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
6206 for (unsigned j = 0; j != BytesPerElement; ++j)
6208 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement+j),
6211 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
6215 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
6218 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
6221 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
6225 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
6226 /// altivec comparison. If it is, return true and fill in Opc/isDot with
6227 /// information about the intrinsic.
6228 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
6230 unsigned IntrinsicID =
6231 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
6234 switch (IntrinsicID) {
6235 default: return false;
6236 // Comparison predicates.
6237 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
6238 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
6239 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
6240 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
6241 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
6242 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
6243 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
6244 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
6245 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
6246 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
6247 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
6248 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
6249 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
6251 // Normal Comparisons.
6252 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
6253 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
6254 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
6255 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
6256 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
6257 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
6258 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
6259 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
6260 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
6261 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
6262 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
6263 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
6264 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
6269 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
6270 /// lower, do it, otherwise return null.
6271 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
6272 SelectionDAG &DAG) const {
6273 // If this is a lowered altivec predicate compare, CompareOpc is set to the
6274 // opcode number of the comparison.
6278 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
6279 return SDValue(); // Don't custom lower most intrinsics.
6281 // If this is a non-dot comparison, make the VCMP node and we are done.
6283 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
6284 Op.getOperand(1), Op.getOperand(2),
6285 DAG.getConstant(CompareOpc, MVT::i32));
6286 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
6289 // Create the PPCISD altivec 'dot' comparison node.
6291 Op.getOperand(2), // LHS
6292 Op.getOperand(3), // RHS
6293 DAG.getConstant(CompareOpc, MVT::i32)
6295 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
6296 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
6298 // Now that we have the comparison, emit a copy from the CR to a GPR.
6299 // This is flagged to the above dot comparison.
6300 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
6301 DAG.getRegister(PPC::CR6, MVT::i32),
6302 CompNode.getValue(1));
6304 // Unpack the result based on how the target uses it.
6305 unsigned BitNo; // Bit # of CR6.
6306 bool InvertBit; // Invert result?
6307 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
6308 default: // Can't happen, don't crash on invalid number though.
6309 case 0: // Return the value of the EQ bit of CR6.
6310 BitNo = 0; InvertBit = false;
6312 case 1: // Return the inverted value of the EQ bit of CR6.
6313 BitNo = 0; InvertBit = true;
6315 case 2: // Return the value of the LT bit of CR6.
6316 BitNo = 2; InvertBit = false;
6318 case 3: // Return the inverted value of the LT bit of CR6.
6319 BitNo = 2; InvertBit = true;
6323 // Shift the bit into the low position.
6324 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
6325 DAG.getConstant(8-(3-BitNo), MVT::i32));
6327 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
6328 DAG.getConstant(1, MVT::i32));
6330 // If we are supposed to, toggle the bit.
6332 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
6333 DAG.getConstant(1, MVT::i32));
6337 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
6338 SelectionDAG &DAG) const {
6340 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
6341 // instructions), but for smaller types, we need to first extend up to v2i32
6342 // before doing going farther.
6343 if (Op.getValueType() == MVT::v2i64) {
6344 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
6345 if (ExtVT != MVT::v2i32) {
6346 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
6347 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
6348 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
6349 ExtVT.getVectorElementType(), 4)));
6350 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
6351 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
6352 DAG.getValueType(MVT::v2i32));
6361 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
6362 SelectionDAG &DAG) const {
6364 // Create a stack slot that is 16-byte aligned.
6365 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6366 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
6367 EVT PtrVT = getPointerTy();
6368 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6370 // Store the input value into Value#0 of the stack slot.
6371 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
6372 Op.getOperand(0), FIdx, MachinePointerInfo(),
6375 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
6376 false, false, false, 0);
6379 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
6381 if (Op.getValueType() == MVT::v4i32) {
6382 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6384 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
6385 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
6387 SDValue RHSSwap = // = vrlw RHS, 16
6388 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
6390 // Shrinkify inputs to v8i16.
6391 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
6392 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
6393 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
6395 // Low parts multiplied together, generating 32-bit results (we ignore the
6397 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
6398 LHS, RHS, DAG, dl, MVT::v4i32);
6400 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
6401 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
6402 // Shift the high parts up 16 bits.
6403 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
6405 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
6406 } else if (Op.getValueType() == MVT::v8i16) {
6407 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6409 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
6411 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
6412 LHS, RHS, Zero, DAG, dl);
6413 } else if (Op.getValueType() == MVT::v16i8) {
6414 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6415 bool isLittleEndian = Subtarget.isLittleEndian();
6417 // Multiply the even 8-bit parts, producing 16-bit sums.
6418 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
6419 LHS, RHS, DAG, dl, MVT::v8i16);
6420 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
6422 // Multiply the odd 8-bit parts, producing 16-bit sums.
6423 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
6424 LHS, RHS, DAG, dl, MVT::v8i16);
6425 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
6427 // Merge the results together. Because vmuleub and vmuloub are
6428 // instructions with a big-endian bias, we must reverse the
6429 // element numbering and reverse the meaning of "odd" and "even"
6430 // when generating little endian code.
6432 for (unsigned i = 0; i != 8; ++i) {
6433 if (isLittleEndian) {
6435 Ops[i*2+1] = 2*i+16;
6438 Ops[i*2+1] = 2*i+1+16;
6442 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
6444 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
6446 llvm_unreachable("Unknown mul to lower!");
6450 /// LowerOperation - Provide custom lowering hooks for some operations.
6452 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6453 switch (Op.getOpcode()) {
6454 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
6455 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6456 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
6457 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6458 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6459 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6460 case ISD::SETCC: return LowerSETCC(Op, DAG);
6461 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
6462 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
6464 return LowerVASTART(Op, DAG, Subtarget);
6467 return LowerVAARG(Op, DAG, Subtarget);
6470 return LowerVACOPY(Op, DAG, Subtarget);
6472 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget);
6473 case ISD::DYNAMIC_STACKALLOC:
6474 return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget);
6476 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
6477 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
6479 case ISD::LOAD: return LowerLOAD(Op, DAG);
6480 case ISD::STORE: return LowerSTORE(Op, DAG);
6481 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
6482 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6483 case ISD::FP_TO_UINT:
6484 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
6486 case ISD::UINT_TO_FP:
6487 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6488 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6490 // Lower 64-bit shifts.
6491 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
6492 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
6493 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
6495 // Vector-related lowering.
6496 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6497 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6498 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6499 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6500 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
6501 case ISD::MUL: return LowerMUL(Op, DAG);
6503 // For counter-based loop handling.
6504 case ISD::INTRINSIC_W_CHAIN: return SDValue();
6506 // Frame & Return address.
6507 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6508 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6512 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
6513 SmallVectorImpl<SDValue>&Results,
6514 SelectionDAG &DAG) const {
6515 const TargetMachine &TM = getTargetMachine();
6517 switch (N->getOpcode()) {
6519 llvm_unreachable("Do not know how to custom type legalize this operation!");
6520 case ISD::READCYCLECOUNTER: {
6521 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
6522 SDValue RTB = DAG.getNode(PPCISD::READ_TIME_BASE, dl, VTs, N->getOperand(0));
6524 Results.push_back(RTB);
6525 Results.push_back(RTB.getValue(1));
6526 Results.push_back(RTB.getValue(2));
6529 case ISD::INTRINSIC_W_CHAIN: {
6530 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
6531 Intrinsic::ppc_is_decremented_ctr_nonzero)
6534 assert(N->getValueType(0) == MVT::i1 &&
6535 "Unexpected result type for CTR decrement intrinsic");
6536 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
6537 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
6538 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
6541 Results.push_back(NewInt);
6542 Results.push_back(NewInt.getValue(1));
6546 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
6547 || TM.getSubtarget<PPCSubtarget>().isPPC64())
6550 EVT VT = N->getValueType(0);
6552 if (VT == MVT::i64) {
6553 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget);
6555 Results.push_back(NewNode);
6556 Results.push_back(NewNode.getValue(1));
6560 case ISD::FP_ROUND_INREG: {
6561 assert(N->getValueType(0) == MVT::ppcf128);
6562 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
6563 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6564 MVT::f64, N->getOperand(0),
6565 DAG.getIntPtrConstant(0));
6566 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6567 MVT::f64, N->getOperand(0),
6568 DAG.getIntPtrConstant(1));
6570 // Add the two halves of the long double in round-to-zero mode.
6571 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
6573 // We know the low half is about to be thrown away, so just use something
6575 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
6579 case ISD::FP_TO_SINT:
6580 // LowerFP_TO_INT() can only handle f32 and f64.
6581 if (N->getOperand(0).getValueType() == MVT::ppcf128)
6583 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
6589 //===----------------------------------------------------------------------===//
6590 // Other Lowering Code
6591 //===----------------------------------------------------------------------===//
6593 static Instruction* callIntrinsic(IRBuilder<> &Builder, Intrinsic::ID Id) {
6594 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
6595 Function *Func = Intrinsic::getDeclaration(M, Id);
6596 return Builder.CreateCall(Func);
6599 // The mappings for emitLeading/TrailingFence is taken from
6600 // http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
6601 Instruction* PPCTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
6602 AtomicOrdering Ord, bool IsStore,
6603 bool IsLoad) const {
6604 if (Ord == SequentiallyConsistent)
6605 return callIntrinsic(Builder, Intrinsic::ppc_sync);
6606 else if (isAtLeastRelease(Ord))
6607 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
6612 Instruction* PPCTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
6613 AtomicOrdering Ord, bool IsStore,
6614 bool IsLoad) const {
6615 if (IsLoad && isAtLeastAcquire(Ord))
6616 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
6617 // FIXME: this is too conservative, a dependent branch + isync is enough.
6618 // See http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html and
6619 // http://www.rdrop.com/users/paulmck/scalability/paper/N2745r.2011.03.04a.html
6620 // and http://www.cl.cam.ac.uk/~pes20/cppppc/ for justification.
6626 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
6627 bool is64bit, unsigned BinOpcode) const {
6628 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6629 const TargetInstrInfo *TII =
6630 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6632 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6633 MachineFunction *F = BB->getParent();
6634 MachineFunction::iterator It = BB;
6637 unsigned dest = MI->getOperand(0).getReg();
6638 unsigned ptrA = MI->getOperand(1).getReg();
6639 unsigned ptrB = MI->getOperand(2).getReg();
6640 unsigned incr = MI->getOperand(3).getReg();
6641 DebugLoc dl = MI->getDebugLoc();
6643 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6644 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6645 F->insert(It, loopMBB);
6646 F->insert(It, exitMBB);
6647 exitMBB->splice(exitMBB->begin(), BB,
6648 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6649 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6651 MachineRegisterInfo &RegInfo = F->getRegInfo();
6652 unsigned TmpReg = (!BinOpcode) ? incr :
6653 RegInfo.createVirtualRegister( is64bit ? &PPC::G8RCRegClass
6654 : &PPC::GPRCRegClass);
6658 // fallthrough --> loopMBB
6659 BB->addSuccessor(loopMBB);
6662 // l[wd]arx dest, ptr
6663 // add r0, dest, incr
6664 // st[wd]cx. r0, ptr
6666 // fallthrough --> exitMBB
6668 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6669 .addReg(ptrA).addReg(ptrB);
6671 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
6672 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6673 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
6674 BuildMI(BB, dl, TII->get(PPC::BCC))
6675 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6676 BB->addSuccessor(loopMBB);
6677 BB->addSuccessor(exitMBB);
6686 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
6687 MachineBasicBlock *BB,
6688 bool is8bit, // operation
6689 unsigned BinOpcode) const {
6690 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6691 const TargetInstrInfo *TII =
6692 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6693 // In 64 bit mode we have to use 64 bits for addresses, even though the
6694 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
6695 // registers without caring whether they're 32 or 64, but here we're
6696 // doing actual arithmetic on the addresses.
6697 bool is64bit = Subtarget.isPPC64();
6698 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6700 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6701 MachineFunction *F = BB->getParent();
6702 MachineFunction::iterator It = BB;
6705 unsigned dest = MI->getOperand(0).getReg();
6706 unsigned ptrA = MI->getOperand(1).getReg();
6707 unsigned ptrB = MI->getOperand(2).getReg();
6708 unsigned incr = MI->getOperand(3).getReg();
6709 DebugLoc dl = MI->getDebugLoc();
6711 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6712 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6713 F->insert(It, loopMBB);
6714 F->insert(It, exitMBB);
6715 exitMBB->splice(exitMBB->begin(), BB,
6716 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6717 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6719 MachineRegisterInfo &RegInfo = F->getRegInfo();
6720 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
6721 : &PPC::GPRCRegClass;
6722 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6723 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6724 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6725 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
6726 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6727 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6728 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6729 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6730 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
6731 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6732 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6734 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
6738 // fallthrough --> loopMBB
6739 BB->addSuccessor(loopMBB);
6741 // The 4-byte load must be aligned, while a char or short may be
6742 // anywhere in the word. Hence all this nasty bookkeeping code.
6743 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6744 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6745 // xori shift, shift1, 24 [16]
6746 // rlwinm ptr, ptr1, 0, 0, 29
6747 // slw incr2, incr, shift
6748 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6749 // slw mask, mask2, shift
6751 // lwarx tmpDest, ptr
6752 // add tmp, tmpDest, incr2
6753 // andc tmp2, tmpDest, mask
6754 // and tmp3, tmp, mask
6755 // or tmp4, tmp3, tmp2
6758 // fallthrough --> exitMBB
6759 // srw dest, tmpDest, shift
6760 if (ptrA != ZeroReg) {
6761 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6762 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6763 .addReg(ptrA).addReg(ptrB);
6767 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6768 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6769 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6770 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6772 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6773 .addReg(Ptr1Reg).addImm(0).addImm(61);
6775 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6776 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6777 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
6778 .addReg(incr).addReg(ShiftReg);
6780 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6782 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6783 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
6785 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6786 .addReg(Mask2Reg).addReg(ShiftReg);
6789 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6790 .addReg(ZeroReg).addReg(PtrReg);
6792 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
6793 .addReg(Incr2Reg).addReg(TmpDestReg);
6794 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
6795 .addReg(TmpDestReg).addReg(MaskReg);
6796 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
6797 .addReg(TmpReg).addReg(MaskReg);
6798 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
6799 .addReg(Tmp3Reg).addReg(Tmp2Reg);
6800 BuildMI(BB, dl, TII->get(PPC::STWCX))
6801 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
6802 BuildMI(BB, dl, TII->get(PPC::BCC))
6803 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6804 BB->addSuccessor(loopMBB);
6805 BB->addSuccessor(exitMBB);
6810 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
6815 llvm::MachineBasicBlock*
6816 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
6817 MachineBasicBlock *MBB) const {
6818 DebugLoc DL = MI->getDebugLoc();
6819 const TargetInstrInfo *TII =
6820 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6822 MachineFunction *MF = MBB->getParent();
6823 MachineRegisterInfo &MRI = MF->getRegInfo();
6825 const BasicBlock *BB = MBB->getBasicBlock();
6826 MachineFunction::iterator I = MBB;
6830 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6831 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6833 unsigned DstReg = MI->getOperand(0).getReg();
6834 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
6835 assert(RC->hasType(MVT::i32) && "Invalid destination!");
6836 unsigned mainDstReg = MRI.createVirtualRegister(RC);
6837 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
6839 MVT PVT = getPointerTy();
6840 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6841 "Invalid Pointer Size!");
6842 // For v = setjmp(buf), we generate
6845 // SjLjSetup mainMBB
6851 // buf[LabelOffset] = LR
6855 // v = phi(main, restore)
6858 MachineBasicBlock *thisMBB = MBB;
6859 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
6860 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
6861 MF->insert(I, mainMBB);
6862 MF->insert(I, sinkMBB);
6864 MachineInstrBuilder MIB;
6866 // Transfer the remainder of BB and its successor edges to sinkMBB.
6867 sinkMBB->splice(sinkMBB->begin(), MBB,
6868 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
6869 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
6871 // Note that the structure of the jmp_buf used here is not compatible
6872 // with that used by libc, and is not designed to be. Specifically, it
6873 // stores only those 'reserved' registers that LLVM does not otherwise
6874 // understand how to spill. Also, by convention, by the time this
6875 // intrinsic is called, Clang has already stored the frame address in the
6876 // first slot of the buffer and stack address in the third. Following the
6877 // X86 target code, we'll store the jump address in the second slot. We also
6878 // need to save the TOC pointer (R2) to handle jumps between shared
6879 // libraries, and that will be stored in the fourth slot. The thread
6880 // identifier (R13) is not affected.
6883 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6884 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6885 const int64_t BPOffset = 4 * PVT.getStoreSize();
6887 // Prepare IP either in reg.
6888 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
6889 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
6890 unsigned BufReg = MI->getOperand(1).getReg();
6892 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
6893 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
6897 MIB.setMemRefs(MMOBegin, MMOEnd);
6900 // Naked functions never have a base pointer, and so we use r1. For all
6901 // other functions, this decision must be delayed until during PEI.
6903 if (MF->getFunction()->getAttributes().hasAttribute(
6904 AttributeSet::FunctionIndex, Attribute::Naked))
6905 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
6907 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
6909 MIB = BuildMI(*thisMBB, MI, DL,
6910 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
6914 MIB.setMemRefs(MMOBegin, MMOEnd);
6917 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
6918 const PPCRegisterInfo *TRI =
6919 getTargetMachine().getSubtarget<PPCSubtarget>().getRegisterInfo();
6920 MIB.addRegMask(TRI->getNoPreservedMask());
6922 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
6924 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
6926 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
6928 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
6929 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
6933 MIB = BuildMI(mainMBB, DL,
6934 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
6937 if (Subtarget.isPPC64()) {
6938 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
6940 .addImm(LabelOffset)
6943 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
6945 .addImm(LabelOffset)
6949 MIB.setMemRefs(MMOBegin, MMOEnd);
6951 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
6952 mainMBB->addSuccessor(sinkMBB);
6955 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
6956 TII->get(PPC::PHI), DstReg)
6957 .addReg(mainDstReg).addMBB(mainMBB)
6958 .addReg(restoreDstReg).addMBB(thisMBB);
6960 MI->eraseFromParent();
6965 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
6966 MachineBasicBlock *MBB) const {
6967 DebugLoc DL = MI->getDebugLoc();
6968 const TargetInstrInfo *TII =
6969 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6971 MachineFunction *MF = MBB->getParent();
6972 MachineRegisterInfo &MRI = MF->getRegInfo();
6975 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6976 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6978 MVT PVT = getPointerTy();
6979 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6980 "Invalid Pointer Size!");
6982 const TargetRegisterClass *RC =
6983 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6984 unsigned Tmp = MRI.createVirtualRegister(RC);
6985 // Since FP is only updated here but NOT referenced, it's treated as GPR.
6986 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6987 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6988 unsigned BP = (PVT == MVT::i64) ? PPC::X30 :
6989 (Subtarget.isSVR4ABI() &&
6990 MF->getTarget().getRelocationModel() == Reloc::PIC_ ?
6991 PPC::R29 : PPC::R30);
6993 MachineInstrBuilder MIB;
6995 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6996 const int64_t SPOffset = 2 * PVT.getStoreSize();
6997 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6998 const int64_t BPOffset = 4 * PVT.getStoreSize();
7000 unsigned BufReg = MI->getOperand(0).getReg();
7002 // Reload FP (the jumped-to function may not have had a
7003 // frame pointer, and if so, then its r31 will be restored
7005 if (PVT == MVT::i64) {
7006 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
7010 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
7014 MIB.setMemRefs(MMOBegin, MMOEnd);
7017 if (PVT == MVT::i64) {
7018 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
7019 .addImm(LabelOffset)
7022 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
7023 .addImm(LabelOffset)
7026 MIB.setMemRefs(MMOBegin, MMOEnd);
7029 if (PVT == MVT::i64) {
7030 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
7034 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
7038 MIB.setMemRefs(MMOBegin, MMOEnd);
7041 if (PVT == MVT::i64) {
7042 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
7046 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
7050 MIB.setMemRefs(MMOBegin, MMOEnd);
7053 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
7054 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
7058 MIB.setMemRefs(MMOBegin, MMOEnd);
7062 BuildMI(*MBB, MI, DL,
7063 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
7064 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
7066 MI->eraseFromParent();
7071 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
7072 MachineBasicBlock *BB) const {
7073 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
7074 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
7075 return emitEHSjLjSetJmp(MI, BB);
7076 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
7077 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
7078 return emitEHSjLjLongJmp(MI, BB);
7081 const TargetInstrInfo *TII =
7082 getTargetMachine().getSubtargetImpl()->getInstrInfo();
7084 // To "insert" these instructions we actually have to insert their
7085 // control-flow patterns.
7086 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7087 MachineFunction::iterator It = BB;
7090 MachineFunction *F = BB->getParent();
7092 if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7093 MI->getOpcode() == PPC::SELECT_CC_I8 ||
7094 MI->getOpcode() == PPC::SELECT_I4 ||
7095 MI->getOpcode() == PPC::SELECT_I8)) {
7096 SmallVector<MachineOperand, 2> Cond;
7097 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7098 MI->getOpcode() == PPC::SELECT_CC_I8)
7099 Cond.push_back(MI->getOperand(4));
7101 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
7102 Cond.push_back(MI->getOperand(1));
7104 DebugLoc dl = MI->getDebugLoc();
7105 const TargetInstrInfo *TII =
7106 getTargetMachine().getSubtargetImpl()->getInstrInfo();
7107 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
7108 Cond, MI->getOperand(2).getReg(),
7109 MI->getOperand(3).getReg());
7110 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7111 MI->getOpcode() == PPC::SELECT_CC_I8 ||
7112 MI->getOpcode() == PPC::SELECT_CC_F4 ||
7113 MI->getOpcode() == PPC::SELECT_CC_F8 ||
7114 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
7115 MI->getOpcode() == PPC::SELECT_CC_VSFRC ||
7116 MI->getOpcode() == PPC::SELECT_CC_VSRC ||
7117 MI->getOpcode() == PPC::SELECT_I4 ||
7118 MI->getOpcode() == PPC::SELECT_I8 ||
7119 MI->getOpcode() == PPC::SELECT_F4 ||
7120 MI->getOpcode() == PPC::SELECT_F8 ||
7121 MI->getOpcode() == PPC::SELECT_VRRC ||
7122 MI->getOpcode() == PPC::SELECT_VSFRC ||
7123 MI->getOpcode() == PPC::SELECT_VSRC) {
7124 // The incoming instruction knows the destination vreg to set, the
7125 // condition code register to branch on, the true/false values to
7126 // select between, and a branch opcode to use.
7131 // cmpTY ccX, r1, r2
7133 // fallthrough --> copy0MBB
7134 MachineBasicBlock *thisMBB = BB;
7135 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7136 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7137 DebugLoc dl = MI->getDebugLoc();
7138 F->insert(It, copy0MBB);
7139 F->insert(It, sinkMBB);
7141 // Transfer the remainder of BB and its successor edges to sinkMBB.
7142 sinkMBB->splice(sinkMBB->begin(), BB,
7143 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7144 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7146 // Next, add the true and fallthrough blocks as its successors.
7147 BB->addSuccessor(copy0MBB);
7148 BB->addSuccessor(sinkMBB);
7150 if (MI->getOpcode() == PPC::SELECT_I4 ||
7151 MI->getOpcode() == PPC::SELECT_I8 ||
7152 MI->getOpcode() == PPC::SELECT_F4 ||
7153 MI->getOpcode() == PPC::SELECT_F8 ||
7154 MI->getOpcode() == PPC::SELECT_VRRC ||
7155 MI->getOpcode() == PPC::SELECT_VSFRC ||
7156 MI->getOpcode() == PPC::SELECT_VSRC) {
7157 BuildMI(BB, dl, TII->get(PPC::BC))
7158 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
7160 unsigned SelectPred = MI->getOperand(4).getImm();
7161 BuildMI(BB, dl, TII->get(PPC::BCC))
7162 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
7166 // %FalseValue = ...
7167 // # fallthrough to sinkMBB
7170 // Update machine-CFG edges
7171 BB->addSuccessor(sinkMBB);
7174 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7177 BuildMI(*BB, BB->begin(), dl,
7178 TII->get(PPC::PHI), MI->getOperand(0).getReg())
7179 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
7180 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7181 } else if (MI->getOpcode() == PPC::ReadTB) {
7182 // To read the 64-bit time-base register on a 32-bit target, we read the
7183 // two halves. Should the counter have wrapped while it was being read, we
7184 // need to try again.
7187 // mfspr Rx,TBU # load from TBU
7188 // mfspr Ry,TB # load from TB
7189 // mfspr Rz,TBU # load from TBU
7190 // cmpw crX,Rx,Rz # check if ‘old’=’new’
7191 // bne readLoop # branch if they're not equal
7194 MachineBasicBlock *readMBB = F->CreateMachineBasicBlock(LLVM_BB);
7195 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7196 DebugLoc dl = MI->getDebugLoc();
7197 F->insert(It, readMBB);
7198 F->insert(It, sinkMBB);
7200 // Transfer the remainder of BB and its successor edges to sinkMBB.
7201 sinkMBB->splice(sinkMBB->begin(), BB,
7202 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7203 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7205 BB->addSuccessor(readMBB);
7208 MachineRegisterInfo &RegInfo = F->getRegInfo();
7209 unsigned ReadAgainReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
7210 unsigned LoReg = MI->getOperand(0).getReg();
7211 unsigned HiReg = MI->getOperand(1).getReg();
7213 BuildMI(BB, dl, TII->get(PPC::MFSPR), HiReg).addImm(269);
7214 BuildMI(BB, dl, TII->get(PPC::MFSPR), LoReg).addImm(268);
7215 BuildMI(BB, dl, TII->get(PPC::MFSPR), ReadAgainReg).addImm(269);
7217 unsigned CmpReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
7219 BuildMI(BB, dl, TII->get(PPC::CMPW), CmpReg)
7220 .addReg(HiReg).addReg(ReadAgainReg);
7221 BuildMI(BB, dl, TII->get(PPC::BCC))
7222 .addImm(PPC::PRED_NE).addReg(CmpReg).addMBB(readMBB);
7224 BB->addSuccessor(readMBB);
7225 BB->addSuccessor(sinkMBB);
7227 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
7228 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
7229 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
7230 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
7231 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
7232 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
7233 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
7234 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
7236 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
7237 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
7238 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
7239 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
7240 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
7241 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
7242 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
7243 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
7245 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
7246 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
7247 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
7248 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
7249 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
7250 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
7251 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
7252 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
7254 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
7255 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
7256 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
7257 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
7258 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
7259 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
7260 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
7261 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
7263 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
7264 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND);
7265 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
7266 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND);
7267 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
7268 BB = EmitAtomicBinary(MI, BB, false, PPC::NAND);
7269 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
7270 BB = EmitAtomicBinary(MI, BB, true, PPC::NAND8);
7272 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
7273 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
7274 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
7275 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
7276 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
7277 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
7278 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
7279 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
7281 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
7282 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
7283 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
7284 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
7285 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
7286 BB = EmitAtomicBinary(MI, BB, false, 0);
7287 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
7288 BB = EmitAtomicBinary(MI, BB, true, 0);
7290 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
7291 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
7292 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
7294 unsigned dest = MI->getOperand(0).getReg();
7295 unsigned ptrA = MI->getOperand(1).getReg();
7296 unsigned ptrB = MI->getOperand(2).getReg();
7297 unsigned oldval = MI->getOperand(3).getReg();
7298 unsigned newval = MI->getOperand(4).getReg();
7299 DebugLoc dl = MI->getDebugLoc();
7301 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
7302 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
7303 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
7304 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7305 F->insert(It, loop1MBB);
7306 F->insert(It, loop2MBB);
7307 F->insert(It, midMBB);
7308 F->insert(It, exitMBB);
7309 exitMBB->splice(exitMBB->begin(), BB,
7310 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7311 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7315 // fallthrough --> loopMBB
7316 BB->addSuccessor(loop1MBB);
7319 // l[wd]arx dest, ptr
7320 // cmp[wd] dest, oldval
7323 // st[wd]cx. newval, ptr
7327 // st[wd]cx. dest, ptr
7330 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
7331 .addReg(ptrA).addReg(ptrB);
7332 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
7333 .addReg(oldval).addReg(dest);
7334 BuildMI(BB, dl, TII->get(PPC::BCC))
7335 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7336 BB->addSuccessor(loop2MBB);
7337 BB->addSuccessor(midMBB);
7340 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7341 .addReg(newval).addReg(ptrA).addReg(ptrB);
7342 BuildMI(BB, dl, TII->get(PPC::BCC))
7343 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7344 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7345 BB->addSuccessor(loop1MBB);
7346 BB->addSuccessor(exitMBB);
7349 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7350 .addReg(dest).addReg(ptrA).addReg(ptrB);
7351 BB->addSuccessor(exitMBB);
7356 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
7357 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
7358 // We must use 64-bit registers for addresses when targeting 64-bit,
7359 // since we're actually doing arithmetic on them. Other registers
7361 bool is64bit = Subtarget.isPPC64();
7362 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
7364 unsigned dest = MI->getOperand(0).getReg();
7365 unsigned ptrA = MI->getOperand(1).getReg();
7366 unsigned ptrB = MI->getOperand(2).getReg();
7367 unsigned oldval = MI->getOperand(3).getReg();
7368 unsigned newval = MI->getOperand(4).getReg();
7369 DebugLoc dl = MI->getDebugLoc();
7371 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
7372 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
7373 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
7374 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7375 F->insert(It, loop1MBB);
7376 F->insert(It, loop2MBB);
7377 F->insert(It, midMBB);
7378 F->insert(It, exitMBB);
7379 exitMBB->splice(exitMBB->begin(), BB,
7380 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7381 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7383 MachineRegisterInfo &RegInfo = F->getRegInfo();
7384 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
7385 : &PPC::GPRCRegClass;
7386 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
7387 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
7388 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
7389 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
7390 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
7391 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
7392 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
7393 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
7394 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
7395 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
7396 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
7397 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
7398 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
7400 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
7401 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
7404 // fallthrough --> loopMBB
7405 BB->addSuccessor(loop1MBB);
7407 // The 4-byte load must be aligned, while a char or short may be
7408 // anywhere in the word. Hence all this nasty bookkeeping code.
7409 // add ptr1, ptrA, ptrB [copy if ptrA==0]
7410 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
7411 // xori shift, shift1, 24 [16]
7412 // rlwinm ptr, ptr1, 0, 0, 29
7413 // slw newval2, newval, shift
7414 // slw oldval2, oldval,shift
7415 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
7416 // slw mask, mask2, shift
7417 // and newval3, newval2, mask
7418 // and oldval3, oldval2, mask
7420 // lwarx tmpDest, ptr
7421 // and tmp, tmpDest, mask
7422 // cmpw tmp, oldval3
7425 // andc tmp2, tmpDest, mask
7426 // or tmp4, tmp2, newval3
7431 // stwcx. tmpDest, ptr
7433 // srw dest, tmpDest, shift
7434 if (ptrA != ZeroReg) {
7435 Ptr1Reg = RegInfo.createVirtualRegister(RC);
7436 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
7437 .addReg(ptrA).addReg(ptrB);
7441 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
7442 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
7443 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
7444 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
7446 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
7447 .addReg(Ptr1Reg).addImm(0).addImm(61);
7449 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
7450 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
7451 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
7452 .addReg(newval).addReg(ShiftReg);
7453 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
7454 .addReg(oldval).addReg(ShiftReg);
7456 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
7458 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
7459 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
7460 .addReg(Mask3Reg).addImm(65535);
7462 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
7463 .addReg(Mask2Reg).addReg(ShiftReg);
7464 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
7465 .addReg(NewVal2Reg).addReg(MaskReg);
7466 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
7467 .addReg(OldVal2Reg).addReg(MaskReg);
7470 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
7471 .addReg(ZeroReg).addReg(PtrReg);
7472 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
7473 .addReg(TmpDestReg).addReg(MaskReg);
7474 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
7475 .addReg(TmpReg).addReg(OldVal3Reg);
7476 BuildMI(BB, dl, TII->get(PPC::BCC))
7477 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7478 BB->addSuccessor(loop2MBB);
7479 BB->addSuccessor(midMBB);
7482 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
7483 .addReg(TmpDestReg).addReg(MaskReg);
7484 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
7485 .addReg(Tmp2Reg).addReg(NewVal3Reg);
7486 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
7487 .addReg(ZeroReg).addReg(PtrReg);
7488 BuildMI(BB, dl, TII->get(PPC::BCC))
7489 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7490 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7491 BB->addSuccessor(loop1MBB);
7492 BB->addSuccessor(exitMBB);
7495 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
7496 .addReg(ZeroReg).addReg(PtrReg);
7497 BB->addSuccessor(exitMBB);
7502 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
7504 } else if (MI->getOpcode() == PPC::FADDrtz) {
7505 // This pseudo performs an FADD with rounding mode temporarily forced
7506 // to round-to-zero. We emit this via custom inserter since the FPSCR
7507 // is not modeled at the SelectionDAG level.
7508 unsigned Dest = MI->getOperand(0).getReg();
7509 unsigned Src1 = MI->getOperand(1).getReg();
7510 unsigned Src2 = MI->getOperand(2).getReg();
7511 DebugLoc dl = MI->getDebugLoc();
7513 MachineRegisterInfo &RegInfo = F->getRegInfo();
7514 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
7516 // Save FPSCR value.
7517 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
7519 // Set rounding mode to round-to-zero.
7520 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
7521 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
7523 // Perform addition.
7524 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
7526 // Restore FPSCR value.
7527 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg);
7528 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7529 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
7530 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7531 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
7532 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7533 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
7534 PPC::ANDIo8 : PPC::ANDIo;
7535 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7536 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
7538 MachineRegisterInfo &RegInfo = F->getRegInfo();
7539 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
7540 &PPC::GPRCRegClass :
7541 &PPC::G8RCRegClass);
7543 DebugLoc dl = MI->getDebugLoc();
7544 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
7545 .addReg(MI->getOperand(1).getReg()).addImm(1);
7546 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
7547 MI->getOperand(0).getReg())
7548 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
7550 llvm_unreachable("Unexpected instr type to insert");
7553 MI->eraseFromParent(); // The pseudo instruction is gone now.
7557 //===----------------------------------------------------------------------===//
7558 // Target Optimization Hooks
7559 //===----------------------------------------------------------------------===//
7561 SDValue PPCTargetLowering::getRsqrtEstimate(SDValue Operand,
7562 DAGCombinerInfo &DCI,
7563 unsigned &RefinementSteps,
7564 bool &UseOneConstNR) const {
7565 EVT VT = Operand.getValueType();
7566 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
7567 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
7568 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7569 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7570 // Convergence is quadratic, so we essentially double the number of digits
7571 // correct after every iteration. For both FRE and FRSQRTE, the minimum
7572 // architected relative accuracy is 2^-5. When hasRecipPrec(), this is
7573 // 2^-14. IEEE float has 23 digits and double has 52 digits.
7574 RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3;
7575 if (VT.getScalarType() == MVT::f64)
7577 UseOneConstNR = true;
7578 return DCI.DAG.getNode(PPCISD::FRSQRTE, SDLoc(Operand), VT, Operand);
7583 SDValue PPCTargetLowering::getRecipEstimate(SDValue Operand,
7584 DAGCombinerInfo &DCI,
7585 unsigned &RefinementSteps) const {
7586 EVT VT = Operand.getValueType();
7587 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
7588 (VT == MVT::f64 && Subtarget.hasFRE()) ||
7589 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7590 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7591 // Convergence is quadratic, so we essentially double the number of digits
7592 // correct after every iteration. For both FRE and FRSQRTE, the minimum
7593 // architected relative accuracy is 2^-5. When hasRecipPrec(), this is
7594 // 2^-14. IEEE float has 23 digits and double has 52 digits.
7595 RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3;
7596 if (VT.getScalarType() == MVT::f64)
7598 return DCI.DAG.getNode(PPCISD::FRE, SDLoc(Operand), VT, Operand);
7603 bool PPCTargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
7604 // Note: This functionality is used only when unsafe-fp-math is enabled, and
7605 // on cores with reciprocal estimates (which are used when unsafe-fp-math is
7606 // enabled for division), this functionality is redundant with the default
7607 // combiner logic (once the division -> reciprocal/multiply transformation
7608 // has taken place). As a result, this matters more for older cores than for
7611 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
7612 // reciprocal if there are two or more FDIVs (for embedded cores with only
7613 // one FP pipeline) for three or more FDIVs (for generic OOO cores).
7614 switch (Subtarget.getDarwinDirective()) {
7616 return NumUsers > 2;
7619 case PPC::DIR_E500mc:
7620 case PPC::DIR_E5500:
7621 return NumUsers > 1;
7625 static bool isConsecutiveLSLoc(SDValue Loc, EVT VT, LSBaseSDNode *Base,
7626 unsigned Bytes, int Dist,
7627 SelectionDAG &DAG) {
7628 if (VT.getSizeInBits() / 8 != Bytes)
7631 SDValue BaseLoc = Base->getBasePtr();
7632 if (Loc.getOpcode() == ISD::FrameIndex) {
7633 if (BaseLoc.getOpcode() != ISD::FrameIndex)
7635 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7636 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
7637 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
7638 int FS = MFI->getObjectSize(FI);
7639 int BFS = MFI->getObjectSize(BFI);
7640 if (FS != BFS || FS != (int)Bytes) return false;
7641 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
7645 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
7646 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
7649 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7650 const GlobalValue *GV1 = nullptr;
7651 const GlobalValue *GV2 = nullptr;
7652 int64_t Offset1 = 0;
7653 int64_t Offset2 = 0;
7654 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
7655 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
7656 if (isGA1 && isGA2 && GV1 == GV2)
7657 return Offset1 == (Offset2 + Dist*Bytes);
7661 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
7662 // not enforce equality of the chain operands.
7663 static bool isConsecutiveLS(SDNode *N, LSBaseSDNode *Base,
7664 unsigned Bytes, int Dist,
7665 SelectionDAG &DAG) {
7666 if (LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(N)) {
7667 EVT VT = LS->getMemoryVT();
7668 SDValue Loc = LS->getBasePtr();
7669 return isConsecutiveLSLoc(Loc, VT, Base, Bytes, Dist, DAG);
7672 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
7674 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
7675 default: return false;
7676 case Intrinsic::ppc_altivec_lvx:
7677 case Intrinsic::ppc_altivec_lvxl:
7678 case Intrinsic::ppc_vsx_lxvw4x:
7681 case Intrinsic::ppc_vsx_lxvd2x:
7684 case Intrinsic::ppc_altivec_lvebx:
7687 case Intrinsic::ppc_altivec_lvehx:
7690 case Intrinsic::ppc_altivec_lvewx:
7695 return isConsecutiveLSLoc(N->getOperand(2), VT, Base, Bytes, Dist, DAG);
7698 if (N->getOpcode() == ISD::INTRINSIC_VOID) {
7700 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
7701 default: return false;
7702 case Intrinsic::ppc_altivec_stvx:
7703 case Intrinsic::ppc_altivec_stvxl:
7704 case Intrinsic::ppc_vsx_stxvw4x:
7707 case Intrinsic::ppc_vsx_stxvd2x:
7710 case Intrinsic::ppc_altivec_stvebx:
7713 case Intrinsic::ppc_altivec_stvehx:
7716 case Intrinsic::ppc_altivec_stvewx:
7721 return isConsecutiveLSLoc(N->getOperand(3), VT, Base, Bytes, Dist, DAG);
7727 // Return true is there is a nearyby consecutive load to the one provided
7728 // (regardless of alignment). We search up and down the chain, looking though
7729 // token factors and other loads (but nothing else). As a result, a true result
7730 // indicates that it is safe to create a new consecutive load adjacent to the
7732 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
7733 SDValue Chain = LD->getChain();
7734 EVT VT = LD->getMemoryVT();
7736 SmallSet<SDNode *, 16> LoadRoots;
7737 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
7738 SmallSet<SDNode *, 16> Visited;
7740 // First, search up the chain, branching to follow all token-factor operands.
7741 // If we find a consecutive load, then we're done, otherwise, record all
7742 // nodes just above the top-level loads and token factors.
7743 while (!Queue.empty()) {
7744 SDNode *ChainNext = Queue.pop_back_val();
7745 if (!Visited.insert(ChainNext).second)
7748 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(ChainNext)) {
7749 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7752 if (!Visited.count(ChainLD->getChain().getNode()))
7753 Queue.push_back(ChainLD->getChain().getNode());
7754 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
7755 for (const SDUse &O : ChainNext->ops())
7756 if (!Visited.count(O.getNode()))
7757 Queue.push_back(O.getNode());
7759 LoadRoots.insert(ChainNext);
7762 // Second, search down the chain, starting from the top-level nodes recorded
7763 // in the first phase. These top-level nodes are the nodes just above all
7764 // loads and token factors. Starting with their uses, recursively look though
7765 // all loads (just the chain uses) and token factors to find a consecutive
7770 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
7771 IE = LoadRoots.end(); I != IE; ++I) {
7772 Queue.push_back(*I);
7774 while (!Queue.empty()) {
7775 SDNode *LoadRoot = Queue.pop_back_val();
7776 if (!Visited.insert(LoadRoot).second)
7779 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(LoadRoot))
7780 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7783 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
7784 UE = LoadRoot->use_end(); UI != UE; ++UI)
7785 if (((isa<MemSDNode>(*UI) &&
7786 cast<MemSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
7787 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
7788 Queue.push_back(*UI);
7795 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
7796 DAGCombinerInfo &DCI) const {
7797 SelectionDAG &DAG = DCI.DAG;
7800 assert(Subtarget.useCRBits() &&
7801 "Expecting to be tracking CR bits");
7802 // If we're tracking CR bits, we need to be careful that we don't have:
7803 // trunc(binary-ops(zext(x), zext(y)))
7805 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
7806 // such that we're unnecessarily moving things into GPRs when it would be
7807 // better to keep them in CR bits.
7809 // Note that trunc here can be an actual i1 trunc, or can be the effective
7810 // truncation that comes from a setcc or select_cc.
7811 if (N->getOpcode() == ISD::TRUNCATE &&
7812 N->getValueType(0) != MVT::i1)
7815 if (N->getOperand(0).getValueType() != MVT::i32 &&
7816 N->getOperand(0).getValueType() != MVT::i64)
7819 if (N->getOpcode() == ISD::SETCC ||
7820 N->getOpcode() == ISD::SELECT_CC) {
7821 // If we're looking at a comparison, then we need to make sure that the
7822 // high bits (all except for the first) don't matter the result.
7824 cast<CondCodeSDNode>(N->getOperand(
7825 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
7826 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
7828 if (ISD::isSignedIntSetCC(CC)) {
7829 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
7830 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
7832 } else if (ISD::isUnsignedIntSetCC(CC)) {
7833 if (!DAG.MaskedValueIsZero(N->getOperand(0),
7834 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
7835 !DAG.MaskedValueIsZero(N->getOperand(1),
7836 APInt::getHighBitsSet(OpBits, OpBits-1)))
7839 // This is neither a signed nor an unsigned comparison, just make sure
7840 // that the high bits are equal.
7841 APInt Op1Zero, Op1One;
7842 APInt Op2Zero, Op2One;
7843 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
7844 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
7846 // We don't really care about what is known about the first bit (if
7847 // anything), so clear it in all masks prior to comparing them.
7848 Op1Zero.clearBit(0); Op1One.clearBit(0);
7849 Op2Zero.clearBit(0); Op2One.clearBit(0);
7851 if (Op1Zero != Op2Zero || Op1One != Op2One)
7856 // We now know that the higher-order bits are irrelevant, we just need to
7857 // make sure that all of the intermediate operations are bit operations, and
7858 // all inputs are extensions.
7859 if (N->getOperand(0).getOpcode() != ISD::AND &&
7860 N->getOperand(0).getOpcode() != ISD::OR &&
7861 N->getOperand(0).getOpcode() != ISD::XOR &&
7862 N->getOperand(0).getOpcode() != ISD::SELECT &&
7863 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
7864 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
7865 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
7866 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
7867 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
7870 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
7871 N->getOperand(1).getOpcode() != ISD::AND &&
7872 N->getOperand(1).getOpcode() != ISD::OR &&
7873 N->getOperand(1).getOpcode() != ISD::XOR &&
7874 N->getOperand(1).getOpcode() != ISD::SELECT &&
7875 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
7876 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
7877 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
7878 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
7879 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
7882 SmallVector<SDValue, 4> Inputs;
7883 SmallVector<SDValue, 8> BinOps, PromOps;
7884 SmallPtrSet<SDNode *, 16> Visited;
7886 for (unsigned i = 0; i < 2; ++i) {
7887 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7888 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7889 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7890 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7891 isa<ConstantSDNode>(N->getOperand(i)))
7892 Inputs.push_back(N->getOperand(i));
7894 BinOps.push_back(N->getOperand(i));
7896 if (N->getOpcode() == ISD::TRUNCATE)
7900 // Visit all inputs, collect all binary operations (and, or, xor and
7901 // select) that are all fed by extensions.
7902 while (!BinOps.empty()) {
7903 SDValue BinOp = BinOps.back();
7906 if (!Visited.insert(BinOp.getNode()).second)
7909 PromOps.push_back(BinOp);
7911 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
7912 // The condition of the select is not promoted.
7913 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
7915 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
7918 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7919 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7920 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7921 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7922 isa<ConstantSDNode>(BinOp.getOperand(i))) {
7923 Inputs.push_back(BinOp.getOperand(i));
7924 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
7925 BinOp.getOperand(i).getOpcode() == ISD::OR ||
7926 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
7927 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
7928 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
7929 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
7930 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7931 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7932 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
7933 BinOps.push_back(BinOp.getOperand(i));
7935 // We have an input that is not an extension or another binary
7936 // operation; we'll abort this transformation.
7942 // Make sure that this is a self-contained cluster of operations (which
7943 // is not quite the same thing as saying that everything has only one
7945 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7946 if (isa<ConstantSDNode>(Inputs[i]))
7949 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
7950 UE = Inputs[i].getNode()->use_end();
7953 if (User != N && !Visited.count(User))
7956 // Make sure that we're not going to promote the non-output-value
7957 // operand(s) or SELECT or SELECT_CC.
7958 // FIXME: Although we could sometimes handle this, and it does occur in
7959 // practice that one of the condition inputs to the select is also one of
7960 // the outputs, we currently can't deal with this.
7961 if (User->getOpcode() == ISD::SELECT) {
7962 if (User->getOperand(0) == Inputs[i])
7964 } else if (User->getOpcode() == ISD::SELECT_CC) {
7965 if (User->getOperand(0) == Inputs[i] ||
7966 User->getOperand(1) == Inputs[i])
7972 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
7973 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
7974 UE = PromOps[i].getNode()->use_end();
7977 if (User != N && !Visited.count(User))
7980 // Make sure that we're not going to promote the non-output-value
7981 // operand(s) or SELECT or SELECT_CC.
7982 // FIXME: Although we could sometimes handle this, and it does occur in
7983 // practice that one of the condition inputs to the select is also one of
7984 // the outputs, we currently can't deal with this.
7985 if (User->getOpcode() == ISD::SELECT) {
7986 if (User->getOperand(0) == PromOps[i])
7988 } else if (User->getOpcode() == ISD::SELECT_CC) {
7989 if (User->getOperand(0) == PromOps[i] ||
7990 User->getOperand(1) == PromOps[i])
7996 // Replace all inputs with the extension operand.
7997 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7998 // Constants may have users outside the cluster of to-be-promoted nodes,
7999 // and so we need to replace those as we do the promotions.
8000 if (isa<ConstantSDNode>(Inputs[i]))
8003 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
8006 // Replace all operations (these are all the same, but have a different
8007 // (i1) return type). DAG.getNode will validate that the types of
8008 // a binary operator match, so go through the list in reverse so that
8009 // we've likely promoted both operands first. Any intermediate truncations or
8010 // extensions disappear.
8011 while (!PromOps.empty()) {
8012 SDValue PromOp = PromOps.back();
8015 if (PromOp.getOpcode() == ISD::TRUNCATE ||
8016 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
8017 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
8018 PromOp.getOpcode() == ISD::ANY_EXTEND) {
8019 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
8020 PromOp.getOperand(0).getValueType() != MVT::i1) {
8021 // The operand is not yet ready (see comment below).
8022 PromOps.insert(PromOps.begin(), PromOp);
8026 SDValue RepValue = PromOp.getOperand(0);
8027 if (isa<ConstantSDNode>(RepValue))
8028 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
8030 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
8035 switch (PromOp.getOpcode()) {
8036 default: C = 0; break;
8037 case ISD::SELECT: C = 1; break;
8038 case ISD::SELECT_CC: C = 2; break;
8041 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
8042 PromOp.getOperand(C).getValueType() != MVT::i1) ||
8043 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
8044 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
8045 // The to-be-promoted operands of this node have not yet been
8046 // promoted (this should be rare because we're going through the
8047 // list backward, but if one of the operands has several users in
8048 // this cluster of to-be-promoted nodes, it is possible).
8049 PromOps.insert(PromOps.begin(), PromOp);
8053 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
8054 PromOp.getNode()->op_end());
8056 // If there are any constant inputs, make sure they're replaced now.
8057 for (unsigned i = 0; i < 2; ++i)
8058 if (isa<ConstantSDNode>(Ops[C+i]))
8059 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
8061 DAG.ReplaceAllUsesOfValueWith(PromOp,
8062 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
8065 // Now we're left with the initial truncation itself.
8066 if (N->getOpcode() == ISD::TRUNCATE)
8067 return N->getOperand(0);
8069 // Otherwise, this is a comparison. The operands to be compared have just
8070 // changed type (to i1), but everything else is the same.
8071 return SDValue(N, 0);
8074 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
8075 DAGCombinerInfo &DCI) const {
8076 SelectionDAG &DAG = DCI.DAG;
8079 // If we're tracking CR bits, we need to be careful that we don't have:
8080 // zext(binary-ops(trunc(x), trunc(y)))
8082 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
8083 // such that we're unnecessarily moving things into CR bits that can more
8084 // efficiently stay in GPRs. Note that if we're not certain that the high
8085 // bits are set as required by the final extension, we still may need to do
8086 // some masking to get the proper behavior.
8088 // This same functionality is important on PPC64 when dealing with
8089 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
8090 // the return values of functions. Because it is so similar, it is handled
8093 if (N->getValueType(0) != MVT::i32 &&
8094 N->getValueType(0) != MVT::i64)
8097 if (!((N->getOperand(0).getValueType() == MVT::i1 &&
8098 Subtarget.useCRBits()) ||
8099 (N->getOperand(0).getValueType() == MVT::i32 &&
8100 Subtarget.isPPC64())))
8103 if (N->getOperand(0).getOpcode() != ISD::AND &&
8104 N->getOperand(0).getOpcode() != ISD::OR &&
8105 N->getOperand(0).getOpcode() != ISD::XOR &&
8106 N->getOperand(0).getOpcode() != ISD::SELECT &&
8107 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
8110 SmallVector<SDValue, 4> Inputs;
8111 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
8112 SmallPtrSet<SDNode *, 16> Visited;
8114 // Visit all inputs, collect all binary operations (and, or, xor and
8115 // select) that are all fed by truncations.
8116 while (!BinOps.empty()) {
8117 SDValue BinOp = BinOps.back();
8120 if (!Visited.insert(BinOp.getNode()).second)
8123 PromOps.push_back(BinOp);
8125 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
8126 // The condition of the select is not promoted.
8127 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
8129 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
8132 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
8133 isa<ConstantSDNode>(BinOp.getOperand(i))) {
8134 Inputs.push_back(BinOp.getOperand(i));
8135 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
8136 BinOp.getOperand(i).getOpcode() == ISD::OR ||
8137 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
8138 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
8139 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
8140 BinOps.push_back(BinOp.getOperand(i));
8142 // We have an input that is not a truncation or another binary
8143 // operation; we'll abort this transformation.
8149 // The operands of a select that must be truncated when the select is
8150 // promoted because the operand is actually part of the to-be-promoted set.
8151 DenseMap<SDNode *, EVT> SelectTruncOp[2];
8153 // Make sure that this is a self-contained cluster of operations (which
8154 // is not quite the same thing as saying that everything has only one
8156 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8157 if (isa<ConstantSDNode>(Inputs[i]))
8160 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
8161 UE = Inputs[i].getNode()->use_end();
8164 if (User != N && !Visited.count(User))
8167 // If we're going to promote the non-output-value operand(s) or SELECT or
8168 // SELECT_CC, record them for truncation.
8169 if (User->getOpcode() == ISD::SELECT) {
8170 if (User->getOperand(0) == Inputs[i])
8171 SelectTruncOp[0].insert(std::make_pair(User,
8172 User->getOperand(0).getValueType()));
8173 } else if (User->getOpcode() == ISD::SELECT_CC) {
8174 if (User->getOperand(0) == Inputs[i])
8175 SelectTruncOp[0].insert(std::make_pair(User,
8176 User->getOperand(0).getValueType()));
8177 if (User->getOperand(1) == Inputs[i])
8178 SelectTruncOp[1].insert(std::make_pair(User,
8179 User->getOperand(1).getValueType()));
8184 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
8185 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
8186 UE = PromOps[i].getNode()->use_end();
8189 if (User != N && !Visited.count(User))
8192 // If we're going to promote the non-output-value operand(s) or SELECT or
8193 // SELECT_CC, record them for truncation.
8194 if (User->getOpcode() == ISD::SELECT) {
8195 if (User->getOperand(0) == PromOps[i])
8196 SelectTruncOp[0].insert(std::make_pair(User,
8197 User->getOperand(0).getValueType()));
8198 } else if (User->getOpcode() == ISD::SELECT_CC) {
8199 if (User->getOperand(0) == PromOps[i])
8200 SelectTruncOp[0].insert(std::make_pair(User,
8201 User->getOperand(0).getValueType()));
8202 if (User->getOperand(1) == PromOps[i])
8203 SelectTruncOp[1].insert(std::make_pair(User,
8204 User->getOperand(1).getValueType()));
8209 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
8210 bool ReallyNeedsExt = false;
8211 if (N->getOpcode() != ISD::ANY_EXTEND) {
8212 // If all of the inputs are not already sign/zero extended, then
8213 // we'll still need to do that at the end.
8214 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8215 if (isa<ConstantSDNode>(Inputs[i]))
8219 Inputs[i].getOperand(0).getValueSizeInBits();
8220 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
8222 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
8223 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
8224 APInt::getHighBitsSet(OpBits,
8225 OpBits-PromBits))) ||
8226 (N->getOpcode() == ISD::SIGN_EXTEND &&
8227 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
8228 (OpBits-(PromBits-1)))) {
8229 ReallyNeedsExt = true;
8235 // Replace all inputs, either with the truncation operand, or a
8236 // truncation or extension to the final output type.
8237 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8238 // Constant inputs need to be replaced with the to-be-promoted nodes that
8239 // use them because they might have users outside of the cluster of
8241 if (isa<ConstantSDNode>(Inputs[i]))
8244 SDValue InSrc = Inputs[i].getOperand(0);
8245 if (Inputs[i].getValueType() == N->getValueType(0))
8246 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
8247 else if (N->getOpcode() == ISD::SIGN_EXTEND)
8248 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8249 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
8250 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8251 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8252 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
8254 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8255 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
8258 // Replace all operations (these are all the same, but have a different
8259 // (promoted) return type). DAG.getNode will validate that the types of
8260 // a binary operator match, so go through the list in reverse so that
8261 // we've likely promoted both operands first.
8262 while (!PromOps.empty()) {
8263 SDValue PromOp = PromOps.back();
8267 switch (PromOp.getOpcode()) {
8268 default: C = 0; break;
8269 case ISD::SELECT: C = 1; break;
8270 case ISD::SELECT_CC: C = 2; break;
8273 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
8274 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
8275 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
8276 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
8277 // The to-be-promoted operands of this node have not yet been
8278 // promoted (this should be rare because we're going through the
8279 // list backward, but if one of the operands has several users in
8280 // this cluster of to-be-promoted nodes, it is possible).
8281 PromOps.insert(PromOps.begin(), PromOp);
8285 // For SELECT and SELECT_CC nodes, we do a similar check for any
8286 // to-be-promoted comparison inputs.
8287 if (PromOp.getOpcode() == ISD::SELECT ||
8288 PromOp.getOpcode() == ISD::SELECT_CC) {
8289 if ((SelectTruncOp[0].count(PromOp.getNode()) &&
8290 PromOp.getOperand(0).getValueType() != N->getValueType(0)) ||
8291 (SelectTruncOp[1].count(PromOp.getNode()) &&
8292 PromOp.getOperand(1).getValueType() != N->getValueType(0))) {
8293 PromOps.insert(PromOps.begin(), PromOp);
8298 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
8299 PromOp.getNode()->op_end());
8301 // If this node has constant inputs, then they'll need to be promoted here.
8302 for (unsigned i = 0; i < 2; ++i) {
8303 if (!isa<ConstantSDNode>(Ops[C+i]))
8305 if (Ops[C+i].getValueType() == N->getValueType(0))
8308 if (N->getOpcode() == ISD::SIGN_EXTEND)
8309 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8310 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8311 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8313 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8316 // If we've promoted the comparison inputs of a SELECT or SELECT_CC,
8317 // truncate them again to the original value type.
8318 if (PromOp.getOpcode() == ISD::SELECT ||
8319 PromOp.getOpcode() == ISD::SELECT_CC) {
8320 auto SI0 = SelectTruncOp[0].find(PromOp.getNode());
8321 if (SI0 != SelectTruncOp[0].end())
8322 Ops[0] = DAG.getNode(ISD::TRUNCATE, dl, SI0->second, Ops[0]);
8323 auto SI1 = SelectTruncOp[1].find(PromOp.getNode());
8324 if (SI1 != SelectTruncOp[1].end())
8325 Ops[1] = DAG.getNode(ISD::TRUNCATE, dl, SI1->second, Ops[1]);
8328 DAG.ReplaceAllUsesOfValueWith(PromOp,
8329 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
8332 // Now we're left with the initial extension itself.
8333 if (!ReallyNeedsExt)
8334 return N->getOperand(0);
8336 // To zero extend, just mask off everything except for the first bit (in the
8338 if (N->getOpcode() == ISD::ZERO_EXTEND)
8339 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
8340 DAG.getConstant(APInt::getLowBitsSet(
8341 N->getValueSizeInBits(0), PromBits),
8342 N->getValueType(0)));
8344 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
8345 "Invalid extension type");
8346 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0));
8348 DAG.getConstant(N->getValueSizeInBits(0)-PromBits, ShiftAmountTy);
8349 return DAG.getNode(ISD::SRA, dl, N->getValueType(0),
8350 DAG.getNode(ISD::SHL, dl, N->getValueType(0),
8351 N->getOperand(0), ShiftCst), ShiftCst);
8354 SDValue PPCTargetLowering::combineFPToIntToFP(SDNode *N,
8355 DAGCombinerInfo &DCI) const {
8356 assert((N->getOpcode() == ISD::SINT_TO_FP ||
8357 N->getOpcode() == ISD::UINT_TO_FP) &&
8358 "Need an int -> FP conversion node here");
8360 if (!Subtarget.has64BitSupport())
8363 SelectionDAG &DAG = DCI.DAG;
8367 // Don't handle ppc_fp128 here or i1 conversions.
8368 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
8370 if (Op.getOperand(0).getValueType() == MVT::i1)
8373 // For i32 intermediate values, unfortunately, the conversion functions
8374 // leave the upper 32 bits of the value are undefined. Within the set of
8375 // scalar instructions, we have no method for zero- or sign-extending the
8376 // value. Thus, we cannot handle i32 intermediate values here.
8377 if (Op.getOperand(0).getValueType() == MVT::i32)
8380 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
8381 "UINT_TO_FP is supported only with FPCVT");
8383 // If we have FCFIDS, then use it when converting to single-precision.
8384 // Otherwise, convert to double-precision and then round.
8385 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
8386 (Op.getOpcode() == ISD::UINT_TO_FP ?
8387 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
8388 (Op.getOpcode() == ISD::UINT_TO_FP ?
8389 PPCISD::FCFIDU : PPCISD::FCFID);
8390 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
8391 MVT::f32 : MVT::f64;
8393 // If we're converting from a float, to an int, and back to a float again,
8394 // then we don't need the store/load pair at all.
8395 if ((Op.getOperand(0).getOpcode() == ISD::FP_TO_UINT &&
8396 Subtarget.hasFPCVT()) ||
8397 (Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT)) {
8398 SDValue Src = Op.getOperand(0).getOperand(0);
8399 if (Src.getValueType() == MVT::f32) {
8400 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
8401 DCI.AddToWorklist(Src.getNode());
8405 Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
8408 SDValue Tmp = DAG.getNode(FCTOp, dl, MVT::f64, Src);
8409 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Tmp);
8411 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) {
8412 FP = DAG.getNode(ISD::FP_ROUND, dl,
8413 MVT::f32, FP, DAG.getIntPtrConstant(0));
8414 DCI.AddToWorklist(FP.getNode());
8423 // expandVSXLoadForLE - Convert VSX loads (which may be intrinsics for
8424 // builtins) into loads with swaps.
8425 SDValue PPCTargetLowering::expandVSXLoadForLE(SDNode *N,
8426 DAGCombinerInfo &DCI) const {
8427 SelectionDAG &DAG = DCI.DAG;
8431 MachineMemOperand *MMO;
8433 switch (N->getOpcode()) {
8435 llvm_unreachable("Unexpected opcode for little endian VSX load");
8437 LoadSDNode *LD = cast<LoadSDNode>(N);
8438 Chain = LD->getChain();
8439 Base = LD->getBasePtr();
8440 MMO = LD->getMemOperand();
8441 // If the MMO suggests this isn't a load of a full vector, leave
8442 // things alone. For a built-in, we have to make the change for
8443 // correctness, so if there is a size problem that will be a bug.
8444 if (MMO->getSize() < 16)
8448 case ISD::INTRINSIC_W_CHAIN: {
8449 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
8450 Chain = Intrin->getChain();
8451 Base = Intrin->getBasePtr();
8452 MMO = Intrin->getMemOperand();
8457 MVT VecTy = N->getValueType(0).getSimpleVT();
8458 SDValue LoadOps[] = { Chain, Base };
8459 SDValue Load = DAG.getMemIntrinsicNode(PPCISD::LXVD2X, dl,
8460 DAG.getVTList(VecTy, MVT::Other),
8461 LoadOps, VecTy, MMO);
8462 DCI.AddToWorklist(Load.getNode());
8463 Chain = Load.getValue(1);
8464 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
8465 DAG.getVTList(VecTy, MVT::Other), Chain, Load);
8466 DCI.AddToWorklist(Swap.getNode());
8470 // expandVSXStoreForLE - Convert VSX stores (which may be intrinsics for
8471 // builtins) into stores with swaps.
8472 SDValue PPCTargetLowering::expandVSXStoreForLE(SDNode *N,
8473 DAGCombinerInfo &DCI) const {
8474 SelectionDAG &DAG = DCI.DAG;
8479 MachineMemOperand *MMO;
8481 switch (N->getOpcode()) {
8483 llvm_unreachable("Unexpected opcode for little endian VSX store");
8485 StoreSDNode *ST = cast<StoreSDNode>(N);
8486 Chain = ST->getChain();
8487 Base = ST->getBasePtr();
8488 MMO = ST->getMemOperand();
8490 // If the MMO suggests this isn't a store of a full vector, leave
8491 // things alone. For a built-in, we have to make the change for
8492 // correctness, so if there is a size problem that will be a bug.
8493 if (MMO->getSize() < 16)
8497 case ISD::INTRINSIC_VOID: {
8498 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
8499 Chain = Intrin->getChain();
8500 // Intrin->getBasePtr() oddly does not get what we want.
8501 Base = Intrin->getOperand(3);
8502 MMO = Intrin->getMemOperand();
8508 SDValue Src = N->getOperand(SrcOpnd);
8509 MVT VecTy = Src.getValueType().getSimpleVT();
8510 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
8511 DAG.getVTList(VecTy, MVT::Other), Chain, Src);
8512 DCI.AddToWorklist(Swap.getNode());
8513 Chain = Swap.getValue(1);
8514 SDValue StoreOps[] = { Chain, Swap, Base };
8515 SDValue Store = DAG.getMemIntrinsicNode(PPCISD::STXVD2X, dl,
8516 DAG.getVTList(MVT::Other),
8517 StoreOps, VecTy, MMO);
8518 DCI.AddToWorklist(Store.getNode());
8522 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
8523 DAGCombinerInfo &DCI) const {
8524 const TargetMachine &TM = getTargetMachine();
8525 SelectionDAG &DAG = DCI.DAG;
8527 switch (N->getOpcode()) {
8530 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8531 if (C->isNullValue()) // 0 << V -> 0.
8532 return N->getOperand(0);
8536 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8537 if (C->isNullValue()) // 0 >>u V -> 0.
8538 return N->getOperand(0);
8542 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8543 if (C->isNullValue() || // 0 >>s V -> 0.
8544 C->isAllOnesValue()) // -1 >>s V -> -1.
8545 return N->getOperand(0);
8548 case ISD::SIGN_EXTEND:
8549 case ISD::ZERO_EXTEND:
8550 case ISD::ANY_EXTEND:
8551 return DAGCombineExtBoolTrunc(N, DCI);
8554 case ISD::SELECT_CC:
8555 return DAGCombineTruncBoolExt(N, DCI);
8556 case ISD::SINT_TO_FP:
8557 case ISD::UINT_TO_FP:
8558 return combineFPToIntToFP(N, DCI);
8560 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
8561 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
8562 !cast<StoreSDNode>(N)->isTruncatingStore() &&
8563 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
8564 N->getOperand(1).getValueType() == MVT::i32 &&
8565 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
8566 SDValue Val = N->getOperand(1).getOperand(0);
8567 if (Val.getValueType() == MVT::f32) {
8568 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8569 DCI.AddToWorklist(Val.getNode());
8571 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
8572 DCI.AddToWorklist(Val.getNode());
8575 N->getOperand(0), Val, N->getOperand(2),
8576 DAG.getValueType(N->getOperand(1).getValueType())
8579 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
8580 DAG.getVTList(MVT::Other), Ops,
8581 cast<StoreSDNode>(N)->getMemoryVT(),
8582 cast<StoreSDNode>(N)->getMemOperand());
8583 DCI.AddToWorklist(Val.getNode());
8587 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
8588 if (cast<StoreSDNode>(N)->isUnindexed() &&
8589 N->getOperand(1).getOpcode() == ISD::BSWAP &&
8590 N->getOperand(1).getNode()->hasOneUse() &&
8591 (N->getOperand(1).getValueType() == MVT::i32 ||
8592 N->getOperand(1).getValueType() == MVT::i16 ||
8593 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8594 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8595 N->getOperand(1).getValueType() == MVT::i64))) {
8596 SDValue BSwapOp = N->getOperand(1).getOperand(0);
8597 // Do an any-extend to 32-bits if this is a half-word input.
8598 if (BSwapOp.getValueType() == MVT::i16)
8599 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
8602 N->getOperand(0), BSwapOp, N->getOperand(2),
8603 DAG.getValueType(N->getOperand(1).getValueType())
8606 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
8607 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
8608 cast<StoreSDNode>(N)->getMemOperand());
8611 // For little endian, VSX stores require generating xxswapd/lxvd2x.
8612 EVT VT = N->getOperand(1).getValueType();
8613 if (VT.isSimple()) {
8614 MVT StoreVT = VT.getSimpleVT();
8615 if (TM.getSubtarget<PPCSubtarget>().hasVSX() &&
8616 TM.getSubtarget<PPCSubtarget>().isLittleEndian() &&
8617 (StoreVT == MVT::v2f64 || StoreVT == MVT::v2i64 ||
8618 StoreVT == MVT::v4f32 || StoreVT == MVT::v4i32))
8619 return expandVSXStoreForLE(N, DCI);
8624 LoadSDNode *LD = cast<LoadSDNode>(N);
8625 EVT VT = LD->getValueType(0);
8627 // For little endian, VSX loads require generating lxvd2x/xxswapd.
8628 if (VT.isSimple()) {
8629 MVT LoadVT = VT.getSimpleVT();
8630 if (TM.getSubtarget<PPCSubtarget>().hasVSX() &&
8631 TM.getSubtarget<PPCSubtarget>().isLittleEndian() &&
8632 (LoadVT == MVT::v2f64 || LoadVT == MVT::v2i64 ||
8633 LoadVT == MVT::v4f32 || LoadVT == MVT::v4i32))
8634 return expandVSXLoadForLE(N, DCI);
8637 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
8638 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
8639 if (ISD::isNON_EXTLoad(N) && VT.isVector() &&
8640 TM.getSubtarget<PPCSubtarget>().hasAltivec() &&
8641 // P8 and later hardware should just use LOAD.
8642 !TM.getSubtarget<PPCSubtarget>().hasP8Vector() &&
8643 (VT == MVT::v16i8 || VT == MVT::v8i16 ||
8644 VT == MVT::v4i32 || VT == MVT::v4f32) &&
8645 LD->getAlignment() < ABIAlignment) {
8646 // This is a type-legal unaligned Altivec load.
8647 SDValue Chain = LD->getChain();
8648 SDValue Ptr = LD->getBasePtr();
8649 bool isLittleEndian = Subtarget.isLittleEndian();
8651 // This implements the loading of unaligned vectors as described in
8652 // the venerable Apple Velocity Engine overview. Specifically:
8653 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
8654 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
8656 // The general idea is to expand a sequence of one or more unaligned
8657 // loads into an alignment-based permutation-control instruction (lvsl
8658 // or lvsr), a series of regular vector loads (which always truncate
8659 // their input address to an aligned address), and a series of
8660 // permutations. The results of these permutations are the requested
8661 // loaded values. The trick is that the last "extra" load is not taken
8662 // from the address you might suspect (sizeof(vector) bytes after the
8663 // last requested load), but rather sizeof(vector) - 1 bytes after the
8664 // last requested vector. The point of this is to avoid a page fault if
8665 // the base address happened to be aligned. This works because if the
8666 // base address is aligned, then adding less than a full vector length
8667 // will cause the last vector in the sequence to be (re)loaded.
8668 // Otherwise, the next vector will be fetched as you might suspect was
8671 // We might be able to reuse the permutation generation from
8672 // a different base address offset from this one by an aligned amount.
8673 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
8674 // optimization later.
8675 Intrinsic::ID Intr = (isLittleEndian ?
8676 Intrinsic::ppc_altivec_lvsr :
8677 Intrinsic::ppc_altivec_lvsl);
8678 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, MVT::v16i8);
8680 // Create the new MMO for the new base load. It is like the original MMO,
8681 // but represents an area in memory almost twice the vector size centered
8682 // on the original address. If the address is unaligned, we might start
8683 // reading up to (sizeof(vector)-1) bytes below the address of the
8684 // original unaligned load.
8685 MachineFunction &MF = DAG.getMachineFunction();
8686 MachineMemOperand *BaseMMO =
8687 MF.getMachineMemOperand(LD->getMemOperand(),
8688 -LD->getMemoryVT().getStoreSize()+1,
8689 2*LD->getMemoryVT().getStoreSize()-1);
8691 // Create the new base load.
8692 SDValue LDXIntID = DAG.getTargetConstant(Intrinsic::ppc_altivec_lvx,
8694 SDValue BaseLoadOps[] = { Chain, LDXIntID, Ptr };
8696 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
8697 DAG.getVTList(MVT::v4i32, MVT::Other),
8698 BaseLoadOps, MVT::v4i32, BaseMMO);
8700 // Note that the value of IncOffset (which is provided to the next
8701 // load's pointer info offset value, and thus used to calculate the
8702 // alignment), and the value of IncValue (which is actually used to
8703 // increment the pointer value) are different! This is because we
8704 // require the next load to appear to be aligned, even though it
8705 // is actually offset from the base pointer by a lesser amount.
8706 int IncOffset = VT.getSizeInBits() / 8;
8707 int IncValue = IncOffset;
8709 // Walk (both up and down) the chain looking for another load at the real
8710 // (aligned) offset (the alignment of the other load does not matter in
8711 // this case). If found, then do not use the offset reduction trick, as
8712 // that will prevent the loads from being later combined (as they would
8713 // otherwise be duplicates).
8714 if (!findConsecutiveLoad(LD, DAG))
8717 SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
8718 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
8720 MachineMemOperand *ExtraMMO =
8721 MF.getMachineMemOperand(LD->getMemOperand(),
8722 1, 2*LD->getMemoryVT().getStoreSize()-1);
8723 SDValue ExtraLoadOps[] = { Chain, LDXIntID, Ptr };
8725 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
8726 DAG.getVTList(MVT::v4i32, MVT::Other),
8727 ExtraLoadOps, MVT::v4i32, ExtraMMO);
8729 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
8730 BaseLoad.getValue(1), ExtraLoad.getValue(1));
8732 // Because vperm has a big-endian bias, we must reverse the order
8733 // of the input vectors and complement the permute control vector
8734 // when generating little endian code. We have already handled the
8735 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
8736 // and ExtraLoad here.
8739 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8740 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
8742 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8743 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
8745 if (VT != MVT::v4i32)
8746 Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm);
8748 // The output of the permutation is our loaded result, the TokenFactor is
8750 DCI.CombineTo(N, Perm, TF);
8751 return SDValue(N, 0);
8755 case ISD::INTRINSIC_WO_CHAIN: {
8756 bool isLittleEndian = Subtarget.isLittleEndian();
8757 Intrinsic::ID Intr = (isLittleEndian ?
8758 Intrinsic::ppc_altivec_lvsr :
8759 Intrinsic::ppc_altivec_lvsl);
8760 if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() == Intr &&
8761 N->getOperand(1)->getOpcode() == ISD::ADD) {
8762 SDValue Add = N->getOperand(1);
8764 if (DAG.MaskedValueIsZero(Add->getOperand(1),
8765 APInt::getAllOnesValue(4 /* 16 byte alignment */).zext(
8766 Add.getValueType().getScalarType().getSizeInBits()))) {
8767 SDNode *BasePtr = Add->getOperand(0).getNode();
8768 for (SDNode::use_iterator UI = BasePtr->use_begin(),
8769 UE = BasePtr->use_end(); UI != UE; ++UI) {
8770 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8771 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() ==
8773 // We've found another LVSL/LVSR, and this address is an aligned
8774 // multiple of that one. The results will be the same, so use the
8775 // one we've just found instead.
8777 return SDValue(*UI, 0);
8785 case ISD::INTRINSIC_W_CHAIN: {
8786 // For little endian, VSX loads require generating lxvd2x/xxswapd.
8787 if (TM.getSubtarget<PPCSubtarget>().hasVSX() &&
8788 TM.getSubtarget<PPCSubtarget>().isLittleEndian()) {
8789 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
8792 case Intrinsic::ppc_vsx_lxvw4x:
8793 case Intrinsic::ppc_vsx_lxvd2x:
8794 return expandVSXLoadForLE(N, DCI);
8799 case ISD::INTRINSIC_VOID: {
8800 // For little endian, VSX stores require generating xxswapd/stxvd2x.
8801 if (TM.getSubtarget<PPCSubtarget>().hasVSX() &&
8802 TM.getSubtarget<PPCSubtarget>().isLittleEndian()) {
8803 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
8806 case Intrinsic::ppc_vsx_stxvw4x:
8807 case Intrinsic::ppc_vsx_stxvd2x:
8808 return expandVSXStoreForLE(N, DCI);
8814 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
8815 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
8816 N->getOperand(0).hasOneUse() &&
8817 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
8818 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8819 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8820 N->getValueType(0) == MVT::i64))) {
8821 SDValue Load = N->getOperand(0);
8822 LoadSDNode *LD = cast<LoadSDNode>(Load);
8823 // Create the byte-swapping load.
8825 LD->getChain(), // Chain
8826 LD->getBasePtr(), // Ptr
8827 DAG.getValueType(N->getValueType(0)) // VT
8830 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
8831 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
8832 MVT::i64 : MVT::i32, MVT::Other),
8833 Ops, LD->getMemoryVT(), LD->getMemOperand());
8835 // If this is an i16 load, insert the truncate.
8836 SDValue ResVal = BSLoad;
8837 if (N->getValueType(0) == MVT::i16)
8838 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
8840 // First, combine the bswap away. This makes the value produced by the
8842 DCI.CombineTo(N, ResVal);
8844 // Next, combine the load away, we give it a bogus result value but a real
8845 // chain result. The result value is dead because the bswap is dead.
8846 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
8848 // Return N so it doesn't get rechecked!
8849 return SDValue(N, 0);
8853 case PPCISD::VCMP: {
8854 // If a VCMPo node already exists with exactly the same operands as this
8855 // node, use its result instead of this node (VCMPo computes both a CR6 and
8856 // a normal output).
8858 if (!N->getOperand(0).hasOneUse() &&
8859 !N->getOperand(1).hasOneUse() &&
8860 !N->getOperand(2).hasOneUse()) {
8862 // Scan all of the users of the LHS, looking for VCMPo's that match.
8863 SDNode *VCMPoNode = nullptr;
8865 SDNode *LHSN = N->getOperand(0).getNode();
8866 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
8868 if (UI->getOpcode() == PPCISD::VCMPo &&
8869 UI->getOperand(1) == N->getOperand(1) &&
8870 UI->getOperand(2) == N->getOperand(2) &&
8871 UI->getOperand(0) == N->getOperand(0)) {
8876 // If there is no VCMPo node, or if the flag value has a single use, don't
8878 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
8881 // Look at the (necessarily single) use of the flag value. If it has a
8882 // chain, this transformation is more complex. Note that multiple things
8883 // could use the value result, which we should ignore.
8884 SDNode *FlagUser = nullptr;
8885 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
8886 FlagUser == nullptr; ++UI) {
8887 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
8889 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
8890 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
8897 // If the user is a MFOCRF instruction, we know this is safe.
8898 // Otherwise we give up for right now.
8899 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
8900 return SDValue(VCMPoNode, 0);
8905 SDValue Cond = N->getOperand(1);
8906 SDValue Target = N->getOperand(2);
8908 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8909 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
8910 Intrinsic::ppc_is_decremented_ctr_nonzero) {
8912 // We now need to make the intrinsic dead (it cannot be instruction
8914 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
8915 assert(Cond.getNode()->hasOneUse() &&
8916 "Counter decrement has more than one use");
8918 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
8919 N->getOperand(0), Target);
8924 // If this is a branch on an altivec predicate comparison, lower this so
8925 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
8926 // lowering is done pre-legalize, because the legalizer lowers the predicate
8927 // compare down to code that is difficult to reassemble.
8928 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
8929 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
8931 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
8932 // value. If so, pass-through the AND to get to the intrinsic.
8933 if (LHS.getOpcode() == ISD::AND &&
8934 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8935 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
8936 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8937 isa<ConstantSDNode>(LHS.getOperand(1)) &&
8938 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
8940 LHS = LHS.getOperand(0);
8942 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8943 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
8944 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8945 isa<ConstantSDNode>(RHS)) {
8946 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
8947 "Counter decrement comparison is not EQ or NE");
8949 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8950 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
8951 (CC == ISD::SETNE && !Val);
8953 // We now need to make the intrinsic dead (it cannot be instruction
8955 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
8956 assert(LHS.getNode()->hasOneUse() &&
8957 "Counter decrement has more than one use");
8959 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
8960 N->getOperand(0), N->getOperand(4));
8966 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8967 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
8968 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
8969 assert(isDot && "Can't compare against a vector result!");
8971 // If this is a comparison against something other than 0/1, then we know
8972 // that the condition is never/always true.
8973 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8974 if (Val != 0 && Val != 1) {
8975 if (CC == ISD::SETEQ) // Cond never true, remove branch.
8976 return N->getOperand(0);
8977 // Always !=, turn it into an unconditional branch.
8978 return DAG.getNode(ISD::BR, dl, MVT::Other,
8979 N->getOperand(0), N->getOperand(4));
8982 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
8984 // Create the PPCISD altivec 'dot' comparison node.
8986 LHS.getOperand(2), // LHS of compare
8987 LHS.getOperand(3), // RHS of compare
8988 DAG.getConstant(CompareOpc, MVT::i32)
8990 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
8991 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
8993 // Unpack the result based on how the target uses it.
8994 PPC::Predicate CompOpc;
8995 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
8996 default: // Can't happen, don't crash on invalid number though.
8997 case 0: // Branch on the value of the EQ bit of CR6.
8998 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
9000 case 1: // Branch on the inverted value of the EQ bit of CR6.
9001 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
9003 case 2: // Branch on the value of the LT bit of CR6.
9004 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
9006 case 3: // Branch on the inverted value of the LT bit of CR6.
9007 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
9011 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
9012 DAG.getConstant(CompOpc, MVT::i32),
9013 DAG.getRegister(PPC::CR6, MVT::i32),
9014 N->getOperand(4), CompNode.getValue(1));
9024 PPCTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
9026 std::vector<SDNode *> *Created) const {
9027 // fold (sdiv X, pow2)
9028 EVT VT = N->getValueType(0);
9029 if (VT == MVT::i64 && !Subtarget.isPPC64())
9031 if ((VT != MVT::i32 && VT != MVT::i64) ||
9032 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
9036 SDValue N0 = N->getOperand(0);
9038 bool IsNegPow2 = (-Divisor).isPowerOf2();
9039 unsigned Lg2 = (IsNegPow2 ? -Divisor : Divisor).countTrailingZeros();
9040 SDValue ShiftAmt = DAG.getConstant(Lg2, VT);
9042 SDValue Op = DAG.getNode(PPCISD::SRA_ADDZE, DL, VT, N0, ShiftAmt);
9044 Created->push_back(Op.getNode());
9047 Op = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT), Op);
9049 Created->push_back(Op.getNode());
9055 //===----------------------------------------------------------------------===//
9056 // Inline Assembly Support
9057 //===----------------------------------------------------------------------===//
9059 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
9062 const SelectionDAG &DAG,
9063 unsigned Depth) const {
9064 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
9065 switch (Op.getOpcode()) {
9067 case PPCISD::LBRX: {
9068 // lhbrx is known to have the top bits cleared out.
9069 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
9070 KnownZero = 0xFFFF0000;
9073 case ISD::INTRINSIC_WO_CHAIN: {
9074 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
9076 case Intrinsic::ppc_altivec_vcmpbfp_p:
9077 case Intrinsic::ppc_altivec_vcmpeqfp_p:
9078 case Intrinsic::ppc_altivec_vcmpequb_p:
9079 case Intrinsic::ppc_altivec_vcmpequh_p:
9080 case Intrinsic::ppc_altivec_vcmpequw_p:
9081 case Intrinsic::ppc_altivec_vcmpgefp_p:
9082 case Intrinsic::ppc_altivec_vcmpgtfp_p:
9083 case Intrinsic::ppc_altivec_vcmpgtsb_p:
9084 case Intrinsic::ppc_altivec_vcmpgtsh_p:
9085 case Intrinsic::ppc_altivec_vcmpgtsw_p:
9086 case Intrinsic::ppc_altivec_vcmpgtub_p:
9087 case Intrinsic::ppc_altivec_vcmpgtuh_p:
9088 case Intrinsic::ppc_altivec_vcmpgtuw_p:
9089 KnownZero = ~1U; // All bits but the low one are known to be zero.
9096 unsigned PPCTargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
9097 switch (Subtarget.getDarwinDirective()) {
9102 case PPC::DIR_PWR5X:
9104 case PPC::DIR_PWR6X:
9106 case PPC::DIR_PWR8: {
9110 const PPCInstrInfo *TII =
9111 static_cast<const PPCInstrInfo *>(getTargetMachine().getSubtargetImpl()->
9114 // For small loops (between 5 and 8 instructions), align to a 32-byte
9115 // boundary so that the entire loop fits in one instruction-cache line.
9116 uint64_t LoopSize = 0;
9117 for (auto I = ML->block_begin(), IE = ML->block_end(); I != IE; ++I)
9118 for (auto J = (*I)->begin(), JE = (*I)->end(); J != JE; ++J)
9119 LoopSize += TII->GetInstSizeInBytes(J);
9121 if (LoopSize > 16 && LoopSize <= 32)
9128 return TargetLowering::getPrefLoopAlignment(ML);
9131 /// getConstraintType - Given a constraint, return the type of
9132 /// constraint it is for this target.
9133 PPCTargetLowering::ConstraintType
9134 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
9135 if (Constraint.size() == 1) {
9136 switch (Constraint[0]) {
9143 return C_RegisterClass;
9145 // FIXME: While Z does indicate a memory constraint, it specifically
9146 // indicates an r+r address (used in conjunction with the 'y' modifier
9147 // in the replacement string). Currently, we're forcing the base
9148 // register to be r0 in the asm printer (which is interpreted as zero)
9149 // and forming the complete address in the second register. This is
9153 } else if (Constraint == "wc") { // individual CR bits.
9154 return C_RegisterClass;
9155 } else if (Constraint == "wa" || Constraint == "wd" ||
9156 Constraint == "wf" || Constraint == "ws") {
9157 return C_RegisterClass; // VSX registers.
9159 return TargetLowering::getConstraintType(Constraint);
9162 /// Examine constraint type and operand type and determine a weight value.
9163 /// This object must already have been set up with the operand type
9164 /// and the current alternative constraint selected.
9165 TargetLowering::ConstraintWeight
9166 PPCTargetLowering::getSingleConstraintMatchWeight(
9167 AsmOperandInfo &info, const char *constraint) const {
9168 ConstraintWeight weight = CW_Invalid;
9169 Value *CallOperandVal = info.CallOperandVal;
9170 // If we don't have a value, we can't do a match,
9171 // but allow it at the lowest weight.
9172 if (!CallOperandVal)
9174 Type *type = CallOperandVal->getType();
9176 // Look at the constraint type.
9177 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
9178 return CW_Register; // an individual CR bit.
9179 else if ((StringRef(constraint) == "wa" ||
9180 StringRef(constraint) == "wd" ||
9181 StringRef(constraint) == "wf") &&
9184 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
9187 switch (*constraint) {
9189 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
9192 if (type->isIntegerTy())
9193 weight = CW_Register;
9196 if (type->isFloatTy())
9197 weight = CW_Register;
9200 if (type->isDoubleTy())
9201 weight = CW_Register;
9204 if (type->isVectorTy())
9205 weight = CW_Register;
9208 weight = CW_Register;
9217 std::pair<unsigned, const TargetRegisterClass*>
9218 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
9220 if (Constraint.size() == 1) {
9221 // GCC RS6000 Constraint Letters
9222 switch (Constraint[0]) {
9224 if (VT == MVT::i64 && Subtarget.isPPC64())
9225 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
9226 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
9228 if (VT == MVT::i64 && Subtarget.isPPC64())
9229 return std::make_pair(0U, &PPC::G8RCRegClass);
9230 return std::make_pair(0U, &PPC::GPRCRegClass);
9232 if (VT == MVT::f32 || VT == MVT::i32)
9233 return std::make_pair(0U, &PPC::F4RCRegClass);
9234 if (VT == MVT::f64 || VT == MVT::i64)
9235 return std::make_pair(0U, &PPC::F8RCRegClass);
9238 return std::make_pair(0U, &PPC::VRRCRegClass);
9240 return std::make_pair(0U, &PPC::CRRCRegClass);
9242 } else if (Constraint == "wc") { // an individual CR bit.
9243 return std::make_pair(0U, &PPC::CRBITRCRegClass);
9244 } else if (Constraint == "wa" || Constraint == "wd" ||
9245 Constraint == "wf") {
9246 return std::make_pair(0U, &PPC::VSRCRegClass);
9247 } else if (Constraint == "ws") {
9248 return std::make_pair(0U, &PPC::VSFRCRegClass);
9251 std::pair<unsigned, const TargetRegisterClass*> R =
9252 TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
9254 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
9255 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
9256 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
9258 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
9259 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
9260 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
9261 PPC::GPRCRegClass.contains(R.first)) {
9262 const TargetRegisterInfo *TRI =
9263 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
9264 return std::make_pair(TRI->getMatchingSuperReg(R.first,
9265 PPC::sub_32, &PPC::G8RCRegClass),
9266 &PPC::G8RCRegClass);
9269 // GCC accepts 'cc' as an alias for 'cr0', and we need to do the same.
9270 if (!R.second && StringRef("{cc}").equals_lower(Constraint)) {
9272 R.second = &PPC::CRRCRegClass;
9279 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
9280 /// vector. If it is invalid, don't add anything to Ops.
9281 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
9282 std::string &Constraint,
9283 std::vector<SDValue>&Ops,
9284 SelectionDAG &DAG) const {
9287 // Only support length 1 constraints.
9288 if (Constraint.length() > 1) return;
9290 char Letter = Constraint[0];
9301 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
9302 if (!CST) return; // Must be an immediate to match.
9303 int64_t Value = CST->getSExtValue();
9304 EVT TCVT = MVT::i64; // All constants taken to be 64 bits so that negative
9305 // numbers are printed as such.
9307 default: llvm_unreachable("Unknown constraint letter!");
9308 case 'I': // "I" is a signed 16-bit constant.
9309 if (isInt<16>(Value))
9310 Result = DAG.getTargetConstant(Value, TCVT);
9312 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
9313 if (isShiftedUInt<16, 16>(Value))
9314 Result = DAG.getTargetConstant(Value, TCVT);
9316 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
9317 if (isShiftedInt<16, 16>(Value))
9318 Result = DAG.getTargetConstant(Value, TCVT);
9320 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
9321 if (isUInt<16>(Value))
9322 Result = DAG.getTargetConstant(Value, TCVT);
9324 case 'M': // "M" is a constant that is greater than 31.
9326 Result = DAG.getTargetConstant(Value, TCVT);
9328 case 'N': // "N" is a positive constant that is an exact power of two.
9329 if (Value > 0 && isPowerOf2_64(Value))
9330 Result = DAG.getTargetConstant(Value, TCVT);
9332 case 'O': // "O" is the constant zero.
9334 Result = DAG.getTargetConstant(Value, TCVT);
9336 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
9337 if (isInt<16>(-Value))
9338 Result = DAG.getTargetConstant(Value, TCVT);
9345 if (Result.getNode()) {
9346 Ops.push_back(Result);
9350 // Handle standard constraint letters.
9351 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
9354 // isLegalAddressingMode - Return true if the addressing mode represented
9355 // by AM is legal for this target, for a load/store of the specified type.
9356 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
9358 // FIXME: PPC does not allow r+i addressing modes for vectors!
9360 // PPC allows a sign-extended 16-bit immediate field.
9361 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
9364 // No global is ever allowed as a base.
9368 // PPC only support r+r,
9370 case 0: // "r+i" or just "i", depending on HasBaseReg.
9373 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
9375 // Otherwise we have r+r or r+i.
9378 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
9380 // Allow 2*r as r+r.
9383 // No other scales are supported.
9390 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
9391 SelectionDAG &DAG) const {
9392 MachineFunction &MF = DAG.getMachineFunction();
9393 MachineFrameInfo *MFI = MF.getFrameInfo();
9394 MFI->setReturnAddressIsTaken(true);
9396 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
9400 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9402 // Make sure the function does not optimize away the store of the RA to
9404 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
9405 FuncInfo->setLRStoreRequired();
9406 bool isPPC64 = Subtarget.isPPC64();
9407 bool isDarwinABI = Subtarget.isDarwinABI();
9410 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9413 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
9414 isPPC64? MVT::i64 : MVT::i32);
9415 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9416 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9418 MachinePointerInfo(), false, false, false, 0);
9421 // Just load the return address off the stack.
9422 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
9423 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9424 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9427 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
9428 SelectionDAG &DAG) const {
9430 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9432 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
9433 bool isPPC64 = PtrVT == MVT::i64;
9435 MachineFunction &MF = DAG.getMachineFunction();
9436 MachineFrameInfo *MFI = MF.getFrameInfo();
9437 MFI->setFrameAddressIsTaken(true);
9439 // Naked functions never have a frame pointer, and so we use r1. For all
9440 // other functions, this decision must be delayed until during PEI.
9442 if (MF.getFunction()->getAttributes().hasAttribute(
9443 AttributeSet::FunctionIndex, Attribute::Naked))
9444 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
9446 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
9448 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
9451 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
9452 FrameAddr, MachinePointerInfo(), false, false,
9457 // FIXME? Maybe this could be a TableGen attribute on some registers and
9458 // this table could be generated automatically from RegInfo.
9459 unsigned PPCTargetLowering::getRegisterByName(const char* RegName,
9461 bool isPPC64 = Subtarget.isPPC64();
9462 bool isDarwinABI = Subtarget.isDarwinABI();
9464 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
9465 (!isPPC64 && VT != MVT::i32))
9466 report_fatal_error("Invalid register global variable type");
9468 bool is64Bit = isPPC64 && VT == MVT::i64;
9469 unsigned Reg = StringSwitch<unsigned>(RegName)
9470 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
9471 .Case("r2", isDarwinABI ? 0 : (is64Bit ? PPC::X2 : PPC::R2))
9472 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
9473 (is64Bit ? PPC::X13 : PPC::R13))
9478 report_fatal_error("Invalid register name global variable");
9482 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
9483 // The PowerPC target isn't yet aware of offsets.
9487 bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
9489 unsigned Intrinsic) const {
9491 switch (Intrinsic) {
9492 case Intrinsic::ppc_altivec_lvx:
9493 case Intrinsic::ppc_altivec_lvxl:
9494 case Intrinsic::ppc_altivec_lvebx:
9495 case Intrinsic::ppc_altivec_lvehx:
9496 case Intrinsic::ppc_altivec_lvewx:
9497 case Intrinsic::ppc_vsx_lxvd2x:
9498 case Intrinsic::ppc_vsx_lxvw4x: {
9500 switch (Intrinsic) {
9501 case Intrinsic::ppc_altivec_lvebx:
9504 case Intrinsic::ppc_altivec_lvehx:
9507 case Intrinsic::ppc_altivec_lvewx:
9510 case Intrinsic::ppc_vsx_lxvd2x:
9518 Info.opc = ISD::INTRINSIC_W_CHAIN;
9520 Info.ptrVal = I.getArgOperand(0);
9521 Info.offset = -VT.getStoreSize()+1;
9522 Info.size = 2*VT.getStoreSize()-1;
9525 Info.readMem = true;
9526 Info.writeMem = false;
9529 case Intrinsic::ppc_altivec_stvx:
9530 case Intrinsic::ppc_altivec_stvxl:
9531 case Intrinsic::ppc_altivec_stvebx:
9532 case Intrinsic::ppc_altivec_stvehx:
9533 case Intrinsic::ppc_altivec_stvewx:
9534 case Intrinsic::ppc_vsx_stxvd2x:
9535 case Intrinsic::ppc_vsx_stxvw4x: {
9537 switch (Intrinsic) {
9538 case Intrinsic::ppc_altivec_stvebx:
9541 case Intrinsic::ppc_altivec_stvehx:
9544 case Intrinsic::ppc_altivec_stvewx:
9547 case Intrinsic::ppc_vsx_stxvd2x:
9555 Info.opc = ISD::INTRINSIC_VOID;
9557 Info.ptrVal = I.getArgOperand(1);
9558 Info.offset = -VT.getStoreSize()+1;
9559 Info.size = 2*VT.getStoreSize()-1;
9562 Info.readMem = false;
9563 Info.writeMem = true;
9573 /// getOptimalMemOpType - Returns the target specific optimal type for load
9574 /// and store operations as a result of memset, memcpy, and memmove
9575 /// lowering. If DstAlign is zero that means it's safe to destination
9576 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
9577 /// means there isn't a need to check it against alignment requirement,
9578 /// probably because the source does not need to be loaded. If 'IsMemset' is
9579 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
9580 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
9581 /// source is constant so it does not need to be loaded.
9582 /// It returns EVT::Other if the type should be determined using generic
9583 /// target-independent logic.
9584 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
9585 unsigned DstAlign, unsigned SrcAlign,
9586 bool IsMemset, bool ZeroMemset,
9588 MachineFunction &MF) const {
9589 if (Subtarget.isPPC64()) {
9596 /// \brief Returns true if it is beneficial to convert a load of a constant
9597 /// to just the constant itself.
9598 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
9600 assert(Ty->isIntegerTy());
9602 unsigned BitSize = Ty->getPrimitiveSizeInBits();
9603 if (BitSize == 0 || BitSize > 64)
9608 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
9609 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
9611 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
9612 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
9613 return NumBits1 == 64 && NumBits2 == 32;
9616 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
9617 if (!VT1.isInteger() || !VT2.isInteger())
9619 unsigned NumBits1 = VT1.getSizeInBits();
9620 unsigned NumBits2 = VT2.getSizeInBits();
9621 return NumBits1 == 64 && NumBits2 == 32;
9624 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
9625 return isInt<16>(Imm) || isUInt<16>(Imm);
9628 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
9629 return isInt<16>(Imm) || isUInt<16>(Imm);
9632 bool PPCTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
9636 if (DisablePPCUnaligned)
9639 // PowerPC supports unaligned memory access for simple non-vector types.
9640 // Although accessing unaligned addresses is not as efficient as accessing
9641 // aligned addresses, it is generally more efficient than manual expansion,
9642 // and generally only traps for software emulation when crossing page
9648 if (VT.getSimpleVT().isVector()) {
9649 if (Subtarget.hasVSX()) {
9650 if (VT != MVT::v2f64 && VT != MVT::v2i64 &&
9651 VT != MVT::v4f32 && VT != MVT::v4i32)
9658 if (VT == MVT::ppcf128)
9667 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
9668 VT = VT.getScalarType();
9673 switch (VT.getSimpleVT().SimpleTy) {
9685 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
9686 EVT VT , unsigned DefinedValues) const {
9687 if (VT == MVT::v2i64)
9690 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
9693 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
9694 if (DisableILPPref || Subtarget.enableMachineScheduler())
9695 return TargetLowering::getSchedulingPreference(N);
9700 // Create a fast isel object.
9702 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
9703 const TargetLibraryInfo *LibInfo) const {
9704 return PPC::createFastISel(FuncInfo, LibInfo);