1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPerfectShuffle.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCTargetObjectFile.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28 #include "llvm/IR/CallingConv.h"
29 #include "llvm/IR/Constants.h"
30 #include "llvm/IR/DerivedTypes.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/Intrinsics.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/Target/TargetOptions.h"
40 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
41 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
43 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
44 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
46 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
47 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
49 static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) {
50 if (TM.getSubtargetImpl()->isDarwin())
51 return new TargetLoweringObjectFileMachO();
53 if (TM.getSubtargetImpl()->isSVR4ABI())
54 return new PPC64LinuxTargetObjectFile();
56 return new TargetLoweringObjectFileELF();
59 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
60 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) {
61 const PPCSubtarget *Subtarget = &TM.getSubtarget<PPCSubtarget>();
65 // Use _setjmp/_longjmp instead of setjmp/longjmp.
66 setUseUnderscoreSetJmp(true);
67 setUseUnderscoreLongJmp(true);
69 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
70 // arguments are at least 4/8 bytes aligned.
71 bool isPPC64 = Subtarget->isPPC64();
72 setMinStackArgumentAlignment(isPPC64 ? 8:4);
74 // Set up the register classes.
75 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
76 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
77 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
79 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
80 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
81 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
83 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
85 // PowerPC has pre-inc load and store's.
86 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
87 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
91 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
92 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
93 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
97 // This is used in the ppcf128->int sequence. Note it has different semantics
98 // from FP_ROUND: that rounds to nearest, this rounds to zero.
99 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
101 // We do not currently implement these libm ops for PowerPC.
102 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
103 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
104 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
105 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
106 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
107 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
109 // PowerPC has no SREM/UREM instructions
110 setOperationAction(ISD::SREM, MVT::i32, Expand);
111 setOperationAction(ISD::UREM, MVT::i32, Expand);
112 setOperationAction(ISD::SREM, MVT::i64, Expand);
113 setOperationAction(ISD::UREM, MVT::i64, Expand);
115 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
116 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
117 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
118 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
119 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
120 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
121 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
122 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
123 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
125 // We don't support sin/cos/sqrt/fmod/pow
126 setOperationAction(ISD::FSIN , MVT::f64, Expand);
127 setOperationAction(ISD::FCOS , MVT::f64, Expand);
128 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
129 setOperationAction(ISD::FREM , MVT::f64, Expand);
130 setOperationAction(ISD::FPOW , MVT::f64, Expand);
131 setOperationAction(ISD::FMA , MVT::f64, Legal);
132 setOperationAction(ISD::FSIN , MVT::f32, Expand);
133 setOperationAction(ISD::FCOS , MVT::f32, Expand);
134 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
135 setOperationAction(ISD::FREM , MVT::f32, Expand);
136 setOperationAction(ISD::FPOW , MVT::f32, Expand);
137 setOperationAction(ISD::FMA , MVT::f32, Legal);
139 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
141 // If we're enabling GP optimizations, use hardware square root
142 if (!Subtarget->hasFSQRT() &&
143 !(TM.Options.UnsafeFPMath &&
144 Subtarget->hasFRSQRTE() && Subtarget->hasFRE()))
145 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
147 if (!Subtarget->hasFSQRT() &&
148 !(TM.Options.UnsafeFPMath &&
149 Subtarget->hasFRSQRTES() && Subtarget->hasFRES()))
150 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
152 if (Subtarget->hasFCPSGN()) {
153 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
154 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
156 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
157 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
160 if (Subtarget->hasFPRND()) {
161 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
162 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
163 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
164 setOperationAction(ISD::FROUND, MVT::f64, Legal);
166 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
167 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
168 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
169 setOperationAction(ISD::FROUND, MVT::f32, Legal);
172 // PowerPC does not have BSWAP, CTPOP or CTTZ
173 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
174 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
175 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
176 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
177 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
178 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
179 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
180 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
182 if (Subtarget->hasPOPCNTD()) {
183 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
184 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
186 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
187 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
190 // PowerPC does not have ROTR
191 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
192 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
194 // PowerPC does not have Select
195 setOperationAction(ISD::SELECT, MVT::i32, Expand);
196 setOperationAction(ISD::SELECT, MVT::i64, Expand);
197 setOperationAction(ISD::SELECT, MVT::f32, Expand);
198 setOperationAction(ISD::SELECT, MVT::f64, Expand);
200 // PowerPC wants to turn select_cc of FP into fsel when possible.
201 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
202 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
204 // PowerPC wants to optimize integer setcc a bit
205 setOperationAction(ISD::SETCC, MVT::i32, Custom);
207 // PowerPC does not have BRCOND which requires SetCC
208 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
210 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
212 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
213 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
215 // PowerPC does not have [U|S]INT_TO_FP
216 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
217 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
219 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
220 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
221 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
222 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
224 // We cannot sextinreg(i1). Expand to shifts.
225 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
227 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
228 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
229 // support continuation, user-level threading, and etc.. As a result, no
230 // other SjLj exception interfaces are implemented and please don't build
231 // your own exception handling based on them.
232 // LLVM/Clang supports zero-cost DWARF exception handling.
233 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
234 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
236 // We want to legalize GlobalAddress and ConstantPool nodes into the
237 // appropriate instructions to materialize the address.
238 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
239 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
240 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
241 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
242 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
243 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
244 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
245 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
246 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
247 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
250 setOperationAction(ISD::TRAP, MVT::Other, Legal);
252 // TRAMPOLINE is custom lowered.
253 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
254 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
256 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
257 setOperationAction(ISD::VASTART , MVT::Other, Custom);
259 if (Subtarget->isSVR4ABI()) {
261 // VAARG always uses double-word chunks, so promote anything smaller.
262 setOperationAction(ISD::VAARG, MVT::i1, Promote);
263 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
264 setOperationAction(ISD::VAARG, MVT::i8, Promote);
265 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
266 setOperationAction(ISD::VAARG, MVT::i16, Promote);
267 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
268 setOperationAction(ISD::VAARG, MVT::i32, Promote);
269 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
270 setOperationAction(ISD::VAARG, MVT::Other, Expand);
272 // VAARG is custom lowered with the 32-bit SVR4 ABI.
273 setOperationAction(ISD::VAARG, MVT::Other, Custom);
274 setOperationAction(ISD::VAARG, MVT::i64, Custom);
277 setOperationAction(ISD::VAARG, MVT::Other, Expand);
279 if (Subtarget->isSVR4ABI() && !isPPC64)
280 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
281 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
283 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
285 // Use the default implementation.
286 setOperationAction(ISD::VAEND , MVT::Other, Expand);
287 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
288 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
289 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
290 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
292 // We want to custom lower some of our intrinsics.
293 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
295 // To handle counter-based loop conditions.
296 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
298 // Comparisons that require checking two conditions.
299 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
300 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
301 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
302 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
303 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
304 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
305 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
306 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
307 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
308 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
309 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
310 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
312 if (Subtarget->has64BitSupport()) {
313 // They also have instructions for converting between i64 and fp.
314 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
315 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
316 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
317 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
318 // This is just the low 32 bits of a (signed) fp->i64 conversion.
319 // We cannot do this with Promote because i64 is not a legal type.
320 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
322 if (PPCSubTarget.hasLFIWAX() || Subtarget->isPPC64())
323 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
325 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
326 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
329 // With the instructions enabled under FPCVT, we can do everything.
330 if (PPCSubTarget.hasFPCVT()) {
331 if (Subtarget->has64BitSupport()) {
332 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
333 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
334 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
335 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
338 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
339 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
340 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
341 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
344 if (Subtarget->use64BitRegs()) {
345 // 64-bit PowerPC implementations can support i64 types directly
346 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
347 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
348 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
349 // 64-bit PowerPC wants to expand i128 shifts itself.
350 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
351 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
352 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
354 // 32-bit PowerPC wants to expand i64 shifts itself.
355 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
356 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
357 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
360 if (Subtarget->hasAltivec()) {
361 // First set operation action for all vector types to expand. Then we
362 // will selectively turn on ones that can be effectively codegen'd.
363 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
364 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
365 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
367 // add/sub are legal for all supported vector VT's.
368 setOperationAction(ISD::ADD , VT, Legal);
369 setOperationAction(ISD::SUB , VT, Legal);
371 // We promote all shuffles to v16i8.
372 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
373 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
375 // We promote all non-typed operations to v4i32.
376 setOperationAction(ISD::AND , VT, Promote);
377 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
378 setOperationAction(ISD::OR , VT, Promote);
379 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
380 setOperationAction(ISD::XOR , VT, Promote);
381 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
382 setOperationAction(ISD::LOAD , VT, Promote);
383 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
384 setOperationAction(ISD::SELECT, VT, Promote);
385 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
386 setOperationAction(ISD::STORE, VT, Promote);
387 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
389 // No other operations are legal.
390 setOperationAction(ISD::MUL , VT, Expand);
391 setOperationAction(ISD::SDIV, VT, Expand);
392 setOperationAction(ISD::SREM, VT, Expand);
393 setOperationAction(ISD::UDIV, VT, Expand);
394 setOperationAction(ISD::UREM, VT, Expand);
395 setOperationAction(ISD::FDIV, VT, Expand);
396 setOperationAction(ISD::FREM, VT, Expand);
397 setOperationAction(ISD::FNEG, VT, Expand);
398 setOperationAction(ISD::FSQRT, VT, Expand);
399 setOperationAction(ISD::FLOG, VT, Expand);
400 setOperationAction(ISD::FLOG10, VT, Expand);
401 setOperationAction(ISD::FLOG2, VT, Expand);
402 setOperationAction(ISD::FEXP, VT, Expand);
403 setOperationAction(ISD::FEXP2, VT, Expand);
404 setOperationAction(ISD::FSIN, VT, Expand);
405 setOperationAction(ISD::FCOS, VT, Expand);
406 setOperationAction(ISD::FABS, VT, Expand);
407 setOperationAction(ISD::FPOWI, VT, Expand);
408 setOperationAction(ISD::FFLOOR, VT, Expand);
409 setOperationAction(ISD::FCEIL, VT, Expand);
410 setOperationAction(ISD::FTRUNC, VT, Expand);
411 setOperationAction(ISD::FRINT, VT, Expand);
412 setOperationAction(ISD::FNEARBYINT, VT, Expand);
413 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
414 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
415 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
416 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
417 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
418 setOperationAction(ISD::UDIVREM, VT, Expand);
419 setOperationAction(ISD::SDIVREM, VT, Expand);
420 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
421 setOperationAction(ISD::FPOW, VT, Expand);
422 setOperationAction(ISD::CTPOP, VT, Expand);
423 setOperationAction(ISD::CTLZ, VT, Expand);
424 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
425 setOperationAction(ISD::CTTZ, VT, Expand);
426 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
427 setOperationAction(ISD::VSELECT, VT, Expand);
428 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
430 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
431 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
432 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
433 setTruncStoreAction(VT, InnerVT, Expand);
435 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
436 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
437 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
440 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
441 // with merges, splats, etc.
442 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
444 setOperationAction(ISD::AND , MVT::v4i32, Legal);
445 setOperationAction(ISD::OR , MVT::v4i32, Legal);
446 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
447 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
448 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
449 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
450 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
451 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
452 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
453 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
454 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
455 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
456 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
457 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
459 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
460 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
461 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
462 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
464 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
465 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
467 if (TM.Options.UnsafeFPMath) {
468 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
469 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
472 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
473 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
474 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
476 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
477 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
479 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
480 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
481 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
482 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
484 // Altivec does not contain unordered floating-point compare instructions
485 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
486 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
487 setCondCodeAction(ISD::SETUGT, MVT::v4f32, Expand);
488 setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand);
489 setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand);
490 setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand);
492 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
493 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
496 if (Subtarget->has64BitSupport()) {
497 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
498 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
501 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
502 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
503 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
504 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
506 setBooleanContents(ZeroOrOneBooleanContent);
507 // Altivec instructions set fields to all zeros or all ones.
508 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
511 setStackPointerRegisterToSaveRestore(PPC::X1);
512 setExceptionPointerRegister(PPC::X3);
513 setExceptionSelectorRegister(PPC::X4);
515 setStackPointerRegisterToSaveRestore(PPC::R1);
516 setExceptionPointerRegister(PPC::R3);
517 setExceptionSelectorRegister(PPC::R4);
520 // We have target-specific dag combine patterns for the following nodes:
521 setTargetDAGCombine(ISD::SINT_TO_FP);
522 setTargetDAGCombine(ISD::LOAD);
523 setTargetDAGCombine(ISD::STORE);
524 setTargetDAGCombine(ISD::BR_CC);
525 setTargetDAGCombine(ISD::BSWAP);
526 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
528 // Use reciprocal estimates.
529 if (TM.Options.UnsafeFPMath) {
530 setTargetDAGCombine(ISD::FDIV);
531 setTargetDAGCombine(ISD::FSQRT);
534 // Darwin long double math library functions have $LDBL128 appended.
535 if (Subtarget->isDarwin()) {
536 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
537 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
538 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
539 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
540 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
541 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
542 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
543 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
544 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
545 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
548 setMinFunctionAlignment(2);
549 if (PPCSubTarget.isDarwin())
550 setPrefFunctionAlignment(4);
552 if (isPPC64 && Subtarget->isJITCodeModel())
553 // Temporary workaround for the inability of PPC64 JIT to handle jump
555 setSupportJumpTables(false);
557 setInsertFencesForAtomic(true);
559 if (Subtarget->enableMachineScheduler())
560 setSchedulingPreference(Sched::Source);
562 setSchedulingPreference(Sched::Hybrid);
564 computeRegisterProperties();
566 // The Freescale cores does better with aggressive inlining of memcpy and
567 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores).
568 if (Subtarget->getDarwinDirective() == PPC::DIR_E500mc ||
569 Subtarget->getDarwinDirective() == PPC::DIR_E5500) {
570 MaxStoresPerMemset = 32;
571 MaxStoresPerMemsetOptSize = 16;
572 MaxStoresPerMemcpy = 32;
573 MaxStoresPerMemcpyOptSize = 8;
574 MaxStoresPerMemmove = 32;
575 MaxStoresPerMemmoveOptSize = 8;
577 setPrefFunctionAlignment(4);
581 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
582 /// the desired ByVal argument alignment.
583 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
584 unsigned MaxMaxAlign) {
585 if (MaxAlign == MaxMaxAlign)
587 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
588 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
590 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
592 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
593 unsigned EltAlign = 0;
594 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
595 if (EltAlign > MaxAlign)
597 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
598 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
599 unsigned EltAlign = 0;
600 getMaxByValAlign(STy->getElementType(i), EltAlign, MaxMaxAlign);
601 if (EltAlign > MaxAlign)
603 if (MaxAlign == MaxMaxAlign)
609 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
610 /// function arguments in the caller parameter area.
611 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
612 // Darwin passes everything on 4 byte boundary.
613 if (PPCSubTarget.isDarwin())
616 // 16byte and wider vectors are passed on 16byte boundary.
617 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
618 unsigned Align = PPCSubTarget.isPPC64() ? 8 : 4;
619 if (PPCSubTarget.hasAltivec() || PPCSubTarget.hasQPX())
620 getMaxByValAlign(Ty, Align, PPCSubTarget.hasQPX() ? 32 : 16);
624 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
627 case PPCISD::FSEL: return "PPCISD::FSEL";
628 case PPCISD::FCFID: return "PPCISD::FCFID";
629 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
630 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
631 case PPCISD::FRE: return "PPCISD::FRE";
632 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
633 case PPCISD::STFIWX: return "PPCISD::STFIWX";
634 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
635 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
636 case PPCISD::VPERM: return "PPCISD::VPERM";
637 case PPCISD::Hi: return "PPCISD::Hi";
638 case PPCISD::Lo: return "PPCISD::Lo";
639 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
640 case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE";
641 case PPCISD::LOAD: return "PPCISD::LOAD";
642 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
643 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
644 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
645 case PPCISD::SRL: return "PPCISD::SRL";
646 case PPCISD::SRA: return "PPCISD::SRA";
647 case PPCISD::SHL: return "PPCISD::SHL";
648 case PPCISD::CALL: return "PPCISD::CALL";
649 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
650 case PPCISD::MTCTR: return "PPCISD::MTCTR";
651 case PPCISD::BCTRL: return "PPCISD::BCTRL";
652 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
653 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
654 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
655 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
656 case PPCISD::VCMP: return "PPCISD::VCMP";
657 case PPCISD::VCMPo: return "PPCISD::VCMPo";
658 case PPCISD::LBRX: return "PPCISD::LBRX";
659 case PPCISD::STBRX: return "PPCISD::STBRX";
660 case PPCISD::LARX: return "PPCISD::LARX";
661 case PPCISD::STCX: return "PPCISD::STCX";
662 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
663 case PPCISD::BDNZ: return "PPCISD::BDNZ";
664 case PPCISD::BDZ: return "PPCISD::BDZ";
665 case PPCISD::MFFS: return "PPCISD::MFFS";
666 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
667 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
668 case PPCISD::CR6SET: return "PPCISD::CR6SET";
669 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
670 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
671 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
672 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
673 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
674 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
675 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
676 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
677 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
678 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
679 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
680 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
681 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
682 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
683 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
684 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
685 case PPCISD::SC: return "PPCISD::SC";
689 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
692 return VT.changeVectorElementTypeToInteger();
695 //===----------------------------------------------------------------------===//
696 // Node matching predicates, for use by the tblgen matching code.
697 //===----------------------------------------------------------------------===//
699 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
700 static bool isFloatingPointZero(SDValue Op) {
701 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
702 return CFP->getValueAPF().isZero();
703 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
704 // Maybe this has already been legalized into the constant pool?
705 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
706 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
707 return CFP->getValueAPF().isZero();
712 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
713 /// true if Op is undef or if it matches the specified value.
714 static bool isConstantOrUndef(int Op, int Val) {
715 return Op < 0 || Op == Val;
718 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
719 /// VPKUHUM instruction.
720 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
722 for (unsigned i = 0; i != 16; ++i)
723 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
726 for (unsigned i = 0; i != 8; ++i)
727 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) ||
728 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1))
734 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
735 /// VPKUWUM instruction.
736 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
738 for (unsigned i = 0; i != 16; i += 2)
739 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
740 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
743 for (unsigned i = 0; i != 8; i += 2)
744 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
745 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) ||
746 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) ||
747 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3))
753 /// isVMerge - Common function, used to match vmrg* shuffles.
755 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
756 unsigned LHSStart, unsigned RHSStart) {
757 assert(N->getValueType(0) == MVT::v16i8 &&
758 "PPC only supports shuffles by bytes!");
759 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
760 "Unsupported merge size!");
762 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
763 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
764 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
765 LHSStart+j+i*UnitSize) ||
766 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
767 RHSStart+j+i*UnitSize))
773 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
774 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
775 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
778 return isVMerge(N, UnitSize, 8, 24);
779 return isVMerge(N, UnitSize, 8, 8);
782 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
783 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
784 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
787 return isVMerge(N, UnitSize, 0, 16);
788 return isVMerge(N, UnitSize, 0, 0);
792 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
793 /// amount, otherwise return -1.
794 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
795 assert(N->getValueType(0) == MVT::v16i8 &&
796 "PPC only supports shuffles by bytes!");
798 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
800 // Find the first non-undef value in the shuffle mask.
802 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
805 if (i == 16) return -1; // all undef.
807 // Otherwise, check to see if the rest of the elements are consecutively
808 // numbered from this value.
809 unsigned ShiftAmt = SVOp->getMaskElt(i);
810 if (ShiftAmt < i) return -1;
814 // Check the rest of the elements to see if they are consecutive.
815 for (++i; i != 16; ++i)
816 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
819 // Check the rest of the elements to see if they are consecutive.
820 for (++i; i != 16; ++i)
821 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
827 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
828 /// specifies a splat of a single element that is suitable for input to
829 /// VSPLTB/VSPLTH/VSPLTW.
830 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
831 assert(N->getValueType(0) == MVT::v16i8 &&
832 (EltSize == 1 || EltSize == 2 || EltSize == 4));
834 // This is a splat operation if each element of the permute is the same, and
835 // if the value doesn't reference the second vector.
836 unsigned ElementBase = N->getMaskElt(0);
838 // FIXME: Handle UNDEF elements too!
839 if (ElementBase >= 16)
842 // Check that the indices are consecutive, in the case of a multi-byte element
843 // splatted with a v16i8 mask.
844 for (unsigned i = 1; i != EltSize; ++i)
845 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
848 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
849 if (N->getMaskElt(i) < 0) continue;
850 for (unsigned j = 0; j != EltSize; ++j)
851 if (N->getMaskElt(i+j) != N->getMaskElt(j))
857 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
859 bool PPC::isAllNegativeZeroVector(SDNode *N) {
860 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
862 APInt APVal, APUndef;
866 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
867 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
868 return CFP->getValueAPF().isNegZero();
873 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
874 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
875 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
876 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
877 assert(isSplatShuffleMask(SVOp, EltSize));
878 return SVOp->getMaskElt(0) / EltSize;
881 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
882 /// by using a vspltis[bhw] instruction of the specified element size, return
883 /// the constant being splatted. The ByteSize field indicates the number of
884 /// bytes of each element [124] -> [bhw].
885 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
888 // If ByteSize of the splat is bigger than the element size of the
889 // build_vector, then we have a case where we are checking for a splat where
890 // multiple elements of the buildvector are folded together into a single
891 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
892 unsigned EltSize = 16/N->getNumOperands();
893 if (EltSize < ByteSize) {
894 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
895 SDValue UniquedVals[4];
896 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
898 // See if all of the elements in the buildvector agree across.
899 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
900 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
901 // If the element isn't a constant, bail fully out.
902 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
905 if (UniquedVals[i&(Multiple-1)].getNode() == 0)
906 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
907 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
908 return SDValue(); // no match.
911 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
912 // either constant or undef values that are identical for each chunk. See
913 // if these chunks can form into a larger vspltis*.
915 // Check to see if all of the leading entries are either 0 or -1. If
916 // neither, then this won't fit into the immediate field.
917 bool LeadingZero = true;
918 bool LeadingOnes = true;
919 for (unsigned i = 0; i != Multiple-1; ++i) {
920 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs.
922 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
923 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
925 // Finally, check the least significant entry.
927 if (UniquedVals[Multiple-1].getNode() == 0)
928 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
929 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
931 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
934 if (UniquedVals[Multiple-1].getNode() == 0)
935 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
936 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
937 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
938 return DAG.getTargetConstant(Val, MVT::i32);
944 // Check to see if this buildvec has a single non-undef value in its elements.
945 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
946 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
947 if (OpVal.getNode() == 0)
948 OpVal = N->getOperand(i);
949 else if (OpVal != N->getOperand(i))
953 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def.
955 unsigned ValSizeInBytes = EltSize;
957 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
958 Value = CN->getZExtValue();
959 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
960 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
961 Value = FloatToBits(CN->getValueAPF().convertToFloat());
964 // If the splat value is larger than the element value, then we can never do
965 // this splat. The only case that we could fit the replicated bits into our
966 // immediate field for would be zero, and we prefer to use vxor for it.
967 if (ValSizeInBytes < ByteSize) return SDValue();
969 // If the element value is larger than the splat value, cut it in half and
970 // check to see if the two halves are equal. Continue doing this until we
971 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
972 while (ValSizeInBytes > ByteSize) {
973 ValSizeInBytes >>= 1;
975 // If the top half equals the bottom half, we're still ok.
976 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
977 (Value & ((1 << (8*ValSizeInBytes))-1)))
981 // Properly sign extend the value.
982 int MaskVal = SignExtend32(Value, ByteSize * 8);
984 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
985 if (MaskVal == 0) return SDValue();
987 // Finally, if this value fits in a 5 bit sext field, return it
988 if (SignExtend32<5>(MaskVal) == MaskVal)
989 return DAG.getTargetConstant(MaskVal, MVT::i32);
993 //===----------------------------------------------------------------------===//
994 // Addressing Mode Selection
995 //===----------------------------------------------------------------------===//
997 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
998 /// or 64-bit immediate, and if the value can be accurately represented as a
999 /// sign extension from a 16-bit value. If so, this returns true and the
1001 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1002 if (N->getOpcode() != ISD::Constant)
1005 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1006 if (N->getValueType(0) == MVT::i32)
1007 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1009 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1011 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1012 return isIntS16Immediate(Op.getNode(), Imm);
1016 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1017 /// can be represented as an indexed [r+r] operation. Returns false if it
1018 /// can be more efficiently represented with [r+imm].
1019 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1021 SelectionDAG &DAG) const {
1023 if (N.getOpcode() == ISD::ADD) {
1024 if (isIntS16Immediate(N.getOperand(1), imm))
1025 return false; // r+i
1026 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1027 return false; // r+i
1029 Base = N.getOperand(0);
1030 Index = N.getOperand(1);
1032 } else if (N.getOpcode() == ISD::OR) {
1033 if (isIntS16Immediate(N.getOperand(1), imm))
1034 return false; // r+i can fold it if we can.
1036 // If this is an or of disjoint bitfields, we can codegen this as an add
1037 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1039 APInt LHSKnownZero, LHSKnownOne;
1040 APInt RHSKnownZero, RHSKnownOne;
1041 DAG.ComputeMaskedBits(N.getOperand(0),
1042 LHSKnownZero, LHSKnownOne);
1044 if (LHSKnownZero.getBoolValue()) {
1045 DAG.ComputeMaskedBits(N.getOperand(1),
1046 RHSKnownZero, RHSKnownOne);
1047 // If all of the bits are known zero on the LHS or RHS, the add won't
1049 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1050 Base = N.getOperand(0);
1051 Index = N.getOperand(1);
1060 // If we happen to be doing an i64 load or store into a stack slot that has
1061 // less than a 4-byte alignment, then the frame-index elimination may need to
1062 // use an indexed load or store instruction (because the offset may not be a
1063 // multiple of 4). The extra register needed to hold the offset comes from the
1064 // register scavenger, and it is possible that the scavenger will need to use
1065 // an emergency spill slot. As a result, we need to make sure that a spill slot
1066 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1068 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1069 // FIXME: This does not handle the LWA case.
1073 // NOTE: We'll exclude negative FIs here, which come from argument
1074 // lowering, because there are no known test cases triggering this problem
1075 // using packed structures (or similar). We can remove this exclusion if
1076 // we find such a test case. The reason why this is so test-case driven is
1077 // because this entire 'fixup' is only to prevent crashes (from the
1078 // register scavenger) on not-really-valid inputs. For example, if we have:
1080 // %b = bitcast i1* %a to i64*
1081 // store i64* a, i64 b
1082 // then the store should really be marked as 'align 1', but is not. If it
1083 // were marked as 'align 1' then the indexed form would have been
1084 // instruction-selected initially, and the problem this 'fixup' is preventing
1085 // won't happen regardless.
1089 MachineFunction &MF = DAG.getMachineFunction();
1090 MachineFrameInfo *MFI = MF.getFrameInfo();
1092 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1096 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1097 FuncInfo->setHasNonRISpills();
1100 /// Returns true if the address N can be represented by a base register plus
1101 /// a signed 16-bit displacement [r+imm], and if it is not better
1102 /// represented as reg+reg. If Aligned is true, only accept displacements
1103 /// suitable for STD and friends, i.e. multiples of 4.
1104 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1107 bool Aligned) const {
1108 // FIXME dl should come from parent load or store, not from address
1110 // If this can be more profitably realized as r+r, fail.
1111 if (SelectAddressRegReg(N, Disp, Base, DAG))
1114 if (N.getOpcode() == ISD::ADD) {
1116 if (isIntS16Immediate(N.getOperand(1), imm) &&
1117 (!Aligned || (imm & 3) == 0)) {
1118 Disp = DAG.getTargetConstant(imm, N.getValueType());
1119 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1120 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1121 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1123 Base = N.getOperand(0);
1125 return true; // [r+i]
1126 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1127 // Match LOAD (ADD (X, Lo(G))).
1128 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1129 && "Cannot handle constant offsets yet!");
1130 Disp = N.getOperand(1).getOperand(0); // The global address.
1131 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1132 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1133 Disp.getOpcode() == ISD::TargetConstantPool ||
1134 Disp.getOpcode() == ISD::TargetJumpTable);
1135 Base = N.getOperand(0);
1136 return true; // [&g+r]
1138 } else if (N.getOpcode() == ISD::OR) {
1140 if (isIntS16Immediate(N.getOperand(1), imm) &&
1141 (!Aligned || (imm & 3) == 0)) {
1142 // If this is an or of disjoint bitfields, we can codegen this as an add
1143 // (for better address arithmetic) if the LHS and RHS of the OR are
1144 // provably disjoint.
1145 APInt LHSKnownZero, LHSKnownOne;
1146 DAG.ComputeMaskedBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1148 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1149 // If all of the bits are known zero on the LHS or RHS, the add won't
1151 Base = N.getOperand(0);
1152 Disp = DAG.getTargetConstant(imm, N.getValueType());
1156 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1157 // Loading from a constant address.
1159 // If this address fits entirely in a 16-bit sext immediate field, codegen
1162 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1163 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1164 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1165 CN->getValueType(0));
1169 // Handle 32-bit sext immediates with LIS + addr mode.
1170 if ((CN->getValueType(0) == MVT::i32 ||
1171 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1172 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1173 int Addr = (int)CN->getZExtValue();
1175 // Otherwise, break this down into an LIS + disp.
1176 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1178 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1179 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1180 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1185 Disp = DAG.getTargetConstant(0, getPointerTy());
1186 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1187 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1188 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1191 return true; // [r+0]
1194 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1195 /// represented as an indexed [r+r] operation.
1196 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1198 SelectionDAG &DAG) const {
1199 // Check to see if we can easily represent this as an [r+r] address. This
1200 // will fail if it thinks that the address is more profitably represented as
1201 // reg+imm, e.g. where imm = 0.
1202 if (SelectAddressRegReg(N, Base, Index, DAG))
1205 // If the operand is an addition, always emit this as [r+r], since this is
1206 // better (for code size, and execution, as the memop does the add for free)
1207 // than emitting an explicit add.
1208 if (N.getOpcode() == ISD::ADD) {
1209 Base = N.getOperand(0);
1210 Index = N.getOperand(1);
1214 // Otherwise, do it the hard way, using R0 as the base register.
1215 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1221 /// getPreIndexedAddressParts - returns true by value, base pointer and
1222 /// offset pointer and addressing mode by reference if the node's address
1223 /// can be legally represented as pre-indexed load / store address.
1224 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1226 ISD::MemIndexedMode &AM,
1227 SelectionDAG &DAG) const {
1228 if (DisablePPCPreinc) return false;
1234 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1235 Ptr = LD->getBasePtr();
1236 VT = LD->getMemoryVT();
1237 Alignment = LD->getAlignment();
1238 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1239 Ptr = ST->getBasePtr();
1240 VT = ST->getMemoryVT();
1241 Alignment = ST->getAlignment();
1246 // PowerPC doesn't have preinc load/store instructions for vectors.
1250 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1252 // Common code will reject creating a pre-inc form if the base pointer
1253 // is a frame index, or if N is a store and the base pointer is either
1254 // the same as or a predecessor of the value being stored. Check for
1255 // those situations here, and try with swapped Base/Offset instead.
1258 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1261 SDValue Val = cast<StoreSDNode>(N)->getValue();
1262 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1267 std::swap(Base, Offset);
1273 // LDU/STU can only handle immediates that are a multiple of 4.
1274 if (VT != MVT::i64) {
1275 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1278 // LDU/STU need an address with at least 4-byte alignment.
1282 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1286 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1287 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1288 // sext i32 to i64 when addr mode is r+i.
1289 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1290 LD->getExtensionType() == ISD::SEXTLOAD &&
1291 isa<ConstantSDNode>(Offset))
1299 //===----------------------------------------------------------------------===//
1300 // LowerOperation implementation
1301 //===----------------------------------------------------------------------===//
1303 /// GetLabelAccessInfo - Return true if we should reference labels using a
1304 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1305 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1306 unsigned &LoOpFlags, const GlobalValue *GV = 0) {
1307 HiOpFlags = PPCII::MO_HA;
1308 LoOpFlags = PPCII::MO_LO;
1310 // Don't use the pic base if not in PIC relocation model. Or if we are on a
1311 // non-darwin platform. We don't support PIC on other platforms yet.
1312 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ &&
1313 TM.getSubtarget<PPCSubtarget>().isDarwin();
1315 HiOpFlags |= PPCII::MO_PIC_FLAG;
1316 LoOpFlags |= PPCII::MO_PIC_FLAG;
1319 // If this is a reference to a global value that requires a non-lazy-ptr, make
1320 // sure that instruction lowering adds it.
1321 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1322 HiOpFlags |= PPCII::MO_NLP_FLAG;
1323 LoOpFlags |= PPCII::MO_NLP_FLAG;
1325 if (GV->hasHiddenVisibility()) {
1326 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1327 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1334 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1335 SelectionDAG &DAG) {
1336 EVT PtrVT = HiPart.getValueType();
1337 SDValue Zero = DAG.getConstant(0, PtrVT);
1340 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1341 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1343 // With PIC, the first instruction is actually "GR+hi(&G)".
1345 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1346 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1348 // Generate non-pic code that has direct accesses to the constant pool.
1349 // The address of the global is just (hi(&g)+lo(&g)).
1350 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1353 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1354 SelectionDAG &DAG) const {
1355 EVT PtrVT = Op.getValueType();
1356 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1357 const Constant *C = CP->getConstVal();
1359 // 64-bit SVR4 ABI code is always position-independent.
1360 // The actual address of the GlobalValue is stored in the TOC.
1361 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1362 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1363 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1364 DAG.getRegister(PPC::X2, MVT::i64));
1367 unsigned MOHiFlag, MOLoFlag;
1368 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1370 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1372 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1373 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1376 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1377 EVT PtrVT = Op.getValueType();
1378 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1380 // 64-bit SVR4 ABI code is always position-independent.
1381 // The actual address of the GlobalValue is stored in the TOC.
1382 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1383 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1384 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1385 DAG.getRegister(PPC::X2, MVT::i64));
1388 unsigned MOHiFlag, MOLoFlag;
1389 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1390 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1391 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1392 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1395 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1396 SelectionDAG &DAG) const {
1397 EVT PtrVT = Op.getValueType();
1399 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1401 unsigned MOHiFlag, MOLoFlag;
1402 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1403 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1404 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1405 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1408 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1409 SelectionDAG &DAG) const {
1411 // FIXME: TLS addresses currently use medium model code sequences,
1412 // which is the most useful form. Eventually support for small and
1413 // large models could be added if users need it, at the cost of
1414 // additional complexity.
1415 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1417 const GlobalValue *GV = GA->getGlobal();
1418 EVT PtrVT = getPointerTy();
1419 bool is64bit = PPCSubTarget.isPPC64();
1421 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1423 if (Model == TLSModel::LocalExec) {
1424 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1425 PPCII::MO_TPREL_HA);
1426 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1427 PPCII::MO_TPREL_LO);
1428 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1429 is64bit ? MVT::i64 : MVT::i32);
1430 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1431 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1435 llvm_unreachable("only local-exec is currently supported for ppc32");
1437 if (Model == TLSModel::InitialExec) {
1438 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1439 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1441 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1442 SDValue TPOffsetHi = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1443 PtrVT, GOTReg, TGA);
1444 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1445 PtrVT, TGA, TPOffsetHi);
1446 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
1449 if (Model == TLSModel::GeneralDynamic) {
1450 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1451 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1452 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1454 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1457 // We need a chain node, and don't have one handy. The underlying
1458 // call has no side effects, so using the function entry node
1460 SDValue Chain = DAG.getEntryNode();
1461 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1462 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1463 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl,
1464 PtrVT, ParmReg, TGA);
1465 // The return value from GET_TLS_ADDR really is in X3 already, but
1466 // some hacks are needed here to tie everything together. The extra
1467 // copies dissolve during subsequent transforms.
1468 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1469 return DAG.getCopyFromReg(Chain, dl, PPC::X3, PtrVT);
1472 if (Model == TLSModel::LocalDynamic) {
1473 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1474 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1475 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1477 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1480 // We need a chain node, and don't have one handy. The underlying
1481 // call has no side effects, so using the function entry node
1483 SDValue Chain = DAG.getEntryNode();
1484 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1485 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1486 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl,
1487 PtrVT, ParmReg, TGA);
1488 // The return value from GET_TLSLD_ADDR really is in X3 already, but
1489 // some hacks are needed here to tie everything together. The extra
1490 // copies dissolve during subsequent transforms.
1491 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1492 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1493 Chain, ParmReg, TGA);
1494 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1497 llvm_unreachable("Unknown TLS model!");
1500 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1501 SelectionDAG &DAG) const {
1502 EVT PtrVT = Op.getValueType();
1503 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1505 const GlobalValue *GV = GSDN->getGlobal();
1507 // 64-bit SVR4 ABI code is always position-independent.
1508 // The actual address of the GlobalValue is stored in the TOC.
1509 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1510 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1511 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1512 DAG.getRegister(PPC::X2, MVT::i64));
1515 unsigned MOHiFlag, MOLoFlag;
1516 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1519 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1521 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1523 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1525 // If the global reference is actually to a non-lazy-pointer, we have to do an
1526 // extra load to get the address of the global.
1527 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1528 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1529 false, false, false, 0);
1533 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1534 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1537 // If we're comparing for equality to zero, expose the fact that this is
1538 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1539 // fold the new nodes.
1540 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1541 if (C->isNullValue() && CC == ISD::SETEQ) {
1542 EVT VT = Op.getOperand(0).getValueType();
1543 SDValue Zext = Op.getOperand(0);
1544 if (VT.bitsLT(MVT::i32)) {
1546 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1548 unsigned Log2b = Log2_32(VT.getSizeInBits());
1549 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1550 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1551 DAG.getConstant(Log2b, MVT::i32));
1552 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1554 // Leave comparisons against 0 and -1 alone for now, since they're usually
1555 // optimized. FIXME: revisit this when we can custom lower all setcc
1557 if (C->isAllOnesValue() || C->isNullValue())
1561 // If we have an integer seteq/setne, turn it into a compare against zero
1562 // by xor'ing the rhs with the lhs, which is faster than setting a
1563 // condition register, reading it back out, and masking the correct bit. The
1564 // normal approach here uses sub to do this instead of xor. Using xor exposes
1565 // the result to other bit-twiddling opportunities.
1566 EVT LHSVT = Op.getOperand(0).getValueType();
1567 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1568 EVT VT = Op.getValueType();
1569 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1571 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1576 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1577 const PPCSubtarget &Subtarget) const {
1578 SDNode *Node = Op.getNode();
1579 EVT VT = Node->getValueType(0);
1580 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1581 SDValue InChain = Node->getOperand(0);
1582 SDValue VAListPtr = Node->getOperand(1);
1583 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1586 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1589 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1590 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1592 InChain = GprIndex.getValue(1);
1594 if (VT == MVT::i64) {
1595 // Check if GprIndex is even
1596 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1597 DAG.getConstant(1, MVT::i32));
1598 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1599 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1600 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1601 DAG.getConstant(1, MVT::i32));
1602 // Align GprIndex to be even if it isn't
1603 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1607 // fpr index is 1 byte after gpr
1608 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1609 DAG.getConstant(1, MVT::i32));
1612 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1613 FprPtr, MachinePointerInfo(SV), MVT::i8,
1615 InChain = FprIndex.getValue(1);
1617 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1618 DAG.getConstant(8, MVT::i32));
1620 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1621 DAG.getConstant(4, MVT::i32));
1624 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1625 MachinePointerInfo(), false, false,
1627 InChain = OverflowArea.getValue(1);
1629 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1630 MachinePointerInfo(), false, false,
1632 InChain = RegSaveArea.getValue(1);
1634 // select overflow_area if index > 8
1635 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1636 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1638 // adjustment constant gpr_index * 4/8
1639 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1640 VT.isInteger() ? GprIndex : FprIndex,
1641 DAG.getConstant(VT.isInteger() ? 4 : 8,
1644 // OurReg = RegSaveArea + RegConstant
1645 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1648 // Floating types are 32 bytes into RegSaveArea
1649 if (VT.isFloatingPoint())
1650 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1651 DAG.getConstant(32, MVT::i32));
1653 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1654 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1655 VT.isInteger() ? GprIndex : FprIndex,
1656 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1659 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1660 VT.isInteger() ? VAListPtr : FprPtr,
1661 MachinePointerInfo(SV),
1662 MVT::i8, false, false, 0);
1664 // determine if we should load from reg_save_area or overflow_area
1665 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1667 // increase overflow_area by 4/8 if gpr/fpr > 8
1668 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1669 DAG.getConstant(VT.isInteger() ? 4 : 8,
1672 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1675 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1677 MachinePointerInfo(),
1678 MVT::i32, false, false, 0);
1680 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1681 false, false, false, 0);
1684 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
1685 const PPCSubtarget &Subtarget) const {
1686 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
1688 // We have to copy the entire va_list struct:
1689 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
1690 return DAG.getMemcpy(Op.getOperand(0), Op,
1691 Op.getOperand(1), Op.getOperand(2),
1692 DAG.getConstant(12, MVT::i32), 8, false, true,
1693 MachinePointerInfo(), MachinePointerInfo());
1696 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
1697 SelectionDAG &DAG) const {
1698 return Op.getOperand(0);
1701 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
1702 SelectionDAG &DAG) const {
1703 SDValue Chain = Op.getOperand(0);
1704 SDValue Trmp = Op.getOperand(1); // trampoline
1705 SDValue FPtr = Op.getOperand(2); // nested function
1706 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1709 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1710 bool isPPC64 = (PtrVT == MVT::i64);
1712 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
1715 TargetLowering::ArgListTy Args;
1716 TargetLowering::ArgListEntry Entry;
1718 Entry.Ty = IntPtrTy;
1719 Entry.Node = Trmp; Args.push_back(Entry);
1721 // TrampSize == (isPPC64 ? 48 : 40);
1722 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1723 isPPC64 ? MVT::i64 : MVT::i32);
1724 Args.push_back(Entry);
1726 Entry.Node = FPtr; Args.push_back(Entry);
1727 Entry.Node = Nest; Args.push_back(Entry);
1729 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1730 TargetLowering::CallLoweringInfo CLI(Chain,
1731 Type::getVoidTy(*DAG.getContext()),
1732 false, false, false, false, 0,
1734 /*isTailCall=*/false,
1735 /*doesNotRet=*/false,
1736 /*isReturnValueUsed=*/true,
1737 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1739 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1741 return CallResult.second;
1744 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1745 const PPCSubtarget &Subtarget) const {
1746 MachineFunction &MF = DAG.getMachineFunction();
1747 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1751 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
1752 // vastart just stores the address of the VarArgsFrameIndex slot into the
1753 // memory location argument.
1754 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1755 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1756 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1757 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
1758 MachinePointerInfo(SV),
1762 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
1763 // We suppose the given va_list is already allocated.
1766 // char gpr; /* index into the array of 8 GPRs
1767 // * stored in the register save area
1768 // * gpr=0 corresponds to r3,
1769 // * gpr=1 to r4, etc.
1771 // char fpr; /* index into the array of 8 FPRs
1772 // * stored in the register save area
1773 // * fpr=0 corresponds to f1,
1774 // * fpr=1 to f2, etc.
1776 // char *overflow_arg_area;
1777 // /* location on stack that holds
1778 // * the next overflow argument
1780 // char *reg_save_area;
1781 // /* where r3:r10 and f1:f8 (if saved)
1787 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
1788 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
1791 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1793 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
1795 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1798 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
1799 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1801 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
1802 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1804 uint64_t FPROffset = 1;
1805 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1807 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1809 // Store first byte : number of int regs
1810 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
1812 MachinePointerInfo(SV),
1813 MVT::i8, false, false, 0);
1814 uint64_t nextOffset = FPROffset;
1815 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
1818 // Store second byte : number of float regs
1819 SDValue secondStore =
1820 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
1821 MachinePointerInfo(SV, nextOffset), MVT::i8,
1823 nextOffset += StackOffset;
1824 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
1826 // Store second word : arguments given on stack
1827 SDValue thirdStore =
1828 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
1829 MachinePointerInfo(SV, nextOffset),
1831 nextOffset += FrameOffset;
1832 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
1834 // Store third word : arguments given in registers
1835 return DAG.getStore(thirdStore, dl, FR, nextPtr,
1836 MachinePointerInfo(SV, nextOffset),
1841 #include "PPCGenCallingConv.inc"
1843 // Function whose sole purpose is to kill compiler warnings
1844 // stemming from unused functions included from PPCGenCallingConv.inc.
1845 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
1846 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
1849 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
1850 CCValAssign::LocInfo &LocInfo,
1851 ISD::ArgFlagsTy &ArgFlags,
1856 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
1858 CCValAssign::LocInfo &LocInfo,
1859 ISD::ArgFlagsTy &ArgFlags,
1861 static const uint16_t ArgRegs[] = {
1862 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1863 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1865 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1867 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1869 // Skip one register if the first unallocated register has an even register
1870 // number and there are still argument registers available which have not been
1871 // allocated yet. RegNum is actually an index into ArgRegs, which means we
1872 // need to skip a register if RegNum is odd.
1873 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
1874 State.AllocateReg(ArgRegs[RegNum]);
1877 // Always return false here, as this function only makes sure that the first
1878 // unallocated register has an odd register number and does not actually
1879 // allocate a register for the current argument.
1883 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
1885 CCValAssign::LocInfo &LocInfo,
1886 ISD::ArgFlagsTy &ArgFlags,
1888 static const uint16_t ArgRegs[] = {
1889 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1893 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1895 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1897 // If there is only one Floating-point register left we need to put both f64
1898 // values of a split ppc_fp128 value on the stack.
1899 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
1900 State.AllocateReg(ArgRegs[RegNum]);
1903 // Always return false here, as this function only makes sure that the two f64
1904 // values a ppc_fp128 value is split into are both passed in registers or both
1905 // passed on the stack and does not actually allocate a register for the
1906 // current argument.
1910 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1912 static const uint16_t *GetFPR() {
1913 static const uint16_t FPR[] = {
1914 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1915 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1921 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
1923 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
1924 unsigned PtrByteSize) {
1925 unsigned ArgSize = ArgVT.getSizeInBits()/8;
1926 if (Flags.isByVal())
1927 ArgSize = Flags.getByValSize();
1928 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1934 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
1935 CallingConv::ID CallConv, bool isVarArg,
1936 const SmallVectorImpl<ISD::InputArg>
1938 SDLoc dl, SelectionDAG &DAG,
1939 SmallVectorImpl<SDValue> &InVals)
1941 if (PPCSubTarget.isSVR4ABI()) {
1942 if (PPCSubTarget.isPPC64())
1943 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
1946 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
1949 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
1955 PPCTargetLowering::LowerFormalArguments_32SVR4(
1957 CallingConv::ID CallConv, bool isVarArg,
1958 const SmallVectorImpl<ISD::InputArg>
1960 SDLoc dl, SelectionDAG &DAG,
1961 SmallVectorImpl<SDValue> &InVals) const {
1963 // 32-bit SVR4 ABI Stack Frame Layout:
1964 // +-----------------------------------+
1965 // +--> | Back chain |
1966 // | +-----------------------------------+
1967 // | | Floating-point register save area |
1968 // | +-----------------------------------+
1969 // | | General register save area |
1970 // | +-----------------------------------+
1971 // | | CR save word |
1972 // | +-----------------------------------+
1973 // | | VRSAVE save word |
1974 // | +-----------------------------------+
1975 // | | Alignment padding |
1976 // | +-----------------------------------+
1977 // | | Vector register save area |
1978 // | +-----------------------------------+
1979 // | | Local variable space |
1980 // | +-----------------------------------+
1981 // | | Parameter list area |
1982 // | +-----------------------------------+
1983 // | | LR save word |
1984 // | +-----------------------------------+
1985 // SP--> +--- | Back chain |
1986 // +-----------------------------------+
1989 // System V Application Binary Interface PowerPC Processor Supplement
1990 // AltiVec Technology Programming Interface Manual
1992 MachineFunction &MF = DAG.getMachineFunction();
1993 MachineFrameInfo *MFI = MF.getFrameInfo();
1994 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1996 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1997 // Potential tail calls could cause overwriting of argument stack slots.
1998 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
1999 (CallConv == CallingConv::Fast));
2000 unsigned PtrByteSize = 4;
2002 // Assign locations to all of the incoming arguments.
2003 SmallVector<CCValAssign, 16> ArgLocs;
2004 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2005 getTargetMachine(), ArgLocs, *DAG.getContext());
2007 // Reserve space for the linkage area on the stack.
2008 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
2010 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2012 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2013 CCValAssign &VA = ArgLocs[i];
2015 // Arguments stored in registers.
2016 if (VA.isRegLoc()) {
2017 const TargetRegisterClass *RC;
2018 EVT ValVT = VA.getValVT();
2020 switch (ValVT.getSimpleVT().SimpleTy) {
2022 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2024 RC = &PPC::GPRCRegClass;
2027 RC = &PPC::F4RCRegClass;
2030 RC = &PPC::F8RCRegClass;
2036 RC = &PPC::VRRCRegClass;
2040 // Transform the arguments stored in physical registers into virtual ones.
2041 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2042 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT);
2044 InVals.push_back(ArgValue);
2046 // Argument stored in memory.
2047 assert(VA.isMemLoc());
2049 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
2050 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2053 // Create load nodes to retrieve arguments from the stack.
2054 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2055 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2056 MachinePointerInfo(),
2057 false, false, false, 0));
2061 // Assign locations to all of the incoming aggregate by value arguments.
2062 // Aggregates passed by value are stored in the local variable space of the
2063 // caller's stack frame, right above the parameter list area.
2064 SmallVector<CCValAssign, 16> ByValArgLocs;
2065 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2066 getTargetMachine(), ByValArgLocs, *DAG.getContext());
2068 // Reserve stack space for the allocations in CCInfo.
2069 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2071 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2073 // Area that is at least reserved in the caller of this function.
2074 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2076 // Set the size that is at least reserved in caller of this function. Tail
2077 // call optimized function's reserved stack space needs to be aligned so that
2078 // taking the difference between two stack areas will result in an aligned
2080 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2083 std::max(MinReservedArea,
2084 PPCFrameLowering::getMinCallFrameSize(false, false));
2086 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
2087 getStackAlignment();
2088 unsigned AlignMask = TargetAlign-1;
2089 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2091 FI->setMinReservedArea(MinReservedArea);
2093 SmallVector<SDValue, 8> MemOps;
2095 // If the function takes variable number of arguments, make a frame index for
2096 // the start of the first vararg value... for expansion of llvm.va_start.
2098 static const uint16_t GPArgRegs[] = {
2099 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2100 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2102 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2104 static const uint16_t FPArgRegs[] = {
2105 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2108 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2110 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2112 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2115 // Make room for NumGPArgRegs and NumFPArgRegs.
2116 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2117 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
2119 FuncInfo->setVarArgsStackOffset(
2120 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2121 CCInfo.getNextStackOffset(), true));
2123 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2124 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2126 // The fixed integer arguments of a variadic function are stored to the
2127 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2128 // the result of va_next.
2129 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2130 // Get an existing live-in vreg, or add a new one.
2131 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2133 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2135 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2136 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2137 MachinePointerInfo(), false, false, 0);
2138 MemOps.push_back(Store);
2139 // Increment the address by four for the next argument to store
2140 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2141 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2144 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2146 // The double arguments are stored to the VarArgsFrameIndex
2148 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2149 // Get an existing live-in vreg, or add a new one.
2150 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2152 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2154 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2155 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2156 MachinePointerInfo(), false, false, 0);
2157 MemOps.push_back(Store);
2158 // Increment the address by eight for the next argument to store
2159 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
2161 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2165 if (!MemOps.empty())
2166 Chain = DAG.getNode(ISD::TokenFactor, dl,
2167 MVT::Other, &MemOps[0], MemOps.size());
2172 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2173 // value to MVT::i64 and then truncate to the correct register size.
2175 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2176 SelectionDAG &DAG, SDValue ArgVal,
2179 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2180 DAG.getValueType(ObjectVT));
2181 else if (Flags.isZExt())
2182 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2183 DAG.getValueType(ObjectVT));
2185 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2188 // Set the size that is at least reserved in caller of this function. Tail
2189 // call optimized functions' reserved stack space needs to be aligned so that
2190 // taking the difference between two stack areas will result in an aligned
2193 PPCTargetLowering::setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG,
2194 unsigned nAltivecParamsAtEnd,
2195 unsigned MinReservedArea,
2196 bool isPPC64) const {
2197 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2198 // Add the Altivec parameters at the end, if needed.
2199 if (nAltivecParamsAtEnd) {
2200 MinReservedArea = ((MinReservedArea+15)/16)*16;
2201 MinReservedArea += 16*nAltivecParamsAtEnd;
2204 std::max(MinReservedArea,
2205 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2206 unsigned TargetAlign
2207 = DAG.getMachineFunction().getTarget().getFrameLowering()->
2208 getStackAlignment();
2209 unsigned AlignMask = TargetAlign-1;
2210 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2211 FI->setMinReservedArea(MinReservedArea);
2215 PPCTargetLowering::LowerFormalArguments_64SVR4(
2217 CallingConv::ID CallConv, bool isVarArg,
2218 const SmallVectorImpl<ISD::InputArg>
2220 SDLoc dl, SelectionDAG &DAG,
2221 SmallVectorImpl<SDValue> &InVals) const {
2222 // TODO: add description of PPC stack frame format, or at least some docs.
2224 MachineFunction &MF = DAG.getMachineFunction();
2225 MachineFrameInfo *MFI = MF.getFrameInfo();
2226 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2228 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2229 // Potential tail calls could cause overwriting of argument stack slots.
2230 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2231 (CallConv == CallingConv::Fast));
2232 unsigned PtrByteSize = 8;
2234 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
2235 // Area that is at least reserved in caller of this function.
2236 unsigned MinReservedArea = ArgOffset;
2238 static const uint16_t GPR[] = {
2239 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2240 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2243 static const uint16_t *FPR = GetFPR();
2245 static const uint16_t VR[] = {
2246 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2247 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2250 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2251 const unsigned Num_FPR_Regs = 13;
2252 const unsigned Num_VR_Regs = array_lengthof(VR);
2254 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2256 // Add DAG nodes to load the arguments or copy them out of registers. On
2257 // entry to a function on PPC, the arguments start after the linkage area,
2258 // although the first ones are often in registers.
2260 SmallVector<SDValue, 8> MemOps;
2261 unsigned nAltivecParamsAtEnd = 0;
2262 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2263 unsigned CurArgIdx = 0;
2264 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2266 bool needsLoad = false;
2267 EVT ObjectVT = Ins[ArgNo].VT;
2268 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2269 unsigned ArgSize = ObjSize;
2270 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2271 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2272 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2274 unsigned CurArgOffset = ArgOffset;
2276 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2277 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2278 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2280 MinReservedArea = ((MinReservedArea+15)/16)*16;
2281 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2285 nAltivecParamsAtEnd++;
2287 // Calculate min reserved area.
2288 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2292 // FIXME the codegen can be much improved in some cases.
2293 // We do not have to keep everything in memory.
2294 if (Flags.isByVal()) {
2295 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2296 ObjSize = Flags.getByValSize();
2297 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2298 // Empty aggregate parameters do not take up registers. Examples:
2302 // etc. However, we have to provide a place-holder in InVals, so
2303 // pretend we have an 8-byte item at the current address for that
2306 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2307 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2308 InVals.push_back(FIN);
2312 unsigned BVAlign = Flags.getByValAlign();
2314 ArgOffset = ((ArgOffset+BVAlign-1)/BVAlign)*BVAlign;
2315 CurArgOffset = ArgOffset;
2318 // All aggregates smaller than 8 bytes must be passed right-justified.
2319 if (ObjSize < PtrByteSize)
2320 CurArgOffset = CurArgOffset + (PtrByteSize - ObjSize);
2321 // The value of the object is its address.
2322 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2323 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2324 InVals.push_back(FIN);
2327 if (GPR_idx != Num_GPR_Regs) {
2328 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2329 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2332 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2333 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2334 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2335 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2336 MachinePointerInfo(FuncArg, CurArgOffset),
2337 ObjType, false, false, 0);
2339 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2340 // store the whole register as-is to the parameter save area
2341 // slot. The address of the parameter was already calculated
2342 // above (InVals.push_back(FIN)) to be the right-justified
2343 // offset within the slot. For this store, we need a new
2344 // frame index that points at the beginning of the slot.
2345 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2346 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2347 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2348 MachinePointerInfo(FuncArg, ArgOffset),
2352 MemOps.push_back(Store);
2355 // Whether we copied from a register or not, advance the offset
2356 // into the parameter save area by a full doubleword.
2357 ArgOffset += PtrByteSize;
2361 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2362 // Store whatever pieces of the object are in registers
2363 // to memory. ArgOffset will be the address of the beginning
2365 if (GPR_idx != Num_GPR_Regs) {
2367 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2368 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2369 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2370 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2371 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2372 MachinePointerInfo(FuncArg, ArgOffset),
2374 MemOps.push_back(Store);
2376 ArgOffset += PtrByteSize;
2378 ArgOffset += ArgSize - j;
2385 switch (ObjectVT.getSimpleVT().SimpleTy) {
2386 default: llvm_unreachable("Unhandled argument type!");
2389 if (GPR_idx != Num_GPR_Regs) {
2390 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2391 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2393 if (ObjectVT == MVT::i32)
2394 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2395 // value to MVT::i64 and then truncate to the correct register size.
2396 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2401 ArgSize = PtrByteSize;
2408 // Every 8 bytes of argument space consumes one of the GPRs available for
2409 // argument passing.
2410 if (GPR_idx != Num_GPR_Regs) {
2413 if (FPR_idx != Num_FPR_Regs) {
2416 if (ObjectVT == MVT::f32)
2417 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2419 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2421 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2425 ArgSize = PtrByteSize;
2434 // Note that vector arguments in registers don't reserve stack space,
2435 // except in varargs functions.
2436 if (VR_idx != Num_VR_Regs) {
2437 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2438 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2440 while ((ArgOffset % 16) != 0) {
2441 ArgOffset += PtrByteSize;
2442 if (GPR_idx != Num_GPR_Regs)
2446 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2450 // Vectors are aligned.
2451 ArgOffset = ((ArgOffset+15)/16)*16;
2452 CurArgOffset = ArgOffset;
2459 // We need to load the argument to a virtual register if we determined
2460 // above that we ran out of physical registers of the appropriate type.
2462 int FI = MFI->CreateFixedObject(ObjSize,
2463 CurArgOffset + (ArgSize - ObjSize),
2465 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2466 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2467 false, false, false, 0);
2470 InVals.push_back(ArgVal);
2473 // Set the size that is at least reserved in caller of this function. Tail
2474 // call optimized functions' reserved stack space needs to be aligned so that
2475 // taking the difference between two stack areas will result in an aligned
2477 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, true);
2479 // If the function takes variable number of arguments, make a frame index for
2480 // the start of the first vararg value... for expansion of llvm.va_start.
2482 int Depth = ArgOffset;
2484 FuncInfo->setVarArgsFrameIndex(
2485 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2486 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2488 // If this function is vararg, store any remaining integer argument regs
2489 // to their spots on the stack so that they may be loaded by deferencing the
2490 // result of va_next.
2491 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2492 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2493 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2494 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2495 MachinePointerInfo(), false, false, 0);
2496 MemOps.push_back(Store);
2497 // Increment the address by four for the next argument to store
2498 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2499 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2503 if (!MemOps.empty())
2504 Chain = DAG.getNode(ISD::TokenFactor, dl,
2505 MVT::Other, &MemOps[0], MemOps.size());
2511 PPCTargetLowering::LowerFormalArguments_Darwin(
2513 CallingConv::ID CallConv, bool isVarArg,
2514 const SmallVectorImpl<ISD::InputArg>
2516 SDLoc dl, SelectionDAG &DAG,
2517 SmallVectorImpl<SDValue> &InVals) const {
2518 // TODO: add description of PPC stack frame format, or at least some docs.
2520 MachineFunction &MF = DAG.getMachineFunction();
2521 MachineFrameInfo *MFI = MF.getFrameInfo();
2522 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2524 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2525 bool isPPC64 = PtrVT == MVT::i64;
2526 // Potential tail calls could cause overwriting of argument stack slots.
2527 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2528 (CallConv == CallingConv::Fast));
2529 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2531 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
2532 // Area that is at least reserved in caller of this function.
2533 unsigned MinReservedArea = ArgOffset;
2535 static const uint16_t GPR_32[] = { // 32-bit registers.
2536 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2537 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2539 static const uint16_t GPR_64[] = { // 64-bit registers.
2540 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2541 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2544 static const uint16_t *FPR = GetFPR();
2546 static const uint16_t VR[] = {
2547 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2548 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2551 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2552 const unsigned Num_FPR_Regs = 13;
2553 const unsigned Num_VR_Regs = array_lengthof( VR);
2555 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2557 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
2559 // In 32-bit non-varargs functions, the stack space for vectors is after the
2560 // stack space for non-vectors. We do not use this space unless we have
2561 // too many vectors to fit in registers, something that only occurs in
2562 // constructed examples:), but we have to walk the arglist to figure
2563 // that out...for the pathological case, compute VecArgOffset as the
2564 // start of the vector parameter area. Computing VecArgOffset is the
2565 // entire point of the following loop.
2566 unsigned VecArgOffset = ArgOffset;
2567 if (!isVarArg && !isPPC64) {
2568 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
2570 EVT ObjectVT = Ins[ArgNo].VT;
2571 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2573 if (Flags.isByVal()) {
2574 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
2575 unsigned ObjSize = Flags.getByValSize();
2577 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2578 VecArgOffset += ArgSize;
2582 switch(ObjectVT.getSimpleVT().SimpleTy) {
2583 default: llvm_unreachable("Unhandled argument type!");
2588 case MVT::i64: // PPC64
2590 // FIXME: We are guaranteed to be !isPPC64 at this point.
2591 // Does MVT::i64 apply?
2598 // Nothing to do, we're only looking at Nonvector args here.
2603 // We've found where the vector parameter area in memory is. Skip the
2604 // first 12 parameters; these don't use that memory.
2605 VecArgOffset = ((VecArgOffset+15)/16)*16;
2606 VecArgOffset += 12*16;
2608 // Add DAG nodes to load the arguments or copy them out of registers. On
2609 // entry to a function on PPC, the arguments start after the linkage area,
2610 // although the first ones are often in registers.
2612 SmallVector<SDValue, 8> MemOps;
2613 unsigned nAltivecParamsAtEnd = 0;
2614 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2615 unsigned CurArgIdx = 0;
2616 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2618 bool needsLoad = false;
2619 EVT ObjectVT = Ins[ArgNo].VT;
2620 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2621 unsigned ArgSize = ObjSize;
2622 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2623 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2624 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2626 unsigned CurArgOffset = ArgOffset;
2628 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2629 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2630 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2631 if (isVarArg || isPPC64) {
2632 MinReservedArea = ((MinReservedArea+15)/16)*16;
2633 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2636 } else nAltivecParamsAtEnd++;
2638 // Calculate min reserved area.
2639 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2643 // FIXME the codegen can be much improved in some cases.
2644 // We do not have to keep everything in memory.
2645 if (Flags.isByVal()) {
2646 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2647 ObjSize = Flags.getByValSize();
2648 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2649 // Objects of size 1 and 2 are right justified, everything else is
2650 // left justified. This means the memory address is adjusted forwards.
2651 if (ObjSize==1 || ObjSize==2) {
2652 CurArgOffset = CurArgOffset + (4 - ObjSize);
2654 // The value of the object is its address.
2655 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2656 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2657 InVals.push_back(FIN);
2658 if (ObjSize==1 || ObjSize==2) {
2659 if (GPR_idx != Num_GPR_Regs) {
2662 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2664 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2665 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2666 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
2667 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2668 MachinePointerInfo(FuncArg,
2670 ObjType, false, false, 0);
2671 MemOps.push_back(Store);
2675 ArgOffset += PtrByteSize;
2679 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2680 // Store whatever pieces of the object are in registers
2681 // to memory. ArgOffset will be the address of the beginning
2683 if (GPR_idx != Num_GPR_Regs) {
2686 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2688 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2689 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2690 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2691 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2692 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2693 MachinePointerInfo(FuncArg, ArgOffset),
2695 MemOps.push_back(Store);
2697 ArgOffset += PtrByteSize;
2699 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
2706 switch (ObjectVT.getSimpleVT().SimpleTy) {
2707 default: llvm_unreachable("Unhandled argument type!");
2710 if (GPR_idx != Num_GPR_Regs) {
2711 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2712 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2716 ArgSize = PtrByteSize;
2718 // All int arguments reserve stack space in the Darwin ABI.
2719 ArgOffset += PtrByteSize;
2723 case MVT::i64: // PPC64
2724 if (GPR_idx != Num_GPR_Regs) {
2725 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2726 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2728 if (ObjectVT == MVT::i32)
2729 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2730 // value to MVT::i64 and then truncate to the correct register size.
2731 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2736 ArgSize = PtrByteSize;
2738 // All int arguments reserve stack space in the Darwin ABI.
2744 // Every 4 bytes of argument space consumes one of the GPRs available for
2745 // argument passing.
2746 if (GPR_idx != Num_GPR_Regs) {
2748 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
2751 if (FPR_idx != Num_FPR_Regs) {
2754 if (ObjectVT == MVT::f32)
2755 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2757 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2759 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2765 // All FP arguments reserve stack space in the Darwin ABI.
2766 ArgOffset += isPPC64 ? 8 : ObjSize;
2772 // Note that vector arguments in registers don't reserve stack space,
2773 // except in varargs functions.
2774 if (VR_idx != Num_VR_Regs) {
2775 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2776 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2778 while ((ArgOffset % 16) != 0) {
2779 ArgOffset += PtrByteSize;
2780 if (GPR_idx != Num_GPR_Regs)
2784 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2788 if (!isVarArg && !isPPC64) {
2789 // Vectors go after all the nonvectors.
2790 CurArgOffset = VecArgOffset;
2793 // Vectors are aligned.
2794 ArgOffset = ((ArgOffset+15)/16)*16;
2795 CurArgOffset = ArgOffset;
2803 // We need to load the argument to a virtual register if we determined above
2804 // that we ran out of physical registers of the appropriate type.
2806 int FI = MFI->CreateFixedObject(ObjSize,
2807 CurArgOffset + (ArgSize - ObjSize),
2809 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2810 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2811 false, false, false, 0);
2814 InVals.push_back(ArgVal);
2817 // Set the size that is at least reserved in caller of this function. Tail
2818 // call optimized functions' reserved stack space needs to be aligned so that
2819 // taking the difference between two stack areas will result in an aligned
2821 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, isPPC64);
2823 // If the function takes variable number of arguments, make a frame index for
2824 // the start of the first vararg value... for expansion of llvm.va_start.
2826 int Depth = ArgOffset;
2828 FuncInfo->setVarArgsFrameIndex(
2829 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2831 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2833 // If this function is vararg, store any remaining integer argument regs
2834 // to their spots on the stack so that they may be loaded by deferencing the
2835 // result of va_next.
2836 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2840 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2842 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2844 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2845 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2846 MachinePointerInfo(), false, false, 0);
2847 MemOps.push_back(Store);
2848 // Increment the address by four for the next argument to store
2849 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2850 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2854 if (!MemOps.empty())
2855 Chain = DAG.getNode(ISD::TokenFactor, dl,
2856 MVT::Other, &MemOps[0], MemOps.size());
2861 /// CalculateParameterAndLinkageAreaSize - Get the size of the parameter plus
2862 /// linkage area for the Darwin ABI, or the 64-bit SVR4 ABI.
2864 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
2868 const SmallVectorImpl<ISD::OutputArg>
2870 const SmallVectorImpl<SDValue> &OutVals,
2871 unsigned &nAltivecParamsAtEnd) {
2872 // Count how many bytes are to be pushed on the stack, including the linkage
2873 // area, and parameter passing area. We start with 24/48 bytes, which is
2874 // prereserved space for [SP][CR][LR][3 x unused].
2875 unsigned NumBytes = PPCFrameLowering::getLinkageSize(isPPC64, true);
2876 unsigned NumOps = Outs.size();
2877 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2879 // Add up all the space actually used.
2880 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
2881 // they all go in registers, but we must reserve stack space for them for
2882 // possible use by the caller. In varargs or 64-bit calls, parameters are
2883 // assigned stack space in order, with padding so Altivec parameters are
2885 nAltivecParamsAtEnd = 0;
2886 for (unsigned i = 0; i != NumOps; ++i) {
2887 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2888 EVT ArgVT = Outs[i].VT;
2889 // Varargs Altivec parameters are padded to a 16 byte boundary.
2890 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
2891 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
2892 if (!isVarArg && !isPPC64) {
2893 // Non-varargs Altivec parameters go after all the non-Altivec
2894 // parameters; handle those later so we know how much padding we need.
2895 nAltivecParamsAtEnd++;
2898 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
2899 NumBytes = ((NumBytes+15)/16)*16;
2901 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2904 // Allow for Altivec parameters at the end, if needed.
2905 if (nAltivecParamsAtEnd) {
2906 NumBytes = ((NumBytes+15)/16)*16;
2907 NumBytes += 16*nAltivecParamsAtEnd;
2910 // The prolog code of the callee may store up to 8 GPR argument registers to
2911 // the stack, allowing va_start to index over them in memory if its varargs.
2912 // Because we cannot tell if this is needed on the caller side, we have to
2913 // conservatively assume that it is needed. As such, make sure we have at
2914 // least enough stack space for the caller to store the 8 GPRs.
2915 NumBytes = std::max(NumBytes,
2916 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2918 // Tail call needs the stack to be aligned.
2919 if (CC == CallingConv::Fast && DAG.getTarget().Options.GuaranteedTailCallOpt){
2920 unsigned TargetAlign = DAG.getMachineFunction().getTarget().
2921 getFrameLowering()->getStackAlignment();
2922 unsigned AlignMask = TargetAlign-1;
2923 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2929 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
2930 /// adjusted to accommodate the arguments for the tailcall.
2931 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
2932 unsigned ParamSize) {
2934 if (!isTailCall) return 0;
2936 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
2937 unsigned CallerMinReservedArea = FI->getMinReservedArea();
2938 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
2939 // Remember only if the new adjustement is bigger.
2940 if (SPDiff < FI->getTailCallSPDelta())
2941 FI->setTailCallSPDelta(SPDiff);
2946 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2947 /// for tail call optimization. Targets which want to do tail call
2948 /// optimization should implement this function.
2950 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2951 CallingConv::ID CalleeCC,
2953 const SmallVectorImpl<ISD::InputArg> &Ins,
2954 SelectionDAG& DAG) const {
2955 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
2958 // Variable argument functions are not supported.
2962 MachineFunction &MF = DAG.getMachineFunction();
2963 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
2964 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
2965 // Functions containing by val parameters are not supported.
2966 for (unsigned i = 0; i != Ins.size(); i++) {
2967 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2968 if (Flags.isByVal()) return false;
2971 // Non PIC/GOT tail calls are supported.
2972 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
2975 // At the moment we can only do local tail calls (in same module, hidden
2976 // or protected) if we are generating PIC.
2977 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2978 return G->getGlobal()->hasHiddenVisibility()
2979 || G->getGlobal()->hasProtectedVisibility();
2985 /// isCallCompatibleAddress - Return the immediate to use if the specified
2986 /// 32-bit value is representable in the immediate field of a BxA instruction.
2987 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
2988 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2991 int Addr = C->getZExtValue();
2992 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
2993 SignExtend32<26>(Addr) != Addr)
2994 return 0; // Top 6 bits have to be sext of immediate.
2996 return DAG.getConstant((int)C->getZExtValue() >> 2,
2997 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
3002 struct TailCallArgumentInfo {
3007 TailCallArgumentInfo() : FrameIdx(0) {}
3012 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3014 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3016 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3017 SmallVectorImpl<SDValue> &MemOpChains,
3019 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3020 SDValue Arg = TailCallArgs[i].Arg;
3021 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3022 int FI = TailCallArgs[i].FrameIdx;
3023 // Store relative to framepointer.
3024 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
3025 MachinePointerInfo::getFixedStack(FI),
3030 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3031 /// the appropriate stack slot for the tail call optimized function call.
3032 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3033 MachineFunction &MF,
3042 // Calculate the new stack slot for the return address.
3043 int SlotSize = isPPC64 ? 8 : 4;
3044 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
3046 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3047 NewRetAddrLoc, true);
3048 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3049 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3050 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3051 MachinePointerInfo::getFixedStack(NewRetAddr),
3054 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3055 // slot as the FP is never overwritten.
3058 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
3059 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3061 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3062 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3063 MachinePointerInfo::getFixedStack(NewFPIdx),
3070 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3071 /// the position of the argument.
3073 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3074 SDValue Arg, int SPDiff, unsigned ArgOffset,
3075 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3076 int Offset = ArgOffset + SPDiff;
3077 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3078 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3079 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3080 SDValue FIN = DAG.getFrameIndex(FI, VT);
3081 TailCallArgumentInfo Info;
3083 Info.FrameIdxOp = FIN;
3085 TailCallArguments.push_back(Info);
3088 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3089 /// stack slot. Returns the chain as result and the loaded frame pointers in
3090 /// LROpOut/FPOpout. Used when tail calling.
3091 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3099 // Load the LR and FP stack slot for later adjusting.
3100 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
3101 LROpOut = getReturnAddrFrameIndex(DAG);
3102 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3103 false, false, false, 0);
3104 Chain = SDValue(LROpOut.getNode(), 1);
3106 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3107 // slot as the FP is never overwritten.
3109 FPOpOut = getFramePointerFrameIndex(DAG);
3110 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3111 false, false, false, 0);
3112 Chain = SDValue(FPOpOut.getNode(), 1);
3118 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3119 /// by "Src" to address "Dst" of size "Size". Alignment information is
3120 /// specified by the specific parameter attribute. The copy will be passed as
3121 /// a byval function parameter.
3122 /// Sometimes what we are copying is the end of a larger object, the part that
3123 /// does not fit in registers.
3125 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3126 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3128 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3129 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3130 false, false, MachinePointerInfo(0),
3131 MachinePointerInfo(0));
3134 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3137 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3138 SDValue Arg, SDValue PtrOff, int SPDiff,
3139 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3140 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
3141 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
3143 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3148 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3150 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3151 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3152 DAG.getConstant(ArgOffset, PtrVT));
3154 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3155 MachinePointerInfo(), false, false, 0));
3156 // Calculate and remember argument location.
3157 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3162 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3163 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3164 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3165 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
3166 MachineFunction &MF = DAG.getMachineFunction();
3168 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3169 // might overwrite each other in case of tail call optimization.
3170 SmallVector<SDValue, 8> MemOpChains2;
3171 // Do not flag preceding copytoreg stuff together with the following stuff.
3173 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3175 if (!MemOpChains2.empty())
3176 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3177 &MemOpChains2[0], MemOpChains2.size());
3179 // Store the return address to the appropriate stack slot.
3180 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3181 isPPC64, isDarwinABI, dl);
3183 // Emit callseq_end just before tailcall node.
3184 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3185 DAG.getIntPtrConstant(0, true), InFlag, dl);
3186 InFlag = Chain.getValue(1);
3190 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3191 SDValue &Chain, SDLoc dl, int SPDiff, bool isTailCall,
3192 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
3193 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
3194 const PPCSubtarget &PPCSubTarget) {
3196 bool isPPC64 = PPCSubTarget.isPPC64();
3197 bool isSVR4ABI = PPCSubTarget.isSVR4ABI();
3199 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3200 NodeTys.push_back(MVT::Other); // Returns a chain
3201 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3203 unsigned CallOpc = PPCISD::CALL;
3205 bool needIndirectCall = true;
3206 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3207 // If this is an absolute destination address, use the munged value.
3208 Callee = SDValue(Dest, 0);
3209 needIndirectCall = false;
3212 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3213 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201
3214 // Use indirect calls for ALL functions calls in JIT mode, since the
3215 // far-call stubs may be outside relocation limits for a BL instruction.
3216 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
3217 unsigned OpFlags = 0;
3218 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3219 (PPCSubTarget.getTargetTriple().isMacOSX() &&
3220 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3221 (G->getGlobal()->isDeclaration() ||
3222 G->getGlobal()->isWeakForLinker())) {
3223 // PC-relative references to external symbols should go through $stub,
3224 // unless we're building with the leopard linker or later, which
3225 // automatically synthesizes these stubs.
3226 OpFlags = PPCII::MO_DARWIN_STUB;
3229 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3230 // every direct call is) turn it into a TargetGlobalAddress /
3231 // TargetExternalSymbol node so that legalize doesn't hack it.
3232 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3233 Callee.getValueType(),
3235 needIndirectCall = false;
3239 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3240 unsigned char OpFlags = 0;
3242 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3243 (PPCSubTarget.getTargetTriple().isMacOSX() &&
3244 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5))) {
3245 // PC-relative references to external symbols should go through $stub,
3246 // unless we're building with the leopard linker or later, which
3247 // automatically synthesizes these stubs.
3248 OpFlags = PPCII::MO_DARWIN_STUB;
3251 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3253 needIndirectCall = false;
3256 if (needIndirectCall) {
3257 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3258 // to do the call, we can't use PPCISD::CALL.
3259 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3261 if (isSVR4ABI && isPPC64) {
3262 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3263 // entry point, but to the function descriptor (the function entry point
3264 // address is part of the function descriptor though).
3265 // The function descriptor is a three doubleword structure with the
3266 // following fields: function entry point, TOC base address and
3267 // environment pointer.
3268 // Thus for a call through a function pointer, the following actions need
3270 // 1. Save the TOC of the caller in the TOC save area of its stack
3271 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3272 // 2. Load the address of the function entry point from the function
3274 // 3. Load the TOC of the callee from the function descriptor into r2.
3275 // 4. Load the environment pointer from the function descriptor into
3277 // 5. Branch to the function entry point address.
3278 // 6. On return of the callee, the TOC of the caller needs to be
3279 // restored (this is done in FinishCall()).
3281 // All those operations are flagged together to ensure that no other
3282 // operations can be scheduled in between. E.g. without flagging the
3283 // operations together, a TOC access in the caller could be scheduled
3284 // between the load of the callee TOC and the branch to the callee, which
3285 // results in the TOC access going through the TOC of the callee instead
3286 // of going through the TOC of the caller, which leads to incorrect code.
3288 // Load the address of the function entry point from the function
3290 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3291 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps,
3292 InFlag.getNode() ? 3 : 2);
3293 Chain = LoadFuncPtr.getValue(1);
3294 InFlag = LoadFuncPtr.getValue(2);
3296 // Load environment pointer into r11.
3297 // Offset of the environment pointer within the function descriptor.
3298 SDValue PtrOff = DAG.getIntPtrConstant(16);
3300 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3301 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
3303 Chain = LoadEnvPtr.getValue(1);
3304 InFlag = LoadEnvPtr.getValue(2);
3306 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3308 Chain = EnvVal.getValue(0);
3309 InFlag = EnvVal.getValue(1);
3311 // Load TOC of the callee into r2. We are using a target-specific load
3312 // with r2 hard coded, because the result of a target-independent load
3313 // would never go directly into r2, since r2 is a reserved register (which
3314 // prevents the register allocator from allocating it), resulting in an
3315 // additional register being allocated and an unnecessary move instruction
3317 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3318 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
3320 Chain = LoadTOCPtr.getValue(0);
3321 InFlag = LoadTOCPtr.getValue(1);
3323 MTCTROps[0] = Chain;
3324 MTCTROps[1] = LoadFuncPtr;
3325 MTCTROps[2] = InFlag;
3328 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps,
3329 2 + (InFlag.getNode() != 0));
3330 InFlag = Chain.getValue(1);
3333 NodeTys.push_back(MVT::Other);
3334 NodeTys.push_back(MVT::Glue);
3335 Ops.push_back(Chain);
3336 CallOpc = PPCISD::BCTRL;
3338 // Add use of X11 (holding environment pointer)
3339 if (isSVR4ABI && isPPC64)
3340 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3341 // Add CTR register as callee so a bctr can be emitted later.
3343 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3346 // If this is a direct call, pass the chain and the callee.
3347 if (Callee.getNode()) {
3348 Ops.push_back(Chain);
3349 Ops.push_back(Callee);
3351 // If this is a tail call add stack pointer delta.
3353 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3355 // Add argument registers to the end of the list so that they are known live
3357 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3358 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3359 RegsToPass[i].second.getValueType()));
3365 bool isLocalCall(const SDValue &Callee)
3367 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3368 return !G->getGlobal()->isDeclaration() &&
3369 !G->getGlobal()->isWeakForLinker();
3374 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3375 CallingConv::ID CallConv, bool isVarArg,
3376 const SmallVectorImpl<ISD::InputArg> &Ins,
3377 SDLoc dl, SelectionDAG &DAG,
3378 SmallVectorImpl<SDValue> &InVals) const {
3380 SmallVector<CCValAssign, 16> RVLocs;
3381 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3382 getTargetMachine(), RVLocs, *DAG.getContext());
3383 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3385 // Copy all of the result registers out of their specified physreg.
3386 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3387 CCValAssign &VA = RVLocs[i];
3388 assert(VA.isRegLoc() && "Can only return in registers!");
3390 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3391 VA.getLocReg(), VA.getLocVT(), InFlag);
3392 Chain = Val.getValue(1);
3393 InFlag = Val.getValue(2);
3395 switch (VA.getLocInfo()) {
3396 default: llvm_unreachable("Unknown loc info!");
3397 case CCValAssign::Full: break;
3398 case CCValAssign::AExt:
3399 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3401 case CCValAssign::ZExt:
3402 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3403 DAG.getValueType(VA.getValVT()));
3404 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3406 case CCValAssign::SExt:
3407 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3408 DAG.getValueType(VA.getValVT()));
3409 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3413 InVals.push_back(Val);
3420 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
3421 bool isTailCall, bool isVarArg,
3423 SmallVector<std::pair<unsigned, SDValue>, 8>
3425 SDValue InFlag, SDValue Chain,
3427 int SPDiff, unsigned NumBytes,
3428 const SmallVectorImpl<ISD::InputArg> &Ins,
3429 SmallVectorImpl<SDValue> &InVals) const {
3430 std::vector<EVT> NodeTys;
3431 SmallVector<SDValue, 8> Ops;
3432 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
3433 isTailCall, RegsToPass, Ops, NodeTys,
3436 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3437 if (isVarArg && PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64())
3438 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3440 // When performing tail call optimization the callee pops its arguments off
3441 // the stack. Account for this here so these bytes can be pushed back on in
3442 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3443 int BytesCalleePops =
3444 (CallConv == CallingConv::Fast &&
3445 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3447 // Add a register mask operand representing the call-preserved registers.
3448 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
3449 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3450 assert(Mask && "Missing call preserved mask for calling convention");
3451 Ops.push_back(DAG.getRegisterMask(Mask));
3453 if (InFlag.getNode())
3454 Ops.push_back(InFlag);
3458 assert(((Callee.getOpcode() == ISD::Register &&
3459 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3460 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3461 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3462 isa<ConstantSDNode>(Callee)) &&
3463 "Expecting an global address, external symbol, absolute value or register");
3465 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size());
3468 // Add a NOP immediately after the branch instruction when using the 64-bit
3469 // SVR4 ABI. At link time, if caller and callee are in a different module and
3470 // thus have a different TOC, the call will be replaced with a call to a stub
3471 // function which saves the current TOC, loads the TOC of the callee and
3472 // branches to the callee. The NOP will be replaced with a load instruction
3473 // which restores the TOC of the caller from the TOC save slot of the current
3474 // stack frame. If caller and callee belong to the same module (and have the
3475 // same TOC), the NOP will remain unchanged.
3477 bool needsTOCRestore = false;
3478 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) {
3479 if (CallOpc == PPCISD::BCTRL) {
3480 // This is a call through a function pointer.
3481 // Restore the caller TOC from the save area into R2.
3482 // See PrepareCall() for more information about calls through function
3483 // pointers in the 64-bit SVR4 ABI.
3484 // We are using a target-specific load with r2 hard coded, because the
3485 // result of a target-independent load would never go directly into r2,
3486 // since r2 is a reserved register (which prevents the register allocator
3487 // from allocating it), resulting in an additional register being
3488 // allocated and an unnecessary move instruction being generated.
3489 needsTOCRestore = true;
3490 } else if ((CallOpc == PPCISD::CALL) &&
3491 (!isLocalCall(Callee) ||
3492 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3493 // Otherwise insert NOP for non-local calls.
3494 CallOpc = PPCISD::CALL_NOP;
3498 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
3499 InFlag = Chain.getValue(1);
3501 if (needsTOCRestore) {
3502 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3503 Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag);
3504 InFlag = Chain.getValue(1);
3507 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3508 DAG.getIntPtrConstant(BytesCalleePops, true),
3511 InFlag = Chain.getValue(1);
3513 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3514 Ins, dl, DAG, InVals);
3518 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3519 SmallVectorImpl<SDValue> &InVals) const {
3520 SelectionDAG &DAG = CLI.DAG;
3522 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3523 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3524 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3525 SDValue Chain = CLI.Chain;
3526 SDValue Callee = CLI.Callee;
3527 bool &isTailCall = CLI.IsTailCall;
3528 CallingConv::ID CallConv = CLI.CallConv;
3529 bool isVarArg = CLI.IsVarArg;
3532 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3535 if (PPCSubTarget.isSVR4ABI()) {
3536 if (PPCSubTarget.isPPC64())
3537 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3538 isTailCall, Outs, OutVals, Ins,
3541 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3542 isTailCall, Outs, OutVals, Ins,
3546 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
3547 isTailCall, Outs, OutVals, Ins,
3552 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
3553 CallingConv::ID CallConv, bool isVarArg,
3555 const SmallVectorImpl<ISD::OutputArg> &Outs,
3556 const SmallVectorImpl<SDValue> &OutVals,
3557 const SmallVectorImpl<ISD::InputArg> &Ins,
3558 SDLoc dl, SelectionDAG &DAG,
3559 SmallVectorImpl<SDValue> &InVals) const {
3560 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
3561 // of the 32-bit SVR4 ABI stack frame layout.
3563 assert((CallConv == CallingConv::C ||
3564 CallConv == CallingConv::Fast) && "Unknown calling convention!");
3566 unsigned PtrByteSize = 4;
3568 MachineFunction &MF = DAG.getMachineFunction();
3570 // Mark this function as potentially containing a function that contains a
3571 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3572 // and restoring the callers stack pointer in this functions epilog. This is
3573 // done because by tail calling the called function might overwrite the value
3574 // in this function's (MF) stack pointer stack slot 0(SP).
3575 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3576 CallConv == CallingConv::Fast)
3577 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3579 // Count how many bytes are to be pushed on the stack, including the linkage
3580 // area, parameter list area and the part of the local variable space which
3581 // contains copies of aggregates which are passed by value.
3583 // Assign locations to all of the outgoing arguments.
3584 SmallVector<CCValAssign, 16> ArgLocs;
3585 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3586 getTargetMachine(), ArgLocs, *DAG.getContext());
3588 // Reserve space for the linkage area on the stack.
3589 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
3592 // Handle fixed and variable vector arguments differently.
3593 // Fixed vector arguments go into registers as long as registers are
3594 // available. Variable vector arguments always go into memory.
3595 unsigned NumArgs = Outs.size();
3597 for (unsigned i = 0; i != NumArgs; ++i) {
3598 MVT ArgVT = Outs[i].VT;
3599 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3602 if (Outs[i].IsFixed) {
3603 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
3606 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
3612 errs() << "Call operand #" << i << " has unhandled type "
3613 << EVT(ArgVT).getEVTString() << "\n";
3615 llvm_unreachable(0);
3619 // All arguments are treated the same.
3620 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
3623 // Assign locations to all of the outgoing aggregate by value arguments.
3624 SmallVector<CCValAssign, 16> ByValArgLocs;
3625 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3626 getTargetMachine(), ByValArgLocs, *DAG.getContext());
3628 // Reserve stack space for the allocations in CCInfo.
3629 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
3631 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
3633 // Size of the linkage area, parameter list area and the part of the local
3634 // space variable where copies of aggregates which are passed by value are
3636 unsigned NumBytes = CCByValInfo.getNextStackOffset();
3638 // Calculate by how many bytes the stack has to be adjusted in case of tail
3639 // call optimization.
3640 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3642 // Adjust the stack pointer for the new arguments...
3643 // These operations are automatically eliminated by the prolog/epilog pass
3644 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
3646 SDValue CallSeqStart = Chain;
3648 // Load the return address and frame pointer so it can be moved somewhere else
3651 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
3654 // Set up a copy of the stack pointer for use loading and storing any
3655 // arguments that may not fit in the registers available for argument
3657 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3659 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3660 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3661 SmallVector<SDValue, 8> MemOpChains;
3663 bool seenFloatArg = false;
3664 // Walk the register/memloc assignments, inserting copies/loads.
3665 for (unsigned i = 0, j = 0, e = ArgLocs.size();
3668 CCValAssign &VA = ArgLocs[i];
3669 SDValue Arg = OutVals[i];
3670 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3672 if (Flags.isByVal()) {
3673 // Argument is an aggregate which is passed by value, thus we need to
3674 // create a copy of it in the local variable space of the current stack
3675 // frame (which is the stack frame of the caller) and pass the address of
3676 // this copy to the callee.
3677 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
3678 CCValAssign &ByValVA = ByValArgLocs[j++];
3679 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
3681 // Memory reserved in the local variable space of the callers stack frame.
3682 unsigned LocMemOffset = ByValVA.getLocMemOffset();
3684 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3685 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3687 // Create a copy of the argument in the local area of the current
3689 SDValue MemcpyCall =
3690 CreateCopyOfByValArgument(Arg, PtrOff,
3691 CallSeqStart.getNode()->getOperand(0),
3694 // This must go outside the CALLSEQ_START..END.
3695 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3696 CallSeqStart.getNode()->getOperand(1),
3698 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3699 NewCallSeqStart.getNode());
3700 Chain = CallSeqStart = NewCallSeqStart;
3702 // Pass the address of the aggregate copy on the stack either in a
3703 // physical register or in the parameter list area of the current stack
3704 // frame to the callee.
3708 if (VA.isRegLoc()) {
3709 seenFloatArg |= VA.getLocVT().isFloatingPoint();
3710 // Put argument in a physical register.
3711 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3713 // Put argument in the parameter list area of the current stack frame.
3714 assert(VA.isMemLoc());
3715 unsigned LocMemOffset = VA.getLocMemOffset();
3718 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3719 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3721 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3722 MachinePointerInfo(),
3725 // Calculate and remember argument location.
3726 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
3732 if (!MemOpChains.empty())
3733 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3734 &MemOpChains[0], MemOpChains.size());
3736 // Build a sequence of copy-to-reg nodes chained together with token chain
3737 // and flag operands which copy the outgoing args into the appropriate regs.
3739 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3740 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3741 RegsToPass[i].second, InFlag);
3742 InFlag = Chain.getValue(1);
3745 // Set CR bit 6 to true if this is a vararg call with floating args passed in
3748 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3749 SDValue Ops[] = { Chain, InFlag };
3751 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
3752 dl, VTs, Ops, InFlag.getNode() ? 2 : 1);
3754 InFlag = Chain.getValue(1);
3758 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
3759 false, TailCallArguments);
3761 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3762 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3766 // Copy an argument into memory, being careful to do this outside the
3767 // call sequence for the call to which the argument belongs.
3769 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
3770 SDValue CallSeqStart,
3771 ISD::ArgFlagsTy Flags,
3774 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
3775 CallSeqStart.getNode()->getOperand(0),
3777 // The MEMCPY must go outside the CALLSEQ_START..END.
3778 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3779 CallSeqStart.getNode()->getOperand(1),
3781 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3782 NewCallSeqStart.getNode());
3783 return NewCallSeqStart;
3787 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
3788 CallingConv::ID CallConv, bool isVarArg,
3790 const SmallVectorImpl<ISD::OutputArg> &Outs,
3791 const SmallVectorImpl<SDValue> &OutVals,
3792 const SmallVectorImpl<ISD::InputArg> &Ins,
3793 SDLoc dl, SelectionDAG &DAG,
3794 SmallVectorImpl<SDValue> &InVals) const {
3796 unsigned NumOps = Outs.size();
3798 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3799 unsigned PtrByteSize = 8;
3801 MachineFunction &MF = DAG.getMachineFunction();
3803 // Mark this function as potentially containing a function that contains a
3804 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3805 // and restoring the callers stack pointer in this functions epilog. This is
3806 // done because by tail calling the called function might overwrite the value
3807 // in this function's (MF) stack pointer stack slot 0(SP).
3808 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3809 CallConv == CallingConv::Fast)
3810 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3812 unsigned nAltivecParamsAtEnd = 0;
3814 // Count how many bytes are to be pushed on the stack, including the linkage
3815 // area, and parameter passing area. We start with at least 48 bytes, which
3816 // is reserved space for [SP][CR][LR][3 x unused].
3817 // NOTE: For PPC64, nAltivecParamsAtEnd always remains zero as a result
3820 CalculateParameterAndLinkageAreaSize(DAG, true, isVarArg, CallConv,
3821 Outs, OutVals, nAltivecParamsAtEnd);
3823 // Calculate by how many bytes the stack has to be adjusted in case of tail
3824 // call optimization.
3825 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3827 // To protect arguments on the stack from being clobbered in a tail call,
3828 // force all the loads to happen before doing any other lowering.
3830 Chain = DAG.getStackArgumentTokenFactor(Chain);
3832 // Adjust the stack pointer for the new arguments...
3833 // These operations are automatically eliminated by the prolog/epilog pass
3834 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
3836 SDValue CallSeqStart = Chain;
3838 // Load the return address and frame pointer so it can be move somewhere else
3841 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
3844 // Set up a copy of the stack pointer for use loading and storing any
3845 // arguments that may not fit in the registers available for argument
3847 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3849 // Figure out which arguments are going to go in registers, and which in
3850 // memory. Also, if this is a vararg function, floating point operations
3851 // must be stored to our stack, and loaded into integer regs as well, if
3852 // any integer regs are available for argument passing.
3853 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
3854 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3856 static const uint16_t GPR[] = {
3857 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3858 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3860 static const uint16_t *FPR = GetFPR();
3862 static const uint16_t VR[] = {
3863 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3864 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3866 const unsigned NumGPRs = array_lengthof(GPR);
3867 const unsigned NumFPRs = 13;
3868 const unsigned NumVRs = array_lengthof(VR);
3870 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3871 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3873 SmallVector<SDValue, 8> MemOpChains;
3874 for (unsigned i = 0; i != NumOps; ++i) {
3875 SDValue Arg = OutVals[i];
3876 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3878 // PtrOff will be used to store the current argument to the stack if a
3879 // register cannot be found for it.
3882 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
3884 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
3886 // Promote integers to 64-bit values.
3887 if (Arg.getValueType() == MVT::i32) {
3888 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
3889 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3890 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
3893 // FIXME memcpy is used way more than necessary. Correctness first.
3894 // Note: "by value" is code for passing a structure by value, not
3896 if (Flags.isByVal()) {
3897 // Note: Size includes alignment padding, so
3898 // struct x { short a; char b; }
3899 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
3900 // These are the proper values we need for right-justifying the
3901 // aggregate in a parameter register.
3902 unsigned Size = Flags.getByValSize();
3904 // An empty aggregate parameter takes up no storage and no
3909 unsigned BVAlign = Flags.getByValAlign();
3911 if (BVAlign % PtrByteSize != 0)
3913 "ByVal alignment is not a multiple of the pointer size");
3915 ArgOffset = ((ArgOffset+BVAlign-1)/BVAlign)*BVAlign;
3918 // All aggregates smaller than 8 bytes must be passed right-justified.
3919 if (Size==1 || Size==2 || Size==4) {
3920 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
3921 if (GPR_idx != NumGPRs) {
3922 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
3923 MachinePointerInfo(), VT,
3925 MemOpChains.push_back(Load.getValue(1));
3926 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3928 ArgOffset += PtrByteSize;
3933 if (GPR_idx == NumGPRs && Size < 8) {
3934 SDValue Const = DAG.getConstant(PtrByteSize - Size,
3935 PtrOff.getValueType());
3936 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3937 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
3940 ArgOffset += PtrByteSize;
3943 // Copy entire object into memory. There are cases where gcc-generated
3944 // code assumes it is there, even if it could be put entirely into
3945 // registers. (This is not what the doc says.)
3947 // FIXME: The above statement is likely due to a misunderstanding of the
3948 // documents. All arguments must be copied into the parameter area BY
3949 // THE CALLEE in the event that the callee takes the address of any
3950 // formal argument. That has not yet been implemented. However, it is
3951 // reasonable to use the stack area as a staging area for the register
3954 // Skip this for small aggregates, as we will use the same slot for a
3955 // right-justified copy, below.
3957 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
3961 // When a register is available, pass a small aggregate right-justified.
3962 if (Size < 8 && GPR_idx != NumGPRs) {
3963 // The easiest way to get this right-justified in a register
3964 // is to copy the structure into the rightmost portion of a
3965 // local variable slot, then load the whole slot into the
3967 // FIXME: The memcpy seems to produce pretty awful code for
3968 // small aggregates, particularly for packed ones.
3969 // FIXME: It would be preferable to use the slot in the
3970 // parameter save area instead of a new local variable.
3971 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
3972 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3973 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
3977 // Load the slot into the register.
3978 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
3979 MachinePointerInfo(),
3980 false, false, false, 0);
3981 MemOpChains.push_back(Load.getValue(1));
3982 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3984 // Done with this argument.
3985 ArgOffset += PtrByteSize;
3989 // For aggregates larger than PtrByteSize, copy the pieces of the
3990 // object that fit into registers from the parameter save area.
3991 for (unsigned j=0; j<Size; j+=PtrByteSize) {
3992 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
3993 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
3994 if (GPR_idx != NumGPRs) {
3995 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
3996 MachinePointerInfo(),
3997 false, false, false, 0);
3998 MemOpChains.push_back(Load.getValue(1));
3999 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4000 ArgOffset += PtrByteSize;
4002 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4009 switch (Arg.getSimpleValueType().SimpleTy) {
4010 default: llvm_unreachable("Unexpected ValueType for argument!");
4013 if (GPR_idx != NumGPRs) {
4014 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4016 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4017 true, isTailCall, false, MemOpChains,
4018 TailCallArguments, dl);
4020 ArgOffset += PtrByteSize;
4024 if (FPR_idx != NumFPRs) {
4025 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4028 // A single float or an aggregate containing only a single float
4029 // must be passed right-justified in the stack doubleword, and
4030 // in the GPR, if one is available.
4032 if (Arg.getSimpleValueType().SimpleTy == MVT::f32) {
4033 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4034 StoreOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4038 SDValue Store = DAG.getStore(Chain, dl, Arg, StoreOff,
4039 MachinePointerInfo(), false, false, 0);
4040 MemOpChains.push_back(Store);
4042 // Float varargs are always shadowed in available integer registers
4043 if (GPR_idx != NumGPRs) {
4044 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4045 MachinePointerInfo(), false, false,
4047 MemOpChains.push_back(Load.getValue(1));
4048 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4050 } else if (GPR_idx != NumGPRs)
4051 // If we have any FPRs remaining, we may also have GPRs remaining.
4054 // Single-precision floating-point values are mapped to the
4055 // second (rightmost) word of the stack doubleword.
4056 if (Arg.getValueType() == MVT::f32) {
4057 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4058 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4061 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4062 true, isTailCall, false, MemOpChains,
4063 TailCallArguments, dl);
4072 // These go aligned on the stack, or in the corresponding R registers
4073 // when within range. The Darwin PPC ABI doc claims they also go in
4074 // V registers; in fact gcc does this only for arguments that are
4075 // prototyped, not for those that match the ... We do it for all
4076 // arguments, seems to work.
4077 while (ArgOffset % 16 !=0) {
4078 ArgOffset += PtrByteSize;
4079 if (GPR_idx != NumGPRs)
4082 // We could elide this store in the case where the object fits
4083 // entirely in R registers. Maybe later.
4084 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4085 DAG.getConstant(ArgOffset, PtrVT));
4086 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4087 MachinePointerInfo(), false, false, 0);
4088 MemOpChains.push_back(Store);
4089 if (VR_idx != NumVRs) {
4090 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4091 MachinePointerInfo(),
4092 false, false, false, 0);
4093 MemOpChains.push_back(Load.getValue(1));
4094 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4097 for (unsigned i=0; i<16; i+=PtrByteSize) {
4098 if (GPR_idx == NumGPRs)
4100 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4101 DAG.getConstant(i, PtrVT));
4102 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4103 false, false, false, 0);
4104 MemOpChains.push_back(Load.getValue(1));
4105 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4110 // Non-varargs Altivec params generally go in registers, but have
4111 // stack space allocated at the end.
4112 if (VR_idx != NumVRs) {
4113 // Doesn't have GPR space allocated.
4114 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4116 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4117 true, isTailCall, true, MemOpChains,
4118 TailCallArguments, dl);
4125 if (!MemOpChains.empty())
4126 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4127 &MemOpChains[0], MemOpChains.size());
4129 // Check if this is an indirect call (MTCTR/BCTRL).
4130 // See PrepareCall() for more information about calls through function
4131 // pointers in the 64-bit SVR4 ABI.
4133 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4134 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4135 !isBLACompatibleAddress(Callee, DAG)) {
4136 // Load r2 into a virtual register and store it to the TOC save area.
4137 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4138 // TOC save area offset.
4139 SDValue PtrOff = DAG.getIntPtrConstant(40);
4140 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4141 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
4143 // R12 must contain the address of an indirect callee. This does not
4144 // mean the MTCTR instruction must use R12; it's easier to model this
4145 // as an extra parameter, so do that.
4146 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
4149 // Build a sequence of copy-to-reg nodes chained together with token chain
4150 // and flag operands which copy the outgoing args into the appropriate regs.
4152 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4153 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4154 RegsToPass[i].second, InFlag);
4155 InFlag = Chain.getValue(1);
4159 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4160 FPOp, true, TailCallArguments);
4162 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4163 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4168 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4169 CallingConv::ID CallConv, bool isVarArg,
4171 const SmallVectorImpl<ISD::OutputArg> &Outs,
4172 const SmallVectorImpl<SDValue> &OutVals,
4173 const SmallVectorImpl<ISD::InputArg> &Ins,
4174 SDLoc dl, SelectionDAG &DAG,
4175 SmallVectorImpl<SDValue> &InVals) const {
4177 unsigned NumOps = Outs.size();
4179 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4180 bool isPPC64 = PtrVT == MVT::i64;
4181 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4183 MachineFunction &MF = DAG.getMachineFunction();
4185 // Mark this function as potentially containing a function that contains a
4186 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4187 // and restoring the callers stack pointer in this functions epilog. This is
4188 // done because by tail calling the called function might overwrite the value
4189 // in this function's (MF) stack pointer stack slot 0(SP).
4190 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4191 CallConv == CallingConv::Fast)
4192 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4194 unsigned nAltivecParamsAtEnd = 0;
4196 // Count how many bytes are to be pushed on the stack, including the linkage
4197 // area, and parameter passing area. We start with 24/48 bytes, which is
4198 // prereserved space for [SP][CR][LR][3 x unused].
4200 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv,
4202 nAltivecParamsAtEnd);
4204 // Calculate by how many bytes the stack has to be adjusted in case of tail
4205 // call optimization.
4206 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4208 // To protect arguments on the stack from being clobbered in a tail call,
4209 // force all the loads to happen before doing any other lowering.
4211 Chain = DAG.getStackArgumentTokenFactor(Chain);
4213 // Adjust the stack pointer for the new arguments...
4214 // These operations are automatically eliminated by the prolog/epilog pass
4215 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4217 SDValue CallSeqStart = Chain;
4219 // Load the return address and frame pointer so it can be move somewhere else
4222 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4225 // Set up a copy of the stack pointer for use loading and storing any
4226 // arguments that may not fit in the registers available for argument
4230 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4232 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4234 // Figure out which arguments are going to go in registers, and which in
4235 // memory. Also, if this is a vararg function, floating point operations
4236 // must be stored to our stack, and loaded into integer regs as well, if
4237 // any integer regs are available for argument passing.
4238 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
4239 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4241 static const uint16_t GPR_32[] = { // 32-bit registers.
4242 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4243 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4245 static const uint16_t GPR_64[] = { // 64-bit registers.
4246 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4247 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4249 static const uint16_t *FPR = GetFPR();
4251 static const uint16_t VR[] = {
4252 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4253 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4255 const unsigned NumGPRs = array_lengthof(GPR_32);
4256 const unsigned NumFPRs = 13;
4257 const unsigned NumVRs = array_lengthof(VR);
4259 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
4261 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4262 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4264 SmallVector<SDValue, 8> MemOpChains;
4265 for (unsigned i = 0; i != NumOps; ++i) {
4266 SDValue Arg = OutVals[i];
4267 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4269 // PtrOff will be used to store the current argument to the stack if a
4270 // register cannot be found for it.
4273 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4275 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4277 // On PPC64, promote integers to 64-bit values.
4278 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4279 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4280 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4281 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4284 // FIXME memcpy is used way more than necessary. Correctness first.
4285 // Note: "by value" is code for passing a structure by value, not
4287 if (Flags.isByVal()) {
4288 unsigned Size = Flags.getByValSize();
4289 // Very small objects are passed right-justified. Everything else is
4290 // passed left-justified.
4291 if (Size==1 || Size==2) {
4292 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4293 if (GPR_idx != NumGPRs) {
4294 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4295 MachinePointerInfo(), VT,
4297 MemOpChains.push_back(Load.getValue(1));
4298 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4300 ArgOffset += PtrByteSize;
4302 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4303 PtrOff.getValueType());
4304 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4305 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4308 ArgOffset += PtrByteSize;
4312 // Copy entire object into memory. There are cases where gcc-generated
4313 // code assumes it is there, even if it could be put entirely into
4314 // registers. (This is not what the doc says.)
4315 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4319 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4320 // copy the pieces of the object that fit into registers from the
4321 // parameter save area.
4322 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4323 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4324 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4325 if (GPR_idx != NumGPRs) {
4326 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4327 MachinePointerInfo(),
4328 false, false, false, 0);
4329 MemOpChains.push_back(Load.getValue(1));
4330 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4331 ArgOffset += PtrByteSize;
4333 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4340 switch (Arg.getSimpleValueType().SimpleTy) {
4341 default: llvm_unreachable("Unexpected ValueType for argument!");
4344 if (GPR_idx != NumGPRs) {
4345 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4347 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4348 isPPC64, isTailCall, false, MemOpChains,
4349 TailCallArguments, dl);
4351 ArgOffset += PtrByteSize;
4355 if (FPR_idx != NumFPRs) {
4356 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4359 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4360 MachinePointerInfo(), false, false, 0);
4361 MemOpChains.push_back(Store);
4363 // Float varargs are always shadowed in available integer registers
4364 if (GPR_idx != NumGPRs) {
4365 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4366 MachinePointerInfo(), false, false,
4368 MemOpChains.push_back(Load.getValue(1));
4369 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4371 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4372 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4373 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4374 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4375 MachinePointerInfo(),
4376 false, false, false, 0);
4377 MemOpChains.push_back(Load.getValue(1));
4378 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4381 // If we have any FPRs remaining, we may also have GPRs remaining.
4382 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4384 if (GPR_idx != NumGPRs)
4386 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4387 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4391 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4392 isPPC64, isTailCall, false, MemOpChains,
4393 TailCallArguments, dl);
4397 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4404 // These go aligned on the stack, or in the corresponding R registers
4405 // when within range. The Darwin PPC ABI doc claims they also go in
4406 // V registers; in fact gcc does this only for arguments that are
4407 // prototyped, not for those that match the ... We do it for all
4408 // arguments, seems to work.
4409 while (ArgOffset % 16 !=0) {
4410 ArgOffset += PtrByteSize;
4411 if (GPR_idx != NumGPRs)
4414 // We could elide this store in the case where the object fits
4415 // entirely in R registers. Maybe later.
4416 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4417 DAG.getConstant(ArgOffset, PtrVT));
4418 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4419 MachinePointerInfo(), false, false, 0);
4420 MemOpChains.push_back(Store);
4421 if (VR_idx != NumVRs) {
4422 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4423 MachinePointerInfo(),
4424 false, false, false, 0);
4425 MemOpChains.push_back(Load.getValue(1));
4426 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4429 for (unsigned i=0; i<16; i+=PtrByteSize) {
4430 if (GPR_idx == NumGPRs)
4432 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4433 DAG.getConstant(i, PtrVT));
4434 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4435 false, false, false, 0);
4436 MemOpChains.push_back(Load.getValue(1));
4437 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4442 // Non-varargs Altivec params generally go in registers, but have
4443 // stack space allocated at the end.
4444 if (VR_idx != NumVRs) {
4445 // Doesn't have GPR space allocated.
4446 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4447 } else if (nAltivecParamsAtEnd==0) {
4448 // We are emitting Altivec params in order.
4449 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4450 isPPC64, isTailCall, true, MemOpChains,
4451 TailCallArguments, dl);
4457 // If all Altivec parameters fit in registers, as they usually do,
4458 // they get stack space following the non-Altivec parameters. We
4459 // don't track this here because nobody below needs it.
4460 // If there are more Altivec parameters than fit in registers emit
4462 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
4464 // Offset is aligned; skip 1st 12 params which go in V registers.
4465 ArgOffset = ((ArgOffset+15)/16)*16;
4467 for (unsigned i = 0; i != NumOps; ++i) {
4468 SDValue Arg = OutVals[i];
4469 EVT ArgType = Outs[i].VT;
4470 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
4471 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
4474 // We are emitting Altivec params in order.
4475 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4476 isPPC64, isTailCall, true, MemOpChains,
4477 TailCallArguments, dl);
4484 if (!MemOpChains.empty())
4485 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4486 &MemOpChains[0], MemOpChains.size());
4488 // On Darwin, R12 must contain the address of an indirect callee. This does
4489 // not mean the MTCTR instruction must use R12; it's easier to model this as
4490 // an extra parameter, so do that.
4492 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4493 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4494 !isBLACompatibleAddress(Callee, DAG))
4495 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
4496 PPC::R12), Callee));
4498 // Build a sequence of copy-to-reg nodes chained together with token chain
4499 // and flag operands which copy the outgoing args into the appropriate regs.
4501 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4502 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4503 RegsToPass[i].second, InFlag);
4504 InFlag = Chain.getValue(1);
4508 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
4509 FPOp, true, TailCallArguments);
4511 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4512 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4517 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
4518 MachineFunction &MF, bool isVarArg,
4519 const SmallVectorImpl<ISD::OutputArg> &Outs,
4520 LLVMContext &Context) const {
4521 SmallVector<CCValAssign, 16> RVLocs;
4522 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
4524 return CCInfo.CheckReturn(Outs, RetCC_PPC);
4528 PPCTargetLowering::LowerReturn(SDValue Chain,
4529 CallingConv::ID CallConv, bool isVarArg,
4530 const SmallVectorImpl<ISD::OutputArg> &Outs,
4531 const SmallVectorImpl<SDValue> &OutVals,
4532 SDLoc dl, SelectionDAG &DAG) const {
4534 SmallVector<CCValAssign, 16> RVLocs;
4535 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4536 getTargetMachine(), RVLocs, *DAG.getContext());
4537 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
4540 SmallVector<SDValue, 4> RetOps(1, Chain);
4542 // Copy the result values into the output registers.
4543 for (unsigned i = 0; i != RVLocs.size(); ++i) {
4544 CCValAssign &VA = RVLocs[i];
4545 assert(VA.isRegLoc() && "Can only return in registers!");
4547 SDValue Arg = OutVals[i];
4549 switch (VA.getLocInfo()) {
4550 default: llvm_unreachable("Unknown loc info!");
4551 case CCValAssign::Full: break;
4552 case CCValAssign::AExt:
4553 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
4555 case CCValAssign::ZExt:
4556 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
4558 case CCValAssign::SExt:
4559 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
4563 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
4564 Flag = Chain.getValue(1);
4565 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
4568 RetOps[0] = Chain; // Update chain.
4570 // Add the flag if we have it.
4572 RetOps.push_back(Flag);
4574 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other,
4575 &RetOps[0], RetOps.size());
4578 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
4579 const PPCSubtarget &Subtarget) const {
4580 // When we pop the dynamic allocation we need to restore the SP link.
4583 // Get the corect type for pointers.
4584 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4586 // Construct the stack pointer operand.
4587 bool isPPC64 = Subtarget.isPPC64();
4588 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
4589 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
4591 // Get the operands for the STACKRESTORE.
4592 SDValue Chain = Op.getOperand(0);
4593 SDValue SaveSP = Op.getOperand(1);
4595 // Load the old link SP.
4596 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
4597 MachinePointerInfo(),
4598 false, false, false, 0);
4600 // Restore the stack pointer.
4601 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
4603 // Store the old link SP.
4604 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
4611 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
4612 MachineFunction &MF = DAG.getMachineFunction();
4613 bool isPPC64 = PPCSubTarget.isPPC64();
4614 bool isDarwinABI = PPCSubTarget.isDarwinABI();
4615 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4617 // Get current frame pointer save index. The users of this index will be
4618 // primarily DYNALLOC instructions.
4619 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4620 int RASI = FI->getReturnAddrSaveIndex();
4622 // If the frame pointer save index hasn't been defined yet.
4624 // Find out what the fix offset of the frame pointer save area.
4625 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
4626 // Allocate the frame index for frame pointer save area.
4627 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
4629 FI->setReturnAddrSaveIndex(RASI);
4631 return DAG.getFrameIndex(RASI, PtrVT);
4635 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
4636 MachineFunction &MF = DAG.getMachineFunction();
4637 bool isPPC64 = PPCSubTarget.isPPC64();
4638 bool isDarwinABI = PPCSubTarget.isDarwinABI();
4639 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4641 // Get current frame pointer save index. The users of this index will be
4642 // primarily DYNALLOC instructions.
4643 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4644 int FPSI = FI->getFramePointerSaveIndex();
4646 // If the frame pointer save index hasn't been defined yet.
4648 // Find out what the fix offset of the frame pointer save area.
4649 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
4652 // Allocate the frame index for frame pointer save area.
4653 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
4655 FI->setFramePointerSaveIndex(FPSI);
4657 return DAG.getFrameIndex(FPSI, PtrVT);
4660 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
4662 const PPCSubtarget &Subtarget) const {
4664 SDValue Chain = Op.getOperand(0);
4665 SDValue Size = Op.getOperand(1);
4668 // Get the corect type for pointers.
4669 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4671 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
4672 DAG.getConstant(0, PtrVT), Size);
4673 // Construct a node for the frame pointer save index.
4674 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
4675 // Build a DYNALLOC node.
4676 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
4677 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
4678 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3);
4681 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
4682 SelectionDAG &DAG) const {
4684 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
4685 DAG.getVTList(MVT::i32, MVT::Other),
4686 Op.getOperand(0), Op.getOperand(1));
4689 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
4690 SelectionDAG &DAG) const {
4692 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
4693 Op.getOperand(0), Op.getOperand(1));
4696 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
4698 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
4699 // Not FP? Not a fsel.
4700 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
4701 !Op.getOperand(2).getValueType().isFloatingPoint())
4704 // We might be able to do better than this under some circumstances, but in
4705 // general, fsel-based lowering of select is a finite-math-only optimization.
4706 // For more information, see section F.3 of the 2.06 ISA specification.
4707 if (!DAG.getTarget().Options.NoInfsFPMath ||
4708 !DAG.getTarget().Options.NoNaNsFPMath)
4711 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4713 EVT ResVT = Op.getValueType();
4714 EVT CmpVT = Op.getOperand(0).getValueType();
4715 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4716 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
4719 // If the RHS of the comparison is a 0.0, we don't need to do the
4720 // subtraction at all.
4722 if (isFloatingPointZero(RHS))
4724 default: break; // SETUO etc aren't handled by fsel.
4728 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4729 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4730 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
4731 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
4732 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
4733 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4734 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
4737 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
4740 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4741 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4742 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
4745 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
4748 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4749 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4750 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4751 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
4756 default: break; // SETUO etc aren't handled by fsel.
4760 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4761 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4762 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4763 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4764 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
4765 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
4766 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4767 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
4770 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4771 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4772 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4773 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
4776 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4777 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4778 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4779 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4782 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
4783 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4784 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4785 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
4788 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
4789 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4790 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4791 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4796 // FIXME: Split this code up when LegalizeDAGTypes lands.
4797 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
4799 assert(Op.getOperand(0).getValueType().isFloatingPoint());
4800 SDValue Src = Op.getOperand(0);
4801 if (Src.getValueType() == MVT::f32)
4802 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
4805 switch (Op.getSimpleValueType().SimpleTy) {
4806 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
4808 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
4809 (PPCSubTarget.hasFPCVT() ? PPCISD::FCTIWUZ :
4814 assert((Op.getOpcode() == ISD::FP_TO_SINT || PPCSubTarget.hasFPCVT()) &&
4815 "i64 FP_TO_UINT is supported only with FPCVT");
4816 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
4822 // Convert the FP value to an int value through memory.
4823 bool i32Stack = Op.getValueType() == MVT::i32 && PPCSubTarget.hasSTFIWX() &&
4824 (Op.getOpcode() == ISD::FP_TO_SINT || PPCSubTarget.hasFPCVT());
4825 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
4826 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
4827 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
4829 // Emit a store to the stack slot.
4832 MachineFunction &MF = DAG.getMachineFunction();
4833 MachineMemOperand *MMO =
4834 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
4835 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
4836 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
4837 DAG.getVTList(MVT::Other), Ops, array_lengthof(Ops),
4840 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
4841 MPI, false, false, 0);
4843 // Result is a load from the stack slot. If loading 4 bytes, make sure to
4845 if (Op.getValueType() == MVT::i32 && !i32Stack) {
4846 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
4847 DAG.getConstant(4, FIPtr.getValueType()));
4848 MPI = MachinePointerInfo();
4851 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MPI,
4852 false, false, false, 0);
4855 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
4856 SelectionDAG &DAG) const {
4858 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
4859 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
4862 assert((Op.getOpcode() == ISD::SINT_TO_FP || PPCSubTarget.hasFPCVT()) &&
4863 "UINT_TO_FP is supported only with FPCVT");
4865 // If we have FCFIDS, then use it when converting to single-precision.
4866 // Otherwise, convert to double-precision and then round.
4867 unsigned FCFOp = (PPCSubTarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
4868 (Op.getOpcode() == ISD::UINT_TO_FP ?
4869 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
4870 (Op.getOpcode() == ISD::UINT_TO_FP ?
4871 PPCISD::FCFIDU : PPCISD::FCFID);
4872 MVT FCFTy = (PPCSubTarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
4873 MVT::f32 : MVT::f64;
4875 if (Op.getOperand(0).getValueType() == MVT::i64) {
4876 SDValue SINT = Op.getOperand(0);
4877 // When converting to single-precision, we actually need to convert
4878 // to double-precision first and then round to single-precision.
4879 // To avoid double-rounding effects during that operation, we have
4880 // to prepare the input operand. Bits that might be truncated when
4881 // converting to double-precision are replaced by a bit that won't
4882 // be lost at this stage, but is below the single-precision rounding
4885 // However, if -enable-unsafe-fp-math is in effect, accept double
4886 // rounding to avoid the extra overhead.
4887 if (Op.getValueType() == MVT::f32 &&
4888 !PPCSubTarget.hasFPCVT() &&
4889 !DAG.getTarget().Options.UnsafeFPMath) {
4891 // Twiddle input to make sure the low 11 bits are zero. (If this
4892 // is the case, we are guaranteed the value will fit into the 53 bit
4893 // mantissa of an IEEE double-precision value without rounding.)
4894 // If any of those low 11 bits were not zero originally, make sure
4895 // bit 12 (value 2048) is set instead, so that the final rounding
4896 // to single-precision gets the correct result.
4897 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
4898 SINT, DAG.getConstant(2047, MVT::i64));
4899 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
4900 Round, DAG.getConstant(2047, MVT::i64));
4901 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
4902 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
4903 Round, DAG.getConstant(-2048, MVT::i64));
4905 // However, we cannot use that value unconditionally: if the magnitude
4906 // of the input value is small, the bit-twiddling we did above might
4907 // end up visibly changing the output. Fortunately, in that case, we
4908 // don't need to twiddle bits since the original input will convert
4909 // exactly to double-precision floating-point already. Therefore,
4910 // construct a conditional to use the original value if the top 11
4911 // bits are all sign-bit copies, and use the rounded value computed
4913 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
4914 SINT, DAG.getConstant(53, MVT::i32));
4915 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
4916 Cond, DAG.getConstant(1, MVT::i64));
4917 Cond = DAG.getSetCC(dl, MVT::i32,
4918 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
4920 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
4923 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
4924 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
4926 if (Op.getValueType() == MVT::f32 && !PPCSubTarget.hasFPCVT())
4927 FP = DAG.getNode(ISD::FP_ROUND, dl,
4928 MVT::f32, FP, DAG.getIntPtrConstant(0));
4932 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
4933 "Unhandled INT_TO_FP type in custom expander!");
4934 // Since we only generate this in 64-bit mode, we can take advantage of
4935 // 64-bit registers. In particular, sign extend the input value into the
4936 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
4937 // then lfd it and fcfid it.
4938 MachineFunction &MF = DAG.getMachineFunction();
4939 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
4940 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4943 if (PPCSubTarget.hasLFIWAX() || PPCSubTarget.hasFPCVT()) {
4944 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
4945 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4947 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
4948 MachinePointerInfo::getFixedStack(FrameIdx),
4951 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
4952 "Expected an i32 store");
4953 MachineMemOperand *MMO =
4954 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
4955 MachineMemOperand::MOLoad, 4, 4);
4956 SDValue Ops[] = { Store, FIdx };
4957 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
4958 PPCISD::LFIWZX : PPCISD::LFIWAX,
4959 dl, DAG.getVTList(MVT::f64, MVT::Other),
4960 Ops, 2, MVT::i32, MMO);
4962 assert(PPCSubTarget.isPPC64() &&
4963 "i32->FP without LFIWAX supported only on PPC64");
4965 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
4966 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4968 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
4971 // STD the extended value into the stack slot.
4972 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
4973 MachinePointerInfo::getFixedStack(FrameIdx),
4976 // Load the value as a double.
4977 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
4978 MachinePointerInfo::getFixedStack(FrameIdx),
4979 false, false, false, 0);
4982 // FCFID it and return it.
4983 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
4984 if (Op.getValueType() == MVT::f32 && !PPCSubTarget.hasFPCVT())
4985 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
4989 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
4990 SelectionDAG &DAG) const {
4993 The rounding mode is in bits 30:31 of FPSR, and has the following
5000 FLT_ROUNDS, on the other hand, expects the following:
5007 To perform the conversion, we do:
5008 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
5011 MachineFunction &MF = DAG.getMachineFunction();
5012 EVT VT = Op.getValueType();
5013 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5014 SDValue MFFSreg, InFlag;
5016 // Save FP Control Word to register
5018 MVT::f64, // return register
5019 MVT::Glue // unused in this context
5021 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
5023 // Save FP register to stack slot
5024 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5025 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
5026 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
5027 StackSlot, MachinePointerInfo(), false, false,0);
5029 // Load FP Control Word from low 32 bits of stack slot.
5030 SDValue Four = DAG.getConstant(4, PtrVT);
5031 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
5032 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
5033 false, false, false, 0);
5035 // Transform as necessary
5037 DAG.getNode(ISD::AND, dl, MVT::i32,
5038 CWD, DAG.getConstant(3, MVT::i32));
5040 DAG.getNode(ISD::SRL, dl, MVT::i32,
5041 DAG.getNode(ISD::AND, dl, MVT::i32,
5042 DAG.getNode(ISD::XOR, dl, MVT::i32,
5043 CWD, DAG.getConstant(3, MVT::i32)),
5044 DAG.getConstant(3, MVT::i32)),
5045 DAG.getConstant(1, MVT::i32));
5048 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
5050 return DAG.getNode((VT.getSizeInBits() < 16 ?
5051 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
5054 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5055 EVT VT = Op.getValueType();
5056 unsigned BitWidth = VT.getSizeInBits();
5058 assert(Op.getNumOperands() == 3 &&
5059 VT == Op.getOperand(1).getValueType() &&
5062 // Expand into a bunch of logical ops. Note that these ops
5063 // depend on the PPC behavior for oversized shift amounts.
5064 SDValue Lo = Op.getOperand(0);
5065 SDValue Hi = Op.getOperand(1);
5066 SDValue Amt = Op.getOperand(2);
5067 EVT AmtVT = Amt.getValueType();
5069 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5070 DAG.getConstant(BitWidth, AmtVT), Amt);
5071 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
5072 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5073 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5074 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5075 DAG.getConstant(-BitWidth, AmtVT));
5076 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5077 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5078 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
5079 SDValue OutOps[] = { OutLo, OutHi };
5080 return DAG.getMergeValues(OutOps, 2, dl);
5083 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5084 EVT VT = Op.getValueType();
5086 unsigned BitWidth = VT.getSizeInBits();
5087 assert(Op.getNumOperands() == 3 &&
5088 VT == Op.getOperand(1).getValueType() &&
5091 // Expand into a bunch of logical ops. Note that these ops
5092 // depend on the PPC behavior for oversized shift amounts.
5093 SDValue Lo = Op.getOperand(0);
5094 SDValue Hi = Op.getOperand(1);
5095 SDValue Amt = Op.getOperand(2);
5096 EVT AmtVT = Amt.getValueType();
5098 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5099 DAG.getConstant(BitWidth, AmtVT), Amt);
5100 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5101 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5102 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5103 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5104 DAG.getConstant(-BitWidth, AmtVT));
5105 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
5106 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5107 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
5108 SDValue OutOps[] = { OutLo, OutHi };
5109 return DAG.getMergeValues(OutOps, 2, dl);
5112 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
5114 EVT VT = Op.getValueType();
5115 unsigned BitWidth = VT.getSizeInBits();
5116 assert(Op.getNumOperands() == 3 &&
5117 VT == Op.getOperand(1).getValueType() &&
5120 // Expand into a bunch of logical ops, followed by a select_cc.
5121 SDValue Lo = Op.getOperand(0);
5122 SDValue Hi = Op.getOperand(1);
5123 SDValue Amt = Op.getOperand(2);
5124 EVT AmtVT = Amt.getValueType();
5126 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5127 DAG.getConstant(BitWidth, AmtVT), Amt);
5128 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5129 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5130 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5131 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5132 DAG.getConstant(-BitWidth, AmtVT));
5133 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
5134 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
5135 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
5136 Tmp4, Tmp6, ISD::SETLE);
5137 SDValue OutOps[] = { OutLo, OutHi };
5138 return DAG.getMergeValues(OutOps, 2, dl);
5141 //===----------------------------------------------------------------------===//
5142 // Vector related lowering.
5145 /// BuildSplatI - Build a canonical splati of Val with an element size of
5146 /// SplatSize. Cast the result to VT.
5147 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
5148 SelectionDAG &DAG, SDLoc dl) {
5149 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
5151 static const EVT VTys[] = { // canonical VT to use for each size.
5152 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
5155 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
5157 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
5161 EVT CanonicalVT = VTys[SplatSize-1];
5163 // Build a canonical splat for this value.
5164 SDValue Elt = DAG.getConstant(Val, MVT::i32);
5165 SmallVector<SDValue, 8> Ops;
5166 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
5167 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
5168 &Ops[0], Ops.size());
5169 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
5172 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
5173 /// specified intrinsic ID.
5174 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
5175 SelectionDAG &DAG, SDLoc dl,
5176 EVT DestVT = MVT::Other) {
5177 if (DestVT == MVT::Other) DestVT = Op.getValueType();
5178 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5179 DAG.getConstant(IID, MVT::i32), Op);
5182 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
5183 /// specified intrinsic ID.
5184 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
5185 SelectionDAG &DAG, SDLoc dl,
5186 EVT DestVT = MVT::Other) {
5187 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
5188 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5189 DAG.getConstant(IID, MVT::i32), LHS, RHS);
5192 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
5193 /// specified intrinsic ID.
5194 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
5195 SDValue Op2, SelectionDAG &DAG,
5196 SDLoc dl, EVT DestVT = MVT::Other) {
5197 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
5198 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5199 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
5203 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
5204 /// amount. The result has the specified value type.
5205 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
5206 EVT VT, SelectionDAG &DAG, SDLoc dl) {
5207 // Force LHS/RHS to be the right type.
5208 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
5209 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
5212 for (unsigned i = 0; i != 16; ++i)
5214 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
5215 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5218 // If this is a case we can't handle, return null and let the default
5219 // expansion code take care of it. If we CAN select this case, and if it
5220 // selects to a single instruction, return Op. Otherwise, if we can codegen
5221 // this case more efficiently than a constant pool load, lower it to the
5222 // sequence of ops that should be used.
5223 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
5224 SelectionDAG &DAG) const {
5226 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5227 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
5229 // Check if this is a splat of a constant value.
5230 APInt APSplatBits, APSplatUndef;
5231 unsigned SplatBitSize;
5233 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
5234 HasAnyUndefs, 0, true) || SplatBitSize > 32)
5237 unsigned SplatBits = APSplatBits.getZExtValue();
5238 unsigned SplatUndef = APSplatUndef.getZExtValue();
5239 unsigned SplatSize = SplatBitSize / 8;
5241 // First, handle single instruction cases.
5244 if (SplatBits == 0) {
5245 // Canonicalize all zero vectors to be v4i32.
5246 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5247 SDValue Z = DAG.getConstant(0, MVT::i32);
5248 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5249 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
5254 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
5255 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
5257 if (SextVal >= -16 && SextVal <= 15)
5258 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
5261 // Two instruction sequences.
5263 // If this value is in the range [-32,30] and is even, use:
5264 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
5265 // If this value is in the range [17,31] and is odd, use:
5266 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
5267 // If this value is in the range [-31,-17] and is odd, use:
5268 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
5269 // Note the last two are three-instruction sequences.
5270 if (SextVal >= -32 && SextVal <= 31) {
5271 // To avoid having these optimizations undone by constant folding,
5272 // we convert to a pseudo that will be expanded later into one of
5274 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
5275 EVT VT = Op.getValueType();
5276 int Size = VT == MVT::v16i8 ? 1 : (VT == MVT::v8i16 ? 2 : 4);
5277 SDValue EltSize = DAG.getConstant(Size, MVT::i32);
5278 return DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
5281 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
5282 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
5284 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
5285 // Make -1 and vspltisw -1:
5286 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
5288 // Make the VSLW intrinsic, computing 0x8000_0000.
5289 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
5292 // xor by OnesV to invert it.
5293 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5294 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5297 // Check to see if this is a wide variety of vsplti*, binop self cases.
5298 static const signed char SplatCsts[] = {
5299 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
5300 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
5303 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
5304 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
5305 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
5306 int i = SplatCsts[idx];
5308 // Figure out what shift amount will be used by altivec if shifted by i in
5310 unsigned TypeShiftAmt = i & (SplatBitSize-1);
5312 // vsplti + shl self.
5313 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
5314 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5315 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5316 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
5317 Intrinsic::ppc_altivec_vslw
5319 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5320 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5323 // vsplti + srl self.
5324 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5325 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5326 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5327 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
5328 Intrinsic::ppc_altivec_vsrw
5330 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5331 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5334 // vsplti + sra self.
5335 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5336 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5337 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5338 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
5339 Intrinsic::ppc_altivec_vsraw
5341 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5342 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5345 // vsplti + rol self.
5346 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
5347 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
5348 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5349 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5350 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
5351 Intrinsic::ppc_altivec_vrlw
5353 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5354 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5357 // t = vsplti c, result = vsldoi t, t, 1
5358 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
5359 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5360 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
5362 // t = vsplti c, result = vsldoi t, t, 2
5363 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
5364 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5365 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
5367 // t = vsplti c, result = vsldoi t, t, 3
5368 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
5369 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5370 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
5377 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5378 /// the specified operations to build the shuffle.
5379 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5380 SDValue RHS, SelectionDAG &DAG,
5382 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5383 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5384 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5387 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5399 if (OpNum == OP_COPY) {
5400 if (LHSID == (1*9+2)*9+3) return LHS;
5401 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5405 SDValue OpLHS, OpRHS;
5406 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5407 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5411 default: llvm_unreachable("Unknown i32 permute!");
5413 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
5414 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
5415 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
5416 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
5419 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
5420 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
5421 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
5422 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
5425 for (unsigned i = 0; i != 16; ++i)
5426 ShufIdxs[i] = (i&3)+0;
5429 for (unsigned i = 0; i != 16; ++i)
5430 ShufIdxs[i] = (i&3)+4;
5433 for (unsigned i = 0; i != 16; ++i)
5434 ShufIdxs[i] = (i&3)+8;
5437 for (unsigned i = 0; i != 16; ++i)
5438 ShufIdxs[i] = (i&3)+12;
5441 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
5443 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
5445 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
5447 EVT VT = OpLHS.getValueType();
5448 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
5449 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
5450 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
5451 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5454 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
5455 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
5456 /// return the code it can be lowered into. Worst case, it can always be
5457 /// lowered into a vperm.
5458 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5459 SelectionDAG &DAG) const {
5461 SDValue V1 = Op.getOperand(0);
5462 SDValue V2 = Op.getOperand(1);
5463 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5464 EVT VT = Op.getValueType();
5466 // Cases that are handled by instructions that take permute immediates
5467 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
5468 // selected by the instruction selector.
5469 if (V2.getOpcode() == ISD::UNDEF) {
5470 if (PPC::isSplatShuffleMask(SVOp, 1) ||
5471 PPC::isSplatShuffleMask(SVOp, 2) ||
5472 PPC::isSplatShuffleMask(SVOp, 4) ||
5473 PPC::isVPKUWUMShuffleMask(SVOp, true) ||
5474 PPC::isVPKUHUMShuffleMask(SVOp, true) ||
5475 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 ||
5476 PPC::isVMRGLShuffleMask(SVOp, 1, true) ||
5477 PPC::isVMRGLShuffleMask(SVOp, 2, true) ||
5478 PPC::isVMRGLShuffleMask(SVOp, 4, true) ||
5479 PPC::isVMRGHShuffleMask(SVOp, 1, true) ||
5480 PPC::isVMRGHShuffleMask(SVOp, 2, true) ||
5481 PPC::isVMRGHShuffleMask(SVOp, 4, true)) {
5486 // Altivec has a variety of "shuffle immediates" that take two vector inputs
5487 // and produce a fixed permutation. If any of these match, do not lower to
5489 if (PPC::isVPKUWUMShuffleMask(SVOp, false) ||
5490 PPC::isVPKUHUMShuffleMask(SVOp, false) ||
5491 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 ||
5492 PPC::isVMRGLShuffleMask(SVOp, 1, false) ||
5493 PPC::isVMRGLShuffleMask(SVOp, 2, false) ||
5494 PPC::isVMRGLShuffleMask(SVOp, 4, false) ||
5495 PPC::isVMRGHShuffleMask(SVOp, 1, false) ||
5496 PPC::isVMRGHShuffleMask(SVOp, 2, false) ||
5497 PPC::isVMRGHShuffleMask(SVOp, 4, false))
5500 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
5501 // perfect shuffle table to emit an optimal matching sequence.
5502 ArrayRef<int> PermMask = SVOp->getMask();
5504 unsigned PFIndexes[4];
5505 bool isFourElementShuffle = true;
5506 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
5507 unsigned EltNo = 8; // Start out undef.
5508 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
5509 if (PermMask[i*4+j] < 0)
5510 continue; // Undef, ignore it.
5512 unsigned ByteSource = PermMask[i*4+j];
5513 if ((ByteSource & 3) != j) {
5514 isFourElementShuffle = false;
5519 EltNo = ByteSource/4;
5520 } else if (EltNo != ByteSource/4) {
5521 isFourElementShuffle = false;
5525 PFIndexes[i] = EltNo;
5528 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
5529 // perfect shuffle vector to determine if it is cost effective to do this as
5530 // discrete instructions, or whether we should use a vperm.
5531 if (isFourElementShuffle) {
5532 // Compute the index in the perfect shuffle table.
5533 unsigned PFTableIndex =
5534 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5536 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5537 unsigned Cost = (PFEntry >> 30);
5539 // Determining when to avoid vperm is tricky. Many things affect the cost
5540 // of vperm, particularly how many times the perm mask needs to be computed.
5541 // For example, if the perm mask can be hoisted out of a loop or is already
5542 // used (perhaps because there are multiple permutes with the same shuffle
5543 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
5544 // the loop requires an extra register.
5546 // As a compromise, we only emit discrete instructions if the shuffle can be
5547 // generated in 3 or fewer operations. When we have loop information
5548 // available, if this block is within a loop, we should avoid using vperm
5549 // for 3-operation perms and use a constant pool load instead.
5551 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5554 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
5555 // vector that will get spilled to the constant pool.
5556 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
5558 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
5559 // that it is in input element units, not in bytes. Convert now.
5560 EVT EltVT = V1.getValueType().getVectorElementType();
5561 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
5563 SmallVector<SDValue, 16> ResultMask;
5564 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
5565 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
5567 for (unsigned j = 0; j != BytesPerElement; ++j)
5568 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
5572 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
5573 &ResultMask[0], ResultMask.size());
5574 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
5577 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
5578 /// altivec comparison. If it is, return true and fill in Opc/isDot with
5579 /// information about the intrinsic.
5580 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
5582 unsigned IntrinsicID =
5583 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
5586 switch (IntrinsicID) {
5587 default: return false;
5588 // Comparison predicates.
5589 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
5590 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
5591 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
5592 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
5593 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
5594 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
5595 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
5596 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
5597 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
5598 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
5599 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
5600 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
5601 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
5603 // Normal Comparisons.
5604 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
5605 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
5606 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
5607 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
5608 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
5609 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
5610 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
5611 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
5612 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
5613 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
5614 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
5615 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
5616 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
5621 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
5622 /// lower, do it, otherwise return null.
5623 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
5624 SelectionDAG &DAG) const {
5625 // If this is a lowered altivec predicate compare, CompareOpc is set to the
5626 // opcode number of the comparison.
5630 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
5631 return SDValue(); // Don't custom lower most intrinsics.
5633 // If this is a non-dot comparison, make the VCMP node and we are done.
5635 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
5636 Op.getOperand(1), Op.getOperand(2),
5637 DAG.getConstant(CompareOpc, MVT::i32));
5638 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
5641 // Create the PPCISD altivec 'dot' comparison node.
5643 Op.getOperand(2), // LHS
5644 Op.getOperand(3), // RHS
5645 DAG.getConstant(CompareOpc, MVT::i32)
5647 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
5648 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
5650 // Now that we have the comparison, emit a copy from the CR to a GPR.
5651 // This is flagged to the above dot comparison.
5652 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
5653 DAG.getRegister(PPC::CR6, MVT::i32),
5654 CompNode.getValue(1));
5656 // Unpack the result based on how the target uses it.
5657 unsigned BitNo; // Bit # of CR6.
5658 bool InvertBit; // Invert result?
5659 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
5660 default: // Can't happen, don't crash on invalid number though.
5661 case 0: // Return the value of the EQ bit of CR6.
5662 BitNo = 0; InvertBit = false;
5664 case 1: // Return the inverted value of the EQ bit of CR6.
5665 BitNo = 0; InvertBit = true;
5667 case 2: // Return the value of the LT bit of CR6.
5668 BitNo = 2; InvertBit = false;
5670 case 3: // Return the inverted value of the LT bit of CR6.
5671 BitNo = 2; InvertBit = true;
5675 // Shift the bit into the low position.
5676 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
5677 DAG.getConstant(8-(3-BitNo), MVT::i32));
5679 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
5680 DAG.getConstant(1, MVT::i32));
5682 // If we are supposed to, toggle the bit.
5684 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
5685 DAG.getConstant(1, MVT::i32));
5689 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
5690 SelectionDAG &DAG) const {
5692 // Create a stack slot that is 16-byte aligned.
5693 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
5694 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
5695 EVT PtrVT = getPointerTy();
5696 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5698 // Store the input value into Value#0 of the stack slot.
5699 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
5700 Op.getOperand(0), FIdx, MachinePointerInfo(),
5703 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
5704 false, false, false, 0);
5707 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
5709 if (Op.getValueType() == MVT::v4i32) {
5710 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5712 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
5713 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
5715 SDValue RHSSwap = // = vrlw RHS, 16
5716 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
5718 // Shrinkify inputs to v8i16.
5719 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
5720 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
5721 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
5723 // Low parts multiplied together, generating 32-bit results (we ignore the
5725 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
5726 LHS, RHS, DAG, dl, MVT::v4i32);
5728 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
5729 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
5730 // Shift the high parts up 16 bits.
5731 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
5733 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
5734 } else if (Op.getValueType() == MVT::v8i16) {
5735 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5737 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
5739 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
5740 LHS, RHS, Zero, DAG, dl);
5741 } else if (Op.getValueType() == MVT::v16i8) {
5742 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5744 // Multiply the even 8-bit parts, producing 16-bit sums.
5745 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
5746 LHS, RHS, DAG, dl, MVT::v8i16);
5747 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
5749 // Multiply the odd 8-bit parts, producing 16-bit sums.
5750 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
5751 LHS, RHS, DAG, dl, MVT::v8i16);
5752 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
5754 // Merge the results together.
5756 for (unsigned i = 0; i != 8; ++i) {
5758 Ops[i*2+1] = 2*i+1+16;
5760 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
5762 llvm_unreachable("Unknown mul to lower!");
5766 /// LowerOperation - Provide custom lowering hooks for some operations.
5768 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
5769 switch (Op.getOpcode()) {
5770 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
5771 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
5772 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
5773 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
5774 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
5775 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
5776 case ISD::SETCC: return LowerSETCC(Op, DAG);
5777 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
5778 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
5780 return LowerVASTART(Op, DAG, PPCSubTarget);
5783 return LowerVAARG(Op, DAG, PPCSubTarget);
5786 return LowerVACOPY(Op, DAG, PPCSubTarget);
5788 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
5789 case ISD::DYNAMIC_STACKALLOC:
5790 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
5792 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
5793 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
5795 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
5796 case ISD::FP_TO_UINT:
5797 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
5799 case ISD::UINT_TO_FP:
5800 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
5801 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
5803 // Lower 64-bit shifts.
5804 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
5805 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
5806 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
5808 // Vector-related lowering.
5809 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
5810 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
5811 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
5812 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
5813 case ISD::MUL: return LowerMUL(Op, DAG);
5815 // For counter-based loop handling.
5816 case ISD::INTRINSIC_W_CHAIN: return SDValue();
5818 // Frame & Return address.
5819 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
5820 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
5824 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
5825 SmallVectorImpl<SDValue>&Results,
5826 SelectionDAG &DAG) const {
5827 const TargetMachine &TM = getTargetMachine();
5829 switch (N->getOpcode()) {
5831 llvm_unreachable("Do not know how to custom type legalize this operation!");
5832 case ISD::INTRINSIC_W_CHAIN: {
5833 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
5834 Intrinsic::ppc_is_decremented_ctr_nonzero)
5837 assert(N->getValueType(0) == MVT::i1 &&
5838 "Unexpected result type for CTR decrement intrinsic");
5839 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
5840 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
5841 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
5844 Results.push_back(NewInt);
5845 Results.push_back(NewInt.getValue(1));
5849 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
5850 || TM.getSubtarget<PPCSubtarget>().isPPC64())
5853 EVT VT = N->getValueType(0);
5855 if (VT == MVT::i64) {
5856 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, PPCSubTarget);
5858 Results.push_back(NewNode);
5859 Results.push_back(NewNode.getValue(1));
5863 case ISD::FP_ROUND_INREG: {
5864 assert(N->getValueType(0) == MVT::ppcf128);
5865 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
5866 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
5867 MVT::f64, N->getOperand(0),
5868 DAG.getIntPtrConstant(0));
5869 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
5870 MVT::f64, N->getOperand(0),
5871 DAG.getIntPtrConstant(1));
5873 // Add the two halves of the long double in round-to-zero mode.
5874 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
5876 // We know the low half is about to be thrown away, so just use something
5878 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
5882 case ISD::FP_TO_SINT:
5883 // LowerFP_TO_INT() can only handle f32 and f64.
5884 if (N->getOperand(0).getValueType() == MVT::ppcf128)
5886 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
5892 //===----------------------------------------------------------------------===//
5893 // Other Lowering Code
5894 //===----------------------------------------------------------------------===//
5897 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
5898 bool is64bit, unsigned BinOpcode) const {
5899 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
5900 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5902 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5903 MachineFunction *F = BB->getParent();
5904 MachineFunction::iterator It = BB;
5907 unsigned dest = MI->getOperand(0).getReg();
5908 unsigned ptrA = MI->getOperand(1).getReg();
5909 unsigned ptrB = MI->getOperand(2).getReg();
5910 unsigned incr = MI->getOperand(3).getReg();
5911 DebugLoc dl = MI->getDebugLoc();
5913 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
5914 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
5915 F->insert(It, loopMBB);
5916 F->insert(It, exitMBB);
5917 exitMBB->splice(exitMBB->begin(), BB,
5918 llvm::next(MachineBasicBlock::iterator(MI)),
5920 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5922 MachineRegisterInfo &RegInfo = F->getRegInfo();
5923 unsigned TmpReg = (!BinOpcode) ? incr :
5924 RegInfo.createVirtualRegister(
5925 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
5926 (const TargetRegisterClass *) &PPC::GPRCRegClass);
5930 // fallthrough --> loopMBB
5931 BB->addSuccessor(loopMBB);
5934 // l[wd]arx dest, ptr
5935 // add r0, dest, incr
5936 // st[wd]cx. r0, ptr
5938 // fallthrough --> exitMBB
5940 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
5941 .addReg(ptrA).addReg(ptrB);
5943 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
5944 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
5945 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
5946 BuildMI(BB, dl, TII->get(PPC::BCC))
5947 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
5948 BB->addSuccessor(loopMBB);
5949 BB->addSuccessor(exitMBB);
5958 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
5959 MachineBasicBlock *BB,
5960 bool is8bit, // operation
5961 unsigned BinOpcode) const {
5962 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
5963 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5964 // In 64 bit mode we have to use 64 bits for addresses, even though the
5965 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
5966 // registers without caring whether they're 32 or 64, but here we're
5967 // doing actual arithmetic on the addresses.
5968 bool is64bit = PPCSubTarget.isPPC64();
5969 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
5971 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5972 MachineFunction *F = BB->getParent();
5973 MachineFunction::iterator It = BB;
5976 unsigned dest = MI->getOperand(0).getReg();
5977 unsigned ptrA = MI->getOperand(1).getReg();
5978 unsigned ptrB = MI->getOperand(2).getReg();
5979 unsigned incr = MI->getOperand(3).getReg();
5980 DebugLoc dl = MI->getDebugLoc();
5982 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
5983 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
5984 F->insert(It, loopMBB);
5985 F->insert(It, exitMBB);
5986 exitMBB->splice(exitMBB->begin(), BB,
5987 llvm::next(MachineBasicBlock::iterator(MI)),
5989 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5991 MachineRegisterInfo &RegInfo = F->getRegInfo();
5992 const TargetRegisterClass *RC =
5993 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
5994 (const TargetRegisterClass *) &PPC::GPRCRegClass;
5995 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
5996 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
5997 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
5998 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
5999 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6000 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6001 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6002 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6003 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
6004 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6005 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6007 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
6011 // fallthrough --> loopMBB
6012 BB->addSuccessor(loopMBB);
6014 // The 4-byte load must be aligned, while a char or short may be
6015 // anywhere in the word. Hence all this nasty bookkeeping code.
6016 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6017 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6018 // xori shift, shift1, 24 [16]
6019 // rlwinm ptr, ptr1, 0, 0, 29
6020 // slw incr2, incr, shift
6021 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6022 // slw mask, mask2, shift
6024 // lwarx tmpDest, ptr
6025 // add tmp, tmpDest, incr2
6026 // andc tmp2, tmpDest, mask
6027 // and tmp3, tmp, mask
6028 // or tmp4, tmp3, tmp2
6031 // fallthrough --> exitMBB
6032 // srw dest, tmpDest, shift
6033 if (ptrA != ZeroReg) {
6034 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6035 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6036 .addReg(ptrA).addReg(ptrB);
6040 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6041 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6042 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6043 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6045 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6046 .addReg(Ptr1Reg).addImm(0).addImm(61);
6048 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6049 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6050 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
6051 .addReg(incr).addReg(ShiftReg);
6053 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6055 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6056 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
6058 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6059 .addReg(Mask2Reg).addReg(ShiftReg);
6062 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6063 .addReg(ZeroReg).addReg(PtrReg);
6065 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
6066 .addReg(Incr2Reg).addReg(TmpDestReg);
6067 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
6068 .addReg(TmpDestReg).addReg(MaskReg);
6069 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
6070 .addReg(TmpReg).addReg(MaskReg);
6071 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
6072 .addReg(Tmp3Reg).addReg(Tmp2Reg);
6073 BuildMI(BB, dl, TII->get(PPC::STWCX))
6074 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
6075 BuildMI(BB, dl, TII->get(PPC::BCC))
6076 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6077 BB->addSuccessor(loopMBB);
6078 BB->addSuccessor(exitMBB);
6083 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
6088 llvm::MachineBasicBlock*
6089 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
6090 MachineBasicBlock *MBB) const {
6091 DebugLoc DL = MI->getDebugLoc();
6092 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6094 MachineFunction *MF = MBB->getParent();
6095 MachineRegisterInfo &MRI = MF->getRegInfo();
6097 const BasicBlock *BB = MBB->getBasicBlock();
6098 MachineFunction::iterator I = MBB;
6102 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6103 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6105 unsigned DstReg = MI->getOperand(0).getReg();
6106 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
6107 assert(RC->hasType(MVT::i32) && "Invalid destination!");
6108 unsigned mainDstReg = MRI.createVirtualRegister(RC);
6109 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
6111 MVT PVT = getPointerTy();
6112 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6113 "Invalid Pointer Size!");
6114 // For v = setjmp(buf), we generate
6117 // SjLjSetup mainMBB
6123 // buf[LabelOffset] = LR
6127 // v = phi(main, restore)
6130 MachineBasicBlock *thisMBB = MBB;
6131 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
6132 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
6133 MF->insert(I, mainMBB);
6134 MF->insert(I, sinkMBB);
6136 MachineInstrBuilder MIB;
6138 // Transfer the remainder of BB and its successor edges to sinkMBB.
6139 sinkMBB->splice(sinkMBB->begin(), MBB,
6140 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
6141 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
6143 // Note that the structure of the jmp_buf used here is not compatible
6144 // with that used by libc, and is not designed to be. Specifically, it
6145 // stores only those 'reserved' registers that LLVM does not otherwise
6146 // understand how to spill. Also, by convention, by the time this
6147 // intrinsic is called, Clang has already stored the frame address in the
6148 // first slot of the buffer and stack address in the third. Following the
6149 // X86 target code, we'll store the jump address in the second slot. We also
6150 // need to save the TOC pointer (R2) to handle jumps between shared
6151 // libraries, and that will be stored in the fourth slot. The thread
6152 // identifier (R13) is not affected.
6155 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6156 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6157 const int64_t BPOffset = 4 * PVT.getStoreSize();
6159 // Prepare IP either in reg.
6160 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
6161 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
6162 unsigned BufReg = MI->getOperand(1).getReg();
6164 if (PPCSubTarget.isPPC64() && PPCSubTarget.isSVR4ABI()) {
6165 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
6169 MIB.setMemRefs(MMOBegin, MMOEnd);
6172 // Naked functions never have a base pointer, and so we use r1. For all
6173 // other functions, this decision must be delayed until during PEI.
6175 if (MF->getFunction()->getAttributes().hasAttribute(
6176 AttributeSet::FunctionIndex, Attribute::Naked))
6177 BaseReg = PPCSubTarget.isPPC64() ? PPC::X1 : PPC::R1;
6179 BaseReg = PPCSubTarget.isPPC64() ? PPC::BP8 : PPC::BP;
6181 MIB = BuildMI(*thisMBB, MI, DL,
6182 TII->get(PPCSubTarget.isPPC64() ? PPC::STD : PPC::STW))
6186 MIB.setMemRefs(MMOBegin, MMOEnd);
6189 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
6190 const PPCRegisterInfo *TRI =
6191 static_cast<const PPCRegisterInfo*>(getTargetMachine().getRegisterInfo());
6192 MIB.addRegMask(TRI->getNoPreservedMask());
6194 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
6196 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
6198 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
6200 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
6201 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
6205 MIB = BuildMI(mainMBB, DL,
6206 TII->get(PPCSubTarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
6209 if (PPCSubTarget.isPPC64()) {
6210 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
6212 .addImm(LabelOffset)
6215 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
6217 .addImm(LabelOffset)
6221 MIB.setMemRefs(MMOBegin, MMOEnd);
6223 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
6224 mainMBB->addSuccessor(sinkMBB);
6227 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
6228 TII->get(PPC::PHI), DstReg)
6229 .addReg(mainDstReg).addMBB(mainMBB)
6230 .addReg(restoreDstReg).addMBB(thisMBB);
6232 MI->eraseFromParent();
6237 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
6238 MachineBasicBlock *MBB) const {
6239 DebugLoc DL = MI->getDebugLoc();
6240 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6242 MachineFunction *MF = MBB->getParent();
6243 MachineRegisterInfo &MRI = MF->getRegInfo();
6246 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6247 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6249 MVT PVT = getPointerTy();
6250 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6251 "Invalid Pointer Size!");
6253 const TargetRegisterClass *RC =
6254 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6255 unsigned Tmp = MRI.createVirtualRegister(RC);
6256 // Since FP is only updated here but NOT referenced, it's treated as GPR.
6257 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6258 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6259 unsigned BP = (PVT == MVT::i64) ? PPC::X30 : PPC::R30;
6261 MachineInstrBuilder MIB;
6263 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6264 const int64_t SPOffset = 2 * PVT.getStoreSize();
6265 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6266 const int64_t BPOffset = 4 * PVT.getStoreSize();
6268 unsigned BufReg = MI->getOperand(0).getReg();
6270 // Reload FP (the jumped-to function may not have had a
6271 // frame pointer, and if so, then its r31 will be restored
6273 if (PVT == MVT::i64) {
6274 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
6278 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
6282 MIB.setMemRefs(MMOBegin, MMOEnd);
6285 if (PVT == MVT::i64) {
6286 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
6287 .addImm(LabelOffset)
6290 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
6291 .addImm(LabelOffset)
6294 MIB.setMemRefs(MMOBegin, MMOEnd);
6297 if (PVT == MVT::i64) {
6298 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
6302 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
6306 MIB.setMemRefs(MMOBegin, MMOEnd);
6309 if (PVT == MVT::i64) {
6310 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
6314 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
6318 MIB.setMemRefs(MMOBegin, MMOEnd);
6321 if (PVT == MVT::i64 && PPCSubTarget.isSVR4ABI()) {
6322 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
6326 MIB.setMemRefs(MMOBegin, MMOEnd);
6330 BuildMI(*MBB, MI, DL,
6331 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
6332 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
6334 MI->eraseFromParent();
6339 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6340 MachineBasicBlock *BB) const {
6341 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
6342 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
6343 return emitEHSjLjSetJmp(MI, BB);
6344 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
6345 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
6346 return emitEHSjLjLongJmp(MI, BB);
6349 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6351 // To "insert" these instructions we actually have to insert their
6352 // control-flow patterns.
6353 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6354 MachineFunction::iterator It = BB;
6357 MachineFunction *F = BB->getParent();
6359 if (PPCSubTarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6360 MI->getOpcode() == PPC::SELECT_CC_I8)) {
6361 SmallVector<MachineOperand, 2> Cond;
6362 Cond.push_back(MI->getOperand(4));
6363 Cond.push_back(MI->getOperand(1));
6365 DebugLoc dl = MI->getDebugLoc();
6366 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6367 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
6368 Cond, MI->getOperand(2).getReg(),
6369 MI->getOperand(3).getReg());
6370 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6371 MI->getOpcode() == PPC::SELECT_CC_I8 ||
6372 MI->getOpcode() == PPC::SELECT_CC_F4 ||
6373 MI->getOpcode() == PPC::SELECT_CC_F8 ||
6374 MI->getOpcode() == PPC::SELECT_CC_VRRC) {
6377 // The incoming instruction knows the destination vreg to set, the
6378 // condition code register to branch on, the true/false values to
6379 // select between, and a branch opcode to use.
6384 // cmpTY ccX, r1, r2
6386 // fallthrough --> copy0MBB
6387 MachineBasicBlock *thisMBB = BB;
6388 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
6389 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
6390 unsigned SelectPred = MI->getOperand(4).getImm();
6391 DebugLoc dl = MI->getDebugLoc();
6392 F->insert(It, copy0MBB);
6393 F->insert(It, sinkMBB);
6395 // Transfer the remainder of BB and its successor edges to sinkMBB.
6396 sinkMBB->splice(sinkMBB->begin(), BB,
6397 llvm::next(MachineBasicBlock::iterator(MI)),
6399 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
6401 // Next, add the true and fallthrough blocks as its successors.
6402 BB->addSuccessor(copy0MBB);
6403 BB->addSuccessor(sinkMBB);
6405 BuildMI(BB, dl, TII->get(PPC::BCC))
6406 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
6409 // %FalseValue = ...
6410 // # fallthrough to sinkMBB
6413 // Update machine-CFG edges
6414 BB->addSuccessor(sinkMBB);
6417 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
6420 BuildMI(*BB, BB->begin(), dl,
6421 TII->get(PPC::PHI), MI->getOperand(0).getReg())
6422 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
6423 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
6425 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
6426 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
6427 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
6428 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
6429 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
6430 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
6431 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
6432 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
6434 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
6435 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
6436 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
6437 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
6438 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
6439 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
6440 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
6441 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
6443 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
6444 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
6445 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
6446 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
6447 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
6448 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
6449 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
6450 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
6452 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
6453 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
6454 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
6455 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
6456 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
6457 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
6458 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
6459 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
6461 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
6462 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
6463 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
6464 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
6465 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
6466 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
6467 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
6468 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
6470 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
6471 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
6472 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
6473 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
6474 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
6475 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
6476 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
6477 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
6479 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
6480 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
6481 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
6482 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
6483 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
6484 BB = EmitAtomicBinary(MI, BB, false, 0);
6485 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
6486 BB = EmitAtomicBinary(MI, BB, true, 0);
6488 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
6489 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
6490 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
6492 unsigned dest = MI->getOperand(0).getReg();
6493 unsigned ptrA = MI->getOperand(1).getReg();
6494 unsigned ptrB = MI->getOperand(2).getReg();
6495 unsigned oldval = MI->getOperand(3).getReg();
6496 unsigned newval = MI->getOperand(4).getReg();
6497 DebugLoc dl = MI->getDebugLoc();
6499 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6500 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6501 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6502 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6503 F->insert(It, loop1MBB);
6504 F->insert(It, loop2MBB);
6505 F->insert(It, midMBB);
6506 F->insert(It, exitMBB);
6507 exitMBB->splice(exitMBB->begin(), BB,
6508 llvm::next(MachineBasicBlock::iterator(MI)),
6510 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6514 // fallthrough --> loopMBB
6515 BB->addSuccessor(loop1MBB);
6518 // l[wd]arx dest, ptr
6519 // cmp[wd] dest, oldval
6522 // st[wd]cx. newval, ptr
6526 // st[wd]cx. dest, ptr
6529 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6530 .addReg(ptrA).addReg(ptrB);
6531 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
6532 .addReg(oldval).addReg(dest);
6533 BuildMI(BB, dl, TII->get(PPC::BCC))
6534 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6535 BB->addSuccessor(loop2MBB);
6536 BB->addSuccessor(midMBB);
6539 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6540 .addReg(newval).addReg(ptrA).addReg(ptrB);
6541 BuildMI(BB, dl, TII->get(PPC::BCC))
6542 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6543 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6544 BB->addSuccessor(loop1MBB);
6545 BB->addSuccessor(exitMBB);
6548 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6549 .addReg(dest).addReg(ptrA).addReg(ptrB);
6550 BB->addSuccessor(exitMBB);
6555 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
6556 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
6557 // We must use 64-bit registers for addresses when targeting 64-bit,
6558 // since we're actually doing arithmetic on them. Other registers
6560 bool is64bit = PPCSubTarget.isPPC64();
6561 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
6563 unsigned dest = MI->getOperand(0).getReg();
6564 unsigned ptrA = MI->getOperand(1).getReg();
6565 unsigned ptrB = MI->getOperand(2).getReg();
6566 unsigned oldval = MI->getOperand(3).getReg();
6567 unsigned newval = MI->getOperand(4).getReg();
6568 DebugLoc dl = MI->getDebugLoc();
6570 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6571 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6572 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6573 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6574 F->insert(It, loop1MBB);
6575 F->insert(It, loop2MBB);
6576 F->insert(It, midMBB);
6577 F->insert(It, exitMBB);
6578 exitMBB->splice(exitMBB->begin(), BB,
6579 llvm::next(MachineBasicBlock::iterator(MI)),
6581 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6583 MachineRegisterInfo &RegInfo = F->getRegInfo();
6584 const TargetRegisterClass *RC =
6585 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6586 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6587 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6588 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6589 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6590 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
6591 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
6592 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
6593 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
6594 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6595 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6596 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6597 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6598 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6599 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6601 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
6602 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6605 // fallthrough --> loopMBB
6606 BB->addSuccessor(loop1MBB);
6608 // The 4-byte load must be aligned, while a char or short may be
6609 // anywhere in the word. Hence all this nasty bookkeeping code.
6610 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6611 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6612 // xori shift, shift1, 24 [16]
6613 // rlwinm ptr, ptr1, 0, 0, 29
6614 // slw newval2, newval, shift
6615 // slw oldval2, oldval,shift
6616 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6617 // slw mask, mask2, shift
6618 // and newval3, newval2, mask
6619 // and oldval3, oldval2, mask
6621 // lwarx tmpDest, ptr
6622 // and tmp, tmpDest, mask
6623 // cmpw tmp, oldval3
6626 // andc tmp2, tmpDest, mask
6627 // or tmp4, tmp2, newval3
6632 // stwcx. tmpDest, ptr
6634 // srw dest, tmpDest, shift
6635 if (ptrA != ZeroReg) {
6636 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6637 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6638 .addReg(ptrA).addReg(ptrB);
6642 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6643 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6644 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6645 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6647 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6648 .addReg(Ptr1Reg).addImm(0).addImm(61);
6650 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6651 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6652 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
6653 .addReg(newval).addReg(ShiftReg);
6654 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
6655 .addReg(oldval).addReg(ShiftReg);
6657 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6659 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6660 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
6661 .addReg(Mask3Reg).addImm(65535);
6663 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6664 .addReg(Mask2Reg).addReg(ShiftReg);
6665 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
6666 .addReg(NewVal2Reg).addReg(MaskReg);
6667 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
6668 .addReg(OldVal2Reg).addReg(MaskReg);
6671 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6672 .addReg(ZeroReg).addReg(PtrReg);
6673 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
6674 .addReg(TmpDestReg).addReg(MaskReg);
6675 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
6676 .addReg(TmpReg).addReg(OldVal3Reg);
6677 BuildMI(BB, dl, TII->get(PPC::BCC))
6678 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6679 BB->addSuccessor(loop2MBB);
6680 BB->addSuccessor(midMBB);
6683 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
6684 .addReg(TmpDestReg).addReg(MaskReg);
6685 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
6686 .addReg(Tmp2Reg).addReg(NewVal3Reg);
6687 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
6688 .addReg(ZeroReg).addReg(PtrReg);
6689 BuildMI(BB, dl, TII->get(PPC::BCC))
6690 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6691 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6692 BB->addSuccessor(loop1MBB);
6693 BB->addSuccessor(exitMBB);
6696 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
6697 .addReg(ZeroReg).addReg(PtrReg);
6698 BB->addSuccessor(exitMBB);
6703 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
6705 } else if (MI->getOpcode() == PPC::FADDrtz) {
6706 // This pseudo performs an FADD with rounding mode temporarily forced
6707 // to round-to-zero. We emit this via custom inserter since the FPSCR
6708 // is not modeled at the SelectionDAG level.
6709 unsigned Dest = MI->getOperand(0).getReg();
6710 unsigned Src1 = MI->getOperand(1).getReg();
6711 unsigned Src2 = MI->getOperand(2).getReg();
6712 DebugLoc dl = MI->getDebugLoc();
6714 MachineRegisterInfo &RegInfo = F->getRegInfo();
6715 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
6717 // Save FPSCR value.
6718 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
6720 // Set rounding mode to round-to-zero.
6721 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
6722 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
6724 // Perform addition.
6725 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
6727 // Restore FPSCR value.
6728 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg);
6730 llvm_unreachable("Unexpected instr type to insert");
6733 MI->eraseFromParent(); // The pseudo instruction is gone now.
6737 //===----------------------------------------------------------------------===//
6738 // Target Optimization Hooks
6739 //===----------------------------------------------------------------------===//
6741 SDValue PPCTargetLowering::DAGCombineFastRecip(SDValue Op,
6742 DAGCombinerInfo &DCI) const {
6743 if (DCI.isAfterLegalizeVectorOps())
6746 EVT VT = Op.getValueType();
6748 if ((VT == MVT::f32 && PPCSubTarget.hasFRES()) ||
6749 (VT == MVT::f64 && PPCSubTarget.hasFRE()) ||
6750 (VT == MVT::v4f32 && PPCSubTarget.hasAltivec())) {
6752 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
6753 // For the reciprocal, we need to find the zero of the function:
6754 // F(X) = A X - 1 [which has a zero at X = 1/A]
6756 // X_{i+1} = X_i (2 - A X_i) = X_i + X_i (1 - A X_i) [this second form
6757 // does not require additional intermediate precision]
6759 // Convergence is quadratic, so we essentially double the number of digits
6760 // correct after every iteration. The minimum architected relative
6761 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
6762 // 23 digits and double has 52 digits.
6763 int Iterations = PPCSubTarget.hasRecipPrec() ? 1 : 3;
6764 if (VT.getScalarType() == MVT::f64)
6767 SelectionDAG &DAG = DCI.DAG;
6771 DAG.getConstantFP(1.0, VT.getScalarType());
6772 if (VT.isVector()) {
6773 assert(VT.getVectorNumElements() == 4 &&
6774 "Unknown vector type");
6775 FPOne = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
6776 FPOne, FPOne, FPOne, FPOne);
6779 SDValue Est = DAG.getNode(PPCISD::FRE, dl, VT, Op);
6780 DCI.AddToWorklist(Est.getNode());
6782 // Newton iterations: Est = Est + Est (1 - Arg * Est)
6783 for (int i = 0; i < Iterations; ++i) {
6784 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Op, Est);
6785 DCI.AddToWorklist(NewEst.getNode());
6787 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPOne, NewEst);
6788 DCI.AddToWorklist(NewEst.getNode());
6790 NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
6791 DCI.AddToWorklist(NewEst.getNode());
6793 Est = DAG.getNode(ISD::FADD, dl, VT, Est, NewEst);
6794 DCI.AddToWorklist(Est.getNode());
6803 SDValue PPCTargetLowering::DAGCombineFastRecipFSQRT(SDValue Op,
6804 DAGCombinerInfo &DCI) const {
6805 if (DCI.isAfterLegalizeVectorOps())
6808 EVT VT = Op.getValueType();
6810 if ((VT == MVT::f32 && PPCSubTarget.hasFRSQRTES()) ||
6811 (VT == MVT::f64 && PPCSubTarget.hasFRSQRTE()) ||
6812 (VT == MVT::v4f32 && PPCSubTarget.hasAltivec())) {
6814 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
6815 // For the reciprocal sqrt, we need to find the zero of the function:
6816 // F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
6818 // X_{i+1} = X_i (1.5 - A X_i^2 / 2)
6819 // As a result, we precompute A/2 prior to the iteration loop.
6821 // Convergence is quadratic, so we essentially double the number of digits
6822 // correct after every iteration. The minimum architected relative
6823 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
6824 // 23 digits and double has 52 digits.
6825 int Iterations = PPCSubTarget.hasRecipPrec() ? 1 : 3;
6826 if (VT.getScalarType() == MVT::f64)
6829 SelectionDAG &DAG = DCI.DAG;
6832 SDValue FPThreeHalves =
6833 DAG.getConstantFP(1.5, VT.getScalarType());
6834 if (VT.isVector()) {
6835 assert(VT.getVectorNumElements() == 4 &&
6836 "Unknown vector type");
6837 FPThreeHalves = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
6838 FPThreeHalves, FPThreeHalves,
6839 FPThreeHalves, FPThreeHalves);
6842 SDValue Est = DAG.getNode(PPCISD::FRSQRTE, dl, VT, Op);
6843 DCI.AddToWorklist(Est.getNode());
6845 // We now need 0.5*Arg which we can write as (1.5*Arg - Arg) so that
6846 // this entire sequence requires only one FP constant.
6847 SDValue HalfArg = DAG.getNode(ISD::FMUL, dl, VT, FPThreeHalves, Op);
6848 DCI.AddToWorklist(HalfArg.getNode());
6850 HalfArg = DAG.getNode(ISD::FSUB, dl, VT, HalfArg, Op);
6851 DCI.AddToWorklist(HalfArg.getNode());
6853 // Newton iterations: Est = Est * (1.5 - HalfArg * Est * Est)
6854 for (int i = 0; i < Iterations; ++i) {
6855 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, Est);
6856 DCI.AddToWorklist(NewEst.getNode());
6858 NewEst = DAG.getNode(ISD::FMUL, dl, VT, HalfArg, NewEst);
6859 DCI.AddToWorklist(NewEst.getNode());
6861 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPThreeHalves, NewEst);
6862 DCI.AddToWorklist(NewEst.getNode());
6864 Est = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
6865 DCI.AddToWorklist(Est.getNode());
6874 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
6875 // not enforce equality of the chain operands.
6876 static bool isConsecutiveLS(LSBaseSDNode *LS, LSBaseSDNode *Base,
6877 unsigned Bytes, int Dist,
6878 SelectionDAG &DAG) {
6879 EVT VT = LS->getMemoryVT();
6880 if (VT.getSizeInBits() / 8 != Bytes)
6883 SDValue Loc = LS->getBasePtr();
6884 SDValue BaseLoc = Base->getBasePtr();
6885 if (Loc.getOpcode() == ISD::FrameIndex) {
6886 if (BaseLoc.getOpcode() != ISD::FrameIndex)
6888 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6889 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
6890 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
6891 int FS = MFI->getObjectSize(FI);
6892 int BFS = MFI->getObjectSize(BFI);
6893 if (FS != BFS || FS != (int)Bytes) return false;
6894 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
6898 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
6899 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
6902 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6903 const GlobalValue *GV1 = NULL;
6904 const GlobalValue *GV2 = NULL;
6905 int64_t Offset1 = 0;
6906 int64_t Offset2 = 0;
6907 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
6908 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
6909 if (isGA1 && isGA2 && GV1 == GV2)
6910 return Offset1 == (Offset2 + Dist*Bytes);
6914 // Return true is there is a nearyby consecutive load to the one provided
6915 // (regardless of alignment). We search up and down the chain, looking though
6916 // token factors and other loads (but nothing else). As a result, a true
6917 // results indicates that it is safe to create a new consecutive load adjacent
6918 // to the load provided.
6919 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
6920 SDValue Chain = LD->getChain();
6921 EVT VT = LD->getMemoryVT();
6923 SmallSet<SDNode *, 16> LoadRoots;
6924 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
6925 SmallSet<SDNode *, 16> Visited;
6927 // First, search up the chain, branching to follow all token-factor operands.
6928 // If we find a consecutive load, then we're done, otherwise, record all
6929 // nodes just above the top-level loads and token factors.
6930 while (!Queue.empty()) {
6931 SDNode *ChainNext = Queue.pop_back_val();
6932 if (!Visited.insert(ChainNext))
6935 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(ChainNext)) {
6936 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
6939 if (!Visited.count(ChainLD->getChain().getNode()))
6940 Queue.push_back(ChainLD->getChain().getNode());
6941 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
6942 for (SDNode::op_iterator O = ChainNext->op_begin(),
6943 OE = ChainNext->op_end(); O != OE; ++O)
6944 if (!Visited.count(O->getNode()))
6945 Queue.push_back(O->getNode());
6947 LoadRoots.insert(ChainNext);
6950 // Second, search down the chain, starting from the top-level nodes recorded
6951 // in the first phase. These top-level nodes are the nodes just above all
6952 // loads and token factors. Starting with their uses, recursively look though
6953 // all loads (just the chain uses) and token factors to find a consecutive
6958 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
6959 IE = LoadRoots.end(); I != IE; ++I) {
6960 Queue.push_back(*I);
6962 while (!Queue.empty()) {
6963 SDNode *LoadRoot = Queue.pop_back_val();
6964 if (!Visited.insert(LoadRoot))
6967 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(LoadRoot))
6968 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
6971 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
6972 UE = LoadRoot->use_end(); UI != UE; ++UI)
6973 if (((isa<LoadSDNode>(*UI) &&
6974 cast<LoadSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
6975 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
6976 Queue.push_back(*UI);
6983 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
6984 DAGCombinerInfo &DCI) const {
6985 const TargetMachine &TM = getTargetMachine();
6986 SelectionDAG &DAG = DCI.DAG;
6988 switch (N->getOpcode()) {
6991 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6992 if (C->isNullValue()) // 0 << V -> 0.
6993 return N->getOperand(0);
6997 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6998 if (C->isNullValue()) // 0 >>u V -> 0.
6999 return N->getOperand(0);
7003 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
7004 if (C->isNullValue() || // 0 >>s V -> 0.
7005 C->isAllOnesValue()) // -1 >>s V -> -1.
7006 return N->getOperand(0);
7010 assert(TM.Options.UnsafeFPMath &&
7011 "Reciprocal estimates require UnsafeFPMath");
7013 if (N->getOperand(1).getOpcode() == ISD::FSQRT) {
7015 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0), DCI);
7016 if (RV.getNode() != 0) {
7017 DCI.AddToWorklist(RV.getNode());
7018 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7019 N->getOperand(0), RV);
7021 } else if (N->getOperand(1).getOpcode() == ISD::FP_EXTEND &&
7022 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
7024 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
7026 if (RV.getNode() != 0) {
7027 DCI.AddToWorklist(RV.getNode());
7028 RV = DAG.getNode(ISD::FP_EXTEND, SDLoc(N->getOperand(1)),
7029 N->getValueType(0), RV);
7030 DCI.AddToWorklist(RV.getNode());
7031 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7032 N->getOperand(0), RV);
7034 } else if (N->getOperand(1).getOpcode() == ISD::FP_ROUND &&
7035 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
7037 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
7039 if (RV.getNode() != 0) {
7040 DCI.AddToWorklist(RV.getNode());
7041 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N->getOperand(1)),
7042 N->getValueType(0), RV,
7043 N->getOperand(1).getOperand(1));
7044 DCI.AddToWorklist(RV.getNode());
7045 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7046 N->getOperand(0), RV);
7050 SDValue RV = DAGCombineFastRecip(N->getOperand(1), DCI);
7051 if (RV.getNode() != 0) {
7052 DCI.AddToWorklist(RV.getNode());
7053 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7054 N->getOperand(0), RV);
7060 assert(TM.Options.UnsafeFPMath &&
7061 "Reciprocal estimates require UnsafeFPMath");
7063 // Compute this as 1/(1/sqrt(X)), which is the reciprocal of the
7065 SDValue RV = DAGCombineFastRecipFSQRT(N->getOperand(0), DCI);
7066 if (RV.getNode() != 0) {
7067 DCI.AddToWorklist(RV.getNode());
7068 RV = DAGCombineFastRecip(RV, DCI);
7069 if (RV.getNode() != 0) {
7070 // Unfortunately, RV is now NaN if the input was exactly 0. Select out
7071 // this case and force the answer to 0.
7073 EVT VT = RV.getValueType();
7075 SDValue Zero = DAG.getConstantFP(0.0, VT.getScalarType());
7076 if (VT.isVector()) {
7077 assert(VT.getVectorNumElements() == 4 && "Unknown vector type");
7078 Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Zero, Zero, Zero, Zero);
7082 DAG.getSetCC(dl, getSetCCResultType(*DAG.getContext(), VT),
7083 N->getOperand(0), Zero, ISD::SETEQ);
7084 DCI.AddToWorklist(ZeroCmp.getNode());
7085 DCI.AddToWorklist(RV.getNode());
7087 RV = DAG.getNode(VT.isVector() ? ISD::VSELECT : ISD::SELECT, dl, VT,
7095 case ISD::SINT_TO_FP:
7096 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
7097 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
7098 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
7099 // We allow the src/dst to be either f32/f64, but the intermediate
7100 // type must be i64.
7101 if (N->getOperand(0).getValueType() == MVT::i64 &&
7102 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
7103 SDValue Val = N->getOperand(0).getOperand(0);
7104 if (Val.getValueType() == MVT::f32) {
7105 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
7106 DCI.AddToWorklist(Val.getNode());
7109 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
7110 DCI.AddToWorklist(Val.getNode());
7111 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
7112 DCI.AddToWorklist(Val.getNode());
7113 if (N->getValueType(0) == MVT::f32) {
7114 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
7115 DAG.getIntPtrConstant(0));
7116 DCI.AddToWorklist(Val.getNode());
7119 } else if (N->getOperand(0).getValueType() == MVT::i32) {
7120 // If the intermediate type is i32, we can avoid the load/store here
7127 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
7128 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
7129 !cast<StoreSDNode>(N)->isTruncatingStore() &&
7130 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
7131 N->getOperand(1).getValueType() == MVT::i32 &&
7132 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
7133 SDValue Val = N->getOperand(1).getOperand(0);
7134 if (Val.getValueType() == MVT::f32) {
7135 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
7136 DCI.AddToWorklist(Val.getNode());
7138 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
7139 DCI.AddToWorklist(Val.getNode());
7142 N->getOperand(0), Val, N->getOperand(2),
7143 DAG.getValueType(N->getOperand(1).getValueType())
7146 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
7147 DAG.getVTList(MVT::Other), Ops, array_lengthof(Ops),
7148 cast<StoreSDNode>(N)->getMemoryVT(),
7149 cast<StoreSDNode>(N)->getMemOperand());
7150 DCI.AddToWorklist(Val.getNode());
7154 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
7155 if (cast<StoreSDNode>(N)->isUnindexed() &&
7156 N->getOperand(1).getOpcode() == ISD::BSWAP &&
7157 N->getOperand(1).getNode()->hasOneUse() &&
7158 (N->getOperand(1).getValueType() == MVT::i32 ||
7159 N->getOperand(1).getValueType() == MVT::i16 ||
7160 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
7161 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
7162 N->getOperand(1).getValueType() == MVT::i64))) {
7163 SDValue BSwapOp = N->getOperand(1).getOperand(0);
7164 // Do an any-extend to 32-bits if this is a half-word input.
7165 if (BSwapOp.getValueType() == MVT::i16)
7166 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
7169 N->getOperand(0), BSwapOp, N->getOperand(2),
7170 DAG.getValueType(N->getOperand(1).getValueType())
7173 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
7174 Ops, array_lengthof(Ops),
7175 cast<StoreSDNode>(N)->getMemoryVT(),
7176 cast<StoreSDNode>(N)->getMemOperand());
7180 LoadSDNode *LD = cast<LoadSDNode>(N);
7181 EVT VT = LD->getValueType(0);
7182 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
7183 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
7184 if (ISD::isNON_EXTLoad(N) && VT.isVector() &&
7185 TM.getSubtarget<PPCSubtarget>().hasAltivec() &&
7186 (VT == MVT::v16i8 || VT == MVT::v8i16 ||
7187 VT == MVT::v4i32 || VT == MVT::v4f32) &&
7188 LD->getAlignment() < ABIAlignment) {
7189 // This is a type-legal unaligned Altivec load.
7190 SDValue Chain = LD->getChain();
7191 SDValue Ptr = LD->getBasePtr();
7193 // This implements the loading of unaligned vectors as described in
7194 // the venerable Apple Velocity Engine overview. Specifically:
7195 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
7196 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
7198 // The general idea is to expand a sequence of one or more unaligned
7199 // loads into a alignment-based permutation-control instruction (lvsl),
7200 // a series of regular vector loads (which always truncate their
7201 // input address to an aligned address), and a series of permutations.
7202 // The results of these permutations are the requested loaded values.
7203 // The trick is that the last "extra" load is not taken from the address
7204 // you might suspect (sizeof(vector) bytes after the last requested
7205 // load), but rather sizeof(vector) - 1 bytes after the last
7206 // requested vector. The point of this is to avoid a page fault if the
7207 // base address happend to be aligned. This works because if the base
7208 // address is aligned, then adding less than a full vector length will
7209 // cause the last vector in the sequence to be (re)loaded. Otherwise,
7210 // the next vector will be fetched as you might suspect was necessary.
7212 // We might be able to reuse the permutation generation from
7213 // a different base address offset from this one by an aligned amount.
7214 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
7215 // optimization later.
7216 SDValue PermCntl = BuildIntrinsicOp(Intrinsic::ppc_altivec_lvsl, Ptr,
7217 DAG, dl, MVT::v16i8);
7219 // Refine the alignment of the original load (a "new" load created here
7220 // which was identical to the first except for the alignment would be
7221 // merged with the existing node regardless).
7222 MachineFunction &MF = DAG.getMachineFunction();
7223 MachineMemOperand *MMO =
7224 MF.getMachineMemOperand(LD->getPointerInfo(),
7225 LD->getMemOperand()->getFlags(),
7226 LD->getMemoryVT().getStoreSize(),
7228 LD->refineAlignment(MMO);
7229 SDValue BaseLoad = SDValue(LD, 0);
7231 // Note that the value of IncOffset (which is provided to the next
7232 // load's pointer info offset value, and thus used to calculate the
7233 // alignment), and the value of IncValue (which is actually used to
7234 // increment the pointer value) are different! This is because we
7235 // require the next load to appear to be aligned, even though it
7236 // is actually offset from the base pointer by a lesser amount.
7237 int IncOffset = VT.getSizeInBits() / 8;
7238 int IncValue = IncOffset;
7240 // Walk (both up and down) the chain looking for another load at the real
7241 // (aligned) offset (the alignment of the other load does not matter in
7242 // this case). If found, then do not use the offset reduction trick, as
7243 // that will prevent the loads from being later combined (as they would
7244 // otherwise be duplicates).
7245 if (!findConsecutiveLoad(LD, DAG))
7248 SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
7249 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
7252 DAG.getLoad(VT, dl, Chain, Ptr,
7253 LD->getPointerInfo().getWithOffset(IncOffset),
7254 LD->isVolatile(), LD->isNonTemporal(),
7255 LD->isInvariant(), ABIAlignment);
7257 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
7258 BaseLoad.getValue(1), ExtraLoad.getValue(1));
7260 if (BaseLoad.getValueType() != MVT::v4i32)
7261 BaseLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, BaseLoad);
7263 if (ExtraLoad.getValueType() != MVT::v4i32)
7264 ExtraLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, ExtraLoad);
7266 SDValue Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
7267 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
7269 if (VT != MVT::v4i32)
7270 Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm);
7272 // Now we need to be really careful about how we update the users of the
7273 // original load. We cannot just call DCI.CombineTo (or
7274 // DAG.ReplaceAllUsesWith for that matter), because the load still has
7275 // uses created here (the permutation for example) that need to stay.
7276 SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
7278 SDUse &Use = UI.getUse();
7280 // Note: BaseLoad is checked here because it might not be N, but a
7282 if (User == Perm.getNode() || User == BaseLoad.getNode() ||
7283 User == TF.getNode() || Use.getResNo() > 1) {
7288 SDValue To = Use.getResNo() ? TF : Perm;
7291 SmallVector<SDValue, 8> Ops;
7292 for (SDNode::op_iterator O = User->op_begin(),
7293 OE = User->op_end(); O != OE; ++O) {
7300 DAG.UpdateNodeOperands(User, Ops.data(), Ops.size());
7303 return SDValue(N, 0);
7307 case ISD::INTRINSIC_WO_CHAIN:
7308 if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() ==
7309 Intrinsic::ppc_altivec_lvsl &&
7310 N->getOperand(1)->getOpcode() == ISD::ADD) {
7311 SDValue Add = N->getOperand(1);
7313 if (DAG.MaskedValueIsZero(Add->getOperand(1),
7314 APInt::getAllOnesValue(4 /* 16 byte alignment */).zext(
7315 Add.getValueType().getScalarType().getSizeInBits()))) {
7316 SDNode *BasePtr = Add->getOperand(0).getNode();
7317 for (SDNode::use_iterator UI = BasePtr->use_begin(),
7318 UE = BasePtr->use_end(); UI != UE; ++UI) {
7319 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
7320 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() ==
7321 Intrinsic::ppc_altivec_lvsl) {
7322 // We've found another LVSL, and this address if an aligned
7323 // multiple of that one. The results will be the same, so use the
7324 // one we've just found instead.
7326 return SDValue(*UI, 0);
7334 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
7335 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
7336 N->getOperand(0).hasOneUse() &&
7337 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
7338 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
7339 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
7340 N->getValueType(0) == MVT::i64))) {
7341 SDValue Load = N->getOperand(0);
7342 LoadSDNode *LD = cast<LoadSDNode>(Load);
7343 // Create the byte-swapping load.
7345 LD->getChain(), // Chain
7346 LD->getBasePtr(), // Ptr
7347 DAG.getValueType(N->getValueType(0)) // VT
7350 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
7351 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
7352 MVT::i64 : MVT::i32, MVT::Other),
7353 Ops, 3, LD->getMemoryVT(), LD->getMemOperand());
7355 // If this is an i16 load, insert the truncate.
7356 SDValue ResVal = BSLoad;
7357 if (N->getValueType(0) == MVT::i16)
7358 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
7360 // First, combine the bswap away. This makes the value produced by the
7362 DCI.CombineTo(N, ResVal);
7364 // Next, combine the load away, we give it a bogus result value but a real
7365 // chain result. The result value is dead because the bswap is dead.
7366 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
7368 // Return N so it doesn't get rechecked!
7369 return SDValue(N, 0);
7373 case PPCISD::VCMP: {
7374 // If a VCMPo node already exists with exactly the same operands as this
7375 // node, use its result instead of this node (VCMPo computes both a CR6 and
7376 // a normal output).
7378 if (!N->getOperand(0).hasOneUse() &&
7379 !N->getOperand(1).hasOneUse() &&
7380 !N->getOperand(2).hasOneUse()) {
7382 // Scan all of the users of the LHS, looking for VCMPo's that match.
7383 SDNode *VCMPoNode = 0;
7385 SDNode *LHSN = N->getOperand(0).getNode();
7386 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
7388 if (UI->getOpcode() == PPCISD::VCMPo &&
7389 UI->getOperand(1) == N->getOperand(1) &&
7390 UI->getOperand(2) == N->getOperand(2) &&
7391 UI->getOperand(0) == N->getOperand(0)) {
7396 // If there is no VCMPo node, or if the flag value has a single use, don't
7398 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
7401 // Look at the (necessarily single) use of the flag value. If it has a
7402 // chain, this transformation is more complex. Note that multiple things
7403 // could use the value result, which we should ignore.
7404 SDNode *FlagUser = 0;
7405 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
7406 FlagUser == 0; ++UI) {
7407 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
7409 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
7410 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
7417 // If the user is a MFOCRF instruction, we know this is safe.
7418 // Otherwise we give up for right now.
7419 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
7420 return SDValue(VCMPoNode, 0);
7425 // If this is a branch on an altivec predicate comparison, lower this so
7426 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
7427 // lowering is done pre-legalize, because the legalizer lowers the predicate
7428 // compare down to code that is difficult to reassemble.
7429 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
7430 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
7432 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
7433 // value. If so, pass-through the AND to get to the intrinsic.
7434 if (LHS.getOpcode() == ISD::AND &&
7435 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
7436 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
7437 Intrinsic::ppc_is_decremented_ctr_nonzero &&
7438 isa<ConstantSDNode>(LHS.getOperand(1)) &&
7439 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
7441 LHS = LHS.getOperand(0);
7443 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
7444 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
7445 Intrinsic::ppc_is_decremented_ctr_nonzero &&
7446 isa<ConstantSDNode>(RHS)) {
7447 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
7448 "Counter decrement comparison is not EQ or NE");
7450 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
7451 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
7452 (CC == ISD::SETNE && !Val);
7454 // We now need to make the intrinsic dead (it cannot be instruction
7456 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
7457 assert(LHS.getNode()->hasOneUse() &&
7458 "Counter decrement has more than one use");
7460 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
7461 N->getOperand(0), N->getOperand(4));
7467 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
7468 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
7469 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
7470 assert(isDot && "Can't compare against a vector result!");
7472 // If this is a comparison against something other than 0/1, then we know
7473 // that the condition is never/always true.
7474 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
7475 if (Val != 0 && Val != 1) {
7476 if (CC == ISD::SETEQ) // Cond never true, remove branch.
7477 return N->getOperand(0);
7478 // Always !=, turn it into an unconditional branch.
7479 return DAG.getNode(ISD::BR, dl, MVT::Other,
7480 N->getOperand(0), N->getOperand(4));
7483 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
7485 // Create the PPCISD altivec 'dot' comparison node.
7487 LHS.getOperand(2), // LHS of compare
7488 LHS.getOperand(3), // RHS of compare
7489 DAG.getConstant(CompareOpc, MVT::i32)
7491 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
7492 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
7494 // Unpack the result based on how the target uses it.
7495 PPC::Predicate CompOpc;
7496 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
7497 default: // Can't happen, don't crash on invalid number though.
7498 case 0: // Branch on the value of the EQ bit of CR6.
7499 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
7501 case 1: // Branch on the inverted value of the EQ bit of CR6.
7502 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
7504 case 2: // Branch on the value of the LT bit of CR6.
7505 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
7507 case 3: // Branch on the inverted value of the LT bit of CR6.
7508 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
7512 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
7513 DAG.getConstant(CompOpc, MVT::i32),
7514 DAG.getRegister(PPC::CR6, MVT::i32),
7515 N->getOperand(4), CompNode.getValue(1));
7524 //===----------------------------------------------------------------------===//
7525 // Inline Assembly Support
7526 //===----------------------------------------------------------------------===//
7528 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
7531 const SelectionDAG &DAG,
7532 unsigned Depth) const {
7533 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
7534 switch (Op.getOpcode()) {
7536 case PPCISD::LBRX: {
7537 // lhbrx is known to have the top bits cleared out.
7538 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
7539 KnownZero = 0xFFFF0000;
7542 case ISD::INTRINSIC_WO_CHAIN: {
7543 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
7545 case Intrinsic::ppc_altivec_vcmpbfp_p:
7546 case Intrinsic::ppc_altivec_vcmpeqfp_p:
7547 case Intrinsic::ppc_altivec_vcmpequb_p:
7548 case Intrinsic::ppc_altivec_vcmpequh_p:
7549 case Intrinsic::ppc_altivec_vcmpequw_p:
7550 case Intrinsic::ppc_altivec_vcmpgefp_p:
7551 case Intrinsic::ppc_altivec_vcmpgtfp_p:
7552 case Intrinsic::ppc_altivec_vcmpgtsb_p:
7553 case Intrinsic::ppc_altivec_vcmpgtsh_p:
7554 case Intrinsic::ppc_altivec_vcmpgtsw_p:
7555 case Intrinsic::ppc_altivec_vcmpgtub_p:
7556 case Intrinsic::ppc_altivec_vcmpgtuh_p:
7557 case Intrinsic::ppc_altivec_vcmpgtuw_p:
7558 KnownZero = ~1U; // All bits but the low one are known to be zero.
7566 /// getConstraintType - Given a constraint, return the type of
7567 /// constraint it is for this target.
7568 PPCTargetLowering::ConstraintType
7569 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
7570 if (Constraint.size() == 1) {
7571 switch (Constraint[0]) {
7578 return C_RegisterClass;
7580 // FIXME: While Z does indicate a memory constraint, it specifically
7581 // indicates an r+r address (used in conjunction with the 'y' modifier
7582 // in the replacement string). Currently, we're forcing the base
7583 // register to be r0 in the asm printer (which is interpreted as zero)
7584 // and forming the complete address in the second register. This is
7589 return TargetLowering::getConstraintType(Constraint);
7592 /// Examine constraint type and operand type and determine a weight value.
7593 /// This object must already have been set up with the operand type
7594 /// and the current alternative constraint selected.
7595 TargetLowering::ConstraintWeight
7596 PPCTargetLowering::getSingleConstraintMatchWeight(
7597 AsmOperandInfo &info, const char *constraint) const {
7598 ConstraintWeight weight = CW_Invalid;
7599 Value *CallOperandVal = info.CallOperandVal;
7600 // If we don't have a value, we can't do a match,
7601 // but allow it at the lowest weight.
7602 if (CallOperandVal == NULL)
7604 Type *type = CallOperandVal->getType();
7605 // Look at the constraint type.
7606 switch (*constraint) {
7608 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
7611 if (type->isIntegerTy())
7612 weight = CW_Register;
7615 if (type->isFloatTy())
7616 weight = CW_Register;
7619 if (type->isDoubleTy())
7620 weight = CW_Register;
7623 if (type->isVectorTy())
7624 weight = CW_Register;
7627 weight = CW_Register;
7636 std::pair<unsigned, const TargetRegisterClass*>
7637 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
7639 if (Constraint.size() == 1) {
7640 // GCC RS6000 Constraint Letters
7641 switch (Constraint[0]) {
7643 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
7644 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
7645 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
7647 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
7648 return std::make_pair(0U, &PPC::G8RCRegClass);
7649 return std::make_pair(0U, &PPC::GPRCRegClass);
7651 if (VT == MVT::f32 || VT == MVT::i32)
7652 return std::make_pair(0U, &PPC::F4RCRegClass);
7653 if (VT == MVT::f64 || VT == MVT::i64)
7654 return std::make_pair(0U, &PPC::F8RCRegClass);
7657 return std::make_pair(0U, &PPC::VRRCRegClass);
7659 return std::make_pair(0U, &PPC::CRRCRegClass);
7663 std::pair<unsigned, const TargetRegisterClass*> R =
7664 TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
7666 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
7667 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
7668 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
7670 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
7671 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
7672 if (R.first && VT == MVT::i64 && PPCSubTarget.isPPC64() &&
7673 PPC::GPRCRegClass.contains(R.first)) {
7674 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
7675 return std::make_pair(TRI->getMatchingSuperReg(R.first,
7676 PPC::sub_32, &PPC::G8RCRegClass),
7677 &PPC::G8RCRegClass);
7684 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
7685 /// vector. If it is invalid, don't add anything to Ops.
7686 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
7687 std::string &Constraint,
7688 std::vector<SDValue>&Ops,
7689 SelectionDAG &DAG) const {
7690 SDValue Result(0,0);
7692 // Only support length 1 constraints.
7693 if (Constraint.length() > 1) return;
7695 char Letter = Constraint[0];
7706 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
7707 if (!CST) return; // Must be an immediate to match.
7708 unsigned Value = CST->getZExtValue();
7710 default: llvm_unreachable("Unknown constraint letter!");
7711 case 'I': // "I" is a signed 16-bit constant.
7712 if ((short)Value == (int)Value)
7713 Result = DAG.getTargetConstant(Value, Op.getValueType());
7715 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
7716 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
7717 if ((short)Value == 0)
7718 Result = DAG.getTargetConstant(Value, Op.getValueType());
7720 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
7721 if ((Value >> 16) == 0)
7722 Result = DAG.getTargetConstant(Value, Op.getValueType());
7724 case 'M': // "M" is a constant that is greater than 31.
7726 Result = DAG.getTargetConstant(Value, Op.getValueType());
7728 case 'N': // "N" is a positive constant that is an exact power of two.
7729 if ((int)Value > 0 && isPowerOf2_32(Value))
7730 Result = DAG.getTargetConstant(Value, Op.getValueType());
7732 case 'O': // "O" is the constant zero.
7734 Result = DAG.getTargetConstant(Value, Op.getValueType());
7736 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
7737 if ((short)-Value == (int)-Value)
7738 Result = DAG.getTargetConstant(Value, Op.getValueType());
7745 if (Result.getNode()) {
7746 Ops.push_back(Result);
7750 // Handle standard constraint letters.
7751 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
7754 // isLegalAddressingMode - Return true if the addressing mode represented
7755 // by AM is legal for this target, for a load/store of the specified type.
7756 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
7758 // FIXME: PPC does not allow r+i addressing modes for vectors!
7760 // PPC allows a sign-extended 16-bit immediate field.
7761 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
7764 // No global is ever allowed as a base.
7768 // PPC only support r+r,
7770 case 0: // "r+i" or just "i", depending on HasBaseReg.
7773 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
7775 // Otherwise we have r+r or r+i.
7778 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
7780 // Allow 2*r as r+r.
7783 // No other scales are supported.
7790 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
7791 SelectionDAG &DAG) const {
7792 MachineFunction &MF = DAG.getMachineFunction();
7793 MachineFrameInfo *MFI = MF.getFrameInfo();
7794 MFI->setReturnAddressIsTaken(true);
7797 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7799 // Make sure the function does not optimize away the store of the RA to
7801 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
7802 FuncInfo->setLRStoreRequired();
7803 bool isPPC64 = PPCSubTarget.isPPC64();
7804 bool isDarwinABI = PPCSubTarget.isDarwinABI();
7807 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
7810 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
7811 isPPC64? MVT::i64 : MVT::i32);
7812 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7813 DAG.getNode(ISD::ADD, dl, getPointerTy(),
7815 MachinePointerInfo(), false, false, false, 0);
7818 // Just load the return address off the stack.
7819 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
7820 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7821 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
7824 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
7825 SelectionDAG &DAG) const {
7827 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7829 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
7830 bool isPPC64 = PtrVT == MVT::i64;
7832 MachineFunction &MF = DAG.getMachineFunction();
7833 MachineFrameInfo *MFI = MF.getFrameInfo();
7834 MFI->setFrameAddressIsTaken(true);
7836 // Naked functions never have a frame pointer, and so we use r1. For all
7837 // other functions, this decision must be delayed until during PEI.
7839 if (MF.getFunction()->getAttributes().hasAttribute(
7840 AttributeSet::FunctionIndex, Attribute::Naked))
7841 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
7843 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
7845 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
7848 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
7849 FrameAddr, MachinePointerInfo(), false, false,
7855 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
7856 // The PowerPC target isn't yet aware of offsets.
7860 /// getOptimalMemOpType - Returns the target specific optimal type for load
7861 /// and store operations as a result of memset, memcpy, and memmove
7862 /// lowering. If DstAlign is zero that means it's safe to destination
7863 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
7864 /// means there isn't a need to check it against alignment requirement,
7865 /// probably because the source does not need to be loaded. If 'IsMemset' is
7866 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
7867 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
7868 /// source is constant so it does not need to be loaded.
7869 /// It returns EVT::Other if the type should be determined using generic
7870 /// target-independent logic.
7871 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
7872 unsigned DstAlign, unsigned SrcAlign,
7873 bool IsMemset, bool ZeroMemset,
7875 MachineFunction &MF) const {
7876 if (this->PPCSubTarget.isPPC64()) {
7883 bool PPCTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
7885 if (DisablePPCUnaligned)
7888 // PowerPC supports unaligned memory access for simple non-vector types.
7889 // Although accessing unaligned addresses is not as efficient as accessing
7890 // aligned addresses, it is generally more efficient than manual expansion,
7891 // and generally only traps for software emulation when crossing page
7897 if (VT.getSimpleVT().isVector())
7900 if (VT == MVT::ppcf128)
7909 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
7910 VT = VT.getScalarType();
7915 switch (VT.getSimpleVT().SimpleTy) {
7926 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
7927 if (DisableILPPref || PPCSubTarget.enableMachineScheduler())
7928 return TargetLowering::getSchedulingPreference(N);
7933 // Create a fast isel object.
7935 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
7936 const TargetLibraryInfo *LibInfo) const {
7937 return PPC::createFastISel(FuncInfo, LibInfo);