1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCMachineFunctionInfo.h"
16 #include "PPCPredicates.h"
17 #include "PPCTargetMachine.h"
18 #include "PPCPerfectShuffle.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/VectorExtras.h"
21 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/PseudoSourceValue.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/Constants.h"
30 #include "llvm/Function.h"
31 #include "llvm/Intrinsics.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/Support/CommandLine.h"
37 static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc",
38 cl::desc("enable preincrement load/store generation on PPC (experimental)"),
41 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
42 : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) {
46 // Use _setjmp/_longjmp instead of setjmp/longjmp.
47 setUseUnderscoreSetJmp(true);
48 setUseUnderscoreLongJmp(true);
50 // Set up the register classes.
51 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
52 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
53 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
55 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
56 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
57 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand);
59 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
61 // PowerPC has pre-inc load and store's.
62 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
63 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
64 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
65 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
66 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
67 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
68 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
69 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
70 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
71 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
73 // Shortening conversions involving ppcf128 get expanded (2 regs -> 1 reg)
74 setConvertAction(MVT::ppcf128, MVT::f64, Expand);
75 setConvertAction(MVT::ppcf128, MVT::f32, Expand);
76 // This is used in the ppcf128->int sequence. Note it has different semantics
77 // from FP_ROUND: that rounds to nearest, this rounds to zero.
78 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
80 // PowerPC has no intrinsics for these particular operations
81 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
82 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
83 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
84 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
86 // PowerPC has no SREM/UREM instructions
87 setOperationAction(ISD::SREM, MVT::i32, Expand);
88 setOperationAction(ISD::UREM, MVT::i32, Expand);
89 setOperationAction(ISD::SREM, MVT::i64, Expand);
90 setOperationAction(ISD::UREM, MVT::i64, Expand);
92 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
93 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
94 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
95 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
96 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
97 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
98 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
99 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
100 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
102 // We don't support sin/cos/sqrt/fmod/pow
103 setOperationAction(ISD::FSIN , MVT::f64, Expand);
104 setOperationAction(ISD::FCOS , MVT::f64, Expand);
105 setOperationAction(ISD::FREM , MVT::f64, Expand);
106 setOperationAction(ISD::FPOW , MVT::f64, Expand);
107 setOperationAction(ISD::FSIN , MVT::f32, Expand);
108 setOperationAction(ISD::FCOS , MVT::f32, Expand);
109 setOperationAction(ISD::FREM , MVT::f32, Expand);
110 setOperationAction(ISD::FPOW , MVT::f32, Expand);
112 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
114 // If we're enabling GP optimizations, use hardware square root
115 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
116 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
117 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
120 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
121 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
123 // PowerPC does not have BSWAP, CTPOP or CTTZ
124 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
125 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
126 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
127 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
128 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
129 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
131 // PowerPC does not have ROTR
132 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
134 // PowerPC does not have Select
135 setOperationAction(ISD::SELECT, MVT::i32, Expand);
136 setOperationAction(ISD::SELECT, MVT::i64, Expand);
137 setOperationAction(ISD::SELECT, MVT::f32, Expand);
138 setOperationAction(ISD::SELECT, MVT::f64, Expand);
140 // PowerPC wants to turn select_cc of FP into fsel when possible.
141 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
142 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
144 // PowerPC wants to optimize integer setcc a bit
145 setOperationAction(ISD::SETCC, MVT::i32, Custom);
147 // PowerPC does not have BRCOND which requires SetCC
148 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
150 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
152 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
153 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
155 // PowerPC does not have [U|S]INT_TO_FP
156 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
157 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
159 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
160 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
161 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
162 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
164 // We cannot sextinreg(i1). Expand to shifts.
165 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
167 // Support label based line numbers.
168 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
169 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
171 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
172 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
173 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
174 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
177 // We want to legalize GlobalAddress and ConstantPool nodes into the
178 // appropriate instructions to materialize the address.
179 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
180 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
181 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
182 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
183 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
184 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
185 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
186 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
188 // RET must be custom lowered, to meet ABI requirements
189 setOperationAction(ISD::RET , MVT::Other, Custom);
191 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
192 setOperationAction(ISD::VASTART , MVT::Other, Custom);
194 // VAARG is custom lowered with ELF 32 ABI
195 if (TM.getSubtarget<PPCSubtarget>().isELF32_ABI())
196 setOperationAction(ISD::VAARG, MVT::Other, Custom);
198 setOperationAction(ISD::VAARG, MVT::Other, Expand);
200 // Use the default implementation.
201 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
202 setOperationAction(ISD::VAEND , MVT::Other, Expand);
203 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
204 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
205 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
206 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
208 // We want to custom lower some of our intrinsics.
209 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
211 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
212 // They also have instructions for converting between i64 and fp.
213 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
214 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
215 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
216 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
217 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
219 // FIXME: disable this lowered code. This generates 64-bit register values,
220 // and we don't model the fact that the top part is clobbered by calls. We
221 // need to flag these together so that the value isn't live across a call.
222 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
224 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
225 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
227 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
228 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
231 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
232 // 64-bit PowerPC implementations can support i64 types directly
233 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
234 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
235 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
237 // 32-bit PowerPC wants to expand i64 shifts itself.
238 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
239 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
240 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
243 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
244 // First set operation action for all vector types to expand. Then we
245 // will selectively turn on ones that can be effectively codegen'd.
246 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
247 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
248 // add/sub are legal for all supported vector VT's.
249 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal);
250 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal);
252 // We promote all shuffles to v16i8.
253 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote);
254 AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8);
256 // We promote all non-typed operations to v4i32.
257 setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote);
258 AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32);
259 setOperationAction(ISD::OR , (MVT::ValueType)VT, Promote);
260 AddPromotedToType (ISD::OR , (MVT::ValueType)VT, MVT::v4i32);
261 setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote);
262 AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32);
263 setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote);
264 AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32);
265 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
266 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32);
267 setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote);
268 AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32);
270 // No other operations are legal.
271 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
272 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
273 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
274 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
275 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
276 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
277 setOperationAction(ISD::FNEG, (MVT::ValueType)VT, Expand);
278 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
279 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
280 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
281 setOperationAction(ISD::UMUL_LOHI, (MVT::ValueType)VT, Expand);
282 setOperationAction(ISD::SMUL_LOHI, (MVT::ValueType)VT, Expand);
283 setOperationAction(ISD::UDIVREM, (MVT::ValueType)VT, Expand);
284 setOperationAction(ISD::SDIVREM, (MVT::ValueType)VT, Expand);
285 setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand);
286 setOperationAction(ISD::FPOW, (MVT::ValueType)VT, Expand);
287 setOperationAction(ISD::CTPOP, (MVT::ValueType)VT, Expand);
288 setOperationAction(ISD::CTLZ, (MVT::ValueType)VT, Expand);
289 setOperationAction(ISD::CTTZ, (MVT::ValueType)VT, Expand);
292 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
293 // with merges, splats, etc.
294 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
296 setOperationAction(ISD::AND , MVT::v4i32, Legal);
297 setOperationAction(ISD::OR , MVT::v4i32, Legal);
298 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
299 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
300 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
301 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
303 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
304 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
305 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
306 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
308 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
309 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
310 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
311 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
313 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
314 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
316 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
317 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
318 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
319 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
322 setSetCCResultType(MVT::i32);
323 setShiftAmountType(MVT::i32);
324 setSetCCResultContents(ZeroOrOneSetCCResult);
326 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
327 setStackPointerRegisterToSaveRestore(PPC::X1);
328 setExceptionPointerRegister(PPC::X3);
329 setExceptionSelectorRegister(PPC::X4);
331 setStackPointerRegisterToSaveRestore(PPC::R1);
332 setExceptionPointerRegister(PPC::R3);
333 setExceptionSelectorRegister(PPC::R4);
336 // We have target-specific dag combine patterns for the following nodes:
337 setTargetDAGCombine(ISD::SINT_TO_FP);
338 setTargetDAGCombine(ISD::STORE);
339 setTargetDAGCombine(ISD::BR_CC);
340 setTargetDAGCombine(ISD::BSWAP);
342 // Darwin long double math library functions have $LDBL128 appended.
343 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) {
344 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
345 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
346 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
347 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
348 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
351 computeRegisterProperties();
354 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
355 /// function arguments in the caller parameter area.
356 unsigned PPCTargetLowering::getByValTypeAlignment(const Type *Ty) const {
357 TargetMachine &TM = getTargetMachine();
358 // Darwin passes everything on 4 byte boundary.
359 if (TM.getSubtarget<PPCSubtarget>().isDarwin())
365 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
368 case PPCISD::FSEL: return "PPCISD::FSEL";
369 case PPCISD::FCFID: return "PPCISD::FCFID";
370 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
371 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
372 case PPCISD::STFIWX: return "PPCISD::STFIWX";
373 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
374 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
375 case PPCISD::VPERM: return "PPCISD::VPERM";
376 case PPCISD::Hi: return "PPCISD::Hi";
377 case PPCISD::Lo: return "PPCISD::Lo";
378 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
379 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
380 case PPCISD::SRL: return "PPCISD::SRL";
381 case PPCISD::SRA: return "PPCISD::SRA";
382 case PPCISD::SHL: return "PPCISD::SHL";
383 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
384 case PPCISD::STD_32: return "PPCISD::STD_32";
385 case PPCISD::CALL_ELF: return "PPCISD::CALL_ELF";
386 case PPCISD::CALL_Macho: return "PPCISD::CALL_Macho";
387 case PPCISD::MTCTR: return "PPCISD::MTCTR";
388 case PPCISD::BCTRL_Macho: return "PPCISD::BCTRL_Macho";
389 case PPCISD::BCTRL_ELF: return "PPCISD::BCTRL_ELF";
390 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
391 case PPCISD::MFCR: return "PPCISD::MFCR";
392 case PPCISD::VCMP: return "PPCISD::VCMP";
393 case PPCISD::VCMPo: return "PPCISD::VCMPo";
394 case PPCISD::LBRX: return "PPCISD::LBRX";
395 case PPCISD::STBRX: return "PPCISD::STBRX";
396 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
397 case PPCISD::MFFS: return "PPCISD::MFFS";
398 case PPCISD::MTFSB0: return "PPCISD::MTFSB0";
399 case PPCISD::MTFSB1: return "PPCISD::MTFSB1";
400 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
401 case PPCISD::MTFSF: return "PPCISD::MTFSF";
405 //===----------------------------------------------------------------------===//
406 // Node matching predicates, for use by the tblgen matching code.
407 //===----------------------------------------------------------------------===//
409 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
410 static bool isFloatingPointZero(SDOperand Op) {
411 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
412 return CFP->getValueAPF().isZero();
413 else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
414 // Maybe this has already been legalized into the constant pool?
415 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
416 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
417 return CFP->getValueAPF().isZero();
422 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
423 /// true if Op is undef or if it matches the specified value.
424 static bool isConstantOrUndef(SDOperand Op, unsigned Val) {
425 return Op.getOpcode() == ISD::UNDEF ||
426 cast<ConstantSDNode>(Op)->getValue() == Val;
429 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
430 /// VPKUHUM instruction.
431 bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) {
433 for (unsigned i = 0; i != 16; ++i)
434 if (!isConstantOrUndef(N->getOperand(i), i*2+1))
437 for (unsigned i = 0; i != 8; ++i)
438 if (!isConstantOrUndef(N->getOperand(i), i*2+1) ||
439 !isConstantOrUndef(N->getOperand(i+8), i*2+1))
445 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
446 /// VPKUWUM instruction.
447 bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) {
449 for (unsigned i = 0; i != 16; i += 2)
450 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
451 !isConstantOrUndef(N->getOperand(i+1), i*2+3))
454 for (unsigned i = 0; i != 8; i += 2)
455 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
456 !isConstantOrUndef(N->getOperand(i+1), i*2+3) ||
457 !isConstantOrUndef(N->getOperand(i+8), i*2+2) ||
458 !isConstantOrUndef(N->getOperand(i+9), i*2+3))
464 /// isVMerge - Common function, used to match vmrg* shuffles.
466 static bool isVMerge(SDNode *N, unsigned UnitSize,
467 unsigned LHSStart, unsigned RHSStart) {
468 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
469 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
470 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
471 "Unsupported merge size!");
473 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
474 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
475 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j),
476 LHSStart+j+i*UnitSize) ||
477 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j),
478 RHSStart+j+i*UnitSize))
484 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
485 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
486 bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
488 return isVMerge(N, UnitSize, 8, 24);
489 return isVMerge(N, UnitSize, 8, 8);
492 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
493 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
494 bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
496 return isVMerge(N, UnitSize, 0, 16);
497 return isVMerge(N, UnitSize, 0, 0);
501 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
502 /// amount, otherwise return -1.
503 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
504 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
505 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
506 // Find the first non-undef value in the shuffle mask.
508 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i)
511 if (i == 16) return -1; // all undef.
513 // Otherwise, check to see if the rest of the elements are consequtively
514 // numbered from this value.
515 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue();
516 if (ShiftAmt < i) return -1;
520 // Check the rest of the elements to see if they are consequtive.
521 for (++i; i != 16; ++i)
522 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i))
525 // Check the rest of the elements to see if they are consequtive.
526 for (++i; i != 16; ++i)
527 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15))
534 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
535 /// specifies a splat of a single element that is suitable for input to
536 /// VSPLTB/VSPLTH/VSPLTW.
537 bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) {
538 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
539 N->getNumOperands() == 16 &&
540 (EltSize == 1 || EltSize == 2 || EltSize == 4));
542 // This is a splat operation if each element of the permute is the same, and
543 // if the value doesn't reference the second vector.
544 unsigned ElementBase = 0;
545 SDOperand Elt = N->getOperand(0);
546 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt))
547 ElementBase = EltV->getValue();
549 return false; // FIXME: Handle UNDEF elements too!
551 if (cast<ConstantSDNode>(Elt)->getValue() >= 16)
554 // Check that they are consequtive.
555 for (unsigned i = 1; i != EltSize; ++i) {
556 if (!isa<ConstantSDNode>(N->getOperand(i)) ||
557 cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase)
561 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
562 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
563 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
564 assert(isa<ConstantSDNode>(N->getOperand(i)) &&
565 "Invalid VECTOR_SHUFFLE mask!");
566 for (unsigned j = 0; j != EltSize; ++j)
567 if (N->getOperand(i+j) != N->getOperand(j))
574 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
576 bool PPC::isAllNegativeZeroVector(SDNode *N) {
577 assert(N->getOpcode() == ISD::BUILD_VECTOR);
578 if (PPC::isSplatShuffleMask(N, N->getNumOperands()))
579 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N))
580 return CFP->getValueAPF().isNegZero();
584 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
585 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
586 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
587 assert(isSplatShuffleMask(N, EltSize));
588 return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize;
591 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
592 /// by using a vspltis[bhw] instruction of the specified element size, return
593 /// the constant being splatted. The ByteSize field indicates the number of
594 /// bytes of each element [124] -> [bhw].
595 SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
596 SDOperand OpVal(0, 0);
598 // If ByteSize of the splat is bigger than the element size of the
599 // build_vector, then we have a case where we are checking for a splat where
600 // multiple elements of the buildvector are folded together into a single
601 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
602 unsigned EltSize = 16/N->getNumOperands();
603 if (EltSize < ByteSize) {
604 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
605 SDOperand UniquedVals[4];
606 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
608 // See if all of the elements in the buildvector agree across.
609 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
610 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
611 // If the element isn't a constant, bail fully out.
612 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand();
615 if (UniquedVals[i&(Multiple-1)].Val == 0)
616 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
617 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
618 return SDOperand(); // no match.
621 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
622 // either constant or undef values that are identical for each chunk. See
623 // if these chunks can form into a larger vspltis*.
625 // Check to see if all of the leading entries are either 0 or -1. If
626 // neither, then this won't fit into the immediate field.
627 bool LeadingZero = true;
628 bool LeadingOnes = true;
629 for (unsigned i = 0; i != Multiple-1; ++i) {
630 if (UniquedVals[i].Val == 0) continue; // Must have been undefs.
632 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
633 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
635 // Finally, check the least significant entry.
637 if (UniquedVals[Multiple-1].Val == 0)
638 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
639 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue();
641 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
644 if (UniquedVals[Multiple-1].Val == 0)
645 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
646 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended();
647 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
648 return DAG.getTargetConstant(Val, MVT::i32);
654 // Check to see if this buildvec has a single non-undef value in its elements.
655 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
656 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
658 OpVal = N->getOperand(i);
659 else if (OpVal != N->getOperand(i))
663 if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def.
665 unsigned ValSizeInBytes = 0;
667 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
668 Value = CN->getValue();
669 ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8;
670 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
671 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
672 Value = FloatToBits(CN->getValueAPF().convertToFloat());
676 // If the splat value is larger than the element value, then we can never do
677 // this splat. The only case that we could fit the replicated bits into our
678 // immediate field for would be zero, and we prefer to use vxor for it.
679 if (ValSizeInBytes < ByteSize) return SDOperand();
681 // If the element value is larger than the splat value, cut it in half and
682 // check to see if the two halves are equal. Continue doing this until we
683 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
684 while (ValSizeInBytes > ByteSize) {
685 ValSizeInBytes >>= 1;
687 // If the top half equals the bottom half, we're still ok.
688 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
689 (Value & ((1 << (8*ValSizeInBytes))-1)))
693 // Properly sign extend the value.
694 int ShAmt = (4-ByteSize)*8;
695 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
697 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
698 if (MaskVal == 0) return SDOperand();
700 // Finally, if this value fits in a 5 bit sext field, return it
701 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
702 return DAG.getTargetConstant(MaskVal, MVT::i32);
706 //===----------------------------------------------------------------------===//
707 // Addressing Mode Selection
708 //===----------------------------------------------------------------------===//
710 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
711 /// or 64-bit immediate, and if the value can be accurately represented as a
712 /// sign extension from a 16-bit value. If so, this returns true and the
714 static bool isIntS16Immediate(SDNode *N, short &Imm) {
715 if (N->getOpcode() != ISD::Constant)
718 Imm = (short)cast<ConstantSDNode>(N)->getValue();
719 if (N->getValueType(0) == MVT::i32)
720 return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue();
722 return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue();
724 static bool isIntS16Immediate(SDOperand Op, short &Imm) {
725 return isIntS16Immediate(Op.Val, Imm);
729 /// SelectAddressRegReg - Given the specified addressed, check to see if it
730 /// can be represented as an indexed [r+r] operation. Returns false if it
731 /// can be more efficiently represented with [r+imm].
732 bool PPCTargetLowering::SelectAddressRegReg(SDOperand N, SDOperand &Base,
736 if (N.getOpcode() == ISD::ADD) {
737 if (isIntS16Immediate(N.getOperand(1), imm))
739 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
742 Base = N.getOperand(0);
743 Index = N.getOperand(1);
745 } else if (N.getOpcode() == ISD::OR) {
746 if (isIntS16Immediate(N.getOperand(1), imm))
747 return false; // r+i can fold it if we can.
749 // If this is an or of disjoint bitfields, we can codegen this as an add
750 // (for better address arithmetic) if the LHS and RHS of the OR are provably
752 APInt LHSKnownZero, LHSKnownOne;
753 APInt RHSKnownZero, RHSKnownOne;
754 DAG.ComputeMaskedBits(N.getOperand(0),
755 APInt::getAllOnesValue(N.getOperand(0)
756 .getValueSizeInBits()),
757 LHSKnownZero, LHSKnownOne);
759 if (LHSKnownZero.getBoolValue()) {
760 DAG.ComputeMaskedBits(N.getOperand(1),
761 APInt::getAllOnesValue(N.getOperand(1)
762 .getValueSizeInBits()),
763 RHSKnownZero, RHSKnownOne);
764 // If all of the bits are known zero on the LHS or RHS, the add won't
766 if (~(LHSKnownZero | RHSKnownZero) == 0) {
767 Base = N.getOperand(0);
768 Index = N.getOperand(1);
777 /// Returns true if the address N can be represented by a base register plus
778 /// a signed 16-bit displacement [r+imm], and if it is not better
779 /// represented as reg+reg.
780 bool PPCTargetLowering::SelectAddressRegImm(SDOperand N, SDOperand &Disp,
781 SDOperand &Base, SelectionDAG &DAG){
782 // If this can be more profitably realized as r+r, fail.
783 if (SelectAddressRegReg(N, Disp, Base, DAG))
786 if (N.getOpcode() == ISD::ADD) {
788 if (isIntS16Immediate(N.getOperand(1), imm)) {
789 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
790 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
791 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
793 Base = N.getOperand(0);
795 return true; // [r+i]
796 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
797 // Match LOAD (ADD (X, Lo(G))).
798 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
799 && "Cannot handle constant offsets yet!");
800 Disp = N.getOperand(1).getOperand(0); // The global address.
801 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
802 Disp.getOpcode() == ISD::TargetConstantPool ||
803 Disp.getOpcode() == ISD::TargetJumpTable);
804 Base = N.getOperand(0);
805 return true; // [&g+r]
807 } else if (N.getOpcode() == ISD::OR) {
809 if (isIntS16Immediate(N.getOperand(1), imm)) {
810 // If this is an or of disjoint bitfields, we can codegen this as an add
811 // (for better address arithmetic) if the LHS and RHS of the OR are
812 // provably disjoint.
813 APInt LHSKnownZero, LHSKnownOne;
814 DAG.ComputeMaskedBits(N.getOperand(0),
815 APInt::getAllOnesValue(32),
816 LHSKnownZero, LHSKnownOne);
817 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
818 // If all of the bits are known zero on the LHS or RHS, the add won't
820 Base = N.getOperand(0);
821 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
825 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
826 // Loading from a constant address.
828 // If this address fits entirely in a 16-bit sext immediate field, codegen
831 if (isIntS16Immediate(CN, Imm)) {
832 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
833 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
837 // Handle 32-bit sext immediates with LIS + addr mode.
838 if (CN->getValueType(0) == MVT::i32 ||
839 (int64_t)CN->getValue() == (int)CN->getValue()) {
840 int Addr = (int)CN->getValue();
842 // Otherwise, break this down into an LIS + disp.
843 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
845 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
846 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
847 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
852 Disp = DAG.getTargetConstant(0, getPointerTy());
853 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
854 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
857 return true; // [r+0]
860 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
861 /// represented as an indexed [r+r] operation.
862 bool PPCTargetLowering::SelectAddressRegRegOnly(SDOperand N, SDOperand &Base,
865 // Check to see if we can easily represent this as an [r+r] address. This
866 // will fail if it thinks that the address is more profitably represented as
867 // reg+imm, e.g. where imm = 0.
868 if (SelectAddressRegReg(N, Base, Index, DAG))
871 // If the operand is an addition, always emit this as [r+r], since this is
872 // better (for code size, and execution, as the memop does the add for free)
873 // than emitting an explicit add.
874 if (N.getOpcode() == ISD::ADD) {
875 Base = N.getOperand(0);
876 Index = N.getOperand(1);
880 // Otherwise, do it the hard way, using R0 as the base register.
881 Base = DAG.getRegister(PPC::R0, N.getValueType());
886 /// SelectAddressRegImmShift - Returns true if the address N can be
887 /// represented by a base register plus a signed 14-bit displacement
888 /// [r+imm*4]. Suitable for use by STD and friends.
889 bool PPCTargetLowering::SelectAddressRegImmShift(SDOperand N, SDOperand &Disp,
892 // If this can be more profitably realized as r+r, fail.
893 if (SelectAddressRegReg(N, Disp, Base, DAG))
896 if (N.getOpcode() == ISD::ADD) {
898 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
899 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
900 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
901 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
903 Base = N.getOperand(0);
905 return true; // [r+i]
906 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
907 // Match LOAD (ADD (X, Lo(G))).
908 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
909 && "Cannot handle constant offsets yet!");
910 Disp = N.getOperand(1).getOperand(0); // The global address.
911 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
912 Disp.getOpcode() == ISD::TargetConstantPool ||
913 Disp.getOpcode() == ISD::TargetJumpTable);
914 Base = N.getOperand(0);
915 return true; // [&g+r]
917 } else if (N.getOpcode() == ISD::OR) {
919 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
920 // If this is an or of disjoint bitfields, we can codegen this as an add
921 // (for better address arithmetic) if the LHS and RHS of the OR are
922 // provably disjoint.
923 APInt LHSKnownZero, LHSKnownOne;
924 DAG.ComputeMaskedBits(N.getOperand(0),
925 APInt::getAllOnesValue(32),
926 LHSKnownZero, LHSKnownOne);
927 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
928 // If all of the bits are known zero on the LHS or RHS, the add won't
930 Base = N.getOperand(0);
931 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
935 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
936 // Loading from a constant address. Verify low two bits are clear.
937 if ((CN->getValue() & 3) == 0) {
938 // If this address fits entirely in a 14-bit sext immediate field, codegen
941 if (isIntS16Immediate(CN, Imm)) {
942 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
943 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
947 // Fold the low-part of 32-bit absolute addresses into addr mode.
948 if (CN->getValueType(0) == MVT::i32 ||
949 (int64_t)CN->getValue() == (int)CN->getValue()) {
950 int Addr = (int)CN->getValue();
952 // Otherwise, break this down into an LIS + disp.
953 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
955 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
956 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
957 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
963 Disp = DAG.getTargetConstant(0, getPointerTy());
964 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
965 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
968 return true; // [r+0]
972 /// getPreIndexedAddressParts - returns true by value, base pointer and
973 /// offset pointer and addressing mode by reference if the node's address
974 /// can be legally represented as pre-indexed load / store address.
975 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
977 ISD::MemIndexedMode &AM,
979 // Disabled by default for now.
980 if (!EnablePPCPreinc) return false;
984 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
985 Ptr = LD->getBasePtr();
986 VT = LD->getMemoryVT();
988 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
990 Ptr = ST->getBasePtr();
991 VT = ST->getMemoryVT();
995 // PowerPC doesn't have preinc load/store instructions for vectors.
996 if (MVT::isVector(VT))
999 // TODO: Check reg+reg first.
1001 // LDU/STU use reg+imm*4, others use reg+imm.
1002 if (VT != MVT::i64) {
1004 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
1008 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
1012 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1013 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1014 // sext i32 to i64 when addr mode is r+i.
1015 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1016 LD->getExtensionType() == ISD::SEXTLOAD &&
1017 isa<ConstantSDNode>(Offset))
1025 //===----------------------------------------------------------------------===//
1026 // LowerOperation implementation
1027 //===----------------------------------------------------------------------===//
1029 SDOperand PPCTargetLowering::LowerConstantPool(SDOperand Op,
1030 SelectionDAG &DAG) {
1031 MVT::ValueType PtrVT = Op.getValueType();
1032 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1033 Constant *C = CP->getConstVal();
1034 SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
1035 SDOperand Zero = DAG.getConstant(0, PtrVT);
1037 const TargetMachine &TM = DAG.getTarget();
1039 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero);
1040 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero);
1042 // If this is a non-darwin platform, we don't support non-static relo models
1044 if (TM.getRelocationModel() == Reloc::Static ||
1045 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1046 // Generate non-pic code that has direct accesses to the constant pool.
1047 // The address of the global is just (hi(&g)+lo(&g)).
1048 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1051 if (TM.getRelocationModel() == Reloc::PIC_) {
1052 // With PIC, the first instruction is actually "GR+hi(&G)".
1053 Hi = DAG.getNode(ISD::ADD, PtrVT,
1054 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1057 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1061 SDOperand PPCTargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
1062 MVT::ValueType PtrVT = Op.getValueType();
1063 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1064 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1065 SDOperand Zero = DAG.getConstant(0, PtrVT);
1067 const TargetMachine &TM = DAG.getTarget();
1069 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero);
1070 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero);
1072 // If this is a non-darwin platform, we don't support non-static relo models
1074 if (TM.getRelocationModel() == Reloc::Static ||
1075 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1076 // Generate non-pic code that has direct accesses to the constant pool.
1077 // The address of the global is just (hi(&g)+lo(&g)).
1078 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1081 if (TM.getRelocationModel() == Reloc::PIC_) {
1082 // With PIC, the first instruction is actually "GR+hi(&G)".
1083 Hi = DAG.getNode(ISD::ADD, PtrVT,
1084 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1087 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1091 SDOperand PPCTargetLowering::LowerGlobalTLSAddress(SDOperand Op,
1092 SelectionDAG &DAG) {
1093 assert(0 && "TLS not implemented for PPC.");
1096 SDOperand PPCTargetLowering::LowerGlobalAddress(SDOperand Op,
1097 SelectionDAG &DAG) {
1098 MVT::ValueType PtrVT = Op.getValueType();
1099 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1100 GlobalValue *GV = GSDN->getGlobal();
1101 SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
1102 // If it's a debug information descriptor, don't mess with it.
1103 if (DAG.isVerifiedDebugInfoDesc(Op))
1105 SDOperand Zero = DAG.getConstant(0, PtrVT);
1107 const TargetMachine &TM = DAG.getTarget();
1109 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero);
1110 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero);
1112 // If this is a non-darwin platform, we don't support non-static relo models
1114 if (TM.getRelocationModel() == Reloc::Static ||
1115 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1116 // Generate non-pic code that has direct accesses to globals.
1117 // The address of the global is just (hi(&g)+lo(&g)).
1118 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1121 if (TM.getRelocationModel() == Reloc::PIC_) {
1122 // With PIC, the first instruction is actually "GR+hi(&G)".
1123 Hi = DAG.getNode(ISD::ADD, PtrVT,
1124 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1127 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1129 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV))
1132 // If the global is weak or external, we have to go through the lazy
1134 return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0);
1137 SDOperand PPCTargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
1138 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1140 // If we're comparing for equality to zero, expose the fact that this is
1141 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1142 // fold the new nodes.
1143 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1144 if (C->isNullValue() && CC == ISD::SETEQ) {
1145 MVT::ValueType VT = Op.getOperand(0).getValueType();
1146 SDOperand Zext = Op.getOperand(0);
1147 if (VT < MVT::i32) {
1149 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0));
1151 unsigned Log2b = Log2_32(MVT::getSizeInBits(VT));
1152 SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext);
1153 SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz,
1154 DAG.getConstant(Log2b, MVT::i32));
1155 return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc);
1157 // Leave comparisons against 0 and -1 alone for now, since they're usually
1158 // optimized. FIXME: revisit this when we can custom lower all setcc
1160 if (C->isAllOnesValue() || C->isNullValue())
1164 // If we have an integer seteq/setne, turn it into a compare against zero
1165 // by xor'ing the rhs with the lhs, which is faster than setting a
1166 // condition register, reading it back out, and masking the correct bit. The
1167 // normal approach here uses sub to do this instead of xor. Using xor exposes
1168 // the result to other bit-twiddling opportunities.
1169 MVT::ValueType LHSVT = Op.getOperand(0).getValueType();
1170 if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1171 MVT::ValueType VT = Op.getValueType();
1172 SDOperand Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0),
1174 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC);
1179 SDOperand PPCTargetLowering::LowerVAARG(SDOperand Op, SelectionDAG &DAG,
1180 int VarArgsFrameIndex,
1181 int VarArgsStackOffset,
1182 unsigned VarArgsNumGPR,
1183 unsigned VarArgsNumFPR,
1184 const PPCSubtarget &Subtarget) {
1186 assert(0 && "VAARG in ELF32 ABI not implemented yet!");
1189 SDOperand PPCTargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG,
1190 int VarArgsFrameIndex,
1191 int VarArgsStackOffset,
1192 unsigned VarArgsNumGPR,
1193 unsigned VarArgsNumFPR,
1194 const PPCSubtarget &Subtarget) {
1196 if (Subtarget.isMachoABI()) {
1197 // vastart just stores the address of the VarArgsFrameIndex slot into the
1198 // memory location argument.
1199 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1200 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1201 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1202 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0);
1205 // For ELF 32 ABI we follow the layout of the va_list struct.
1206 // We suppose the given va_list is already allocated.
1209 // char gpr; /* index into the array of 8 GPRs
1210 // * stored in the register save area
1211 // * gpr=0 corresponds to r3,
1212 // * gpr=1 to r4, etc.
1214 // char fpr; /* index into the array of 8 FPRs
1215 // * stored in the register save area
1216 // * fpr=0 corresponds to f1,
1217 // * fpr=1 to f2, etc.
1219 // char *overflow_arg_area;
1220 // /* location on stack that holds
1221 // * the next overflow argument
1223 // char *reg_save_area;
1224 // /* where r3:r10 and f1:f8 (if saved)
1230 SDOperand ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i8);
1231 SDOperand ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i8);
1234 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1236 SDOperand StackOffsetFI = DAG.getFrameIndex(VarArgsStackOffset, PtrVT);
1237 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1239 uint64_t FrameOffset = MVT::getSizeInBits(PtrVT)/8;
1240 SDOperand ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1242 uint64_t StackOffset = MVT::getSizeInBits(PtrVT)/8 - 1;
1243 SDOperand ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1245 uint64_t FPROffset = 1;
1246 SDOperand ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1248 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1250 // Store first byte : number of int regs
1251 SDOperand firstStore = DAG.getStore(Op.getOperand(0), ArgGPR,
1252 Op.getOperand(1), SV, 0);
1253 uint64_t nextOffset = FPROffset;
1254 SDOperand nextPtr = DAG.getNode(ISD::ADD, PtrVT, Op.getOperand(1),
1257 // Store second byte : number of float regs
1258 SDOperand secondStore =
1259 DAG.getStore(firstStore, ArgFPR, nextPtr, SV, nextOffset);
1260 nextOffset += StackOffset;
1261 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstStackOffset);
1263 // Store second word : arguments given on stack
1264 SDOperand thirdStore =
1265 DAG.getStore(secondStore, StackOffsetFI, nextPtr, SV, nextOffset);
1266 nextOffset += FrameOffset;
1267 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstFrameOffset);
1269 // Store third word : arguments given in registers
1270 return DAG.getStore(thirdStore, FR, nextPtr, SV, nextOffset);
1274 #include "PPCGenCallingConv.inc"
1276 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1277 /// depending on which subtarget is selected.
1278 static const unsigned *GetFPR(const PPCSubtarget &Subtarget) {
1279 if (Subtarget.isMachoABI()) {
1280 static const unsigned FPR[] = {
1281 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1282 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1288 static const unsigned FPR[] = {
1289 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1295 SDOperand PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op,
1297 int &VarArgsFrameIndex,
1298 int &VarArgsStackOffset,
1299 unsigned &VarArgsNumGPR,
1300 unsigned &VarArgsNumFPR,
1301 const PPCSubtarget &Subtarget) {
1302 // TODO: add description of PPC stack frame format, or at least some docs.
1304 MachineFunction &MF = DAG.getMachineFunction();
1305 MachineFrameInfo *MFI = MF.getFrameInfo();
1306 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1307 SmallVector<SDOperand, 8> ArgValues;
1308 SDOperand Root = Op.getOperand(0);
1310 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1311 bool isPPC64 = PtrVT == MVT::i64;
1312 bool isMachoABI = Subtarget.isMachoABI();
1313 bool isELF32_ABI = Subtarget.isELF32_ABI();
1314 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1316 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1318 static const unsigned GPR_32[] = { // 32-bit registers.
1319 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1320 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1322 static const unsigned GPR_64[] = { // 64-bit registers.
1323 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1324 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1327 static const unsigned *FPR = GetFPR(Subtarget);
1329 static const unsigned VR[] = {
1330 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1331 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1334 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
1335 const unsigned Num_FPR_Regs = isMachoABI ? 13 : 8;
1336 const unsigned Num_VR_Regs = array_lengthof( VR);
1338 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1340 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1342 // Add DAG nodes to load the arguments or copy them out of registers. On
1343 // entry to a function on PPC, the arguments start after the linkage area,
1344 // although the first ones are often in registers.
1346 // In the ELF 32 ABI, GPRs and stack are double word align: an argument
1347 // represented with two words (long long or double) must be copied to an
1348 // even GPR_idx value or to an even ArgOffset value.
1350 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
1352 bool needsLoad = false;
1353 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
1354 unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8;
1355 unsigned ArgSize = ObjSize;
1356 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(ArgNo+3))->getValue();
1357 unsigned AlignFlag = 1 << ISD::ParamFlags::OrigAlignmentOffs;
1358 // See if next argument requires stack alignment in ELF
1359 bool Expand = (ObjectVT == MVT::f64) || ((ArgNo + 1 < e) &&
1360 (cast<ConstantSDNode>(Op.getOperand(ArgNo+4))->getValue() & AlignFlag) &&
1361 (!(Flags & AlignFlag)));
1363 unsigned CurArgOffset = ArgOffset;
1365 default: assert(0 && "Unhandled argument type!");
1367 // Double word align in ELF
1368 if (Expand && isELF32_ABI) GPR_idx += (GPR_idx % 2);
1369 if (GPR_idx != Num_GPR_Regs) {
1370 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
1371 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1372 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32);
1376 ArgSize = PtrByteSize;
1378 // Stack align in ELF
1379 if (needsLoad && Expand && isELF32_ABI)
1380 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1381 // All int arguments reserve stack space in Macho ABI.
1382 if (isMachoABI || needsLoad) ArgOffset += PtrByteSize;
1385 case MVT::i64: // PPC64
1386 if (GPR_idx != Num_GPR_Regs) {
1387 unsigned VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
1388 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1389 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1394 // All int arguments reserve stack space in Macho ABI.
1395 if (isMachoABI || needsLoad) ArgOffset += 8;
1400 // Every 4 bytes of argument space consumes one of the GPRs available for
1401 // argument passing.
1402 if (GPR_idx != Num_GPR_Regs && isMachoABI) {
1404 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
1407 if (FPR_idx != Num_FPR_Regs) {
1409 if (ObjectVT == MVT::f32)
1410 VReg = RegInfo.createVirtualRegister(&PPC::F4RCRegClass);
1412 VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
1413 RegInfo.addLiveIn(FPR[FPR_idx], VReg);
1414 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
1420 // Stack align in ELF
1421 if (needsLoad && Expand && isELF32_ABI)
1422 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1423 // All FP arguments reserve stack space in Macho ABI.
1424 if (isMachoABI || needsLoad) ArgOffset += isPPC64 ? 8 : ObjSize;
1430 // Note that vector arguments in registers don't reserve stack space.
1431 if (VR_idx != Num_VR_Regs) {
1432 unsigned VReg = RegInfo.createVirtualRegister(&PPC::VRRCRegClass);
1433 RegInfo.addLiveIn(VR[VR_idx], VReg);
1434 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
1437 // This should be simple, but requires getting 16-byte aligned stack
1439 assert(0 && "Loading VR argument not implemented yet!");
1445 // We need to load the argument to a virtual register if we determined above
1446 // that we ran out of physical registers of the appropriate type.
1448 int FI = MFI->CreateFixedObject(ObjSize,
1449 CurArgOffset + (ArgSize - ObjSize));
1450 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
1451 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
1454 ArgValues.push_back(ArgVal);
1457 // If the function takes variable number of arguments, make a frame index for
1458 // the start of the first vararg value... for expansion of llvm.va_start.
1459 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1464 VarArgsNumGPR = GPR_idx;
1465 VarArgsNumFPR = FPR_idx;
1467 // Make room for Num_GPR_Regs, Num_FPR_Regs and for a possible frame
1469 depth = -(Num_GPR_Regs * MVT::getSizeInBits(PtrVT)/8 +
1470 Num_FPR_Regs * MVT::getSizeInBits(MVT::f64)/8 +
1471 MVT::getSizeInBits(PtrVT)/8);
1473 VarArgsStackOffset = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8,
1480 VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8,
1482 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1484 SmallVector<SDOperand, 8> MemOps;
1486 // In ELF 32 ABI, the fixed integer arguments of a variadic function are
1487 // stored to the VarArgsFrameIndex on the stack.
1489 for (GPR_idx = 0; GPR_idx != VarArgsNumGPR; ++GPR_idx) {
1490 SDOperand Val = DAG.getRegister(GPR[GPR_idx], PtrVT);
1491 SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0);
1492 MemOps.push_back(Store);
1493 // Increment the address by four for the next argument to store
1494 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT);
1495 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1499 // If this function is vararg, store any remaining integer argument regs
1500 // to their spots on the stack so that they may be loaded by deferencing the
1501 // result of va_next.
1502 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
1505 VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
1507 VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
1509 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1510 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
1511 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1512 MemOps.push_back(Store);
1513 // Increment the address by four for the next argument to store
1514 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT);
1515 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1518 // In ELF 32 ABI, the double arguments are stored to the VarArgsFrameIndex
1521 for (FPR_idx = 0; FPR_idx != VarArgsNumFPR; ++FPR_idx) {
1522 SDOperand Val = DAG.getRegister(FPR[FPR_idx], MVT::f64);
1523 SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0);
1524 MemOps.push_back(Store);
1525 // Increment the address by eight for the next argument to store
1526 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8,
1528 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1531 for (; FPR_idx != Num_FPR_Regs; ++FPR_idx) {
1533 VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
1535 RegInfo.addLiveIn(FPR[FPR_idx], VReg);
1536 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::f64);
1537 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1538 MemOps.push_back(Store);
1539 // Increment the address by eight for the next argument to store
1540 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8,
1542 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1546 if (!MemOps.empty())
1547 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size());
1550 ArgValues.push_back(Root);
1552 // Return the new list of results.
1553 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
1554 Op.Val->value_end());
1555 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
1558 /// isCallCompatibleAddress - Return the immediate to use if the specified
1559 /// 32-bit value is representable in the immediate field of a BxA instruction.
1560 static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) {
1561 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
1564 int Addr = C->getValue();
1565 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
1566 (Addr << 6 >> 6) != Addr)
1567 return 0; // Top 6 bits have to be sext of immediate.
1569 return DAG.getConstant((int)C->getValue() >> 2,
1570 DAG.getTargetLoweringInfo().getPointerTy()).Val;
1573 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1574 /// by "Src" to address "Dst" of size "Size". Alignment information is
1575 /// specified by the specific parameter attribute. The copy will be passed as
1576 /// a byval function parameter.
1577 /// Sometimes what we are copying is the end of a larger object, the part that
1578 /// does not fit in registers.
1580 CreateCopyOfByValArgument(SDOperand Src, SDOperand Dst, SDOperand Chain,
1581 unsigned Flags, SelectionDAG &DAG, unsigned Size) {
1582 unsigned Align = 1 <<
1583 ((Flags & ISD::ParamFlags::ByValAlign) >> ISD::ParamFlags::ByValAlignOffs);
1584 SDOperand AlignNode = DAG.getConstant(Align, MVT::i32);
1585 SDOperand SizeNode = DAG.getConstant(Size, MVT::i32);
1586 SDOperand AlwaysInline = DAG.getConstant(0, MVT::i32);
1587 return DAG.getMemcpy(Chain, Dst, Src, SizeNode, AlignNode, AlwaysInline);
1590 SDOperand PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG,
1591 const PPCSubtarget &Subtarget) {
1592 SDOperand Chain = Op.getOperand(0);
1593 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1594 SDOperand Callee = Op.getOperand(4);
1595 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
1597 bool isMachoABI = Subtarget.isMachoABI();
1598 bool isELF32_ABI = Subtarget.isELF32_ABI();
1600 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1601 bool isPPC64 = PtrVT == MVT::i64;
1602 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1604 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in
1605 // SelectExpr to use to put the arguments in the appropriate registers.
1606 std::vector<SDOperand> args_to_use;
1608 // Count how many bytes are to be pushed on the stack, including the linkage
1609 // area, and parameter passing area. We start with 24/48 bytes, which is
1610 // prereserved space for [SP][CR][LR][3 x unused].
1611 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1613 // Add up all the space actually used.
1614 for (unsigned i = 0; i != NumOps; ++i) {
1615 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue();
1616 unsigned ArgSize =MVT::getSizeInBits(Op.getOperand(5+2*i).getValueType())/8;
1617 if (Flags & ISD::ParamFlags::ByVal)
1618 ArgSize = (Flags & ISD::ParamFlags::ByValSize) >>
1619 ISD::ParamFlags::ByValSizeOffs;
1620 ArgSize = std::max(ArgSize, PtrByteSize);
1621 NumBytes += ArgSize;
1624 // The prolog code of the callee may store up to 8 GPR argument registers to
1625 // the stack, allowing va_start to index over them in memory if its varargs.
1626 // Because we cannot tell if this is needed on the caller side, we have to
1627 // conservatively assume that it is needed. As such, make sure we have at
1628 // least enough stack space for the caller to store the 8 GPRs.
1629 NumBytes = std::max(NumBytes,
1630 PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI));
1632 // Adjust the stack pointer for the new arguments...
1633 // These operations are automatically eliminated by the prolog/epilog pass
1634 Chain = DAG.getCALLSEQ_START(Chain,
1635 DAG.getConstant(NumBytes, PtrVT));
1636 SDOperand CallSeqStart = Chain;
1638 // Set up a copy of the stack pointer for use loading and storing any
1639 // arguments that may not fit in the registers available for argument
1643 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
1645 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
1647 // Figure out which arguments are going to go in registers, and which in
1648 // memory. Also, if this is a vararg function, floating point operations
1649 // must be stored to our stack, and loaded into integer regs as well, if
1650 // any integer regs are available for argument passing.
1651 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1652 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1654 static const unsigned GPR_32[] = { // 32-bit registers.
1655 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1656 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1658 static const unsigned GPR_64[] = { // 64-bit registers.
1659 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1660 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1662 static const unsigned *FPR = GetFPR(Subtarget);
1664 static const unsigned VR[] = {
1665 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1666 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1668 const unsigned NumGPRs = array_lengthof(GPR_32);
1669 const unsigned NumFPRs = isMachoABI ? 13 : 8;
1670 const unsigned NumVRs = array_lengthof( VR);
1672 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1674 std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
1675 SmallVector<SDOperand, 8> MemOpChains;
1676 for (unsigned i = 0; i != NumOps; ++i) {
1678 SDOperand Arg = Op.getOperand(5+2*i);
1679 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue();
1680 unsigned AlignFlag = 1 << ISD::ParamFlags::OrigAlignmentOffs;
1681 // See if next argument requires stack alignment in ELF
1682 unsigned next = 5+2*(i+1)+1;
1683 bool Expand = (Arg.getValueType() == MVT::f64) || ((i + 1 < NumOps) &&
1684 (cast<ConstantSDNode>(Op.getOperand(next))->getValue() & AlignFlag) &&
1685 (!(Flags & AlignFlag)));
1687 // PtrOff will be used to store the current argument to the stack if a
1688 // register cannot be found for it.
1691 // Stack align in ELF 32
1692 if (isELF32_ABI && Expand)
1693 PtrOff = DAG.getConstant(ArgOffset + ((ArgOffset/4) % 2) * PtrByteSize,
1694 StackPtr.getValueType());
1696 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
1698 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff);
1700 // On PPC64, promote integers to 64-bit values.
1701 if (isPPC64 && Arg.getValueType() == MVT::i32) {
1702 unsigned ExtOp = (Flags & 1) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1704 Arg = DAG.getNode(ExtOp, MVT::i64, Arg);
1707 // FIXME Elf untested, what are alignment rules?
1708 if (Flags & ISD::ParamFlags::ByVal) {
1709 unsigned Size = (Flags & ISD::ParamFlags::ByValSize) >>
1710 ISD::ParamFlags::ByValSizeOffs;
1711 if (isELF32_ABI && Expand) GPR_idx += (GPR_idx % 2);
1712 for (unsigned j=0; j<Size; j+=PtrByteSize) {
1713 SDOperand Const = DAG.getConstant(j, PtrOff.getValueType());
1714 SDOperand AddArg = DAG.getNode(ISD::ADD, PtrVT, Arg, Const);
1715 if (GPR_idx != NumGPRs) {
1716 SDOperand Load = DAG.getLoad(PtrVT, Chain, AddArg, NULL, 0);
1717 MemOpChains.push_back(Load.getValue(1));
1718 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
1720 ArgOffset += PtrByteSize;
1722 SDOperand AddPtr = DAG.getNode(ISD::ADD, PtrVT, PtrOff, Const);
1723 SDOperand MemcpyCall = CreateCopyOfByValArgument(AddArg, AddPtr,
1724 CallSeqStart.Val->getOperand(0),
1725 Flags, DAG, Size - j);
1726 // This must go outside the CALLSEQ_START..END.
1727 SDOperand NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
1728 CallSeqStart.Val->getOperand(1));
1729 DAG.ReplaceAllUsesWith(CallSeqStart.Val, NewCallSeqStart.Val);
1730 CallSeqStart = NewCallSeqStart;
1731 ArgOffset += ((Size - j + 3)/4)*4;
1737 switch (Arg.getValueType()) {
1738 default: assert(0 && "Unexpected ValueType for argument!");
1741 // Double word align in ELF
1742 if (isELF32_ABI && Expand) GPR_idx += (GPR_idx % 2);
1743 if (GPR_idx != NumGPRs) {
1744 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
1746 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1749 if (inMem || isMachoABI) {
1750 // Stack align in ELF
1751 if (isELF32_ABI && Expand)
1752 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1754 ArgOffset += PtrByteSize;
1760 // Float varargs need to be promoted to double.
1761 if (Arg.getValueType() == MVT::f32)
1762 Arg = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Arg);
1765 if (FPR_idx != NumFPRs) {
1766 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
1769 SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
1770 MemOpChains.push_back(Store);
1772 // Float varargs are always shadowed in available integer registers
1773 if (GPR_idx != NumGPRs) {
1774 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
1775 MemOpChains.push_back(Load.getValue(1));
1776 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
1779 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
1780 SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType());
1781 PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour);
1782 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
1783 MemOpChains.push_back(Load.getValue(1));
1784 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
1788 // If we have any FPRs remaining, we may also have GPRs remaining.
1789 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
1792 if (GPR_idx != NumGPRs)
1794 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
1795 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
1800 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1803 if (inMem || isMachoABI) {
1804 // Stack align in ELF
1805 if (isELF32_ABI && Expand)
1806 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1810 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
1817 assert(!isVarArg && "Don't support passing vectors to varargs yet!");
1818 assert(VR_idx != NumVRs &&
1819 "Don't support passing more than 12 vector args yet!");
1820 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
1824 if (!MemOpChains.empty())
1825 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1826 &MemOpChains[0], MemOpChains.size());
1828 // Build a sequence of copy-to-reg nodes chained together with token chain
1829 // and flag operands which copy the outgoing args into the appropriate regs.
1831 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1832 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1834 InFlag = Chain.getValue(1);
1837 // With the ELF 32 ABI, set CR6 to true if this is a vararg call.
1838 if (isVarArg && isELF32_ABI) {
1839 SDOperand SetCR(DAG.getTargetNode(PPC::SETCR, MVT::i32), 0);
1840 Chain = DAG.getCopyToReg(Chain, PPC::CR6, SetCR, InFlag);
1841 InFlag = Chain.getValue(1);
1844 std::vector<MVT::ValueType> NodeTys;
1845 NodeTys.push_back(MVT::Other); // Returns a chain
1846 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
1848 SmallVector<SDOperand, 8> Ops;
1849 unsigned CallOpc = isMachoABI? PPCISD::CALL_Macho : PPCISD::CALL_ELF;
1851 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1852 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1853 // node so that legalize doesn't hack it.
1854 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1855 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
1856 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1857 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType());
1858 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
1859 // If this is an absolute destination address, use the munged value.
1860 Callee = SDOperand(Dest, 0);
1862 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
1863 // to do the call, we can't use PPCISD::CALL.
1864 SDOperand MTCTROps[] = {Chain, Callee, InFlag};
1865 Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+(InFlag.Val!=0));
1866 InFlag = Chain.getValue(1);
1868 // Copy the callee address into R12 on darwin.
1870 Chain = DAG.getCopyToReg(Chain, PPC::R12, Callee, InFlag);
1871 InFlag = Chain.getValue(1);
1875 NodeTys.push_back(MVT::Other);
1876 NodeTys.push_back(MVT::Flag);
1877 Ops.push_back(Chain);
1878 CallOpc = isMachoABI ? PPCISD::BCTRL_Macho : PPCISD::BCTRL_ELF;
1882 // If this is a direct call, pass the chain and the callee.
1884 Ops.push_back(Chain);
1885 Ops.push_back(Callee);
1888 // Add argument registers to the end of the list so that they are known live
1890 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1891 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1892 RegsToPass[i].second.getValueType()));
1895 Ops.push_back(InFlag);
1896 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
1897 InFlag = Chain.getValue(1);
1899 Chain = DAG.getCALLSEQ_END(Chain,
1900 DAG.getConstant(NumBytes, PtrVT),
1901 DAG.getConstant(0, PtrVT),
1903 if (Op.Val->getValueType(0) != MVT::Other)
1904 InFlag = Chain.getValue(1);
1906 SDOperand ResultVals[3];
1907 unsigned NumResults = 0;
1910 // If the call has results, copy the values out of the ret val registers.
1911 switch (Op.Val->getValueType(0)) {
1912 default: assert(0 && "Unexpected ret value!");
1913 case MVT::Other: break;
1915 if (Op.Val->getValueType(1) == MVT::i32) {
1916 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1);
1917 ResultVals[0] = Chain.getValue(0);
1918 Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32,
1919 Chain.getValue(2)).getValue(1);
1920 ResultVals[1] = Chain.getValue(0);
1922 NodeTys.push_back(MVT::i32);
1924 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1);
1925 ResultVals[0] = Chain.getValue(0);
1928 NodeTys.push_back(MVT::i32);
1931 Chain = DAG.getCopyFromReg(Chain, PPC::X3, MVT::i64, InFlag).getValue(1);
1932 ResultVals[0] = Chain.getValue(0);
1934 NodeTys.push_back(MVT::i64);
1937 if (Op.Val->getValueType(1) == MVT::f64) {
1938 Chain = DAG.getCopyFromReg(Chain, PPC::F1, MVT::f64, InFlag).getValue(1);
1939 ResultVals[0] = Chain.getValue(0);
1940 Chain = DAG.getCopyFromReg(Chain, PPC::F2, MVT::f64,
1941 Chain.getValue(2)).getValue(1);
1942 ResultVals[1] = Chain.getValue(0);
1944 NodeTys.push_back(MVT::f64);
1945 NodeTys.push_back(MVT::f64);
1948 // else fall through
1950 Chain = DAG.getCopyFromReg(Chain, PPC::F1, Op.Val->getValueType(0),
1951 InFlag).getValue(1);
1952 ResultVals[0] = Chain.getValue(0);
1954 NodeTys.push_back(Op.Val->getValueType(0));
1960 Chain = DAG.getCopyFromReg(Chain, PPC::V2, Op.Val->getValueType(0),
1961 InFlag).getValue(1);
1962 ResultVals[0] = Chain.getValue(0);
1964 NodeTys.push_back(Op.Val->getValueType(0));
1968 NodeTys.push_back(MVT::Other);
1970 // If the function returns void, just return the chain.
1971 if (NumResults == 0)
1974 // Otherwise, merge everything together with a MERGE_VALUES node.
1975 ResultVals[NumResults++] = Chain;
1976 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys,
1977 ResultVals, NumResults);
1978 return Res.getValue(Op.ResNo);
1981 SDOperand PPCTargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG,
1982 TargetMachine &TM) {
1983 SmallVector<CCValAssign, 16> RVLocs;
1984 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
1985 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1986 CCState CCInfo(CC, isVarArg, TM, RVLocs);
1987 CCInfo.AnalyzeReturn(Op.Val, RetCC_PPC);
1989 // If this is the first return lowered for this function, add the regs to the
1990 // liveout set for the function.
1991 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1992 for (unsigned i = 0; i != RVLocs.size(); ++i)
1993 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1996 SDOperand Chain = Op.getOperand(0);
1999 // Copy the result values into the output registers.
2000 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2001 CCValAssign &VA = RVLocs[i];
2002 assert(VA.isRegLoc() && "Can only return in registers!");
2003 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
2004 Flag = Chain.getValue(1);
2008 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain, Flag);
2010 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain);
2013 SDOperand PPCTargetLowering::LowerSTACKRESTORE(SDOperand Op, SelectionDAG &DAG,
2014 const PPCSubtarget &Subtarget) {
2015 // When we pop the dynamic allocation we need to restore the SP link.
2017 // Get the corect type for pointers.
2018 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2020 // Construct the stack pointer operand.
2021 bool IsPPC64 = Subtarget.isPPC64();
2022 unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1;
2023 SDOperand StackPtr = DAG.getRegister(SP, PtrVT);
2025 // Get the operands for the STACKRESTORE.
2026 SDOperand Chain = Op.getOperand(0);
2027 SDOperand SaveSP = Op.getOperand(1);
2029 // Load the old link SP.
2030 SDOperand LoadLinkSP = DAG.getLoad(PtrVT, Chain, StackPtr, NULL, 0);
2032 // Restore the stack pointer.
2033 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), SP, SaveSP);
2035 // Store the old link SP.
2036 return DAG.getStore(Chain, LoadLinkSP, StackPtr, NULL, 0);
2039 SDOperand PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDOperand Op,
2041 const PPCSubtarget &Subtarget) {
2042 MachineFunction &MF = DAG.getMachineFunction();
2043 bool IsPPC64 = Subtarget.isPPC64();
2044 bool isMachoABI = Subtarget.isMachoABI();
2046 // Get current frame pointer save index. The users of this index will be
2047 // primarily DYNALLOC instructions.
2048 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2049 int FPSI = FI->getFramePointerSaveIndex();
2051 // If the frame pointer save index hasn't been defined yet.
2053 // Find out what the fix offset of the frame pointer save area.
2054 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isMachoABI);
2056 // Allocate the frame index for frame pointer save area.
2057 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
2059 FI->setFramePointerSaveIndex(FPSI);
2063 SDOperand Chain = Op.getOperand(0);
2064 SDOperand Size = Op.getOperand(1);
2066 // Get the corect type for pointers.
2067 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2069 SDOperand NegSize = DAG.getNode(ISD::SUB, PtrVT,
2070 DAG.getConstant(0, PtrVT), Size);
2071 // Construct a node for the frame pointer save index.
2072 SDOperand FPSIdx = DAG.getFrameIndex(FPSI, PtrVT);
2073 // Build a DYNALLOC node.
2074 SDOperand Ops[3] = { Chain, NegSize, FPSIdx };
2075 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
2076 return DAG.getNode(PPCISD::DYNALLOC, VTs, Ops, 3);
2080 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
2082 SDOperand PPCTargetLowering::LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
2083 // Not FP? Not a fsel.
2084 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) ||
2085 !MVT::isFloatingPoint(Op.getOperand(2).getValueType()))
2088 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2090 // Cannot handle SETEQ/SETNE.
2091 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand();
2093 MVT::ValueType ResVT = Op.getValueType();
2094 MVT::ValueType CmpVT = Op.getOperand(0).getValueType();
2095 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2096 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3);
2098 // If the RHS of the comparison is a 0.0, we don't need to do the
2099 // subtraction at all.
2100 if (isFloatingPointZero(RHS))
2102 default: break; // SETUO etc aren't handled by fsel.
2106 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
2110 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
2111 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
2112 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
2116 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
2120 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
2121 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
2122 return DAG.getNode(PPCISD::FSEL, ResVT,
2123 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV);
2128 default: break; // SETUO etc aren't handled by fsel.
2132 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
2133 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2134 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2135 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
2139 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
2140 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2141 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2142 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
2146 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
2147 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2148 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2149 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
2153 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
2154 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2155 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2156 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
2161 // FIXME: Split this code up when LegalizeDAGTypes lands.
2162 SDOperand PPCTargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
2163 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType()));
2164 SDOperand Src = Op.getOperand(0);
2165 if (Src.getValueType() == MVT::f32)
2166 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src);
2169 switch (Op.getValueType()) {
2170 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
2172 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src);
2175 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src);
2179 // Convert the FP value to an int value through memory.
2180 SDOperand FIPtr = DAG.CreateStackTemporary(MVT::f64);
2182 // Emit a store to the stack slot.
2183 SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Tmp, FIPtr, NULL, 0);
2185 // Result is a load from the stack slot. If loading 4 bytes, make sure to
2187 if (Op.getValueType() == MVT::i32)
2188 FIPtr = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr,
2189 DAG.getConstant(4, FIPtr.getValueType()));
2190 return DAG.getLoad(Op.getValueType(), Chain, FIPtr, NULL, 0);
2193 SDOperand PPCTargetLowering::LowerFP_ROUND_INREG(SDOperand Op,
2194 SelectionDAG &DAG) {
2195 assert(Op.getValueType() == MVT::ppcf128);
2196 SDNode *Node = Op.Val;
2197 assert(Node->getOperand(0).getValueType() == MVT::ppcf128);
2198 assert(Node->getOperand(0).Val->getOpcode() == ISD::BUILD_PAIR);
2199 SDOperand Lo = Node->getOperand(0).Val->getOperand(0);
2200 SDOperand Hi = Node->getOperand(0).Val->getOperand(1);
2202 // This sequence changes FPSCR to do round-to-zero, adds the two halves
2203 // of the long double, and puts FPSCR back the way it was. We do not
2204 // actually model FPSCR.
2205 std::vector<MVT::ValueType> NodeTys;
2206 SDOperand Ops[4], Result, MFFSreg, InFlag, FPreg;
2208 NodeTys.push_back(MVT::f64); // Return register
2209 NodeTys.push_back(MVT::Flag); // Returns a flag for later insns
2210 Result = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0);
2211 MFFSreg = Result.getValue(0);
2212 InFlag = Result.getValue(1);
2215 NodeTys.push_back(MVT::Flag); // Returns a flag
2216 Ops[0] = DAG.getConstant(31, MVT::i32);
2218 Result = DAG.getNode(PPCISD::MTFSB1, NodeTys, Ops, 2);
2219 InFlag = Result.getValue(0);
2222 NodeTys.push_back(MVT::Flag); // Returns a flag
2223 Ops[0] = DAG.getConstant(30, MVT::i32);
2225 Result = DAG.getNode(PPCISD::MTFSB0, NodeTys, Ops, 2);
2226 InFlag = Result.getValue(0);
2229 NodeTys.push_back(MVT::f64); // result of add
2230 NodeTys.push_back(MVT::Flag); // Returns a flag
2234 Result = DAG.getNode(PPCISD::FADDRTZ, NodeTys, Ops, 3);
2235 FPreg = Result.getValue(0);
2236 InFlag = Result.getValue(1);
2239 NodeTys.push_back(MVT::f64);
2240 Ops[0] = DAG.getConstant(1, MVT::i32);
2244 Result = DAG.getNode(PPCISD::MTFSF, NodeTys, Ops, 4);
2245 FPreg = Result.getValue(0);
2247 // We know the low half is about to be thrown away, so just use something
2249 return DAG.getNode(ISD::BUILD_PAIR, Lo.getValueType(), FPreg, FPreg);
2252 SDOperand PPCTargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
2253 if (Op.getOperand(0).getValueType() == MVT::i64) {
2254 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
2255 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
2256 if (Op.getValueType() == MVT::f32)
2257 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0));
2261 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
2262 "Unhandled SINT_TO_FP type in custom expander!");
2263 // Since we only generate this in 64-bit mode, we can take advantage of
2264 // 64-bit registers. In particular, sign extend the input value into the
2265 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
2266 // then lfd it and fcfid it.
2267 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
2268 int FrameIdx = FrameInfo->CreateStackObject(8, 8);
2269 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2270 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
2272 SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32,
2275 // STD the extended value into the stack slot.
2276 MemOperand MO(PseudoSourceValue::getFixedStack(),
2277 MemOperand::MOStore, FrameIdx, 8, 8);
2278 SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other,
2279 DAG.getEntryNode(), Ext64, FIdx,
2280 DAG.getMemOperand(MO));
2281 // Load the value as a double.
2282 SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0);
2284 // FCFID it and return it.
2285 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld);
2286 if (Op.getValueType() == MVT::f32)
2287 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0));
2291 SDOperand PPCTargetLowering::LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG) {
2293 The rounding mode is in bits 30:31 of FPSR, and has the following
2300 FLT_ROUNDS, on the other hand, expects the following:
2307 To perform the conversion, we do:
2308 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
2311 MachineFunction &MF = DAG.getMachineFunction();
2312 MVT::ValueType VT = Op.getValueType();
2313 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2314 std::vector<MVT::ValueType> NodeTys;
2315 SDOperand MFFSreg, InFlag;
2317 // Save FP Control Word to register
2318 NodeTys.push_back(MVT::f64); // return register
2319 NodeTys.push_back(MVT::Flag); // unused in this context
2320 SDOperand Chain = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0);
2322 // Save FP register to stack slot
2323 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
2324 SDOperand StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
2325 SDOperand Store = DAG.getStore(DAG.getEntryNode(), Chain,
2326 StackSlot, NULL, 0);
2328 // Load FP Control Word from low 32 bits of stack slot.
2329 SDOperand Four = DAG.getConstant(4, PtrVT);
2330 SDOperand Addr = DAG.getNode(ISD::ADD, PtrVT, StackSlot, Four);
2331 SDOperand CWD = DAG.getLoad(MVT::i32, Store, Addr, NULL, 0);
2333 // Transform as necessary
2335 DAG.getNode(ISD::AND, MVT::i32,
2336 CWD, DAG.getConstant(3, MVT::i32));
2338 DAG.getNode(ISD::SRL, MVT::i32,
2339 DAG.getNode(ISD::AND, MVT::i32,
2340 DAG.getNode(ISD::XOR, MVT::i32,
2341 CWD, DAG.getConstant(3, MVT::i32)),
2342 DAG.getConstant(3, MVT::i32)),
2343 DAG.getConstant(1, MVT::i8));
2346 DAG.getNode(ISD::XOR, MVT::i32, CWD1, CWD2);
2348 return DAG.getNode((MVT::getSizeInBits(VT) < 16 ?
2349 ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal);
2352 SDOperand PPCTargetLowering::LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) {
2353 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
2354 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
2356 // Expand into a bunch of logical ops. Note that these ops
2357 // depend on the PPC behavior for oversized shift amounts.
2358 SDOperand Lo = Op.getOperand(0);
2359 SDOperand Hi = Op.getOperand(1);
2360 SDOperand Amt = Op.getOperand(2);
2362 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
2363 DAG.getConstant(32, MVT::i32), Amt);
2364 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt);
2365 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1);
2366 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
2367 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
2368 DAG.getConstant(-32U, MVT::i32));
2369 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5);
2370 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
2371 SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt);
2372 SDOperand OutOps[] = { OutLo, OutHi };
2373 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
2377 SDOperand PPCTargetLowering::LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) {
2378 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
2379 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRL!");
2381 // Otherwise, expand into a bunch of logical ops. Note that these ops
2382 // depend on the PPC behavior for oversized shift amounts.
2383 SDOperand Lo = Op.getOperand(0);
2384 SDOperand Hi = Op.getOperand(1);
2385 SDOperand Amt = Op.getOperand(2);
2387 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
2388 DAG.getConstant(32, MVT::i32), Amt);
2389 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
2390 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
2391 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
2392 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
2393 DAG.getConstant(-32U, MVT::i32));
2394 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5);
2395 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
2396 SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt);
2397 SDOperand OutOps[] = { OutLo, OutHi };
2398 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
2402 SDOperand PPCTargetLowering::LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) {
2403 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
2404 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!");
2406 // Otherwise, expand into a bunch of logical ops, followed by a select_cc.
2407 SDOperand Lo = Op.getOperand(0);
2408 SDOperand Hi = Op.getOperand(1);
2409 SDOperand Amt = Op.getOperand(2);
2411 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
2412 DAG.getConstant(32, MVT::i32), Amt);
2413 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
2414 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
2415 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
2416 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
2417 DAG.getConstant(-32U, MVT::i32));
2418 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5);
2419 SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt);
2420 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32),
2421 Tmp4, Tmp6, ISD::SETLE);
2422 SDOperand OutOps[] = { OutLo, OutHi };
2423 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
2427 //===----------------------------------------------------------------------===//
2428 // Vector related lowering.
2431 // If this is a vector of constants or undefs, get the bits. A bit in
2432 // UndefBits is set if the corresponding element of the vector is an
2433 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
2434 // zero. Return true if this is not an array of constants, false if it is.
2436 static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
2437 uint64_t UndefBits[2]) {
2438 // Start with zero'd results.
2439 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0;
2441 unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType());
2442 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
2443 SDOperand OpVal = BV->getOperand(i);
2445 unsigned PartNo = i >= e/2; // In the upper 128 bits?
2446 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t.
2448 uint64_t EltBits = 0;
2449 if (OpVal.getOpcode() == ISD::UNDEF) {
2450 uint64_t EltUndefBits = ~0U >> (32-EltBitSize);
2451 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize);
2453 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
2454 EltBits = CN->getValue() & (~0U >> (32-EltBitSize));
2455 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
2456 assert(CN->getValueType(0) == MVT::f32 &&
2457 "Only one legal FP vector type!");
2458 EltBits = FloatToBits(CN->getValueAPF().convertToFloat());
2460 // Nonconstant element.
2464 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize);
2467 //printf("%llx %llx %llx %llx\n",
2468 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]);
2472 // If this is a splat (repetition) of a value across the whole vector, return
2473 // the smallest size that splats it. For example, "0x01010101010101..." is a
2474 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
2475 // SplatSize = 1 byte.
2476 static bool isConstantSplat(const uint64_t Bits128[2],
2477 const uint64_t Undef128[2],
2478 unsigned &SplatBits, unsigned &SplatUndef,
2479 unsigned &SplatSize) {
2481 // Don't let undefs prevent splats from matching. See if the top 64-bits are
2482 // the same as the lower 64-bits, ignoring undefs.
2483 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0]))
2484 return false; // Can't be a splat if two pieces don't match.
2486 uint64_t Bits64 = Bits128[0] | Bits128[1];
2487 uint64_t Undef64 = Undef128[0] & Undef128[1];
2489 // Check that the top 32-bits are the same as the lower 32-bits, ignoring
2491 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64))
2492 return false; // Can't be a splat if two pieces don't match.
2494 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32);
2495 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32);
2497 // If the top 16-bits are different than the lower 16-bits, ignoring
2498 // undefs, we have an i32 splat.
2499 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) {
2501 SplatUndef = Undef32;
2506 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16);
2507 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16);
2509 // If the top 8-bits are different than the lower 8-bits, ignoring
2510 // undefs, we have an i16 splat.
2511 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) {
2513 SplatUndef = Undef16;
2518 // Otherwise, we have an 8-bit splat.
2519 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8);
2520 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8);
2525 /// BuildSplatI - Build a canonical splati of Val with an element size of
2526 /// SplatSize. Cast the result to VT.
2527 static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT,
2528 SelectionDAG &DAG) {
2529 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
2531 static const MVT::ValueType VTys[] = { // canonical VT to use for each size.
2532 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
2535 MVT::ValueType ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
2537 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
2541 MVT::ValueType CanonicalVT = VTys[SplatSize-1];
2543 // Build a canonical splat for this value.
2544 SDOperand Elt = DAG.getConstant(Val, MVT::getVectorElementType(CanonicalVT));
2545 SmallVector<SDOperand, 8> Ops;
2546 Ops.assign(MVT::getVectorNumElements(CanonicalVT), Elt);
2547 SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT,
2548 &Ops[0], Ops.size());
2549 return DAG.getNode(ISD::BIT_CONVERT, ReqVT, Res);
2552 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
2553 /// specified intrinsic ID.
2554 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS,
2556 MVT::ValueType DestVT = MVT::Other) {
2557 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
2558 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
2559 DAG.getConstant(IID, MVT::i32), LHS, RHS);
2562 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
2563 /// specified intrinsic ID.
2564 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1,
2565 SDOperand Op2, SelectionDAG &DAG,
2566 MVT::ValueType DestVT = MVT::Other) {
2567 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
2568 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
2569 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
2573 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
2574 /// amount. The result has the specified value type.
2575 static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt,
2576 MVT::ValueType VT, SelectionDAG &DAG) {
2577 // Force LHS/RHS to be the right type.
2578 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS);
2579 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS);
2582 for (unsigned i = 0; i != 16; ++i)
2583 Ops[i] = DAG.getConstant(i+Amt, MVT::i32);
2584 SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS,
2585 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16));
2586 return DAG.getNode(ISD::BIT_CONVERT, VT, T);
2589 // If this is a case we can't handle, return null and let the default
2590 // expansion code take care of it. If we CAN select this case, and if it
2591 // selects to a single instruction, return Op. Otherwise, if we can codegen
2592 // this case more efficiently than a constant pool load, lower it to the
2593 // sequence of ops that should be used.
2594 SDOperand PPCTargetLowering::LowerBUILD_VECTOR(SDOperand Op,
2595 SelectionDAG &DAG) {
2596 // If this is a vector of constants or undefs, get the bits. A bit in
2597 // UndefBits is set if the corresponding element of the vector is an
2598 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
2600 uint64_t VectorBits[2];
2601 uint64_t UndefBits[2];
2602 if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits))
2603 return SDOperand(); // Not a constant vector.
2605 // If this is a splat (repetition) of a value across the whole vector, return
2606 // the smallest size that splats it. For example, "0x01010101010101..." is a
2607 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
2608 // SplatSize = 1 byte.
2609 unsigned SplatBits, SplatUndef, SplatSize;
2610 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){
2611 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0;
2613 // First, handle single instruction cases.
2616 if (SplatBits == 0) {
2617 // Canonicalize all zero vectors to be v4i32.
2618 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
2619 SDOperand Z = DAG.getConstant(0, MVT::i32);
2620 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z);
2621 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z);
2626 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
2627 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize);
2628 if (SextVal >= -16 && SextVal <= 15)
2629 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG);
2632 // Two instruction sequences.
2634 // If this value is in the range [-32,30] and is even, use:
2635 // tmp = VSPLTI[bhw], result = add tmp, tmp
2636 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
2637 Op = BuildSplatI(SextVal >> 1, SplatSize, Op.getValueType(), DAG);
2638 return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op);
2641 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
2642 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
2644 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
2645 // Make -1 and vspltisw -1:
2646 SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG);
2648 // Make the VSLW intrinsic, computing 0x8000_0000.
2649 SDOperand Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
2652 // xor by OnesV to invert it.
2653 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV);
2654 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2657 // Check to see if this is a wide variety of vsplti*, binop self cases.
2658 unsigned SplatBitSize = SplatSize*8;
2659 static const signed char SplatCsts[] = {
2660 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
2661 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
2664 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
2665 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
2666 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
2667 int i = SplatCsts[idx];
2669 // Figure out what shift amount will be used by altivec if shifted by i in
2671 unsigned TypeShiftAmt = i & (SplatBitSize-1);
2673 // vsplti + shl self.
2674 if (SextVal == (i << (int)TypeShiftAmt)) {
2675 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2676 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2677 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
2678 Intrinsic::ppc_altivec_vslw
2680 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2681 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2684 // vsplti + srl self.
2685 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
2686 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2687 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2688 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
2689 Intrinsic::ppc_altivec_vsrw
2691 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2692 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2695 // vsplti + sra self.
2696 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
2697 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2698 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2699 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
2700 Intrinsic::ppc_altivec_vsraw
2702 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2703 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2706 // vsplti + rol self.
2707 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
2708 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
2709 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2710 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2711 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
2712 Intrinsic::ppc_altivec_vrlw
2714 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2715 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2718 // t = vsplti c, result = vsldoi t, t, 1
2719 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
2720 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2721 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG);
2723 // t = vsplti c, result = vsldoi t, t, 2
2724 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
2725 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2726 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG);
2728 // t = vsplti c, result = vsldoi t, t, 3
2729 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
2730 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2731 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG);
2735 // Three instruction sequences.
2737 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
2738 if (SextVal >= 0 && SextVal <= 31) {
2739 SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG);
2740 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
2741 LHS = DAG.getNode(ISD::SUB, LHS.getValueType(), LHS, RHS);
2742 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
2744 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
2745 if (SextVal >= -31 && SextVal <= 0) {
2746 SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG);
2747 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
2748 LHS = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS);
2749 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
2756 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
2757 /// the specified operations to build the shuffle.
2758 static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS,
2759 SDOperand RHS, SelectionDAG &DAG) {
2760 unsigned OpNum = (PFEntry >> 26) & 0x0F;
2761 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
2762 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
2765 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
2777 if (OpNum == OP_COPY) {
2778 if (LHSID == (1*9+2)*9+3) return LHS;
2779 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
2783 SDOperand OpLHS, OpRHS;
2784 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG);
2785 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG);
2787 unsigned ShufIdxs[16];
2789 default: assert(0 && "Unknown i32 permute!");
2791 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
2792 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
2793 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
2794 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
2797 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
2798 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
2799 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
2800 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
2803 for (unsigned i = 0; i != 16; ++i)
2804 ShufIdxs[i] = (i&3)+0;
2807 for (unsigned i = 0; i != 16; ++i)
2808 ShufIdxs[i] = (i&3)+4;
2811 for (unsigned i = 0; i != 16; ++i)
2812 ShufIdxs[i] = (i&3)+8;
2815 for (unsigned i = 0; i != 16; ++i)
2816 ShufIdxs[i] = (i&3)+12;
2819 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG);
2821 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG);
2823 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG);
2826 for (unsigned i = 0; i != 16; ++i)
2827 Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i32);
2829 return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS,
2830 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
2833 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
2834 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
2835 /// return the code it can be lowered into. Worst case, it can always be
2836 /// lowered into a vperm.
2837 SDOperand PPCTargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op,
2838 SelectionDAG &DAG) {
2839 SDOperand V1 = Op.getOperand(0);
2840 SDOperand V2 = Op.getOperand(1);
2841 SDOperand PermMask = Op.getOperand(2);
2843 // Cases that are handled by instructions that take permute immediates
2844 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
2845 // selected by the instruction selector.
2846 if (V2.getOpcode() == ISD::UNDEF) {
2847 if (PPC::isSplatShuffleMask(PermMask.Val, 1) ||
2848 PPC::isSplatShuffleMask(PermMask.Val, 2) ||
2849 PPC::isSplatShuffleMask(PermMask.Val, 4) ||
2850 PPC::isVPKUWUMShuffleMask(PermMask.Val, true) ||
2851 PPC::isVPKUHUMShuffleMask(PermMask.Val, true) ||
2852 PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 ||
2853 PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) ||
2854 PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) ||
2855 PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) ||
2856 PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) ||
2857 PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) ||
2858 PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) {
2863 // Altivec has a variety of "shuffle immediates" that take two vector inputs
2864 // and produce a fixed permutation. If any of these match, do not lower to
2866 if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) ||
2867 PPC::isVPKUHUMShuffleMask(PermMask.Val, false) ||
2868 PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 ||
2869 PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) ||
2870 PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) ||
2871 PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) ||
2872 PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) ||
2873 PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) ||
2874 PPC::isVMRGHShuffleMask(PermMask.Val, 4, false))
2877 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
2878 // perfect shuffle table to emit an optimal matching sequence.
2879 unsigned PFIndexes[4];
2880 bool isFourElementShuffle = true;
2881 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
2882 unsigned EltNo = 8; // Start out undef.
2883 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
2884 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF)
2885 continue; // Undef, ignore it.
2887 unsigned ByteSource =
2888 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue();
2889 if ((ByteSource & 3) != j) {
2890 isFourElementShuffle = false;
2895 EltNo = ByteSource/4;
2896 } else if (EltNo != ByteSource/4) {
2897 isFourElementShuffle = false;
2901 PFIndexes[i] = EltNo;
2904 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
2905 // perfect shuffle vector to determine if it is cost effective to do this as
2906 // discrete instructions, or whether we should use a vperm.
2907 if (isFourElementShuffle) {
2908 // Compute the index in the perfect shuffle table.
2909 unsigned PFTableIndex =
2910 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
2912 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
2913 unsigned Cost = (PFEntry >> 30);
2915 // Determining when to avoid vperm is tricky. Many things affect the cost
2916 // of vperm, particularly how many times the perm mask needs to be computed.
2917 // For example, if the perm mask can be hoisted out of a loop or is already
2918 // used (perhaps because there are multiple permutes with the same shuffle
2919 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
2920 // the loop requires an extra register.
2922 // As a compromise, we only emit discrete instructions if the shuffle can be
2923 // generated in 3 or fewer operations. When we have loop information
2924 // available, if this block is within a loop, we should avoid using vperm
2925 // for 3-operation perms and use a constant pool load instead.
2927 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG);
2930 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
2931 // vector that will get spilled to the constant pool.
2932 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
2934 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
2935 // that it is in input element units, not in bytes. Convert now.
2936 MVT::ValueType EltVT = MVT::getVectorElementType(V1.getValueType());
2937 unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8;
2939 SmallVector<SDOperand, 16> ResultMask;
2940 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
2942 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
2945 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue();
2947 for (unsigned j = 0; j != BytesPerElement; ++j)
2948 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
2952 SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8,
2953 &ResultMask[0], ResultMask.size());
2954 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
2957 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
2958 /// altivec comparison. If it is, return true and fill in Opc/isDot with
2959 /// information about the intrinsic.
2960 static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc,
2962 unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue();
2965 switch (IntrinsicID) {
2966 default: return false;
2967 // Comparison predicates.
2968 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
2969 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
2970 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
2971 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
2972 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
2973 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
2974 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
2975 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
2976 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
2977 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
2978 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
2979 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
2980 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
2982 // Normal Comparisons.
2983 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
2984 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
2985 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
2986 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
2987 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
2988 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
2989 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
2990 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
2991 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
2992 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
2993 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
2994 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
2995 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
3000 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
3001 /// lower, do it, otherwise return null.
3002 SDOperand PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op,
3003 SelectionDAG &DAG) {
3004 // If this is a lowered altivec predicate compare, CompareOpc is set to the
3005 // opcode number of the comparison.
3008 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
3009 return SDOperand(); // Don't custom lower most intrinsics.
3011 // If this is a non-dot comparison, make the VCMP node and we are done.
3013 SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(),
3014 Op.getOperand(1), Op.getOperand(2),
3015 DAG.getConstant(CompareOpc, MVT::i32));
3016 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp);
3019 // Create the PPCISD altivec 'dot' comparison node.
3021 Op.getOperand(2), // LHS
3022 Op.getOperand(3), // RHS
3023 DAG.getConstant(CompareOpc, MVT::i32)
3025 std::vector<MVT::ValueType> VTs;
3026 VTs.push_back(Op.getOperand(2).getValueType());
3027 VTs.push_back(MVT::Flag);
3028 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
3030 // Now that we have the comparison, emit a copy from the CR to a GPR.
3031 // This is flagged to the above dot comparison.
3032 SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32,
3033 DAG.getRegister(PPC::CR6, MVT::i32),
3034 CompNode.getValue(1));
3036 // Unpack the result based on how the target uses it.
3037 unsigned BitNo; // Bit # of CR6.
3038 bool InvertBit; // Invert result?
3039 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
3040 default: // Can't happen, don't crash on invalid number though.
3041 case 0: // Return the value of the EQ bit of CR6.
3042 BitNo = 0; InvertBit = false;
3044 case 1: // Return the inverted value of the EQ bit of CR6.
3045 BitNo = 0; InvertBit = true;
3047 case 2: // Return the value of the LT bit of CR6.
3048 BitNo = 2; InvertBit = false;
3050 case 3: // Return the inverted value of the LT bit of CR6.
3051 BitNo = 2; InvertBit = true;
3055 // Shift the bit into the low position.
3056 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags,
3057 DAG.getConstant(8-(3-BitNo), MVT::i32));
3059 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags,
3060 DAG.getConstant(1, MVT::i32));
3062 // If we are supposed to, toggle the bit.
3064 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags,
3065 DAG.getConstant(1, MVT::i32));
3069 SDOperand PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op,
3070 SelectionDAG &DAG) {
3071 // Create a stack slot that is 16-byte aligned.
3072 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
3073 int FrameIdx = FrameInfo->CreateStackObject(16, 16);
3074 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3075 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
3077 // Store the input value into Value#0 of the stack slot.
3078 SDOperand Store = DAG.getStore(DAG.getEntryNode(),
3079 Op.getOperand(0), FIdx, NULL, 0);
3081 return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0);
3084 SDOperand PPCTargetLowering::LowerMUL(SDOperand Op, SelectionDAG &DAG) {
3085 if (Op.getValueType() == MVT::v4i32) {
3086 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3088 SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG);
3089 SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt.
3091 SDOperand RHSSwap = // = vrlw RHS, 16
3092 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG);
3094 // Shrinkify inputs to v8i16.
3095 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS);
3096 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS);
3097 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap);
3099 // Low parts multiplied together, generating 32-bit results (we ignore the
3101 SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
3102 LHS, RHS, DAG, MVT::v4i32);
3104 SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
3105 LHS, RHSSwap, Zero, DAG, MVT::v4i32);
3106 // Shift the high parts up 16 bits.
3107 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG);
3108 return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd);
3109 } else if (Op.getValueType() == MVT::v8i16) {
3110 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3112 SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG);
3114 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
3115 LHS, RHS, Zero, DAG);
3116 } else if (Op.getValueType() == MVT::v16i8) {
3117 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3119 // Multiply the even 8-bit parts, producing 16-bit sums.
3120 SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
3121 LHS, RHS, DAG, MVT::v8i16);
3122 EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts);
3124 // Multiply the odd 8-bit parts, producing 16-bit sums.
3125 SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
3126 LHS, RHS, DAG, MVT::v8i16);
3127 OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts);
3129 // Merge the results together.
3131 for (unsigned i = 0; i != 8; ++i) {
3132 Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8);
3133 Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8);
3135 return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts,
3136 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
3138 assert(0 && "Unknown mul to lower!");
3143 /// LowerOperation - Provide custom lowering hooks for some operations.
3145 SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
3146 switch (Op.getOpcode()) {
3147 default: assert(0 && "Wasn't expecting to be able to lower this!");
3148 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3149 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
3150 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3151 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
3152 case ISD::SETCC: return LowerSETCC(Op, DAG);
3154 return LowerVASTART(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
3155 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
3158 return LowerVAARG(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
3159 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
3161 case ISD::FORMAL_ARGUMENTS:
3162 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex,
3163 VarArgsStackOffset, VarArgsNumGPR,
3164 VarArgsNumFPR, PPCSubTarget);
3166 case ISD::CALL: return LowerCALL(Op, DAG, PPCSubTarget);
3167 case ISD::RET: return LowerRET(Op, DAG, getTargetMachine());
3168 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
3169 case ISD::DYNAMIC_STACKALLOC:
3170 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
3172 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
3173 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
3174 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
3175 case ISD::FP_ROUND_INREG: return LowerFP_ROUND_INREG(Op, DAG);
3176 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
3178 // Lower 64-bit shifts.
3179 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
3180 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
3181 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
3183 // Vector-related lowering.
3184 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
3185 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
3186 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
3187 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
3188 case ISD::MUL: return LowerMUL(Op, DAG);
3190 // Frame & Return address.
3191 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
3192 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
3197 SDNode *PPCTargetLowering::ExpandOperationResult(SDNode *N, SelectionDAG &DAG) {
3198 switch (N->getOpcode()) {
3199 default: assert(0 && "Wasn't expecting to be able to lower this!");
3200 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(SDOperand(N, 0), DAG).Val;
3205 //===----------------------------------------------------------------------===//
3206 // Other Lowering Code
3207 //===----------------------------------------------------------------------===//
3210 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
3211 MachineBasicBlock *BB) {
3212 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3213 assert((MI->getOpcode() == PPC::SELECT_CC_I4 ||
3214 MI->getOpcode() == PPC::SELECT_CC_I8 ||
3215 MI->getOpcode() == PPC::SELECT_CC_F4 ||
3216 MI->getOpcode() == PPC::SELECT_CC_F8 ||
3217 MI->getOpcode() == PPC::SELECT_CC_VRRC) &&
3218 "Unexpected instr type to insert");
3220 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
3221 // control-flow pattern. The incoming instruction knows the destination vreg
3222 // to set, the condition code register to branch on, the true/false values to
3223 // select between, and a branch opcode to use.
3224 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3225 ilist<MachineBasicBlock>::iterator It = BB;
3231 // cmpTY ccX, r1, r2
3233 // fallthrough --> copy0MBB
3234 MachineBasicBlock *thisMBB = BB;
3235 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
3236 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
3237 unsigned SelectPred = MI->getOperand(4).getImm();
3238 BuildMI(BB, TII->get(PPC::BCC))
3239 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
3240 MachineFunction *F = BB->getParent();
3241 F->getBasicBlockList().insert(It, copy0MBB);
3242 F->getBasicBlockList().insert(It, sinkMBB);
3243 // Update machine-CFG edges by first adding all successors of the current
3244 // block to the new block which will contain the Phi node for the select.
3245 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
3246 e = BB->succ_end(); i != e; ++i)
3247 sinkMBB->addSuccessor(*i);
3248 // Next, remove all successors of the current block, and add the true
3249 // and fallthrough blocks as its successors.
3250 while(!BB->succ_empty())
3251 BB->removeSuccessor(BB->succ_begin());
3252 BB->addSuccessor(copy0MBB);
3253 BB->addSuccessor(sinkMBB);
3256 // %FalseValue = ...
3257 // # fallthrough to sinkMBB
3260 // Update machine-CFG edges
3261 BB->addSuccessor(sinkMBB);
3264 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
3267 BuildMI(BB, TII->get(PPC::PHI), MI->getOperand(0).getReg())
3268 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
3269 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
3271 delete MI; // The pseudo instruction is gone now.
3275 //===----------------------------------------------------------------------===//
3276 // Target Optimization Hooks
3277 //===----------------------------------------------------------------------===//
3279 SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
3280 DAGCombinerInfo &DCI) const {
3281 TargetMachine &TM = getTargetMachine();
3282 SelectionDAG &DAG = DCI.DAG;
3283 switch (N->getOpcode()) {
3286 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
3287 if (C->getValue() == 0) // 0 << V -> 0.
3288 return N->getOperand(0);
3292 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
3293 if (C->getValue() == 0) // 0 >>u V -> 0.
3294 return N->getOperand(0);
3298 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
3299 if (C->getValue() == 0 || // 0 >>s V -> 0.
3300 C->isAllOnesValue()) // -1 >>s V -> -1.
3301 return N->getOperand(0);
3305 case ISD::SINT_TO_FP:
3306 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
3307 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
3308 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
3309 // We allow the src/dst to be either f32/f64, but the intermediate
3310 // type must be i64.
3311 if (N->getOperand(0).getValueType() == MVT::i64 &&
3312 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
3313 SDOperand Val = N->getOperand(0).getOperand(0);
3314 if (Val.getValueType() == MVT::f32) {
3315 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
3316 DCI.AddToWorklist(Val.Val);
3319 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val);
3320 DCI.AddToWorklist(Val.Val);
3321 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val);
3322 DCI.AddToWorklist(Val.Val);
3323 if (N->getValueType(0) == MVT::f32) {
3324 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val,
3325 DAG.getIntPtrConstant(0));
3326 DCI.AddToWorklist(Val.Val);
3329 } else if (N->getOperand(0).getValueType() == MVT::i32) {
3330 // If the intermediate type is i32, we can avoid the load/store here
3337 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
3338 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
3339 !cast<StoreSDNode>(N)->isTruncatingStore() &&
3340 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
3341 N->getOperand(1).getValueType() == MVT::i32 &&
3342 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
3343 SDOperand Val = N->getOperand(1).getOperand(0);
3344 if (Val.getValueType() == MVT::f32) {
3345 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
3346 DCI.AddToWorklist(Val.Val);
3348 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val);
3349 DCI.AddToWorklist(Val.Val);
3351 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val,
3352 N->getOperand(2), N->getOperand(3));
3353 DCI.AddToWorklist(Val.Val);
3357 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
3358 if (N->getOperand(1).getOpcode() == ISD::BSWAP &&
3359 N->getOperand(1).Val->hasOneUse() &&
3360 (N->getOperand(1).getValueType() == MVT::i32 ||
3361 N->getOperand(1).getValueType() == MVT::i16)) {
3362 SDOperand BSwapOp = N->getOperand(1).getOperand(0);
3363 // Do an any-extend to 32-bits if this is a half-word input.
3364 if (BSwapOp.getValueType() == MVT::i16)
3365 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp);
3367 return DAG.getNode(PPCISD::STBRX, MVT::Other, N->getOperand(0), BSwapOp,
3368 N->getOperand(2), N->getOperand(3),
3369 DAG.getValueType(N->getOperand(1).getValueType()));
3373 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
3374 if (ISD::isNON_EXTLoad(N->getOperand(0).Val) &&
3375 N->getOperand(0).hasOneUse() &&
3376 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
3377 SDOperand Load = N->getOperand(0);
3378 LoadSDNode *LD = cast<LoadSDNode>(Load);
3379 // Create the byte-swapping load.
3380 std::vector<MVT::ValueType> VTs;
3381 VTs.push_back(MVT::i32);
3382 VTs.push_back(MVT::Other);
3383 SDOperand MO = DAG.getMemOperand(LD->getMemOperand());
3385 LD->getChain(), // Chain
3386 LD->getBasePtr(), // Ptr
3388 DAG.getValueType(N->getValueType(0)) // VT
3390 SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4);
3392 // If this is an i16 load, insert the truncate.
3393 SDOperand ResVal = BSLoad;
3394 if (N->getValueType(0) == MVT::i16)
3395 ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad);
3397 // First, combine the bswap away. This makes the value produced by the
3399 DCI.CombineTo(N, ResVal);
3401 // Next, combine the load away, we give it a bogus result value but a real
3402 // chain result. The result value is dead because the bswap is dead.
3403 DCI.CombineTo(Load.Val, ResVal, BSLoad.getValue(1));
3405 // Return N so it doesn't get rechecked!
3406 return SDOperand(N, 0);
3410 case PPCISD::VCMP: {
3411 // If a VCMPo node already exists with exactly the same operands as this
3412 // node, use its result instead of this node (VCMPo computes both a CR6 and
3413 // a normal output).
3415 if (!N->getOperand(0).hasOneUse() &&
3416 !N->getOperand(1).hasOneUse() &&
3417 !N->getOperand(2).hasOneUse()) {
3419 // Scan all of the users of the LHS, looking for VCMPo's that match.
3420 SDNode *VCMPoNode = 0;
3422 SDNode *LHSN = N->getOperand(0).Val;
3423 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
3425 if ((*UI)->getOpcode() == PPCISD::VCMPo &&
3426 (*UI)->getOperand(1) == N->getOperand(1) &&
3427 (*UI)->getOperand(2) == N->getOperand(2) &&
3428 (*UI)->getOperand(0) == N->getOperand(0)) {
3433 // If there is no VCMPo node, or if the flag value has a single use, don't
3435 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
3438 // Look at the (necessarily single) use of the flag value. If it has a
3439 // chain, this transformation is more complex. Note that multiple things
3440 // could use the value result, which we should ignore.
3441 SDNode *FlagUser = 0;
3442 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
3443 FlagUser == 0; ++UI) {
3444 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
3446 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
3447 if (User->getOperand(i) == SDOperand(VCMPoNode, 1)) {
3454 // If the user is a MFCR instruction, we know this is safe. Otherwise we
3455 // give up for right now.
3456 if (FlagUser->getOpcode() == PPCISD::MFCR)
3457 return SDOperand(VCMPoNode, 0);
3462 // If this is a branch on an altivec predicate comparison, lower this so
3463 // that we don't have to do a MFCR: instead, branch directly on CR6. This
3464 // lowering is done pre-legalize, because the legalizer lowers the predicate
3465 // compare down to code that is difficult to reassemble.
3466 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
3467 SDOperand LHS = N->getOperand(2), RHS = N->getOperand(3);
3471 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
3472 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
3473 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
3474 assert(isDot && "Can't compare against a vector result!");
3476 // If this is a comparison against something other than 0/1, then we know
3477 // that the condition is never/always true.
3478 unsigned Val = cast<ConstantSDNode>(RHS)->getValue();
3479 if (Val != 0 && Val != 1) {
3480 if (CC == ISD::SETEQ) // Cond never true, remove branch.
3481 return N->getOperand(0);
3482 // Always !=, turn it into an unconditional branch.
3483 return DAG.getNode(ISD::BR, MVT::Other,
3484 N->getOperand(0), N->getOperand(4));
3487 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
3489 // Create the PPCISD altivec 'dot' comparison node.
3490 std::vector<MVT::ValueType> VTs;
3492 LHS.getOperand(2), // LHS of compare
3493 LHS.getOperand(3), // RHS of compare
3494 DAG.getConstant(CompareOpc, MVT::i32)
3496 VTs.push_back(LHS.getOperand(2).getValueType());
3497 VTs.push_back(MVT::Flag);
3498 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
3500 // Unpack the result based on how the target uses it.
3501 PPC::Predicate CompOpc;
3502 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) {
3503 default: // Can't happen, don't crash on invalid number though.
3504 case 0: // Branch on the value of the EQ bit of CR6.
3505 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
3507 case 1: // Branch on the inverted value of the EQ bit of CR6.
3508 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
3510 case 2: // Branch on the value of the LT bit of CR6.
3511 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
3513 case 3: // Branch on the inverted value of the LT bit of CR6.
3514 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
3518 return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0),
3519 DAG.getConstant(CompOpc, MVT::i32),
3520 DAG.getRegister(PPC::CR6, MVT::i32),
3521 N->getOperand(4), CompNode.getValue(1));
3530 //===----------------------------------------------------------------------===//
3531 // Inline Assembly Support
3532 //===----------------------------------------------------------------------===//
3534 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
3538 const SelectionDAG &DAG,
3539 unsigned Depth) const {
3540 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
3541 switch (Op.getOpcode()) {
3543 case PPCISD::LBRX: {
3544 // lhbrx is known to have the top bits cleared out.
3545 if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16)
3546 KnownZero = 0xFFFF0000;
3549 case ISD::INTRINSIC_WO_CHAIN: {
3550 switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) {
3552 case Intrinsic::ppc_altivec_vcmpbfp_p:
3553 case Intrinsic::ppc_altivec_vcmpeqfp_p:
3554 case Intrinsic::ppc_altivec_vcmpequb_p:
3555 case Intrinsic::ppc_altivec_vcmpequh_p:
3556 case Intrinsic::ppc_altivec_vcmpequw_p:
3557 case Intrinsic::ppc_altivec_vcmpgefp_p:
3558 case Intrinsic::ppc_altivec_vcmpgtfp_p:
3559 case Intrinsic::ppc_altivec_vcmpgtsb_p:
3560 case Intrinsic::ppc_altivec_vcmpgtsh_p:
3561 case Intrinsic::ppc_altivec_vcmpgtsw_p:
3562 case Intrinsic::ppc_altivec_vcmpgtub_p:
3563 case Intrinsic::ppc_altivec_vcmpgtuh_p:
3564 case Intrinsic::ppc_altivec_vcmpgtuw_p:
3565 KnownZero = ~1U; // All bits but the low one are known to be zero.
3573 /// getConstraintType - Given a constraint, return the type of
3574 /// constraint it is for this target.
3575 PPCTargetLowering::ConstraintType
3576 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
3577 if (Constraint.size() == 1) {
3578 switch (Constraint[0]) {
3585 return C_RegisterClass;
3588 return TargetLowering::getConstraintType(Constraint);
3591 std::pair<unsigned, const TargetRegisterClass*>
3592 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
3593 MVT::ValueType VT) const {
3594 if (Constraint.size() == 1) {
3595 // GCC RS6000 Constraint Letters
3596 switch (Constraint[0]) {
3599 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
3600 return std::make_pair(0U, PPC::G8RCRegisterClass);
3601 return std::make_pair(0U, PPC::GPRCRegisterClass);
3604 return std::make_pair(0U, PPC::F4RCRegisterClass);
3605 else if (VT == MVT::f64)
3606 return std::make_pair(0U, PPC::F8RCRegisterClass);
3609 return std::make_pair(0U, PPC::VRRCRegisterClass);
3611 return std::make_pair(0U, PPC::CRRCRegisterClass);
3615 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3619 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3620 /// vector. If it is invalid, don't add anything to Ops.
3621 void PPCTargetLowering::LowerAsmOperandForConstraint(SDOperand Op, char Letter,
3622 std::vector<SDOperand>&Ops,
3623 SelectionDAG &DAG) {
3624 SDOperand Result(0,0);
3635 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
3636 if (!CST) return; // Must be an immediate to match.
3637 unsigned Value = CST->getValue();
3639 default: assert(0 && "Unknown constraint letter!");
3640 case 'I': // "I" is a signed 16-bit constant.
3641 if ((short)Value == (int)Value)
3642 Result = DAG.getTargetConstant(Value, Op.getValueType());
3644 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
3645 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
3646 if ((short)Value == 0)
3647 Result = DAG.getTargetConstant(Value, Op.getValueType());
3649 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
3650 if ((Value >> 16) == 0)
3651 Result = DAG.getTargetConstant(Value, Op.getValueType());
3653 case 'M': // "M" is a constant that is greater than 31.
3655 Result = DAG.getTargetConstant(Value, Op.getValueType());
3657 case 'N': // "N" is a positive constant that is an exact power of two.
3658 if ((int)Value > 0 && isPowerOf2_32(Value))
3659 Result = DAG.getTargetConstant(Value, Op.getValueType());
3661 case 'O': // "O" is the constant zero.
3663 Result = DAG.getTargetConstant(Value, Op.getValueType());
3665 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
3666 if ((short)-Value == (int)-Value)
3667 Result = DAG.getTargetConstant(Value, Op.getValueType());
3675 Ops.push_back(Result);
3679 // Handle standard constraint letters.
3680 TargetLowering::LowerAsmOperandForConstraint(Op, Letter, Ops, DAG);
3683 // isLegalAddressingMode - Return true if the addressing mode represented
3684 // by AM is legal for this target, for a load/store of the specified type.
3685 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
3686 const Type *Ty) const {
3687 // FIXME: PPC does not allow r+i addressing modes for vectors!
3689 // PPC allows a sign-extended 16-bit immediate field.
3690 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
3693 // No global is ever allowed as a base.
3697 // PPC only support r+r,
3699 case 0: // "r+i" or just "i", depending on HasBaseReg.
3702 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
3704 // Otherwise we have r+r or r+i.
3707 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
3709 // Allow 2*r as r+r.
3712 // No other scales are supported.
3719 /// isLegalAddressImmediate - Return true if the integer value can be used
3720 /// as the offset of the target addressing mode for load / store of the
3722 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{
3723 // PPC allows a sign-extended 16-bit immediate field.
3724 return (V > -(1 << 16) && V < (1 << 16)-1);
3727 bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
3731 SDOperand PPCTargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) {
3732 // Depths > 0 not supported yet!
3733 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
3736 MachineFunction &MF = DAG.getMachineFunction();
3737 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3738 int RAIdx = FuncInfo->getReturnAddrSaveIndex();
3740 bool isPPC64 = PPCSubTarget.isPPC64();
3742 PPCFrameInfo::getReturnSaveOffset(isPPC64, PPCSubTarget.isMachoABI());
3744 // Set up a frame object for the return address.
3745 RAIdx = MF.getFrameInfo()->CreateFixedObject(isPPC64 ? 8 : 4, Offset);
3747 // Remember it for next time.
3748 FuncInfo->setReturnAddrSaveIndex(RAIdx);
3750 // Make sure the function really does not optimize away the store of the RA
3752 FuncInfo->setLRStoreRequired();
3755 // Just load the return address off the stack.
3756 SDOperand RetAddrFI = DAG.getFrameIndex(RAIdx, getPointerTy());
3757 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
3760 SDOperand PPCTargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) {
3761 // Depths > 0 not supported yet!
3762 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
3765 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3766 bool isPPC64 = PtrVT == MVT::i64;
3768 MachineFunction &MF = DAG.getMachineFunction();
3769 MachineFrameInfo *MFI = MF.getFrameInfo();
3770 bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects())
3771 && MFI->getStackSize();
3774 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::X31 : PPC::X1,
3777 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::R31 : PPC::R1,