1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPerfectShuffle.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCTargetObjectFile.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28 #include "llvm/IR/CallingConv.h"
29 #include "llvm/IR/Constants.h"
30 #include "llvm/IR/DerivedTypes.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/Intrinsics.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/Target/TargetOptions.h"
40 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
41 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
43 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
44 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
46 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
47 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
49 static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) {
50 if (TM.getSubtargetImpl()->isDarwin())
51 return new TargetLoweringObjectFileMachO();
53 if (TM.getSubtargetImpl()->isSVR4ABI())
54 return new PPC64LinuxTargetObjectFile();
56 return new TargetLoweringObjectFileELF();
59 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
60 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) {
61 const PPCSubtarget *Subtarget = &TM.getSubtarget<PPCSubtarget>();
65 // Use _setjmp/_longjmp instead of setjmp/longjmp.
66 setUseUnderscoreSetJmp(true);
67 setUseUnderscoreLongJmp(true);
69 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
70 // arguments are at least 4/8 bytes aligned.
71 bool isPPC64 = Subtarget->isPPC64();
72 setMinStackArgumentAlignment(isPPC64 ? 8:4);
74 // Set up the register classes.
75 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
76 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
77 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
79 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
80 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
81 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
83 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
85 // PowerPC has pre-inc load and store's.
86 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
87 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
91 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
92 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
93 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
97 // This is used in the ppcf128->int sequence. Note it has different semantics
98 // from FP_ROUND: that rounds to nearest, this rounds to zero.
99 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
101 // We do not currently implement these libm ops for PowerPC.
102 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
103 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
104 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
105 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
106 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
107 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
109 // PowerPC has no SREM/UREM instructions
110 setOperationAction(ISD::SREM, MVT::i32, Expand);
111 setOperationAction(ISD::UREM, MVT::i32, Expand);
112 setOperationAction(ISD::SREM, MVT::i64, Expand);
113 setOperationAction(ISD::UREM, MVT::i64, Expand);
115 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
116 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
117 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
118 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
119 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
120 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
121 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
122 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
123 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
125 // We don't support sin/cos/sqrt/fmod/pow
126 setOperationAction(ISD::FSIN , MVT::f64, Expand);
127 setOperationAction(ISD::FCOS , MVT::f64, Expand);
128 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
129 setOperationAction(ISD::FREM , MVT::f64, Expand);
130 setOperationAction(ISD::FPOW , MVT::f64, Expand);
131 setOperationAction(ISD::FMA , MVT::f64, Legal);
132 setOperationAction(ISD::FSIN , MVT::f32, Expand);
133 setOperationAction(ISD::FCOS , MVT::f32, Expand);
134 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
135 setOperationAction(ISD::FREM , MVT::f32, Expand);
136 setOperationAction(ISD::FPOW , MVT::f32, Expand);
137 setOperationAction(ISD::FMA , MVT::f32, Legal);
139 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
141 // If we're enabling GP optimizations, use hardware square root
142 if (!Subtarget->hasFSQRT() &&
143 !(TM.Options.UnsafeFPMath &&
144 Subtarget->hasFRSQRTE() && Subtarget->hasFRE()))
145 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
147 if (!Subtarget->hasFSQRT() &&
148 !(TM.Options.UnsafeFPMath &&
149 Subtarget->hasFRSQRTES() && Subtarget->hasFRES()))
150 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
152 if (Subtarget->hasFCPSGN()) {
153 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
154 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
156 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
157 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
160 if (Subtarget->hasFPRND()) {
161 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
162 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
163 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
164 setOperationAction(ISD::FROUND, MVT::f64, Legal);
166 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
167 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
168 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
169 setOperationAction(ISD::FROUND, MVT::f32, Legal);
172 // PowerPC does not have BSWAP, CTPOP or CTTZ
173 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
174 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
175 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
176 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
177 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
178 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
179 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
180 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
182 if (Subtarget->hasPOPCNTD()) {
183 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
184 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
186 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
187 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
190 // PowerPC does not have ROTR
191 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
192 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
194 // PowerPC does not have Select
195 setOperationAction(ISD::SELECT, MVT::i32, Expand);
196 setOperationAction(ISD::SELECT, MVT::i64, Expand);
197 setOperationAction(ISD::SELECT, MVT::f32, Expand);
198 setOperationAction(ISD::SELECT, MVT::f64, Expand);
200 // PowerPC wants to turn select_cc of FP into fsel when possible.
201 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
202 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
204 // PowerPC wants to optimize integer setcc a bit
205 setOperationAction(ISD::SETCC, MVT::i32, Custom);
207 // PowerPC does not have BRCOND which requires SetCC
208 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
210 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
212 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
213 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
215 // PowerPC does not have [U|S]INT_TO_FP
216 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
217 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
219 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
220 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
221 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
222 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
224 // We cannot sextinreg(i1). Expand to shifts.
225 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
227 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
228 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
229 // support continuation, user-level threading, and etc.. As a result, no
230 // other SjLj exception interfaces are implemented and please don't build
231 // your own exception handling based on them.
232 // LLVM/Clang supports zero-cost DWARF exception handling.
233 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
234 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
236 // We want to legalize GlobalAddress and ConstantPool nodes into the
237 // appropriate instructions to materialize the address.
238 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
239 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
240 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
241 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
242 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
243 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
244 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
245 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
246 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
247 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
250 setOperationAction(ISD::TRAP, MVT::Other, Legal);
252 // TRAMPOLINE is custom lowered.
253 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
254 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
256 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
257 setOperationAction(ISD::VASTART , MVT::Other, Custom);
259 if (Subtarget->isSVR4ABI()) {
261 // VAARG always uses double-word chunks, so promote anything smaller.
262 setOperationAction(ISD::VAARG, MVT::i1, Promote);
263 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
264 setOperationAction(ISD::VAARG, MVT::i8, Promote);
265 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
266 setOperationAction(ISD::VAARG, MVT::i16, Promote);
267 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
268 setOperationAction(ISD::VAARG, MVT::i32, Promote);
269 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
270 setOperationAction(ISD::VAARG, MVT::Other, Expand);
272 // VAARG is custom lowered with the 32-bit SVR4 ABI.
273 setOperationAction(ISD::VAARG, MVT::Other, Custom);
274 setOperationAction(ISD::VAARG, MVT::i64, Custom);
277 setOperationAction(ISD::VAARG, MVT::Other, Expand);
279 if (Subtarget->isSVR4ABI() && !isPPC64)
280 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
281 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
283 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
285 // Use the default implementation.
286 setOperationAction(ISD::VAEND , MVT::Other, Expand);
287 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
288 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
289 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
290 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
292 // We want to custom lower some of our intrinsics.
293 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
295 // To handle counter-based loop conditions.
296 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
298 // Comparisons that require checking two conditions.
299 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
300 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
301 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
302 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
303 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
304 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
305 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
306 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
307 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
308 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
309 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
310 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
312 if (Subtarget->has64BitSupport()) {
313 // They also have instructions for converting between i64 and fp.
314 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
315 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
316 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
317 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
318 // This is just the low 32 bits of a (signed) fp->i64 conversion.
319 // We cannot do this with Promote because i64 is not a legal type.
320 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
322 if (PPCSubTarget.hasLFIWAX() || Subtarget->isPPC64())
323 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
325 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
326 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
329 // With the instructions enabled under FPCVT, we can do everything.
330 if (PPCSubTarget.hasFPCVT()) {
331 if (Subtarget->has64BitSupport()) {
332 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
333 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
334 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
335 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
338 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
339 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
340 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
341 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
344 if (Subtarget->use64BitRegs()) {
345 // 64-bit PowerPC implementations can support i64 types directly
346 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
347 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
348 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
349 // 64-bit PowerPC wants to expand i128 shifts itself.
350 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
351 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
352 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
354 // 32-bit PowerPC wants to expand i64 shifts itself.
355 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
356 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
357 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
360 if (Subtarget->hasAltivec()) {
361 // First set operation action for all vector types to expand. Then we
362 // will selectively turn on ones that can be effectively codegen'd.
363 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
364 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
365 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
367 // add/sub are legal for all supported vector VT's.
368 setOperationAction(ISD::ADD , VT, Legal);
369 setOperationAction(ISD::SUB , VT, Legal);
371 // We promote all shuffles to v16i8.
372 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
373 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
375 // We promote all non-typed operations to v4i32.
376 setOperationAction(ISD::AND , VT, Promote);
377 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
378 setOperationAction(ISD::OR , VT, Promote);
379 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
380 setOperationAction(ISD::XOR , VT, Promote);
381 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
382 setOperationAction(ISD::LOAD , VT, Promote);
383 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
384 setOperationAction(ISD::SELECT, VT, Promote);
385 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
386 setOperationAction(ISD::STORE, VT, Promote);
387 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
389 // No other operations are legal.
390 setOperationAction(ISD::MUL , VT, Expand);
391 setOperationAction(ISD::SDIV, VT, Expand);
392 setOperationAction(ISD::SREM, VT, Expand);
393 setOperationAction(ISD::UDIV, VT, Expand);
394 setOperationAction(ISD::UREM, VT, Expand);
395 setOperationAction(ISD::FDIV, VT, Expand);
396 setOperationAction(ISD::FREM, VT, Expand);
397 setOperationAction(ISD::FNEG, VT, Expand);
398 setOperationAction(ISD::FSQRT, VT, Expand);
399 setOperationAction(ISD::FLOG, VT, Expand);
400 setOperationAction(ISD::FLOG10, VT, Expand);
401 setOperationAction(ISD::FLOG2, VT, Expand);
402 setOperationAction(ISD::FEXP, VT, Expand);
403 setOperationAction(ISD::FEXP2, VT, Expand);
404 setOperationAction(ISD::FSIN, VT, Expand);
405 setOperationAction(ISD::FCOS, VT, Expand);
406 setOperationAction(ISD::FABS, VT, Expand);
407 setOperationAction(ISD::FPOWI, VT, Expand);
408 setOperationAction(ISD::FFLOOR, VT, Expand);
409 setOperationAction(ISD::FCEIL, VT, Expand);
410 setOperationAction(ISD::FTRUNC, VT, Expand);
411 setOperationAction(ISD::FRINT, VT, Expand);
412 setOperationAction(ISD::FNEARBYINT, VT, Expand);
413 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
414 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
415 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
416 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
417 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
418 setOperationAction(ISD::UDIVREM, VT, Expand);
419 setOperationAction(ISD::SDIVREM, VT, Expand);
420 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
421 setOperationAction(ISD::FPOW, VT, Expand);
422 setOperationAction(ISD::CTPOP, VT, Expand);
423 setOperationAction(ISD::CTLZ, VT, Expand);
424 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
425 setOperationAction(ISD::CTTZ, VT, Expand);
426 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
427 setOperationAction(ISD::VSELECT, VT, Expand);
428 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
430 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
431 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
432 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
433 setTruncStoreAction(VT, InnerVT, Expand);
435 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
436 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
437 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
440 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
441 // with merges, splats, etc.
442 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
444 setOperationAction(ISD::AND , MVT::v4i32, Legal);
445 setOperationAction(ISD::OR , MVT::v4i32, Legal);
446 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
447 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
448 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
449 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
450 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
451 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
452 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
453 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
454 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
455 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
456 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
457 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
459 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
460 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
461 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
462 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
464 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
465 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
467 if (TM.Options.UnsafeFPMath) {
468 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
469 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
472 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
473 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
474 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
476 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
477 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
479 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
480 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
481 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
482 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
484 // Altivec does not contain unordered floating-point compare instructions
485 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
486 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
487 setCondCodeAction(ISD::SETUGT, MVT::v4f32, Expand);
488 setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand);
489 setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand);
490 setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand);
492 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
493 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
496 if (Subtarget->has64BitSupport()) {
497 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
498 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
501 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
502 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
503 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
504 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
506 setBooleanContents(ZeroOrOneBooleanContent);
507 // Altivec instructions set fields to all zeros or all ones.
508 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
511 setStackPointerRegisterToSaveRestore(PPC::X1);
512 setExceptionPointerRegister(PPC::X3);
513 setExceptionSelectorRegister(PPC::X4);
515 setStackPointerRegisterToSaveRestore(PPC::R1);
516 setExceptionPointerRegister(PPC::R3);
517 setExceptionSelectorRegister(PPC::R4);
520 // We have target-specific dag combine patterns for the following nodes:
521 setTargetDAGCombine(ISD::SINT_TO_FP);
522 setTargetDAGCombine(ISD::LOAD);
523 setTargetDAGCombine(ISD::STORE);
524 setTargetDAGCombine(ISD::BR_CC);
525 setTargetDAGCombine(ISD::BSWAP);
526 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
528 // Use reciprocal estimates.
529 if (TM.Options.UnsafeFPMath) {
530 setTargetDAGCombine(ISD::FDIV);
531 setTargetDAGCombine(ISD::FSQRT);
534 // Darwin long double math library functions have $LDBL128 appended.
535 if (Subtarget->isDarwin()) {
536 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
537 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
538 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
539 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
540 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
541 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
542 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
543 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
544 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
545 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
548 setMinFunctionAlignment(2);
549 if (PPCSubTarget.isDarwin())
550 setPrefFunctionAlignment(4);
552 if (isPPC64 && Subtarget->isJITCodeModel())
553 // Temporary workaround for the inability of PPC64 JIT to handle jump
555 setSupportJumpTables(false);
557 setInsertFencesForAtomic(true);
559 if (Subtarget->enableMachineScheduler())
560 setSchedulingPreference(Sched::Source);
562 setSchedulingPreference(Sched::Hybrid);
564 computeRegisterProperties();
566 // The Freescale cores does better with aggressive inlining of memcpy and
567 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores).
568 if (Subtarget->getDarwinDirective() == PPC::DIR_E500mc ||
569 Subtarget->getDarwinDirective() == PPC::DIR_E5500) {
570 MaxStoresPerMemset = 32;
571 MaxStoresPerMemsetOptSize = 16;
572 MaxStoresPerMemcpy = 32;
573 MaxStoresPerMemcpyOptSize = 8;
574 MaxStoresPerMemmove = 32;
575 MaxStoresPerMemmoveOptSize = 8;
577 setPrefFunctionAlignment(4);
581 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
582 /// the desired ByVal argument alignment.
583 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
584 unsigned MaxMaxAlign) {
585 if (MaxAlign == MaxMaxAlign)
587 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
588 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
590 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
592 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
593 unsigned EltAlign = 0;
594 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
595 if (EltAlign > MaxAlign)
597 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
598 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
599 unsigned EltAlign = 0;
600 getMaxByValAlign(STy->getElementType(i), EltAlign, MaxMaxAlign);
601 if (EltAlign > MaxAlign)
603 if (MaxAlign == MaxMaxAlign)
609 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
610 /// function arguments in the caller parameter area.
611 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
612 // Darwin passes everything on 4 byte boundary.
613 if (PPCSubTarget.isDarwin())
616 // 16byte and wider vectors are passed on 16byte boundary.
617 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
618 unsigned Align = PPCSubTarget.isPPC64() ? 8 : 4;
619 if (PPCSubTarget.hasAltivec() || PPCSubTarget.hasQPX())
620 getMaxByValAlign(Ty, Align, PPCSubTarget.hasQPX() ? 32 : 16);
624 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
627 case PPCISD::FSEL: return "PPCISD::FSEL";
628 case PPCISD::FCFID: return "PPCISD::FCFID";
629 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
630 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
631 case PPCISD::FRE: return "PPCISD::FRE";
632 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
633 case PPCISD::STFIWX: return "PPCISD::STFIWX";
634 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
635 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
636 case PPCISD::VPERM: return "PPCISD::VPERM";
637 case PPCISD::Hi: return "PPCISD::Hi";
638 case PPCISD::Lo: return "PPCISD::Lo";
639 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
640 case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE";
641 case PPCISD::LOAD: return "PPCISD::LOAD";
642 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
643 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
644 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
645 case PPCISD::SRL: return "PPCISD::SRL";
646 case PPCISD::SRA: return "PPCISD::SRA";
647 case PPCISD::SHL: return "PPCISD::SHL";
648 case PPCISD::CALL: return "PPCISD::CALL";
649 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
650 case PPCISD::MTCTR: return "PPCISD::MTCTR";
651 case PPCISD::BCTRL: return "PPCISD::BCTRL";
652 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
653 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
654 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
655 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
656 case PPCISD::VCMP: return "PPCISD::VCMP";
657 case PPCISD::VCMPo: return "PPCISD::VCMPo";
658 case PPCISD::LBRX: return "PPCISD::LBRX";
659 case PPCISD::STBRX: return "PPCISD::STBRX";
660 case PPCISD::LARX: return "PPCISD::LARX";
661 case PPCISD::STCX: return "PPCISD::STCX";
662 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
663 case PPCISD::BDNZ: return "PPCISD::BDNZ";
664 case PPCISD::BDZ: return "PPCISD::BDZ";
665 case PPCISD::MFFS: return "PPCISD::MFFS";
666 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
667 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
668 case PPCISD::CR6SET: return "PPCISD::CR6SET";
669 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
670 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
671 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
672 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
673 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
674 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
675 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
676 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
677 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
678 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
679 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
680 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
681 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
682 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
683 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
684 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
685 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
686 case PPCISD::SC: return "PPCISD::SC";
690 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
693 return VT.changeVectorElementTypeToInteger();
696 //===----------------------------------------------------------------------===//
697 // Node matching predicates, for use by the tblgen matching code.
698 //===----------------------------------------------------------------------===//
700 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
701 static bool isFloatingPointZero(SDValue Op) {
702 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
703 return CFP->getValueAPF().isZero();
704 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
705 // Maybe this has already been legalized into the constant pool?
706 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
707 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
708 return CFP->getValueAPF().isZero();
713 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
714 /// true if Op is undef or if it matches the specified value.
715 static bool isConstantOrUndef(int Op, int Val) {
716 return Op < 0 || Op == Val;
719 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
720 /// VPKUHUM instruction.
721 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
723 for (unsigned i = 0; i != 16; ++i)
724 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
727 for (unsigned i = 0; i != 8; ++i)
728 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) ||
729 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1))
735 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
736 /// VPKUWUM instruction.
737 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
739 for (unsigned i = 0; i != 16; i += 2)
740 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
741 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
744 for (unsigned i = 0; i != 8; i += 2)
745 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
746 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) ||
747 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) ||
748 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3))
754 /// isVMerge - Common function, used to match vmrg* shuffles.
756 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
757 unsigned LHSStart, unsigned RHSStart) {
758 assert(N->getValueType(0) == MVT::v16i8 &&
759 "PPC only supports shuffles by bytes!");
760 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
761 "Unsupported merge size!");
763 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
764 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
765 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
766 LHSStart+j+i*UnitSize) ||
767 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
768 RHSStart+j+i*UnitSize))
774 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
775 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
776 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
779 return isVMerge(N, UnitSize, 8, 24);
780 return isVMerge(N, UnitSize, 8, 8);
783 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
784 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
785 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
788 return isVMerge(N, UnitSize, 0, 16);
789 return isVMerge(N, UnitSize, 0, 0);
793 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
794 /// amount, otherwise return -1.
795 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
796 assert(N->getValueType(0) == MVT::v16i8 &&
797 "PPC only supports shuffles by bytes!");
799 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
801 // Find the first non-undef value in the shuffle mask.
803 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
806 if (i == 16) return -1; // all undef.
808 // Otherwise, check to see if the rest of the elements are consecutively
809 // numbered from this value.
810 unsigned ShiftAmt = SVOp->getMaskElt(i);
811 if (ShiftAmt < i) return -1;
815 // Check the rest of the elements to see if they are consecutive.
816 for (++i; i != 16; ++i)
817 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
820 // Check the rest of the elements to see if they are consecutive.
821 for (++i; i != 16; ++i)
822 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
828 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
829 /// specifies a splat of a single element that is suitable for input to
830 /// VSPLTB/VSPLTH/VSPLTW.
831 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
832 assert(N->getValueType(0) == MVT::v16i8 &&
833 (EltSize == 1 || EltSize == 2 || EltSize == 4));
835 // This is a splat operation if each element of the permute is the same, and
836 // if the value doesn't reference the second vector.
837 unsigned ElementBase = N->getMaskElt(0);
839 // FIXME: Handle UNDEF elements too!
840 if (ElementBase >= 16)
843 // Check that the indices are consecutive, in the case of a multi-byte element
844 // splatted with a v16i8 mask.
845 for (unsigned i = 1; i != EltSize; ++i)
846 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
849 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
850 if (N->getMaskElt(i) < 0) continue;
851 for (unsigned j = 0; j != EltSize; ++j)
852 if (N->getMaskElt(i+j) != N->getMaskElt(j))
858 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
860 bool PPC::isAllNegativeZeroVector(SDNode *N) {
861 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
863 APInt APVal, APUndef;
867 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
868 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
869 return CFP->getValueAPF().isNegZero();
874 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
875 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
876 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
877 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
878 assert(isSplatShuffleMask(SVOp, EltSize));
879 return SVOp->getMaskElt(0) / EltSize;
882 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
883 /// by using a vspltis[bhw] instruction of the specified element size, return
884 /// the constant being splatted. The ByteSize field indicates the number of
885 /// bytes of each element [124] -> [bhw].
886 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
889 // If ByteSize of the splat is bigger than the element size of the
890 // build_vector, then we have a case where we are checking for a splat where
891 // multiple elements of the buildvector are folded together into a single
892 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
893 unsigned EltSize = 16/N->getNumOperands();
894 if (EltSize < ByteSize) {
895 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
896 SDValue UniquedVals[4];
897 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
899 // See if all of the elements in the buildvector agree across.
900 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
901 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
902 // If the element isn't a constant, bail fully out.
903 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
906 if (UniquedVals[i&(Multiple-1)].getNode() == 0)
907 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
908 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
909 return SDValue(); // no match.
912 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
913 // either constant or undef values that are identical for each chunk. See
914 // if these chunks can form into a larger vspltis*.
916 // Check to see if all of the leading entries are either 0 or -1. If
917 // neither, then this won't fit into the immediate field.
918 bool LeadingZero = true;
919 bool LeadingOnes = true;
920 for (unsigned i = 0; i != Multiple-1; ++i) {
921 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs.
923 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
924 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
926 // Finally, check the least significant entry.
928 if (UniquedVals[Multiple-1].getNode() == 0)
929 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
930 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
932 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
935 if (UniquedVals[Multiple-1].getNode() == 0)
936 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
937 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
938 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
939 return DAG.getTargetConstant(Val, MVT::i32);
945 // Check to see if this buildvec has a single non-undef value in its elements.
946 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
947 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
948 if (OpVal.getNode() == 0)
949 OpVal = N->getOperand(i);
950 else if (OpVal != N->getOperand(i))
954 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def.
956 unsigned ValSizeInBytes = EltSize;
958 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
959 Value = CN->getZExtValue();
960 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
961 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
962 Value = FloatToBits(CN->getValueAPF().convertToFloat());
965 // If the splat value is larger than the element value, then we can never do
966 // this splat. The only case that we could fit the replicated bits into our
967 // immediate field for would be zero, and we prefer to use vxor for it.
968 if (ValSizeInBytes < ByteSize) return SDValue();
970 // If the element value is larger than the splat value, cut it in half and
971 // check to see if the two halves are equal. Continue doing this until we
972 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
973 while (ValSizeInBytes > ByteSize) {
974 ValSizeInBytes >>= 1;
976 // If the top half equals the bottom half, we're still ok.
977 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
978 (Value & ((1 << (8*ValSizeInBytes))-1)))
982 // Properly sign extend the value.
983 int MaskVal = SignExtend32(Value, ByteSize * 8);
985 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
986 if (MaskVal == 0) return SDValue();
988 // Finally, if this value fits in a 5 bit sext field, return it
989 if (SignExtend32<5>(MaskVal) == MaskVal)
990 return DAG.getTargetConstant(MaskVal, MVT::i32);
994 //===----------------------------------------------------------------------===//
995 // Addressing Mode Selection
996 //===----------------------------------------------------------------------===//
998 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
999 /// or 64-bit immediate, and if the value can be accurately represented as a
1000 /// sign extension from a 16-bit value. If so, this returns true and the
1002 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1003 if (N->getOpcode() != ISD::Constant)
1006 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1007 if (N->getValueType(0) == MVT::i32)
1008 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1010 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1012 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1013 return isIntS16Immediate(Op.getNode(), Imm);
1017 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1018 /// can be represented as an indexed [r+r] operation. Returns false if it
1019 /// can be more efficiently represented with [r+imm].
1020 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1022 SelectionDAG &DAG) const {
1024 if (N.getOpcode() == ISD::ADD) {
1025 if (isIntS16Immediate(N.getOperand(1), imm))
1026 return false; // r+i
1027 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1028 return false; // r+i
1030 Base = N.getOperand(0);
1031 Index = N.getOperand(1);
1033 } else if (N.getOpcode() == ISD::OR) {
1034 if (isIntS16Immediate(N.getOperand(1), imm))
1035 return false; // r+i can fold it if we can.
1037 // If this is an or of disjoint bitfields, we can codegen this as an add
1038 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1040 APInt LHSKnownZero, LHSKnownOne;
1041 APInt RHSKnownZero, RHSKnownOne;
1042 DAG.ComputeMaskedBits(N.getOperand(0),
1043 LHSKnownZero, LHSKnownOne);
1045 if (LHSKnownZero.getBoolValue()) {
1046 DAG.ComputeMaskedBits(N.getOperand(1),
1047 RHSKnownZero, RHSKnownOne);
1048 // If all of the bits are known zero on the LHS or RHS, the add won't
1050 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1051 Base = N.getOperand(0);
1052 Index = N.getOperand(1);
1061 // If we happen to be doing an i64 load or store into a stack slot that has
1062 // less than a 4-byte alignment, then the frame-index elimination may need to
1063 // use an indexed load or store instruction (because the offset may not be a
1064 // multiple of 4). The extra register needed to hold the offset comes from the
1065 // register scavenger, and it is possible that the scavenger will need to use
1066 // an emergency spill slot. As a result, we need to make sure that a spill slot
1067 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1069 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1070 // FIXME: This does not handle the LWA case.
1074 // NOTE: We'll exclude negative FIs here, which come from argument
1075 // lowering, because there are no known test cases triggering this problem
1076 // using packed structures (or similar). We can remove this exclusion if
1077 // we find such a test case. The reason why this is so test-case driven is
1078 // because this entire 'fixup' is only to prevent crashes (from the
1079 // register scavenger) on not-really-valid inputs. For example, if we have:
1081 // %b = bitcast i1* %a to i64*
1082 // store i64* a, i64 b
1083 // then the store should really be marked as 'align 1', but is not. If it
1084 // were marked as 'align 1' then the indexed form would have been
1085 // instruction-selected initially, and the problem this 'fixup' is preventing
1086 // won't happen regardless.
1090 MachineFunction &MF = DAG.getMachineFunction();
1091 MachineFrameInfo *MFI = MF.getFrameInfo();
1093 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1097 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1098 FuncInfo->setHasNonRISpills();
1101 /// Returns true if the address N can be represented by a base register plus
1102 /// a signed 16-bit displacement [r+imm], and if it is not better
1103 /// represented as reg+reg. If Aligned is true, only accept displacements
1104 /// suitable for STD and friends, i.e. multiples of 4.
1105 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1108 bool Aligned) const {
1109 // FIXME dl should come from parent load or store, not from address
1111 // If this can be more profitably realized as r+r, fail.
1112 if (SelectAddressRegReg(N, Disp, Base, DAG))
1115 if (N.getOpcode() == ISD::ADD) {
1117 if (isIntS16Immediate(N.getOperand(1), imm) &&
1118 (!Aligned || (imm & 3) == 0)) {
1119 Disp = DAG.getTargetConstant(imm, N.getValueType());
1120 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1121 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1122 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1124 Base = N.getOperand(0);
1126 return true; // [r+i]
1127 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1128 // Match LOAD (ADD (X, Lo(G))).
1129 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1130 && "Cannot handle constant offsets yet!");
1131 Disp = N.getOperand(1).getOperand(0); // The global address.
1132 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1133 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1134 Disp.getOpcode() == ISD::TargetConstantPool ||
1135 Disp.getOpcode() == ISD::TargetJumpTable);
1136 Base = N.getOperand(0);
1137 return true; // [&g+r]
1139 } else if (N.getOpcode() == ISD::OR) {
1141 if (isIntS16Immediate(N.getOperand(1), imm) &&
1142 (!Aligned || (imm & 3) == 0)) {
1143 // If this is an or of disjoint bitfields, we can codegen this as an add
1144 // (for better address arithmetic) if the LHS and RHS of the OR are
1145 // provably disjoint.
1146 APInt LHSKnownZero, LHSKnownOne;
1147 DAG.ComputeMaskedBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1149 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1150 // If all of the bits are known zero on the LHS or RHS, the add won't
1152 Base = N.getOperand(0);
1153 Disp = DAG.getTargetConstant(imm, N.getValueType());
1157 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1158 // Loading from a constant address.
1160 // If this address fits entirely in a 16-bit sext immediate field, codegen
1163 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1164 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1165 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1166 CN->getValueType(0));
1170 // Handle 32-bit sext immediates with LIS + addr mode.
1171 if ((CN->getValueType(0) == MVT::i32 ||
1172 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1173 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1174 int Addr = (int)CN->getZExtValue();
1176 // Otherwise, break this down into an LIS + disp.
1177 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1179 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1180 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1181 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1186 Disp = DAG.getTargetConstant(0, getPointerTy());
1187 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1188 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1189 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1192 return true; // [r+0]
1195 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1196 /// represented as an indexed [r+r] operation.
1197 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1199 SelectionDAG &DAG) const {
1200 // Check to see if we can easily represent this as an [r+r] address. This
1201 // will fail if it thinks that the address is more profitably represented as
1202 // reg+imm, e.g. where imm = 0.
1203 if (SelectAddressRegReg(N, Base, Index, DAG))
1206 // If the operand is an addition, always emit this as [r+r], since this is
1207 // better (for code size, and execution, as the memop does the add for free)
1208 // than emitting an explicit add.
1209 if (N.getOpcode() == ISD::ADD) {
1210 Base = N.getOperand(0);
1211 Index = N.getOperand(1);
1215 // Otherwise, do it the hard way, using R0 as the base register.
1216 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1222 /// getPreIndexedAddressParts - returns true by value, base pointer and
1223 /// offset pointer and addressing mode by reference if the node's address
1224 /// can be legally represented as pre-indexed load / store address.
1225 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1227 ISD::MemIndexedMode &AM,
1228 SelectionDAG &DAG) const {
1229 if (DisablePPCPreinc) return false;
1235 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1236 Ptr = LD->getBasePtr();
1237 VT = LD->getMemoryVT();
1238 Alignment = LD->getAlignment();
1239 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1240 Ptr = ST->getBasePtr();
1241 VT = ST->getMemoryVT();
1242 Alignment = ST->getAlignment();
1247 // PowerPC doesn't have preinc load/store instructions for vectors.
1251 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1253 // Common code will reject creating a pre-inc form if the base pointer
1254 // is a frame index, or if N is a store and the base pointer is either
1255 // the same as or a predecessor of the value being stored. Check for
1256 // those situations here, and try with swapped Base/Offset instead.
1259 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1262 SDValue Val = cast<StoreSDNode>(N)->getValue();
1263 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1268 std::swap(Base, Offset);
1274 // LDU/STU can only handle immediates that are a multiple of 4.
1275 if (VT != MVT::i64) {
1276 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1279 // LDU/STU need an address with at least 4-byte alignment.
1283 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1287 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1288 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1289 // sext i32 to i64 when addr mode is r+i.
1290 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1291 LD->getExtensionType() == ISD::SEXTLOAD &&
1292 isa<ConstantSDNode>(Offset))
1300 //===----------------------------------------------------------------------===//
1301 // LowerOperation implementation
1302 //===----------------------------------------------------------------------===//
1304 /// GetLabelAccessInfo - Return true if we should reference labels using a
1305 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1306 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1307 unsigned &LoOpFlags, const GlobalValue *GV = 0) {
1308 HiOpFlags = PPCII::MO_HA;
1309 LoOpFlags = PPCII::MO_LO;
1311 // Don't use the pic base if not in PIC relocation model. Or if we are on a
1312 // non-darwin platform. We don't support PIC on other platforms yet.
1313 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ &&
1314 TM.getSubtarget<PPCSubtarget>().isDarwin();
1316 HiOpFlags |= PPCII::MO_PIC_FLAG;
1317 LoOpFlags |= PPCII::MO_PIC_FLAG;
1320 // If this is a reference to a global value that requires a non-lazy-ptr, make
1321 // sure that instruction lowering adds it.
1322 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1323 HiOpFlags |= PPCII::MO_NLP_FLAG;
1324 LoOpFlags |= PPCII::MO_NLP_FLAG;
1326 if (GV->hasHiddenVisibility()) {
1327 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1328 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1335 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1336 SelectionDAG &DAG) {
1337 EVT PtrVT = HiPart.getValueType();
1338 SDValue Zero = DAG.getConstant(0, PtrVT);
1341 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1342 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1344 // With PIC, the first instruction is actually "GR+hi(&G)".
1346 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1347 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1349 // Generate non-pic code that has direct accesses to the constant pool.
1350 // The address of the global is just (hi(&g)+lo(&g)).
1351 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1354 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1355 SelectionDAG &DAG) const {
1356 EVT PtrVT = Op.getValueType();
1357 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1358 const Constant *C = CP->getConstVal();
1360 // 64-bit SVR4 ABI code is always position-independent.
1361 // The actual address of the GlobalValue is stored in the TOC.
1362 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1363 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1364 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1365 DAG.getRegister(PPC::X2, MVT::i64));
1368 unsigned MOHiFlag, MOLoFlag;
1369 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1371 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1373 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1374 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1377 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1378 EVT PtrVT = Op.getValueType();
1379 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1381 // 64-bit SVR4 ABI code is always position-independent.
1382 // The actual address of the GlobalValue is stored in the TOC.
1383 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1384 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1385 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1386 DAG.getRegister(PPC::X2, MVT::i64));
1389 unsigned MOHiFlag, MOLoFlag;
1390 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1391 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1392 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1393 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1396 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1397 SelectionDAG &DAG) const {
1398 EVT PtrVT = Op.getValueType();
1400 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1402 unsigned MOHiFlag, MOLoFlag;
1403 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1404 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1405 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1406 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1409 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1410 SelectionDAG &DAG) const {
1412 // FIXME: TLS addresses currently use medium model code sequences,
1413 // which is the most useful form. Eventually support for small and
1414 // large models could be added if users need it, at the cost of
1415 // additional complexity.
1416 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1418 const GlobalValue *GV = GA->getGlobal();
1419 EVT PtrVT = getPointerTy();
1420 bool is64bit = PPCSubTarget.isPPC64();
1422 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1424 if (Model == TLSModel::LocalExec) {
1425 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1426 PPCII::MO_TPREL_HA);
1427 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1428 PPCII::MO_TPREL_LO);
1429 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1430 is64bit ? MVT::i64 : MVT::i32);
1431 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1432 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1435 if (Model == TLSModel::InitialExec) {
1436 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1437 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1441 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1442 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1443 PtrVT, GOTReg, TGA);
1445 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
1446 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1447 PtrVT, TGA, GOTPtr);
1448 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
1451 if (Model == TLSModel::GeneralDynamic) {
1452 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1453 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1454 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1456 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1459 // We need a chain node, and don't have one handy. The underlying
1460 // call has no side effects, so using the function entry node
1462 SDValue Chain = DAG.getEntryNode();
1463 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1464 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1465 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl,
1466 PtrVT, ParmReg, TGA);
1467 // The return value from GET_TLS_ADDR really is in X3 already, but
1468 // some hacks are needed here to tie everything together. The extra
1469 // copies dissolve during subsequent transforms.
1470 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1471 return DAG.getCopyFromReg(Chain, dl, PPC::X3, PtrVT);
1474 if (Model == TLSModel::LocalDynamic) {
1475 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1476 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1477 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1479 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1482 // We need a chain node, and don't have one handy. The underlying
1483 // call has no side effects, so using the function entry node
1485 SDValue Chain = DAG.getEntryNode();
1486 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1487 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1488 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl,
1489 PtrVT, ParmReg, TGA);
1490 // The return value from GET_TLSLD_ADDR really is in X3 already, but
1491 // some hacks are needed here to tie everything together. The extra
1492 // copies dissolve during subsequent transforms.
1493 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1494 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1495 Chain, ParmReg, TGA);
1496 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1499 llvm_unreachable("Unknown TLS model!");
1502 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1503 SelectionDAG &DAG) const {
1504 EVT PtrVT = Op.getValueType();
1505 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1507 const GlobalValue *GV = GSDN->getGlobal();
1509 // 64-bit SVR4 ABI code is always position-independent.
1510 // The actual address of the GlobalValue is stored in the TOC.
1511 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1512 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1513 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1514 DAG.getRegister(PPC::X2, MVT::i64));
1517 unsigned MOHiFlag, MOLoFlag;
1518 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1521 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1523 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1525 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1527 // If the global reference is actually to a non-lazy-pointer, we have to do an
1528 // extra load to get the address of the global.
1529 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1530 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1531 false, false, false, 0);
1535 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1536 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1539 // If we're comparing for equality to zero, expose the fact that this is
1540 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1541 // fold the new nodes.
1542 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1543 if (C->isNullValue() && CC == ISD::SETEQ) {
1544 EVT VT = Op.getOperand(0).getValueType();
1545 SDValue Zext = Op.getOperand(0);
1546 if (VT.bitsLT(MVT::i32)) {
1548 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1550 unsigned Log2b = Log2_32(VT.getSizeInBits());
1551 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1552 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1553 DAG.getConstant(Log2b, MVT::i32));
1554 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1556 // Leave comparisons against 0 and -1 alone for now, since they're usually
1557 // optimized. FIXME: revisit this when we can custom lower all setcc
1559 if (C->isAllOnesValue() || C->isNullValue())
1563 // If we have an integer seteq/setne, turn it into a compare against zero
1564 // by xor'ing the rhs with the lhs, which is faster than setting a
1565 // condition register, reading it back out, and masking the correct bit. The
1566 // normal approach here uses sub to do this instead of xor. Using xor exposes
1567 // the result to other bit-twiddling opportunities.
1568 EVT LHSVT = Op.getOperand(0).getValueType();
1569 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1570 EVT VT = Op.getValueType();
1571 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1573 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1578 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1579 const PPCSubtarget &Subtarget) const {
1580 SDNode *Node = Op.getNode();
1581 EVT VT = Node->getValueType(0);
1582 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1583 SDValue InChain = Node->getOperand(0);
1584 SDValue VAListPtr = Node->getOperand(1);
1585 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1588 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1591 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1592 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1594 InChain = GprIndex.getValue(1);
1596 if (VT == MVT::i64) {
1597 // Check if GprIndex is even
1598 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1599 DAG.getConstant(1, MVT::i32));
1600 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1601 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1602 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1603 DAG.getConstant(1, MVT::i32));
1604 // Align GprIndex to be even if it isn't
1605 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1609 // fpr index is 1 byte after gpr
1610 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1611 DAG.getConstant(1, MVT::i32));
1614 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1615 FprPtr, MachinePointerInfo(SV), MVT::i8,
1617 InChain = FprIndex.getValue(1);
1619 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1620 DAG.getConstant(8, MVT::i32));
1622 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1623 DAG.getConstant(4, MVT::i32));
1626 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1627 MachinePointerInfo(), false, false,
1629 InChain = OverflowArea.getValue(1);
1631 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1632 MachinePointerInfo(), false, false,
1634 InChain = RegSaveArea.getValue(1);
1636 // select overflow_area if index > 8
1637 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1638 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1640 // adjustment constant gpr_index * 4/8
1641 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1642 VT.isInteger() ? GprIndex : FprIndex,
1643 DAG.getConstant(VT.isInteger() ? 4 : 8,
1646 // OurReg = RegSaveArea + RegConstant
1647 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1650 // Floating types are 32 bytes into RegSaveArea
1651 if (VT.isFloatingPoint())
1652 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1653 DAG.getConstant(32, MVT::i32));
1655 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1656 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1657 VT.isInteger() ? GprIndex : FprIndex,
1658 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1661 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1662 VT.isInteger() ? VAListPtr : FprPtr,
1663 MachinePointerInfo(SV),
1664 MVT::i8, false, false, 0);
1666 // determine if we should load from reg_save_area or overflow_area
1667 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1669 // increase overflow_area by 4/8 if gpr/fpr > 8
1670 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1671 DAG.getConstant(VT.isInteger() ? 4 : 8,
1674 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1677 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1679 MachinePointerInfo(),
1680 MVT::i32, false, false, 0);
1682 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1683 false, false, false, 0);
1686 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
1687 const PPCSubtarget &Subtarget) const {
1688 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
1690 // We have to copy the entire va_list struct:
1691 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
1692 return DAG.getMemcpy(Op.getOperand(0), Op,
1693 Op.getOperand(1), Op.getOperand(2),
1694 DAG.getConstant(12, MVT::i32), 8, false, true,
1695 MachinePointerInfo(), MachinePointerInfo());
1698 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
1699 SelectionDAG &DAG) const {
1700 return Op.getOperand(0);
1703 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
1704 SelectionDAG &DAG) const {
1705 SDValue Chain = Op.getOperand(0);
1706 SDValue Trmp = Op.getOperand(1); // trampoline
1707 SDValue FPtr = Op.getOperand(2); // nested function
1708 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1711 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1712 bool isPPC64 = (PtrVT == MVT::i64);
1714 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
1717 TargetLowering::ArgListTy Args;
1718 TargetLowering::ArgListEntry Entry;
1720 Entry.Ty = IntPtrTy;
1721 Entry.Node = Trmp; Args.push_back(Entry);
1723 // TrampSize == (isPPC64 ? 48 : 40);
1724 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1725 isPPC64 ? MVT::i64 : MVT::i32);
1726 Args.push_back(Entry);
1728 Entry.Node = FPtr; Args.push_back(Entry);
1729 Entry.Node = Nest; Args.push_back(Entry);
1731 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1732 TargetLowering::CallLoweringInfo CLI(Chain,
1733 Type::getVoidTy(*DAG.getContext()),
1734 false, false, false, false, 0,
1736 /*isTailCall=*/false,
1737 /*doesNotRet=*/false,
1738 /*isReturnValueUsed=*/true,
1739 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1741 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1743 return CallResult.second;
1746 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1747 const PPCSubtarget &Subtarget) const {
1748 MachineFunction &MF = DAG.getMachineFunction();
1749 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1753 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
1754 // vastart just stores the address of the VarArgsFrameIndex slot into the
1755 // memory location argument.
1756 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1757 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1758 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1759 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
1760 MachinePointerInfo(SV),
1764 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
1765 // We suppose the given va_list is already allocated.
1768 // char gpr; /* index into the array of 8 GPRs
1769 // * stored in the register save area
1770 // * gpr=0 corresponds to r3,
1771 // * gpr=1 to r4, etc.
1773 // char fpr; /* index into the array of 8 FPRs
1774 // * stored in the register save area
1775 // * fpr=0 corresponds to f1,
1776 // * fpr=1 to f2, etc.
1778 // char *overflow_arg_area;
1779 // /* location on stack that holds
1780 // * the next overflow argument
1782 // char *reg_save_area;
1783 // /* where r3:r10 and f1:f8 (if saved)
1789 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
1790 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
1793 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1795 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
1797 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1800 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
1801 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1803 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
1804 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1806 uint64_t FPROffset = 1;
1807 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1809 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1811 // Store first byte : number of int regs
1812 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
1814 MachinePointerInfo(SV),
1815 MVT::i8, false, false, 0);
1816 uint64_t nextOffset = FPROffset;
1817 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
1820 // Store second byte : number of float regs
1821 SDValue secondStore =
1822 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
1823 MachinePointerInfo(SV, nextOffset), MVT::i8,
1825 nextOffset += StackOffset;
1826 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
1828 // Store second word : arguments given on stack
1829 SDValue thirdStore =
1830 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
1831 MachinePointerInfo(SV, nextOffset),
1833 nextOffset += FrameOffset;
1834 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
1836 // Store third word : arguments given in registers
1837 return DAG.getStore(thirdStore, dl, FR, nextPtr,
1838 MachinePointerInfo(SV, nextOffset),
1843 #include "PPCGenCallingConv.inc"
1845 // Function whose sole purpose is to kill compiler warnings
1846 // stemming from unused functions included from PPCGenCallingConv.inc.
1847 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
1848 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
1851 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
1852 CCValAssign::LocInfo &LocInfo,
1853 ISD::ArgFlagsTy &ArgFlags,
1858 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
1860 CCValAssign::LocInfo &LocInfo,
1861 ISD::ArgFlagsTy &ArgFlags,
1863 static const uint16_t ArgRegs[] = {
1864 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1865 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1867 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1869 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1871 // Skip one register if the first unallocated register has an even register
1872 // number and there are still argument registers available which have not been
1873 // allocated yet. RegNum is actually an index into ArgRegs, which means we
1874 // need to skip a register if RegNum is odd.
1875 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
1876 State.AllocateReg(ArgRegs[RegNum]);
1879 // Always return false here, as this function only makes sure that the first
1880 // unallocated register has an odd register number and does not actually
1881 // allocate a register for the current argument.
1885 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
1887 CCValAssign::LocInfo &LocInfo,
1888 ISD::ArgFlagsTy &ArgFlags,
1890 static const uint16_t ArgRegs[] = {
1891 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1895 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1897 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1899 // If there is only one Floating-point register left we need to put both f64
1900 // values of a split ppc_fp128 value on the stack.
1901 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
1902 State.AllocateReg(ArgRegs[RegNum]);
1905 // Always return false here, as this function only makes sure that the two f64
1906 // values a ppc_fp128 value is split into are both passed in registers or both
1907 // passed on the stack and does not actually allocate a register for the
1908 // current argument.
1912 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1914 static const uint16_t *GetFPR() {
1915 static const uint16_t FPR[] = {
1916 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1917 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1923 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
1925 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
1926 unsigned PtrByteSize) {
1927 unsigned ArgSize = ArgVT.getSizeInBits()/8;
1928 if (Flags.isByVal())
1929 ArgSize = Flags.getByValSize();
1930 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1936 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
1937 CallingConv::ID CallConv, bool isVarArg,
1938 const SmallVectorImpl<ISD::InputArg>
1940 SDLoc dl, SelectionDAG &DAG,
1941 SmallVectorImpl<SDValue> &InVals)
1943 if (PPCSubTarget.isSVR4ABI()) {
1944 if (PPCSubTarget.isPPC64())
1945 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
1948 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
1951 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
1957 PPCTargetLowering::LowerFormalArguments_32SVR4(
1959 CallingConv::ID CallConv, bool isVarArg,
1960 const SmallVectorImpl<ISD::InputArg>
1962 SDLoc dl, SelectionDAG &DAG,
1963 SmallVectorImpl<SDValue> &InVals) const {
1965 // 32-bit SVR4 ABI Stack Frame Layout:
1966 // +-----------------------------------+
1967 // +--> | Back chain |
1968 // | +-----------------------------------+
1969 // | | Floating-point register save area |
1970 // | +-----------------------------------+
1971 // | | General register save area |
1972 // | +-----------------------------------+
1973 // | | CR save word |
1974 // | +-----------------------------------+
1975 // | | VRSAVE save word |
1976 // | +-----------------------------------+
1977 // | | Alignment padding |
1978 // | +-----------------------------------+
1979 // | | Vector register save area |
1980 // | +-----------------------------------+
1981 // | | Local variable space |
1982 // | +-----------------------------------+
1983 // | | Parameter list area |
1984 // | +-----------------------------------+
1985 // | | LR save word |
1986 // | +-----------------------------------+
1987 // SP--> +--- | Back chain |
1988 // +-----------------------------------+
1991 // System V Application Binary Interface PowerPC Processor Supplement
1992 // AltiVec Technology Programming Interface Manual
1994 MachineFunction &MF = DAG.getMachineFunction();
1995 MachineFrameInfo *MFI = MF.getFrameInfo();
1996 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1998 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1999 // Potential tail calls could cause overwriting of argument stack slots.
2000 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2001 (CallConv == CallingConv::Fast));
2002 unsigned PtrByteSize = 4;
2004 // Assign locations to all of the incoming arguments.
2005 SmallVector<CCValAssign, 16> ArgLocs;
2006 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2007 getTargetMachine(), ArgLocs, *DAG.getContext());
2009 // Reserve space for the linkage area on the stack.
2010 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
2012 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2014 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2015 CCValAssign &VA = ArgLocs[i];
2017 // Arguments stored in registers.
2018 if (VA.isRegLoc()) {
2019 const TargetRegisterClass *RC;
2020 EVT ValVT = VA.getValVT();
2022 switch (ValVT.getSimpleVT().SimpleTy) {
2024 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2026 RC = &PPC::GPRCRegClass;
2029 RC = &PPC::F4RCRegClass;
2032 RC = &PPC::F8RCRegClass;
2038 RC = &PPC::VRRCRegClass;
2042 // Transform the arguments stored in physical registers into virtual ones.
2043 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2044 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT);
2046 InVals.push_back(ArgValue);
2048 // Argument stored in memory.
2049 assert(VA.isMemLoc());
2051 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
2052 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2055 // Create load nodes to retrieve arguments from the stack.
2056 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2057 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2058 MachinePointerInfo(),
2059 false, false, false, 0));
2063 // Assign locations to all of the incoming aggregate by value arguments.
2064 // Aggregates passed by value are stored in the local variable space of the
2065 // caller's stack frame, right above the parameter list area.
2066 SmallVector<CCValAssign, 16> ByValArgLocs;
2067 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2068 getTargetMachine(), ByValArgLocs, *DAG.getContext());
2070 // Reserve stack space for the allocations in CCInfo.
2071 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2073 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2075 // Area that is at least reserved in the caller of this function.
2076 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2078 // Set the size that is at least reserved in caller of this function. Tail
2079 // call optimized function's reserved stack space needs to be aligned so that
2080 // taking the difference between two stack areas will result in an aligned
2082 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2085 std::max(MinReservedArea,
2086 PPCFrameLowering::getMinCallFrameSize(false, false));
2088 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
2089 getStackAlignment();
2090 unsigned AlignMask = TargetAlign-1;
2091 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2093 FI->setMinReservedArea(MinReservedArea);
2095 SmallVector<SDValue, 8> MemOps;
2097 // If the function takes variable number of arguments, make a frame index for
2098 // the start of the first vararg value... for expansion of llvm.va_start.
2100 static const uint16_t GPArgRegs[] = {
2101 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2102 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2104 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2106 static const uint16_t FPArgRegs[] = {
2107 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2110 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2112 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2114 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2117 // Make room for NumGPArgRegs and NumFPArgRegs.
2118 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2119 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
2121 FuncInfo->setVarArgsStackOffset(
2122 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2123 CCInfo.getNextStackOffset(), true));
2125 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2126 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2128 // The fixed integer arguments of a variadic function are stored to the
2129 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2130 // the result of va_next.
2131 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2132 // Get an existing live-in vreg, or add a new one.
2133 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2135 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2137 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2138 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2139 MachinePointerInfo(), false, false, 0);
2140 MemOps.push_back(Store);
2141 // Increment the address by four for the next argument to store
2142 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2143 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2146 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2148 // The double arguments are stored to the VarArgsFrameIndex
2150 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2151 // Get an existing live-in vreg, or add a new one.
2152 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2154 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2156 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2157 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2158 MachinePointerInfo(), false, false, 0);
2159 MemOps.push_back(Store);
2160 // Increment the address by eight for the next argument to store
2161 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
2163 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2167 if (!MemOps.empty())
2168 Chain = DAG.getNode(ISD::TokenFactor, dl,
2169 MVT::Other, &MemOps[0], MemOps.size());
2174 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2175 // value to MVT::i64 and then truncate to the correct register size.
2177 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2178 SelectionDAG &DAG, SDValue ArgVal,
2181 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2182 DAG.getValueType(ObjectVT));
2183 else if (Flags.isZExt())
2184 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2185 DAG.getValueType(ObjectVT));
2187 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2190 // Set the size that is at least reserved in caller of this function. Tail
2191 // call optimized functions' reserved stack space needs to be aligned so that
2192 // taking the difference between two stack areas will result in an aligned
2195 PPCTargetLowering::setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG,
2196 unsigned nAltivecParamsAtEnd,
2197 unsigned MinReservedArea,
2198 bool isPPC64) const {
2199 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2200 // Add the Altivec parameters at the end, if needed.
2201 if (nAltivecParamsAtEnd) {
2202 MinReservedArea = ((MinReservedArea+15)/16)*16;
2203 MinReservedArea += 16*nAltivecParamsAtEnd;
2206 std::max(MinReservedArea,
2207 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2208 unsigned TargetAlign
2209 = DAG.getMachineFunction().getTarget().getFrameLowering()->
2210 getStackAlignment();
2211 unsigned AlignMask = TargetAlign-1;
2212 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2213 FI->setMinReservedArea(MinReservedArea);
2217 PPCTargetLowering::LowerFormalArguments_64SVR4(
2219 CallingConv::ID CallConv, bool isVarArg,
2220 const SmallVectorImpl<ISD::InputArg>
2222 SDLoc dl, SelectionDAG &DAG,
2223 SmallVectorImpl<SDValue> &InVals) const {
2224 // TODO: add description of PPC stack frame format, or at least some docs.
2226 MachineFunction &MF = DAG.getMachineFunction();
2227 MachineFrameInfo *MFI = MF.getFrameInfo();
2228 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2230 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2231 // Potential tail calls could cause overwriting of argument stack slots.
2232 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2233 (CallConv == CallingConv::Fast));
2234 unsigned PtrByteSize = 8;
2236 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
2237 // Area that is at least reserved in caller of this function.
2238 unsigned MinReservedArea = ArgOffset;
2240 static const uint16_t GPR[] = {
2241 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2242 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2245 static const uint16_t *FPR = GetFPR();
2247 static const uint16_t VR[] = {
2248 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2249 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2252 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2253 const unsigned Num_FPR_Regs = 13;
2254 const unsigned Num_VR_Regs = array_lengthof(VR);
2256 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2258 // Add DAG nodes to load the arguments or copy them out of registers. On
2259 // entry to a function on PPC, the arguments start after the linkage area,
2260 // although the first ones are often in registers.
2262 SmallVector<SDValue, 8> MemOps;
2263 unsigned nAltivecParamsAtEnd = 0;
2264 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2265 unsigned CurArgIdx = 0;
2266 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2268 bool needsLoad = false;
2269 EVT ObjectVT = Ins[ArgNo].VT;
2270 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2271 unsigned ArgSize = ObjSize;
2272 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2273 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2274 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2276 unsigned CurArgOffset = ArgOffset;
2278 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2279 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2280 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2282 MinReservedArea = ((MinReservedArea+15)/16)*16;
2283 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2287 nAltivecParamsAtEnd++;
2289 // Calculate min reserved area.
2290 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2294 // FIXME the codegen can be much improved in some cases.
2295 // We do not have to keep everything in memory.
2296 if (Flags.isByVal()) {
2297 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2298 ObjSize = Flags.getByValSize();
2299 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2300 // Empty aggregate parameters do not take up registers. Examples:
2304 // etc. However, we have to provide a place-holder in InVals, so
2305 // pretend we have an 8-byte item at the current address for that
2308 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2309 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2310 InVals.push_back(FIN);
2314 unsigned BVAlign = Flags.getByValAlign();
2316 ArgOffset = ((ArgOffset+BVAlign-1)/BVAlign)*BVAlign;
2317 CurArgOffset = ArgOffset;
2320 // All aggregates smaller than 8 bytes must be passed right-justified.
2321 if (ObjSize < PtrByteSize)
2322 CurArgOffset = CurArgOffset + (PtrByteSize - ObjSize);
2323 // The value of the object is its address.
2324 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2325 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2326 InVals.push_back(FIN);
2329 if (GPR_idx != Num_GPR_Regs) {
2330 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2331 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2334 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2335 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2336 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2337 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2338 MachinePointerInfo(FuncArg),
2339 ObjType, false, false, 0);
2341 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2342 // store the whole register as-is to the parameter save area
2343 // slot. The address of the parameter was already calculated
2344 // above (InVals.push_back(FIN)) to be the right-justified
2345 // offset within the slot. For this store, we need a new
2346 // frame index that points at the beginning of the slot.
2347 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2348 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2349 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2350 MachinePointerInfo(FuncArg),
2354 MemOps.push_back(Store);
2357 // Whether we copied from a register or not, advance the offset
2358 // into the parameter save area by a full doubleword.
2359 ArgOffset += PtrByteSize;
2363 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2364 // Store whatever pieces of the object are in registers
2365 // to memory. ArgOffset will be the address of the beginning
2367 if (GPR_idx != Num_GPR_Regs) {
2369 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2370 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2371 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2372 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2373 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2374 MachinePointerInfo(FuncArg, j),
2376 MemOps.push_back(Store);
2378 ArgOffset += PtrByteSize;
2380 ArgOffset += ArgSize - j;
2387 switch (ObjectVT.getSimpleVT().SimpleTy) {
2388 default: llvm_unreachable("Unhandled argument type!");
2391 if (GPR_idx != Num_GPR_Regs) {
2392 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2393 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2395 if (ObjectVT == MVT::i32)
2396 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2397 // value to MVT::i64 and then truncate to the correct register size.
2398 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2403 ArgSize = PtrByteSize;
2410 // Every 8 bytes of argument space consumes one of the GPRs available for
2411 // argument passing.
2412 if (GPR_idx != Num_GPR_Regs) {
2415 if (FPR_idx != Num_FPR_Regs) {
2418 if (ObjectVT == MVT::f32)
2419 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2421 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2423 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2427 ArgSize = PtrByteSize;
2436 // Note that vector arguments in registers don't reserve stack space,
2437 // except in varargs functions.
2438 if (VR_idx != Num_VR_Regs) {
2439 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2440 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2442 while ((ArgOffset % 16) != 0) {
2443 ArgOffset += PtrByteSize;
2444 if (GPR_idx != Num_GPR_Regs)
2448 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2452 // Vectors are aligned.
2453 ArgOffset = ((ArgOffset+15)/16)*16;
2454 CurArgOffset = ArgOffset;
2461 // We need to load the argument to a virtual register if we determined
2462 // above that we ran out of physical registers of the appropriate type.
2464 int FI = MFI->CreateFixedObject(ObjSize,
2465 CurArgOffset + (ArgSize - ObjSize),
2467 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2468 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2469 false, false, false, 0);
2472 InVals.push_back(ArgVal);
2475 // Set the size that is at least reserved in caller of this function. Tail
2476 // call optimized functions' reserved stack space needs to be aligned so that
2477 // taking the difference between two stack areas will result in an aligned
2479 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, true);
2481 // If the function takes variable number of arguments, make a frame index for
2482 // the start of the first vararg value... for expansion of llvm.va_start.
2484 int Depth = ArgOffset;
2486 FuncInfo->setVarArgsFrameIndex(
2487 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2488 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2490 // If this function is vararg, store any remaining integer argument regs
2491 // to their spots on the stack so that they may be loaded by deferencing the
2492 // result of va_next.
2493 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2494 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2495 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2496 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2497 MachinePointerInfo(), false, false, 0);
2498 MemOps.push_back(Store);
2499 // Increment the address by four for the next argument to store
2500 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2501 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2505 if (!MemOps.empty())
2506 Chain = DAG.getNode(ISD::TokenFactor, dl,
2507 MVT::Other, &MemOps[0], MemOps.size());
2513 PPCTargetLowering::LowerFormalArguments_Darwin(
2515 CallingConv::ID CallConv, bool isVarArg,
2516 const SmallVectorImpl<ISD::InputArg>
2518 SDLoc dl, SelectionDAG &DAG,
2519 SmallVectorImpl<SDValue> &InVals) const {
2520 // TODO: add description of PPC stack frame format, or at least some docs.
2522 MachineFunction &MF = DAG.getMachineFunction();
2523 MachineFrameInfo *MFI = MF.getFrameInfo();
2524 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2526 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2527 bool isPPC64 = PtrVT == MVT::i64;
2528 // Potential tail calls could cause overwriting of argument stack slots.
2529 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2530 (CallConv == CallingConv::Fast));
2531 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2533 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
2534 // Area that is at least reserved in caller of this function.
2535 unsigned MinReservedArea = ArgOffset;
2537 static const uint16_t GPR_32[] = { // 32-bit registers.
2538 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2539 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2541 static const uint16_t GPR_64[] = { // 64-bit registers.
2542 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2543 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2546 static const uint16_t *FPR = GetFPR();
2548 static const uint16_t VR[] = {
2549 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2550 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2553 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2554 const unsigned Num_FPR_Regs = 13;
2555 const unsigned Num_VR_Regs = array_lengthof( VR);
2557 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2559 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
2561 // In 32-bit non-varargs functions, the stack space for vectors is after the
2562 // stack space for non-vectors. We do not use this space unless we have
2563 // too many vectors to fit in registers, something that only occurs in
2564 // constructed examples:), but we have to walk the arglist to figure
2565 // that out...for the pathological case, compute VecArgOffset as the
2566 // start of the vector parameter area. Computing VecArgOffset is the
2567 // entire point of the following loop.
2568 unsigned VecArgOffset = ArgOffset;
2569 if (!isVarArg && !isPPC64) {
2570 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
2572 EVT ObjectVT = Ins[ArgNo].VT;
2573 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2575 if (Flags.isByVal()) {
2576 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
2577 unsigned ObjSize = Flags.getByValSize();
2579 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2580 VecArgOffset += ArgSize;
2584 switch(ObjectVT.getSimpleVT().SimpleTy) {
2585 default: llvm_unreachable("Unhandled argument type!");
2590 case MVT::i64: // PPC64
2592 // FIXME: We are guaranteed to be !isPPC64 at this point.
2593 // Does MVT::i64 apply?
2600 // Nothing to do, we're only looking at Nonvector args here.
2605 // We've found where the vector parameter area in memory is. Skip the
2606 // first 12 parameters; these don't use that memory.
2607 VecArgOffset = ((VecArgOffset+15)/16)*16;
2608 VecArgOffset += 12*16;
2610 // Add DAG nodes to load the arguments or copy them out of registers. On
2611 // entry to a function on PPC, the arguments start after the linkage area,
2612 // although the first ones are often in registers.
2614 SmallVector<SDValue, 8> MemOps;
2615 unsigned nAltivecParamsAtEnd = 0;
2616 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2617 unsigned CurArgIdx = 0;
2618 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2620 bool needsLoad = false;
2621 EVT ObjectVT = Ins[ArgNo].VT;
2622 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2623 unsigned ArgSize = ObjSize;
2624 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2625 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2626 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2628 unsigned CurArgOffset = ArgOffset;
2630 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2631 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2632 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2633 if (isVarArg || isPPC64) {
2634 MinReservedArea = ((MinReservedArea+15)/16)*16;
2635 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2638 } else nAltivecParamsAtEnd++;
2640 // Calculate min reserved area.
2641 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2645 // FIXME the codegen can be much improved in some cases.
2646 // We do not have to keep everything in memory.
2647 if (Flags.isByVal()) {
2648 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2649 ObjSize = Flags.getByValSize();
2650 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2651 // Objects of size 1 and 2 are right justified, everything else is
2652 // left justified. This means the memory address is adjusted forwards.
2653 if (ObjSize==1 || ObjSize==2) {
2654 CurArgOffset = CurArgOffset + (4 - ObjSize);
2656 // The value of the object is its address.
2657 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2658 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2659 InVals.push_back(FIN);
2660 if (ObjSize==1 || ObjSize==2) {
2661 if (GPR_idx != Num_GPR_Regs) {
2664 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2666 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2667 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2668 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
2669 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2670 MachinePointerInfo(FuncArg),
2671 ObjType, false, false, 0);
2672 MemOps.push_back(Store);
2676 ArgOffset += PtrByteSize;
2680 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2681 // Store whatever pieces of the object are in registers
2682 // to memory. ArgOffset will be the address of the beginning
2684 if (GPR_idx != Num_GPR_Regs) {
2687 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2689 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2690 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2691 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2692 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2693 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2694 MachinePointerInfo(FuncArg, j),
2696 MemOps.push_back(Store);
2698 ArgOffset += PtrByteSize;
2700 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
2707 switch (ObjectVT.getSimpleVT().SimpleTy) {
2708 default: llvm_unreachable("Unhandled argument type!");
2711 if (GPR_idx != Num_GPR_Regs) {
2712 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2713 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2717 ArgSize = PtrByteSize;
2719 // All int arguments reserve stack space in the Darwin ABI.
2720 ArgOffset += PtrByteSize;
2724 case MVT::i64: // PPC64
2725 if (GPR_idx != Num_GPR_Regs) {
2726 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2727 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2729 if (ObjectVT == MVT::i32)
2730 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2731 // value to MVT::i64 and then truncate to the correct register size.
2732 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2737 ArgSize = PtrByteSize;
2739 // All int arguments reserve stack space in the Darwin ABI.
2745 // Every 4 bytes of argument space consumes one of the GPRs available for
2746 // argument passing.
2747 if (GPR_idx != Num_GPR_Regs) {
2749 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
2752 if (FPR_idx != Num_FPR_Regs) {
2755 if (ObjectVT == MVT::f32)
2756 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2758 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2760 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2766 // All FP arguments reserve stack space in the Darwin ABI.
2767 ArgOffset += isPPC64 ? 8 : ObjSize;
2773 // Note that vector arguments in registers don't reserve stack space,
2774 // except in varargs functions.
2775 if (VR_idx != Num_VR_Regs) {
2776 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2777 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2779 while ((ArgOffset % 16) != 0) {
2780 ArgOffset += PtrByteSize;
2781 if (GPR_idx != Num_GPR_Regs)
2785 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2789 if (!isVarArg && !isPPC64) {
2790 // Vectors go after all the nonvectors.
2791 CurArgOffset = VecArgOffset;
2794 // Vectors are aligned.
2795 ArgOffset = ((ArgOffset+15)/16)*16;
2796 CurArgOffset = ArgOffset;
2804 // We need to load the argument to a virtual register if we determined above
2805 // that we ran out of physical registers of the appropriate type.
2807 int FI = MFI->CreateFixedObject(ObjSize,
2808 CurArgOffset + (ArgSize - ObjSize),
2810 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2811 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2812 false, false, false, 0);
2815 InVals.push_back(ArgVal);
2818 // Set the size that is at least reserved in caller of this function. Tail
2819 // call optimized functions' reserved stack space needs to be aligned so that
2820 // taking the difference between two stack areas will result in an aligned
2822 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, isPPC64);
2824 // If the function takes variable number of arguments, make a frame index for
2825 // the start of the first vararg value... for expansion of llvm.va_start.
2827 int Depth = ArgOffset;
2829 FuncInfo->setVarArgsFrameIndex(
2830 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2832 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2834 // If this function is vararg, store any remaining integer argument regs
2835 // to their spots on the stack so that they may be loaded by deferencing the
2836 // result of va_next.
2837 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2841 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2843 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2845 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2846 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2847 MachinePointerInfo(), false, false, 0);
2848 MemOps.push_back(Store);
2849 // Increment the address by four for the next argument to store
2850 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2851 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2855 if (!MemOps.empty())
2856 Chain = DAG.getNode(ISD::TokenFactor, dl,
2857 MVT::Other, &MemOps[0], MemOps.size());
2862 /// CalculateParameterAndLinkageAreaSize - Get the size of the parameter plus
2863 /// linkage area for the Darwin ABI, or the 64-bit SVR4 ABI.
2865 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
2869 const SmallVectorImpl<ISD::OutputArg>
2871 const SmallVectorImpl<SDValue> &OutVals,
2872 unsigned &nAltivecParamsAtEnd) {
2873 // Count how many bytes are to be pushed on the stack, including the linkage
2874 // area, and parameter passing area. We start with 24/48 bytes, which is
2875 // prereserved space for [SP][CR][LR][3 x unused].
2876 unsigned NumBytes = PPCFrameLowering::getLinkageSize(isPPC64, true);
2877 unsigned NumOps = Outs.size();
2878 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2880 // Add up all the space actually used.
2881 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
2882 // they all go in registers, but we must reserve stack space for them for
2883 // possible use by the caller. In varargs or 64-bit calls, parameters are
2884 // assigned stack space in order, with padding so Altivec parameters are
2886 nAltivecParamsAtEnd = 0;
2887 for (unsigned i = 0; i != NumOps; ++i) {
2888 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2889 EVT ArgVT = Outs[i].VT;
2890 // Varargs Altivec parameters are padded to a 16 byte boundary.
2891 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
2892 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
2893 if (!isVarArg && !isPPC64) {
2894 // Non-varargs Altivec parameters go after all the non-Altivec
2895 // parameters; handle those later so we know how much padding we need.
2896 nAltivecParamsAtEnd++;
2899 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
2900 NumBytes = ((NumBytes+15)/16)*16;
2902 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2905 // Allow for Altivec parameters at the end, if needed.
2906 if (nAltivecParamsAtEnd) {
2907 NumBytes = ((NumBytes+15)/16)*16;
2908 NumBytes += 16*nAltivecParamsAtEnd;
2911 // The prolog code of the callee may store up to 8 GPR argument registers to
2912 // the stack, allowing va_start to index over them in memory if its varargs.
2913 // Because we cannot tell if this is needed on the caller side, we have to
2914 // conservatively assume that it is needed. As such, make sure we have at
2915 // least enough stack space for the caller to store the 8 GPRs.
2916 NumBytes = std::max(NumBytes,
2917 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2919 // Tail call needs the stack to be aligned.
2920 if (CC == CallingConv::Fast && DAG.getTarget().Options.GuaranteedTailCallOpt){
2921 unsigned TargetAlign = DAG.getMachineFunction().getTarget().
2922 getFrameLowering()->getStackAlignment();
2923 unsigned AlignMask = TargetAlign-1;
2924 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2930 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
2931 /// adjusted to accommodate the arguments for the tailcall.
2932 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
2933 unsigned ParamSize) {
2935 if (!isTailCall) return 0;
2937 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
2938 unsigned CallerMinReservedArea = FI->getMinReservedArea();
2939 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
2940 // Remember only if the new adjustement is bigger.
2941 if (SPDiff < FI->getTailCallSPDelta())
2942 FI->setTailCallSPDelta(SPDiff);
2947 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2948 /// for tail call optimization. Targets which want to do tail call
2949 /// optimization should implement this function.
2951 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2952 CallingConv::ID CalleeCC,
2954 const SmallVectorImpl<ISD::InputArg> &Ins,
2955 SelectionDAG& DAG) const {
2956 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
2959 // Variable argument functions are not supported.
2963 MachineFunction &MF = DAG.getMachineFunction();
2964 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
2965 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
2966 // Functions containing by val parameters are not supported.
2967 for (unsigned i = 0; i != Ins.size(); i++) {
2968 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2969 if (Flags.isByVal()) return false;
2972 // Non-PIC/GOT tail calls are supported.
2973 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
2976 // At the moment we can only do local tail calls (in same module, hidden
2977 // or protected) if we are generating PIC.
2978 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2979 return G->getGlobal()->hasHiddenVisibility()
2980 || G->getGlobal()->hasProtectedVisibility();
2986 /// isCallCompatibleAddress - Return the immediate to use if the specified
2987 /// 32-bit value is representable in the immediate field of a BxA instruction.
2988 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
2989 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2992 int Addr = C->getZExtValue();
2993 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
2994 SignExtend32<26>(Addr) != Addr)
2995 return 0; // Top 6 bits have to be sext of immediate.
2997 return DAG.getConstant((int)C->getZExtValue() >> 2,
2998 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
3003 struct TailCallArgumentInfo {
3008 TailCallArgumentInfo() : FrameIdx(0) {}
3013 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3015 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3017 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3018 SmallVectorImpl<SDValue> &MemOpChains,
3020 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3021 SDValue Arg = TailCallArgs[i].Arg;
3022 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3023 int FI = TailCallArgs[i].FrameIdx;
3024 // Store relative to framepointer.
3025 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
3026 MachinePointerInfo::getFixedStack(FI),
3031 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3032 /// the appropriate stack slot for the tail call optimized function call.
3033 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3034 MachineFunction &MF,
3043 // Calculate the new stack slot for the return address.
3044 int SlotSize = isPPC64 ? 8 : 4;
3045 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
3047 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3048 NewRetAddrLoc, true);
3049 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3050 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3051 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3052 MachinePointerInfo::getFixedStack(NewRetAddr),
3055 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3056 // slot as the FP is never overwritten.
3059 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
3060 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3062 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3063 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3064 MachinePointerInfo::getFixedStack(NewFPIdx),
3071 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3072 /// the position of the argument.
3074 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3075 SDValue Arg, int SPDiff, unsigned ArgOffset,
3076 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3077 int Offset = ArgOffset + SPDiff;
3078 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3079 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3080 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3081 SDValue FIN = DAG.getFrameIndex(FI, VT);
3082 TailCallArgumentInfo Info;
3084 Info.FrameIdxOp = FIN;
3086 TailCallArguments.push_back(Info);
3089 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3090 /// stack slot. Returns the chain as result and the loaded frame pointers in
3091 /// LROpOut/FPOpout. Used when tail calling.
3092 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3100 // Load the LR and FP stack slot for later adjusting.
3101 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
3102 LROpOut = getReturnAddrFrameIndex(DAG);
3103 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3104 false, false, false, 0);
3105 Chain = SDValue(LROpOut.getNode(), 1);
3107 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3108 // slot as the FP is never overwritten.
3110 FPOpOut = getFramePointerFrameIndex(DAG);
3111 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3112 false, false, false, 0);
3113 Chain = SDValue(FPOpOut.getNode(), 1);
3119 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3120 /// by "Src" to address "Dst" of size "Size". Alignment information is
3121 /// specified by the specific parameter attribute. The copy will be passed as
3122 /// a byval function parameter.
3123 /// Sometimes what we are copying is the end of a larger object, the part that
3124 /// does not fit in registers.
3126 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3127 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3129 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3130 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3131 false, false, MachinePointerInfo(0),
3132 MachinePointerInfo(0));
3135 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3138 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3139 SDValue Arg, SDValue PtrOff, int SPDiff,
3140 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3141 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
3142 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
3144 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3149 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3151 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3152 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3153 DAG.getConstant(ArgOffset, PtrVT));
3155 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3156 MachinePointerInfo(), false, false, 0));
3157 // Calculate and remember argument location.
3158 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3163 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3164 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3165 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3166 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
3167 MachineFunction &MF = DAG.getMachineFunction();
3169 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3170 // might overwrite each other in case of tail call optimization.
3171 SmallVector<SDValue, 8> MemOpChains2;
3172 // Do not flag preceding copytoreg stuff together with the following stuff.
3174 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3176 if (!MemOpChains2.empty())
3177 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3178 &MemOpChains2[0], MemOpChains2.size());
3180 // Store the return address to the appropriate stack slot.
3181 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3182 isPPC64, isDarwinABI, dl);
3184 // Emit callseq_end just before tailcall node.
3185 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3186 DAG.getIntPtrConstant(0, true), InFlag, dl);
3187 InFlag = Chain.getValue(1);
3191 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3192 SDValue &Chain, SDLoc dl, int SPDiff, bool isTailCall,
3193 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
3194 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
3195 const PPCSubtarget &PPCSubTarget) {
3197 bool isPPC64 = PPCSubTarget.isPPC64();
3198 bool isSVR4ABI = PPCSubTarget.isSVR4ABI();
3200 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3201 NodeTys.push_back(MVT::Other); // Returns a chain
3202 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3204 unsigned CallOpc = PPCISD::CALL;
3206 bool needIndirectCall = true;
3207 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3208 // If this is an absolute destination address, use the munged value.
3209 Callee = SDValue(Dest, 0);
3210 needIndirectCall = false;
3213 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3214 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201
3215 // Use indirect calls for ALL functions calls in JIT mode, since the
3216 // far-call stubs may be outside relocation limits for a BL instruction.
3217 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
3218 unsigned OpFlags = 0;
3219 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3220 (PPCSubTarget.getTargetTriple().isMacOSX() &&
3221 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3222 (G->getGlobal()->isDeclaration() ||
3223 G->getGlobal()->isWeakForLinker())) {
3224 // PC-relative references to external symbols should go through $stub,
3225 // unless we're building with the leopard linker or later, which
3226 // automatically synthesizes these stubs.
3227 OpFlags = PPCII::MO_DARWIN_STUB;
3230 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3231 // every direct call is) turn it into a TargetGlobalAddress /
3232 // TargetExternalSymbol node so that legalize doesn't hack it.
3233 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3234 Callee.getValueType(),
3236 needIndirectCall = false;
3240 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3241 unsigned char OpFlags = 0;
3243 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3244 (PPCSubTarget.getTargetTriple().isMacOSX() &&
3245 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5))) {
3246 // PC-relative references to external symbols should go through $stub,
3247 // unless we're building with the leopard linker or later, which
3248 // automatically synthesizes these stubs.
3249 OpFlags = PPCII::MO_DARWIN_STUB;
3252 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3254 needIndirectCall = false;
3257 if (needIndirectCall) {
3258 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3259 // to do the call, we can't use PPCISD::CALL.
3260 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3262 if (isSVR4ABI && isPPC64) {
3263 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3264 // entry point, but to the function descriptor (the function entry point
3265 // address is part of the function descriptor though).
3266 // The function descriptor is a three doubleword structure with the
3267 // following fields: function entry point, TOC base address and
3268 // environment pointer.
3269 // Thus for a call through a function pointer, the following actions need
3271 // 1. Save the TOC of the caller in the TOC save area of its stack
3272 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3273 // 2. Load the address of the function entry point from the function
3275 // 3. Load the TOC of the callee from the function descriptor into r2.
3276 // 4. Load the environment pointer from the function descriptor into
3278 // 5. Branch to the function entry point address.
3279 // 6. On return of the callee, the TOC of the caller needs to be
3280 // restored (this is done in FinishCall()).
3282 // All those operations are flagged together to ensure that no other
3283 // operations can be scheduled in between. E.g. without flagging the
3284 // operations together, a TOC access in the caller could be scheduled
3285 // between the load of the callee TOC and the branch to the callee, which
3286 // results in the TOC access going through the TOC of the callee instead
3287 // of going through the TOC of the caller, which leads to incorrect code.
3289 // Load the address of the function entry point from the function
3291 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3292 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps,
3293 InFlag.getNode() ? 3 : 2);
3294 Chain = LoadFuncPtr.getValue(1);
3295 InFlag = LoadFuncPtr.getValue(2);
3297 // Load environment pointer into r11.
3298 // Offset of the environment pointer within the function descriptor.
3299 SDValue PtrOff = DAG.getIntPtrConstant(16);
3301 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3302 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
3304 Chain = LoadEnvPtr.getValue(1);
3305 InFlag = LoadEnvPtr.getValue(2);
3307 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3309 Chain = EnvVal.getValue(0);
3310 InFlag = EnvVal.getValue(1);
3312 // Load TOC of the callee into r2. We are using a target-specific load
3313 // with r2 hard coded, because the result of a target-independent load
3314 // would never go directly into r2, since r2 is a reserved register (which
3315 // prevents the register allocator from allocating it), resulting in an
3316 // additional register being allocated and an unnecessary move instruction
3318 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3319 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
3321 Chain = LoadTOCPtr.getValue(0);
3322 InFlag = LoadTOCPtr.getValue(1);
3324 MTCTROps[0] = Chain;
3325 MTCTROps[1] = LoadFuncPtr;
3326 MTCTROps[2] = InFlag;
3329 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps,
3330 2 + (InFlag.getNode() != 0));
3331 InFlag = Chain.getValue(1);
3334 NodeTys.push_back(MVT::Other);
3335 NodeTys.push_back(MVT::Glue);
3336 Ops.push_back(Chain);
3337 CallOpc = PPCISD::BCTRL;
3339 // Add use of X11 (holding environment pointer)
3340 if (isSVR4ABI && isPPC64)
3341 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3342 // Add CTR register as callee so a bctr can be emitted later.
3344 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3347 // If this is a direct call, pass the chain and the callee.
3348 if (Callee.getNode()) {
3349 Ops.push_back(Chain);
3350 Ops.push_back(Callee);
3352 // If this is a tail call add stack pointer delta.
3354 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3356 // Add argument registers to the end of the list so that they are known live
3358 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3359 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3360 RegsToPass[i].second.getValueType()));
3366 bool isLocalCall(const SDValue &Callee)
3368 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3369 return !G->getGlobal()->isDeclaration() &&
3370 !G->getGlobal()->isWeakForLinker();
3375 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3376 CallingConv::ID CallConv, bool isVarArg,
3377 const SmallVectorImpl<ISD::InputArg> &Ins,
3378 SDLoc dl, SelectionDAG &DAG,
3379 SmallVectorImpl<SDValue> &InVals) const {
3381 SmallVector<CCValAssign, 16> RVLocs;
3382 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3383 getTargetMachine(), RVLocs, *DAG.getContext());
3384 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3386 // Copy all of the result registers out of their specified physreg.
3387 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3388 CCValAssign &VA = RVLocs[i];
3389 assert(VA.isRegLoc() && "Can only return in registers!");
3391 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3392 VA.getLocReg(), VA.getLocVT(), InFlag);
3393 Chain = Val.getValue(1);
3394 InFlag = Val.getValue(2);
3396 switch (VA.getLocInfo()) {
3397 default: llvm_unreachable("Unknown loc info!");
3398 case CCValAssign::Full: break;
3399 case CCValAssign::AExt:
3400 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3402 case CCValAssign::ZExt:
3403 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3404 DAG.getValueType(VA.getValVT()));
3405 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3407 case CCValAssign::SExt:
3408 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3409 DAG.getValueType(VA.getValVT()));
3410 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3414 InVals.push_back(Val);
3421 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
3422 bool isTailCall, bool isVarArg,
3424 SmallVector<std::pair<unsigned, SDValue>, 8>
3426 SDValue InFlag, SDValue Chain,
3428 int SPDiff, unsigned NumBytes,
3429 const SmallVectorImpl<ISD::InputArg> &Ins,
3430 SmallVectorImpl<SDValue> &InVals) const {
3431 std::vector<EVT> NodeTys;
3432 SmallVector<SDValue, 8> Ops;
3433 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
3434 isTailCall, RegsToPass, Ops, NodeTys,
3437 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3438 if (isVarArg && PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64())
3439 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3441 // When performing tail call optimization the callee pops its arguments off
3442 // the stack. Account for this here so these bytes can be pushed back on in
3443 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3444 int BytesCalleePops =
3445 (CallConv == CallingConv::Fast &&
3446 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3448 // Add a register mask operand representing the call-preserved registers.
3449 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
3450 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3451 assert(Mask && "Missing call preserved mask for calling convention");
3452 Ops.push_back(DAG.getRegisterMask(Mask));
3454 if (InFlag.getNode())
3455 Ops.push_back(InFlag);
3459 assert(((Callee.getOpcode() == ISD::Register &&
3460 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3461 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3462 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3463 isa<ConstantSDNode>(Callee)) &&
3464 "Expecting an global address, external symbol, absolute value or register");
3466 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size());
3469 // Add a NOP immediately after the branch instruction when using the 64-bit
3470 // SVR4 ABI. At link time, if caller and callee are in a different module and
3471 // thus have a different TOC, the call will be replaced with a call to a stub
3472 // function which saves the current TOC, loads the TOC of the callee and
3473 // branches to the callee. The NOP will be replaced with a load instruction
3474 // which restores the TOC of the caller from the TOC save slot of the current
3475 // stack frame. If caller and callee belong to the same module (and have the
3476 // same TOC), the NOP will remain unchanged.
3478 bool needsTOCRestore = false;
3479 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) {
3480 if (CallOpc == PPCISD::BCTRL) {
3481 // This is a call through a function pointer.
3482 // Restore the caller TOC from the save area into R2.
3483 // See PrepareCall() for more information about calls through function
3484 // pointers in the 64-bit SVR4 ABI.
3485 // We are using a target-specific load with r2 hard coded, because the
3486 // result of a target-independent load would never go directly into r2,
3487 // since r2 is a reserved register (which prevents the register allocator
3488 // from allocating it), resulting in an additional register being
3489 // allocated and an unnecessary move instruction being generated.
3490 needsTOCRestore = true;
3491 } else if ((CallOpc == PPCISD::CALL) &&
3492 (!isLocalCall(Callee) ||
3493 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3494 // Otherwise insert NOP for non-local calls.
3495 CallOpc = PPCISD::CALL_NOP;
3499 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
3500 InFlag = Chain.getValue(1);
3502 if (needsTOCRestore) {
3503 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3504 Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag);
3505 InFlag = Chain.getValue(1);
3508 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3509 DAG.getIntPtrConstant(BytesCalleePops, true),
3512 InFlag = Chain.getValue(1);
3514 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3515 Ins, dl, DAG, InVals);
3519 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3520 SmallVectorImpl<SDValue> &InVals) const {
3521 SelectionDAG &DAG = CLI.DAG;
3523 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3524 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3525 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3526 SDValue Chain = CLI.Chain;
3527 SDValue Callee = CLI.Callee;
3528 bool &isTailCall = CLI.IsTailCall;
3529 CallingConv::ID CallConv = CLI.CallConv;
3530 bool isVarArg = CLI.IsVarArg;
3533 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3536 if (PPCSubTarget.isSVR4ABI()) {
3537 if (PPCSubTarget.isPPC64())
3538 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3539 isTailCall, Outs, OutVals, Ins,
3542 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3543 isTailCall, Outs, OutVals, Ins,
3547 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
3548 isTailCall, Outs, OutVals, Ins,
3553 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
3554 CallingConv::ID CallConv, bool isVarArg,
3556 const SmallVectorImpl<ISD::OutputArg> &Outs,
3557 const SmallVectorImpl<SDValue> &OutVals,
3558 const SmallVectorImpl<ISD::InputArg> &Ins,
3559 SDLoc dl, SelectionDAG &DAG,
3560 SmallVectorImpl<SDValue> &InVals) const {
3561 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
3562 // of the 32-bit SVR4 ABI stack frame layout.
3564 assert((CallConv == CallingConv::C ||
3565 CallConv == CallingConv::Fast) && "Unknown calling convention!");
3567 unsigned PtrByteSize = 4;
3569 MachineFunction &MF = DAG.getMachineFunction();
3571 // Mark this function as potentially containing a function that contains a
3572 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3573 // and restoring the callers stack pointer in this functions epilog. This is
3574 // done because by tail calling the called function might overwrite the value
3575 // in this function's (MF) stack pointer stack slot 0(SP).
3576 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3577 CallConv == CallingConv::Fast)
3578 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3580 // Count how many bytes are to be pushed on the stack, including the linkage
3581 // area, parameter list area and the part of the local variable space which
3582 // contains copies of aggregates which are passed by value.
3584 // Assign locations to all of the outgoing arguments.
3585 SmallVector<CCValAssign, 16> ArgLocs;
3586 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3587 getTargetMachine(), ArgLocs, *DAG.getContext());
3589 // Reserve space for the linkage area on the stack.
3590 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
3593 // Handle fixed and variable vector arguments differently.
3594 // Fixed vector arguments go into registers as long as registers are
3595 // available. Variable vector arguments always go into memory.
3596 unsigned NumArgs = Outs.size();
3598 for (unsigned i = 0; i != NumArgs; ++i) {
3599 MVT ArgVT = Outs[i].VT;
3600 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3603 if (Outs[i].IsFixed) {
3604 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
3607 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
3613 errs() << "Call operand #" << i << " has unhandled type "
3614 << EVT(ArgVT).getEVTString() << "\n";
3616 llvm_unreachable(0);
3620 // All arguments are treated the same.
3621 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
3624 // Assign locations to all of the outgoing aggregate by value arguments.
3625 SmallVector<CCValAssign, 16> ByValArgLocs;
3626 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3627 getTargetMachine(), ByValArgLocs, *DAG.getContext());
3629 // Reserve stack space for the allocations in CCInfo.
3630 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
3632 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
3634 // Size of the linkage area, parameter list area and the part of the local
3635 // space variable where copies of aggregates which are passed by value are
3637 unsigned NumBytes = CCByValInfo.getNextStackOffset();
3639 // Calculate by how many bytes the stack has to be adjusted in case of tail
3640 // call optimization.
3641 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3643 // Adjust the stack pointer for the new arguments...
3644 // These operations are automatically eliminated by the prolog/epilog pass
3645 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
3647 SDValue CallSeqStart = Chain;
3649 // Load the return address and frame pointer so it can be moved somewhere else
3652 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
3655 // Set up a copy of the stack pointer for use loading and storing any
3656 // arguments that may not fit in the registers available for argument
3658 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3660 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3661 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3662 SmallVector<SDValue, 8> MemOpChains;
3664 bool seenFloatArg = false;
3665 // Walk the register/memloc assignments, inserting copies/loads.
3666 for (unsigned i = 0, j = 0, e = ArgLocs.size();
3669 CCValAssign &VA = ArgLocs[i];
3670 SDValue Arg = OutVals[i];
3671 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3673 if (Flags.isByVal()) {
3674 // Argument is an aggregate which is passed by value, thus we need to
3675 // create a copy of it in the local variable space of the current stack
3676 // frame (which is the stack frame of the caller) and pass the address of
3677 // this copy to the callee.
3678 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
3679 CCValAssign &ByValVA = ByValArgLocs[j++];
3680 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
3682 // Memory reserved in the local variable space of the callers stack frame.
3683 unsigned LocMemOffset = ByValVA.getLocMemOffset();
3685 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3686 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3688 // Create a copy of the argument in the local area of the current
3690 SDValue MemcpyCall =
3691 CreateCopyOfByValArgument(Arg, PtrOff,
3692 CallSeqStart.getNode()->getOperand(0),
3695 // This must go outside the CALLSEQ_START..END.
3696 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3697 CallSeqStart.getNode()->getOperand(1),
3699 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3700 NewCallSeqStart.getNode());
3701 Chain = CallSeqStart = NewCallSeqStart;
3703 // Pass the address of the aggregate copy on the stack either in a
3704 // physical register or in the parameter list area of the current stack
3705 // frame to the callee.
3709 if (VA.isRegLoc()) {
3710 seenFloatArg |= VA.getLocVT().isFloatingPoint();
3711 // Put argument in a physical register.
3712 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3714 // Put argument in the parameter list area of the current stack frame.
3715 assert(VA.isMemLoc());
3716 unsigned LocMemOffset = VA.getLocMemOffset();
3719 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3720 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3722 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3723 MachinePointerInfo(),
3726 // Calculate and remember argument location.
3727 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
3733 if (!MemOpChains.empty())
3734 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3735 &MemOpChains[0], MemOpChains.size());
3737 // Build a sequence of copy-to-reg nodes chained together with token chain
3738 // and flag operands which copy the outgoing args into the appropriate regs.
3740 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3741 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3742 RegsToPass[i].second, InFlag);
3743 InFlag = Chain.getValue(1);
3746 // Set CR bit 6 to true if this is a vararg call with floating args passed in
3749 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3750 SDValue Ops[] = { Chain, InFlag };
3752 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
3753 dl, VTs, Ops, InFlag.getNode() ? 2 : 1);
3755 InFlag = Chain.getValue(1);
3759 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
3760 false, TailCallArguments);
3762 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3763 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3767 // Copy an argument into memory, being careful to do this outside the
3768 // call sequence for the call to which the argument belongs.
3770 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
3771 SDValue CallSeqStart,
3772 ISD::ArgFlagsTy Flags,
3775 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
3776 CallSeqStart.getNode()->getOperand(0),
3778 // The MEMCPY must go outside the CALLSEQ_START..END.
3779 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3780 CallSeqStart.getNode()->getOperand(1),
3782 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3783 NewCallSeqStart.getNode());
3784 return NewCallSeqStart;
3788 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
3789 CallingConv::ID CallConv, bool isVarArg,
3791 const SmallVectorImpl<ISD::OutputArg> &Outs,
3792 const SmallVectorImpl<SDValue> &OutVals,
3793 const SmallVectorImpl<ISD::InputArg> &Ins,
3794 SDLoc dl, SelectionDAG &DAG,
3795 SmallVectorImpl<SDValue> &InVals) const {
3797 unsigned NumOps = Outs.size();
3799 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3800 unsigned PtrByteSize = 8;
3802 MachineFunction &MF = DAG.getMachineFunction();
3804 // Mark this function as potentially containing a function that contains a
3805 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3806 // and restoring the callers stack pointer in this functions epilog. This is
3807 // done because by tail calling the called function might overwrite the value
3808 // in this function's (MF) stack pointer stack slot 0(SP).
3809 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3810 CallConv == CallingConv::Fast)
3811 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3813 unsigned nAltivecParamsAtEnd = 0;
3815 // Count how many bytes are to be pushed on the stack, including the linkage
3816 // area, and parameter passing area. We start with at least 48 bytes, which
3817 // is reserved space for [SP][CR][LR][3 x unused].
3818 // NOTE: For PPC64, nAltivecParamsAtEnd always remains zero as a result
3821 CalculateParameterAndLinkageAreaSize(DAG, true, isVarArg, CallConv,
3822 Outs, OutVals, nAltivecParamsAtEnd);
3824 // Calculate by how many bytes the stack has to be adjusted in case of tail
3825 // call optimization.
3826 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3828 // To protect arguments on the stack from being clobbered in a tail call,
3829 // force all the loads to happen before doing any other lowering.
3831 Chain = DAG.getStackArgumentTokenFactor(Chain);
3833 // Adjust the stack pointer for the new arguments...
3834 // These operations are automatically eliminated by the prolog/epilog pass
3835 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
3837 SDValue CallSeqStart = Chain;
3839 // Load the return address and frame pointer so it can be move somewhere else
3842 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
3845 // Set up a copy of the stack pointer for use loading and storing any
3846 // arguments that may not fit in the registers available for argument
3848 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3850 // Figure out which arguments are going to go in registers, and which in
3851 // memory. Also, if this is a vararg function, floating point operations
3852 // must be stored to our stack, and loaded into integer regs as well, if
3853 // any integer regs are available for argument passing.
3854 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
3855 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3857 static const uint16_t GPR[] = {
3858 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3859 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3861 static const uint16_t *FPR = GetFPR();
3863 static const uint16_t VR[] = {
3864 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3865 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3867 const unsigned NumGPRs = array_lengthof(GPR);
3868 const unsigned NumFPRs = 13;
3869 const unsigned NumVRs = array_lengthof(VR);
3871 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3872 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3874 SmallVector<SDValue, 8> MemOpChains;
3875 for (unsigned i = 0; i != NumOps; ++i) {
3876 SDValue Arg = OutVals[i];
3877 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3879 // PtrOff will be used to store the current argument to the stack if a
3880 // register cannot be found for it.
3883 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
3885 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
3887 // Promote integers to 64-bit values.
3888 if (Arg.getValueType() == MVT::i32) {
3889 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
3890 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3891 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
3894 // FIXME memcpy is used way more than necessary. Correctness first.
3895 // Note: "by value" is code for passing a structure by value, not
3897 if (Flags.isByVal()) {
3898 // Note: Size includes alignment padding, so
3899 // struct x { short a; char b; }
3900 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
3901 // These are the proper values we need for right-justifying the
3902 // aggregate in a parameter register.
3903 unsigned Size = Flags.getByValSize();
3905 // An empty aggregate parameter takes up no storage and no
3910 unsigned BVAlign = Flags.getByValAlign();
3912 if (BVAlign % PtrByteSize != 0)
3914 "ByVal alignment is not a multiple of the pointer size");
3916 ArgOffset = ((ArgOffset+BVAlign-1)/BVAlign)*BVAlign;
3919 // All aggregates smaller than 8 bytes must be passed right-justified.
3920 if (Size==1 || Size==2 || Size==4) {
3921 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
3922 if (GPR_idx != NumGPRs) {
3923 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
3924 MachinePointerInfo(), VT,
3926 MemOpChains.push_back(Load.getValue(1));
3927 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3929 ArgOffset += PtrByteSize;
3934 if (GPR_idx == NumGPRs && Size < 8) {
3935 SDValue Const = DAG.getConstant(PtrByteSize - Size,
3936 PtrOff.getValueType());
3937 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3938 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
3941 ArgOffset += PtrByteSize;
3944 // Copy entire object into memory. There are cases where gcc-generated
3945 // code assumes it is there, even if it could be put entirely into
3946 // registers. (This is not what the doc says.)
3948 // FIXME: The above statement is likely due to a misunderstanding of the
3949 // documents. All arguments must be copied into the parameter area BY
3950 // THE CALLEE in the event that the callee takes the address of any
3951 // formal argument. That has not yet been implemented. However, it is
3952 // reasonable to use the stack area as a staging area for the register
3955 // Skip this for small aggregates, as we will use the same slot for a
3956 // right-justified copy, below.
3958 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
3962 // When a register is available, pass a small aggregate right-justified.
3963 if (Size < 8 && GPR_idx != NumGPRs) {
3964 // The easiest way to get this right-justified in a register
3965 // is to copy the structure into the rightmost portion of a
3966 // local variable slot, then load the whole slot into the
3968 // FIXME: The memcpy seems to produce pretty awful code for
3969 // small aggregates, particularly for packed ones.
3970 // FIXME: It would be preferable to use the slot in the
3971 // parameter save area instead of a new local variable.
3972 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
3973 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3974 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
3978 // Load the slot into the register.
3979 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
3980 MachinePointerInfo(),
3981 false, false, false, 0);
3982 MemOpChains.push_back(Load.getValue(1));
3983 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3985 // Done with this argument.
3986 ArgOffset += PtrByteSize;
3990 // For aggregates larger than PtrByteSize, copy the pieces of the
3991 // object that fit into registers from the parameter save area.
3992 for (unsigned j=0; j<Size; j+=PtrByteSize) {
3993 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
3994 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
3995 if (GPR_idx != NumGPRs) {
3996 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
3997 MachinePointerInfo(),
3998 false, false, false, 0);
3999 MemOpChains.push_back(Load.getValue(1));
4000 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4001 ArgOffset += PtrByteSize;
4003 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4010 switch (Arg.getSimpleValueType().SimpleTy) {
4011 default: llvm_unreachable("Unexpected ValueType for argument!");
4014 if (GPR_idx != NumGPRs) {
4015 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4017 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4018 true, isTailCall, false, MemOpChains,
4019 TailCallArguments, dl);
4021 ArgOffset += PtrByteSize;
4025 if (FPR_idx != NumFPRs) {
4026 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4029 // A single float or an aggregate containing only a single float
4030 // must be passed right-justified in the stack doubleword, and
4031 // in the GPR, if one is available.
4033 if (Arg.getSimpleValueType().SimpleTy == MVT::f32) {
4034 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4035 StoreOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4039 SDValue Store = DAG.getStore(Chain, dl, Arg, StoreOff,
4040 MachinePointerInfo(), false, false, 0);
4041 MemOpChains.push_back(Store);
4043 // Float varargs are always shadowed in available integer registers
4044 if (GPR_idx != NumGPRs) {
4045 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4046 MachinePointerInfo(), false, false,
4048 MemOpChains.push_back(Load.getValue(1));
4049 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4051 } else if (GPR_idx != NumGPRs)
4052 // If we have any FPRs remaining, we may also have GPRs remaining.
4055 // Single-precision floating-point values are mapped to the
4056 // second (rightmost) word of the stack doubleword.
4057 if (Arg.getValueType() == MVT::f32) {
4058 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4059 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4062 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4063 true, isTailCall, false, MemOpChains,
4064 TailCallArguments, dl);
4073 // These go aligned on the stack, or in the corresponding R registers
4074 // when within range. The Darwin PPC ABI doc claims they also go in
4075 // V registers; in fact gcc does this only for arguments that are
4076 // prototyped, not for those that match the ... We do it for all
4077 // arguments, seems to work.
4078 while (ArgOffset % 16 !=0) {
4079 ArgOffset += PtrByteSize;
4080 if (GPR_idx != NumGPRs)
4083 // We could elide this store in the case where the object fits
4084 // entirely in R registers. Maybe later.
4085 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4086 DAG.getConstant(ArgOffset, PtrVT));
4087 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4088 MachinePointerInfo(), false, false, 0);
4089 MemOpChains.push_back(Store);
4090 if (VR_idx != NumVRs) {
4091 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4092 MachinePointerInfo(),
4093 false, false, false, 0);
4094 MemOpChains.push_back(Load.getValue(1));
4095 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4098 for (unsigned i=0; i<16; i+=PtrByteSize) {
4099 if (GPR_idx == NumGPRs)
4101 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4102 DAG.getConstant(i, PtrVT));
4103 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4104 false, false, false, 0);
4105 MemOpChains.push_back(Load.getValue(1));
4106 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4111 // Non-varargs Altivec params generally go in registers, but have
4112 // stack space allocated at the end.
4113 if (VR_idx != NumVRs) {
4114 // Doesn't have GPR space allocated.
4115 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4117 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4118 true, isTailCall, true, MemOpChains,
4119 TailCallArguments, dl);
4126 if (!MemOpChains.empty())
4127 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4128 &MemOpChains[0], MemOpChains.size());
4130 // Check if this is an indirect call (MTCTR/BCTRL).
4131 // See PrepareCall() for more information about calls through function
4132 // pointers in the 64-bit SVR4 ABI.
4134 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4135 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4136 !isBLACompatibleAddress(Callee, DAG)) {
4137 // Load r2 into a virtual register and store it to the TOC save area.
4138 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4139 // TOC save area offset.
4140 SDValue PtrOff = DAG.getIntPtrConstant(40);
4141 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4142 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
4144 // R12 must contain the address of an indirect callee. This does not
4145 // mean the MTCTR instruction must use R12; it's easier to model this
4146 // as an extra parameter, so do that.
4147 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
4150 // Build a sequence of copy-to-reg nodes chained together with token chain
4151 // and flag operands which copy the outgoing args into the appropriate regs.
4153 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4154 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4155 RegsToPass[i].second, InFlag);
4156 InFlag = Chain.getValue(1);
4160 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4161 FPOp, true, TailCallArguments);
4163 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4164 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4169 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4170 CallingConv::ID CallConv, bool isVarArg,
4172 const SmallVectorImpl<ISD::OutputArg> &Outs,
4173 const SmallVectorImpl<SDValue> &OutVals,
4174 const SmallVectorImpl<ISD::InputArg> &Ins,
4175 SDLoc dl, SelectionDAG &DAG,
4176 SmallVectorImpl<SDValue> &InVals) const {
4178 unsigned NumOps = Outs.size();
4180 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4181 bool isPPC64 = PtrVT == MVT::i64;
4182 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4184 MachineFunction &MF = DAG.getMachineFunction();
4186 // Mark this function as potentially containing a function that contains a
4187 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4188 // and restoring the callers stack pointer in this functions epilog. This is
4189 // done because by tail calling the called function might overwrite the value
4190 // in this function's (MF) stack pointer stack slot 0(SP).
4191 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4192 CallConv == CallingConv::Fast)
4193 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4195 unsigned nAltivecParamsAtEnd = 0;
4197 // Count how many bytes are to be pushed on the stack, including the linkage
4198 // area, and parameter passing area. We start with 24/48 bytes, which is
4199 // prereserved space for [SP][CR][LR][3 x unused].
4201 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv,
4203 nAltivecParamsAtEnd);
4205 // Calculate by how many bytes the stack has to be adjusted in case of tail
4206 // call optimization.
4207 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4209 // To protect arguments on the stack from being clobbered in a tail call,
4210 // force all the loads to happen before doing any other lowering.
4212 Chain = DAG.getStackArgumentTokenFactor(Chain);
4214 // Adjust the stack pointer for the new arguments...
4215 // These operations are automatically eliminated by the prolog/epilog pass
4216 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4218 SDValue CallSeqStart = Chain;
4220 // Load the return address and frame pointer so it can be move somewhere else
4223 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4226 // Set up a copy of the stack pointer for use loading and storing any
4227 // arguments that may not fit in the registers available for argument
4231 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4233 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4235 // Figure out which arguments are going to go in registers, and which in
4236 // memory. Also, if this is a vararg function, floating point operations
4237 // must be stored to our stack, and loaded into integer regs as well, if
4238 // any integer regs are available for argument passing.
4239 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
4240 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4242 static const uint16_t GPR_32[] = { // 32-bit registers.
4243 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4244 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4246 static const uint16_t GPR_64[] = { // 64-bit registers.
4247 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4248 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4250 static const uint16_t *FPR = GetFPR();
4252 static const uint16_t VR[] = {
4253 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4254 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4256 const unsigned NumGPRs = array_lengthof(GPR_32);
4257 const unsigned NumFPRs = 13;
4258 const unsigned NumVRs = array_lengthof(VR);
4260 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
4262 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4263 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4265 SmallVector<SDValue, 8> MemOpChains;
4266 for (unsigned i = 0; i != NumOps; ++i) {
4267 SDValue Arg = OutVals[i];
4268 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4270 // PtrOff will be used to store the current argument to the stack if a
4271 // register cannot be found for it.
4274 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4276 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4278 // On PPC64, promote integers to 64-bit values.
4279 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4280 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4281 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4282 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4285 // FIXME memcpy is used way more than necessary. Correctness first.
4286 // Note: "by value" is code for passing a structure by value, not
4288 if (Flags.isByVal()) {
4289 unsigned Size = Flags.getByValSize();
4290 // Very small objects are passed right-justified. Everything else is
4291 // passed left-justified.
4292 if (Size==1 || Size==2) {
4293 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4294 if (GPR_idx != NumGPRs) {
4295 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4296 MachinePointerInfo(), VT,
4298 MemOpChains.push_back(Load.getValue(1));
4299 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4301 ArgOffset += PtrByteSize;
4303 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4304 PtrOff.getValueType());
4305 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4306 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4309 ArgOffset += PtrByteSize;
4313 // Copy entire object into memory. There are cases where gcc-generated
4314 // code assumes it is there, even if it could be put entirely into
4315 // registers. (This is not what the doc says.)
4316 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4320 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4321 // copy the pieces of the object that fit into registers from the
4322 // parameter save area.
4323 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4324 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4325 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4326 if (GPR_idx != NumGPRs) {
4327 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4328 MachinePointerInfo(),
4329 false, false, false, 0);
4330 MemOpChains.push_back(Load.getValue(1));
4331 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4332 ArgOffset += PtrByteSize;
4334 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4341 switch (Arg.getSimpleValueType().SimpleTy) {
4342 default: llvm_unreachable("Unexpected ValueType for argument!");
4345 if (GPR_idx != NumGPRs) {
4346 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4348 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4349 isPPC64, isTailCall, false, MemOpChains,
4350 TailCallArguments, dl);
4352 ArgOffset += PtrByteSize;
4356 if (FPR_idx != NumFPRs) {
4357 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4360 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4361 MachinePointerInfo(), false, false, 0);
4362 MemOpChains.push_back(Store);
4364 // Float varargs are always shadowed in available integer registers
4365 if (GPR_idx != NumGPRs) {
4366 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4367 MachinePointerInfo(), false, false,
4369 MemOpChains.push_back(Load.getValue(1));
4370 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4372 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4373 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4374 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4375 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4376 MachinePointerInfo(),
4377 false, false, false, 0);
4378 MemOpChains.push_back(Load.getValue(1));
4379 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4382 // If we have any FPRs remaining, we may also have GPRs remaining.
4383 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4385 if (GPR_idx != NumGPRs)
4387 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4388 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4392 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4393 isPPC64, isTailCall, false, MemOpChains,
4394 TailCallArguments, dl);
4398 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4405 // These go aligned on the stack, or in the corresponding R registers
4406 // when within range. The Darwin PPC ABI doc claims they also go in
4407 // V registers; in fact gcc does this only for arguments that are
4408 // prototyped, not for those that match the ... We do it for all
4409 // arguments, seems to work.
4410 while (ArgOffset % 16 !=0) {
4411 ArgOffset += PtrByteSize;
4412 if (GPR_idx != NumGPRs)
4415 // We could elide this store in the case where the object fits
4416 // entirely in R registers. Maybe later.
4417 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4418 DAG.getConstant(ArgOffset, PtrVT));
4419 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4420 MachinePointerInfo(), false, false, 0);
4421 MemOpChains.push_back(Store);
4422 if (VR_idx != NumVRs) {
4423 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4424 MachinePointerInfo(),
4425 false, false, false, 0);
4426 MemOpChains.push_back(Load.getValue(1));
4427 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4430 for (unsigned i=0; i<16; i+=PtrByteSize) {
4431 if (GPR_idx == NumGPRs)
4433 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4434 DAG.getConstant(i, PtrVT));
4435 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4436 false, false, false, 0);
4437 MemOpChains.push_back(Load.getValue(1));
4438 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4443 // Non-varargs Altivec params generally go in registers, but have
4444 // stack space allocated at the end.
4445 if (VR_idx != NumVRs) {
4446 // Doesn't have GPR space allocated.
4447 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4448 } else if (nAltivecParamsAtEnd==0) {
4449 // We are emitting Altivec params in order.
4450 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4451 isPPC64, isTailCall, true, MemOpChains,
4452 TailCallArguments, dl);
4458 // If all Altivec parameters fit in registers, as they usually do,
4459 // they get stack space following the non-Altivec parameters. We
4460 // don't track this here because nobody below needs it.
4461 // If there are more Altivec parameters than fit in registers emit
4463 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
4465 // Offset is aligned; skip 1st 12 params which go in V registers.
4466 ArgOffset = ((ArgOffset+15)/16)*16;
4468 for (unsigned i = 0; i != NumOps; ++i) {
4469 SDValue Arg = OutVals[i];
4470 EVT ArgType = Outs[i].VT;
4471 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
4472 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
4475 // We are emitting Altivec params in order.
4476 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4477 isPPC64, isTailCall, true, MemOpChains,
4478 TailCallArguments, dl);
4485 if (!MemOpChains.empty())
4486 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4487 &MemOpChains[0], MemOpChains.size());
4489 // On Darwin, R12 must contain the address of an indirect callee. This does
4490 // not mean the MTCTR instruction must use R12; it's easier to model this as
4491 // an extra parameter, so do that.
4493 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4494 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4495 !isBLACompatibleAddress(Callee, DAG))
4496 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
4497 PPC::R12), Callee));
4499 // Build a sequence of copy-to-reg nodes chained together with token chain
4500 // and flag operands which copy the outgoing args into the appropriate regs.
4502 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4503 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4504 RegsToPass[i].second, InFlag);
4505 InFlag = Chain.getValue(1);
4509 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
4510 FPOp, true, TailCallArguments);
4512 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4513 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4518 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
4519 MachineFunction &MF, bool isVarArg,
4520 const SmallVectorImpl<ISD::OutputArg> &Outs,
4521 LLVMContext &Context) const {
4522 SmallVector<CCValAssign, 16> RVLocs;
4523 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
4525 return CCInfo.CheckReturn(Outs, RetCC_PPC);
4529 PPCTargetLowering::LowerReturn(SDValue Chain,
4530 CallingConv::ID CallConv, bool isVarArg,
4531 const SmallVectorImpl<ISD::OutputArg> &Outs,
4532 const SmallVectorImpl<SDValue> &OutVals,
4533 SDLoc dl, SelectionDAG &DAG) const {
4535 SmallVector<CCValAssign, 16> RVLocs;
4536 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4537 getTargetMachine(), RVLocs, *DAG.getContext());
4538 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
4541 SmallVector<SDValue, 4> RetOps(1, Chain);
4543 // Copy the result values into the output registers.
4544 for (unsigned i = 0; i != RVLocs.size(); ++i) {
4545 CCValAssign &VA = RVLocs[i];
4546 assert(VA.isRegLoc() && "Can only return in registers!");
4548 SDValue Arg = OutVals[i];
4550 switch (VA.getLocInfo()) {
4551 default: llvm_unreachable("Unknown loc info!");
4552 case CCValAssign::Full: break;
4553 case CCValAssign::AExt:
4554 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
4556 case CCValAssign::ZExt:
4557 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
4559 case CCValAssign::SExt:
4560 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
4564 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
4565 Flag = Chain.getValue(1);
4566 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
4569 RetOps[0] = Chain; // Update chain.
4571 // Add the flag if we have it.
4573 RetOps.push_back(Flag);
4575 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other,
4576 &RetOps[0], RetOps.size());
4579 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
4580 const PPCSubtarget &Subtarget) const {
4581 // When we pop the dynamic allocation we need to restore the SP link.
4584 // Get the corect type for pointers.
4585 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4587 // Construct the stack pointer operand.
4588 bool isPPC64 = Subtarget.isPPC64();
4589 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
4590 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
4592 // Get the operands for the STACKRESTORE.
4593 SDValue Chain = Op.getOperand(0);
4594 SDValue SaveSP = Op.getOperand(1);
4596 // Load the old link SP.
4597 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
4598 MachinePointerInfo(),
4599 false, false, false, 0);
4601 // Restore the stack pointer.
4602 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
4604 // Store the old link SP.
4605 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
4612 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
4613 MachineFunction &MF = DAG.getMachineFunction();
4614 bool isPPC64 = PPCSubTarget.isPPC64();
4615 bool isDarwinABI = PPCSubTarget.isDarwinABI();
4616 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4618 // Get current frame pointer save index. The users of this index will be
4619 // primarily DYNALLOC instructions.
4620 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4621 int RASI = FI->getReturnAddrSaveIndex();
4623 // If the frame pointer save index hasn't been defined yet.
4625 // Find out what the fix offset of the frame pointer save area.
4626 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
4627 // Allocate the frame index for frame pointer save area.
4628 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
4630 FI->setReturnAddrSaveIndex(RASI);
4632 return DAG.getFrameIndex(RASI, PtrVT);
4636 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
4637 MachineFunction &MF = DAG.getMachineFunction();
4638 bool isPPC64 = PPCSubTarget.isPPC64();
4639 bool isDarwinABI = PPCSubTarget.isDarwinABI();
4640 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4642 // Get current frame pointer save index. The users of this index will be
4643 // primarily DYNALLOC instructions.
4644 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4645 int FPSI = FI->getFramePointerSaveIndex();
4647 // If the frame pointer save index hasn't been defined yet.
4649 // Find out what the fix offset of the frame pointer save area.
4650 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
4653 // Allocate the frame index for frame pointer save area.
4654 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
4656 FI->setFramePointerSaveIndex(FPSI);
4658 return DAG.getFrameIndex(FPSI, PtrVT);
4661 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
4663 const PPCSubtarget &Subtarget) const {
4665 SDValue Chain = Op.getOperand(0);
4666 SDValue Size = Op.getOperand(1);
4669 // Get the corect type for pointers.
4670 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4672 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
4673 DAG.getConstant(0, PtrVT), Size);
4674 // Construct a node for the frame pointer save index.
4675 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
4676 // Build a DYNALLOC node.
4677 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
4678 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
4679 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3);
4682 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
4683 SelectionDAG &DAG) const {
4685 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
4686 DAG.getVTList(MVT::i32, MVT::Other),
4687 Op.getOperand(0), Op.getOperand(1));
4690 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
4691 SelectionDAG &DAG) const {
4693 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
4694 Op.getOperand(0), Op.getOperand(1));
4697 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
4699 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
4700 // Not FP? Not a fsel.
4701 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
4702 !Op.getOperand(2).getValueType().isFloatingPoint())
4705 // We might be able to do better than this under some circumstances, but in
4706 // general, fsel-based lowering of select is a finite-math-only optimization.
4707 // For more information, see section F.3 of the 2.06 ISA specification.
4708 if (!DAG.getTarget().Options.NoInfsFPMath ||
4709 !DAG.getTarget().Options.NoNaNsFPMath)
4712 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4714 EVT ResVT = Op.getValueType();
4715 EVT CmpVT = Op.getOperand(0).getValueType();
4716 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4717 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
4720 // If the RHS of the comparison is a 0.0, we don't need to do the
4721 // subtraction at all.
4723 if (isFloatingPointZero(RHS))
4725 default: break; // SETUO etc aren't handled by fsel.
4729 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4730 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4731 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
4732 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
4733 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
4734 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4735 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
4738 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
4741 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4742 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4743 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
4746 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
4749 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4750 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4751 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4752 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
4757 default: break; // SETUO etc aren't handled by fsel.
4761 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4762 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4763 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4764 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4765 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
4766 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
4767 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4768 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
4771 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4772 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4773 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4774 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
4777 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4778 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4779 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4780 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4783 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
4784 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4785 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4786 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
4789 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
4790 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4791 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4792 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4797 // FIXME: Split this code up when LegalizeDAGTypes lands.
4798 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
4800 assert(Op.getOperand(0).getValueType().isFloatingPoint());
4801 SDValue Src = Op.getOperand(0);
4802 if (Src.getValueType() == MVT::f32)
4803 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
4806 switch (Op.getSimpleValueType().SimpleTy) {
4807 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
4809 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
4810 (PPCSubTarget.hasFPCVT() ? PPCISD::FCTIWUZ :
4815 assert((Op.getOpcode() == ISD::FP_TO_SINT || PPCSubTarget.hasFPCVT()) &&
4816 "i64 FP_TO_UINT is supported only with FPCVT");
4817 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
4823 // Convert the FP value to an int value through memory.
4824 bool i32Stack = Op.getValueType() == MVT::i32 && PPCSubTarget.hasSTFIWX() &&
4825 (Op.getOpcode() == ISD::FP_TO_SINT || PPCSubTarget.hasFPCVT());
4826 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
4827 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
4828 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
4830 // Emit a store to the stack slot.
4833 MachineFunction &MF = DAG.getMachineFunction();
4834 MachineMemOperand *MMO =
4835 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
4836 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
4837 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
4838 DAG.getVTList(MVT::Other), Ops, array_lengthof(Ops),
4841 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
4842 MPI, false, false, 0);
4844 // Result is a load from the stack slot. If loading 4 bytes, make sure to
4846 if (Op.getValueType() == MVT::i32 && !i32Stack) {
4847 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
4848 DAG.getConstant(4, FIPtr.getValueType()));
4849 MPI = MachinePointerInfo();
4852 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MPI,
4853 false, false, false, 0);
4856 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
4857 SelectionDAG &DAG) const {
4859 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
4860 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
4863 assert((Op.getOpcode() == ISD::SINT_TO_FP || PPCSubTarget.hasFPCVT()) &&
4864 "UINT_TO_FP is supported only with FPCVT");
4866 // If we have FCFIDS, then use it when converting to single-precision.
4867 // Otherwise, convert to double-precision and then round.
4868 unsigned FCFOp = (PPCSubTarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
4869 (Op.getOpcode() == ISD::UINT_TO_FP ?
4870 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
4871 (Op.getOpcode() == ISD::UINT_TO_FP ?
4872 PPCISD::FCFIDU : PPCISD::FCFID);
4873 MVT FCFTy = (PPCSubTarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
4874 MVT::f32 : MVT::f64;
4876 if (Op.getOperand(0).getValueType() == MVT::i64) {
4877 SDValue SINT = Op.getOperand(0);
4878 // When converting to single-precision, we actually need to convert
4879 // to double-precision first and then round to single-precision.
4880 // To avoid double-rounding effects during that operation, we have
4881 // to prepare the input operand. Bits that might be truncated when
4882 // converting to double-precision are replaced by a bit that won't
4883 // be lost at this stage, but is below the single-precision rounding
4886 // However, if -enable-unsafe-fp-math is in effect, accept double
4887 // rounding to avoid the extra overhead.
4888 if (Op.getValueType() == MVT::f32 &&
4889 !PPCSubTarget.hasFPCVT() &&
4890 !DAG.getTarget().Options.UnsafeFPMath) {
4892 // Twiddle input to make sure the low 11 bits are zero. (If this
4893 // is the case, we are guaranteed the value will fit into the 53 bit
4894 // mantissa of an IEEE double-precision value without rounding.)
4895 // If any of those low 11 bits were not zero originally, make sure
4896 // bit 12 (value 2048) is set instead, so that the final rounding
4897 // to single-precision gets the correct result.
4898 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
4899 SINT, DAG.getConstant(2047, MVT::i64));
4900 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
4901 Round, DAG.getConstant(2047, MVT::i64));
4902 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
4903 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
4904 Round, DAG.getConstant(-2048, MVT::i64));
4906 // However, we cannot use that value unconditionally: if the magnitude
4907 // of the input value is small, the bit-twiddling we did above might
4908 // end up visibly changing the output. Fortunately, in that case, we
4909 // don't need to twiddle bits since the original input will convert
4910 // exactly to double-precision floating-point already. Therefore,
4911 // construct a conditional to use the original value if the top 11
4912 // bits are all sign-bit copies, and use the rounded value computed
4914 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
4915 SINT, DAG.getConstant(53, MVT::i32));
4916 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
4917 Cond, DAG.getConstant(1, MVT::i64));
4918 Cond = DAG.getSetCC(dl, MVT::i32,
4919 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
4921 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
4924 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
4925 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
4927 if (Op.getValueType() == MVT::f32 && !PPCSubTarget.hasFPCVT())
4928 FP = DAG.getNode(ISD::FP_ROUND, dl,
4929 MVT::f32, FP, DAG.getIntPtrConstant(0));
4933 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
4934 "Unhandled INT_TO_FP type in custom expander!");
4935 // Since we only generate this in 64-bit mode, we can take advantage of
4936 // 64-bit registers. In particular, sign extend the input value into the
4937 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
4938 // then lfd it and fcfid it.
4939 MachineFunction &MF = DAG.getMachineFunction();
4940 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
4941 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4944 if (PPCSubTarget.hasLFIWAX() || PPCSubTarget.hasFPCVT()) {
4945 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
4946 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4948 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
4949 MachinePointerInfo::getFixedStack(FrameIdx),
4952 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
4953 "Expected an i32 store");
4954 MachineMemOperand *MMO =
4955 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
4956 MachineMemOperand::MOLoad, 4, 4);
4957 SDValue Ops[] = { Store, FIdx };
4958 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
4959 PPCISD::LFIWZX : PPCISD::LFIWAX,
4960 dl, DAG.getVTList(MVT::f64, MVT::Other),
4961 Ops, 2, MVT::i32, MMO);
4963 assert(PPCSubTarget.isPPC64() &&
4964 "i32->FP without LFIWAX supported only on PPC64");
4966 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
4967 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4969 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
4972 // STD the extended value into the stack slot.
4973 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
4974 MachinePointerInfo::getFixedStack(FrameIdx),
4977 // Load the value as a double.
4978 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
4979 MachinePointerInfo::getFixedStack(FrameIdx),
4980 false, false, false, 0);
4983 // FCFID it and return it.
4984 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
4985 if (Op.getValueType() == MVT::f32 && !PPCSubTarget.hasFPCVT())
4986 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
4990 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
4991 SelectionDAG &DAG) const {
4994 The rounding mode is in bits 30:31 of FPSR, and has the following
5001 FLT_ROUNDS, on the other hand, expects the following:
5008 To perform the conversion, we do:
5009 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
5012 MachineFunction &MF = DAG.getMachineFunction();
5013 EVT VT = Op.getValueType();
5014 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5015 SDValue MFFSreg, InFlag;
5017 // Save FP Control Word to register
5019 MVT::f64, // return register
5020 MVT::Glue // unused in this context
5022 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
5024 // Save FP register to stack slot
5025 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5026 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
5027 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
5028 StackSlot, MachinePointerInfo(), false, false,0);
5030 // Load FP Control Word from low 32 bits of stack slot.
5031 SDValue Four = DAG.getConstant(4, PtrVT);
5032 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
5033 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
5034 false, false, false, 0);
5036 // Transform as necessary
5038 DAG.getNode(ISD::AND, dl, MVT::i32,
5039 CWD, DAG.getConstant(3, MVT::i32));
5041 DAG.getNode(ISD::SRL, dl, MVT::i32,
5042 DAG.getNode(ISD::AND, dl, MVT::i32,
5043 DAG.getNode(ISD::XOR, dl, MVT::i32,
5044 CWD, DAG.getConstant(3, MVT::i32)),
5045 DAG.getConstant(3, MVT::i32)),
5046 DAG.getConstant(1, MVT::i32));
5049 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
5051 return DAG.getNode((VT.getSizeInBits() < 16 ?
5052 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
5055 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5056 EVT VT = Op.getValueType();
5057 unsigned BitWidth = VT.getSizeInBits();
5059 assert(Op.getNumOperands() == 3 &&
5060 VT == Op.getOperand(1).getValueType() &&
5063 // Expand into a bunch of logical ops. Note that these ops
5064 // depend on the PPC behavior for oversized shift amounts.
5065 SDValue Lo = Op.getOperand(0);
5066 SDValue Hi = Op.getOperand(1);
5067 SDValue Amt = Op.getOperand(2);
5068 EVT AmtVT = Amt.getValueType();
5070 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5071 DAG.getConstant(BitWidth, AmtVT), Amt);
5072 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
5073 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5074 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5075 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5076 DAG.getConstant(-BitWidth, AmtVT));
5077 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5078 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5079 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
5080 SDValue OutOps[] = { OutLo, OutHi };
5081 return DAG.getMergeValues(OutOps, 2, dl);
5084 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5085 EVT VT = Op.getValueType();
5087 unsigned BitWidth = VT.getSizeInBits();
5088 assert(Op.getNumOperands() == 3 &&
5089 VT == Op.getOperand(1).getValueType() &&
5092 // Expand into a bunch of logical ops. Note that these ops
5093 // depend on the PPC behavior for oversized shift amounts.
5094 SDValue Lo = Op.getOperand(0);
5095 SDValue Hi = Op.getOperand(1);
5096 SDValue Amt = Op.getOperand(2);
5097 EVT AmtVT = Amt.getValueType();
5099 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5100 DAG.getConstant(BitWidth, AmtVT), Amt);
5101 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5102 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5103 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5104 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5105 DAG.getConstant(-BitWidth, AmtVT));
5106 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
5107 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5108 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
5109 SDValue OutOps[] = { OutLo, OutHi };
5110 return DAG.getMergeValues(OutOps, 2, dl);
5113 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
5115 EVT VT = Op.getValueType();
5116 unsigned BitWidth = VT.getSizeInBits();
5117 assert(Op.getNumOperands() == 3 &&
5118 VT == Op.getOperand(1).getValueType() &&
5121 // Expand into a bunch of logical ops, followed by a select_cc.
5122 SDValue Lo = Op.getOperand(0);
5123 SDValue Hi = Op.getOperand(1);
5124 SDValue Amt = Op.getOperand(2);
5125 EVT AmtVT = Amt.getValueType();
5127 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5128 DAG.getConstant(BitWidth, AmtVT), Amt);
5129 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5130 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5131 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5132 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5133 DAG.getConstant(-BitWidth, AmtVT));
5134 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
5135 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
5136 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
5137 Tmp4, Tmp6, ISD::SETLE);
5138 SDValue OutOps[] = { OutLo, OutHi };
5139 return DAG.getMergeValues(OutOps, 2, dl);
5142 //===----------------------------------------------------------------------===//
5143 // Vector related lowering.
5146 /// BuildSplatI - Build a canonical splati of Val with an element size of
5147 /// SplatSize. Cast the result to VT.
5148 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
5149 SelectionDAG &DAG, SDLoc dl) {
5150 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
5152 static const EVT VTys[] = { // canonical VT to use for each size.
5153 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
5156 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
5158 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
5162 EVT CanonicalVT = VTys[SplatSize-1];
5164 // Build a canonical splat for this value.
5165 SDValue Elt = DAG.getConstant(Val, MVT::i32);
5166 SmallVector<SDValue, 8> Ops;
5167 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
5168 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
5169 &Ops[0], Ops.size());
5170 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
5173 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
5174 /// specified intrinsic ID.
5175 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
5176 SelectionDAG &DAG, SDLoc dl,
5177 EVT DestVT = MVT::Other) {
5178 if (DestVT == MVT::Other) DestVT = Op.getValueType();
5179 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5180 DAG.getConstant(IID, MVT::i32), Op);
5183 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
5184 /// specified intrinsic ID.
5185 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
5186 SelectionDAG &DAG, SDLoc dl,
5187 EVT DestVT = MVT::Other) {
5188 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
5189 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5190 DAG.getConstant(IID, MVT::i32), LHS, RHS);
5193 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
5194 /// specified intrinsic ID.
5195 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
5196 SDValue Op2, SelectionDAG &DAG,
5197 SDLoc dl, EVT DestVT = MVT::Other) {
5198 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
5199 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5200 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
5204 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
5205 /// amount. The result has the specified value type.
5206 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
5207 EVT VT, SelectionDAG &DAG, SDLoc dl) {
5208 // Force LHS/RHS to be the right type.
5209 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
5210 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
5213 for (unsigned i = 0; i != 16; ++i)
5215 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
5216 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5219 // If this is a case we can't handle, return null and let the default
5220 // expansion code take care of it. If we CAN select this case, and if it
5221 // selects to a single instruction, return Op. Otherwise, if we can codegen
5222 // this case more efficiently than a constant pool load, lower it to the
5223 // sequence of ops that should be used.
5224 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
5225 SelectionDAG &DAG) const {
5227 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5228 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
5230 // Check if this is a splat of a constant value.
5231 APInt APSplatBits, APSplatUndef;
5232 unsigned SplatBitSize;
5234 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
5235 HasAnyUndefs, 0, true) || SplatBitSize > 32)
5238 unsigned SplatBits = APSplatBits.getZExtValue();
5239 unsigned SplatUndef = APSplatUndef.getZExtValue();
5240 unsigned SplatSize = SplatBitSize / 8;
5242 // First, handle single instruction cases.
5245 if (SplatBits == 0) {
5246 // Canonicalize all zero vectors to be v4i32.
5247 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5248 SDValue Z = DAG.getConstant(0, MVT::i32);
5249 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5250 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
5255 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
5256 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
5258 if (SextVal >= -16 && SextVal <= 15)
5259 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
5262 // Two instruction sequences.
5264 // If this value is in the range [-32,30] and is even, use:
5265 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
5266 // If this value is in the range [17,31] and is odd, use:
5267 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
5268 // If this value is in the range [-31,-17] and is odd, use:
5269 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
5270 // Note the last two are three-instruction sequences.
5271 if (SextVal >= -32 && SextVal <= 31) {
5272 // To avoid having these optimizations undone by constant folding,
5273 // we convert to a pseudo that will be expanded later into one of
5275 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
5276 EVT VT = Op.getValueType();
5277 int Size = VT == MVT::v16i8 ? 1 : (VT == MVT::v8i16 ? 2 : 4);
5278 SDValue EltSize = DAG.getConstant(Size, MVT::i32);
5279 return DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
5282 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
5283 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
5285 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
5286 // Make -1 and vspltisw -1:
5287 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
5289 // Make the VSLW intrinsic, computing 0x8000_0000.
5290 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
5293 // xor by OnesV to invert it.
5294 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5295 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5298 // Check to see if this is a wide variety of vsplti*, binop self cases.
5299 static const signed char SplatCsts[] = {
5300 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
5301 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
5304 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
5305 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
5306 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
5307 int i = SplatCsts[idx];
5309 // Figure out what shift amount will be used by altivec if shifted by i in
5311 unsigned TypeShiftAmt = i & (SplatBitSize-1);
5313 // vsplti + shl self.
5314 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
5315 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5316 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5317 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
5318 Intrinsic::ppc_altivec_vslw
5320 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5321 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5324 // vsplti + srl self.
5325 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5326 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5327 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5328 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
5329 Intrinsic::ppc_altivec_vsrw
5331 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5332 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5335 // vsplti + sra self.
5336 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5337 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5338 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5339 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
5340 Intrinsic::ppc_altivec_vsraw
5342 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5343 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5346 // vsplti + rol self.
5347 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
5348 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
5349 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5350 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5351 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
5352 Intrinsic::ppc_altivec_vrlw
5354 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5355 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5358 // t = vsplti c, result = vsldoi t, t, 1
5359 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
5360 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5361 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
5363 // t = vsplti c, result = vsldoi t, t, 2
5364 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
5365 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5366 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
5368 // t = vsplti c, result = vsldoi t, t, 3
5369 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
5370 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5371 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
5378 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5379 /// the specified operations to build the shuffle.
5380 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5381 SDValue RHS, SelectionDAG &DAG,
5383 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5384 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5385 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5388 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5400 if (OpNum == OP_COPY) {
5401 if (LHSID == (1*9+2)*9+3) return LHS;
5402 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5406 SDValue OpLHS, OpRHS;
5407 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5408 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5412 default: llvm_unreachable("Unknown i32 permute!");
5414 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
5415 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
5416 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
5417 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
5420 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
5421 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
5422 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
5423 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
5426 for (unsigned i = 0; i != 16; ++i)
5427 ShufIdxs[i] = (i&3)+0;
5430 for (unsigned i = 0; i != 16; ++i)
5431 ShufIdxs[i] = (i&3)+4;
5434 for (unsigned i = 0; i != 16; ++i)
5435 ShufIdxs[i] = (i&3)+8;
5438 for (unsigned i = 0; i != 16; ++i)
5439 ShufIdxs[i] = (i&3)+12;
5442 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
5444 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
5446 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
5448 EVT VT = OpLHS.getValueType();
5449 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
5450 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
5451 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
5452 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5455 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
5456 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
5457 /// return the code it can be lowered into. Worst case, it can always be
5458 /// lowered into a vperm.
5459 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5460 SelectionDAG &DAG) const {
5462 SDValue V1 = Op.getOperand(0);
5463 SDValue V2 = Op.getOperand(1);
5464 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5465 EVT VT = Op.getValueType();
5467 // Cases that are handled by instructions that take permute immediates
5468 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
5469 // selected by the instruction selector.
5470 if (V2.getOpcode() == ISD::UNDEF) {
5471 if (PPC::isSplatShuffleMask(SVOp, 1) ||
5472 PPC::isSplatShuffleMask(SVOp, 2) ||
5473 PPC::isSplatShuffleMask(SVOp, 4) ||
5474 PPC::isVPKUWUMShuffleMask(SVOp, true) ||
5475 PPC::isVPKUHUMShuffleMask(SVOp, true) ||
5476 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 ||
5477 PPC::isVMRGLShuffleMask(SVOp, 1, true) ||
5478 PPC::isVMRGLShuffleMask(SVOp, 2, true) ||
5479 PPC::isVMRGLShuffleMask(SVOp, 4, true) ||
5480 PPC::isVMRGHShuffleMask(SVOp, 1, true) ||
5481 PPC::isVMRGHShuffleMask(SVOp, 2, true) ||
5482 PPC::isVMRGHShuffleMask(SVOp, 4, true)) {
5487 // Altivec has a variety of "shuffle immediates" that take two vector inputs
5488 // and produce a fixed permutation. If any of these match, do not lower to
5490 if (PPC::isVPKUWUMShuffleMask(SVOp, false) ||
5491 PPC::isVPKUHUMShuffleMask(SVOp, false) ||
5492 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 ||
5493 PPC::isVMRGLShuffleMask(SVOp, 1, false) ||
5494 PPC::isVMRGLShuffleMask(SVOp, 2, false) ||
5495 PPC::isVMRGLShuffleMask(SVOp, 4, false) ||
5496 PPC::isVMRGHShuffleMask(SVOp, 1, false) ||
5497 PPC::isVMRGHShuffleMask(SVOp, 2, false) ||
5498 PPC::isVMRGHShuffleMask(SVOp, 4, false))
5501 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
5502 // perfect shuffle table to emit an optimal matching sequence.
5503 ArrayRef<int> PermMask = SVOp->getMask();
5505 unsigned PFIndexes[4];
5506 bool isFourElementShuffle = true;
5507 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
5508 unsigned EltNo = 8; // Start out undef.
5509 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
5510 if (PermMask[i*4+j] < 0)
5511 continue; // Undef, ignore it.
5513 unsigned ByteSource = PermMask[i*4+j];
5514 if ((ByteSource & 3) != j) {
5515 isFourElementShuffle = false;
5520 EltNo = ByteSource/4;
5521 } else if (EltNo != ByteSource/4) {
5522 isFourElementShuffle = false;
5526 PFIndexes[i] = EltNo;
5529 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
5530 // perfect shuffle vector to determine if it is cost effective to do this as
5531 // discrete instructions, or whether we should use a vperm.
5532 if (isFourElementShuffle) {
5533 // Compute the index in the perfect shuffle table.
5534 unsigned PFTableIndex =
5535 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5537 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5538 unsigned Cost = (PFEntry >> 30);
5540 // Determining when to avoid vperm is tricky. Many things affect the cost
5541 // of vperm, particularly how many times the perm mask needs to be computed.
5542 // For example, if the perm mask can be hoisted out of a loop or is already
5543 // used (perhaps because there are multiple permutes with the same shuffle
5544 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
5545 // the loop requires an extra register.
5547 // As a compromise, we only emit discrete instructions if the shuffle can be
5548 // generated in 3 or fewer operations. When we have loop information
5549 // available, if this block is within a loop, we should avoid using vperm
5550 // for 3-operation perms and use a constant pool load instead.
5552 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5555 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
5556 // vector that will get spilled to the constant pool.
5557 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
5559 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
5560 // that it is in input element units, not in bytes. Convert now.
5561 EVT EltVT = V1.getValueType().getVectorElementType();
5562 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
5564 SmallVector<SDValue, 16> ResultMask;
5565 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
5566 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
5568 for (unsigned j = 0; j != BytesPerElement; ++j)
5569 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
5573 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
5574 &ResultMask[0], ResultMask.size());
5575 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
5578 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
5579 /// altivec comparison. If it is, return true and fill in Opc/isDot with
5580 /// information about the intrinsic.
5581 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
5583 unsigned IntrinsicID =
5584 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
5587 switch (IntrinsicID) {
5588 default: return false;
5589 // Comparison predicates.
5590 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
5591 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
5592 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
5593 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
5594 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
5595 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
5596 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
5597 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
5598 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
5599 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
5600 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
5601 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
5602 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
5604 // Normal Comparisons.
5605 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
5606 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
5607 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
5608 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
5609 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
5610 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
5611 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
5612 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
5613 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
5614 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
5615 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
5616 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
5617 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
5622 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
5623 /// lower, do it, otherwise return null.
5624 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
5625 SelectionDAG &DAG) const {
5626 // If this is a lowered altivec predicate compare, CompareOpc is set to the
5627 // opcode number of the comparison.
5631 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
5632 return SDValue(); // Don't custom lower most intrinsics.
5634 // If this is a non-dot comparison, make the VCMP node and we are done.
5636 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
5637 Op.getOperand(1), Op.getOperand(2),
5638 DAG.getConstant(CompareOpc, MVT::i32));
5639 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
5642 // Create the PPCISD altivec 'dot' comparison node.
5644 Op.getOperand(2), // LHS
5645 Op.getOperand(3), // RHS
5646 DAG.getConstant(CompareOpc, MVT::i32)
5648 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
5649 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
5651 // Now that we have the comparison, emit a copy from the CR to a GPR.
5652 // This is flagged to the above dot comparison.
5653 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
5654 DAG.getRegister(PPC::CR6, MVT::i32),
5655 CompNode.getValue(1));
5657 // Unpack the result based on how the target uses it.
5658 unsigned BitNo; // Bit # of CR6.
5659 bool InvertBit; // Invert result?
5660 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
5661 default: // Can't happen, don't crash on invalid number though.
5662 case 0: // Return the value of the EQ bit of CR6.
5663 BitNo = 0; InvertBit = false;
5665 case 1: // Return the inverted value of the EQ bit of CR6.
5666 BitNo = 0; InvertBit = true;
5668 case 2: // Return the value of the LT bit of CR6.
5669 BitNo = 2; InvertBit = false;
5671 case 3: // Return the inverted value of the LT bit of CR6.
5672 BitNo = 2; InvertBit = true;
5676 // Shift the bit into the low position.
5677 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
5678 DAG.getConstant(8-(3-BitNo), MVT::i32));
5680 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
5681 DAG.getConstant(1, MVT::i32));
5683 // If we are supposed to, toggle the bit.
5685 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
5686 DAG.getConstant(1, MVT::i32));
5690 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
5691 SelectionDAG &DAG) const {
5693 // Create a stack slot that is 16-byte aligned.
5694 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
5695 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
5696 EVT PtrVT = getPointerTy();
5697 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5699 // Store the input value into Value#0 of the stack slot.
5700 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
5701 Op.getOperand(0), FIdx, MachinePointerInfo(),
5704 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
5705 false, false, false, 0);
5708 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
5710 if (Op.getValueType() == MVT::v4i32) {
5711 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5713 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
5714 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
5716 SDValue RHSSwap = // = vrlw RHS, 16
5717 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
5719 // Shrinkify inputs to v8i16.
5720 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
5721 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
5722 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
5724 // Low parts multiplied together, generating 32-bit results (we ignore the
5726 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
5727 LHS, RHS, DAG, dl, MVT::v4i32);
5729 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
5730 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
5731 // Shift the high parts up 16 bits.
5732 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
5734 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
5735 } else if (Op.getValueType() == MVT::v8i16) {
5736 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5738 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
5740 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
5741 LHS, RHS, Zero, DAG, dl);
5742 } else if (Op.getValueType() == MVT::v16i8) {
5743 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5745 // Multiply the even 8-bit parts, producing 16-bit sums.
5746 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
5747 LHS, RHS, DAG, dl, MVT::v8i16);
5748 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
5750 // Multiply the odd 8-bit parts, producing 16-bit sums.
5751 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
5752 LHS, RHS, DAG, dl, MVT::v8i16);
5753 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
5755 // Merge the results together.
5757 for (unsigned i = 0; i != 8; ++i) {
5759 Ops[i*2+1] = 2*i+1+16;
5761 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
5763 llvm_unreachable("Unknown mul to lower!");
5767 /// LowerOperation - Provide custom lowering hooks for some operations.
5769 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
5770 switch (Op.getOpcode()) {
5771 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
5772 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
5773 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
5774 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
5775 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
5776 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
5777 case ISD::SETCC: return LowerSETCC(Op, DAG);
5778 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
5779 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
5781 return LowerVASTART(Op, DAG, PPCSubTarget);
5784 return LowerVAARG(Op, DAG, PPCSubTarget);
5787 return LowerVACOPY(Op, DAG, PPCSubTarget);
5789 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
5790 case ISD::DYNAMIC_STACKALLOC:
5791 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
5793 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
5794 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
5796 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
5797 case ISD::FP_TO_UINT:
5798 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
5800 case ISD::UINT_TO_FP:
5801 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
5802 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
5804 // Lower 64-bit shifts.
5805 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
5806 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
5807 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
5809 // Vector-related lowering.
5810 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
5811 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
5812 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
5813 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
5814 case ISD::MUL: return LowerMUL(Op, DAG);
5816 // For counter-based loop handling.
5817 case ISD::INTRINSIC_W_CHAIN: return SDValue();
5819 // Frame & Return address.
5820 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
5821 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
5825 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
5826 SmallVectorImpl<SDValue>&Results,
5827 SelectionDAG &DAG) const {
5828 const TargetMachine &TM = getTargetMachine();
5830 switch (N->getOpcode()) {
5832 llvm_unreachable("Do not know how to custom type legalize this operation!");
5833 case ISD::INTRINSIC_W_CHAIN: {
5834 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
5835 Intrinsic::ppc_is_decremented_ctr_nonzero)
5838 assert(N->getValueType(0) == MVT::i1 &&
5839 "Unexpected result type for CTR decrement intrinsic");
5840 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
5841 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
5842 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
5845 Results.push_back(NewInt);
5846 Results.push_back(NewInt.getValue(1));
5850 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
5851 || TM.getSubtarget<PPCSubtarget>().isPPC64())
5854 EVT VT = N->getValueType(0);
5856 if (VT == MVT::i64) {
5857 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, PPCSubTarget);
5859 Results.push_back(NewNode);
5860 Results.push_back(NewNode.getValue(1));
5864 case ISD::FP_ROUND_INREG: {
5865 assert(N->getValueType(0) == MVT::ppcf128);
5866 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
5867 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
5868 MVT::f64, N->getOperand(0),
5869 DAG.getIntPtrConstant(0));
5870 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
5871 MVT::f64, N->getOperand(0),
5872 DAG.getIntPtrConstant(1));
5874 // Add the two halves of the long double in round-to-zero mode.
5875 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
5877 // We know the low half is about to be thrown away, so just use something
5879 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
5883 case ISD::FP_TO_SINT:
5884 // LowerFP_TO_INT() can only handle f32 and f64.
5885 if (N->getOperand(0).getValueType() == MVT::ppcf128)
5887 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
5893 //===----------------------------------------------------------------------===//
5894 // Other Lowering Code
5895 //===----------------------------------------------------------------------===//
5898 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
5899 bool is64bit, unsigned BinOpcode) const {
5900 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
5901 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5903 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5904 MachineFunction *F = BB->getParent();
5905 MachineFunction::iterator It = BB;
5908 unsigned dest = MI->getOperand(0).getReg();
5909 unsigned ptrA = MI->getOperand(1).getReg();
5910 unsigned ptrB = MI->getOperand(2).getReg();
5911 unsigned incr = MI->getOperand(3).getReg();
5912 DebugLoc dl = MI->getDebugLoc();
5914 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
5915 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
5916 F->insert(It, loopMBB);
5917 F->insert(It, exitMBB);
5918 exitMBB->splice(exitMBB->begin(), BB,
5919 llvm::next(MachineBasicBlock::iterator(MI)),
5921 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5923 MachineRegisterInfo &RegInfo = F->getRegInfo();
5924 unsigned TmpReg = (!BinOpcode) ? incr :
5925 RegInfo.createVirtualRegister(
5926 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
5927 (const TargetRegisterClass *) &PPC::GPRCRegClass);
5931 // fallthrough --> loopMBB
5932 BB->addSuccessor(loopMBB);
5935 // l[wd]arx dest, ptr
5936 // add r0, dest, incr
5937 // st[wd]cx. r0, ptr
5939 // fallthrough --> exitMBB
5941 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
5942 .addReg(ptrA).addReg(ptrB);
5944 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
5945 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
5946 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
5947 BuildMI(BB, dl, TII->get(PPC::BCC))
5948 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
5949 BB->addSuccessor(loopMBB);
5950 BB->addSuccessor(exitMBB);
5959 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
5960 MachineBasicBlock *BB,
5961 bool is8bit, // operation
5962 unsigned BinOpcode) const {
5963 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
5964 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5965 // In 64 bit mode we have to use 64 bits for addresses, even though the
5966 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
5967 // registers without caring whether they're 32 or 64, but here we're
5968 // doing actual arithmetic on the addresses.
5969 bool is64bit = PPCSubTarget.isPPC64();
5970 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
5972 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5973 MachineFunction *F = BB->getParent();
5974 MachineFunction::iterator It = BB;
5977 unsigned dest = MI->getOperand(0).getReg();
5978 unsigned ptrA = MI->getOperand(1).getReg();
5979 unsigned ptrB = MI->getOperand(2).getReg();
5980 unsigned incr = MI->getOperand(3).getReg();
5981 DebugLoc dl = MI->getDebugLoc();
5983 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
5984 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
5985 F->insert(It, loopMBB);
5986 F->insert(It, exitMBB);
5987 exitMBB->splice(exitMBB->begin(), BB,
5988 llvm::next(MachineBasicBlock::iterator(MI)),
5990 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5992 MachineRegisterInfo &RegInfo = F->getRegInfo();
5993 const TargetRegisterClass *RC =
5994 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
5995 (const TargetRegisterClass *) &PPC::GPRCRegClass;
5996 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
5997 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
5998 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
5999 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
6000 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6001 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6002 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6003 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6004 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
6005 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6006 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6008 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
6012 // fallthrough --> loopMBB
6013 BB->addSuccessor(loopMBB);
6015 // The 4-byte load must be aligned, while a char or short may be
6016 // anywhere in the word. Hence all this nasty bookkeeping code.
6017 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6018 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6019 // xori shift, shift1, 24 [16]
6020 // rlwinm ptr, ptr1, 0, 0, 29
6021 // slw incr2, incr, shift
6022 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6023 // slw mask, mask2, shift
6025 // lwarx tmpDest, ptr
6026 // add tmp, tmpDest, incr2
6027 // andc tmp2, tmpDest, mask
6028 // and tmp3, tmp, mask
6029 // or tmp4, tmp3, tmp2
6032 // fallthrough --> exitMBB
6033 // srw dest, tmpDest, shift
6034 if (ptrA != ZeroReg) {
6035 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6036 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6037 .addReg(ptrA).addReg(ptrB);
6041 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6042 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6043 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6044 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6046 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6047 .addReg(Ptr1Reg).addImm(0).addImm(61);
6049 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6050 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6051 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
6052 .addReg(incr).addReg(ShiftReg);
6054 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6056 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6057 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
6059 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6060 .addReg(Mask2Reg).addReg(ShiftReg);
6063 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6064 .addReg(ZeroReg).addReg(PtrReg);
6066 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
6067 .addReg(Incr2Reg).addReg(TmpDestReg);
6068 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
6069 .addReg(TmpDestReg).addReg(MaskReg);
6070 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
6071 .addReg(TmpReg).addReg(MaskReg);
6072 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
6073 .addReg(Tmp3Reg).addReg(Tmp2Reg);
6074 BuildMI(BB, dl, TII->get(PPC::STWCX))
6075 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
6076 BuildMI(BB, dl, TII->get(PPC::BCC))
6077 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6078 BB->addSuccessor(loopMBB);
6079 BB->addSuccessor(exitMBB);
6084 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
6089 llvm::MachineBasicBlock*
6090 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
6091 MachineBasicBlock *MBB) const {
6092 DebugLoc DL = MI->getDebugLoc();
6093 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6095 MachineFunction *MF = MBB->getParent();
6096 MachineRegisterInfo &MRI = MF->getRegInfo();
6098 const BasicBlock *BB = MBB->getBasicBlock();
6099 MachineFunction::iterator I = MBB;
6103 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6104 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6106 unsigned DstReg = MI->getOperand(0).getReg();
6107 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
6108 assert(RC->hasType(MVT::i32) && "Invalid destination!");
6109 unsigned mainDstReg = MRI.createVirtualRegister(RC);
6110 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
6112 MVT PVT = getPointerTy();
6113 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6114 "Invalid Pointer Size!");
6115 // For v = setjmp(buf), we generate
6118 // SjLjSetup mainMBB
6124 // buf[LabelOffset] = LR
6128 // v = phi(main, restore)
6131 MachineBasicBlock *thisMBB = MBB;
6132 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
6133 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
6134 MF->insert(I, mainMBB);
6135 MF->insert(I, sinkMBB);
6137 MachineInstrBuilder MIB;
6139 // Transfer the remainder of BB and its successor edges to sinkMBB.
6140 sinkMBB->splice(sinkMBB->begin(), MBB,
6141 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
6142 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
6144 // Note that the structure of the jmp_buf used here is not compatible
6145 // with that used by libc, and is not designed to be. Specifically, it
6146 // stores only those 'reserved' registers that LLVM does not otherwise
6147 // understand how to spill. Also, by convention, by the time this
6148 // intrinsic is called, Clang has already stored the frame address in the
6149 // first slot of the buffer and stack address in the third. Following the
6150 // X86 target code, we'll store the jump address in the second slot. We also
6151 // need to save the TOC pointer (R2) to handle jumps between shared
6152 // libraries, and that will be stored in the fourth slot. The thread
6153 // identifier (R13) is not affected.
6156 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6157 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6158 const int64_t BPOffset = 4 * PVT.getStoreSize();
6160 // Prepare IP either in reg.
6161 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
6162 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
6163 unsigned BufReg = MI->getOperand(1).getReg();
6165 if (PPCSubTarget.isPPC64() && PPCSubTarget.isSVR4ABI()) {
6166 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
6170 MIB.setMemRefs(MMOBegin, MMOEnd);
6173 // Naked functions never have a base pointer, and so we use r1. For all
6174 // other functions, this decision must be delayed until during PEI.
6176 if (MF->getFunction()->getAttributes().hasAttribute(
6177 AttributeSet::FunctionIndex, Attribute::Naked))
6178 BaseReg = PPCSubTarget.isPPC64() ? PPC::X1 : PPC::R1;
6180 BaseReg = PPCSubTarget.isPPC64() ? PPC::BP8 : PPC::BP;
6182 MIB = BuildMI(*thisMBB, MI, DL,
6183 TII->get(PPCSubTarget.isPPC64() ? PPC::STD : PPC::STW))
6187 MIB.setMemRefs(MMOBegin, MMOEnd);
6190 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
6191 const PPCRegisterInfo *TRI =
6192 static_cast<const PPCRegisterInfo*>(getTargetMachine().getRegisterInfo());
6193 MIB.addRegMask(TRI->getNoPreservedMask());
6195 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
6197 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
6199 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
6201 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
6202 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
6206 MIB = BuildMI(mainMBB, DL,
6207 TII->get(PPCSubTarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
6210 if (PPCSubTarget.isPPC64()) {
6211 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
6213 .addImm(LabelOffset)
6216 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
6218 .addImm(LabelOffset)
6222 MIB.setMemRefs(MMOBegin, MMOEnd);
6224 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
6225 mainMBB->addSuccessor(sinkMBB);
6228 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
6229 TII->get(PPC::PHI), DstReg)
6230 .addReg(mainDstReg).addMBB(mainMBB)
6231 .addReg(restoreDstReg).addMBB(thisMBB);
6233 MI->eraseFromParent();
6238 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
6239 MachineBasicBlock *MBB) const {
6240 DebugLoc DL = MI->getDebugLoc();
6241 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6243 MachineFunction *MF = MBB->getParent();
6244 MachineRegisterInfo &MRI = MF->getRegInfo();
6247 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6248 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6250 MVT PVT = getPointerTy();
6251 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6252 "Invalid Pointer Size!");
6254 const TargetRegisterClass *RC =
6255 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6256 unsigned Tmp = MRI.createVirtualRegister(RC);
6257 // Since FP is only updated here but NOT referenced, it's treated as GPR.
6258 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6259 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6260 unsigned BP = (PVT == MVT::i64) ? PPC::X30 : PPC::R30;
6262 MachineInstrBuilder MIB;
6264 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6265 const int64_t SPOffset = 2 * PVT.getStoreSize();
6266 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6267 const int64_t BPOffset = 4 * PVT.getStoreSize();
6269 unsigned BufReg = MI->getOperand(0).getReg();
6271 // Reload FP (the jumped-to function may not have had a
6272 // frame pointer, and if so, then its r31 will be restored
6274 if (PVT == MVT::i64) {
6275 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
6279 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
6283 MIB.setMemRefs(MMOBegin, MMOEnd);
6286 if (PVT == MVT::i64) {
6287 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
6288 .addImm(LabelOffset)
6291 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
6292 .addImm(LabelOffset)
6295 MIB.setMemRefs(MMOBegin, MMOEnd);
6298 if (PVT == MVT::i64) {
6299 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
6303 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
6307 MIB.setMemRefs(MMOBegin, MMOEnd);
6310 if (PVT == MVT::i64) {
6311 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
6315 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
6319 MIB.setMemRefs(MMOBegin, MMOEnd);
6322 if (PVT == MVT::i64 && PPCSubTarget.isSVR4ABI()) {
6323 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
6327 MIB.setMemRefs(MMOBegin, MMOEnd);
6331 BuildMI(*MBB, MI, DL,
6332 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
6333 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
6335 MI->eraseFromParent();
6340 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6341 MachineBasicBlock *BB) const {
6342 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
6343 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
6344 return emitEHSjLjSetJmp(MI, BB);
6345 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
6346 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
6347 return emitEHSjLjLongJmp(MI, BB);
6350 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6352 // To "insert" these instructions we actually have to insert their
6353 // control-flow patterns.
6354 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6355 MachineFunction::iterator It = BB;
6358 MachineFunction *F = BB->getParent();
6360 if (PPCSubTarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6361 MI->getOpcode() == PPC::SELECT_CC_I8)) {
6362 SmallVector<MachineOperand, 2> Cond;
6363 Cond.push_back(MI->getOperand(4));
6364 Cond.push_back(MI->getOperand(1));
6366 DebugLoc dl = MI->getDebugLoc();
6367 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6368 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
6369 Cond, MI->getOperand(2).getReg(),
6370 MI->getOperand(3).getReg());
6371 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6372 MI->getOpcode() == PPC::SELECT_CC_I8 ||
6373 MI->getOpcode() == PPC::SELECT_CC_F4 ||
6374 MI->getOpcode() == PPC::SELECT_CC_F8 ||
6375 MI->getOpcode() == PPC::SELECT_CC_VRRC) {
6378 // The incoming instruction knows the destination vreg to set, the
6379 // condition code register to branch on, the true/false values to
6380 // select between, and a branch opcode to use.
6385 // cmpTY ccX, r1, r2
6387 // fallthrough --> copy0MBB
6388 MachineBasicBlock *thisMBB = BB;
6389 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
6390 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
6391 unsigned SelectPred = MI->getOperand(4).getImm();
6392 DebugLoc dl = MI->getDebugLoc();
6393 F->insert(It, copy0MBB);
6394 F->insert(It, sinkMBB);
6396 // Transfer the remainder of BB and its successor edges to sinkMBB.
6397 sinkMBB->splice(sinkMBB->begin(), BB,
6398 llvm::next(MachineBasicBlock::iterator(MI)),
6400 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
6402 // Next, add the true and fallthrough blocks as its successors.
6403 BB->addSuccessor(copy0MBB);
6404 BB->addSuccessor(sinkMBB);
6406 BuildMI(BB, dl, TII->get(PPC::BCC))
6407 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
6410 // %FalseValue = ...
6411 // # fallthrough to sinkMBB
6414 // Update machine-CFG edges
6415 BB->addSuccessor(sinkMBB);
6418 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
6421 BuildMI(*BB, BB->begin(), dl,
6422 TII->get(PPC::PHI), MI->getOperand(0).getReg())
6423 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
6424 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
6426 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
6427 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
6428 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
6429 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
6430 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
6431 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
6432 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
6433 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
6435 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
6436 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
6437 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
6438 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
6439 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
6440 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
6441 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
6442 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
6444 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
6445 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
6446 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
6447 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
6448 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
6449 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
6450 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
6451 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
6453 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
6454 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
6455 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
6456 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
6457 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
6458 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
6459 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
6460 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
6462 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
6463 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
6464 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
6465 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
6466 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
6467 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
6468 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
6469 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
6471 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
6472 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
6473 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
6474 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
6475 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
6476 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
6477 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
6478 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
6480 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
6481 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
6482 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
6483 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
6484 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
6485 BB = EmitAtomicBinary(MI, BB, false, 0);
6486 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
6487 BB = EmitAtomicBinary(MI, BB, true, 0);
6489 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
6490 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
6491 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
6493 unsigned dest = MI->getOperand(0).getReg();
6494 unsigned ptrA = MI->getOperand(1).getReg();
6495 unsigned ptrB = MI->getOperand(2).getReg();
6496 unsigned oldval = MI->getOperand(3).getReg();
6497 unsigned newval = MI->getOperand(4).getReg();
6498 DebugLoc dl = MI->getDebugLoc();
6500 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6501 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6502 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6503 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6504 F->insert(It, loop1MBB);
6505 F->insert(It, loop2MBB);
6506 F->insert(It, midMBB);
6507 F->insert(It, exitMBB);
6508 exitMBB->splice(exitMBB->begin(), BB,
6509 llvm::next(MachineBasicBlock::iterator(MI)),
6511 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6515 // fallthrough --> loopMBB
6516 BB->addSuccessor(loop1MBB);
6519 // l[wd]arx dest, ptr
6520 // cmp[wd] dest, oldval
6523 // st[wd]cx. newval, ptr
6527 // st[wd]cx. dest, ptr
6530 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6531 .addReg(ptrA).addReg(ptrB);
6532 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
6533 .addReg(oldval).addReg(dest);
6534 BuildMI(BB, dl, TII->get(PPC::BCC))
6535 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6536 BB->addSuccessor(loop2MBB);
6537 BB->addSuccessor(midMBB);
6540 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6541 .addReg(newval).addReg(ptrA).addReg(ptrB);
6542 BuildMI(BB, dl, TII->get(PPC::BCC))
6543 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6544 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6545 BB->addSuccessor(loop1MBB);
6546 BB->addSuccessor(exitMBB);
6549 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6550 .addReg(dest).addReg(ptrA).addReg(ptrB);
6551 BB->addSuccessor(exitMBB);
6556 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
6557 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
6558 // We must use 64-bit registers for addresses when targeting 64-bit,
6559 // since we're actually doing arithmetic on them. Other registers
6561 bool is64bit = PPCSubTarget.isPPC64();
6562 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
6564 unsigned dest = MI->getOperand(0).getReg();
6565 unsigned ptrA = MI->getOperand(1).getReg();
6566 unsigned ptrB = MI->getOperand(2).getReg();
6567 unsigned oldval = MI->getOperand(3).getReg();
6568 unsigned newval = MI->getOperand(4).getReg();
6569 DebugLoc dl = MI->getDebugLoc();
6571 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6572 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6573 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6574 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6575 F->insert(It, loop1MBB);
6576 F->insert(It, loop2MBB);
6577 F->insert(It, midMBB);
6578 F->insert(It, exitMBB);
6579 exitMBB->splice(exitMBB->begin(), BB,
6580 llvm::next(MachineBasicBlock::iterator(MI)),
6582 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6584 MachineRegisterInfo &RegInfo = F->getRegInfo();
6585 const TargetRegisterClass *RC =
6586 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6587 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6588 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6589 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6590 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6591 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
6592 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
6593 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
6594 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
6595 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6596 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6597 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6598 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6599 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6600 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6602 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
6603 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6606 // fallthrough --> loopMBB
6607 BB->addSuccessor(loop1MBB);
6609 // The 4-byte load must be aligned, while a char or short may be
6610 // anywhere in the word. Hence all this nasty bookkeeping code.
6611 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6612 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6613 // xori shift, shift1, 24 [16]
6614 // rlwinm ptr, ptr1, 0, 0, 29
6615 // slw newval2, newval, shift
6616 // slw oldval2, oldval,shift
6617 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6618 // slw mask, mask2, shift
6619 // and newval3, newval2, mask
6620 // and oldval3, oldval2, mask
6622 // lwarx tmpDest, ptr
6623 // and tmp, tmpDest, mask
6624 // cmpw tmp, oldval3
6627 // andc tmp2, tmpDest, mask
6628 // or tmp4, tmp2, newval3
6633 // stwcx. tmpDest, ptr
6635 // srw dest, tmpDest, shift
6636 if (ptrA != ZeroReg) {
6637 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6638 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6639 .addReg(ptrA).addReg(ptrB);
6643 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6644 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6645 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6646 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6648 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6649 .addReg(Ptr1Reg).addImm(0).addImm(61);
6651 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6652 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6653 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
6654 .addReg(newval).addReg(ShiftReg);
6655 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
6656 .addReg(oldval).addReg(ShiftReg);
6658 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6660 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6661 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
6662 .addReg(Mask3Reg).addImm(65535);
6664 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6665 .addReg(Mask2Reg).addReg(ShiftReg);
6666 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
6667 .addReg(NewVal2Reg).addReg(MaskReg);
6668 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
6669 .addReg(OldVal2Reg).addReg(MaskReg);
6672 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6673 .addReg(ZeroReg).addReg(PtrReg);
6674 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
6675 .addReg(TmpDestReg).addReg(MaskReg);
6676 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
6677 .addReg(TmpReg).addReg(OldVal3Reg);
6678 BuildMI(BB, dl, TII->get(PPC::BCC))
6679 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6680 BB->addSuccessor(loop2MBB);
6681 BB->addSuccessor(midMBB);
6684 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
6685 .addReg(TmpDestReg).addReg(MaskReg);
6686 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
6687 .addReg(Tmp2Reg).addReg(NewVal3Reg);
6688 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
6689 .addReg(ZeroReg).addReg(PtrReg);
6690 BuildMI(BB, dl, TII->get(PPC::BCC))
6691 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6692 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6693 BB->addSuccessor(loop1MBB);
6694 BB->addSuccessor(exitMBB);
6697 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
6698 .addReg(ZeroReg).addReg(PtrReg);
6699 BB->addSuccessor(exitMBB);
6704 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
6706 } else if (MI->getOpcode() == PPC::FADDrtz) {
6707 // This pseudo performs an FADD with rounding mode temporarily forced
6708 // to round-to-zero. We emit this via custom inserter since the FPSCR
6709 // is not modeled at the SelectionDAG level.
6710 unsigned Dest = MI->getOperand(0).getReg();
6711 unsigned Src1 = MI->getOperand(1).getReg();
6712 unsigned Src2 = MI->getOperand(2).getReg();
6713 DebugLoc dl = MI->getDebugLoc();
6715 MachineRegisterInfo &RegInfo = F->getRegInfo();
6716 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
6718 // Save FPSCR value.
6719 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
6721 // Set rounding mode to round-to-zero.
6722 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
6723 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
6725 // Perform addition.
6726 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
6728 // Restore FPSCR value.
6729 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg);
6731 llvm_unreachable("Unexpected instr type to insert");
6734 MI->eraseFromParent(); // The pseudo instruction is gone now.
6738 //===----------------------------------------------------------------------===//
6739 // Target Optimization Hooks
6740 //===----------------------------------------------------------------------===//
6742 SDValue PPCTargetLowering::DAGCombineFastRecip(SDValue Op,
6743 DAGCombinerInfo &DCI) const {
6744 if (DCI.isAfterLegalizeVectorOps())
6747 EVT VT = Op.getValueType();
6749 if ((VT == MVT::f32 && PPCSubTarget.hasFRES()) ||
6750 (VT == MVT::f64 && PPCSubTarget.hasFRE()) ||
6751 (VT == MVT::v4f32 && PPCSubTarget.hasAltivec())) {
6753 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
6754 // For the reciprocal, we need to find the zero of the function:
6755 // F(X) = A X - 1 [which has a zero at X = 1/A]
6757 // X_{i+1} = X_i (2 - A X_i) = X_i + X_i (1 - A X_i) [this second form
6758 // does not require additional intermediate precision]
6760 // Convergence is quadratic, so we essentially double the number of digits
6761 // correct after every iteration. The minimum architected relative
6762 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
6763 // 23 digits and double has 52 digits.
6764 int Iterations = PPCSubTarget.hasRecipPrec() ? 1 : 3;
6765 if (VT.getScalarType() == MVT::f64)
6768 SelectionDAG &DAG = DCI.DAG;
6772 DAG.getConstantFP(1.0, VT.getScalarType());
6773 if (VT.isVector()) {
6774 assert(VT.getVectorNumElements() == 4 &&
6775 "Unknown vector type");
6776 FPOne = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
6777 FPOne, FPOne, FPOne, FPOne);
6780 SDValue Est = DAG.getNode(PPCISD::FRE, dl, VT, Op);
6781 DCI.AddToWorklist(Est.getNode());
6783 // Newton iterations: Est = Est + Est (1 - Arg * Est)
6784 for (int i = 0; i < Iterations; ++i) {
6785 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Op, Est);
6786 DCI.AddToWorklist(NewEst.getNode());
6788 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPOne, NewEst);
6789 DCI.AddToWorklist(NewEst.getNode());
6791 NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
6792 DCI.AddToWorklist(NewEst.getNode());
6794 Est = DAG.getNode(ISD::FADD, dl, VT, Est, NewEst);
6795 DCI.AddToWorklist(Est.getNode());
6804 SDValue PPCTargetLowering::DAGCombineFastRecipFSQRT(SDValue Op,
6805 DAGCombinerInfo &DCI) const {
6806 if (DCI.isAfterLegalizeVectorOps())
6809 EVT VT = Op.getValueType();
6811 if ((VT == MVT::f32 && PPCSubTarget.hasFRSQRTES()) ||
6812 (VT == MVT::f64 && PPCSubTarget.hasFRSQRTE()) ||
6813 (VT == MVT::v4f32 && PPCSubTarget.hasAltivec())) {
6815 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
6816 // For the reciprocal sqrt, we need to find the zero of the function:
6817 // F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
6819 // X_{i+1} = X_i (1.5 - A X_i^2 / 2)
6820 // As a result, we precompute A/2 prior to the iteration loop.
6822 // Convergence is quadratic, so we essentially double the number of digits
6823 // correct after every iteration. The minimum architected relative
6824 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
6825 // 23 digits and double has 52 digits.
6826 int Iterations = PPCSubTarget.hasRecipPrec() ? 1 : 3;
6827 if (VT.getScalarType() == MVT::f64)
6830 SelectionDAG &DAG = DCI.DAG;
6833 SDValue FPThreeHalves =
6834 DAG.getConstantFP(1.5, VT.getScalarType());
6835 if (VT.isVector()) {
6836 assert(VT.getVectorNumElements() == 4 &&
6837 "Unknown vector type");
6838 FPThreeHalves = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
6839 FPThreeHalves, FPThreeHalves,
6840 FPThreeHalves, FPThreeHalves);
6843 SDValue Est = DAG.getNode(PPCISD::FRSQRTE, dl, VT, Op);
6844 DCI.AddToWorklist(Est.getNode());
6846 // We now need 0.5*Arg which we can write as (1.5*Arg - Arg) so that
6847 // this entire sequence requires only one FP constant.
6848 SDValue HalfArg = DAG.getNode(ISD::FMUL, dl, VT, FPThreeHalves, Op);
6849 DCI.AddToWorklist(HalfArg.getNode());
6851 HalfArg = DAG.getNode(ISD::FSUB, dl, VT, HalfArg, Op);
6852 DCI.AddToWorklist(HalfArg.getNode());
6854 // Newton iterations: Est = Est * (1.5 - HalfArg * Est * Est)
6855 for (int i = 0; i < Iterations; ++i) {
6856 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, Est);
6857 DCI.AddToWorklist(NewEst.getNode());
6859 NewEst = DAG.getNode(ISD::FMUL, dl, VT, HalfArg, NewEst);
6860 DCI.AddToWorklist(NewEst.getNode());
6862 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPThreeHalves, NewEst);
6863 DCI.AddToWorklist(NewEst.getNode());
6865 Est = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
6866 DCI.AddToWorklist(Est.getNode());
6875 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
6876 // not enforce equality of the chain operands.
6877 static bool isConsecutiveLS(LSBaseSDNode *LS, LSBaseSDNode *Base,
6878 unsigned Bytes, int Dist,
6879 SelectionDAG &DAG) {
6880 EVT VT = LS->getMemoryVT();
6881 if (VT.getSizeInBits() / 8 != Bytes)
6884 SDValue Loc = LS->getBasePtr();
6885 SDValue BaseLoc = Base->getBasePtr();
6886 if (Loc.getOpcode() == ISD::FrameIndex) {
6887 if (BaseLoc.getOpcode() != ISD::FrameIndex)
6889 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6890 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
6891 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
6892 int FS = MFI->getObjectSize(FI);
6893 int BFS = MFI->getObjectSize(BFI);
6894 if (FS != BFS || FS != (int)Bytes) return false;
6895 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
6899 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
6900 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
6903 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6904 const GlobalValue *GV1 = NULL;
6905 const GlobalValue *GV2 = NULL;
6906 int64_t Offset1 = 0;
6907 int64_t Offset2 = 0;
6908 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
6909 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
6910 if (isGA1 && isGA2 && GV1 == GV2)
6911 return Offset1 == (Offset2 + Dist*Bytes);
6915 // Return true is there is a nearyby consecutive load to the one provided
6916 // (regardless of alignment). We search up and down the chain, looking though
6917 // token factors and other loads (but nothing else). As a result, a true
6918 // results indicates that it is safe to create a new consecutive load adjacent
6919 // to the load provided.
6920 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
6921 SDValue Chain = LD->getChain();
6922 EVT VT = LD->getMemoryVT();
6924 SmallSet<SDNode *, 16> LoadRoots;
6925 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
6926 SmallSet<SDNode *, 16> Visited;
6928 // First, search up the chain, branching to follow all token-factor operands.
6929 // If we find a consecutive load, then we're done, otherwise, record all
6930 // nodes just above the top-level loads and token factors.
6931 while (!Queue.empty()) {
6932 SDNode *ChainNext = Queue.pop_back_val();
6933 if (!Visited.insert(ChainNext))
6936 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(ChainNext)) {
6937 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
6940 if (!Visited.count(ChainLD->getChain().getNode()))
6941 Queue.push_back(ChainLD->getChain().getNode());
6942 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
6943 for (SDNode::op_iterator O = ChainNext->op_begin(),
6944 OE = ChainNext->op_end(); O != OE; ++O)
6945 if (!Visited.count(O->getNode()))
6946 Queue.push_back(O->getNode());
6948 LoadRoots.insert(ChainNext);
6951 // Second, search down the chain, starting from the top-level nodes recorded
6952 // in the first phase. These top-level nodes are the nodes just above all
6953 // loads and token factors. Starting with their uses, recursively look though
6954 // all loads (just the chain uses) and token factors to find a consecutive
6959 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
6960 IE = LoadRoots.end(); I != IE; ++I) {
6961 Queue.push_back(*I);
6963 while (!Queue.empty()) {
6964 SDNode *LoadRoot = Queue.pop_back_val();
6965 if (!Visited.insert(LoadRoot))
6968 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(LoadRoot))
6969 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
6972 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
6973 UE = LoadRoot->use_end(); UI != UE; ++UI)
6974 if (((isa<LoadSDNode>(*UI) &&
6975 cast<LoadSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
6976 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
6977 Queue.push_back(*UI);
6984 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
6985 DAGCombinerInfo &DCI) const {
6986 const TargetMachine &TM = getTargetMachine();
6987 SelectionDAG &DAG = DCI.DAG;
6989 switch (N->getOpcode()) {
6992 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6993 if (C->isNullValue()) // 0 << V -> 0.
6994 return N->getOperand(0);
6998 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6999 if (C->isNullValue()) // 0 >>u V -> 0.
7000 return N->getOperand(0);
7004 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
7005 if (C->isNullValue() || // 0 >>s V -> 0.
7006 C->isAllOnesValue()) // -1 >>s V -> -1.
7007 return N->getOperand(0);
7011 assert(TM.Options.UnsafeFPMath &&
7012 "Reciprocal estimates require UnsafeFPMath");
7014 if (N->getOperand(1).getOpcode() == ISD::FSQRT) {
7016 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0), DCI);
7017 if (RV.getNode() != 0) {
7018 DCI.AddToWorklist(RV.getNode());
7019 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7020 N->getOperand(0), RV);
7022 } else if (N->getOperand(1).getOpcode() == ISD::FP_EXTEND &&
7023 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
7025 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
7027 if (RV.getNode() != 0) {
7028 DCI.AddToWorklist(RV.getNode());
7029 RV = DAG.getNode(ISD::FP_EXTEND, SDLoc(N->getOperand(1)),
7030 N->getValueType(0), RV);
7031 DCI.AddToWorklist(RV.getNode());
7032 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7033 N->getOperand(0), RV);
7035 } else if (N->getOperand(1).getOpcode() == ISD::FP_ROUND &&
7036 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
7038 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
7040 if (RV.getNode() != 0) {
7041 DCI.AddToWorklist(RV.getNode());
7042 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N->getOperand(1)),
7043 N->getValueType(0), RV,
7044 N->getOperand(1).getOperand(1));
7045 DCI.AddToWorklist(RV.getNode());
7046 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7047 N->getOperand(0), RV);
7051 SDValue RV = DAGCombineFastRecip(N->getOperand(1), DCI);
7052 if (RV.getNode() != 0) {
7053 DCI.AddToWorklist(RV.getNode());
7054 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7055 N->getOperand(0), RV);
7061 assert(TM.Options.UnsafeFPMath &&
7062 "Reciprocal estimates require UnsafeFPMath");
7064 // Compute this as 1/(1/sqrt(X)), which is the reciprocal of the
7066 SDValue RV = DAGCombineFastRecipFSQRT(N->getOperand(0), DCI);
7067 if (RV.getNode() != 0) {
7068 DCI.AddToWorklist(RV.getNode());
7069 RV = DAGCombineFastRecip(RV, DCI);
7070 if (RV.getNode() != 0) {
7071 // Unfortunately, RV is now NaN if the input was exactly 0. Select out
7072 // this case and force the answer to 0.
7074 EVT VT = RV.getValueType();
7076 SDValue Zero = DAG.getConstantFP(0.0, VT.getScalarType());
7077 if (VT.isVector()) {
7078 assert(VT.getVectorNumElements() == 4 && "Unknown vector type");
7079 Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Zero, Zero, Zero, Zero);
7083 DAG.getSetCC(dl, getSetCCResultType(*DAG.getContext(), VT),
7084 N->getOperand(0), Zero, ISD::SETEQ);
7085 DCI.AddToWorklist(ZeroCmp.getNode());
7086 DCI.AddToWorklist(RV.getNode());
7088 RV = DAG.getNode(VT.isVector() ? ISD::VSELECT : ISD::SELECT, dl, VT,
7096 case ISD::SINT_TO_FP:
7097 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
7098 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
7099 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
7100 // We allow the src/dst to be either f32/f64, but the intermediate
7101 // type must be i64.
7102 if (N->getOperand(0).getValueType() == MVT::i64 &&
7103 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
7104 SDValue Val = N->getOperand(0).getOperand(0);
7105 if (Val.getValueType() == MVT::f32) {
7106 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
7107 DCI.AddToWorklist(Val.getNode());
7110 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
7111 DCI.AddToWorklist(Val.getNode());
7112 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
7113 DCI.AddToWorklist(Val.getNode());
7114 if (N->getValueType(0) == MVT::f32) {
7115 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
7116 DAG.getIntPtrConstant(0));
7117 DCI.AddToWorklist(Val.getNode());
7120 } else if (N->getOperand(0).getValueType() == MVT::i32) {
7121 // If the intermediate type is i32, we can avoid the load/store here
7128 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
7129 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
7130 !cast<StoreSDNode>(N)->isTruncatingStore() &&
7131 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
7132 N->getOperand(1).getValueType() == MVT::i32 &&
7133 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
7134 SDValue Val = N->getOperand(1).getOperand(0);
7135 if (Val.getValueType() == MVT::f32) {
7136 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
7137 DCI.AddToWorklist(Val.getNode());
7139 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
7140 DCI.AddToWorklist(Val.getNode());
7143 N->getOperand(0), Val, N->getOperand(2),
7144 DAG.getValueType(N->getOperand(1).getValueType())
7147 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
7148 DAG.getVTList(MVT::Other), Ops, array_lengthof(Ops),
7149 cast<StoreSDNode>(N)->getMemoryVT(),
7150 cast<StoreSDNode>(N)->getMemOperand());
7151 DCI.AddToWorklist(Val.getNode());
7155 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
7156 if (cast<StoreSDNode>(N)->isUnindexed() &&
7157 N->getOperand(1).getOpcode() == ISD::BSWAP &&
7158 N->getOperand(1).getNode()->hasOneUse() &&
7159 (N->getOperand(1).getValueType() == MVT::i32 ||
7160 N->getOperand(1).getValueType() == MVT::i16 ||
7161 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
7162 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
7163 N->getOperand(1).getValueType() == MVT::i64))) {
7164 SDValue BSwapOp = N->getOperand(1).getOperand(0);
7165 // Do an any-extend to 32-bits if this is a half-word input.
7166 if (BSwapOp.getValueType() == MVT::i16)
7167 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
7170 N->getOperand(0), BSwapOp, N->getOperand(2),
7171 DAG.getValueType(N->getOperand(1).getValueType())
7174 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
7175 Ops, array_lengthof(Ops),
7176 cast<StoreSDNode>(N)->getMemoryVT(),
7177 cast<StoreSDNode>(N)->getMemOperand());
7181 LoadSDNode *LD = cast<LoadSDNode>(N);
7182 EVT VT = LD->getValueType(0);
7183 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
7184 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
7185 if (ISD::isNON_EXTLoad(N) && VT.isVector() &&
7186 TM.getSubtarget<PPCSubtarget>().hasAltivec() &&
7187 (VT == MVT::v16i8 || VT == MVT::v8i16 ||
7188 VT == MVT::v4i32 || VT == MVT::v4f32) &&
7189 LD->getAlignment() < ABIAlignment) {
7190 // This is a type-legal unaligned Altivec load.
7191 SDValue Chain = LD->getChain();
7192 SDValue Ptr = LD->getBasePtr();
7194 // This implements the loading of unaligned vectors as described in
7195 // the venerable Apple Velocity Engine overview. Specifically:
7196 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
7197 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
7199 // The general idea is to expand a sequence of one or more unaligned
7200 // loads into a alignment-based permutation-control instruction (lvsl),
7201 // a series of regular vector loads (which always truncate their
7202 // input address to an aligned address), and a series of permutations.
7203 // The results of these permutations are the requested loaded values.
7204 // The trick is that the last "extra" load is not taken from the address
7205 // you might suspect (sizeof(vector) bytes after the last requested
7206 // load), but rather sizeof(vector) - 1 bytes after the last
7207 // requested vector. The point of this is to avoid a page fault if the
7208 // base address happened to be aligned. This works because if the base
7209 // address is aligned, then adding less than a full vector length will
7210 // cause the last vector in the sequence to be (re)loaded. Otherwise,
7211 // the next vector will be fetched as you might suspect was necessary.
7213 // We might be able to reuse the permutation generation from
7214 // a different base address offset from this one by an aligned amount.
7215 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
7216 // optimization later.
7217 SDValue PermCntl = BuildIntrinsicOp(Intrinsic::ppc_altivec_lvsl, Ptr,
7218 DAG, dl, MVT::v16i8);
7220 // Refine the alignment of the original load (a "new" load created here
7221 // which was identical to the first except for the alignment would be
7222 // merged with the existing node regardless).
7223 MachineFunction &MF = DAG.getMachineFunction();
7224 MachineMemOperand *MMO =
7225 MF.getMachineMemOperand(LD->getPointerInfo(),
7226 LD->getMemOperand()->getFlags(),
7227 LD->getMemoryVT().getStoreSize(),
7229 LD->refineAlignment(MMO);
7230 SDValue BaseLoad = SDValue(LD, 0);
7232 // Note that the value of IncOffset (which is provided to the next
7233 // load's pointer info offset value, and thus used to calculate the
7234 // alignment), and the value of IncValue (which is actually used to
7235 // increment the pointer value) are different! This is because we
7236 // require the next load to appear to be aligned, even though it
7237 // is actually offset from the base pointer by a lesser amount.
7238 int IncOffset = VT.getSizeInBits() / 8;
7239 int IncValue = IncOffset;
7241 // Walk (both up and down) the chain looking for another load at the real
7242 // (aligned) offset (the alignment of the other load does not matter in
7243 // this case). If found, then do not use the offset reduction trick, as
7244 // that will prevent the loads from being later combined (as they would
7245 // otherwise be duplicates).
7246 if (!findConsecutiveLoad(LD, DAG))
7249 SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
7250 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
7253 DAG.getLoad(VT, dl, Chain, Ptr,
7254 LD->getPointerInfo().getWithOffset(IncOffset),
7255 LD->isVolatile(), LD->isNonTemporal(),
7256 LD->isInvariant(), ABIAlignment);
7258 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
7259 BaseLoad.getValue(1), ExtraLoad.getValue(1));
7261 if (BaseLoad.getValueType() != MVT::v4i32)
7262 BaseLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, BaseLoad);
7264 if (ExtraLoad.getValueType() != MVT::v4i32)
7265 ExtraLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, ExtraLoad);
7267 SDValue Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
7268 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
7270 if (VT != MVT::v4i32)
7271 Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm);
7273 // Now we need to be really careful about how we update the users of the
7274 // original load. We cannot just call DCI.CombineTo (or
7275 // DAG.ReplaceAllUsesWith for that matter), because the load still has
7276 // uses created here (the permutation for example) that need to stay.
7277 SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
7279 SDUse &Use = UI.getUse();
7281 // Note: BaseLoad is checked here because it might not be N, but a
7283 if (User == Perm.getNode() || User == BaseLoad.getNode() ||
7284 User == TF.getNode() || Use.getResNo() > 1) {
7289 SDValue To = Use.getResNo() ? TF : Perm;
7292 SmallVector<SDValue, 8> Ops;
7293 for (SDNode::op_iterator O = User->op_begin(),
7294 OE = User->op_end(); O != OE; ++O) {
7301 DAG.UpdateNodeOperands(User, Ops.data(), Ops.size());
7304 return SDValue(N, 0);
7308 case ISD::INTRINSIC_WO_CHAIN:
7309 if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() ==
7310 Intrinsic::ppc_altivec_lvsl &&
7311 N->getOperand(1)->getOpcode() == ISD::ADD) {
7312 SDValue Add = N->getOperand(1);
7314 if (DAG.MaskedValueIsZero(Add->getOperand(1),
7315 APInt::getAllOnesValue(4 /* 16 byte alignment */).zext(
7316 Add.getValueType().getScalarType().getSizeInBits()))) {
7317 SDNode *BasePtr = Add->getOperand(0).getNode();
7318 for (SDNode::use_iterator UI = BasePtr->use_begin(),
7319 UE = BasePtr->use_end(); UI != UE; ++UI) {
7320 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
7321 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() ==
7322 Intrinsic::ppc_altivec_lvsl) {
7323 // We've found another LVSL, and this address if an aligned
7324 // multiple of that one. The results will be the same, so use the
7325 // one we've just found instead.
7327 return SDValue(*UI, 0);
7335 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
7336 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
7337 N->getOperand(0).hasOneUse() &&
7338 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
7339 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
7340 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
7341 N->getValueType(0) == MVT::i64))) {
7342 SDValue Load = N->getOperand(0);
7343 LoadSDNode *LD = cast<LoadSDNode>(Load);
7344 // Create the byte-swapping load.
7346 LD->getChain(), // Chain
7347 LD->getBasePtr(), // Ptr
7348 DAG.getValueType(N->getValueType(0)) // VT
7351 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
7352 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
7353 MVT::i64 : MVT::i32, MVT::Other),
7354 Ops, 3, LD->getMemoryVT(), LD->getMemOperand());
7356 // If this is an i16 load, insert the truncate.
7357 SDValue ResVal = BSLoad;
7358 if (N->getValueType(0) == MVT::i16)
7359 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
7361 // First, combine the bswap away. This makes the value produced by the
7363 DCI.CombineTo(N, ResVal);
7365 // Next, combine the load away, we give it a bogus result value but a real
7366 // chain result. The result value is dead because the bswap is dead.
7367 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
7369 // Return N so it doesn't get rechecked!
7370 return SDValue(N, 0);
7374 case PPCISD::VCMP: {
7375 // If a VCMPo node already exists with exactly the same operands as this
7376 // node, use its result instead of this node (VCMPo computes both a CR6 and
7377 // a normal output).
7379 if (!N->getOperand(0).hasOneUse() &&
7380 !N->getOperand(1).hasOneUse() &&
7381 !N->getOperand(2).hasOneUse()) {
7383 // Scan all of the users of the LHS, looking for VCMPo's that match.
7384 SDNode *VCMPoNode = 0;
7386 SDNode *LHSN = N->getOperand(0).getNode();
7387 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
7389 if (UI->getOpcode() == PPCISD::VCMPo &&
7390 UI->getOperand(1) == N->getOperand(1) &&
7391 UI->getOperand(2) == N->getOperand(2) &&
7392 UI->getOperand(0) == N->getOperand(0)) {
7397 // If there is no VCMPo node, or if the flag value has a single use, don't
7399 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
7402 // Look at the (necessarily single) use of the flag value. If it has a
7403 // chain, this transformation is more complex. Note that multiple things
7404 // could use the value result, which we should ignore.
7405 SDNode *FlagUser = 0;
7406 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
7407 FlagUser == 0; ++UI) {
7408 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
7410 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
7411 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
7418 // If the user is a MFOCRF instruction, we know this is safe.
7419 // Otherwise we give up for right now.
7420 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
7421 return SDValue(VCMPoNode, 0);
7426 // If this is a branch on an altivec predicate comparison, lower this so
7427 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
7428 // lowering is done pre-legalize, because the legalizer lowers the predicate
7429 // compare down to code that is difficult to reassemble.
7430 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
7431 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
7433 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
7434 // value. If so, pass-through the AND to get to the intrinsic.
7435 if (LHS.getOpcode() == ISD::AND &&
7436 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
7437 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
7438 Intrinsic::ppc_is_decremented_ctr_nonzero &&
7439 isa<ConstantSDNode>(LHS.getOperand(1)) &&
7440 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
7442 LHS = LHS.getOperand(0);
7444 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
7445 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
7446 Intrinsic::ppc_is_decremented_ctr_nonzero &&
7447 isa<ConstantSDNode>(RHS)) {
7448 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
7449 "Counter decrement comparison is not EQ or NE");
7451 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
7452 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
7453 (CC == ISD::SETNE && !Val);
7455 // We now need to make the intrinsic dead (it cannot be instruction
7457 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
7458 assert(LHS.getNode()->hasOneUse() &&
7459 "Counter decrement has more than one use");
7461 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
7462 N->getOperand(0), N->getOperand(4));
7468 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
7469 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
7470 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
7471 assert(isDot && "Can't compare against a vector result!");
7473 // If this is a comparison against something other than 0/1, then we know
7474 // that the condition is never/always true.
7475 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
7476 if (Val != 0 && Val != 1) {
7477 if (CC == ISD::SETEQ) // Cond never true, remove branch.
7478 return N->getOperand(0);
7479 // Always !=, turn it into an unconditional branch.
7480 return DAG.getNode(ISD::BR, dl, MVT::Other,
7481 N->getOperand(0), N->getOperand(4));
7484 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
7486 // Create the PPCISD altivec 'dot' comparison node.
7488 LHS.getOperand(2), // LHS of compare
7489 LHS.getOperand(3), // RHS of compare
7490 DAG.getConstant(CompareOpc, MVT::i32)
7492 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
7493 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
7495 // Unpack the result based on how the target uses it.
7496 PPC::Predicate CompOpc;
7497 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
7498 default: // Can't happen, don't crash on invalid number though.
7499 case 0: // Branch on the value of the EQ bit of CR6.
7500 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
7502 case 1: // Branch on the inverted value of the EQ bit of CR6.
7503 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
7505 case 2: // Branch on the value of the LT bit of CR6.
7506 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
7508 case 3: // Branch on the inverted value of the LT bit of CR6.
7509 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
7513 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
7514 DAG.getConstant(CompOpc, MVT::i32),
7515 DAG.getRegister(PPC::CR6, MVT::i32),
7516 N->getOperand(4), CompNode.getValue(1));
7525 //===----------------------------------------------------------------------===//
7526 // Inline Assembly Support
7527 //===----------------------------------------------------------------------===//
7529 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
7532 const SelectionDAG &DAG,
7533 unsigned Depth) const {
7534 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
7535 switch (Op.getOpcode()) {
7537 case PPCISD::LBRX: {
7538 // lhbrx is known to have the top bits cleared out.
7539 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
7540 KnownZero = 0xFFFF0000;
7543 case ISD::INTRINSIC_WO_CHAIN: {
7544 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
7546 case Intrinsic::ppc_altivec_vcmpbfp_p:
7547 case Intrinsic::ppc_altivec_vcmpeqfp_p:
7548 case Intrinsic::ppc_altivec_vcmpequb_p:
7549 case Intrinsic::ppc_altivec_vcmpequh_p:
7550 case Intrinsic::ppc_altivec_vcmpequw_p:
7551 case Intrinsic::ppc_altivec_vcmpgefp_p:
7552 case Intrinsic::ppc_altivec_vcmpgtfp_p:
7553 case Intrinsic::ppc_altivec_vcmpgtsb_p:
7554 case Intrinsic::ppc_altivec_vcmpgtsh_p:
7555 case Intrinsic::ppc_altivec_vcmpgtsw_p:
7556 case Intrinsic::ppc_altivec_vcmpgtub_p:
7557 case Intrinsic::ppc_altivec_vcmpgtuh_p:
7558 case Intrinsic::ppc_altivec_vcmpgtuw_p:
7559 KnownZero = ~1U; // All bits but the low one are known to be zero.
7567 /// getConstraintType - Given a constraint, return the type of
7568 /// constraint it is for this target.
7569 PPCTargetLowering::ConstraintType
7570 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
7571 if (Constraint.size() == 1) {
7572 switch (Constraint[0]) {
7579 return C_RegisterClass;
7581 // FIXME: While Z does indicate a memory constraint, it specifically
7582 // indicates an r+r address (used in conjunction with the 'y' modifier
7583 // in the replacement string). Currently, we're forcing the base
7584 // register to be r0 in the asm printer (which is interpreted as zero)
7585 // and forming the complete address in the second register. This is
7590 return TargetLowering::getConstraintType(Constraint);
7593 /// Examine constraint type and operand type and determine a weight value.
7594 /// This object must already have been set up with the operand type
7595 /// and the current alternative constraint selected.
7596 TargetLowering::ConstraintWeight
7597 PPCTargetLowering::getSingleConstraintMatchWeight(
7598 AsmOperandInfo &info, const char *constraint) const {
7599 ConstraintWeight weight = CW_Invalid;
7600 Value *CallOperandVal = info.CallOperandVal;
7601 // If we don't have a value, we can't do a match,
7602 // but allow it at the lowest weight.
7603 if (CallOperandVal == NULL)
7605 Type *type = CallOperandVal->getType();
7606 // Look at the constraint type.
7607 switch (*constraint) {
7609 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
7612 if (type->isIntegerTy())
7613 weight = CW_Register;
7616 if (type->isFloatTy())
7617 weight = CW_Register;
7620 if (type->isDoubleTy())
7621 weight = CW_Register;
7624 if (type->isVectorTy())
7625 weight = CW_Register;
7628 weight = CW_Register;
7637 std::pair<unsigned, const TargetRegisterClass*>
7638 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
7640 if (Constraint.size() == 1) {
7641 // GCC RS6000 Constraint Letters
7642 switch (Constraint[0]) {
7644 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
7645 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
7646 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
7648 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
7649 return std::make_pair(0U, &PPC::G8RCRegClass);
7650 return std::make_pair(0U, &PPC::GPRCRegClass);
7652 if (VT == MVT::f32 || VT == MVT::i32)
7653 return std::make_pair(0U, &PPC::F4RCRegClass);
7654 if (VT == MVT::f64 || VT == MVT::i64)
7655 return std::make_pair(0U, &PPC::F8RCRegClass);
7658 return std::make_pair(0U, &PPC::VRRCRegClass);
7660 return std::make_pair(0U, &PPC::CRRCRegClass);
7664 std::pair<unsigned, const TargetRegisterClass*> R =
7665 TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
7667 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
7668 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
7669 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
7671 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
7672 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
7673 if (R.first && VT == MVT::i64 && PPCSubTarget.isPPC64() &&
7674 PPC::GPRCRegClass.contains(R.first)) {
7675 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
7676 return std::make_pair(TRI->getMatchingSuperReg(R.first,
7677 PPC::sub_32, &PPC::G8RCRegClass),
7678 &PPC::G8RCRegClass);
7685 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
7686 /// vector. If it is invalid, don't add anything to Ops.
7687 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
7688 std::string &Constraint,
7689 std::vector<SDValue>&Ops,
7690 SelectionDAG &DAG) const {
7691 SDValue Result(0,0);
7693 // Only support length 1 constraints.
7694 if (Constraint.length() > 1) return;
7696 char Letter = Constraint[0];
7707 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
7708 if (!CST) return; // Must be an immediate to match.
7709 unsigned Value = CST->getZExtValue();
7711 default: llvm_unreachable("Unknown constraint letter!");
7712 case 'I': // "I" is a signed 16-bit constant.
7713 if ((short)Value == (int)Value)
7714 Result = DAG.getTargetConstant(Value, Op.getValueType());
7716 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
7717 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
7718 if ((short)Value == 0)
7719 Result = DAG.getTargetConstant(Value, Op.getValueType());
7721 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
7722 if ((Value >> 16) == 0)
7723 Result = DAG.getTargetConstant(Value, Op.getValueType());
7725 case 'M': // "M" is a constant that is greater than 31.
7727 Result = DAG.getTargetConstant(Value, Op.getValueType());
7729 case 'N': // "N" is a positive constant that is an exact power of two.
7730 if ((int)Value > 0 && isPowerOf2_32(Value))
7731 Result = DAG.getTargetConstant(Value, Op.getValueType());
7733 case 'O': // "O" is the constant zero.
7735 Result = DAG.getTargetConstant(Value, Op.getValueType());
7737 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
7738 if ((short)-Value == (int)-Value)
7739 Result = DAG.getTargetConstant(Value, Op.getValueType());
7746 if (Result.getNode()) {
7747 Ops.push_back(Result);
7751 // Handle standard constraint letters.
7752 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
7755 // isLegalAddressingMode - Return true if the addressing mode represented
7756 // by AM is legal for this target, for a load/store of the specified type.
7757 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
7759 // FIXME: PPC does not allow r+i addressing modes for vectors!
7761 // PPC allows a sign-extended 16-bit immediate field.
7762 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
7765 // No global is ever allowed as a base.
7769 // PPC only support r+r,
7771 case 0: // "r+i" or just "i", depending on HasBaseReg.
7774 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
7776 // Otherwise we have r+r or r+i.
7779 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
7781 // Allow 2*r as r+r.
7784 // No other scales are supported.
7791 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
7792 SelectionDAG &DAG) const {
7793 MachineFunction &MF = DAG.getMachineFunction();
7794 MachineFrameInfo *MFI = MF.getFrameInfo();
7795 MFI->setReturnAddressIsTaken(true);
7797 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
7801 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7803 // Make sure the function does not optimize away the store of the RA to
7805 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
7806 FuncInfo->setLRStoreRequired();
7807 bool isPPC64 = PPCSubTarget.isPPC64();
7808 bool isDarwinABI = PPCSubTarget.isDarwinABI();
7811 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
7814 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
7815 isPPC64? MVT::i64 : MVT::i32);
7816 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7817 DAG.getNode(ISD::ADD, dl, getPointerTy(),
7819 MachinePointerInfo(), false, false, false, 0);
7822 // Just load the return address off the stack.
7823 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
7824 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7825 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
7828 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
7829 SelectionDAG &DAG) const {
7831 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7833 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
7834 bool isPPC64 = PtrVT == MVT::i64;
7836 MachineFunction &MF = DAG.getMachineFunction();
7837 MachineFrameInfo *MFI = MF.getFrameInfo();
7838 MFI->setFrameAddressIsTaken(true);
7840 // Naked functions never have a frame pointer, and so we use r1. For all
7841 // other functions, this decision must be delayed until during PEI.
7843 if (MF.getFunction()->getAttributes().hasAttribute(
7844 AttributeSet::FunctionIndex, Attribute::Naked))
7845 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
7847 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
7849 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
7852 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
7853 FrameAddr, MachinePointerInfo(), false, false,
7859 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
7860 // The PowerPC target isn't yet aware of offsets.
7864 /// getOptimalMemOpType - Returns the target specific optimal type for load
7865 /// and store operations as a result of memset, memcpy, and memmove
7866 /// lowering. If DstAlign is zero that means it's safe to destination
7867 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
7868 /// means there isn't a need to check it against alignment requirement,
7869 /// probably because the source does not need to be loaded. If 'IsMemset' is
7870 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
7871 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
7872 /// source is constant so it does not need to be loaded.
7873 /// It returns EVT::Other if the type should be determined using generic
7874 /// target-independent logic.
7875 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
7876 unsigned DstAlign, unsigned SrcAlign,
7877 bool IsMemset, bool ZeroMemset,
7879 MachineFunction &MF) const {
7880 if (this->PPCSubTarget.isPPC64()) {
7887 bool PPCTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
7890 if (DisablePPCUnaligned)
7893 // PowerPC supports unaligned memory access for simple non-vector types.
7894 // Although accessing unaligned addresses is not as efficient as accessing
7895 // aligned addresses, it is generally more efficient than manual expansion,
7896 // and generally only traps for software emulation when crossing page
7902 if (VT.getSimpleVT().isVector())
7905 if (VT == MVT::ppcf128)
7914 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
7915 VT = VT.getScalarType();
7920 switch (VT.getSimpleVT().SimpleTy) {
7931 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
7932 if (DisableILPPref || PPCSubTarget.enableMachineScheduler())
7933 return TargetLowering::getSchedulingPreference(N);
7938 // Create a fast isel object.
7940 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
7941 const TargetLibraryInfo *LibInfo) const {
7942 return PPC::createFastISel(FuncInfo, LibInfo);