1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPerfectShuffle.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCTargetObjectFile.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28 #include "llvm/IR/CallingConv.h"
29 #include "llvm/IR/Constants.h"
30 #include "llvm/IR/DerivedTypes.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/Intrinsics.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/Target/TargetOptions.h"
40 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
41 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
43 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
44 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
46 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
47 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
49 static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) {
50 if (TM.getSubtargetImpl()->isDarwin())
51 return new TargetLoweringObjectFileMachO();
53 if (TM.getSubtargetImpl()->isSVR4ABI())
54 return new PPC64LinuxTargetObjectFile();
56 return new TargetLoweringObjectFileELF();
59 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
60 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) {
61 const PPCSubtarget *Subtarget = &TM.getSubtarget<PPCSubtarget>();
65 // Use _setjmp/_longjmp instead of setjmp/longjmp.
66 setUseUnderscoreSetJmp(true);
67 setUseUnderscoreLongJmp(true);
69 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
70 // arguments are at least 4/8 bytes aligned.
71 bool isPPC64 = Subtarget->isPPC64();
72 setMinStackArgumentAlignment(isPPC64 ? 8:4);
74 // Set up the register classes.
75 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
76 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
77 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
79 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
80 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
81 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
83 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
85 // PowerPC has pre-inc load and store's.
86 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
87 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
91 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
92 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
93 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
97 // This is used in the ppcf128->int sequence. Note it has different semantics
98 // from FP_ROUND: that rounds to nearest, this rounds to zero.
99 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
101 // We do not currently implement these libm ops for PowerPC.
102 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
103 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
104 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
105 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
106 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
107 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
109 // PowerPC has no SREM/UREM instructions
110 setOperationAction(ISD::SREM, MVT::i32, Expand);
111 setOperationAction(ISD::UREM, MVT::i32, Expand);
112 setOperationAction(ISD::SREM, MVT::i64, Expand);
113 setOperationAction(ISD::UREM, MVT::i64, Expand);
115 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
116 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
117 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
118 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
119 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
120 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
121 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
122 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
123 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
125 // We don't support sin/cos/sqrt/fmod/pow
126 setOperationAction(ISD::FSIN , MVT::f64, Expand);
127 setOperationAction(ISD::FCOS , MVT::f64, Expand);
128 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
129 setOperationAction(ISD::FREM , MVT::f64, Expand);
130 setOperationAction(ISD::FPOW , MVT::f64, Expand);
131 setOperationAction(ISD::FMA , MVT::f64, Legal);
132 setOperationAction(ISD::FSIN , MVT::f32, Expand);
133 setOperationAction(ISD::FCOS , MVT::f32, Expand);
134 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
135 setOperationAction(ISD::FREM , MVT::f32, Expand);
136 setOperationAction(ISD::FPOW , MVT::f32, Expand);
137 setOperationAction(ISD::FMA , MVT::f32, Legal);
139 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
141 // If we're enabling GP optimizations, use hardware square root
142 if (!Subtarget->hasFSQRT() &&
143 !(TM.Options.UnsafeFPMath &&
144 Subtarget->hasFRSQRTE() && Subtarget->hasFRE()))
145 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
147 if (!Subtarget->hasFSQRT() &&
148 !(TM.Options.UnsafeFPMath &&
149 Subtarget->hasFRSQRTES() && Subtarget->hasFRES()))
150 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
152 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
153 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
155 if (Subtarget->hasFPRND()) {
156 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
157 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
158 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
160 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
161 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
162 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
164 // frin does not implement "ties to even." Thus, this is safe only in
166 if (TM.Options.UnsafeFPMath) {
167 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
168 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
170 // These need to set FE_INEXACT, and use a custom inserter.
171 setOperationAction(ISD::FRINT, MVT::f64, Legal);
172 setOperationAction(ISD::FRINT, MVT::f32, Legal);
176 // PowerPC does not have BSWAP, CTPOP or CTTZ
177 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
178 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
179 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
180 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
181 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
182 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
183 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
184 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
186 if (Subtarget->hasPOPCNTD()) {
187 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
188 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
190 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
191 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
194 // PowerPC does not have ROTR
195 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
196 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
198 // PowerPC does not have Select
199 setOperationAction(ISD::SELECT, MVT::i32, Expand);
200 setOperationAction(ISD::SELECT, MVT::i64, Expand);
201 setOperationAction(ISD::SELECT, MVT::f32, Expand);
202 setOperationAction(ISD::SELECT, MVT::f64, Expand);
204 // PowerPC wants to turn select_cc of FP into fsel when possible.
205 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
206 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
208 // PowerPC wants to optimize integer setcc a bit
209 setOperationAction(ISD::SETCC, MVT::i32, Custom);
211 // PowerPC does not have BRCOND which requires SetCC
212 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
214 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
216 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
217 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
219 // PowerPC does not have [U|S]INT_TO_FP
220 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
221 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
223 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
224 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
225 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
226 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
228 // We cannot sextinreg(i1). Expand to shifts.
229 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
231 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
232 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
233 // support continuation, user-level threading, and etc.. As a result, no
234 // other SjLj exception interfaces are implemented and please don't build
235 // your own exception handling based on them.
236 // LLVM/Clang supports zero-cost DWARF exception handling.
237 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
238 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
240 // We want to legalize GlobalAddress and ConstantPool nodes into the
241 // appropriate instructions to materialize the address.
242 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
243 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
244 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
245 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
246 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
247 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
248 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
249 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
250 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
251 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
254 setOperationAction(ISD::TRAP, MVT::Other, Legal);
256 // TRAMPOLINE is custom lowered.
257 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
258 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
260 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
261 setOperationAction(ISD::VASTART , MVT::Other, Custom);
263 if (Subtarget->isSVR4ABI()) {
265 // VAARG always uses double-word chunks, so promote anything smaller.
266 setOperationAction(ISD::VAARG, MVT::i1, Promote);
267 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
268 setOperationAction(ISD::VAARG, MVT::i8, Promote);
269 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
270 setOperationAction(ISD::VAARG, MVT::i16, Promote);
271 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
272 setOperationAction(ISD::VAARG, MVT::i32, Promote);
273 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
274 setOperationAction(ISD::VAARG, MVT::Other, Expand);
276 // VAARG is custom lowered with the 32-bit SVR4 ABI.
277 setOperationAction(ISD::VAARG, MVT::Other, Custom);
278 setOperationAction(ISD::VAARG, MVT::i64, Custom);
281 setOperationAction(ISD::VAARG, MVT::Other, Expand);
283 // Use the default implementation.
284 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
285 setOperationAction(ISD::VAEND , MVT::Other, Expand);
286 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
287 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
288 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
289 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
291 // We want to custom lower some of our intrinsics.
292 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
294 // To handle counter-based loop conditions.
295 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
297 // Comparisons that require checking two conditions.
298 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
299 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
300 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
301 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
302 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
303 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
304 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
305 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
306 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
307 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
308 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
309 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
311 if (Subtarget->has64BitSupport()) {
312 // They also have instructions for converting between i64 and fp.
313 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
314 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
315 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
316 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
317 // This is just the low 32 bits of a (signed) fp->i64 conversion.
318 // We cannot do this with Promote because i64 is not a legal type.
319 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
321 if (PPCSubTarget.hasLFIWAX() || Subtarget->isPPC64())
322 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
324 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
325 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
328 // With the instructions enabled under FPCVT, we can do everything.
329 if (PPCSubTarget.hasFPCVT()) {
330 if (Subtarget->has64BitSupport()) {
331 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
332 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
333 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
334 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
337 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
338 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
339 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
340 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
343 if (Subtarget->use64BitRegs()) {
344 // 64-bit PowerPC implementations can support i64 types directly
345 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
346 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
347 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
348 // 64-bit PowerPC wants to expand i128 shifts itself.
349 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
350 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
351 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
353 // 32-bit PowerPC wants to expand i64 shifts itself.
354 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
355 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
356 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
359 if (Subtarget->hasAltivec()) {
360 // First set operation action for all vector types to expand. Then we
361 // will selectively turn on ones that can be effectively codegen'd.
362 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
363 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
364 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
366 // add/sub are legal for all supported vector VT's.
367 setOperationAction(ISD::ADD , VT, Legal);
368 setOperationAction(ISD::SUB , VT, Legal);
370 // We promote all shuffles to v16i8.
371 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
372 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
374 // We promote all non-typed operations to v4i32.
375 setOperationAction(ISD::AND , VT, Promote);
376 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
377 setOperationAction(ISD::OR , VT, Promote);
378 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
379 setOperationAction(ISD::XOR , VT, Promote);
380 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
381 setOperationAction(ISD::LOAD , VT, Promote);
382 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
383 setOperationAction(ISD::SELECT, VT, Promote);
384 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
385 setOperationAction(ISD::STORE, VT, Promote);
386 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
388 // No other operations are legal.
389 setOperationAction(ISD::MUL , VT, Expand);
390 setOperationAction(ISD::SDIV, VT, Expand);
391 setOperationAction(ISD::SREM, VT, Expand);
392 setOperationAction(ISD::UDIV, VT, Expand);
393 setOperationAction(ISD::UREM, VT, Expand);
394 setOperationAction(ISD::FDIV, VT, Expand);
395 setOperationAction(ISD::FNEG, VT, Expand);
396 setOperationAction(ISD::FSQRT, VT, Expand);
397 setOperationAction(ISD::FLOG, VT, Expand);
398 setOperationAction(ISD::FLOG10, VT, Expand);
399 setOperationAction(ISD::FLOG2, VT, Expand);
400 setOperationAction(ISD::FEXP, VT, Expand);
401 setOperationAction(ISD::FEXP2, VT, Expand);
402 setOperationAction(ISD::FSIN, VT, Expand);
403 setOperationAction(ISD::FCOS, VT, Expand);
404 setOperationAction(ISD::FABS, VT, Expand);
405 setOperationAction(ISD::FPOWI, VT, Expand);
406 setOperationAction(ISD::FFLOOR, VT, Expand);
407 setOperationAction(ISD::FCEIL, VT, Expand);
408 setOperationAction(ISD::FTRUNC, VT, Expand);
409 setOperationAction(ISD::FRINT, VT, Expand);
410 setOperationAction(ISD::FNEARBYINT, VT, Expand);
411 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
412 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
413 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
414 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
415 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
416 setOperationAction(ISD::UDIVREM, VT, Expand);
417 setOperationAction(ISD::SDIVREM, VT, Expand);
418 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
419 setOperationAction(ISD::FPOW, VT, Expand);
420 setOperationAction(ISD::CTPOP, VT, Expand);
421 setOperationAction(ISD::CTLZ, VT, Expand);
422 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
423 setOperationAction(ISD::CTTZ, VT, Expand);
424 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
425 setOperationAction(ISD::VSELECT, VT, Expand);
426 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
428 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
429 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
430 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
431 setTruncStoreAction(VT, InnerVT, Expand);
433 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
434 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
435 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
438 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
439 // with merges, splats, etc.
440 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
442 setOperationAction(ISD::AND , MVT::v4i32, Legal);
443 setOperationAction(ISD::OR , MVT::v4i32, Legal);
444 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
445 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
446 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
447 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
448 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
449 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
450 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
451 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
452 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
453 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
454 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
455 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
457 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
458 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
459 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
460 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
462 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
463 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
465 if (TM.Options.UnsafeFPMath) {
466 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
467 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
470 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
471 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
472 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
474 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
475 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
477 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
478 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
479 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
480 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
482 // Altivec does not contain unordered floating-point compare instructions
483 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
484 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
485 setCondCodeAction(ISD::SETUGT, MVT::v4f32, Expand);
486 setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand);
487 setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand);
488 setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand);
491 if (Subtarget->has64BitSupport()) {
492 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
493 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
496 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
497 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
498 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
499 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
501 setBooleanContents(ZeroOrOneBooleanContent);
502 // Altivec instructions set fields to all zeros or all ones.
503 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
506 setStackPointerRegisterToSaveRestore(PPC::X1);
507 setExceptionPointerRegister(PPC::X3);
508 setExceptionSelectorRegister(PPC::X4);
510 setStackPointerRegisterToSaveRestore(PPC::R1);
511 setExceptionPointerRegister(PPC::R3);
512 setExceptionSelectorRegister(PPC::R4);
515 // We have target-specific dag combine patterns for the following nodes:
516 setTargetDAGCombine(ISD::SINT_TO_FP);
517 setTargetDAGCombine(ISD::LOAD);
518 setTargetDAGCombine(ISD::STORE);
519 setTargetDAGCombine(ISD::BR_CC);
520 setTargetDAGCombine(ISD::BSWAP);
521 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
523 // Use reciprocal estimates.
524 if (TM.Options.UnsafeFPMath) {
525 setTargetDAGCombine(ISD::FDIV);
526 setTargetDAGCombine(ISD::FSQRT);
529 // Darwin long double math library functions have $LDBL128 appended.
530 if (Subtarget->isDarwin()) {
531 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
532 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
533 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
534 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
535 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
536 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
537 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
538 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
539 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
540 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
543 setMinFunctionAlignment(2);
544 if (PPCSubTarget.isDarwin())
545 setPrefFunctionAlignment(4);
547 if (isPPC64 && Subtarget->isJITCodeModel())
548 // Temporary workaround for the inability of PPC64 JIT to handle jump
550 setSupportJumpTables(false);
552 setInsertFencesForAtomic(true);
554 setSchedulingPreference(Sched::Hybrid);
556 computeRegisterProperties();
558 // The Freescale cores does better with aggressive inlining of memcpy and
559 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores).
560 if (Subtarget->getDarwinDirective() == PPC::DIR_E500mc ||
561 Subtarget->getDarwinDirective() == PPC::DIR_E5500) {
562 MaxStoresPerMemset = 32;
563 MaxStoresPerMemsetOptSize = 16;
564 MaxStoresPerMemcpy = 32;
565 MaxStoresPerMemcpyOptSize = 8;
566 MaxStoresPerMemmove = 32;
567 MaxStoresPerMemmoveOptSize = 8;
569 setPrefFunctionAlignment(4);
573 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
574 /// function arguments in the caller parameter area.
575 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
576 const TargetMachine &TM = getTargetMachine();
577 // Darwin passes everything on 4 byte boundary.
578 if (TM.getSubtarget<PPCSubtarget>().isDarwin())
581 // 16byte and wider vectors are passed on 16byte boundary.
582 if (VectorType *VTy = dyn_cast<VectorType>(Ty))
583 if (VTy->getBitWidth() >= 128)
586 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
587 if (PPCSubTarget.isPPC64())
593 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
596 case PPCISD::FSEL: return "PPCISD::FSEL";
597 case PPCISD::FCFID: return "PPCISD::FCFID";
598 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
599 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
600 case PPCISD::FRE: return "PPCISD::FRE";
601 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
602 case PPCISD::STFIWX: return "PPCISD::STFIWX";
603 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
604 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
605 case PPCISD::VPERM: return "PPCISD::VPERM";
606 case PPCISD::Hi: return "PPCISD::Hi";
607 case PPCISD::Lo: return "PPCISD::Lo";
608 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
609 case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE";
610 case PPCISD::LOAD: return "PPCISD::LOAD";
611 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
612 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
613 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
614 case PPCISD::SRL: return "PPCISD::SRL";
615 case PPCISD::SRA: return "PPCISD::SRA";
616 case PPCISD::SHL: return "PPCISD::SHL";
617 case PPCISD::CALL: return "PPCISD::CALL";
618 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
619 case PPCISD::MTCTR: return "PPCISD::MTCTR";
620 case PPCISD::BCTRL: return "PPCISD::BCTRL";
621 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
622 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
623 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
624 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
625 case PPCISD::VCMP: return "PPCISD::VCMP";
626 case PPCISD::VCMPo: return "PPCISD::VCMPo";
627 case PPCISD::LBRX: return "PPCISD::LBRX";
628 case PPCISD::STBRX: return "PPCISD::STBRX";
629 case PPCISD::LARX: return "PPCISD::LARX";
630 case PPCISD::STCX: return "PPCISD::STCX";
631 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
632 case PPCISD::BDNZ: return "PPCISD::BDNZ";
633 case PPCISD::BDZ: return "PPCISD::BDZ";
634 case PPCISD::MFFS: return "PPCISD::MFFS";
635 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
636 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
637 case PPCISD::CR6SET: return "PPCISD::CR6SET";
638 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
639 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
640 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
641 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
642 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
643 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
644 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
645 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
646 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
647 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
648 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
649 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
650 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
651 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
652 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
653 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
654 case PPCISD::SC: return "PPCISD::SC";
658 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
661 return VT.changeVectorElementTypeToInteger();
664 //===----------------------------------------------------------------------===//
665 // Node matching predicates, for use by the tblgen matching code.
666 //===----------------------------------------------------------------------===//
668 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
669 static bool isFloatingPointZero(SDValue Op) {
670 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
671 return CFP->getValueAPF().isZero();
672 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
673 // Maybe this has already been legalized into the constant pool?
674 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
675 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
676 return CFP->getValueAPF().isZero();
681 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
682 /// true if Op is undef or if it matches the specified value.
683 static bool isConstantOrUndef(int Op, int Val) {
684 return Op < 0 || Op == Val;
687 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
688 /// VPKUHUM instruction.
689 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
691 for (unsigned i = 0; i != 16; ++i)
692 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
695 for (unsigned i = 0; i != 8; ++i)
696 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) ||
697 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1))
703 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
704 /// VPKUWUM instruction.
705 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
707 for (unsigned i = 0; i != 16; i += 2)
708 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
709 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
712 for (unsigned i = 0; i != 8; i += 2)
713 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
714 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) ||
715 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) ||
716 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3))
722 /// isVMerge - Common function, used to match vmrg* shuffles.
724 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
725 unsigned LHSStart, unsigned RHSStart) {
726 assert(N->getValueType(0) == MVT::v16i8 &&
727 "PPC only supports shuffles by bytes!");
728 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
729 "Unsupported merge size!");
731 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
732 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
733 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
734 LHSStart+j+i*UnitSize) ||
735 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
736 RHSStart+j+i*UnitSize))
742 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
743 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
744 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
747 return isVMerge(N, UnitSize, 8, 24);
748 return isVMerge(N, UnitSize, 8, 8);
751 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
752 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
753 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
756 return isVMerge(N, UnitSize, 0, 16);
757 return isVMerge(N, UnitSize, 0, 0);
761 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
762 /// amount, otherwise return -1.
763 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
764 assert(N->getValueType(0) == MVT::v16i8 &&
765 "PPC only supports shuffles by bytes!");
767 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
769 // Find the first non-undef value in the shuffle mask.
771 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
774 if (i == 16) return -1; // all undef.
776 // Otherwise, check to see if the rest of the elements are consecutively
777 // numbered from this value.
778 unsigned ShiftAmt = SVOp->getMaskElt(i);
779 if (ShiftAmt < i) return -1;
783 // Check the rest of the elements to see if they are consecutive.
784 for (++i; i != 16; ++i)
785 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
788 // Check the rest of the elements to see if they are consecutive.
789 for (++i; i != 16; ++i)
790 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
796 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
797 /// specifies a splat of a single element that is suitable for input to
798 /// VSPLTB/VSPLTH/VSPLTW.
799 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
800 assert(N->getValueType(0) == MVT::v16i8 &&
801 (EltSize == 1 || EltSize == 2 || EltSize == 4));
803 // This is a splat operation if each element of the permute is the same, and
804 // if the value doesn't reference the second vector.
805 unsigned ElementBase = N->getMaskElt(0);
807 // FIXME: Handle UNDEF elements too!
808 if (ElementBase >= 16)
811 // Check that the indices are consecutive, in the case of a multi-byte element
812 // splatted with a v16i8 mask.
813 for (unsigned i = 1; i != EltSize; ++i)
814 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
817 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
818 if (N->getMaskElt(i) < 0) continue;
819 for (unsigned j = 0; j != EltSize; ++j)
820 if (N->getMaskElt(i+j) != N->getMaskElt(j))
826 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
828 bool PPC::isAllNegativeZeroVector(SDNode *N) {
829 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
831 APInt APVal, APUndef;
835 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
836 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
837 return CFP->getValueAPF().isNegZero();
842 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
843 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
844 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
845 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
846 assert(isSplatShuffleMask(SVOp, EltSize));
847 return SVOp->getMaskElt(0) / EltSize;
850 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
851 /// by using a vspltis[bhw] instruction of the specified element size, return
852 /// the constant being splatted. The ByteSize field indicates the number of
853 /// bytes of each element [124] -> [bhw].
854 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
857 // If ByteSize of the splat is bigger than the element size of the
858 // build_vector, then we have a case where we are checking for a splat where
859 // multiple elements of the buildvector are folded together into a single
860 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
861 unsigned EltSize = 16/N->getNumOperands();
862 if (EltSize < ByteSize) {
863 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
864 SDValue UniquedVals[4];
865 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
867 // See if all of the elements in the buildvector agree across.
868 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
869 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
870 // If the element isn't a constant, bail fully out.
871 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
874 if (UniquedVals[i&(Multiple-1)].getNode() == 0)
875 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
876 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
877 return SDValue(); // no match.
880 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
881 // either constant or undef values that are identical for each chunk. See
882 // if these chunks can form into a larger vspltis*.
884 // Check to see if all of the leading entries are either 0 or -1. If
885 // neither, then this won't fit into the immediate field.
886 bool LeadingZero = true;
887 bool LeadingOnes = true;
888 for (unsigned i = 0; i != Multiple-1; ++i) {
889 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs.
891 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
892 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
894 // Finally, check the least significant entry.
896 if (UniquedVals[Multiple-1].getNode() == 0)
897 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
898 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
900 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
903 if (UniquedVals[Multiple-1].getNode() == 0)
904 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
905 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
906 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
907 return DAG.getTargetConstant(Val, MVT::i32);
913 // Check to see if this buildvec has a single non-undef value in its elements.
914 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
915 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
916 if (OpVal.getNode() == 0)
917 OpVal = N->getOperand(i);
918 else if (OpVal != N->getOperand(i))
922 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def.
924 unsigned ValSizeInBytes = EltSize;
926 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
927 Value = CN->getZExtValue();
928 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
929 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
930 Value = FloatToBits(CN->getValueAPF().convertToFloat());
933 // If the splat value is larger than the element value, then we can never do
934 // this splat. The only case that we could fit the replicated bits into our
935 // immediate field for would be zero, and we prefer to use vxor for it.
936 if (ValSizeInBytes < ByteSize) return SDValue();
938 // If the element value is larger than the splat value, cut it in half and
939 // check to see if the two halves are equal. Continue doing this until we
940 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
941 while (ValSizeInBytes > ByteSize) {
942 ValSizeInBytes >>= 1;
944 // If the top half equals the bottom half, we're still ok.
945 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
946 (Value & ((1 << (8*ValSizeInBytes))-1)))
950 // Properly sign extend the value.
951 int MaskVal = SignExtend32(Value, ByteSize * 8);
953 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
954 if (MaskVal == 0) return SDValue();
956 // Finally, if this value fits in a 5 bit sext field, return it
957 if (SignExtend32<5>(MaskVal) == MaskVal)
958 return DAG.getTargetConstant(MaskVal, MVT::i32);
962 //===----------------------------------------------------------------------===//
963 // Addressing Mode Selection
964 //===----------------------------------------------------------------------===//
966 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
967 /// or 64-bit immediate, and if the value can be accurately represented as a
968 /// sign extension from a 16-bit value. If so, this returns true and the
970 static bool isIntS16Immediate(SDNode *N, short &Imm) {
971 if (N->getOpcode() != ISD::Constant)
974 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
975 if (N->getValueType(0) == MVT::i32)
976 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
978 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
980 static bool isIntS16Immediate(SDValue Op, short &Imm) {
981 return isIntS16Immediate(Op.getNode(), Imm);
985 /// SelectAddressRegReg - Given the specified addressed, check to see if it
986 /// can be represented as an indexed [r+r] operation. Returns false if it
987 /// can be more efficiently represented with [r+imm].
988 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
990 SelectionDAG &DAG) const {
992 if (N.getOpcode() == ISD::ADD) {
993 if (isIntS16Immediate(N.getOperand(1), imm))
995 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
998 Base = N.getOperand(0);
999 Index = N.getOperand(1);
1001 } else if (N.getOpcode() == ISD::OR) {
1002 if (isIntS16Immediate(N.getOperand(1), imm))
1003 return false; // r+i can fold it if we can.
1005 // If this is an or of disjoint bitfields, we can codegen this as an add
1006 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1008 APInt LHSKnownZero, LHSKnownOne;
1009 APInt RHSKnownZero, RHSKnownOne;
1010 DAG.ComputeMaskedBits(N.getOperand(0),
1011 LHSKnownZero, LHSKnownOne);
1013 if (LHSKnownZero.getBoolValue()) {
1014 DAG.ComputeMaskedBits(N.getOperand(1),
1015 RHSKnownZero, RHSKnownOne);
1016 // If all of the bits are known zero on the LHS or RHS, the add won't
1018 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1019 Base = N.getOperand(0);
1020 Index = N.getOperand(1);
1029 /// Returns true if the address N can be represented by a base register plus
1030 /// a signed 16-bit displacement [r+imm], and if it is not better
1031 /// represented as reg+reg. If Aligned is true, only accept displacements
1032 /// suitable for STD and friends, i.e. multiples of 4.
1033 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1036 bool Aligned) const {
1037 // FIXME dl should come from parent load or store, not from address
1039 // If this can be more profitably realized as r+r, fail.
1040 if (SelectAddressRegReg(N, Disp, Base, DAG))
1043 if (N.getOpcode() == ISD::ADD) {
1045 if (isIntS16Immediate(N.getOperand(1), imm) &&
1046 (!Aligned || (imm & 3) == 0)) {
1047 Disp = DAG.getTargetConstant(imm, N.getValueType());
1048 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1049 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1051 Base = N.getOperand(0);
1053 return true; // [r+i]
1054 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1055 // Match LOAD (ADD (X, Lo(G))).
1056 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1057 && "Cannot handle constant offsets yet!");
1058 Disp = N.getOperand(1).getOperand(0); // The global address.
1059 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1060 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1061 Disp.getOpcode() == ISD::TargetConstantPool ||
1062 Disp.getOpcode() == ISD::TargetJumpTable);
1063 Base = N.getOperand(0);
1064 return true; // [&g+r]
1066 } else if (N.getOpcode() == ISD::OR) {
1068 if (isIntS16Immediate(N.getOperand(1), imm) &&
1069 (!Aligned || (imm & 3) == 0)) {
1070 // If this is an or of disjoint bitfields, we can codegen this as an add
1071 // (for better address arithmetic) if the LHS and RHS of the OR are
1072 // provably disjoint.
1073 APInt LHSKnownZero, LHSKnownOne;
1074 DAG.ComputeMaskedBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1076 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1077 // If all of the bits are known zero on the LHS or RHS, the add won't
1079 Base = N.getOperand(0);
1080 Disp = DAG.getTargetConstant(imm, N.getValueType());
1084 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1085 // Loading from a constant address.
1087 // If this address fits entirely in a 16-bit sext immediate field, codegen
1090 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1091 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1092 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1093 CN->getValueType(0));
1097 // Handle 32-bit sext immediates with LIS + addr mode.
1098 if ((CN->getValueType(0) == MVT::i32 ||
1099 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1100 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1101 int Addr = (int)CN->getZExtValue();
1103 // Otherwise, break this down into an LIS + disp.
1104 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1106 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1107 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1108 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1113 Disp = DAG.getTargetConstant(0, getPointerTy());
1114 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
1115 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1118 return true; // [r+0]
1121 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1122 /// represented as an indexed [r+r] operation.
1123 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1125 SelectionDAG &DAG) const {
1126 // Check to see if we can easily represent this as an [r+r] address. This
1127 // will fail if it thinks that the address is more profitably represented as
1128 // reg+imm, e.g. where imm = 0.
1129 if (SelectAddressRegReg(N, Base, Index, DAG))
1132 // If the operand is an addition, always emit this as [r+r], since this is
1133 // better (for code size, and execution, as the memop does the add for free)
1134 // than emitting an explicit add.
1135 if (N.getOpcode() == ISD::ADD) {
1136 Base = N.getOperand(0);
1137 Index = N.getOperand(1);
1141 // Otherwise, do it the hard way, using R0 as the base register.
1142 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1148 /// getPreIndexedAddressParts - returns true by value, base pointer and
1149 /// offset pointer and addressing mode by reference if the node's address
1150 /// can be legally represented as pre-indexed load / store address.
1151 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1153 ISD::MemIndexedMode &AM,
1154 SelectionDAG &DAG) const {
1155 if (DisablePPCPreinc) return false;
1161 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1162 Ptr = LD->getBasePtr();
1163 VT = LD->getMemoryVT();
1164 Alignment = LD->getAlignment();
1165 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1166 Ptr = ST->getBasePtr();
1167 VT = ST->getMemoryVT();
1168 Alignment = ST->getAlignment();
1173 // PowerPC doesn't have preinc load/store instructions for vectors.
1177 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1179 // Common code will reject creating a pre-inc form if the base pointer
1180 // is a frame index, or if N is a store and the base pointer is either
1181 // the same as or a predecessor of the value being stored. Check for
1182 // those situations here, and try with swapped Base/Offset instead.
1185 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1188 SDValue Val = cast<StoreSDNode>(N)->getValue();
1189 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1194 std::swap(Base, Offset);
1200 // LDU/STU can only handle immediates that are a multiple of 4.
1201 if (VT != MVT::i64) {
1202 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1205 // LDU/STU need an address with at least 4-byte alignment.
1209 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1213 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1214 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1215 // sext i32 to i64 when addr mode is r+i.
1216 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1217 LD->getExtensionType() == ISD::SEXTLOAD &&
1218 isa<ConstantSDNode>(Offset))
1226 //===----------------------------------------------------------------------===//
1227 // LowerOperation implementation
1228 //===----------------------------------------------------------------------===//
1230 /// GetLabelAccessInfo - Return true if we should reference labels using a
1231 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1232 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1233 unsigned &LoOpFlags, const GlobalValue *GV = 0) {
1234 HiOpFlags = PPCII::MO_HA;
1235 LoOpFlags = PPCII::MO_LO;
1237 // Don't use the pic base if not in PIC relocation model. Or if we are on a
1238 // non-darwin platform. We don't support PIC on other platforms yet.
1239 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ &&
1240 TM.getSubtarget<PPCSubtarget>().isDarwin();
1242 HiOpFlags |= PPCII::MO_PIC_FLAG;
1243 LoOpFlags |= PPCII::MO_PIC_FLAG;
1246 // If this is a reference to a global value that requires a non-lazy-ptr, make
1247 // sure that instruction lowering adds it.
1248 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1249 HiOpFlags |= PPCII::MO_NLP_FLAG;
1250 LoOpFlags |= PPCII::MO_NLP_FLAG;
1252 if (GV->hasHiddenVisibility()) {
1253 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1254 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1261 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1262 SelectionDAG &DAG) {
1263 EVT PtrVT = HiPart.getValueType();
1264 SDValue Zero = DAG.getConstant(0, PtrVT);
1267 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1268 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1270 // With PIC, the first instruction is actually "GR+hi(&G)".
1272 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1273 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1275 // Generate non-pic code that has direct accesses to the constant pool.
1276 // The address of the global is just (hi(&g)+lo(&g)).
1277 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1280 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1281 SelectionDAG &DAG) const {
1282 EVT PtrVT = Op.getValueType();
1283 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1284 const Constant *C = CP->getConstVal();
1286 // 64-bit SVR4 ABI code is always position-independent.
1287 // The actual address of the GlobalValue is stored in the TOC.
1288 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1289 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1290 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1291 DAG.getRegister(PPC::X2, MVT::i64));
1294 unsigned MOHiFlag, MOLoFlag;
1295 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1297 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1299 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1300 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1303 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1304 EVT PtrVT = Op.getValueType();
1305 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1307 // 64-bit SVR4 ABI code is always position-independent.
1308 // The actual address of the GlobalValue is stored in the TOC.
1309 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1310 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1311 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1312 DAG.getRegister(PPC::X2, MVT::i64));
1315 unsigned MOHiFlag, MOLoFlag;
1316 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1317 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1318 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1319 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1322 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1323 SelectionDAG &DAG) const {
1324 EVT PtrVT = Op.getValueType();
1326 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1328 unsigned MOHiFlag, MOLoFlag;
1329 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1330 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1331 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1332 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1335 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1336 SelectionDAG &DAG) const {
1338 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1340 const GlobalValue *GV = GA->getGlobal();
1341 EVT PtrVT = getPointerTy();
1342 bool is64bit = PPCSubTarget.isPPC64();
1344 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1346 if (Model == TLSModel::LocalExec) {
1347 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1348 PPCII::MO_TPREL_HA);
1349 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1350 PPCII::MO_TPREL_LO);
1351 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1352 is64bit ? MVT::i64 : MVT::i32);
1353 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1354 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1358 llvm_unreachable("only local-exec is currently supported for ppc32");
1360 if (Model == TLSModel::InitialExec) {
1361 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1362 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1363 SDValue TPOffsetHi = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1364 PtrVT, GOTReg, TGA);
1365 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1366 PtrVT, TGA, TPOffsetHi);
1367 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGA);
1370 if (Model == TLSModel::GeneralDynamic) {
1371 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1372 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1373 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1375 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1378 // We need a chain node, and don't have one handy. The underlying
1379 // call has no side effects, so using the function entry node
1381 SDValue Chain = DAG.getEntryNode();
1382 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1383 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1384 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl,
1385 PtrVT, ParmReg, TGA);
1386 // The return value from GET_TLS_ADDR really is in X3 already, but
1387 // some hacks are needed here to tie everything together. The extra
1388 // copies dissolve during subsequent transforms.
1389 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1390 return DAG.getCopyFromReg(Chain, dl, PPC::X3, PtrVT);
1393 if (Model == TLSModel::LocalDynamic) {
1394 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1395 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1396 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1398 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1401 // We need a chain node, and don't have one handy. The underlying
1402 // call has no side effects, so using the function entry node
1404 SDValue Chain = DAG.getEntryNode();
1405 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1406 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1407 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl,
1408 PtrVT, ParmReg, TGA);
1409 // The return value from GET_TLSLD_ADDR really is in X3 already, but
1410 // some hacks are needed here to tie everything together. The extra
1411 // copies dissolve during subsequent transforms.
1412 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1413 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1414 Chain, ParmReg, TGA);
1415 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1418 llvm_unreachable("Unknown TLS model!");
1421 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1422 SelectionDAG &DAG) const {
1423 EVT PtrVT = Op.getValueType();
1424 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1426 const GlobalValue *GV = GSDN->getGlobal();
1428 // 64-bit SVR4 ABI code is always position-independent.
1429 // The actual address of the GlobalValue is stored in the TOC.
1430 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1431 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1432 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1433 DAG.getRegister(PPC::X2, MVT::i64));
1436 unsigned MOHiFlag, MOLoFlag;
1437 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1440 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1442 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1444 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1446 // If the global reference is actually to a non-lazy-pointer, we have to do an
1447 // extra load to get the address of the global.
1448 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1449 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1450 false, false, false, 0);
1454 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1455 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1458 // If we're comparing for equality to zero, expose the fact that this is
1459 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1460 // fold the new nodes.
1461 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1462 if (C->isNullValue() && CC == ISD::SETEQ) {
1463 EVT VT = Op.getOperand(0).getValueType();
1464 SDValue Zext = Op.getOperand(0);
1465 if (VT.bitsLT(MVT::i32)) {
1467 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1469 unsigned Log2b = Log2_32(VT.getSizeInBits());
1470 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1471 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1472 DAG.getConstant(Log2b, MVT::i32));
1473 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1475 // Leave comparisons against 0 and -1 alone for now, since they're usually
1476 // optimized. FIXME: revisit this when we can custom lower all setcc
1478 if (C->isAllOnesValue() || C->isNullValue())
1482 // If we have an integer seteq/setne, turn it into a compare against zero
1483 // by xor'ing the rhs with the lhs, which is faster than setting a
1484 // condition register, reading it back out, and masking the correct bit. The
1485 // normal approach here uses sub to do this instead of xor. Using xor exposes
1486 // the result to other bit-twiddling opportunities.
1487 EVT LHSVT = Op.getOperand(0).getValueType();
1488 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1489 EVT VT = Op.getValueType();
1490 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1492 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1497 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1498 const PPCSubtarget &Subtarget) const {
1499 SDNode *Node = Op.getNode();
1500 EVT VT = Node->getValueType(0);
1501 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1502 SDValue InChain = Node->getOperand(0);
1503 SDValue VAListPtr = Node->getOperand(1);
1504 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1507 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1510 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1511 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1513 InChain = GprIndex.getValue(1);
1515 if (VT == MVT::i64) {
1516 // Check if GprIndex is even
1517 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1518 DAG.getConstant(1, MVT::i32));
1519 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1520 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1521 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1522 DAG.getConstant(1, MVT::i32));
1523 // Align GprIndex to be even if it isn't
1524 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1528 // fpr index is 1 byte after gpr
1529 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1530 DAG.getConstant(1, MVT::i32));
1533 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1534 FprPtr, MachinePointerInfo(SV), MVT::i8,
1536 InChain = FprIndex.getValue(1);
1538 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1539 DAG.getConstant(8, MVT::i32));
1541 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1542 DAG.getConstant(4, MVT::i32));
1545 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1546 MachinePointerInfo(), false, false,
1548 InChain = OverflowArea.getValue(1);
1550 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1551 MachinePointerInfo(), false, false,
1553 InChain = RegSaveArea.getValue(1);
1555 // select overflow_area if index > 8
1556 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1557 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1559 // adjustment constant gpr_index * 4/8
1560 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1561 VT.isInteger() ? GprIndex : FprIndex,
1562 DAG.getConstant(VT.isInteger() ? 4 : 8,
1565 // OurReg = RegSaveArea + RegConstant
1566 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1569 // Floating types are 32 bytes into RegSaveArea
1570 if (VT.isFloatingPoint())
1571 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1572 DAG.getConstant(32, MVT::i32));
1574 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1575 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1576 VT.isInteger() ? GprIndex : FprIndex,
1577 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1580 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1581 VT.isInteger() ? VAListPtr : FprPtr,
1582 MachinePointerInfo(SV),
1583 MVT::i8, false, false, 0);
1585 // determine if we should load from reg_save_area or overflow_area
1586 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1588 // increase overflow_area by 4/8 if gpr/fpr > 8
1589 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1590 DAG.getConstant(VT.isInteger() ? 4 : 8,
1593 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1596 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1598 MachinePointerInfo(),
1599 MVT::i32, false, false, 0);
1601 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1602 false, false, false, 0);
1605 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
1606 SelectionDAG &DAG) const {
1607 return Op.getOperand(0);
1610 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
1611 SelectionDAG &DAG) const {
1612 SDValue Chain = Op.getOperand(0);
1613 SDValue Trmp = Op.getOperand(1); // trampoline
1614 SDValue FPtr = Op.getOperand(2); // nested function
1615 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1618 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1619 bool isPPC64 = (PtrVT == MVT::i64);
1621 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
1624 TargetLowering::ArgListTy Args;
1625 TargetLowering::ArgListEntry Entry;
1627 Entry.Ty = IntPtrTy;
1628 Entry.Node = Trmp; Args.push_back(Entry);
1630 // TrampSize == (isPPC64 ? 48 : 40);
1631 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1632 isPPC64 ? MVT::i64 : MVT::i32);
1633 Args.push_back(Entry);
1635 Entry.Node = FPtr; Args.push_back(Entry);
1636 Entry.Node = Nest; Args.push_back(Entry);
1638 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1639 TargetLowering::CallLoweringInfo CLI(Chain,
1640 Type::getVoidTy(*DAG.getContext()),
1641 false, false, false, false, 0,
1643 /*isTailCall=*/false,
1644 /*doesNotRet=*/false,
1645 /*isReturnValueUsed=*/true,
1646 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1648 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1650 return CallResult.second;
1653 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1654 const PPCSubtarget &Subtarget) const {
1655 MachineFunction &MF = DAG.getMachineFunction();
1656 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1660 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
1661 // vastart just stores the address of the VarArgsFrameIndex slot into the
1662 // memory location argument.
1663 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1664 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1665 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1666 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
1667 MachinePointerInfo(SV),
1671 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
1672 // We suppose the given va_list is already allocated.
1675 // char gpr; /* index into the array of 8 GPRs
1676 // * stored in the register save area
1677 // * gpr=0 corresponds to r3,
1678 // * gpr=1 to r4, etc.
1680 // char fpr; /* index into the array of 8 FPRs
1681 // * stored in the register save area
1682 // * fpr=0 corresponds to f1,
1683 // * fpr=1 to f2, etc.
1685 // char *overflow_arg_area;
1686 // /* location on stack that holds
1687 // * the next overflow argument
1689 // char *reg_save_area;
1690 // /* where r3:r10 and f1:f8 (if saved)
1696 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
1697 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
1700 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1702 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
1704 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1707 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
1708 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1710 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
1711 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1713 uint64_t FPROffset = 1;
1714 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1716 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1718 // Store first byte : number of int regs
1719 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
1721 MachinePointerInfo(SV),
1722 MVT::i8, false, false, 0);
1723 uint64_t nextOffset = FPROffset;
1724 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
1727 // Store second byte : number of float regs
1728 SDValue secondStore =
1729 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
1730 MachinePointerInfo(SV, nextOffset), MVT::i8,
1732 nextOffset += StackOffset;
1733 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
1735 // Store second word : arguments given on stack
1736 SDValue thirdStore =
1737 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
1738 MachinePointerInfo(SV, nextOffset),
1740 nextOffset += FrameOffset;
1741 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
1743 // Store third word : arguments given in registers
1744 return DAG.getStore(thirdStore, dl, FR, nextPtr,
1745 MachinePointerInfo(SV, nextOffset),
1750 #include "PPCGenCallingConv.inc"
1752 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
1753 CCValAssign::LocInfo &LocInfo,
1754 ISD::ArgFlagsTy &ArgFlags,
1759 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
1761 CCValAssign::LocInfo &LocInfo,
1762 ISD::ArgFlagsTy &ArgFlags,
1764 static const uint16_t ArgRegs[] = {
1765 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1766 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1768 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1770 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1772 // Skip one register if the first unallocated register has an even register
1773 // number and there are still argument registers available which have not been
1774 // allocated yet. RegNum is actually an index into ArgRegs, which means we
1775 // need to skip a register if RegNum is odd.
1776 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
1777 State.AllocateReg(ArgRegs[RegNum]);
1780 // Always return false here, as this function only makes sure that the first
1781 // unallocated register has an odd register number and does not actually
1782 // allocate a register for the current argument.
1786 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
1788 CCValAssign::LocInfo &LocInfo,
1789 ISD::ArgFlagsTy &ArgFlags,
1791 static const uint16_t ArgRegs[] = {
1792 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1796 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1798 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1800 // If there is only one Floating-point register left we need to put both f64
1801 // values of a split ppc_fp128 value on the stack.
1802 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
1803 State.AllocateReg(ArgRegs[RegNum]);
1806 // Always return false here, as this function only makes sure that the two f64
1807 // values a ppc_fp128 value is split into are both passed in registers or both
1808 // passed on the stack and does not actually allocate a register for the
1809 // current argument.
1813 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1815 static const uint16_t *GetFPR() {
1816 static const uint16_t FPR[] = {
1817 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1818 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1824 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
1826 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
1827 unsigned PtrByteSize) {
1828 unsigned ArgSize = ArgVT.getSizeInBits()/8;
1829 if (Flags.isByVal())
1830 ArgSize = Flags.getByValSize();
1831 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1837 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
1838 CallingConv::ID CallConv, bool isVarArg,
1839 const SmallVectorImpl<ISD::InputArg>
1841 SDLoc dl, SelectionDAG &DAG,
1842 SmallVectorImpl<SDValue> &InVals)
1844 if (PPCSubTarget.isSVR4ABI()) {
1845 if (PPCSubTarget.isPPC64())
1846 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
1849 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
1852 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
1858 PPCTargetLowering::LowerFormalArguments_32SVR4(
1860 CallingConv::ID CallConv, bool isVarArg,
1861 const SmallVectorImpl<ISD::InputArg>
1863 SDLoc dl, SelectionDAG &DAG,
1864 SmallVectorImpl<SDValue> &InVals) const {
1866 // 32-bit SVR4 ABI Stack Frame Layout:
1867 // +-----------------------------------+
1868 // +--> | Back chain |
1869 // | +-----------------------------------+
1870 // | | Floating-point register save area |
1871 // | +-----------------------------------+
1872 // | | General register save area |
1873 // | +-----------------------------------+
1874 // | | CR save word |
1875 // | +-----------------------------------+
1876 // | | VRSAVE save word |
1877 // | +-----------------------------------+
1878 // | | Alignment padding |
1879 // | +-----------------------------------+
1880 // | | Vector register save area |
1881 // | +-----------------------------------+
1882 // | | Local variable space |
1883 // | +-----------------------------------+
1884 // | | Parameter list area |
1885 // | +-----------------------------------+
1886 // | | LR save word |
1887 // | +-----------------------------------+
1888 // SP--> +--- | Back chain |
1889 // +-----------------------------------+
1892 // System V Application Binary Interface PowerPC Processor Supplement
1893 // AltiVec Technology Programming Interface Manual
1895 MachineFunction &MF = DAG.getMachineFunction();
1896 MachineFrameInfo *MFI = MF.getFrameInfo();
1897 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1899 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1900 // Potential tail calls could cause overwriting of argument stack slots.
1901 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
1902 (CallConv == CallingConv::Fast));
1903 unsigned PtrByteSize = 4;
1905 // Assign locations to all of the incoming arguments.
1906 SmallVector<CCValAssign, 16> ArgLocs;
1907 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1908 getTargetMachine(), ArgLocs, *DAG.getContext());
1910 // Reserve space for the linkage area on the stack.
1911 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
1913 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
1915 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1916 CCValAssign &VA = ArgLocs[i];
1918 // Arguments stored in registers.
1919 if (VA.isRegLoc()) {
1920 const TargetRegisterClass *RC;
1921 EVT ValVT = VA.getValVT();
1923 switch (ValVT.getSimpleVT().SimpleTy) {
1925 llvm_unreachable("ValVT not supported by formal arguments Lowering");
1927 RC = &PPC::GPRCRegClass;
1930 RC = &PPC::F4RCRegClass;
1933 RC = &PPC::F8RCRegClass;
1939 RC = &PPC::VRRCRegClass;
1943 // Transform the arguments stored in physical registers into virtual ones.
1944 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1945 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT);
1947 InVals.push_back(ArgValue);
1949 // Argument stored in memory.
1950 assert(VA.isMemLoc());
1952 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
1953 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
1956 // Create load nodes to retrieve arguments from the stack.
1957 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1958 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
1959 MachinePointerInfo(),
1960 false, false, false, 0));
1964 // Assign locations to all of the incoming aggregate by value arguments.
1965 // Aggregates passed by value are stored in the local variable space of the
1966 // caller's stack frame, right above the parameter list area.
1967 SmallVector<CCValAssign, 16> ByValArgLocs;
1968 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1969 getTargetMachine(), ByValArgLocs, *DAG.getContext());
1971 // Reserve stack space for the allocations in CCInfo.
1972 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
1974 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
1976 // Area that is at least reserved in the caller of this function.
1977 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
1979 // Set the size that is at least reserved in caller of this function. Tail
1980 // call optimized function's reserved stack space needs to be aligned so that
1981 // taking the difference between two stack areas will result in an aligned
1983 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1986 std::max(MinReservedArea,
1987 PPCFrameLowering::getMinCallFrameSize(false, false));
1989 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
1990 getStackAlignment();
1991 unsigned AlignMask = TargetAlign-1;
1992 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
1994 FI->setMinReservedArea(MinReservedArea);
1996 SmallVector<SDValue, 8> MemOps;
1998 // If the function takes variable number of arguments, make a frame index for
1999 // the start of the first vararg value... for expansion of llvm.va_start.
2001 static const uint16_t GPArgRegs[] = {
2002 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2003 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2005 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2007 static const uint16_t FPArgRegs[] = {
2008 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2011 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2013 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2015 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2018 // Make room for NumGPArgRegs and NumFPArgRegs.
2019 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2020 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
2022 FuncInfo->setVarArgsStackOffset(
2023 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2024 CCInfo.getNextStackOffset(), true));
2026 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2027 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2029 // The fixed integer arguments of a variadic function are stored to the
2030 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2031 // the result of va_next.
2032 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2033 // Get an existing live-in vreg, or add a new one.
2034 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2036 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2038 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2039 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2040 MachinePointerInfo(), false, false, 0);
2041 MemOps.push_back(Store);
2042 // Increment the address by four for the next argument to store
2043 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2044 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2047 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2049 // The double arguments are stored to the VarArgsFrameIndex
2051 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2052 // Get an existing live-in vreg, or add a new one.
2053 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2055 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2057 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2058 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2059 MachinePointerInfo(), false, false, 0);
2060 MemOps.push_back(Store);
2061 // Increment the address by eight for the next argument to store
2062 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
2064 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2068 if (!MemOps.empty())
2069 Chain = DAG.getNode(ISD::TokenFactor, dl,
2070 MVT::Other, &MemOps[0], MemOps.size());
2075 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2076 // value to MVT::i64 and then truncate to the correct register size.
2078 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2079 SelectionDAG &DAG, SDValue ArgVal,
2082 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2083 DAG.getValueType(ObjectVT));
2084 else if (Flags.isZExt())
2085 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2086 DAG.getValueType(ObjectVT));
2088 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2091 // Set the size that is at least reserved in caller of this function. Tail
2092 // call optimized functions' reserved stack space needs to be aligned so that
2093 // taking the difference between two stack areas will result in an aligned
2096 PPCTargetLowering::setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG,
2097 unsigned nAltivecParamsAtEnd,
2098 unsigned MinReservedArea,
2099 bool isPPC64) const {
2100 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2101 // Add the Altivec parameters at the end, if needed.
2102 if (nAltivecParamsAtEnd) {
2103 MinReservedArea = ((MinReservedArea+15)/16)*16;
2104 MinReservedArea += 16*nAltivecParamsAtEnd;
2107 std::max(MinReservedArea,
2108 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2109 unsigned TargetAlign
2110 = DAG.getMachineFunction().getTarget().getFrameLowering()->
2111 getStackAlignment();
2112 unsigned AlignMask = TargetAlign-1;
2113 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2114 FI->setMinReservedArea(MinReservedArea);
2118 PPCTargetLowering::LowerFormalArguments_64SVR4(
2120 CallingConv::ID CallConv, bool isVarArg,
2121 const SmallVectorImpl<ISD::InputArg>
2123 SDLoc dl, SelectionDAG &DAG,
2124 SmallVectorImpl<SDValue> &InVals) const {
2125 // TODO: add description of PPC stack frame format, or at least some docs.
2127 MachineFunction &MF = DAG.getMachineFunction();
2128 MachineFrameInfo *MFI = MF.getFrameInfo();
2129 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2131 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2132 // Potential tail calls could cause overwriting of argument stack slots.
2133 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2134 (CallConv == CallingConv::Fast));
2135 unsigned PtrByteSize = 8;
2137 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
2138 // Area that is at least reserved in caller of this function.
2139 unsigned MinReservedArea = ArgOffset;
2141 static const uint16_t GPR[] = {
2142 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2143 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2146 static const uint16_t *FPR = GetFPR();
2148 static const uint16_t VR[] = {
2149 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2150 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2153 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2154 const unsigned Num_FPR_Regs = 13;
2155 const unsigned Num_VR_Regs = array_lengthof(VR);
2157 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2159 // Add DAG nodes to load the arguments or copy them out of registers. On
2160 // entry to a function on PPC, the arguments start after the linkage area,
2161 // although the first ones are often in registers.
2163 SmallVector<SDValue, 8> MemOps;
2164 unsigned nAltivecParamsAtEnd = 0;
2165 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2166 unsigned CurArgIdx = 0;
2167 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2169 bool needsLoad = false;
2170 EVT ObjectVT = Ins[ArgNo].VT;
2171 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2172 unsigned ArgSize = ObjSize;
2173 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2174 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2175 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2177 unsigned CurArgOffset = ArgOffset;
2179 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2180 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2181 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2183 MinReservedArea = ((MinReservedArea+15)/16)*16;
2184 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2188 nAltivecParamsAtEnd++;
2190 // Calculate min reserved area.
2191 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2195 // FIXME the codegen can be much improved in some cases.
2196 // We do not have to keep everything in memory.
2197 if (Flags.isByVal()) {
2198 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2199 ObjSize = Flags.getByValSize();
2200 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2201 // Empty aggregate parameters do not take up registers. Examples:
2205 // etc. However, we have to provide a place-holder in InVals, so
2206 // pretend we have an 8-byte item at the current address for that
2209 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2210 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2211 InVals.push_back(FIN);
2214 // All aggregates smaller than 8 bytes must be passed right-justified.
2215 if (ObjSize < PtrByteSize)
2216 CurArgOffset = CurArgOffset + (PtrByteSize - ObjSize);
2217 // The value of the object is its address.
2218 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2219 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2220 InVals.push_back(FIN);
2223 if (GPR_idx != Num_GPR_Regs) {
2224 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2225 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2228 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2229 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2230 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2231 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2232 MachinePointerInfo(FuncArg, CurArgOffset),
2233 ObjType, false, false, 0);
2235 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2236 // store the whole register as-is to the parameter save area
2237 // slot. The address of the parameter was already calculated
2238 // above (InVals.push_back(FIN)) to be the right-justified
2239 // offset within the slot. For this store, we need a new
2240 // frame index that points at the beginning of the slot.
2241 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2242 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2243 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2244 MachinePointerInfo(FuncArg, ArgOffset),
2248 MemOps.push_back(Store);
2251 // Whether we copied from a register or not, advance the offset
2252 // into the parameter save area by a full doubleword.
2253 ArgOffset += PtrByteSize;
2257 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2258 // Store whatever pieces of the object are in registers
2259 // to memory. ArgOffset will be the address of the beginning
2261 if (GPR_idx != Num_GPR_Regs) {
2263 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2264 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2265 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2266 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2267 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2268 MachinePointerInfo(FuncArg, ArgOffset),
2270 MemOps.push_back(Store);
2272 ArgOffset += PtrByteSize;
2274 ArgOffset += ArgSize - j;
2281 switch (ObjectVT.getSimpleVT().SimpleTy) {
2282 default: llvm_unreachable("Unhandled argument type!");
2285 if (GPR_idx != Num_GPR_Regs) {
2286 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2287 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2289 if (ObjectVT == MVT::i32)
2290 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2291 // value to MVT::i64 and then truncate to the correct register size.
2292 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2297 ArgSize = PtrByteSize;
2304 // Every 8 bytes of argument space consumes one of the GPRs available for
2305 // argument passing.
2306 if (GPR_idx != Num_GPR_Regs) {
2309 if (FPR_idx != Num_FPR_Regs) {
2312 if (ObjectVT == MVT::f32)
2313 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2315 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2317 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2321 ArgSize = PtrByteSize;
2330 // Note that vector arguments in registers don't reserve stack space,
2331 // except in varargs functions.
2332 if (VR_idx != Num_VR_Regs) {
2333 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2334 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2336 while ((ArgOffset % 16) != 0) {
2337 ArgOffset += PtrByteSize;
2338 if (GPR_idx != Num_GPR_Regs)
2342 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2346 // Vectors are aligned.
2347 ArgOffset = ((ArgOffset+15)/16)*16;
2348 CurArgOffset = ArgOffset;
2355 // We need to load the argument to a virtual register if we determined
2356 // above that we ran out of physical registers of the appropriate type.
2358 int FI = MFI->CreateFixedObject(ObjSize,
2359 CurArgOffset + (ArgSize - ObjSize),
2361 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2362 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2363 false, false, false, 0);
2366 InVals.push_back(ArgVal);
2369 // Set the size that is at least reserved in caller of this function. Tail
2370 // call optimized functions' reserved stack space needs to be aligned so that
2371 // taking the difference between two stack areas will result in an aligned
2373 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, true);
2375 // If the function takes variable number of arguments, make a frame index for
2376 // the start of the first vararg value... for expansion of llvm.va_start.
2378 int Depth = ArgOffset;
2380 FuncInfo->setVarArgsFrameIndex(
2381 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2382 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2384 // If this function is vararg, store any remaining integer argument regs
2385 // to their spots on the stack so that they may be loaded by deferencing the
2386 // result of va_next.
2387 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2388 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2389 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2390 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2391 MachinePointerInfo(), false, false, 0);
2392 MemOps.push_back(Store);
2393 // Increment the address by four for the next argument to store
2394 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2395 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2399 if (!MemOps.empty())
2400 Chain = DAG.getNode(ISD::TokenFactor, dl,
2401 MVT::Other, &MemOps[0], MemOps.size());
2407 PPCTargetLowering::LowerFormalArguments_Darwin(
2409 CallingConv::ID CallConv, bool isVarArg,
2410 const SmallVectorImpl<ISD::InputArg>
2412 SDLoc dl, SelectionDAG &DAG,
2413 SmallVectorImpl<SDValue> &InVals) const {
2414 // TODO: add description of PPC stack frame format, or at least some docs.
2416 MachineFunction &MF = DAG.getMachineFunction();
2417 MachineFrameInfo *MFI = MF.getFrameInfo();
2418 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2420 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2421 bool isPPC64 = PtrVT == MVT::i64;
2422 // Potential tail calls could cause overwriting of argument stack slots.
2423 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2424 (CallConv == CallingConv::Fast));
2425 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2427 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
2428 // Area that is at least reserved in caller of this function.
2429 unsigned MinReservedArea = ArgOffset;
2431 static const uint16_t GPR_32[] = { // 32-bit registers.
2432 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2433 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2435 static const uint16_t GPR_64[] = { // 64-bit registers.
2436 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2437 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2440 static const uint16_t *FPR = GetFPR();
2442 static const uint16_t VR[] = {
2443 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2444 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2447 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2448 const unsigned Num_FPR_Regs = 13;
2449 const unsigned Num_VR_Regs = array_lengthof( VR);
2451 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2453 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
2455 // In 32-bit non-varargs functions, the stack space for vectors is after the
2456 // stack space for non-vectors. We do not use this space unless we have
2457 // too many vectors to fit in registers, something that only occurs in
2458 // constructed examples:), but we have to walk the arglist to figure
2459 // that out...for the pathological case, compute VecArgOffset as the
2460 // start of the vector parameter area. Computing VecArgOffset is the
2461 // entire point of the following loop.
2462 unsigned VecArgOffset = ArgOffset;
2463 if (!isVarArg && !isPPC64) {
2464 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
2466 EVT ObjectVT = Ins[ArgNo].VT;
2467 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2469 if (Flags.isByVal()) {
2470 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
2471 unsigned ObjSize = Flags.getByValSize();
2473 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2474 VecArgOffset += ArgSize;
2478 switch(ObjectVT.getSimpleVT().SimpleTy) {
2479 default: llvm_unreachable("Unhandled argument type!");
2484 case MVT::i64: // PPC64
2486 // FIXME: We are guaranteed to be !isPPC64 at this point.
2487 // Does MVT::i64 apply?
2494 // Nothing to do, we're only looking at Nonvector args here.
2499 // We've found where the vector parameter area in memory is. Skip the
2500 // first 12 parameters; these don't use that memory.
2501 VecArgOffset = ((VecArgOffset+15)/16)*16;
2502 VecArgOffset += 12*16;
2504 // Add DAG nodes to load the arguments or copy them out of registers. On
2505 // entry to a function on PPC, the arguments start after the linkage area,
2506 // although the first ones are often in registers.
2508 SmallVector<SDValue, 8> MemOps;
2509 unsigned nAltivecParamsAtEnd = 0;
2510 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2511 unsigned CurArgIdx = 0;
2512 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2514 bool needsLoad = false;
2515 EVT ObjectVT = Ins[ArgNo].VT;
2516 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2517 unsigned ArgSize = ObjSize;
2518 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2519 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2520 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2522 unsigned CurArgOffset = ArgOffset;
2524 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2525 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2526 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2527 if (isVarArg || isPPC64) {
2528 MinReservedArea = ((MinReservedArea+15)/16)*16;
2529 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2532 } else nAltivecParamsAtEnd++;
2534 // Calculate min reserved area.
2535 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2539 // FIXME the codegen can be much improved in some cases.
2540 // We do not have to keep everything in memory.
2541 if (Flags.isByVal()) {
2542 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2543 ObjSize = Flags.getByValSize();
2544 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2545 // Objects of size 1 and 2 are right justified, everything else is
2546 // left justified. This means the memory address is adjusted forwards.
2547 if (ObjSize==1 || ObjSize==2) {
2548 CurArgOffset = CurArgOffset + (4 - ObjSize);
2550 // The value of the object is its address.
2551 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2552 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2553 InVals.push_back(FIN);
2554 if (ObjSize==1 || ObjSize==2) {
2555 if (GPR_idx != Num_GPR_Regs) {
2558 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2560 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2561 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2562 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
2563 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2564 MachinePointerInfo(FuncArg,
2566 ObjType, false, false, 0);
2567 MemOps.push_back(Store);
2571 ArgOffset += PtrByteSize;
2575 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2576 // Store whatever pieces of the object are in registers
2577 // to memory. ArgOffset will be the address of the beginning
2579 if (GPR_idx != Num_GPR_Regs) {
2582 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2584 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2585 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2586 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2587 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2588 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2589 MachinePointerInfo(FuncArg, ArgOffset),
2591 MemOps.push_back(Store);
2593 ArgOffset += PtrByteSize;
2595 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
2602 switch (ObjectVT.getSimpleVT().SimpleTy) {
2603 default: llvm_unreachable("Unhandled argument type!");
2606 if (GPR_idx != Num_GPR_Regs) {
2607 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2608 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2612 ArgSize = PtrByteSize;
2614 // All int arguments reserve stack space in the Darwin ABI.
2615 ArgOffset += PtrByteSize;
2619 case MVT::i64: // PPC64
2620 if (GPR_idx != Num_GPR_Regs) {
2621 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2622 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2624 if (ObjectVT == MVT::i32)
2625 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2626 // value to MVT::i64 and then truncate to the correct register size.
2627 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2632 ArgSize = PtrByteSize;
2634 // All int arguments reserve stack space in the Darwin ABI.
2640 // Every 4 bytes of argument space consumes one of the GPRs available for
2641 // argument passing.
2642 if (GPR_idx != Num_GPR_Regs) {
2644 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
2647 if (FPR_idx != Num_FPR_Regs) {
2650 if (ObjectVT == MVT::f32)
2651 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2653 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2655 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2661 // All FP arguments reserve stack space in the Darwin ABI.
2662 ArgOffset += isPPC64 ? 8 : ObjSize;
2668 // Note that vector arguments in registers don't reserve stack space,
2669 // except in varargs functions.
2670 if (VR_idx != Num_VR_Regs) {
2671 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2672 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2674 while ((ArgOffset % 16) != 0) {
2675 ArgOffset += PtrByteSize;
2676 if (GPR_idx != Num_GPR_Regs)
2680 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2684 if (!isVarArg && !isPPC64) {
2685 // Vectors go after all the nonvectors.
2686 CurArgOffset = VecArgOffset;
2689 // Vectors are aligned.
2690 ArgOffset = ((ArgOffset+15)/16)*16;
2691 CurArgOffset = ArgOffset;
2699 // We need to load the argument to a virtual register if we determined above
2700 // that we ran out of physical registers of the appropriate type.
2702 int FI = MFI->CreateFixedObject(ObjSize,
2703 CurArgOffset + (ArgSize - ObjSize),
2705 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2706 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2707 false, false, false, 0);
2710 InVals.push_back(ArgVal);
2713 // Set the size that is at least reserved in caller of this function. Tail
2714 // call optimized functions' reserved stack space needs to be aligned so that
2715 // taking the difference between two stack areas will result in an aligned
2717 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, isPPC64);
2719 // If the function takes variable number of arguments, make a frame index for
2720 // the start of the first vararg value... for expansion of llvm.va_start.
2722 int Depth = ArgOffset;
2724 FuncInfo->setVarArgsFrameIndex(
2725 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2727 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2729 // If this function is vararg, store any remaining integer argument regs
2730 // to their spots on the stack so that they may be loaded by deferencing the
2731 // result of va_next.
2732 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2736 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2738 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2740 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2741 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2742 MachinePointerInfo(), false, false, 0);
2743 MemOps.push_back(Store);
2744 // Increment the address by four for the next argument to store
2745 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2746 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2750 if (!MemOps.empty())
2751 Chain = DAG.getNode(ISD::TokenFactor, dl,
2752 MVT::Other, &MemOps[0], MemOps.size());
2757 /// CalculateParameterAndLinkageAreaSize - Get the size of the parameter plus
2758 /// linkage area for the Darwin ABI, or the 64-bit SVR4 ABI.
2760 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
2764 const SmallVectorImpl<ISD::OutputArg>
2766 const SmallVectorImpl<SDValue> &OutVals,
2767 unsigned &nAltivecParamsAtEnd) {
2768 // Count how many bytes are to be pushed on the stack, including the linkage
2769 // area, and parameter passing area. We start with 24/48 bytes, which is
2770 // prereserved space for [SP][CR][LR][3 x unused].
2771 unsigned NumBytes = PPCFrameLowering::getLinkageSize(isPPC64, true);
2772 unsigned NumOps = Outs.size();
2773 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2775 // Add up all the space actually used.
2776 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
2777 // they all go in registers, but we must reserve stack space for them for
2778 // possible use by the caller. In varargs or 64-bit calls, parameters are
2779 // assigned stack space in order, with padding so Altivec parameters are
2781 nAltivecParamsAtEnd = 0;
2782 for (unsigned i = 0; i != NumOps; ++i) {
2783 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2784 EVT ArgVT = Outs[i].VT;
2785 // Varargs Altivec parameters are padded to a 16 byte boundary.
2786 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
2787 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
2788 if (!isVarArg && !isPPC64) {
2789 // Non-varargs Altivec parameters go after all the non-Altivec
2790 // parameters; handle those later so we know how much padding we need.
2791 nAltivecParamsAtEnd++;
2794 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
2795 NumBytes = ((NumBytes+15)/16)*16;
2797 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2800 // Allow for Altivec parameters at the end, if needed.
2801 if (nAltivecParamsAtEnd) {
2802 NumBytes = ((NumBytes+15)/16)*16;
2803 NumBytes += 16*nAltivecParamsAtEnd;
2806 // The prolog code of the callee may store up to 8 GPR argument registers to
2807 // the stack, allowing va_start to index over them in memory if its varargs.
2808 // Because we cannot tell if this is needed on the caller side, we have to
2809 // conservatively assume that it is needed. As such, make sure we have at
2810 // least enough stack space for the caller to store the 8 GPRs.
2811 NumBytes = std::max(NumBytes,
2812 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2814 // Tail call needs the stack to be aligned.
2815 if (CC == CallingConv::Fast && DAG.getTarget().Options.GuaranteedTailCallOpt){
2816 unsigned TargetAlign = DAG.getMachineFunction().getTarget().
2817 getFrameLowering()->getStackAlignment();
2818 unsigned AlignMask = TargetAlign-1;
2819 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2825 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
2826 /// adjusted to accommodate the arguments for the tailcall.
2827 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
2828 unsigned ParamSize) {
2830 if (!isTailCall) return 0;
2832 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
2833 unsigned CallerMinReservedArea = FI->getMinReservedArea();
2834 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
2835 // Remember only if the new adjustement is bigger.
2836 if (SPDiff < FI->getTailCallSPDelta())
2837 FI->setTailCallSPDelta(SPDiff);
2842 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2843 /// for tail call optimization. Targets which want to do tail call
2844 /// optimization should implement this function.
2846 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2847 CallingConv::ID CalleeCC,
2849 const SmallVectorImpl<ISD::InputArg> &Ins,
2850 SelectionDAG& DAG) const {
2851 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
2854 // Variable argument functions are not supported.
2858 MachineFunction &MF = DAG.getMachineFunction();
2859 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
2860 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
2861 // Functions containing by val parameters are not supported.
2862 for (unsigned i = 0; i != Ins.size(); i++) {
2863 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2864 if (Flags.isByVal()) return false;
2867 // Non PIC/GOT tail calls are supported.
2868 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
2871 // At the moment we can only do local tail calls (in same module, hidden
2872 // or protected) if we are generating PIC.
2873 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2874 return G->getGlobal()->hasHiddenVisibility()
2875 || G->getGlobal()->hasProtectedVisibility();
2881 /// isCallCompatibleAddress - Return the immediate to use if the specified
2882 /// 32-bit value is representable in the immediate field of a BxA instruction.
2883 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
2884 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2887 int Addr = C->getZExtValue();
2888 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
2889 SignExtend32<26>(Addr) != Addr)
2890 return 0; // Top 6 bits have to be sext of immediate.
2892 return DAG.getConstant((int)C->getZExtValue() >> 2,
2893 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
2898 struct TailCallArgumentInfo {
2903 TailCallArgumentInfo() : FrameIdx(0) {}
2908 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
2910 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
2912 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs,
2913 SmallVector<SDValue, 8> &MemOpChains,
2915 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
2916 SDValue Arg = TailCallArgs[i].Arg;
2917 SDValue FIN = TailCallArgs[i].FrameIdxOp;
2918 int FI = TailCallArgs[i].FrameIdx;
2919 // Store relative to framepointer.
2920 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
2921 MachinePointerInfo::getFixedStack(FI),
2926 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
2927 /// the appropriate stack slot for the tail call optimized function call.
2928 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
2929 MachineFunction &MF,
2938 // Calculate the new stack slot for the return address.
2939 int SlotSize = isPPC64 ? 8 : 4;
2940 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
2942 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
2943 NewRetAddrLoc, true);
2944 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2945 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
2946 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
2947 MachinePointerInfo::getFixedStack(NewRetAddr),
2950 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
2951 // slot as the FP is never overwritten.
2954 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
2955 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
2957 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
2958 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
2959 MachinePointerInfo::getFixedStack(NewFPIdx),
2966 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
2967 /// the position of the argument.
2969 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
2970 SDValue Arg, int SPDiff, unsigned ArgOffset,
2971 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
2972 int Offset = ArgOffset + SPDiff;
2973 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
2974 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2975 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2976 SDValue FIN = DAG.getFrameIndex(FI, VT);
2977 TailCallArgumentInfo Info;
2979 Info.FrameIdxOp = FIN;
2981 TailCallArguments.push_back(Info);
2984 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
2985 /// stack slot. Returns the chain as result and the loaded frame pointers in
2986 /// LROpOut/FPOpout. Used when tail calling.
2987 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
2995 // Load the LR and FP stack slot for later adjusting.
2996 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
2997 LROpOut = getReturnAddrFrameIndex(DAG);
2998 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
2999 false, false, false, 0);
3000 Chain = SDValue(LROpOut.getNode(), 1);
3002 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3003 // slot as the FP is never overwritten.
3005 FPOpOut = getFramePointerFrameIndex(DAG);
3006 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3007 false, false, false, 0);
3008 Chain = SDValue(FPOpOut.getNode(), 1);
3014 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3015 /// by "Src" to address "Dst" of size "Size". Alignment information is
3016 /// specified by the specific parameter attribute. The copy will be passed as
3017 /// a byval function parameter.
3018 /// Sometimes what we are copying is the end of a larger object, the part that
3019 /// does not fit in registers.
3021 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3022 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3024 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3025 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3026 false, false, MachinePointerInfo(0),
3027 MachinePointerInfo(0));
3030 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3033 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3034 SDValue Arg, SDValue PtrOff, int SPDiff,
3035 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3036 bool isVector, SmallVector<SDValue, 8> &MemOpChains,
3037 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments,
3039 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3044 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3046 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3047 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3048 DAG.getConstant(ArgOffset, PtrVT));
3050 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3051 MachinePointerInfo(), false, false, 0));
3052 // Calculate and remember argument location.
3053 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3058 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3059 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3060 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3061 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments) {
3062 MachineFunction &MF = DAG.getMachineFunction();
3064 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3065 // might overwrite each other in case of tail call optimization.
3066 SmallVector<SDValue, 8> MemOpChains2;
3067 // Do not flag preceding copytoreg stuff together with the following stuff.
3069 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3071 if (!MemOpChains2.empty())
3072 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3073 &MemOpChains2[0], MemOpChains2.size());
3075 // Store the return address to the appropriate stack slot.
3076 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3077 isPPC64, isDarwinABI, dl);
3079 // Emit callseq_end just before tailcall node.
3080 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3081 DAG.getIntPtrConstant(0, true), InFlag, dl);
3082 InFlag = Chain.getValue(1);
3086 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3087 SDValue &Chain, SDLoc dl, int SPDiff, bool isTailCall,
3088 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
3089 SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys,
3090 const PPCSubtarget &PPCSubTarget) {
3092 bool isPPC64 = PPCSubTarget.isPPC64();
3093 bool isSVR4ABI = PPCSubTarget.isSVR4ABI();
3095 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3096 NodeTys.push_back(MVT::Other); // Returns a chain
3097 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3099 unsigned CallOpc = PPCISD::CALL;
3101 bool needIndirectCall = true;
3102 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3103 // If this is an absolute destination address, use the munged value.
3104 Callee = SDValue(Dest, 0);
3105 needIndirectCall = false;
3108 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3109 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201
3110 // Use indirect calls for ALL functions calls in JIT mode, since the
3111 // far-call stubs may be outside relocation limits for a BL instruction.
3112 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
3113 unsigned OpFlags = 0;
3114 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3115 (PPCSubTarget.getTargetTriple().isMacOSX() &&
3116 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3117 (G->getGlobal()->isDeclaration() ||
3118 G->getGlobal()->isWeakForLinker())) {
3119 // PC-relative references to external symbols should go through $stub,
3120 // unless we're building with the leopard linker or later, which
3121 // automatically synthesizes these stubs.
3122 OpFlags = PPCII::MO_DARWIN_STUB;
3125 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3126 // every direct call is) turn it into a TargetGlobalAddress /
3127 // TargetExternalSymbol node so that legalize doesn't hack it.
3128 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3129 Callee.getValueType(),
3131 needIndirectCall = false;
3135 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3136 unsigned char OpFlags = 0;
3138 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3139 (PPCSubTarget.getTargetTriple().isMacOSX() &&
3140 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5))) {
3141 // PC-relative references to external symbols should go through $stub,
3142 // unless we're building with the leopard linker or later, which
3143 // automatically synthesizes these stubs.
3144 OpFlags = PPCII::MO_DARWIN_STUB;
3147 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3149 needIndirectCall = false;
3152 if (needIndirectCall) {
3153 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3154 // to do the call, we can't use PPCISD::CALL.
3155 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3157 if (isSVR4ABI && isPPC64) {
3158 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3159 // entry point, but to the function descriptor (the function entry point
3160 // address is part of the function descriptor though).
3161 // The function descriptor is a three doubleword structure with the
3162 // following fields: function entry point, TOC base address and
3163 // environment pointer.
3164 // Thus for a call through a function pointer, the following actions need
3166 // 1. Save the TOC of the caller in the TOC save area of its stack
3167 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3168 // 2. Load the address of the function entry point from the function
3170 // 3. Load the TOC of the callee from the function descriptor into r2.
3171 // 4. Load the environment pointer from the function descriptor into
3173 // 5. Branch to the function entry point address.
3174 // 6. On return of the callee, the TOC of the caller needs to be
3175 // restored (this is done in FinishCall()).
3177 // All those operations are flagged together to ensure that no other
3178 // operations can be scheduled in between. E.g. without flagging the
3179 // operations together, a TOC access in the caller could be scheduled
3180 // between the load of the callee TOC and the branch to the callee, which
3181 // results in the TOC access going through the TOC of the callee instead
3182 // of going through the TOC of the caller, which leads to incorrect code.
3184 // Load the address of the function entry point from the function
3186 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3187 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps,
3188 InFlag.getNode() ? 3 : 2);
3189 Chain = LoadFuncPtr.getValue(1);
3190 InFlag = LoadFuncPtr.getValue(2);
3192 // Load environment pointer into r11.
3193 // Offset of the environment pointer within the function descriptor.
3194 SDValue PtrOff = DAG.getIntPtrConstant(16);
3196 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3197 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
3199 Chain = LoadEnvPtr.getValue(1);
3200 InFlag = LoadEnvPtr.getValue(2);
3202 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3204 Chain = EnvVal.getValue(0);
3205 InFlag = EnvVal.getValue(1);
3207 // Load TOC of the callee into r2. We are using a target-specific load
3208 // with r2 hard coded, because the result of a target-independent load
3209 // would never go directly into r2, since r2 is a reserved register (which
3210 // prevents the register allocator from allocating it), resulting in an
3211 // additional register being allocated and an unnecessary move instruction
3213 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3214 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
3216 Chain = LoadTOCPtr.getValue(0);
3217 InFlag = LoadTOCPtr.getValue(1);
3219 MTCTROps[0] = Chain;
3220 MTCTROps[1] = LoadFuncPtr;
3221 MTCTROps[2] = InFlag;
3224 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps,
3225 2 + (InFlag.getNode() != 0));
3226 InFlag = Chain.getValue(1);
3229 NodeTys.push_back(MVT::Other);
3230 NodeTys.push_back(MVT::Glue);
3231 Ops.push_back(Chain);
3232 CallOpc = PPCISD::BCTRL;
3234 // Add use of X11 (holding environment pointer)
3235 if (isSVR4ABI && isPPC64)
3236 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3237 // Add CTR register as callee so a bctr can be emitted later.
3239 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3242 // If this is a direct call, pass the chain and the callee.
3243 if (Callee.getNode()) {
3244 Ops.push_back(Chain);
3245 Ops.push_back(Callee);
3247 // If this is a tail call add stack pointer delta.
3249 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3251 // Add argument registers to the end of the list so that they are known live
3253 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3254 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3255 RegsToPass[i].second.getValueType()));
3261 bool isLocalCall(const SDValue &Callee)
3263 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3264 return !G->getGlobal()->isDeclaration() &&
3265 !G->getGlobal()->isWeakForLinker();
3270 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3271 CallingConv::ID CallConv, bool isVarArg,
3272 const SmallVectorImpl<ISD::InputArg> &Ins,
3273 SDLoc dl, SelectionDAG &DAG,
3274 SmallVectorImpl<SDValue> &InVals) const {
3276 SmallVector<CCValAssign, 16> RVLocs;
3277 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3278 getTargetMachine(), RVLocs, *DAG.getContext());
3279 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3281 // Copy all of the result registers out of their specified physreg.
3282 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3283 CCValAssign &VA = RVLocs[i];
3284 assert(VA.isRegLoc() && "Can only return in registers!");
3286 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3287 VA.getLocReg(), VA.getLocVT(), InFlag);
3288 Chain = Val.getValue(1);
3289 InFlag = Val.getValue(2);
3291 switch (VA.getLocInfo()) {
3292 default: llvm_unreachable("Unknown loc info!");
3293 case CCValAssign::Full: break;
3294 case CCValAssign::AExt:
3295 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3297 case CCValAssign::ZExt:
3298 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3299 DAG.getValueType(VA.getValVT()));
3300 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3302 case CCValAssign::SExt:
3303 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3304 DAG.getValueType(VA.getValVT()));
3305 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3309 InVals.push_back(Val);
3316 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
3317 bool isTailCall, bool isVarArg,
3319 SmallVector<std::pair<unsigned, SDValue>, 8>
3321 SDValue InFlag, SDValue Chain,
3323 int SPDiff, unsigned NumBytes,
3324 const SmallVectorImpl<ISD::InputArg> &Ins,
3325 SmallVectorImpl<SDValue> &InVals) const {
3326 std::vector<EVT> NodeTys;
3327 SmallVector<SDValue, 8> Ops;
3328 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
3329 isTailCall, RegsToPass, Ops, NodeTys,
3332 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3333 if (isVarArg && PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64())
3334 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3336 // When performing tail call optimization the callee pops its arguments off
3337 // the stack. Account for this here so these bytes can be pushed back on in
3338 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3339 int BytesCalleePops =
3340 (CallConv == CallingConv::Fast &&
3341 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3343 // Add a register mask operand representing the call-preserved registers.
3344 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
3345 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3346 assert(Mask && "Missing call preserved mask for calling convention");
3347 Ops.push_back(DAG.getRegisterMask(Mask));
3349 if (InFlag.getNode())
3350 Ops.push_back(InFlag);
3354 assert(((Callee.getOpcode() == ISD::Register &&
3355 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3356 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3357 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3358 isa<ConstantSDNode>(Callee)) &&
3359 "Expecting an global address, external symbol, absolute value or register");
3361 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size());
3364 // Add a NOP immediately after the branch instruction when using the 64-bit
3365 // SVR4 ABI. At link time, if caller and callee are in a different module and
3366 // thus have a different TOC, the call will be replaced with a call to a stub
3367 // function which saves the current TOC, loads the TOC of the callee and
3368 // branches to the callee. The NOP will be replaced with a load instruction
3369 // which restores the TOC of the caller from the TOC save slot of the current
3370 // stack frame. If caller and callee belong to the same module (and have the
3371 // same TOC), the NOP will remain unchanged.
3373 bool needsTOCRestore = false;
3374 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) {
3375 if (CallOpc == PPCISD::BCTRL) {
3376 // This is a call through a function pointer.
3377 // Restore the caller TOC from the save area into R2.
3378 // See PrepareCall() for more information about calls through function
3379 // pointers in the 64-bit SVR4 ABI.
3380 // We are using a target-specific load with r2 hard coded, because the
3381 // result of a target-independent load would never go directly into r2,
3382 // since r2 is a reserved register (which prevents the register allocator
3383 // from allocating it), resulting in an additional register being
3384 // allocated and an unnecessary move instruction being generated.
3385 needsTOCRestore = true;
3386 } else if ((CallOpc == PPCISD::CALL) && !isLocalCall(Callee)) {
3387 // Otherwise insert NOP for non-local calls.
3388 CallOpc = PPCISD::CALL_NOP;
3392 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
3393 InFlag = Chain.getValue(1);
3395 if (needsTOCRestore) {
3396 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3397 Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag);
3398 InFlag = Chain.getValue(1);
3401 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3402 DAG.getIntPtrConstant(BytesCalleePops, true),
3405 InFlag = Chain.getValue(1);
3407 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3408 Ins, dl, DAG, InVals);
3412 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3413 SmallVectorImpl<SDValue> &InVals) const {
3414 SelectionDAG &DAG = CLI.DAG;
3416 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
3417 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
3418 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
3419 SDValue Chain = CLI.Chain;
3420 SDValue Callee = CLI.Callee;
3421 bool &isTailCall = CLI.IsTailCall;
3422 CallingConv::ID CallConv = CLI.CallConv;
3423 bool isVarArg = CLI.IsVarArg;
3426 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3429 if (PPCSubTarget.isSVR4ABI()) {
3430 if (PPCSubTarget.isPPC64())
3431 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3432 isTailCall, Outs, OutVals, Ins,
3435 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3436 isTailCall, Outs, OutVals, Ins,
3440 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
3441 isTailCall, Outs, OutVals, Ins,
3446 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
3447 CallingConv::ID CallConv, bool isVarArg,
3449 const SmallVectorImpl<ISD::OutputArg> &Outs,
3450 const SmallVectorImpl<SDValue> &OutVals,
3451 const SmallVectorImpl<ISD::InputArg> &Ins,
3452 SDLoc dl, SelectionDAG &DAG,
3453 SmallVectorImpl<SDValue> &InVals) const {
3454 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
3455 // of the 32-bit SVR4 ABI stack frame layout.
3457 assert((CallConv == CallingConv::C ||
3458 CallConv == CallingConv::Fast) && "Unknown calling convention!");
3460 unsigned PtrByteSize = 4;
3462 MachineFunction &MF = DAG.getMachineFunction();
3464 // Mark this function as potentially containing a function that contains a
3465 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3466 // and restoring the callers stack pointer in this functions epilog. This is
3467 // done because by tail calling the called function might overwrite the value
3468 // in this function's (MF) stack pointer stack slot 0(SP).
3469 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3470 CallConv == CallingConv::Fast)
3471 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3473 // Count how many bytes are to be pushed on the stack, including the linkage
3474 // area, parameter list area and the part of the local variable space which
3475 // contains copies of aggregates which are passed by value.
3477 // Assign locations to all of the outgoing arguments.
3478 SmallVector<CCValAssign, 16> ArgLocs;
3479 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3480 getTargetMachine(), ArgLocs, *DAG.getContext());
3482 // Reserve space for the linkage area on the stack.
3483 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
3486 // Handle fixed and variable vector arguments differently.
3487 // Fixed vector arguments go into registers as long as registers are
3488 // available. Variable vector arguments always go into memory.
3489 unsigned NumArgs = Outs.size();
3491 for (unsigned i = 0; i != NumArgs; ++i) {
3492 MVT ArgVT = Outs[i].VT;
3493 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3496 if (Outs[i].IsFixed) {
3497 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
3500 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
3506 errs() << "Call operand #" << i << " has unhandled type "
3507 << EVT(ArgVT).getEVTString() << "\n";
3509 llvm_unreachable(0);
3513 // All arguments are treated the same.
3514 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
3517 // Assign locations to all of the outgoing aggregate by value arguments.
3518 SmallVector<CCValAssign, 16> ByValArgLocs;
3519 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3520 getTargetMachine(), ByValArgLocs, *DAG.getContext());
3522 // Reserve stack space for the allocations in CCInfo.
3523 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
3525 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
3527 // Size of the linkage area, parameter list area and the part of the local
3528 // space variable where copies of aggregates which are passed by value are
3530 unsigned NumBytes = CCByValInfo.getNextStackOffset();
3532 // Calculate by how many bytes the stack has to be adjusted in case of tail
3533 // call optimization.
3534 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3536 // Adjust the stack pointer for the new arguments...
3537 // These operations are automatically eliminated by the prolog/epilog pass
3538 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
3540 SDValue CallSeqStart = Chain;
3542 // Load the return address and frame pointer so it can be moved somewhere else
3545 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
3548 // Set up a copy of the stack pointer for use loading and storing any
3549 // arguments that may not fit in the registers available for argument
3551 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3553 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3554 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3555 SmallVector<SDValue, 8> MemOpChains;
3557 bool seenFloatArg = false;
3558 // Walk the register/memloc assignments, inserting copies/loads.
3559 for (unsigned i = 0, j = 0, e = ArgLocs.size();
3562 CCValAssign &VA = ArgLocs[i];
3563 SDValue Arg = OutVals[i];
3564 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3566 if (Flags.isByVal()) {
3567 // Argument is an aggregate which is passed by value, thus we need to
3568 // create a copy of it in the local variable space of the current stack
3569 // frame (which is the stack frame of the caller) and pass the address of
3570 // this copy to the callee.
3571 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
3572 CCValAssign &ByValVA = ByValArgLocs[j++];
3573 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
3575 // Memory reserved in the local variable space of the callers stack frame.
3576 unsigned LocMemOffset = ByValVA.getLocMemOffset();
3578 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3579 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3581 // Create a copy of the argument in the local area of the current
3583 SDValue MemcpyCall =
3584 CreateCopyOfByValArgument(Arg, PtrOff,
3585 CallSeqStart.getNode()->getOperand(0),
3588 // This must go outside the CALLSEQ_START..END.
3589 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3590 CallSeqStart.getNode()->getOperand(1),
3592 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3593 NewCallSeqStart.getNode());
3594 Chain = CallSeqStart = NewCallSeqStart;
3596 // Pass the address of the aggregate copy on the stack either in a
3597 // physical register or in the parameter list area of the current stack
3598 // frame to the callee.
3602 if (VA.isRegLoc()) {
3603 seenFloatArg |= VA.getLocVT().isFloatingPoint();
3604 // Put argument in a physical register.
3605 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3607 // Put argument in the parameter list area of the current stack frame.
3608 assert(VA.isMemLoc());
3609 unsigned LocMemOffset = VA.getLocMemOffset();
3612 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3613 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3615 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3616 MachinePointerInfo(),
3619 // Calculate and remember argument location.
3620 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
3626 if (!MemOpChains.empty())
3627 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3628 &MemOpChains[0], MemOpChains.size());
3630 // Build a sequence of copy-to-reg nodes chained together with token chain
3631 // and flag operands which copy the outgoing args into the appropriate regs.
3633 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3634 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3635 RegsToPass[i].second, InFlag);
3636 InFlag = Chain.getValue(1);
3639 // Set CR bit 6 to true if this is a vararg call with floating args passed in
3642 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3643 SDValue Ops[] = { Chain, InFlag };
3645 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
3646 dl, VTs, Ops, InFlag.getNode() ? 2 : 1);
3648 InFlag = Chain.getValue(1);
3652 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
3653 false, TailCallArguments);
3655 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3656 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3660 // Copy an argument into memory, being careful to do this outside the
3661 // call sequence for the call to which the argument belongs.
3663 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
3664 SDValue CallSeqStart,
3665 ISD::ArgFlagsTy Flags,
3668 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
3669 CallSeqStart.getNode()->getOperand(0),
3671 // The MEMCPY must go outside the CALLSEQ_START..END.
3672 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3673 CallSeqStart.getNode()->getOperand(1),
3675 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3676 NewCallSeqStart.getNode());
3677 return NewCallSeqStart;
3681 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
3682 CallingConv::ID CallConv, bool isVarArg,
3684 const SmallVectorImpl<ISD::OutputArg> &Outs,
3685 const SmallVectorImpl<SDValue> &OutVals,
3686 const SmallVectorImpl<ISD::InputArg> &Ins,
3687 SDLoc dl, SelectionDAG &DAG,
3688 SmallVectorImpl<SDValue> &InVals) const {
3690 unsigned NumOps = Outs.size();
3692 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3693 unsigned PtrByteSize = 8;
3695 MachineFunction &MF = DAG.getMachineFunction();
3697 // Mark this function as potentially containing a function that contains a
3698 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3699 // and restoring the callers stack pointer in this functions epilog. This is
3700 // done because by tail calling the called function might overwrite the value
3701 // in this function's (MF) stack pointer stack slot 0(SP).
3702 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3703 CallConv == CallingConv::Fast)
3704 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3706 unsigned nAltivecParamsAtEnd = 0;
3708 // Count how many bytes are to be pushed on the stack, including the linkage
3709 // area, and parameter passing area. We start with at least 48 bytes, which
3710 // is reserved space for [SP][CR][LR][3 x unused].
3711 // NOTE: For PPC64, nAltivecParamsAtEnd always remains zero as a result
3714 CalculateParameterAndLinkageAreaSize(DAG, true, isVarArg, CallConv,
3715 Outs, OutVals, nAltivecParamsAtEnd);
3717 // Calculate by how many bytes the stack has to be adjusted in case of tail
3718 // call optimization.
3719 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3721 // To protect arguments on the stack from being clobbered in a tail call,
3722 // force all the loads to happen before doing any other lowering.
3724 Chain = DAG.getStackArgumentTokenFactor(Chain);
3726 // Adjust the stack pointer for the new arguments...
3727 // These operations are automatically eliminated by the prolog/epilog pass
3728 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
3730 SDValue CallSeqStart = Chain;
3732 // Load the return address and frame pointer so it can be move somewhere else
3735 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
3738 // Set up a copy of the stack pointer for use loading and storing any
3739 // arguments that may not fit in the registers available for argument
3741 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3743 // Figure out which arguments are going to go in registers, and which in
3744 // memory. Also, if this is a vararg function, floating point operations
3745 // must be stored to our stack, and loaded into integer regs as well, if
3746 // any integer regs are available for argument passing.
3747 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
3748 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3750 static const uint16_t GPR[] = {
3751 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3752 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3754 static const uint16_t *FPR = GetFPR();
3756 static const uint16_t VR[] = {
3757 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3758 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3760 const unsigned NumGPRs = array_lengthof(GPR);
3761 const unsigned NumFPRs = 13;
3762 const unsigned NumVRs = array_lengthof(VR);
3764 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3765 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3767 SmallVector<SDValue, 8> MemOpChains;
3768 for (unsigned i = 0; i != NumOps; ++i) {
3769 SDValue Arg = OutVals[i];
3770 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3772 // PtrOff will be used to store the current argument to the stack if a
3773 // register cannot be found for it.
3776 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
3778 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
3780 // Promote integers to 64-bit values.
3781 if (Arg.getValueType() == MVT::i32) {
3782 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
3783 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3784 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
3787 // FIXME memcpy is used way more than necessary. Correctness first.
3788 // Note: "by value" is code for passing a structure by value, not
3790 if (Flags.isByVal()) {
3791 // Note: Size includes alignment padding, so
3792 // struct x { short a; char b; }
3793 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
3794 // These are the proper values we need for right-justifying the
3795 // aggregate in a parameter register.
3796 unsigned Size = Flags.getByValSize();
3798 // An empty aggregate parameter takes up no storage and no
3803 // All aggregates smaller than 8 bytes must be passed right-justified.
3804 if (Size==1 || Size==2 || Size==4) {
3805 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
3806 if (GPR_idx != NumGPRs) {
3807 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
3808 MachinePointerInfo(), VT,
3810 MemOpChains.push_back(Load.getValue(1));
3811 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3813 ArgOffset += PtrByteSize;
3818 if (GPR_idx == NumGPRs && Size < 8) {
3819 SDValue Const = DAG.getConstant(PtrByteSize - Size,
3820 PtrOff.getValueType());
3821 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3822 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
3825 ArgOffset += PtrByteSize;
3828 // Copy entire object into memory. There are cases where gcc-generated
3829 // code assumes it is there, even if it could be put entirely into
3830 // registers. (This is not what the doc says.)
3832 // FIXME: The above statement is likely due to a misunderstanding of the
3833 // documents. All arguments must be copied into the parameter area BY
3834 // THE CALLEE in the event that the callee takes the address of any
3835 // formal argument. That has not yet been implemented. However, it is
3836 // reasonable to use the stack area as a staging area for the register
3839 // Skip this for small aggregates, as we will use the same slot for a
3840 // right-justified copy, below.
3842 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
3846 // When a register is available, pass a small aggregate right-justified.
3847 if (Size < 8 && GPR_idx != NumGPRs) {
3848 // The easiest way to get this right-justified in a register
3849 // is to copy the structure into the rightmost portion of a
3850 // local variable slot, then load the whole slot into the
3852 // FIXME: The memcpy seems to produce pretty awful code for
3853 // small aggregates, particularly for packed ones.
3854 // FIXME: It would be preferable to use the slot in the
3855 // parameter save area instead of a new local variable.
3856 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
3857 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3858 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
3862 // Load the slot into the register.
3863 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
3864 MachinePointerInfo(),
3865 false, false, false, 0);
3866 MemOpChains.push_back(Load.getValue(1));
3867 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3869 // Done with this argument.
3870 ArgOffset += PtrByteSize;
3874 // For aggregates larger than PtrByteSize, copy the pieces of the
3875 // object that fit into registers from the parameter save area.
3876 for (unsigned j=0; j<Size; j+=PtrByteSize) {
3877 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
3878 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
3879 if (GPR_idx != NumGPRs) {
3880 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
3881 MachinePointerInfo(),
3882 false, false, false, 0);
3883 MemOpChains.push_back(Load.getValue(1));
3884 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3885 ArgOffset += PtrByteSize;
3887 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
3894 switch (Arg.getValueType().getSimpleVT().SimpleTy) {
3895 default: llvm_unreachable("Unexpected ValueType for argument!");
3898 if (GPR_idx != NumGPRs) {
3899 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
3901 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3902 true, isTailCall, false, MemOpChains,
3903 TailCallArguments, dl);
3905 ArgOffset += PtrByteSize;
3909 if (FPR_idx != NumFPRs) {
3910 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
3913 // A single float or an aggregate containing only a single float
3914 // must be passed right-justified in the stack doubleword, and
3915 // in the GPR, if one is available.
3917 if (Arg.getValueType().getSimpleVT().SimpleTy == MVT::f32) {
3918 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
3919 StoreOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
3923 SDValue Store = DAG.getStore(Chain, dl, Arg, StoreOff,
3924 MachinePointerInfo(), false, false, 0);
3925 MemOpChains.push_back(Store);
3927 // Float varargs are always shadowed in available integer registers
3928 if (GPR_idx != NumGPRs) {
3929 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
3930 MachinePointerInfo(), false, false,
3932 MemOpChains.push_back(Load.getValue(1));
3933 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3935 } else if (GPR_idx != NumGPRs)
3936 // If we have any FPRs remaining, we may also have GPRs remaining.
3939 // Single-precision floating-point values are mapped to the
3940 // second (rightmost) word of the stack doubleword.
3941 if (Arg.getValueType() == MVT::f32) {
3942 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
3943 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
3946 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3947 true, isTailCall, false, MemOpChains,
3948 TailCallArguments, dl);
3957 // These go aligned on the stack, or in the corresponding R registers
3958 // when within range. The Darwin PPC ABI doc claims they also go in
3959 // V registers; in fact gcc does this only for arguments that are
3960 // prototyped, not for those that match the ... We do it for all
3961 // arguments, seems to work.
3962 while (ArgOffset % 16 !=0) {
3963 ArgOffset += PtrByteSize;
3964 if (GPR_idx != NumGPRs)
3967 // We could elide this store in the case where the object fits
3968 // entirely in R registers. Maybe later.
3969 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3970 DAG.getConstant(ArgOffset, PtrVT));
3971 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
3972 MachinePointerInfo(), false, false, 0);
3973 MemOpChains.push_back(Store);
3974 if (VR_idx != NumVRs) {
3975 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
3976 MachinePointerInfo(),
3977 false, false, false, 0);
3978 MemOpChains.push_back(Load.getValue(1));
3979 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
3982 for (unsigned i=0; i<16; i+=PtrByteSize) {
3983 if (GPR_idx == NumGPRs)
3985 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
3986 DAG.getConstant(i, PtrVT));
3987 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
3988 false, false, false, 0);
3989 MemOpChains.push_back(Load.getValue(1));
3990 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3995 // Non-varargs Altivec params generally go in registers, but have
3996 // stack space allocated at the end.
3997 if (VR_idx != NumVRs) {
3998 // Doesn't have GPR space allocated.
3999 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4001 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4002 true, isTailCall, true, MemOpChains,
4003 TailCallArguments, dl);
4010 if (!MemOpChains.empty())
4011 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4012 &MemOpChains[0], MemOpChains.size());
4014 // Check if this is an indirect call (MTCTR/BCTRL).
4015 // See PrepareCall() for more information about calls through function
4016 // pointers in the 64-bit SVR4 ABI.
4018 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4019 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4020 !isBLACompatibleAddress(Callee, DAG)) {
4021 // Load r2 into a virtual register and store it to the TOC save area.
4022 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4023 // TOC save area offset.
4024 SDValue PtrOff = DAG.getIntPtrConstant(40);
4025 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4026 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
4028 // R12 must contain the address of an indirect callee. This does not
4029 // mean the MTCTR instruction must use R12; it's easier to model this
4030 // as an extra parameter, so do that.
4031 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
4034 // Build a sequence of copy-to-reg nodes chained together with token chain
4035 // and flag operands which copy the outgoing args into the appropriate regs.
4037 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4038 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4039 RegsToPass[i].second, InFlag);
4040 InFlag = Chain.getValue(1);
4044 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4045 FPOp, true, TailCallArguments);
4047 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4048 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4053 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4054 CallingConv::ID CallConv, bool isVarArg,
4056 const SmallVectorImpl<ISD::OutputArg> &Outs,
4057 const SmallVectorImpl<SDValue> &OutVals,
4058 const SmallVectorImpl<ISD::InputArg> &Ins,
4059 SDLoc dl, SelectionDAG &DAG,
4060 SmallVectorImpl<SDValue> &InVals) const {
4062 unsigned NumOps = Outs.size();
4064 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4065 bool isPPC64 = PtrVT == MVT::i64;
4066 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4068 MachineFunction &MF = DAG.getMachineFunction();
4070 // Mark this function as potentially containing a function that contains a
4071 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4072 // and restoring the callers stack pointer in this functions epilog. This is
4073 // done because by tail calling the called function might overwrite the value
4074 // in this function's (MF) stack pointer stack slot 0(SP).
4075 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4076 CallConv == CallingConv::Fast)
4077 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4079 unsigned nAltivecParamsAtEnd = 0;
4081 // Count how many bytes are to be pushed on the stack, including the linkage
4082 // area, and parameter passing area. We start with 24/48 bytes, which is
4083 // prereserved space for [SP][CR][LR][3 x unused].
4085 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv,
4087 nAltivecParamsAtEnd);
4089 // Calculate by how many bytes the stack has to be adjusted in case of tail
4090 // call optimization.
4091 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4093 // To protect arguments on the stack from being clobbered in a tail call,
4094 // force all the loads to happen before doing any other lowering.
4096 Chain = DAG.getStackArgumentTokenFactor(Chain);
4098 // Adjust the stack pointer for the new arguments...
4099 // These operations are automatically eliminated by the prolog/epilog pass
4100 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4102 SDValue CallSeqStart = Chain;
4104 // Load the return address and frame pointer so it can be move somewhere else
4107 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4110 // Set up a copy of the stack pointer for use loading and storing any
4111 // arguments that may not fit in the registers available for argument
4115 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4117 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4119 // Figure out which arguments are going to go in registers, and which in
4120 // memory. Also, if this is a vararg function, floating point operations
4121 // must be stored to our stack, and loaded into integer regs as well, if
4122 // any integer regs are available for argument passing.
4123 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
4124 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4126 static const uint16_t GPR_32[] = { // 32-bit registers.
4127 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4128 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4130 static const uint16_t GPR_64[] = { // 64-bit registers.
4131 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4132 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4134 static const uint16_t *FPR = GetFPR();
4136 static const uint16_t VR[] = {
4137 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4138 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4140 const unsigned NumGPRs = array_lengthof(GPR_32);
4141 const unsigned NumFPRs = 13;
4142 const unsigned NumVRs = array_lengthof(VR);
4144 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
4146 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4147 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4149 SmallVector<SDValue, 8> MemOpChains;
4150 for (unsigned i = 0; i != NumOps; ++i) {
4151 SDValue Arg = OutVals[i];
4152 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4154 // PtrOff will be used to store the current argument to the stack if a
4155 // register cannot be found for it.
4158 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4160 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4162 // On PPC64, promote integers to 64-bit values.
4163 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4164 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4165 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4166 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4169 // FIXME memcpy is used way more than necessary. Correctness first.
4170 // Note: "by value" is code for passing a structure by value, not
4172 if (Flags.isByVal()) {
4173 unsigned Size = Flags.getByValSize();
4174 // Very small objects are passed right-justified. Everything else is
4175 // passed left-justified.
4176 if (Size==1 || Size==2) {
4177 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4178 if (GPR_idx != NumGPRs) {
4179 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4180 MachinePointerInfo(), VT,
4182 MemOpChains.push_back(Load.getValue(1));
4183 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4185 ArgOffset += PtrByteSize;
4187 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4188 PtrOff.getValueType());
4189 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4190 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4193 ArgOffset += PtrByteSize;
4197 // Copy entire object into memory. There are cases where gcc-generated
4198 // code assumes it is there, even if it could be put entirely into
4199 // registers. (This is not what the doc says.)
4200 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4204 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4205 // copy the pieces of the object that fit into registers from the
4206 // parameter save area.
4207 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4208 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4209 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4210 if (GPR_idx != NumGPRs) {
4211 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4212 MachinePointerInfo(),
4213 false, false, false, 0);
4214 MemOpChains.push_back(Load.getValue(1));
4215 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4216 ArgOffset += PtrByteSize;
4218 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4225 switch (Arg.getValueType().getSimpleVT().SimpleTy) {
4226 default: llvm_unreachable("Unexpected ValueType for argument!");
4229 if (GPR_idx != NumGPRs) {
4230 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4232 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4233 isPPC64, isTailCall, false, MemOpChains,
4234 TailCallArguments, dl);
4236 ArgOffset += PtrByteSize;
4240 if (FPR_idx != NumFPRs) {
4241 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4244 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4245 MachinePointerInfo(), false, false, 0);
4246 MemOpChains.push_back(Store);
4248 // Float varargs are always shadowed in available integer registers
4249 if (GPR_idx != NumGPRs) {
4250 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4251 MachinePointerInfo(), false, false,
4253 MemOpChains.push_back(Load.getValue(1));
4254 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4256 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4257 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4258 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4259 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4260 MachinePointerInfo(),
4261 false, false, false, 0);
4262 MemOpChains.push_back(Load.getValue(1));
4263 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4266 // If we have any FPRs remaining, we may also have GPRs remaining.
4267 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4269 if (GPR_idx != NumGPRs)
4271 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4272 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4276 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4277 isPPC64, isTailCall, false, MemOpChains,
4278 TailCallArguments, dl);
4282 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4289 // These go aligned on the stack, or in the corresponding R registers
4290 // when within range. The Darwin PPC ABI doc claims they also go in
4291 // V registers; in fact gcc does this only for arguments that are
4292 // prototyped, not for those that match the ... We do it for all
4293 // arguments, seems to work.
4294 while (ArgOffset % 16 !=0) {
4295 ArgOffset += PtrByteSize;
4296 if (GPR_idx != NumGPRs)
4299 // We could elide this store in the case where the object fits
4300 // entirely in R registers. Maybe later.
4301 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4302 DAG.getConstant(ArgOffset, PtrVT));
4303 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4304 MachinePointerInfo(), false, false, 0);
4305 MemOpChains.push_back(Store);
4306 if (VR_idx != NumVRs) {
4307 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4308 MachinePointerInfo(),
4309 false, false, false, 0);
4310 MemOpChains.push_back(Load.getValue(1));
4311 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4314 for (unsigned i=0; i<16; i+=PtrByteSize) {
4315 if (GPR_idx == NumGPRs)
4317 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4318 DAG.getConstant(i, PtrVT));
4319 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4320 false, false, false, 0);
4321 MemOpChains.push_back(Load.getValue(1));
4322 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4327 // Non-varargs Altivec params generally go in registers, but have
4328 // stack space allocated at the end.
4329 if (VR_idx != NumVRs) {
4330 // Doesn't have GPR space allocated.
4331 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4332 } else if (nAltivecParamsAtEnd==0) {
4333 // We are emitting Altivec params in order.
4334 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4335 isPPC64, isTailCall, true, MemOpChains,
4336 TailCallArguments, dl);
4342 // If all Altivec parameters fit in registers, as they usually do,
4343 // they get stack space following the non-Altivec parameters. We
4344 // don't track this here because nobody below needs it.
4345 // If there are more Altivec parameters than fit in registers emit
4347 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
4349 // Offset is aligned; skip 1st 12 params which go in V registers.
4350 ArgOffset = ((ArgOffset+15)/16)*16;
4352 for (unsigned i = 0; i != NumOps; ++i) {
4353 SDValue Arg = OutVals[i];
4354 EVT ArgType = Outs[i].VT;
4355 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
4356 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
4359 // We are emitting Altivec params in order.
4360 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4361 isPPC64, isTailCall, true, MemOpChains,
4362 TailCallArguments, dl);
4369 if (!MemOpChains.empty())
4370 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4371 &MemOpChains[0], MemOpChains.size());
4373 // On Darwin, R12 must contain the address of an indirect callee. This does
4374 // not mean the MTCTR instruction must use R12; it's easier to model this as
4375 // an extra parameter, so do that.
4377 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4378 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4379 !isBLACompatibleAddress(Callee, DAG))
4380 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
4381 PPC::R12), Callee));
4383 // Build a sequence of copy-to-reg nodes chained together with token chain
4384 // and flag operands which copy the outgoing args into the appropriate regs.
4386 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4387 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4388 RegsToPass[i].second, InFlag);
4389 InFlag = Chain.getValue(1);
4393 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
4394 FPOp, true, TailCallArguments);
4396 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4397 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4402 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
4403 MachineFunction &MF, bool isVarArg,
4404 const SmallVectorImpl<ISD::OutputArg> &Outs,
4405 LLVMContext &Context) const {
4406 SmallVector<CCValAssign, 16> RVLocs;
4407 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
4409 return CCInfo.CheckReturn(Outs, RetCC_PPC);
4413 PPCTargetLowering::LowerReturn(SDValue Chain,
4414 CallingConv::ID CallConv, bool isVarArg,
4415 const SmallVectorImpl<ISD::OutputArg> &Outs,
4416 const SmallVectorImpl<SDValue> &OutVals,
4417 SDLoc dl, SelectionDAG &DAG) const {
4419 SmallVector<CCValAssign, 16> RVLocs;
4420 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4421 getTargetMachine(), RVLocs, *DAG.getContext());
4422 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
4425 SmallVector<SDValue, 4> RetOps(1, Chain);
4427 // Copy the result values into the output registers.
4428 for (unsigned i = 0; i != RVLocs.size(); ++i) {
4429 CCValAssign &VA = RVLocs[i];
4430 assert(VA.isRegLoc() && "Can only return in registers!");
4432 SDValue Arg = OutVals[i];
4434 switch (VA.getLocInfo()) {
4435 default: llvm_unreachable("Unknown loc info!");
4436 case CCValAssign::Full: break;
4437 case CCValAssign::AExt:
4438 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
4440 case CCValAssign::ZExt:
4441 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
4443 case CCValAssign::SExt:
4444 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
4448 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
4449 Flag = Chain.getValue(1);
4450 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
4453 RetOps[0] = Chain; // Update chain.
4455 // Add the flag if we have it.
4457 RetOps.push_back(Flag);
4459 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other,
4460 &RetOps[0], RetOps.size());
4463 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
4464 const PPCSubtarget &Subtarget) const {
4465 // When we pop the dynamic allocation we need to restore the SP link.
4468 // Get the corect type for pointers.
4469 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4471 // Construct the stack pointer operand.
4472 bool isPPC64 = Subtarget.isPPC64();
4473 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
4474 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
4476 // Get the operands for the STACKRESTORE.
4477 SDValue Chain = Op.getOperand(0);
4478 SDValue SaveSP = Op.getOperand(1);
4480 // Load the old link SP.
4481 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
4482 MachinePointerInfo(),
4483 false, false, false, 0);
4485 // Restore the stack pointer.
4486 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
4488 // Store the old link SP.
4489 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
4496 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
4497 MachineFunction &MF = DAG.getMachineFunction();
4498 bool isPPC64 = PPCSubTarget.isPPC64();
4499 bool isDarwinABI = PPCSubTarget.isDarwinABI();
4500 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4502 // Get current frame pointer save index. The users of this index will be
4503 // primarily DYNALLOC instructions.
4504 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4505 int RASI = FI->getReturnAddrSaveIndex();
4507 // If the frame pointer save index hasn't been defined yet.
4509 // Find out what the fix offset of the frame pointer save area.
4510 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
4511 // Allocate the frame index for frame pointer save area.
4512 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
4514 FI->setReturnAddrSaveIndex(RASI);
4516 return DAG.getFrameIndex(RASI, PtrVT);
4520 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
4521 MachineFunction &MF = DAG.getMachineFunction();
4522 bool isPPC64 = PPCSubTarget.isPPC64();
4523 bool isDarwinABI = PPCSubTarget.isDarwinABI();
4524 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4526 // Get current frame pointer save index. The users of this index will be
4527 // primarily DYNALLOC instructions.
4528 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4529 int FPSI = FI->getFramePointerSaveIndex();
4531 // If the frame pointer save index hasn't been defined yet.
4533 // Find out what the fix offset of the frame pointer save area.
4534 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
4537 // Allocate the frame index for frame pointer save area.
4538 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
4540 FI->setFramePointerSaveIndex(FPSI);
4542 return DAG.getFrameIndex(FPSI, PtrVT);
4545 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
4547 const PPCSubtarget &Subtarget) const {
4549 SDValue Chain = Op.getOperand(0);
4550 SDValue Size = Op.getOperand(1);
4553 // Get the corect type for pointers.
4554 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4556 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
4557 DAG.getConstant(0, PtrVT), Size);
4558 // Construct a node for the frame pointer save index.
4559 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
4560 // Build a DYNALLOC node.
4561 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
4562 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
4563 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3);
4566 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
4567 SelectionDAG &DAG) const {
4569 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
4570 DAG.getVTList(MVT::i32, MVT::Other),
4571 Op.getOperand(0), Op.getOperand(1));
4574 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
4575 SelectionDAG &DAG) const {
4577 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
4578 Op.getOperand(0), Op.getOperand(1));
4581 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
4583 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
4584 // Not FP? Not a fsel.
4585 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
4586 !Op.getOperand(2).getValueType().isFloatingPoint())
4589 // We might be able to do better than this under some circumstances, but in
4590 // general, fsel-based lowering of select is a finite-math-only optimization.
4591 // For more information, see section F.3 of the 2.06 ISA specification.
4592 if (!DAG.getTarget().Options.NoInfsFPMath ||
4593 !DAG.getTarget().Options.NoNaNsFPMath)
4596 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4598 EVT ResVT = Op.getValueType();
4599 EVT CmpVT = Op.getOperand(0).getValueType();
4600 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4601 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
4604 // If the RHS of the comparison is a 0.0, we don't need to do the
4605 // subtraction at all.
4607 if (isFloatingPointZero(RHS))
4609 default: break; // SETUO etc aren't handled by fsel.
4613 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4614 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4615 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
4616 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
4617 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
4618 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4619 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
4622 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
4625 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4626 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4627 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
4630 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
4633 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4634 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4635 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4636 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
4641 default: break; // SETUO etc aren't handled by fsel.
4645 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4646 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4647 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4648 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4649 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
4650 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
4651 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4652 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
4655 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4656 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4657 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4658 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
4661 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4662 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4663 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4664 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4667 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
4668 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4669 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4670 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
4673 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
4674 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4675 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4676 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4681 // FIXME: Split this code up when LegalizeDAGTypes lands.
4682 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
4684 assert(Op.getOperand(0).getValueType().isFloatingPoint());
4685 SDValue Src = Op.getOperand(0);
4686 if (Src.getValueType() == MVT::f32)
4687 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
4690 switch (Op.getValueType().getSimpleVT().SimpleTy) {
4691 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
4693 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
4694 (PPCSubTarget.hasFPCVT() ? PPCISD::FCTIWUZ :
4699 assert((Op.getOpcode() == ISD::FP_TO_SINT || PPCSubTarget.hasFPCVT()) &&
4700 "i64 FP_TO_UINT is supported only with FPCVT");
4701 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
4707 // Convert the FP value to an int value through memory.
4708 bool i32Stack = Op.getValueType() == MVT::i32 && PPCSubTarget.hasSTFIWX() &&
4709 (Op.getOpcode() == ISD::FP_TO_SINT || PPCSubTarget.hasFPCVT());
4710 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
4711 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
4712 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
4714 // Emit a store to the stack slot.
4717 MachineFunction &MF = DAG.getMachineFunction();
4718 MachineMemOperand *MMO =
4719 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
4720 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
4721 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
4722 DAG.getVTList(MVT::Other), Ops, array_lengthof(Ops),
4725 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
4726 MPI, false, false, 0);
4728 // Result is a load from the stack slot. If loading 4 bytes, make sure to
4730 if (Op.getValueType() == MVT::i32 && !i32Stack) {
4731 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
4732 DAG.getConstant(4, FIPtr.getValueType()));
4733 MPI = MachinePointerInfo();
4736 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MPI,
4737 false, false, false, 0);
4740 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
4741 SelectionDAG &DAG) const {
4743 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
4744 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
4747 assert((Op.getOpcode() == ISD::SINT_TO_FP || PPCSubTarget.hasFPCVT()) &&
4748 "UINT_TO_FP is supported only with FPCVT");
4750 // If we have FCFIDS, then use it when converting to single-precision.
4751 // Otherwise, convert to double-precision and then round.
4752 unsigned FCFOp = (PPCSubTarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
4753 (Op.getOpcode() == ISD::UINT_TO_FP ?
4754 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
4755 (Op.getOpcode() == ISD::UINT_TO_FP ?
4756 PPCISD::FCFIDU : PPCISD::FCFID);
4757 MVT FCFTy = (PPCSubTarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
4758 MVT::f32 : MVT::f64;
4760 if (Op.getOperand(0).getValueType() == MVT::i64) {
4761 SDValue SINT = Op.getOperand(0);
4762 // When converting to single-precision, we actually need to convert
4763 // to double-precision first and then round to single-precision.
4764 // To avoid double-rounding effects during that operation, we have
4765 // to prepare the input operand. Bits that might be truncated when
4766 // converting to double-precision are replaced by a bit that won't
4767 // be lost at this stage, but is below the single-precision rounding
4770 // However, if -enable-unsafe-fp-math is in effect, accept double
4771 // rounding to avoid the extra overhead.
4772 if (Op.getValueType() == MVT::f32 &&
4773 !PPCSubTarget.hasFPCVT() &&
4774 !DAG.getTarget().Options.UnsafeFPMath) {
4776 // Twiddle input to make sure the low 11 bits are zero. (If this
4777 // is the case, we are guaranteed the value will fit into the 53 bit
4778 // mantissa of an IEEE double-precision value without rounding.)
4779 // If any of those low 11 bits were not zero originally, make sure
4780 // bit 12 (value 2048) is set instead, so that the final rounding
4781 // to single-precision gets the correct result.
4782 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
4783 SINT, DAG.getConstant(2047, MVT::i64));
4784 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
4785 Round, DAG.getConstant(2047, MVT::i64));
4786 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
4787 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
4788 Round, DAG.getConstant(-2048, MVT::i64));
4790 // However, we cannot use that value unconditionally: if the magnitude
4791 // of the input value is small, the bit-twiddling we did above might
4792 // end up visibly changing the output. Fortunately, in that case, we
4793 // don't need to twiddle bits since the original input will convert
4794 // exactly to double-precision floating-point already. Therefore,
4795 // construct a conditional to use the original value if the top 11
4796 // bits are all sign-bit copies, and use the rounded value computed
4798 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
4799 SINT, DAG.getConstant(53, MVT::i32));
4800 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
4801 Cond, DAG.getConstant(1, MVT::i64));
4802 Cond = DAG.getSetCC(dl, MVT::i32,
4803 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
4805 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
4808 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
4809 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
4811 if (Op.getValueType() == MVT::f32 && !PPCSubTarget.hasFPCVT())
4812 FP = DAG.getNode(ISD::FP_ROUND, dl,
4813 MVT::f32, FP, DAG.getIntPtrConstant(0));
4817 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
4818 "Unhandled INT_TO_FP type in custom expander!");
4819 // Since we only generate this in 64-bit mode, we can take advantage of
4820 // 64-bit registers. In particular, sign extend the input value into the
4821 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
4822 // then lfd it and fcfid it.
4823 MachineFunction &MF = DAG.getMachineFunction();
4824 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
4825 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4828 if (PPCSubTarget.hasLFIWAX() || PPCSubTarget.hasFPCVT()) {
4829 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
4830 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4832 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
4833 MachinePointerInfo::getFixedStack(FrameIdx),
4836 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
4837 "Expected an i32 store");
4838 MachineMemOperand *MMO =
4839 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
4840 MachineMemOperand::MOLoad, 4, 4);
4841 SDValue Ops[] = { Store, FIdx };
4842 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
4843 PPCISD::LFIWZX : PPCISD::LFIWAX,
4844 dl, DAG.getVTList(MVT::f64, MVT::Other),
4845 Ops, 2, MVT::i32, MMO);
4847 assert(PPCSubTarget.isPPC64() &&
4848 "i32->FP without LFIWAX supported only on PPC64");
4850 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
4851 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4853 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
4856 // STD the extended value into the stack slot.
4857 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
4858 MachinePointerInfo::getFixedStack(FrameIdx),
4861 // Load the value as a double.
4862 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
4863 MachinePointerInfo::getFixedStack(FrameIdx),
4864 false, false, false, 0);
4867 // FCFID it and return it.
4868 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
4869 if (Op.getValueType() == MVT::f32 && !PPCSubTarget.hasFPCVT())
4870 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
4874 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
4875 SelectionDAG &DAG) const {
4878 The rounding mode is in bits 30:31 of FPSR, and has the following
4885 FLT_ROUNDS, on the other hand, expects the following:
4892 To perform the conversion, we do:
4893 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
4896 MachineFunction &MF = DAG.getMachineFunction();
4897 EVT VT = Op.getValueType();
4898 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4899 SDValue MFFSreg, InFlag;
4901 // Save FP Control Word to register
4903 MVT::f64, // return register
4904 MVT::Glue // unused in this context
4906 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
4908 // Save FP register to stack slot
4909 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
4910 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
4911 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
4912 StackSlot, MachinePointerInfo(), false, false,0);
4914 // Load FP Control Word from low 32 bits of stack slot.
4915 SDValue Four = DAG.getConstant(4, PtrVT);
4916 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
4917 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
4918 false, false, false, 0);
4920 // Transform as necessary
4922 DAG.getNode(ISD::AND, dl, MVT::i32,
4923 CWD, DAG.getConstant(3, MVT::i32));
4925 DAG.getNode(ISD::SRL, dl, MVT::i32,
4926 DAG.getNode(ISD::AND, dl, MVT::i32,
4927 DAG.getNode(ISD::XOR, dl, MVT::i32,
4928 CWD, DAG.getConstant(3, MVT::i32)),
4929 DAG.getConstant(3, MVT::i32)),
4930 DAG.getConstant(1, MVT::i32));
4933 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
4935 return DAG.getNode((VT.getSizeInBits() < 16 ?
4936 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
4939 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
4940 EVT VT = Op.getValueType();
4941 unsigned BitWidth = VT.getSizeInBits();
4943 assert(Op.getNumOperands() == 3 &&
4944 VT == Op.getOperand(1).getValueType() &&
4947 // Expand into a bunch of logical ops. Note that these ops
4948 // depend on the PPC behavior for oversized shift amounts.
4949 SDValue Lo = Op.getOperand(0);
4950 SDValue Hi = Op.getOperand(1);
4951 SDValue Amt = Op.getOperand(2);
4952 EVT AmtVT = Amt.getValueType();
4954 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
4955 DAG.getConstant(BitWidth, AmtVT), Amt);
4956 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
4957 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
4958 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
4959 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
4960 DAG.getConstant(-BitWidth, AmtVT));
4961 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
4962 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
4963 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
4964 SDValue OutOps[] = { OutLo, OutHi };
4965 return DAG.getMergeValues(OutOps, 2, dl);
4968 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
4969 EVT VT = Op.getValueType();
4971 unsigned BitWidth = VT.getSizeInBits();
4972 assert(Op.getNumOperands() == 3 &&
4973 VT == Op.getOperand(1).getValueType() &&
4976 // Expand into a bunch of logical ops. Note that these ops
4977 // depend on the PPC behavior for oversized shift amounts.
4978 SDValue Lo = Op.getOperand(0);
4979 SDValue Hi = Op.getOperand(1);
4980 SDValue Amt = Op.getOperand(2);
4981 EVT AmtVT = Amt.getValueType();
4983 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
4984 DAG.getConstant(BitWidth, AmtVT), Amt);
4985 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
4986 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
4987 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
4988 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
4989 DAG.getConstant(-BitWidth, AmtVT));
4990 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
4991 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
4992 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
4993 SDValue OutOps[] = { OutLo, OutHi };
4994 return DAG.getMergeValues(OutOps, 2, dl);
4997 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
4999 EVT VT = Op.getValueType();
5000 unsigned BitWidth = VT.getSizeInBits();
5001 assert(Op.getNumOperands() == 3 &&
5002 VT == Op.getOperand(1).getValueType() &&
5005 // Expand into a bunch of logical ops, followed by a select_cc.
5006 SDValue Lo = Op.getOperand(0);
5007 SDValue Hi = Op.getOperand(1);
5008 SDValue Amt = Op.getOperand(2);
5009 EVT AmtVT = Amt.getValueType();
5011 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5012 DAG.getConstant(BitWidth, AmtVT), Amt);
5013 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5014 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5015 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5016 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5017 DAG.getConstant(-BitWidth, AmtVT));
5018 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
5019 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
5020 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
5021 Tmp4, Tmp6, ISD::SETLE);
5022 SDValue OutOps[] = { OutLo, OutHi };
5023 return DAG.getMergeValues(OutOps, 2, dl);
5026 //===----------------------------------------------------------------------===//
5027 // Vector related lowering.
5030 /// BuildSplatI - Build a canonical splati of Val with an element size of
5031 /// SplatSize. Cast the result to VT.
5032 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
5033 SelectionDAG &DAG, SDLoc dl) {
5034 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
5036 static const EVT VTys[] = { // canonical VT to use for each size.
5037 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
5040 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
5042 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
5046 EVT CanonicalVT = VTys[SplatSize-1];
5048 // Build a canonical splat for this value.
5049 SDValue Elt = DAG.getConstant(Val, MVT::i32);
5050 SmallVector<SDValue, 8> Ops;
5051 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
5052 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
5053 &Ops[0], Ops.size());
5054 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
5057 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
5058 /// specified intrinsic ID.
5059 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
5060 SelectionDAG &DAG, SDLoc dl,
5061 EVT DestVT = MVT::Other) {
5062 if (DestVT == MVT::Other) DestVT = Op.getValueType();
5063 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5064 DAG.getConstant(IID, MVT::i32), Op);
5067 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
5068 /// specified intrinsic ID.
5069 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
5070 SelectionDAG &DAG, SDLoc dl,
5071 EVT DestVT = MVT::Other) {
5072 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
5073 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5074 DAG.getConstant(IID, MVT::i32), LHS, RHS);
5077 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
5078 /// specified intrinsic ID.
5079 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
5080 SDValue Op2, SelectionDAG &DAG,
5081 SDLoc dl, EVT DestVT = MVT::Other) {
5082 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
5083 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5084 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
5088 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
5089 /// amount. The result has the specified value type.
5090 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
5091 EVT VT, SelectionDAG &DAG, SDLoc dl) {
5092 // Force LHS/RHS to be the right type.
5093 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
5094 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
5097 for (unsigned i = 0; i != 16; ++i)
5099 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
5100 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5103 // If this is a case we can't handle, return null and let the default
5104 // expansion code take care of it. If we CAN select this case, and if it
5105 // selects to a single instruction, return Op. Otherwise, if we can codegen
5106 // this case more efficiently than a constant pool load, lower it to the
5107 // sequence of ops that should be used.
5108 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
5109 SelectionDAG &DAG) const {
5111 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5112 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
5114 // Check if this is a splat of a constant value.
5115 APInt APSplatBits, APSplatUndef;
5116 unsigned SplatBitSize;
5118 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
5119 HasAnyUndefs, 0, true) || SplatBitSize > 32)
5122 unsigned SplatBits = APSplatBits.getZExtValue();
5123 unsigned SplatUndef = APSplatUndef.getZExtValue();
5124 unsigned SplatSize = SplatBitSize / 8;
5126 // First, handle single instruction cases.
5129 if (SplatBits == 0) {
5130 // Canonicalize all zero vectors to be v4i32.
5131 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5132 SDValue Z = DAG.getConstant(0, MVT::i32);
5133 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5134 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
5139 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
5140 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
5142 if (SextVal >= -16 && SextVal <= 15)
5143 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
5146 // Two instruction sequences.
5148 // If this value is in the range [-32,30] and is even, use:
5149 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
5150 // If this value is in the range [17,31] and is odd, use:
5151 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
5152 // If this value is in the range [-31,-17] and is odd, use:
5153 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
5154 // Note the last two are three-instruction sequences.
5155 if (SextVal >= -32 && SextVal <= 31) {
5156 // To avoid having these optimizations undone by constant folding,
5157 // we convert to a pseudo that will be expanded later into one of
5159 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
5160 EVT VT = Op.getValueType();
5161 int Size = VT == MVT::v16i8 ? 1 : (VT == MVT::v8i16 ? 2 : 4);
5162 SDValue EltSize = DAG.getConstant(Size, MVT::i32);
5163 return DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
5166 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
5167 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
5169 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
5170 // Make -1 and vspltisw -1:
5171 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
5173 // Make the VSLW intrinsic, computing 0x8000_0000.
5174 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
5177 // xor by OnesV to invert it.
5178 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5179 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5182 // Check to see if this is a wide variety of vsplti*, binop self cases.
5183 static const signed char SplatCsts[] = {
5184 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
5185 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
5188 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
5189 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
5190 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
5191 int i = SplatCsts[idx];
5193 // Figure out what shift amount will be used by altivec if shifted by i in
5195 unsigned TypeShiftAmt = i & (SplatBitSize-1);
5197 // vsplti + shl self.
5198 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
5199 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5200 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5201 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
5202 Intrinsic::ppc_altivec_vslw
5204 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5205 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5208 // vsplti + srl self.
5209 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5210 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5211 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5212 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
5213 Intrinsic::ppc_altivec_vsrw
5215 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5216 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5219 // vsplti + sra self.
5220 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5221 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5222 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5223 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
5224 Intrinsic::ppc_altivec_vsraw
5226 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5227 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5230 // vsplti + rol self.
5231 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
5232 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
5233 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5234 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5235 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
5236 Intrinsic::ppc_altivec_vrlw
5238 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5239 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5242 // t = vsplti c, result = vsldoi t, t, 1
5243 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
5244 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5245 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
5247 // t = vsplti c, result = vsldoi t, t, 2
5248 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
5249 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5250 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
5252 // t = vsplti c, result = vsldoi t, t, 3
5253 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
5254 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5255 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
5262 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5263 /// the specified operations to build the shuffle.
5264 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5265 SDValue RHS, SelectionDAG &DAG,
5267 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5268 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5269 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5272 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5284 if (OpNum == OP_COPY) {
5285 if (LHSID == (1*9+2)*9+3) return LHS;
5286 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5290 SDValue OpLHS, OpRHS;
5291 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5292 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5296 default: llvm_unreachable("Unknown i32 permute!");
5298 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
5299 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
5300 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
5301 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
5304 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
5305 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
5306 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
5307 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
5310 for (unsigned i = 0; i != 16; ++i)
5311 ShufIdxs[i] = (i&3)+0;
5314 for (unsigned i = 0; i != 16; ++i)
5315 ShufIdxs[i] = (i&3)+4;
5318 for (unsigned i = 0; i != 16; ++i)
5319 ShufIdxs[i] = (i&3)+8;
5322 for (unsigned i = 0; i != 16; ++i)
5323 ShufIdxs[i] = (i&3)+12;
5326 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
5328 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
5330 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
5332 EVT VT = OpLHS.getValueType();
5333 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
5334 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
5335 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
5336 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5339 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
5340 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
5341 /// return the code it can be lowered into. Worst case, it can always be
5342 /// lowered into a vperm.
5343 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5344 SelectionDAG &DAG) const {
5346 SDValue V1 = Op.getOperand(0);
5347 SDValue V2 = Op.getOperand(1);
5348 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5349 EVT VT = Op.getValueType();
5351 // Cases that are handled by instructions that take permute immediates
5352 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
5353 // selected by the instruction selector.
5354 if (V2.getOpcode() == ISD::UNDEF) {
5355 if (PPC::isSplatShuffleMask(SVOp, 1) ||
5356 PPC::isSplatShuffleMask(SVOp, 2) ||
5357 PPC::isSplatShuffleMask(SVOp, 4) ||
5358 PPC::isVPKUWUMShuffleMask(SVOp, true) ||
5359 PPC::isVPKUHUMShuffleMask(SVOp, true) ||
5360 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 ||
5361 PPC::isVMRGLShuffleMask(SVOp, 1, true) ||
5362 PPC::isVMRGLShuffleMask(SVOp, 2, true) ||
5363 PPC::isVMRGLShuffleMask(SVOp, 4, true) ||
5364 PPC::isVMRGHShuffleMask(SVOp, 1, true) ||
5365 PPC::isVMRGHShuffleMask(SVOp, 2, true) ||
5366 PPC::isVMRGHShuffleMask(SVOp, 4, true)) {
5371 // Altivec has a variety of "shuffle immediates" that take two vector inputs
5372 // and produce a fixed permutation. If any of these match, do not lower to
5374 if (PPC::isVPKUWUMShuffleMask(SVOp, false) ||
5375 PPC::isVPKUHUMShuffleMask(SVOp, false) ||
5376 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 ||
5377 PPC::isVMRGLShuffleMask(SVOp, 1, false) ||
5378 PPC::isVMRGLShuffleMask(SVOp, 2, false) ||
5379 PPC::isVMRGLShuffleMask(SVOp, 4, false) ||
5380 PPC::isVMRGHShuffleMask(SVOp, 1, false) ||
5381 PPC::isVMRGHShuffleMask(SVOp, 2, false) ||
5382 PPC::isVMRGHShuffleMask(SVOp, 4, false))
5385 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
5386 // perfect shuffle table to emit an optimal matching sequence.
5387 ArrayRef<int> PermMask = SVOp->getMask();
5389 unsigned PFIndexes[4];
5390 bool isFourElementShuffle = true;
5391 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
5392 unsigned EltNo = 8; // Start out undef.
5393 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
5394 if (PermMask[i*4+j] < 0)
5395 continue; // Undef, ignore it.
5397 unsigned ByteSource = PermMask[i*4+j];
5398 if ((ByteSource & 3) != j) {
5399 isFourElementShuffle = false;
5404 EltNo = ByteSource/4;
5405 } else if (EltNo != ByteSource/4) {
5406 isFourElementShuffle = false;
5410 PFIndexes[i] = EltNo;
5413 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
5414 // perfect shuffle vector to determine if it is cost effective to do this as
5415 // discrete instructions, or whether we should use a vperm.
5416 if (isFourElementShuffle) {
5417 // Compute the index in the perfect shuffle table.
5418 unsigned PFTableIndex =
5419 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5421 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5422 unsigned Cost = (PFEntry >> 30);
5424 // Determining when to avoid vperm is tricky. Many things affect the cost
5425 // of vperm, particularly how many times the perm mask needs to be computed.
5426 // For example, if the perm mask can be hoisted out of a loop or is already
5427 // used (perhaps because there are multiple permutes with the same shuffle
5428 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
5429 // the loop requires an extra register.
5431 // As a compromise, we only emit discrete instructions if the shuffle can be
5432 // generated in 3 or fewer operations. When we have loop information
5433 // available, if this block is within a loop, we should avoid using vperm
5434 // for 3-operation perms and use a constant pool load instead.
5436 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5439 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
5440 // vector that will get spilled to the constant pool.
5441 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
5443 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
5444 // that it is in input element units, not in bytes. Convert now.
5445 EVT EltVT = V1.getValueType().getVectorElementType();
5446 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
5448 SmallVector<SDValue, 16> ResultMask;
5449 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
5450 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
5452 for (unsigned j = 0; j != BytesPerElement; ++j)
5453 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
5457 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
5458 &ResultMask[0], ResultMask.size());
5459 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
5462 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
5463 /// altivec comparison. If it is, return true and fill in Opc/isDot with
5464 /// information about the intrinsic.
5465 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
5467 unsigned IntrinsicID =
5468 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
5471 switch (IntrinsicID) {
5472 default: return false;
5473 // Comparison predicates.
5474 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
5475 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
5476 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
5477 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
5478 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
5479 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
5480 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
5481 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
5482 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
5483 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
5484 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
5485 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
5486 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
5488 // Normal Comparisons.
5489 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
5490 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
5491 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
5492 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
5493 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
5494 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
5495 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
5496 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
5497 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
5498 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
5499 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
5500 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
5501 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
5506 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
5507 /// lower, do it, otherwise return null.
5508 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
5509 SelectionDAG &DAG) const {
5510 // If this is a lowered altivec predicate compare, CompareOpc is set to the
5511 // opcode number of the comparison.
5515 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
5516 return SDValue(); // Don't custom lower most intrinsics.
5518 // If this is a non-dot comparison, make the VCMP node and we are done.
5520 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
5521 Op.getOperand(1), Op.getOperand(2),
5522 DAG.getConstant(CompareOpc, MVT::i32));
5523 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
5526 // Create the PPCISD altivec 'dot' comparison node.
5528 Op.getOperand(2), // LHS
5529 Op.getOperand(3), // RHS
5530 DAG.getConstant(CompareOpc, MVT::i32)
5532 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
5533 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
5535 // Now that we have the comparison, emit a copy from the CR to a GPR.
5536 // This is flagged to the above dot comparison.
5537 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
5538 DAG.getRegister(PPC::CR6, MVT::i32),
5539 CompNode.getValue(1));
5541 // Unpack the result based on how the target uses it.
5542 unsigned BitNo; // Bit # of CR6.
5543 bool InvertBit; // Invert result?
5544 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
5545 default: // Can't happen, don't crash on invalid number though.
5546 case 0: // Return the value of the EQ bit of CR6.
5547 BitNo = 0; InvertBit = false;
5549 case 1: // Return the inverted value of the EQ bit of CR6.
5550 BitNo = 0; InvertBit = true;
5552 case 2: // Return the value of the LT bit of CR6.
5553 BitNo = 2; InvertBit = false;
5555 case 3: // Return the inverted value of the LT bit of CR6.
5556 BitNo = 2; InvertBit = true;
5560 // Shift the bit into the low position.
5561 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
5562 DAG.getConstant(8-(3-BitNo), MVT::i32));
5564 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
5565 DAG.getConstant(1, MVT::i32));
5567 // If we are supposed to, toggle the bit.
5569 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
5570 DAG.getConstant(1, MVT::i32));
5574 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
5575 SelectionDAG &DAG) const {
5577 // Create a stack slot that is 16-byte aligned.
5578 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
5579 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
5580 EVT PtrVT = getPointerTy();
5581 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5583 // Store the input value into Value#0 of the stack slot.
5584 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
5585 Op.getOperand(0), FIdx, MachinePointerInfo(),
5588 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
5589 false, false, false, 0);
5592 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
5594 if (Op.getValueType() == MVT::v4i32) {
5595 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5597 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
5598 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
5600 SDValue RHSSwap = // = vrlw RHS, 16
5601 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
5603 // Shrinkify inputs to v8i16.
5604 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
5605 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
5606 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
5608 // Low parts multiplied together, generating 32-bit results (we ignore the
5610 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
5611 LHS, RHS, DAG, dl, MVT::v4i32);
5613 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
5614 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
5615 // Shift the high parts up 16 bits.
5616 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
5618 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
5619 } else if (Op.getValueType() == MVT::v8i16) {
5620 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5622 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
5624 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
5625 LHS, RHS, Zero, DAG, dl);
5626 } else if (Op.getValueType() == MVT::v16i8) {
5627 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5629 // Multiply the even 8-bit parts, producing 16-bit sums.
5630 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
5631 LHS, RHS, DAG, dl, MVT::v8i16);
5632 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
5634 // Multiply the odd 8-bit parts, producing 16-bit sums.
5635 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
5636 LHS, RHS, DAG, dl, MVT::v8i16);
5637 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
5639 // Merge the results together.
5641 for (unsigned i = 0; i != 8; ++i) {
5643 Ops[i*2+1] = 2*i+1+16;
5645 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
5647 llvm_unreachable("Unknown mul to lower!");
5651 /// LowerOperation - Provide custom lowering hooks for some operations.
5653 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
5654 switch (Op.getOpcode()) {
5655 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
5656 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
5657 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
5658 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
5659 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
5660 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
5661 case ISD::SETCC: return LowerSETCC(Op, DAG);
5662 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
5663 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
5665 return LowerVASTART(Op, DAG, PPCSubTarget);
5668 return LowerVAARG(Op, DAG, PPCSubTarget);
5670 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
5671 case ISD::DYNAMIC_STACKALLOC:
5672 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
5674 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
5675 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
5677 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
5678 case ISD::FP_TO_UINT:
5679 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
5681 case ISD::UINT_TO_FP:
5682 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
5683 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
5685 // Lower 64-bit shifts.
5686 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
5687 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
5688 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
5690 // Vector-related lowering.
5691 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
5692 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
5693 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
5694 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
5695 case ISD::MUL: return LowerMUL(Op, DAG);
5697 // For counter-based loop handling.
5698 case ISD::INTRINSIC_W_CHAIN: return SDValue();
5700 // Frame & Return address.
5701 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
5702 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
5706 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
5707 SmallVectorImpl<SDValue>&Results,
5708 SelectionDAG &DAG) const {
5709 const TargetMachine &TM = getTargetMachine();
5711 switch (N->getOpcode()) {
5713 llvm_unreachable("Do not know how to custom type legalize this operation!");
5714 case ISD::INTRINSIC_W_CHAIN: {
5715 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
5716 Intrinsic::ppc_is_decremented_ctr_nonzero)
5719 assert(N->getValueType(0) == MVT::i1 &&
5720 "Unexpected result type for CTR decrement intrinsic");
5721 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
5722 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
5723 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
5726 Results.push_back(NewInt);
5727 Results.push_back(NewInt.getValue(1));
5731 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
5732 || TM.getSubtarget<PPCSubtarget>().isPPC64())
5735 EVT VT = N->getValueType(0);
5737 if (VT == MVT::i64) {
5738 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, PPCSubTarget);
5740 Results.push_back(NewNode);
5741 Results.push_back(NewNode.getValue(1));
5745 case ISD::FP_ROUND_INREG: {
5746 assert(N->getValueType(0) == MVT::ppcf128);
5747 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
5748 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
5749 MVT::f64, N->getOperand(0),
5750 DAG.getIntPtrConstant(0));
5751 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
5752 MVT::f64, N->getOperand(0),
5753 DAG.getIntPtrConstant(1));
5755 // Add the two halves of the long double in round-to-zero mode.
5756 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
5758 // We know the low half is about to be thrown away, so just use something
5760 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
5764 case ISD::FP_TO_SINT:
5765 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
5771 //===----------------------------------------------------------------------===//
5772 // Other Lowering Code
5773 //===----------------------------------------------------------------------===//
5776 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
5777 bool is64bit, unsigned BinOpcode) const {
5778 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
5779 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5781 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5782 MachineFunction *F = BB->getParent();
5783 MachineFunction::iterator It = BB;
5786 unsigned dest = MI->getOperand(0).getReg();
5787 unsigned ptrA = MI->getOperand(1).getReg();
5788 unsigned ptrB = MI->getOperand(2).getReg();
5789 unsigned incr = MI->getOperand(3).getReg();
5790 DebugLoc dl = MI->getDebugLoc();
5792 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
5793 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
5794 F->insert(It, loopMBB);
5795 F->insert(It, exitMBB);
5796 exitMBB->splice(exitMBB->begin(), BB,
5797 llvm::next(MachineBasicBlock::iterator(MI)),
5799 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5801 MachineRegisterInfo &RegInfo = F->getRegInfo();
5802 unsigned TmpReg = (!BinOpcode) ? incr :
5803 RegInfo.createVirtualRegister(
5804 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
5805 (const TargetRegisterClass *) &PPC::GPRCRegClass);
5809 // fallthrough --> loopMBB
5810 BB->addSuccessor(loopMBB);
5813 // l[wd]arx dest, ptr
5814 // add r0, dest, incr
5815 // st[wd]cx. r0, ptr
5817 // fallthrough --> exitMBB
5819 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
5820 .addReg(ptrA).addReg(ptrB);
5822 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
5823 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
5824 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
5825 BuildMI(BB, dl, TII->get(PPC::BCC))
5826 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
5827 BB->addSuccessor(loopMBB);
5828 BB->addSuccessor(exitMBB);
5837 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
5838 MachineBasicBlock *BB,
5839 bool is8bit, // operation
5840 unsigned BinOpcode) const {
5841 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
5842 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5843 // In 64 bit mode we have to use 64 bits for addresses, even though the
5844 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
5845 // registers without caring whether they're 32 or 64, but here we're
5846 // doing actual arithmetic on the addresses.
5847 bool is64bit = PPCSubTarget.isPPC64();
5848 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
5850 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5851 MachineFunction *F = BB->getParent();
5852 MachineFunction::iterator It = BB;
5855 unsigned dest = MI->getOperand(0).getReg();
5856 unsigned ptrA = MI->getOperand(1).getReg();
5857 unsigned ptrB = MI->getOperand(2).getReg();
5858 unsigned incr = MI->getOperand(3).getReg();
5859 DebugLoc dl = MI->getDebugLoc();
5861 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
5862 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
5863 F->insert(It, loopMBB);
5864 F->insert(It, exitMBB);
5865 exitMBB->splice(exitMBB->begin(), BB,
5866 llvm::next(MachineBasicBlock::iterator(MI)),
5868 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5870 MachineRegisterInfo &RegInfo = F->getRegInfo();
5871 const TargetRegisterClass *RC =
5872 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
5873 (const TargetRegisterClass *) &PPC::GPRCRegClass;
5874 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
5875 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
5876 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
5877 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
5878 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
5879 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
5880 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
5881 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
5882 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
5883 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
5884 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
5886 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
5890 // fallthrough --> loopMBB
5891 BB->addSuccessor(loopMBB);
5893 // The 4-byte load must be aligned, while a char or short may be
5894 // anywhere in the word. Hence all this nasty bookkeeping code.
5895 // add ptr1, ptrA, ptrB [copy if ptrA==0]
5896 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
5897 // xori shift, shift1, 24 [16]
5898 // rlwinm ptr, ptr1, 0, 0, 29
5899 // slw incr2, incr, shift
5900 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
5901 // slw mask, mask2, shift
5903 // lwarx tmpDest, ptr
5904 // add tmp, tmpDest, incr2
5905 // andc tmp2, tmpDest, mask
5906 // and tmp3, tmp, mask
5907 // or tmp4, tmp3, tmp2
5910 // fallthrough --> exitMBB
5911 // srw dest, tmpDest, shift
5912 if (ptrA != ZeroReg) {
5913 Ptr1Reg = RegInfo.createVirtualRegister(RC);
5914 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
5915 .addReg(ptrA).addReg(ptrB);
5919 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
5920 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
5921 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
5922 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
5924 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
5925 .addReg(Ptr1Reg).addImm(0).addImm(61);
5927 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
5928 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
5929 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
5930 .addReg(incr).addReg(ShiftReg);
5932 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
5934 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
5935 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
5937 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
5938 .addReg(Mask2Reg).addReg(ShiftReg);
5941 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
5942 .addReg(ZeroReg).addReg(PtrReg);
5944 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
5945 .addReg(Incr2Reg).addReg(TmpDestReg);
5946 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
5947 .addReg(TmpDestReg).addReg(MaskReg);
5948 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
5949 .addReg(TmpReg).addReg(MaskReg);
5950 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
5951 .addReg(Tmp3Reg).addReg(Tmp2Reg);
5952 BuildMI(BB, dl, TII->get(PPC::STWCX))
5953 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
5954 BuildMI(BB, dl, TII->get(PPC::BCC))
5955 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
5956 BB->addSuccessor(loopMBB);
5957 BB->addSuccessor(exitMBB);
5962 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
5967 llvm::MachineBasicBlock*
5968 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
5969 MachineBasicBlock *MBB) const {
5970 DebugLoc DL = MI->getDebugLoc();
5971 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5973 MachineFunction *MF = MBB->getParent();
5974 MachineRegisterInfo &MRI = MF->getRegInfo();
5976 const BasicBlock *BB = MBB->getBasicBlock();
5977 MachineFunction::iterator I = MBB;
5981 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
5982 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
5984 unsigned DstReg = MI->getOperand(0).getReg();
5985 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
5986 assert(RC->hasType(MVT::i32) && "Invalid destination!");
5987 unsigned mainDstReg = MRI.createVirtualRegister(RC);
5988 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
5990 MVT PVT = getPointerTy();
5991 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
5992 "Invalid Pointer Size!");
5993 // For v = setjmp(buf), we generate
5996 // SjLjSetup mainMBB
6002 // buf[LabelOffset] = LR
6006 // v = phi(main, restore)
6009 MachineBasicBlock *thisMBB = MBB;
6010 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
6011 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
6012 MF->insert(I, mainMBB);
6013 MF->insert(I, sinkMBB);
6015 MachineInstrBuilder MIB;
6017 // Transfer the remainder of BB and its successor edges to sinkMBB.
6018 sinkMBB->splice(sinkMBB->begin(), MBB,
6019 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
6020 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
6022 // Note that the structure of the jmp_buf used here is not compatible
6023 // with that used by libc, and is not designed to be. Specifically, it
6024 // stores only those 'reserved' registers that LLVM does not otherwise
6025 // understand how to spill. Also, by convention, by the time this
6026 // intrinsic is called, Clang has already stored the frame address in the
6027 // first slot of the buffer and stack address in the third. Following the
6028 // X86 target code, we'll store the jump address in the second slot. We also
6029 // need to save the TOC pointer (R2) to handle jumps between shared
6030 // libraries, and that will be stored in the fourth slot. The thread
6031 // identifier (R13) is not affected.
6034 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6035 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6037 // Prepare IP either in reg.
6038 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
6039 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
6040 unsigned BufReg = MI->getOperand(1).getReg();
6042 if (PPCSubTarget.isPPC64() && PPCSubTarget.isSVR4ABI()) {
6043 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
6048 MIB.setMemRefs(MMOBegin, MMOEnd);
6052 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
6053 const PPCRegisterInfo *TRI =
6054 static_cast<const PPCRegisterInfo*>(getTargetMachine().getRegisterInfo());
6055 MIB.addRegMask(TRI->getNoPreservedMask());
6057 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
6059 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
6061 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
6063 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
6064 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
6068 MIB = BuildMI(mainMBB, DL,
6069 TII->get(PPCSubTarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
6072 if (PPCSubTarget.isPPC64()) {
6073 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
6075 .addImm(LabelOffset)
6078 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
6080 .addImm(LabelOffset)
6084 MIB.setMemRefs(MMOBegin, MMOEnd);
6086 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
6087 mainMBB->addSuccessor(sinkMBB);
6090 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
6091 TII->get(PPC::PHI), DstReg)
6092 .addReg(mainDstReg).addMBB(mainMBB)
6093 .addReg(restoreDstReg).addMBB(thisMBB);
6095 MI->eraseFromParent();
6100 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
6101 MachineBasicBlock *MBB) const {
6102 DebugLoc DL = MI->getDebugLoc();
6103 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6105 MachineFunction *MF = MBB->getParent();
6106 MachineRegisterInfo &MRI = MF->getRegInfo();
6109 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6110 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6112 MVT PVT = getPointerTy();
6113 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6114 "Invalid Pointer Size!");
6116 const TargetRegisterClass *RC =
6117 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6118 unsigned Tmp = MRI.createVirtualRegister(RC);
6119 // Since FP is only updated here but NOT referenced, it's treated as GPR.
6120 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6121 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6123 MachineInstrBuilder MIB;
6125 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6126 const int64_t SPOffset = 2 * PVT.getStoreSize();
6127 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6129 unsigned BufReg = MI->getOperand(0).getReg();
6131 // Reload FP (the jumped-to function may not have had a
6132 // frame pointer, and if so, then its r31 will be restored
6134 if (PVT == MVT::i64) {
6135 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
6139 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
6143 MIB.setMemRefs(MMOBegin, MMOEnd);
6146 if (PVT == MVT::i64) {
6147 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
6148 .addImm(LabelOffset)
6151 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
6152 .addImm(LabelOffset)
6155 MIB.setMemRefs(MMOBegin, MMOEnd);
6158 if (PVT == MVT::i64) {
6159 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
6163 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
6167 MIB.setMemRefs(MMOBegin, MMOEnd);
6169 // FIXME: When we also support base pointers, that register must also be
6173 if (PVT == MVT::i64 && PPCSubTarget.isSVR4ABI()) {
6174 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
6178 MIB.setMemRefs(MMOBegin, MMOEnd);
6182 BuildMI(*MBB, MI, DL,
6183 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
6184 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
6186 MI->eraseFromParent();
6191 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6192 MachineBasicBlock *BB) const {
6193 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
6194 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
6195 return emitEHSjLjSetJmp(MI, BB);
6196 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
6197 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
6198 return emitEHSjLjLongJmp(MI, BB);
6201 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6203 // To "insert" these instructions we actually have to insert their
6204 // control-flow patterns.
6205 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6206 MachineFunction::iterator It = BB;
6209 MachineFunction *F = BB->getParent();
6211 if (PPCSubTarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6212 MI->getOpcode() == PPC::SELECT_CC_I8)) {
6213 SmallVector<MachineOperand, 2> Cond;
6214 Cond.push_back(MI->getOperand(4));
6215 Cond.push_back(MI->getOperand(1));
6217 DebugLoc dl = MI->getDebugLoc();
6218 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6219 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
6220 Cond, MI->getOperand(2).getReg(),
6221 MI->getOperand(3).getReg());
6222 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6223 MI->getOpcode() == PPC::SELECT_CC_I8 ||
6224 MI->getOpcode() == PPC::SELECT_CC_F4 ||
6225 MI->getOpcode() == PPC::SELECT_CC_F8 ||
6226 MI->getOpcode() == PPC::SELECT_CC_VRRC) {
6229 // The incoming instruction knows the destination vreg to set, the
6230 // condition code register to branch on, the true/false values to
6231 // select between, and a branch opcode to use.
6236 // cmpTY ccX, r1, r2
6238 // fallthrough --> copy0MBB
6239 MachineBasicBlock *thisMBB = BB;
6240 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
6241 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
6242 unsigned SelectPred = MI->getOperand(4).getImm();
6243 DebugLoc dl = MI->getDebugLoc();
6244 F->insert(It, copy0MBB);
6245 F->insert(It, sinkMBB);
6247 // Transfer the remainder of BB and its successor edges to sinkMBB.
6248 sinkMBB->splice(sinkMBB->begin(), BB,
6249 llvm::next(MachineBasicBlock::iterator(MI)),
6251 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
6253 // Next, add the true and fallthrough blocks as its successors.
6254 BB->addSuccessor(copy0MBB);
6255 BB->addSuccessor(sinkMBB);
6257 BuildMI(BB, dl, TII->get(PPC::BCC))
6258 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
6261 // %FalseValue = ...
6262 // # fallthrough to sinkMBB
6265 // Update machine-CFG edges
6266 BB->addSuccessor(sinkMBB);
6269 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
6272 BuildMI(*BB, BB->begin(), dl,
6273 TII->get(PPC::PHI), MI->getOperand(0).getReg())
6274 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
6275 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
6277 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
6278 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
6279 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
6280 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
6281 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
6282 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
6283 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
6284 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
6286 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
6287 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
6288 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
6289 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
6290 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
6291 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
6292 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
6293 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
6295 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
6296 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
6297 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
6298 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
6299 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
6300 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
6301 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
6302 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
6304 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
6305 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
6306 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
6307 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
6308 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
6309 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
6310 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
6311 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
6313 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
6314 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
6315 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
6316 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
6317 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
6318 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
6319 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
6320 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
6322 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
6323 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
6324 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
6325 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
6326 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
6327 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
6328 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
6329 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
6331 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
6332 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
6333 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
6334 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
6335 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
6336 BB = EmitAtomicBinary(MI, BB, false, 0);
6337 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
6338 BB = EmitAtomicBinary(MI, BB, true, 0);
6340 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
6341 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
6342 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
6344 unsigned dest = MI->getOperand(0).getReg();
6345 unsigned ptrA = MI->getOperand(1).getReg();
6346 unsigned ptrB = MI->getOperand(2).getReg();
6347 unsigned oldval = MI->getOperand(3).getReg();
6348 unsigned newval = MI->getOperand(4).getReg();
6349 DebugLoc dl = MI->getDebugLoc();
6351 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6352 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6353 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6354 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6355 F->insert(It, loop1MBB);
6356 F->insert(It, loop2MBB);
6357 F->insert(It, midMBB);
6358 F->insert(It, exitMBB);
6359 exitMBB->splice(exitMBB->begin(), BB,
6360 llvm::next(MachineBasicBlock::iterator(MI)),
6362 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6366 // fallthrough --> loopMBB
6367 BB->addSuccessor(loop1MBB);
6370 // l[wd]arx dest, ptr
6371 // cmp[wd] dest, oldval
6374 // st[wd]cx. newval, ptr
6378 // st[wd]cx. dest, ptr
6381 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6382 .addReg(ptrA).addReg(ptrB);
6383 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
6384 .addReg(oldval).addReg(dest);
6385 BuildMI(BB, dl, TII->get(PPC::BCC))
6386 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6387 BB->addSuccessor(loop2MBB);
6388 BB->addSuccessor(midMBB);
6391 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6392 .addReg(newval).addReg(ptrA).addReg(ptrB);
6393 BuildMI(BB, dl, TII->get(PPC::BCC))
6394 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6395 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6396 BB->addSuccessor(loop1MBB);
6397 BB->addSuccessor(exitMBB);
6400 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6401 .addReg(dest).addReg(ptrA).addReg(ptrB);
6402 BB->addSuccessor(exitMBB);
6407 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
6408 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
6409 // We must use 64-bit registers for addresses when targeting 64-bit,
6410 // since we're actually doing arithmetic on them. Other registers
6412 bool is64bit = PPCSubTarget.isPPC64();
6413 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
6415 unsigned dest = MI->getOperand(0).getReg();
6416 unsigned ptrA = MI->getOperand(1).getReg();
6417 unsigned ptrB = MI->getOperand(2).getReg();
6418 unsigned oldval = MI->getOperand(3).getReg();
6419 unsigned newval = MI->getOperand(4).getReg();
6420 DebugLoc dl = MI->getDebugLoc();
6422 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6423 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6424 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6425 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6426 F->insert(It, loop1MBB);
6427 F->insert(It, loop2MBB);
6428 F->insert(It, midMBB);
6429 F->insert(It, exitMBB);
6430 exitMBB->splice(exitMBB->begin(), BB,
6431 llvm::next(MachineBasicBlock::iterator(MI)),
6433 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6435 MachineRegisterInfo &RegInfo = F->getRegInfo();
6436 const TargetRegisterClass *RC =
6437 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6438 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6439 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6440 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6441 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6442 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
6443 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
6444 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
6445 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
6446 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6447 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6448 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6449 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6450 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6451 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6453 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
6454 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6457 // fallthrough --> loopMBB
6458 BB->addSuccessor(loop1MBB);
6460 // The 4-byte load must be aligned, while a char or short may be
6461 // anywhere in the word. Hence all this nasty bookkeeping code.
6462 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6463 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6464 // xori shift, shift1, 24 [16]
6465 // rlwinm ptr, ptr1, 0, 0, 29
6466 // slw newval2, newval, shift
6467 // slw oldval2, oldval,shift
6468 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6469 // slw mask, mask2, shift
6470 // and newval3, newval2, mask
6471 // and oldval3, oldval2, mask
6473 // lwarx tmpDest, ptr
6474 // and tmp, tmpDest, mask
6475 // cmpw tmp, oldval3
6478 // andc tmp2, tmpDest, mask
6479 // or tmp4, tmp2, newval3
6484 // stwcx. tmpDest, ptr
6486 // srw dest, tmpDest, shift
6487 if (ptrA != ZeroReg) {
6488 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6489 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6490 .addReg(ptrA).addReg(ptrB);
6494 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6495 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6496 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6497 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6499 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6500 .addReg(Ptr1Reg).addImm(0).addImm(61);
6502 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6503 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6504 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
6505 .addReg(newval).addReg(ShiftReg);
6506 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
6507 .addReg(oldval).addReg(ShiftReg);
6509 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6511 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6512 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
6513 .addReg(Mask3Reg).addImm(65535);
6515 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6516 .addReg(Mask2Reg).addReg(ShiftReg);
6517 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
6518 .addReg(NewVal2Reg).addReg(MaskReg);
6519 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
6520 .addReg(OldVal2Reg).addReg(MaskReg);
6523 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6524 .addReg(ZeroReg).addReg(PtrReg);
6525 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
6526 .addReg(TmpDestReg).addReg(MaskReg);
6527 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
6528 .addReg(TmpReg).addReg(OldVal3Reg);
6529 BuildMI(BB, dl, TII->get(PPC::BCC))
6530 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6531 BB->addSuccessor(loop2MBB);
6532 BB->addSuccessor(midMBB);
6535 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
6536 .addReg(TmpDestReg).addReg(MaskReg);
6537 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
6538 .addReg(Tmp2Reg).addReg(NewVal3Reg);
6539 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
6540 .addReg(ZeroReg).addReg(PtrReg);
6541 BuildMI(BB, dl, TII->get(PPC::BCC))
6542 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6543 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6544 BB->addSuccessor(loop1MBB);
6545 BB->addSuccessor(exitMBB);
6548 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
6549 .addReg(ZeroReg).addReg(PtrReg);
6550 BB->addSuccessor(exitMBB);
6555 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
6557 } else if (MI->getOpcode() == PPC::FADDrtz) {
6558 // This pseudo performs an FADD with rounding mode temporarily forced
6559 // to round-to-zero. We emit this via custom inserter since the FPSCR
6560 // is not modeled at the SelectionDAG level.
6561 unsigned Dest = MI->getOperand(0).getReg();
6562 unsigned Src1 = MI->getOperand(1).getReg();
6563 unsigned Src2 = MI->getOperand(2).getReg();
6564 DebugLoc dl = MI->getDebugLoc();
6566 MachineRegisterInfo &RegInfo = F->getRegInfo();
6567 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
6569 // Save FPSCR value.
6570 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
6572 // Set rounding mode to round-to-zero.
6573 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
6574 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
6576 // Perform addition.
6577 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
6579 // Restore FPSCR value.
6580 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg);
6581 } else if (MI->getOpcode() == PPC::FRINDrint ||
6582 MI->getOpcode() == PPC::FRINSrint) {
6583 bool isf32 = MI->getOpcode() == PPC::FRINSrint;
6584 unsigned Dest = MI->getOperand(0).getReg();
6585 unsigned Src = MI->getOperand(1).getReg();
6586 DebugLoc dl = MI->getDebugLoc();
6588 MachineRegisterInfo &RegInfo = F->getRegInfo();
6589 unsigned CRReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
6591 // Perform the rounding.
6592 BuildMI(*BB, MI, dl, TII->get(isf32 ? PPC::FRINS : PPC::FRIND), Dest)
6595 // Compare the results.
6596 BuildMI(*BB, MI, dl, TII->get(isf32 ? PPC::FCMPUS : PPC::FCMPUD), CRReg)
6597 .addReg(Dest).addReg(Src);
6599 // If the results were not equal, then set the FPSCR XX bit.
6600 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6601 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6602 F->insert(It, midMBB);
6603 F->insert(It, exitMBB);
6604 exitMBB->splice(exitMBB->begin(), BB,
6605 llvm::next(MachineBasicBlock::iterator(MI)),
6607 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6609 BuildMI(*BB, MI, dl, TII->get(PPC::BCC))
6610 .addImm(PPC::PRED_EQ).addReg(CRReg).addMBB(exitMBB);
6612 BB->addSuccessor(midMBB);
6613 BB->addSuccessor(exitMBB);
6617 // Set the FPSCR XX bit (FE_INEXACT). Note that we cannot just set
6618 // the FI bit here because that will not automatically set XX also,
6619 // and XX is what libm interprets as the FE_INEXACT flag.
6620 BuildMI(BB, dl, TII->get(PPC::MTFSB1)).addImm(/* 38 - 32 = */ 6);
6621 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6623 BB->addSuccessor(exitMBB);
6627 llvm_unreachable("Unexpected instr type to insert");
6630 MI->eraseFromParent(); // The pseudo instruction is gone now.
6634 //===----------------------------------------------------------------------===//
6635 // Target Optimization Hooks
6636 //===----------------------------------------------------------------------===//
6638 SDValue PPCTargetLowering::DAGCombineFastRecip(SDValue Op,
6639 DAGCombinerInfo &DCI) const {
6640 if (DCI.isAfterLegalizeVectorOps())
6643 EVT VT = Op.getValueType();
6645 if ((VT == MVT::f32 && PPCSubTarget.hasFRES()) ||
6646 (VT == MVT::f64 && PPCSubTarget.hasFRE()) ||
6647 (VT == MVT::v4f32 && PPCSubTarget.hasAltivec())) {
6649 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
6650 // For the reciprocal, we need to find the zero of the function:
6651 // F(X) = A X - 1 [which has a zero at X = 1/A]
6653 // X_{i+1} = X_i (2 - A X_i) = X_i + X_i (1 - A X_i) [this second form
6654 // does not require additional intermediate precision]
6656 // Convergence is quadratic, so we essentially double the number of digits
6657 // correct after every iteration. The minimum architected relative
6658 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
6659 // 23 digits and double has 52 digits.
6660 int Iterations = PPCSubTarget.hasRecipPrec() ? 1 : 3;
6661 if (VT.getScalarType() == MVT::f64)
6664 SelectionDAG &DAG = DCI.DAG;
6668 DAG.getConstantFP(1.0, VT.getScalarType());
6669 if (VT.isVector()) {
6670 assert(VT.getVectorNumElements() == 4 &&
6671 "Unknown vector type");
6672 FPOne = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
6673 FPOne, FPOne, FPOne, FPOne);
6676 SDValue Est = DAG.getNode(PPCISD::FRE, dl, VT, Op);
6677 DCI.AddToWorklist(Est.getNode());
6679 // Newton iterations: Est = Est + Est (1 - Arg * Est)
6680 for (int i = 0; i < Iterations; ++i) {
6681 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Op, Est);
6682 DCI.AddToWorklist(NewEst.getNode());
6684 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPOne, NewEst);
6685 DCI.AddToWorklist(NewEst.getNode());
6687 NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
6688 DCI.AddToWorklist(NewEst.getNode());
6690 Est = DAG.getNode(ISD::FADD, dl, VT, Est, NewEst);
6691 DCI.AddToWorklist(Est.getNode());
6700 SDValue PPCTargetLowering::DAGCombineFastRecipFSQRT(SDValue Op,
6701 DAGCombinerInfo &DCI) const {
6702 if (DCI.isAfterLegalizeVectorOps())
6705 EVT VT = Op.getValueType();
6707 if ((VT == MVT::f32 && PPCSubTarget.hasFRSQRTES()) ||
6708 (VT == MVT::f64 && PPCSubTarget.hasFRSQRTE()) ||
6709 (VT == MVT::v4f32 && PPCSubTarget.hasAltivec())) {
6711 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
6712 // For the reciprocal sqrt, we need to find the zero of the function:
6713 // F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
6715 // X_{i+1} = X_i (1.5 - A X_i^2 / 2)
6716 // As a result, we precompute A/2 prior to the iteration loop.
6718 // Convergence is quadratic, so we essentially double the number of digits
6719 // correct after every iteration. The minimum architected relative
6720 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
6721 // 23 digits and double has 52 digits.
6722 int Iterations = PPCSubTarget.hasRecipPrec() ? 1 : 3;
6723 if (VT.getScalarType() == MVT::f64)
6726 SelectionDAG &DAG = DCI.DAG;
6729 SDValue FPThreeHalves =
6730 DAG.getConstantFP(1.5, VT.getScalarType());
6731 if (VT.isVector()) {
6732 assert(VT.getVectorNumElements() == 4 &&
6733 "Unknown vector type");
6734 FPThreeHalves = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
6735 FPThreeHalves, FPThreeHalves,
6736 FPThreeHalves, FPThreeHalves);
6739 SDValue Est = DAG.getNode(PPCISD::FRSQRTE, dl, VT, Op);
6740 DCI.AddToWorklist(Est.getNode());
6742 // We now need 0.5*Arg which we can write as (1.5*Arg - Arg) so that
6743 // this entire sequence requires only one FP constant.
6744 SDValue HalfArg = DAG.getNode(ISD::FMUL, dl, VT, FPThreeHalves, Op);
6745 DCI.AddToWorklist(HalfArg.getNode());
6747 HalfArg = DAG.getNode(ISD::FSUB, dl, VT, HalfArg, Op);
6748 DCI.AddToWorklist(HalfArg.getNode());
6750 // Newton iterations: Est = Est * (1.5 - HalfArg * Est * Est)
6751 for (int i = 0; i < Iterations; ++i) {
6752 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, Est);
6753 DCI.AddToWorklist(NewEst.getNode());
6755 NewEst = DAG.getNode(ISD::FMUL, dl, VT, HalfArg, NewEst);
6756 DCI.AddToWorklist(NewEst.getNode());
6758 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPThreeHalves, NewEst);
6759 DCI.AddToWorklist(NewEst.getNode());
6761 Est = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
6762 DCI.AddToWorklist(Est.getNode());
6771 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
6772 // not enforce equality of the chain operands.
6773 static bool isConsecutiveLS(LSBaseSDNode *LS, LSBaseSDNode *Base,
6774 unsigned Bytes, int Dist,
6775 SelectionDAG &DAG) {
6776 EVT VT = LS->getMemoryVT();
6777 if (VT.getSizeInBits() / 8 != Bytes)
6780 SDValue Loc = LS->getBasePtr();
6781 SDValue BaseLoc = Base->getBasePtr();
6782 if (Loc.getOpcode() == ISD::FrameIndex) {
6783 if (BaseLoc.getOpcode() != ISD::FrameIndex)
6785 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6786 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
6787 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
6788 int FS = MFI->getObjectSize(FI);
6789 int BFS = MFI->getObjectSize(BFI);
6790 if (FS != BFS || FS != (int)Bytes) return false;
6791 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
6795 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
6796 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
6799 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6800 const GlobalValue *GV1 = NULL;
6801 const GlobalValue *GV2 = NULL;
6802 int64_t Offset1 = 0;
6803 int64_t Offset2 = 0;
6804 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
6805 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
6806 if (isGA1 && isGA2 && GV1 == GV2)
6807 return Offset1 == (Offset2 + Dist*Bytes);
6811 // Return true is there is a nearyby consecutive load to the one provided
6812 // (regardless of alignment). We search up and down the chain, looking though
6813 // token factors and other loads (but nothing else). As a result, a true
6814 // results indicates that it is safe to create a new consecutive load adjacent
6815 // to the load provided.
6816 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
6817 SDValue Chain = LD->getChain();
6818 EVT VT = LD->getMemoryVT();
6820 SmallSet<SDNode *, 16> LoadRoots;
6821 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
6822 SmallSet<SDNode *, 16> Visited;
6824 // First, search up the chain, branching to follow all token-factor operands.
6825 // If we find a consecutive load, then we're done, otherwise, record all
6826 // nodes just above the top-level loads and token factors.
6827 while (!Queue.empty()) {
6828 SDNode *ChainNext = Queue.pop_back_val();
6829 if (!Visited.insert(ChainNext))
6832 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(ChainNext)) {
6833 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
6836 if (!Visited.count(ChainLD->getChain().getNode()))
6837 Queue.push_back(ChainLD->getChain().getNode());
6838 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
6839 for (SDNode::op_iterator O = ChainNext->op_begin(),
6840 OE = ChainNext->op_end(); O != OE; ++O)
6841 if (!Visited.count(O->getNode()))
6842 Queue.push_back(O->getNode());
6844 LoadRoots.insert(ChainNext);
6847 // Second, search down the chain, starting from the top-level nodes recorded
6848 // in the first phase. These top-level nodes are the nodes just above all
6849 // loads and token factors. Starting with their uses, recursively look though
6850 // all loads (just the chain uses) and token factors to find a consecutive
6855 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
6856 IE = LoadRoots.end(); I != IE; ++I) {
6857 Queue.push_back(*I);
6859 while (!Queue.empty()) {
6860 SDNode *LoadRoot = Queue.pop_back_val();
6861 if (!Visited.insert(LoadRoot))
6864 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(LoadRoot))
6865 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
6868 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
6869 UE = LoadRoot->use_end(); UI != UE; ++UI)
6870 if (((isa<LoadSDNode>(*UI) &&
6871 cast<LoadSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
6872 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
6873 Queue.push_back(*UI);
6880 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
6881 DAGCombinerInfo &DCI) const {
6882 const TargetMachine &TM = getTargetMachine();
6883 SelectionDAG &DAG = DCI.DAG;
6885 switch (N->getOpcode()) {
6888 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6889 if (C->isNullValue()) // 0 << V -> 0.
6890 return N->getOperand(0);
6894 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6895 if (C->isNullValue()) // 0 >>u V -> 0.
6896 return N->getOperand(0);
6900 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6901 if (C->isNullValue() || // 0 >>s V -> 0.
6902 C->isAllOnesValue()) // -1 >>s V -> -1.
6903 return N->getOperand(0);
6907 assert(TM.Options.UnsafeFPMath &&
6908 "Reciprocal estimates require UnsafeFPMath");
6910 if (N->getOperand(1).getOpcode() == ISD::FSQRT) {
6912 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0), DCI);
6913 if (RV.getNode() != 0) {
6914 DCI.AddToWorklist(RV.getNode());
6915 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
6916 N->getOperand(0), RV);
6918 } else if (N->getOperand(1).getOpcode() == ISD::FP_EXTEND &&
6919 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
6921 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
6923 if (RV.getNode() != 0) {
6924 DCI.AddToWorklist(RV.getNode());
6925 RV = DAG.getNode(ISD::FP_EXTEND, SDLoc(N->getOperand(1)),
6926 N->getValueType(0), RV);
6927 DCI.AddToWorklist(RV.getNode());
6928 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
6929 N->getOperand(0), RV);
6931 } else if (N->getOperand(1).getOpcode() == ISD::FP_ROUND &&
6932 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
6934 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
6936 if (RV.getNode() != 0) {
6937 DCI.AddToWorklist(RV.getNode());
6938 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N->getOperand(1)),
6939 N->getValueType(0), RV,
6940 N->getOperand(1).getOperand(1));
6941 DCI.AddToWorklist(RV.getNode());
6942 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
6943 N->getOperand(0), RV);
6947 SDValue RV = DAGCombineFastRecip(N->getOperand(1), DCI);
6948 if (RV.getNode() != 0) {
6949 DCI.AddToWorklist(RV.getNode());
6950 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
6951 N->getOperand(0), RV);
6957 assert(TM.Options.UnsafeFPMath &&
6958 "Reciprocal estimates require UnsafeFPMath");
6960 // Compute this as 1/(1/sqrt(X)), which is the reciprocal of the
6962 SDValue RV = DAGCombineFastRecipFSQRT(N->getOperand(0), DCI);
6963 if (RV.getNode() != 0) {
6964 DCI.AddToWorklist(RV.getNode());
6965 RV = DAGCombineFastRecip(RV, DCI);
6966 if (RV.getNode() != 0)
6972 case ISD::SINT_TO_FP:
6973 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
6974 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
6975 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
6976 // We allow the src/dst to be either f32/f64, but the intermediate
6977 // type must be i64.
6978 if (N->getOperand(0).getValueType() == MVT::i64 &&
6979 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
6980 SDValue Val = N->getOperand(0).getOperand(0);
6981 if (Val.getValueType() == MVT::f32) {
6982 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
6983 DCI.AddToWorklist(Val.getNode());
6986 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
6987 DCI.AddToWorklist(Val.getNode());
6988 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
6989 DCI.AddToWorklist(Val.getNode());
6990 if (N->getValueType(0) == MVT::f32) {
6991 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
6992 DAG.getIntPtrConstant(0));
6993 DCI.AddToWorklist(Val.getNode());
6996 } else if (N->getOperand(0).getValueType() == MVT::i32) {
6997 // If the intermediate type is i32, we can avoid the load/store here
7004 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
7005 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
7006 !cast<StoreSDNode>(N)->isTruncatingStore() &&
7007 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
7008 N->getOperand(1).getValueType() == MVT::i32 &&
7009 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
7010 SDValue Val = N->getOperand(1).getOperand(0);
7011 if (Val.getValueType() == MVT::f32) {
7012 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
7013 DCI.AddToWorklist(Val.getNode());
7015 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
7016 DCI.AddToWorklist(Val.getNode());
7019 N->getOperand(0), Val, N->getOperand(2),
7020 DAG.getValueType(N->getOperand(1).getValueType())
7023 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
7024 DAG.getVTList(MVT::Other), Ops, array_lengthof(Ops),
7025 cast<StoreSDNode>(N)->getMemoryVT(),
7026 cast<StoreSDNode>(N)->getMemOperand());
7027 DCI.AddToWorklist(Val.getNode());
7031 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
7032 if (cast<StoreSDNode>(N)->isUnindexed() &&
7033 N->getOperand(1).getOpcode() == ISD::BSWAP &&
7034 N->getOperand(1).getNode()->hasOneUse() &&
7035 (N->getOperand(1).getValueType() == MVT::i32 ||
7036 N->getOperand(1).getValueType() == MVT::i16 ||
7037 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
7038 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
7039 N->getOperand(1).getValueType() == MVT::i64))) {
7040 SDValue BSwapOp = N->getOperand(1).getOperand(0);
7041 // Do an any-extend to 32-bits if this is a half-word input.
7042 if (BSwapOp.getValueType() == MVT::i16)
7043 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
7046 N->getOperand(0), BSwapOp, N->getOperand(2),
7047 DAG.getValueType(N->getOperand(1).getValueType())
7050 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
7051 Ops, array_lengthof(Ops),
7052 cast<StoreSDNode>(N)->getMemoryVT(),
7053 cast<StoreSDNode>(N)->getMemOperand());
7057 LoadSDNode *LD = cast<LoadSDNode>(N);
7058 EVT VT = LD->getValueType(0);
7059 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
7060 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
7061 if (ISD::isNON_EXTLoad(N) && VT.isVector() &&
7062 TM.getSubtarget<PPCSubtarget>().hasAltivec() &&
7063 DCI.getDAGCombineLevel() == AfterLegalizeTypes &&
7064 LD->getAlignment() < ABIAlignment) {
7065 // This is a type-legal unaligned Altivec load.
7066 SDValue Chain = LD->getChain();
7067 SDValue Ptr = LD->getBasePtr();
7069 // This implements the loading of unaligned vectors as described in
7070 // the venerable Apple Velocity Engine overview. Specifically:
7071 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
7072 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
7074 // The general idea is to expand a sequence of one or more unaligned
7075 // loads into a alignment-based permutation-control instruction (lvsl),
7076 // a series of regular vector loads (which always truncate their
7077 // input address to an aligned address), and a series of permutations.
7078 // The results of these permutations are the requested loaded values.
7079 // The trick is that the last "extra" load is not taken from the address
7080 // you might suspect (sizeof(vector) bytes after the last requested
7081 // load), but rather sizeof(vector) - 1 bytes after the last
7082 // requested vector. The point of this is to avoid a page fault if the
7083 // base address happend to be aligned. This works because if the base
7084 // address is aligned, then adding less than a full vector length will
7085 // cause the last vector in the sequence to be (re)loaded. Otherwise,
7086 // the next vector will be fetched as you might suspect was necessary.
7088 // We might be able to reuse the permutation generation from
7089 // a different base address offset from this one by an aligned amount.
7090 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
7091 // optimization later.
7092 SDValue PermCntl = BuildIntrinsicOp(Intrinsic::ppc_altivec_lvsl, Ptr,
7093 DAG, dl, MVT::v16i8);
7095 // Refine the alignment of the original load (a "new" load created here
7096 // which was identical to the first except for the alignment would be
7097 // merged with the existing node regardless).
7098 MachineFunction &MF = DAG.getMachineFunction();
7099 MachineMemOperand *MMO =
7100 MF.getMachineMemOperand(LD->getPointerInfo(),
7101 LD->getMemOperand()->getFlags(),
7102 LD->getMemoryVT().getStoreSize(),
7104 LD->refineAlignment(MMO);
7105 SDValue BaseLoad = SDValue(LD, 0);
7107 // Note that the value of IncOffset (which is provided to the next
7108 // load's pointer info offset value, and thus used to calculate the
7109 // alignment), and the value of IncValue (which is actually used to
7110 // increment the pointer value) are different! This is because we
7111 // require the next load to appear to be aligned, even though it
7112 // is actually offset from the base pointer by a lesser amount.
7113 int IncOffset = VT.getSizeInBits() / 8;
7114 int IncValue = IncOffset;
7116 // Walk (both up and down) the chain looking for another load at the real
7117 // (aligned) offset (the alignment of the other load does not matter in
7118 // this case). If found, then do not use the offset reduction trick, as
7119 // that will prevent the loads from being later combined (as they would
7120 // otherwise be duplicates).
7121 if (!findConsecutiveLoad(LD, DAG))
7124 SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
7125 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
7128 DAG.getLoad(VT, dl, Chain, Ptr,
7129 LD->getPointerInfo().getWithOffset(IncOffset),
7130 LD->isVolatile(), LD->isNonTemporal(),
7131 LD->isInvariant(), ABIAlignment);
7133 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
7134 BaseLoad.getValue(1), ExtraLoad.getValue(1));
7136 if (BaseLoad.getValueType() != MVT::v4i32)
7137 BaseLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, BaseLoad);
7139 if (ExtraLoad.getValueType() != MVT::v4i32)
7140 ExtraLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, ExtraLoad);
7142 SDValue Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
7143 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
7145 if (VT != MVT::v4i32)
7146 Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm);
7148 // Now we need to be really careful about how we update the users of the
7149 // original load. We cannot just call DCI.CombineTo (or
7150 // DAG.ReplaceAllUsesWith for that matter), because the load still has
7151 // uses created here (the permutation for example) that need to stay.
7152 SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
7154 SDUse &Use = UI.getUse();
7156 // Note: BaseLoad is checked here because it might not be N, but a
7158 if (User == Perm.getNode() || User == BaseLoad.getNode() ||
7159 User == TF.getNode() || Use.getResNo() > 1) {
7164 SDValue To = Use.getResNo() ? TF : Perm;
7167 SmallVector<SDValue, 8> Ops;
7168 for (SDNode::op_iterator O = User->op_begin(),
7169 OE = User->op_end(); O != OE; ++O) {
7176 DAG.UpdateNodeOperands(User, Ops.data(), Ops.size());
7179 return SDValue(N, 0);
7183 case ISD::INTRINSIC_WO_CHAIN:
7184 if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() ==
7185 Intrinsic::ppc_altivec_lvsl &&
7186 N->getOperand(1)->getOpcode() == ISD::ADD) {
7187 SDValue Add = N->getOperand(1);
7189 if (DAG.MaskedValueIsZero(Add->getOperand(1),
7190 APInt::getAllOnesValue(4 /* 16 byte alignment */).zext(
7191 Add.getValueType().getScalarType().getSizeInBits()))) {
7192 SDNode *BasePtr = Add->getOperand(0).getNode();
7193 for (SDNode::use_iterator UI = BasePtr->use_begin(),
7194 UE = BasePtr->use_end(); UI != UE; ++UI) {
7195 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
7196 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() ==
7197 Intrinsic::ppc_altivec_lvsl) {
7198 // We've found another LVSL, and this address if an aligned
7199 // multiple of that one. The results will be the same, so use the
7200 // one we've just found instead.
7202 return SDValue(*UI, 0);
7208 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
7209 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
7210 N->getOperand(0).hasOneUse() &&
7211 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
7212 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
7213 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
7214 N->getValueType(0) == MVT::i64))) {
7215 SDValue Load = N->getOperand(0);
7216 LoadSDNode *LD = cast<LoadSDNode>(Load);
7217 // Create the byte-swapping load.
7219 LD->getChain(), // Chain
7220 LD->getBasePtr(), // Ptr
7221 DAG.getValueType(N->getValueType(0)) // VT
7224 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
7225 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
7226 MVT::i64 : MVT::i32, MVT::Other),
7227 Ops, 3, LD->getMemoryVT(), LD->getMemOperand());
7229 // If this is an i16 load, insert the truncate.
7230 SDValue ResVal = BSLoad;
7231 if (N->getValueType(0) == MVT::i16)
7232 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
7234 // First, combine the bswap away. This makes the value produced by the
7236 DCI.CombineTo(N, ResVal);
7238 // Next, combine the load away, we give it a bogus result value but a real
7239 // chain result. The result value is dead because the bswap is dead.
7240 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
7242 // Return N so it doesn't get rechecked!
7243 return SDValue(N, 0);
7247 case PPCISD::VCMP: {
7248 // If a VCMPo node already exists with exactly the same operands as this
7249 // node, use its result instead of this node (VCMPo computes both a CR6 and
7250 // a normal output).
7252 if (!N->getOperand(0).hasOneUse() &&
7253 !N->getOperand(1).hasOneUse() &&
7254 !N->getOperand(2).hasOneUse()) {
7256 // Scan all of the users of the LHS, looking for VCMPo's that match.
7257 SDNode *VCMPoNode = 0;
7259 SDNode *LHSN = N->getOperand(0).getNode();
7260 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
7262 if (UI->getOpcode() == PPCISD::VCMPo &&
7263 UI->getOperand(1) == N->getOperand(1) &&
7264 UI->getOperand(2) == N->getOperand(2) &&
7265 UI->getOperand(0) == N->getOperand(0)) {
7270 // If there is no VCMPo node, or if the flag value has a single use, don't
7272 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
7275 // Look at the (necessarily single) use of the flag value. If it has a
7276 // chain, this transformation is more complex. Note that multiple things
7277 // could use the value result, which we should ignore.
7278 SDNode *FlagUser = 0;
7279 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
7280 FlagUser == 0; ++UI) {
7281 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
7283 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
7284 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
7291 // If the user is a MFOCRF instruction, we know this is safe.
7292 // Otherwise we give up for right now.
7293 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
7294 return SDValue(VCMPoNode, 0);
7299 // If this is a branch on an altivec predicate comparison, lower this so
7300 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
7301 // lowering is done pre-legalize, because the legalizer lowers the predicate
7302 // compare down to code that is difficult to reassemble.
7303 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
7304 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
7306 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
7307 // value. If so, pass-through the AND to get to the intrinsic.
7308 if (LHS.getOpcode() == ISD::AND &&
7309 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
7310 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
7311 Intrinsic::ppc_is_decremented_ctr_nonzero &&
7312 isa<ConstantSDNode>(LHS.getOperand(1)) &&
7313 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
7315 LHS = LHS.getOperand(0);
7317 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
7318 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
7319 Intrinsic::ppc_is_decremented_ctr_nonzero &&
7320 isa<ConstantSDNode>(RHS)) {
7321 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
7322 "Counter decrement comparison is not EQ or NE");
7324 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
7325 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
7326 (CC == ISD::SETNE && !Val);
7328 // We now need to make the intrinsic dead (it cannot be instruction
7330 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
7331 assert(LHS.getNode()->hasOneUse() &&
7332 "Counter decrement has more than one use");
7334 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
7335 N->getOperand(0), N->getOperand(4));
7341 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
7342 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
7343 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
7344 assert(isDot && "Can't compare against a vector result!");
7346 // If this is a comparison against something other than 0/1, then we know
7347 // that the condition is never/always true.
7348 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
7349 if (Val != 0 && Val != 1) {
7350 if (CC == ISD::SETEQ) // Cond never true, remove branch.
7351 return N->getOperand(0);
7352 // Always !=, turn it into an unconditional branch.
7353 return DAG.getNode(ISD::BR, dl, MVT::Other,
7354 N->getOperand(0), N->getOperand(4));
7357 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
7359 // Create the PPCISD altivec 'dot' comparison node.
7361 LHS.getOperand(2), // LHS of compare
7362 LHS.getOperand(3), // RHS of compare
7363 DAG.getConstant(CompareOpc, MVT::i32)
7365 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
7366 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
7368 // Unpack the result based on how the target uses it.
7369 PPC::Predicate CompOpc;
7370 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
7371 default: // Can't happen, don't crash on invalid number though.
7372 case 0: // Branch on the value of the EQ bit of CR6.
7373 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
7375 case 1: // Branch on the inverted value of the EQ bit of CR6.
7376 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
7378 case 2: // Branch on the value of the LT bit of CR6.
7379 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
7381 case 3: // Branch on the inverted value of the LT bit of CR6.
7382 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
7386 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
7387 DAG.getConstant(CompOpc, MVT::i32),
7388 DAG.getRegister(PPC::CR6, MVT::i32),
7389 N->getOperand(4), CompNode.getValue(1));
7398 //===----------------------------------------------------------------------===//
7399 // Inline Assembly Support
7400 //===----------------------------------------------------------------------===//
7402 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
7405 const SelectionDAG &DAG,
7406 unsigned Depth) const {
7407 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
7408 switch (Op.getOpcode()) {
7410 case PPCISD::LBRX: {
7411 // lhbrx is known to have the top bits cleared out.
7412 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
7413 KnownZero = 0xFFFF0000;
7416 case ISD::INTRINSIC_WO_CHAIN: {
7417 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
7419 case Intrinsic::ppc_altivec_vcmpbfp_p:
7420 case Intrinsic::ppc_altivec_vcmpeqfp_p:
7421 case Intrinsic::ppc_altivec_vcmpequb_p:
7422 case Intrinsic::ppc_altivec_vcmpequh_p:
7423 case Intrinsic::ppc_altivec_vcmpequw_p:
7424 case Intrinsic::ppc_altivec_vcmpgefp_p:
7425 case Intrinsic::ppc_altivec_vcmpgtfp_p:
7426 case Intrinsic::ppc_altivec_vcmpgtsb_p:
7427 case Intrinsic::ppc_altivec_vcmpgtsh_p:
7428 case Intrinsic::ppc_altivec_vcmpgtsw_p:
7429 case Intrinsic::ppc_altivec_vcmpgtub_p:
7430 case Intrinsic::ppc_altivec_vcmpgtuh_p:
7431 case Intrinsic::ppc_altivec_vcmpgtuw_p:
7432 KnownZero = ~1U; // All bits but the low one are known to be zero.
7440 /// getConstraintType - Given a constraint, return the type of
7441 /// constraint it is for this target.
7442 PPCTargetLowering::ConstraintType
7443 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
7444 if (Constraint.size() == 1) {
7445 switch (Constraint[0]) {
7452 return C_RegisterClass;
7454 // FIXME: While Z does indicate a memory constraint, it specifically
7455 // indicates an r+r address (used in conjunction with the 'y' modifier
7456 // in the replacement string). Currently, we're forcing the base
7457 // register to be r0 in the asm printer (which is interpreted as zero)
7458 // and forming the complete address in the second register. This is
7463 return TargetLowering::getConstraintType(Constraint);
7466 /// Examine constraint type and operand type and determine a weight value.
7467 /// This object must already have been set up with the operand type
7468 /// and the current alternative constraint selected.
7469 TargetLowering::ConstraintWeight
7470 PPCTargetLowering::getSingleConstraintMatchWeight(
7471 AsmOperandInfo &info, const char *constraint) const {
7472 ConstraintWeight weight = CW_Invalid;
7473 Value *CallOperandVal = info.CallOperandVal;
7474 // If we don't have a value, we can't do a match,
7475 // but allow it at the lowest weight.
7476 if (CallOperandVal == NULL)
7478 Type *type = CallOperandVal->getType();
7479 // Look at the constraint type.
7480 switch (*constraint) {
7482 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
7485 if (type->isIntegerTy())
7486 weight = CW_Register;
7489 if (type->isFloatTy())
7490 weight = CW_Register;
7493 if (type->isDoubleTy())
7494 weight = CW_Register;
7497 if (type->isVectorTy())
7498 weight = CW_Register;
7501 weight = CW_Register;
7510 std::pair<unsigned, const TargetRegisterClass*>
7511 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
7513 if (Constraint.size() == 1) {
7514 // GCC RS6000 Constraint Letters
7515 switch (Constraint[0]) {
7517 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
7518 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
7519 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
7521 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
7522 return std::make_pair(0U, &PPC::G8RCRegClass);
7523 return std::make_pair(0U, &PPC::GPRCRegClass);
7525 if (VT == MVT::f32 || VT == MVT::i32)
7526 return std::make_pair(0U, &PPC::F4RCRegClass);
7527 if (VT == MVT::f64 || VT == MVT::i64)
7528 return std::make_pair(0U, &PPC::F8RCRegClass);
7531 return std::make_pair(0U, &PPC::VRRCRegClass);
7533 return std::make_pair(0U, &PPC::CRRCRegClass);
7537 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
7541 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
7542 /// vector. If it is invalid, don't add anything to Ops.
7543 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
7544 std::string &Constraint,
7545 std::vector<SDValue>&Ops,
7546 SelectionDAG &DAG) const {
7547 SDValue Result(0,0);
7549 // Only support length 1 constraints.
7550 if (Constraint.length() > 1) return;
7552 char Letter = Constraint[0];
7563 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
7564 if (!CST) return; // Must be an immediate to match.
7565 unsigned Value = CST->getZExtValue();
7567 default: llvm_unreachable("Unknown constraint letter!");
7568 case 'I': // "I" is a signed 16-bit constant.
7569 if ((short)Value == (int)Value)
7570 Result = DAG.getTargetConstant(Value, Op.getValueType());
7572 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
7573 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
7574 if ((short)Value == 0)
7575 Result = DAG.getTargetConstant(Value, Op.getValueType());
7577 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
7578 if ((Value >> 16) == 0)
7579 Result = DAG.getTargetConstant(Value, Op.getValueType());
7581 case 'M': // "M" is a constant that is greater than 31.
7583 Result = DAG.getTargetConstant(Value, Op.getValueType());
7585 case 'N': // "N" is a positive constant that is an exact power of two.
7586 if ((int)Value > 0 && isPowerOf2_32(Value))
7587 Result = DAG.getTargetConstant(Value, Op.getValueType());
7589 case 'O': // "O" is the constant zero.
7591 Result = DAG.getTargetConstant(Value, Op.getValueType());
7593 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
7594 if ((short)-Value == (int)-Value)
7595 Result = DAG.getTargetConstant(Value, Op.getValueType());
7602 if (Result.getNode()) {
7603 Ops.push_back(Result);
7607 // Handle standard constraint letters.
7608 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
7611 // isLegalAddressingMode - Return true if the addressing mode represented
7612 // by AM is legal for this target, for a load/store of the specified type.
7613 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
7615 // FIXME: PPC does not allow r+i addressing modes for vectors!
7617 // PPC allows a sign-extended 16-bit immediate field.
7618 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
7621 // No global is ever allowed as a base.
7625 // PPC only support r+r,
7627 case 0: // "r+i" or just "i", depending on HasBaseReg.
7630 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
7632 // Otherwise we have r+r or r+i.
7635 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
7637 // Allow 2*r as r+r.
7640 // No other scales are supported.
7647 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
7648 SelectionDAG &DAG) const {
7649 MachineFunction &MF = DAG.getMachineFunction();
7650 MachineFrameInfo *MFI = MF.getFrameInfo();
7651 MFI->setReturnAddressIsTaken(true);
7654 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7656 // Make sure the function does not optimize away the store of the RA to
7658 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
7659 FuncInfo->setLRStoreRequired();
7660 bool isPPC64 = PPCSubTarget.isPPC64();
7661 bool isDarwinABI = PPCSubTarget.isDarwinABI();
7664 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
7667 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
7668 isPPC64? MVT::i64 : MVT::i32);
7669 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7670 DAG.getNode(ISD::ADD, dl, getPointerTy(),
7672 MachinePointerInfo(), false, false, false, 0);
7675 // Just load the return address off the stack.
7676 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
7677 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7678 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
7681 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
7682 SelectionDAG &DAG) const {
7684 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7686 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
7687 bool isPPC64 = PtrVT == MVT::i64;
7689 MachineFunction &MF = DAG.getMachineFunction();
7690 MachineFrameInfo *MFI = MF.getFrameInfo();
7691 MFI->setFrameAddressIsTaken(true);
7693 // Naked functions never have a frame pointer, and so we use r1. For all
7694 // other functions, this decision must be delayed until during PEI.
7696 if (MF.getFunction()->getAttributes().hasAttribute(
7697 AttributeSet::FunctionIndex, Attribute::Naked))
7698 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
7700 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
7702 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
7705 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
7706 FrameAddr, MachinePointerInfo(), false, false,
7712 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
7713 // The PowerPC target isn't yet aware of offsets.
7717 /// getOptimalMemOpType - Returns the target specific optimal type for load
7718 /// and store operations as a result of memset, memcpy, and memmove
7719 /// lowering. If DstAlign is zero that means it's safe to destination
7720 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
7721 /// means there isn't a need to check it against alignment requirement,
7722 /// probably because the source does not need to be loaded. If 'IsMemset' is
7723 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
7724 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
7725 /// source is constant so it does not need to be loaded.
7726 /// It returns EVT::Other if the type should be determined using generic
7727 /// target-independent logic.
7728 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
7729 unsigned DstAlign, unsigned SrcAlign,
7730 bool IsMemset, bool ZeroMemset,
7732 MachineFunction &MF) const {
7733 if (this->PPCSubTarget.isPPC64()) {
7740 bool PPCTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
7742 if (DisablePPCUnaligned)
7745 // PowerPC supports unaligned memory access for simple non-vector types.
7746 // Although accessing unaligned addresses is not as efficient as accessing
7747 // aligned addresses, it is generally more efficient than manual expansion,
7748 // and generally only traps for software emulation when crossing page
7754 if (VT.getSimpleVT().isVector())
7757 if (VT == MVT::ppcf128)
7766 /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than
7767 /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to
7768 /// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd
7769 /// is expanded to mul + add.
7770 bool PPCTargetLowering::isFMAFasterThanMulAndAdd(EVT VT) const {
7774 switch (VT.getSimpleVT().SimpleTy) {
7786 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
7788 return TargetLowering::getSchedulingPreference(N);