1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCMachineFunctionInfo.h"
16 #include "PPCPredicates.h"
17 #include "PPCTargetMachine.h"
18 #include "PPCPerfectShuffle.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/VectorExtras.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/PseudoSourceValue.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CallingConv.h"
29 #include "llvm/Constants.h"
30 #include "llvm/Function.h"
31 #include "llvm/Intrinsics.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/Target/TargetLoweringObjectFile.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/DerivedTypes.h"
41 static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
42 CCValAssign::LocInfo &LocInfo,
43 ISD::ArgFlagsTy &ArgFlags,
45 static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, EVT &ValVT,
47 CCValAssign::LocInfo &LocInfo,
48 ISD::ArgFlagsTy &ArgFlags,
50 static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, EVT &ValVT,
52 CCValAssign::LocInfo &LocInfo,
53 ISD::ArgFlagsTy &ArgFlags,
56 static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc",
57 cl::desc("enable preincrement load/store generation on PPC (experimental)"),
60 static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) {
61 if (TM.getSubtargetImpl()->isDarwin())
62 return new TargetLoweringObjectFileMachO();
63 return new TargetLoweringObjectFileELF(true);
67 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
68 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) {
72 // Use _setjmp/_longjmp instead of setjmp/longjmp.
73 setUseUnderscoreSetJmp(true);
74 setUseUnderscoreLongJmp(true);
76 // Set up the register classes.
77 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
78 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
79 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
81 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
82 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
83 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
85 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
87 // PowerPC has pre-inc load and store's.
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
91 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
92 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
93 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
99 // This is used in the ppcf128->int sequence. Note it has different semantics
100 // from FP_ROUND: that rounds to nearest, this rounds to zero.
101 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
103 // PowerPC has no SREM/UREM instructions
104 setOperationAction(ISD::SREM, MVT::i32, Expand);
105 setOperationAction(ISD::UREM, MVT::i32, Expand);
106 setOperationAction(ISD::SREM, MVT::i64, Expand);
107 setOperationAction(ISD::UREM, MVT::i64, Expand);
109 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
110 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
111 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
112 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
113 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
114 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
115 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
116 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
117 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
119 // We don't support sin/cos/sqrt/fmod/pow
120 setOperationAction(ISD::FSIN , MVT::f64, Expand);
121 setOperationAction(ISD::FCOS , MVT::f64, Expand);
122 setOperationAction(ISD::FREM , MVT::f64, Expand);
123 setOperationAction(ISD::FPOW , MVT::f64, Expand);
124 setOperationAction(ISD::FSIN , MVT::f32, Expand);
125 setOperationAction(ISD::FCOS , MVT::f32, Expand);
126 setOperationAction(ISD::FREM , MVT::f32, Expand);
127 setOperationAction(ISD::FPOW , MVT::f32, Expand);
129 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
131 // If we're enabling GP optimizations, use hardware square root
132 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
133 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
134 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
137 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
138 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
140 // PowerPC does not have BSWAP, CTPOP or CTTZ
141 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
142 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
143 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
144 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
145 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
146 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
148 // PowerPC does not have ROTR
149 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
150 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
152 // PowerPC does not have Select
153 setOperationAction(ISD::SELECT, MVT::i32, Expand);
154 setOperationAction(ISD::SELECT, MVT::i64, Expand);
155 setOperationAction(ISD::SELECT, MVT::f32, Expand);
156 setOperationAction(ISD::SELECT, MVT::f64, Expand);
158 // PowerPC wants to turn select_cc of FP into fsel when possible.
159 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
160 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
162 // PowerPC wants to optimize integer setcc a bit
163 setOperationAction(ISD::SETCC, MVT::i32, Custom);
165 // PowerPC does not have BRCOND which requires SetCC
166 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
168 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
170 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
171 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
173 // PowerPC does not have [U|S]INT_TO_FP
174 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
175 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
177 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
178 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
179 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
180 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
182 // We cannot sextinreg(i1). Expand to shifts.
183 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
185 // Support label based line numbers.
186 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
187 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
189 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
190 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
191 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
192 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
195 // We want to legalize GlobalAddress and ConstantPool nodes into the
196 // appropriate instructions to materialize the address.
197 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
198 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
199 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
200 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
201 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
202 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
203 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
204 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
207 setOperationAction(ISD::TRAP, MVT::Other, Legal);
209 // TRAMPOLINE is custom lowered.
210 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
212 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
213 setOperationAction(ISD::VASTART , MVT::Other, Custom);
215 // VAARG is custom lowered with the SVR4 ABI
216 if (TM.getSubtarget<PPCSubtarget>().isSVR4ABI())
217 setOperationAction(ISD::VAARG, MVT::Other, Custom);
219 setOperationAction(ISD::VAARG, MVT::Other, Expand);
221 // Use the default implementation.
222 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
223 setOperationAction(ISD::VAEND , MVT::Other, Expand);
224 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
225 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
226 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
227 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
229 // We want to custom lower some of our intrinsics.
230 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
232 // Comparisons that require checking two conditions.
233 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
234 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
235 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
236 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
237 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
238 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
239 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
240 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
241 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
242 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
243 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
244 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
246 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
247 // They also have instructions for converting between i64 and fp.
248 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
249 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
250 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
251 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
252 // This is just the low 32 bits of a (signed) fp->i64 conversion.
253 // We cannot do this with Promote because i64 is not a legal type.
254 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
256 // FIXME: disable this lowered code. This generates 64-bit register values,
257 // and we don't model the fact that the top part is clobbered by calls. We
258 // need to flag these together so that the value isn't live across a call.
259 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
261 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
262 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
265 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
266 // 64-bit PowerPC implementations can support i64 types directly
267 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
268 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
269 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
270 // 64-bit PowerPC wants to expand i128 shifts itself.
271 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
272 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
273 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
275 // 32-bit PowerPC wants to expand i64 shifts itself.
276 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
277 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
278 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
281 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
282 // First set operation action for all vector types to expand. Then we
283 // will selectively turn on ones that can be effectively codegen'd.
284 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
285 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
286 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
288 // add/sub are legal for all supported vector VT's.
289 setOperationAction(ISD::ADD , VT, Legal);
290 setOperationAction(ISD::SUB , VT, Legal);
292 // We promote all shuffles to v16i8.
293 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
294 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
296 // We promote all non-typed operations to v4i32.
297 setOperationAction(ISD::AND , VT, Promote);
298 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
299 setOperationAction(ISD::OR , VT, Promote);
300 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
301 setOperationAction(ISD::XOR , VT, Promote);
302 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
303 setOperationAction(ISD::LOAD , VT, Promote);
304 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
305 setOperationAction(ISD::SELECT, VT, Promote);
306 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
307 setOperationAction(ISD::STORE, VT, Promote);
308 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
310 // No other operations are legal.
311 setOperationAction(ISD::MUL , VT, Expand);
312 setOperationAction(ISD::SDIV, VT, Expand);
313 setOperationAction(ISD::SREM, VT, Expand);
314 setOperationAction(ISD::UDIV, VT, Expand);
315 setOperationAction(ISD::UREM, VT, Expand);
316 setOperationAction(ISD::FDIV, VT, Expand);
317 setOperationAction(ISD::FNEG, VT, Expand);
318 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
319 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
320 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
321 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
322 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
323 setOperationAction(ISD::UDIVREM, VT, Expand);
324 setOperationAction(ISD::SDIVREM, VT, Expand);
325 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
326 setOperationAction(ISD::FPOW, VT, Expand);
327 setOperationAction(ISD::CTPOP, VT, Expand);
328 setOperationAction(ISD::CTLZ, VT, Expand);
329 setOperationAction(ISD::CTTZ, VT, Expand);
332 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
333 // with merges, splats, etc.
334 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
336 setOperationAction(ISD::AND , MVT::v4i32, Legal);
337 setOperationAction(ISD::OR , MVT::v4i32, Legal);
338 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
339 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
340 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
341 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
343 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
344 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
345 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
346 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
348 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
349 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
350 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
351 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
353 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
354 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
356 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
357 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
358 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
359 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
362 setShiftAmountType(MVT::i32);
363 setBooleanContents(ZeroOrOneBooleanContent);
365 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
366 setStackPointerRegisterToSaveRestore(PPC::X1);
367 setExceptionPointerRegister(PPC::X3);
368 setExceptionSelectorRegister(PPC::X4);
370 setStackPointerRegisterToSaveRestore(PPC::R1);
371 setExceptionPointerRegister(PPC::R3);
372 setExceptionSelectorRegister(PPC::R4);
375 // We have target-specific dag combine patterns for the following nodes:
376 setTargetDAGCombine(ISD::SINT_TO_FP);
377 setTargetDAGCombine(ISD::STORE);
378 setTargetDAGCombine(ISD::BR_CC);
379 setTargetDAGCombine(ISD::BSWAP);
381 // Darwin long double math library functions have $LDBL128 appended.
382 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) {
383 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
384 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
385 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
386 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
387 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
388 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
389 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
390 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
391 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
392 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
395 computeRegisterProperties();
398 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
399 /// function arguments in the caller parameter area.
400 unsigned PPCTargetLowering::getByValTypeAlignment(const Type *Ty) const {
401 TargetMachine &TM = getTargetMachine();
402 // Darwin passes everything on 4 byte boundary.
403 if (TM.getSubtarget<PPCSubtarget>().isDarwin())
409 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
412 case PPCISD::FSEL: return "PPCISD::FSEL";
413 case PPCISD::FCFID: return "PPCISD::FCFID";
414 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
415 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
416 case PPCISD::STFIWX: return "PPCISD::STFIWX";
417 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
418 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
419 case PPCISD::VPERM: return "PPCISD::VPERM";
420 case PPCISD::Hi: return "PPCISD::Hi";
421 case PPCISD::Lo: return "PPCISD::Lo";
422 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
423 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
424 case PPCISD::SRL: return "PPCISD::SRL";
425 case PPCISD::SRA: return "PPCISD::SRA";
426 case PPCISD::SHL: return "PPCISD::SHL";
427 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
428 case PPCISD::STD_32: return "PPCISD::STD_32";
429 case PPCISD::CALL_SVR4: return "PPCISD::CALL_SVR4";
430 case PPCISD::CALL_Darwin: return "PPCISD::CALL_Darwin";
431 case PPCISD::MTCTR: return "PPCISD::MTCTR";
432 case PPCISD::BCTRL_Darwin: return "PPCISD::BCTRL_Darwin";
433 case PPCISD::BCTRL_SVR4: return "PPCISD::BCTRL_SVR4";
434 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
435 case PPCISD::MFCR: return "PPCISD::MFCR";
436 case PPCISD::VCMP: return "PPCISD::VCMP";
437 case PPCISD::VCMPo: return "PPCISD::VCMPo";
438 case PPCISD::LBRX: return "PPCISD::LBRX";
439 case PPCISD::STBRX: return "PPCISD::STBRX";
440 case PPCISD::LARX: return "PPCISD::LARX";
441 case PPCISD::STCX: return "PPCISD::STCX";
442 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
443 case PPCISD::MFFS: return "PPCISD::MFFS";
444 case PPCISD::MTFSB0: return "PPCISD::MTFSB0";
445 case PPCISD::MTFSB1: return "PPCISD::MTFSB1";
446 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
447 case PPCISD::MTFSF: return "PPCISD::MTFSF";
448 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
452 MVT::SimpleValueType PPCTargetLowering::getSetCCResultType(EVT VT) const {
456 /// getFunctionAlignment - Return the Log2 alignment of this function.
457 unsigned PPCTargetLowering::getFunctionAlignment(const Function *F) const {
458 if (getTargetMachine().getSubtarget<PPCSubtarget>().isDarwin())
459 return F->hasFnAttr(Attribute::OptimizeForSize) ? 2 : 4;
464 //===----------------------------------------------------------------------===//
465 // Node matching predicates, for use by the tblgen matching code.
466 //===----------------------------------------------------------------------===//
468 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
469 static bool isFloatingPointZero(SDValue Op) {
470 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
471 return CFP->getValueAPF().isZero();
472 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
473 // Maybe this has already been legalized into the constant pool?
474 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
475 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
476 return CFP->getValueAPF().isZero();
481 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
482 /// true if Op is undef or if it matches the specified value.
483 static bool isConstantOrUndef(int Op, int Val) {
484 return Op < 0 || Op == Val;
487 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
488 /// VPKUHUM instruction.
489 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
491 for (unsigned i = 0; i != 16; ++i)
492 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
495 for (unsigned i = 0; i != 8; ++i)
496 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) ||
497 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1))
503 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
504 /// VPKUWUM instruction.
505 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
507 for (unsigned i = 0; i != 16; i += 2)
508 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
509 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
512 for (unsigned i = 0; i != 8; i += 2)
513 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
514 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) ||
515 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) ||
516 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3))
522 /// isVMerge - Common function, used to match vmrg* shuffles.
524 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
525 unsigned LHSStart, unsigned RHSStart) {
526 assert(N->getValueType(0) == MVT::v16i8 &&
527 "PPC only supports shuffles by bytes!");
528 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
529 "Unsupported merge size!");
531 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
532 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
533 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
534 LHSStart+j+i*UnitSize) ||
535 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
536 RHSStart+j+i*UnitSize))
542 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
543 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
544 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
547 return isVMerge(N, UnitSize, 8, 24);
548 return isVMerge(N, UnitSize, 8, 8);
551 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
552 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
553 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
556 return isVMerge(N, UnitSize, 0, 16);
557 return isVMerge(N, UnitSize, 0, 0);
561 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
562 /// amount, otherwise return -1.
563 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
564 assert(N->getValueType(0) == MVT::v16i8 &&
565 "PPC only supports shuffles by bytes!");
567 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
569 // Find the first non-undef value in the shuffle mask.
571 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
574 if (i == 16) return -1; // all undef.
576 // Otherwise, check to see if the rest of the elements are consecutively
577 // numbered from this value.
578 unsigned ShiftAmt = SVOp->getMaskElt(i);
579 if (ShiftAmt < i) return -1;
583 // Check the rest of the elements to see if they are consecutive.
584 for (++i; i != 16; ++i)
585 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
588 // Check the rest of the elements to see if they are consecutive.
589 for (++i; i != 16; ++i)
590 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
596 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
597 /// specifies a splat of a single element that is suitable for input to
598 /// VSPLTB/VSPLTH/VSPLTW.
599 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
600 assert(N->getValueType(0) == MVT::v16i8 &&
601 (EltSize == 1 || EltSize == 2 || EltSize == 4));
603 // This is a splat operation if each element of the permute is the same, and
604 // if the value doesn't reference the second vector.
605 unsigned ElementBase = N->getMaskElt(0);
607 // FIXME: Handle UNDEF elements too!
608 if (ElementBase >= 16)
611 // Check that the indices are consecutive, in the case of a multi-byte element
612 // splatted with a v16i8 mask.
613 for (unsigned i = 1; i != EltSize; ++i)
614 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
617 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
618 if (N->getMaskElt(i) < 0) continue;
619 for (unsigned j = 0; j != EltSize; ++j)
620 if (N->getMaskElt(i+j) != N->getMaskElt(j))
626 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
628 bool PPC::isAllNegativeZeroVector(SDNode *N) {
629 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
631 APInt APVal, APUndef;
635 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32))
636 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
637 return CFP->getValueAPF().isNegZero();
642 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
643 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
644 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
645 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
646 assert(isSplatShuffleMask(SVOp, EltSize));
647 return SVOp->getMaskElt(0) / EltSize;
650 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
651 /// by using a vspltis[bhw] instruction of the specified element size, return
652 /// the constant being splatted. The ByteSize field indicates the number of
653 /// bytes of each element [124] -> [bhw].
654 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
657 // If ByteSize of the splat is bigger than the element size of the
658 // build_vector, then we have a case where we are checking for a splat where
659 // multiple elements of the buildvector are folded together into a single
660 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
661 unsigned EltSize = 16/N->getNumOperands();
662 if (EltSize < ByteSize) {
663 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
664 SDValue UniquedVals[4];
665 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
667 // See if all of the elements in the buildvector agree across.
668 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
669 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
670 // If the element isn't a constant, bail fully out.
671 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
674 if (UniquedVals[i&(Multiple-1)].getNode() == 0)
675 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
676 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
677 return SDValue(); // no match.
680 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
681 // either constant or undef values that are identical for each chunk. See
682 // if these chunks can form into a larger vspltis*.
684 // Check to see if all of the leading entries are either 0 or -1. If
685 // neither, then this won't fit into the immediate field.
686 bool LeadingZero = true;
687 bool LeadingOnes = true;
688 for (unsigned i = 0; i != Multiple-1; ++i) {
689 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs.
691 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
692 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
694 // Finally, check the least significant entry.
696 if (UniquedVals[Multiple-1].getNode() == 0)
697 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
698 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
700 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
703 if (UniquedVals[Multiple-1].getNode() == 0)
704 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
705 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
706 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
707 return DAG.getTargetConstant(Val, MVT::i32);
713 // Check to see if this buildvec has a single non-undef value in its elements.
714 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
715 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
716 if (OpVal.getNode() == 0)
717 OpVal = N->getOperand(i);
718 else if (OpVal != N->getOperand(i))
722 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def.
724 unsigned ValSizeInBytes = EltSize;
726 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
727 Value = CN->getZExtValue();
728 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
729 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
730 Value = FloatToBits(CN->getValueAPF().convertToFloat());
733 // If the splat value is larger than the element value, then we can never do
734 // this splat. The only case that we could fit the replicated bits into our
735 // immediate field for would be zero, and we prefer to use vxor for it.
736 if (ValSizeInBytes < ByteSize) return SDValue();
738 // If the element value is larger than the splat value, cut it in half and
739 // check to see if the two halves are equal. Continue doing this until we
740 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
741 while (ValSizeInBytes > ByteSize) {
742 ValSizeInBytes >>= 1;
744 // If the top half equals the bottom half, we're still ok.
745 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
746 (Value & ((1 << (8*ValSizeInBytes))-1)))
750 // Properly sign extend the value.
751 int ShAmt = (4-ByteSize)*8;
752 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
754 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
755 if (MaskVal == 0) return SDValue();
757 // Finally, if this value fits in a 5 bit sext field, return it
758 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
759 return DAG.getTargetConstant(MaskVal, MVT::i32);
763 //===----------------------------------------------------------------------===//
764 // Addressing Mode Selection
765 //===----------------------------------------------------------------------===//
767 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
768 /// or 64-bit immediate, and if the value can be accurately represented as a
769 /// sign extension from a 16-bit value. If so, this returns true and the
771 static bool isIntS16Immediate(SDNode *N, short &Imm) {
772 if (N->getOpcode() != ISD::Constant)
775 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
776 if (N->getValueType(0) == MVT::i32)
777 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
779 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
781 static bool isIntS16Immediate(SDValue Op, short &Imm) {
782 return isIntS16Immediate(Op.getNode(), Imm);
786 /// SelectAddressRegReg - Given the specified addressed, check to see if it
787 /// can be represented as an indexed [r+r] operation. Returns false if it
788 /// can be more efficiently represented with [r+imm].
789 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
791 SelectionDAG &DAG) const {
793 if (N.getOpcode() == ISD::ADD) {
794 if (isIntS16Immediate(N.getOperand(1), imm))
796 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
799 Base = N.getOperand(0);
800 Index = N.getOperand(1);
802 } else if (N.getOpcode() == ISD::OR) {
803 if (isIntS16Immediate(N.getOperand(1), imm))
804 return false; // r+i can fold it if we can.
806 // If this is an or of disjoint bitfields, we can codegen this as an add
807 // (for better address arithmetic) if the LHS and RHS of the OR are provably
809 APInt LHSKnownZero, LHSKnownOne;
810 APInt RHSKnownZero, RHSKnownOne;
811 DAG.ComputeMaskedBits(N.getOperand(0),
812 APInt::getAllOnesValue(N.getOperand(0)
813 .getValueSizeInBits()),
814 LHSKnownZero, LHSKnownOne);
816 if (LHSKnownZero.getBoolValue()) {
817 DAG.ComputeMaskedBits(N.getOperand(1),
818 APInt::getAllOnesValue(N.getOperand(1)
819 .getValueSizeInBits()),
820 RHSKnownZero, RHSKnownOne);
821 // If all of the bits are known zero on the LHS or RHS, the add won't
823 if (~(LHSKnownZero | RHSKnownZero) == 0) {
824 Base = N.getOperand(0);
825 Index = N.getOperand(1);
834 /// Returns true if the address N can be represented by a base register plus
835 /// a signed 16-bit displacement [r+imm], and if it is not better
836 /// represented as reg+reg.
837 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
839 SelectionDAG &DAG) const {
840 // FIXME dl should come from parent load or store, not from address
841 DebugLoc dl = N.getDebugLoc();
842 // If this can be more profitably realized as r+r, fail.
843 if (SelectAddressRegReg(N, Disp, Base, DAG))
846 if (N.getOpcode() == ISD::ADD) {
848 if (isIntS16Immediate(N.getOperand(1), imm)) {
849 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
850 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
851 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
853 Base = N.getOperand(0);
855 return true; // [r+i]
856 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
857 // Match LOAD (ADD (X, Lo(G))).
858 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
859 && "Cannot handle constant offsets yet!");
860 Disp = N.getOperand(1).getOperand(0); // The global address.
861 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
862 Disp.getOpcode() == ISD::TargetConstantPool ||
863 Disp.getOpcode() == ISD::TargetJumpTable);
864 Base = N.getOperand(0);
865 return true; // [&g+r]
867 } else if (N.getOpcode() == ISD::OR) {
869 if (isIntS16Immediate(N.getOperand(1), imm)) {
870 // If this is an or of disjoint bitfields, we can codegen this as an add
871 // (for better address arithmetic) if the LHS and RHS of the OR are
872 // provably disjoint.
873 APInt LHSKnownZero, LHSKnownOne;
874 DAG.ComputeMaskedBits(N.getOperand(0),
875 APInt::getAllOnesValue(N.getOperand(0)
876 .getValueSizeInBits()),
877 LHSKnownZero, LHSKnownOne);
879 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
880 // If all of the bits are known zero on the LHS or RHS, the add won't
882 Base = N.getOperand(0);
883 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
887 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
888 // Loading from a constant address.
890 // If this address fits entirely in a 16-bit sext immediate field, codegen
893 if (isIntS16Immediate(CN, Imm)) {
894 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
895 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
899 // Handle 32-bit sext immediates with LIS + addr mode.
900 if (CN->getValueType(0) == MVT::i32 ||
901 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
902 int Addr = (int)CN->getZExtValue();
904 // Otherwise, break this down into an LIS + disp.
905 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
907 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
908 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
909 Base = SDValue(DAG.getTargetNode(Opc, dl, CN->getValueType(0), Base), 0);
914 Disp = DAG.getTargetConstant(0, getPointerTy());
915 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
916 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
919 return true; // [r+0]
922 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
923 /// represented as an indexed [r+r] operation.
924 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
926 SelectionDAG &DAG) const {
927 // Check to see if we can easily represent this as an [r+r] address. This
928 // will fail if it thinks that the address is more profitably represented as
929 // reg+imm, e.g. where imm = 0.
930 if (SelectAddressRegReg(N, Base, Index, DAG))
933 // If the operand is an addition, always emit this as [r+r], since this is
934 // better (for code size, and execution, as the memop does the add for free)
935 // than emitting an explicit add.
936 if (N.getOpcode() == ISD::ADD) {
937 Base = N.getOperand(0);
938 Index = N.getOperand(1);
942 // Otherwise, do it the hard way, using R0 as the base register.
943 Base = DAG.getRegister(PPC::R0, N.getValueType());
948 /// SelectAddressRegImmShift - Returns true if the address N can be
949 /// represented by a base register plus a signed 14-bit displacement
950 /// [r+imm*4]. Suitable for use by STD and friends.
951 bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp,
953 SelectionDAG &DAG) const {
954 // FIXME dl should come from the parent load or store, not the address
955 DebugLoc dl = N.getDebugLoc();
956 // If this can be more profitably realized as r+r, fail.
957 if (SelectAddressRegReg(N, Disp, Base, DAG))
960 if (N.getOpcode() == ISD::ADD) {
962 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
963 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
964 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
965 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
967 Base = N.getOperand(0);
969 return true; // [r+i]
970 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
971 // Match LOAD (ADD (X, Lo(G))).
972 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
973 && "Cannot handle constant offsets yet!");
974 Disp = N.getOperand(1).getOperand(0); // The global address.
975 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
976 Disp.getOpcode() == ISD::TargetConstantPool ||
977 Disp.getOpcode() == ISD::TargetJumpTable);
978 Base = N.getOperand(0);
979 return true; // [&g+r]
981 } else if (N.getOpcode() == ISD::OR) {
983 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
984 // If this is an or of disjoint bitfields, we can codegen this as an add
985 // (for better address arithmetic) if the LHS and RHS of the OR are
986 // provably disjoint.
987 APInt LHSKnownZero, LHSKnownOne;
988 DAG.ComputeMaskedBits(N.getOperand(0),
989 APInt::getAllOnesValue(N.getOperand(0)
990 .getValueSizeInBits()),
991 LHSKnownZero, LHSKnownOne);
992 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
993 // If all of the bits are known zero on the LHS or RHS, the add won't
995 Base = N.getOperand(0);
996 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
1000 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1001 // Loading from a constant address. Verify low two bits are clear.
1002 if ((CN->getZExtValue() & 3) == 0) {
1003 // If this address fits entirely in a 14-bit sext immediate field, codegen
1006 if (isIntS16Immediate(CN, Imm)) {
1007 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
1008 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
1012 // Fold the low-part of 32-bit absolute addresses into addr mode.
1013 if (CN->getValueType(0) == MVT::i32 ||
1014 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
1015 int Addr = (int)CN->getZExtValue();
1017 // Otherwise, break this down into an LIS + disp.
1018 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
1019 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
1020 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1021 Base = SDValue(DAG.getTargetNode(Opc, dl, CN->getValueType(0), Base),0);
1027 Disp = DAG.getTargetConstant(0, getPointerTy());
1028 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
1029 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1032 return true; // [r+0]
1036 /// getPreIndexedAddressParts - returns true by value, base pointer and
1037 /// offset pointer and addressing mode by reference if the node's address
1038 /// can be legally represented as pre-indexed load / store address.
1039 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1041 ISD::MemIndexedMode &AM,
1042 SelectionDAG &DAG) const {
1043 // Disabled by default for now.
1044 if (!EnablePPCPreinc) return false;
1048 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1049 Ptr = LD->getBasePtr();
1050 VT = LD->getMemoryVT();
1052 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1054 Ptr = ST->getBasePtr();
1055 VT = ST->getMemoryVT();
1059 // PowerPC doesn't have preinc load/store instructions for vectors.
1063 // TODO: Check reg+reg first.
1065 // LDU/STU use reg+imm*4, others use reg+imm.
1066 if (VT != MVT::i64) {
1068 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
1072 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
1076 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1077 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1078 // sext i32 to i64 when addr mode is r+i.
1079 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1080 LD->getExtensionType() == ISD::SEXTLOAD &&
1081 isa<ConstantSDNode>(Offset))
1089 //===----------------------------------------------------------------------===//
1090 // LowerOperation implementation
1091 //===----------------------------------------------------------------------===//
1093 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1094 SelectionDAG &DAG) {
1095 EVT PtrVT = Op.getValueType();
1096 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1097 Constant *C = CP->getConstVal();
1098 SDValue CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
1099 SDValue Zero = DAG.getConstant(0, PtrVT);
1100 // FIXME there isn't really any debug info here
1101 DebugLoc dl = Op.getDebugLoc();
1103 const TargetMachine &TM = DAG.getTarget();
1105 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, CPI, Zero);
1106 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, CPI, Zero);
1108 // If this is a non-darwin platform, we don't support non-static relo models
1110 if (TM.getRelocationModel() == Reloc::Static ||
1111 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1112 // Generate non-pic code that has direct accesses to the constant pool.
1113 // The address of the global is just (hi(&g)+lo(&g)).
1114 return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1117 if (TM.getRelocationModel() == Reloc::PIC_) {
1118 // With PIC, the first instruction is actually "GR+hi(&G)".
1119 Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
1120 DAG.getNode(PPCISD::GlobalBaseReg,
1121 DebugLoc::getUnknownLoc(), PtrVT), Hi);
1124 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1128 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
1129 EVT PtrVT = Op.getValueType();
1130 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1131 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1132 SDValue Zero = DAG.getConstant(0, PtrVT);
1133 // FIXME there isn't really any debug loc here
1134 DebugLoc dl = Op.getDebugLoc();
1136 const TargetMachine &TM = DAG.getTarget();
1138 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, JTI, Zero);
1139 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, JTI, Zero);
1141 // If this is a non-darwin platform, we don't support non-static relo models
1143 if (TM.getRelocationModel() == Reloc::Static ||
1144 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1145 // Generate non-pic code that has direct accesses to the constant pool.
1146 // The address of the global is just (hi(&g)+lo(&g)).
1147 return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1150 if (TM.getRelocationModel() == Reloc::PIC_) {
1151 // With PIC, the first instruction is actually "GR+hi(&G)".
1152 Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
1153 DAG.getNode(PPCISD::GlobalBaseReg,
1154 DebugLoc::getUnknownLoc(), PtrVT), Hi);
1157 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1161 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1162 SelectionDAG &DAG) {
1163 llvm_unreachable("TLS not implemented for PPC.");
1164 return SDValue(); // Not reached
1167 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1168 SelectionDAG &DAG) {
1169 EVT PtrVT = Op.getValueType();
1170 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1171 GlobalValue *GV = GSDN->getGlobal();
1172 SDValue GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
1173 SDValue Zero = DAG.getConstant(0, PtrVT);
1174 // FIXME there isn't really any debug info here
1175 DebugLoc dl = GSDN->getDebugLoc();
1177 const TargetMachine &TM = DAG.getTarget();
1179 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, GA, Zero);
1180 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, GA, Zero);
1182 // If this is a non-darwin platform, we don't support non-static relo models
1184 if (TM.getRelocationModel() == Reloc::Static ||
1185 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1186 // Generate non-pic code that has direct accesses to globals.
1187 // The address of the global is just (hi(&g)+lo(&g)).
1188 return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1191 if (TM.getRelocationModel() == Reloc::PIC_) {
1192 // With PIC, the first instruction is actually "GR+hi(&G)".
1193 Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
1194 DAG.getNode(PPCISD::GlobalBaseReg,
1195 DebugLoc::getUnknownLoc(), PtrVT), Hi);
1198 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1200 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM))
1203 // If the global is weak or external, we have to go through the lazy
1205 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Lo, NULL, 0);
1208 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
1209 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1210 DebugLoc dl = Op.getDebugLoc();
1212 // If we're comparing for equality to zero, expose the fact that this is
1213 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1214 // fold the new nodes.
1215 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1216 if (C->isNullValue() && CC == ISD::SETEQ) {
1217 EVT VT = Op.getOperand(0).getValueType();
1218 SDValue Zext = Op.getOperand(0);
1219 if (VT.bitsLT(MVT::i32)) {
1221 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1223 unsigned Log2b = Log2_32(VT.getSizeInBits());
1224 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1225 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1226 DAG.getConstant(Log2b, MVT::i32));
1227 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1229 // Leave comparisons against 0 and -1 alone for now, since they're usually
1230 // optimized. FIXME: revisit this when we can custom lower all setcc
1232 if (C->isAllOnesValue() || C->isNullValue())
1236 // If we have an integer seteq/setne, turn it into a compare against zero
1237 // by xor'ing the rhs with the lhs, which is faster than setting a
1238 // condition register, reading it back out, and masking the correct bit. The
1239 // normal approach here uses sub to do this instead of xor. Using xor exposes
1240 // the result to other bit-twiddling opportunities.
1241 EVT LHSVT = Op.getOperand(0).getValueType();
1242 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1243 EVT VT = Op.getValueType();
1244 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1246 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1251 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1252 int VarArgsFrameIndex,
1253 int VarArgsStackOffset,
1254 unsigned VarArgsNumGPR,
1255 unsigned VarArgsNumFPR,
1256 const PPCSubtarget &Subtarget) {
1258 llvm_unreachable("VAARG not yet implemented for the SVR4 ABI!");
1259 return SDValue(); // Not reached
1262 SDValue PPCTargetLowering::LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
1263 SDValue Chain = Op.getOperand(0);
1264 SDValue Trmp = Op.getOperand(1); // trampoline
1265 SDValue FPtr = Op.getOperand(2); // nested function
1266 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1267 DebugLoc dl = Op.getDebugLoc();
1269 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1270 bool isPPC64 = (PtrVT == MVT::i64);
1271 const Type *IntPtrTy =
1272 DAG.getTargetLoweringInfo().getTargetData()->getIntPtrType();
1274 TargetLowering::ArgListTy Args;
1275 TargetLowering::ArgListEntry Entry;
1277 Entry.Ty = IntPtrTy;
1278 Entry.Node = Trmp; Args.push_back(Entry);
1280 // TrampSize == (isPPC64 ? 48 : 40);
1281 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1282 isPPC64 ? MVT::i64 : MVT::i32);
1283 Args.push_back(Entry);
1285 Entry.Node = FPtr; Args.push_back(Entry);
1286 Entry.Node = Nest; Args.push_back(Entry);
1288 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1289 std::pair<SDValue, SDValue> CallResult =
1290 LowerCallTo(Chain, Op.getValueType().getTypeForEVT(),
1291 false, false, false, false, 0, CallingConv::C, false,
1292 /*isReturnValueUsed=*/true,
1293 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1297 { CallResult.first, CallResult.second };
1299 return DAG.getMergeValues(Ops, 2, dl);
1302 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1303 int VarArgsFrameIndex,
1304 int VarArgsStackOffset,
1305 unsigned VarArgsNumGPR,
1306 unsigned VarArgsNumFPR,
1307 const PPCSubtarget &Subtarget) {
1308 DebugLoc dl = Op.getDebugLoc();
1310 if (Subtarget.isDarwinABI()) {
1311 // vastart just stores the address of the VarArgsFrameIndex slot into the
1312 // memory location argument.
1313 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1314 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1315 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1316 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
1319 // For the SVR4 ABI we follow the layout of the va_list struct.
1320 // We suppose the given va_list is already allocated.
1323 // char gpr; /* index into the array of 8 GPRs
1324 // * stored in the register save area
1325 // * gpr=0 corresponds to r3,
1326 // * gpr=1 to r4, etc.
1328 // char fpr; /* index into the array of 8 FPRs
1329 // * stored in the register save area
1330 // * fpr=0 corresponds to f1,
1331 // * fpr=1 to f2, etc.
1333 // char *overflow_arg_area;
1334 // /* location on stack that holds
1335 // * the next overflow argument
1337 // char *reg_save_area;
1338 // /* where r3:r10 and f1:f8 (if saved)
1344 SDValue ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i32);
1345 SDValue ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i32);
1348 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1350 SDValue StackOffsetFI = DAG.getFrameIndex(VarArgsStackOffset, PtrVT);
1351 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1353 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
1354 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1356 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
1357 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1359 uint64_t FPROffset = 1;
1360 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1362 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1364 // Store first byte : number of int regs
1365 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
1366 Op.getOperand(1), SV, 0, MVT::i8);
1367 uint64_t nextOffset = FPROffset;
1368 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
1371 // Store second byte : number of float regs
1372 SDValue secondStore =
1373 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr, SV, nextOffset, MVT::i8);
1374 nextOffset += StackOffset;
1375 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
1377 // Store second word : arguments given on stack
1378 SDValue thirdStore =
1379 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr, SV, nextOffset);
1380 nextOffset += FrameOffset;
1381 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
1383 // Store third word : arguments given in registers
1384 return DAG.getStore(thirdStore, dl, FR, nextPtr, SV, nextOffset);
1388 #include "PPCGenCallingConv.inc"
1390 static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
1391 CCValAssign::LocInfo &LocInfo,
1392 ISD::ArgFlagsTy &ArgFlags,
1397 static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, EVT &ValVT,
1399 CCValAssign::LocInfo &LocInfo,
1400 ISD::ArgFlagsTy &ArgFlags,
1402 static const unsigned ArgRegs[] = {
1403 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1404 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1406 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1408 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1410 // Skip one register if the first unallocated register has an even register
1411 // number and there are still argument registers available which have not been
1412 // allocated yet. RegNum is actually an index into ArgRegs, which means we
1413 // need to skip a register if RegNum is odd.
1414 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
1415 State.AllocateReg(ArgRegs[RegNum]);
1418 // Always return false here, as this function only makes sure that the first
1419 // unallocated register has an odd register number and does not actually
1420 // allocate a register for the current argument.
1424 static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, EVT &ValVT,
1426 CCValAssign::LocInfo &LocInfo,
1427 ISD::ArgFlagsTy &ArgFlags,
1429 static const unsigned ArgRegs[] = {
1430 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1434 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1436 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1438 // If there is only one Floating-point register left we need to put both f64
1439 // values of a split ppc_fp128 value on the stack.
1440 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
1441 State.AllocateReg(ArgRegs[RegNum]);
1444 // Always return false here, as this function only makes sure that the two f64
1445 // values a ppc_fp128 value is split into are both passed in registers or both
1446 // passed on the stack and does not actually allocate a register for the
1447 // current argument.
1451 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1452 /// depending on which subtarget is selected.
1453 static const unsigned *GetFPR(const PPCSubtarget &Subtarget) {
1454 if (Subtarget.isDarwinABI()) {
1455 static const unsigned FPR[] = {
1456 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1457 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1463 static const unsigned FPR[] = {
1464 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1470 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
1472 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
1473 unsigned PtrByteSize) {
1474 unsigned ArgSize = ArgVT.getSizeInBits()/8;
1475 if (Flags.isByVal())
1476 ArgSize = Flags.getByValSize();
1477 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1483 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
1484 unsigned CallConv, bool isVarArg,
1485 const SmallVectorImpl<ISD::InputArg>
1487 DebugLoc dl, SelectionDAG &DAG,
1488 SmallVectorImpl<SDValue> &InVals) {
1489 if (PPCSubTarget.isSVR4ABI()) {
1490 return LowerFormalArguments_SVR4(Chain, CallConv, isVarArg, Ins,
1493 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
1499 PPCTargetLowering::LowerFormalArguments_SVR4(
1501 unsigned CallConv, bool isVarArg,
1502 const SmallVectorImpl<ISD::InputArg>
1504 DebugLoc dl, SelectionDAG &DAG,
1505 SmallVectorImpl<SDValue> &InVals) {
1507 // SVR4 ABI Stack Frame Layout:
1508 // +-----------------------------------+
1509 // +--> | Back chain |
1510 // | +-----------------------------------+
1511 // | | Floating-point register save area |
1512 // | +-----------------------------------+
1513 // | | General register save area |
1514 // | +-----------------------------------+
1515 // | | CR save word |
1516 // | +-----------------------------------+
1517 // | | VRSAVE save word |
1518 // | +-----------------------------------+
1519 // | | Alignment padding |
1520 // | +-----------------------------------+
1521 // | | Vector register save area |
1522 // | +-----------------------------------+
1523 // | | Local variable space |
1524 // | +-----------------------------------+
1525 // | | Parameter list area |
1526 // | +-----------------------------------+
1527 // | | LR save word |
1528 // | +-----------------------------------+
1529 // SP--> +--- | Back chain |
1530 // +-----------------------------------+
1533 // System V Application Binary Interface PowerPC Processor Supplement
1534 // AltiVec Technology Programming Interface Manual
1536 MachineFunction &MF = DAG.getMachineFunction();
1537 MachineFrameInfo *MFI = MF.getFrameInfo();
1539 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1540 // Potential tail calls could cause overwriting of argument stack slots.
1541 bool isImmutable = !(PerformTailCallOpt && (CallConv==CallingConv::Fast));
1542 unsigned PtrByteSize = 4;
1544 // Assign locations to all of the incoming arguments.
1545 SmallVector<CCValAssign, 16> ArgLocs;
1546 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1549 // Reserve space for the linkage area on the stack.
1550 CCInfo.AllocateStack(PPCFrameInfo::getLinkageSize(false, false), PtrByteSize);
1552 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4);
1554 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1555 CCValAssign &VA = ArgLocs[i];
1557 // Arguments stored in registers.
1558 if (VA.isRegLoc()) {
1559 TargetRegisterClass *RC;
1560 EVT ValVT = VA.getValVT();
1562 switch (ValVT.getSimpleVT().SimpleTy) {
1564 llvm_unreachable("ValVT not supported by formal arguments Lowering");
1566 RC = PPC::GPRCRegisterClass;
1569 RC = PPC::F4RCRegisterClass;
1572 RC = PPC::F8RCRegisterClass;
1578 RC = PPC::VRRCRegisterClass;
1582 // Transform the arguments stored in physical registers into virtual ones.
1583 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1584 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT);
1586 InVals.push_back(ArgValue);
1588 // Argument stored in memory.
1589 assert(VA.isMemLoc());
1591 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
1592 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
1595 // Create load nodes to retrieve arguments from the stack.
1596 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1597 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, NULL, 0));
1601 // Assign locations to all of the incoming aggregate by value arguments.
1602 // Aggregates passed by value are stored in the local variable space of the
1603 // caller's stack frame, right above the parameter list area.
1604 SmallVector<CCValAssign, 16> ByValArgLocs;
1605 CCState CCByValInfo(CallConv, isVarArg, getTargetMachine(),
1606 ByValArgLocs, *DAG.getContext());
1608 // Reserve stack space for the allocations in CCInfo.
1609 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
1611 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4_ByVal);
1613 // Area that is at least reserved in the caller of this function.
1614 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
1616 // Set the size that is at least reserved in caller of this function. Tail
1617 // call optimized function's reserved stack space needs to be aligned so that
1618 // taking the difference between two stack areas will result in an aligned
1620 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1623 std::max(MinReservedArea,
1624 PPCFrameInfo::getMinCallFrameSize(false, false));
1626 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
1627 getStackAlignment();
1628 unsigned AlignMask = TargetAlign-1;
1629 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
1631 FI->setMinReservedArea(MinReservedArea);
1633 SmallVector<SDValue, 8> MemOps;
1635 // If the function takes variable number of arguments, make a frame index for
1636 // the start of the first vararg value... for expansion of llvm.va_start.
1638 static const unsigned GPArgRegs[] = {
1639 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1640 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1642 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
1644 static const unsigned FPArgRegs[] = {
1645 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1648 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
1650 VarArgsNumGPR = CCInfo.getFirstUnallocated(GPArgRegs, NumGPArgRegs);
1651 VarArgsNumFPR = CCInfo.getFirstUnallocated(FPArgRegs, NumFPArgRegs);
1653 // Make room for NumGPArgRegs and NumFPArgRegs.
1654 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
1655 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
1657 VarArgsStackOffset = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
1658 CCInfo.getNextStackOffset());
1660 VarArgsFrameIndex = MFI->CreateStackObject(Depth, 8);
1661 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1663 // The fixed integer arguments of a variadic function are
1664 // stored to the VarArgsFrameIndex on the stack.
1665 unsigned GPRIndex = 0;
1666 for (; GPRIndex != VarArgsNumGPR; ++GPRIndex) {
1667 SDValue Val = DAG.getRegister(GPArgRegs[GPRIndex], PtrVT);
1668 SDValue Store = DAG.getStore(Chain, dl, Val, FIN, NULL, 0);
1669 MemOps.push_back(Store);
1670 // Increment the address by four for the next argument to store
1671 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
1672 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1675 // If this function is vararg, store any remaining integer argument regs
1676 // to their spots on the stack so that they may be loaded by deferencing the
1677 // result of va_next.
1678 for (; GPRIndex != NumGPArgRegs; ++GPRIndex) {
1679 unsigned VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
1681 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
1682 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
1683 MemOps.push_back(Store);
1684 // Increment the address by four for the next argument to store
1685 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
1686 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1689 // FIXME SVR4: We only need to save FP argument registers if CR bit 6 is
1692 // The double arguments are stored to the VarArgsFrameIndex
1694 unsigned FPRIndex = 0;
1695 for (FPRIndex = 0; FPRIndex != VarArgsNumFPR; ++FPRIndex) {
1696 SDValue Val = DAG.getRegister(FPArgRegs[FPRIndex], MVT::f64);
1697 SDValue Store = DAG.getStore(Chain, dl, Val, FIN, NULL, 0);
1698 MemOps.push_back(Store);
1699 // Increment the address by eight for the next argument to store
1700 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
1702 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1705 for (; FPRIndex != NumFPArgRegs; ++FPRIndex) {
1706 unsigned VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
1708 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
1709 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
1710 MemOps.push_back(Store);
1711 // Increment the address by eight for the next argument to store
1712 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
1714 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1718 if (!MemOps.empty())
1719 Chain = DAG.getNode(ISD::TokenFactor, dl,
1720 MVT::Other, &MemOps[0], MemOps.size());
1726 PPCTargetLowering::LowerFormalArguments_Darwin(
1728 unsigned CallConv, bool isVarArg,
1729 const SmallVectorImpl<ISD::InputArg>
1731 DebugLoc dl, SelectionDAG &DAG,
1732 SmallVectorImpl<SDValue> &InVals) {
1734 // TODO: add description of PPC stack frame format, or at least some docs.
1736 MachineFunction &MF = DAG.getMachineFunction();
1737 MachineFrameInfo *MFI = MF.getFrameInfo();
1739 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1740 bool isPPC64 = PtrVT == MVT::i64;
1741 // Potential tail calls could cause overwriting of argument stack slots.
1742 bool isImmutable = !(PerformTailCallOpt && (CallConv==CallingConv::Fast));
1743 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1745 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, true);
1746 // Area that is at least reserved in caller of this function.
1747 unsigned MinReservedArea = ArgOffset;
1749 static const unsigned GPR_32[] = { // 32-bit registers.
1750 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1751 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1753 static const unsigned GPR_64[] = { // 64-bit registers.
1754 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1755 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1758 static const unsigned *FPR = GetFPR(PPCSubTarget);
1760 static const unsigned VR[] = {
1761 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1762 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1765 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
1766 const unsigned Num_FPR_Regs = 13;
1767 const unsigned Num_VR_Regs = array_lengthof( VR);
1769 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1771 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1773 // In 32-bit non-varargs functions, the stack space for vectors is after the
1774 // stack space for non-vectors. We do not use this space unless we have
1775 // too many vectors to fit in registers, something that only occurs in
1776 // constructed examples:), but we have to walk the arglist to figure
1777 // that out...for the pathological case, compute VecArgOffset as the
1778 // start of the vector parameter area. Computing VecArgOffset is the
1779 // entire point of the following loop.
1780 unsigned VecArgOffset = ArgOffset;
1781 if (!isVarArg && !isPPC64) {
1782 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
1784 EVT ObjectVT = Ins[ArgNo].VT;
1785 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
1786 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
1788 if (Flags.isByVal()) {
1789 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
1790 ObjSize = Flags.getByValSize();
1792 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1793 VecArgOffset += ArgSize;
1797 switch(ObjectVT.getSimpleVT().SimpleTy) {
1798 default: llvm_unreachable("Unhandled argument type!");
1801 VecArgOffset += isPPC64 ? 8 : 4;
1803 case MVT::i64: // PPC64
1811 // Nothing to do, we're only looking at Nonvector args here.
1816 // We've found where the vector parameter area in memory is. Skip the
1817 // first 12 parameters; these don't use that memory.
1818 VecArgOffset = ((VecArgOffset+15)/16)*16;
1819 VecArgOffset += 12*16;
1821 // Add DAG nodes to load the arguments or copy them out of registers. On
1822 // entry to a function on PPC, the arguments start after the linkage area,
1823 // although the first ones are often in registers.
1825 SmallVector<SDValue, 8> MemOps;
1826 unsigned nAltivecParamsAtEnd = 0;
1827 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
1829 bool needsLoad = false;
1830 EVT ObjectVT = Ins[ArgNo].VT;
1831 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
1832 unsigned ArgSize = ObjSize;
1833 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
1835 unsigned CurArgOffset = ArgOffset;
1837 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
1838 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
1839 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
1840 if (isVarArg || isPPC64) {
1841 MinReservedArea = ((MinReservedArea+15)/16)*16;
1842 MinReservedArea += CalculateStackSlotSize(ObjectVT,
1845 } else nAltivecParamsAtEnd++;
1847 // Calculate min reserved area.
1848 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
1852 // FIXME the codegen can be much improved in some cases.
1853 // We do not have to keep everything in memory.
1854 if (Flags.isByVal()) {
1855 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
1856 ObjSize = Flags.getByValSize();
1857 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1858 // Objects of size 1 and 2 are right justified, everything else is
1859 // left justified. This means the memory address is adjusted forwards.
1860 if (ObjSize==1 || ObjSize==2) {
1861 CurArgOffset = CurArgOffset + (4 - ObjSize);
1863 // The value of the object is its address.
1864 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset);
1865 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1866 InVals.push_back(FIN);
1867 if (ObjSize==1 || ObjSize==2) {
1868 if (GPR_idx != Num_GPR_Regs) {
1869 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
1870 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
1871 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
1872 NULL, 0, ObjSize==1 ? MVT::i8 : MVT::i16 );
1873 MemOps.push_back(Store);
1877 ArgOffset += PtrByteSize;
1881 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
1882 // Store whatever pieces of the object are in registers
1883 // to memory. ArgVal will be address of the beginning of
1885 if (GPR_idx != Num_GPR_Regs) {
1886 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
1887 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset);
1888 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1889 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
1890 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
1891 MemOps.push_back(Store);
1893 ArgOffset += PtrByteSize;
1895 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
1902 switch (ObjectVT.getSimpleVT().SimpleTy) {
1903 default: llvm_unreachable("Unhandled argument type!");
1906 if (GPR_idx != Num_GPR_Regs) {
1907 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
1908 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
1912 ArgSize = PtrByteSize;
1914 // All int arguments reserve stack space in the Darwin ABI.
1915 ArgOffset += PtrByteSize;
1919 case MVT::i64: // PPC64
1920 if (GPR_idx != Num_GPR_Regs) {
1921 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
1922 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1924 if (ObjectVT == MVT::i32) {
1925 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
1926 // value to MVT::i64 and then truncate to the correct register size.
1928 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
1929 DAG.getValueType(ObjectVT));
1930 else if (Flags.isZExt())
1931 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
1932 DAG.getValueType(ObjectVT));
1934 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
1940 ArgSize = PtrByteSize;
1942 // All int arguments reserve stack space in the Darwin ABI.
1948 // Every 4 bytes of argument space consumes one of the GPRs available for
1949 // argument passing.
1950 if (GPR_idx != Num_GPR_Regs) {
1952 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
1955 if (FPR_idx != Num_FPR_Regs) {
1958 if (ObjectVT == MVT::f32)
1959 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
1961 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
1963 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
1969 // All FP arguments reserve stack space in the Darwin ABI.
1970 ArgOffset += isPPC64 ? 8 : ObjSize;
1976 // Note that vector arguments in registers don't reserve stack space,
1977 // except in varargs functions.
1978 if (VR_idx != Num_VR_Regs) {
1979 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
1980 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
1982 while ((ArgOffset % 16) != 0) {
1983 ArgOffset += PtrByteSize;
1984 if (GPR_idx != Num_GPR_Regs)
1988 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs);
1992 if (!isVarArg && !isPPC64) {
1993 // Vectors go after all the nonvectors.
1994 CurArgOffset = VecArgOffset;
1997 // Vectors are aligned.
1998 ArgOffset = ((ArgOffset+15)/16)*16;
1999 CurArgOffset = ArgOffset;
2007 // We need to load the argument to a virtual register if we determined above
2008 // that we ran out of physical registers of the appropriate type.
2010 int FI = MFI->CreateFixedObject(ObjSize,
2011 CurArgOffset + (ArgSize - ObjSize),
2013 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2014 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, NULL, 0);
2017 InVals.push_back(ArgVal);
2020 // Set the size that is at least reserved in caller of this function. Tail
2021 // call optimized function's reserved stack space needs to be aligned so that
2022 // taking the difference between two stack areas will result in an aligned
2024 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2025 // Add the Altivec parameters at the end, if needed.
2026 if (nAltivecParamsAtEnd) {
2027 MinReservedArea = ((MinReservedArea+15)/16)*16;
2028 MinReservedArea += 16*nAltivecParamsAtEnd;
2031 std::max(MinReservedArea,
2032 PPCFrameInfo::getMinCallFrameSize(isPPC64, true));
2033 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
2034 getStackAlignment();
2035 unsigned AlignMask = TargetAlign-1;
2036 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2037 FI->setMinReservedArea(MinReservedArea);
2039 // If the function takes variable number of arguments, make a frame index for
2040 // the start of the first vararg value... for expansion of llvm.va_start.
2042 int Depth = ArgOffset;
2044 VarArgsFrameIndex = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2046 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
2048 // If this function is vararg, store any remaining integer argument regs
2049 // to their spots on the stack so that they may be loaded by deferencing the
2050 // result of va_next.
2051 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2055 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2057 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2059 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2060 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
2061 MemOps.push_back(Store);
2062 // Increment the address by four for the next argument to store
2063 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2064 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2068 if (!MemOps.empty())
2069 Chain = DAG.getNode(ISD::TokenFactor, dl,
2070 MVT::Other, &MemOps[0], MemOps.size());
2075 /// CalculateParameterAndLinkageAreaSize - Get the size of the paramter plus
2076 /// linkage area for the Darwin ABI.
2078 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
2082 const SmallVectorImpl<ISD::OutputArg>
2084 unsigned &nAltivecParamsAtEnd) {
2085 // Count how many bytes are to be pushed on the stack, including the linkage
2086 // area, and parameter passing area. We start with 24/48 bytes, which is
2087 // prereserved space for [SP][CR][LR][3 x unused].
2088 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, true);
2089 unsigned NumOps = Outs.size();
2090 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2092 // Add up all the space actually used.
2093 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
2094 // they all go in registers, but we must reserve stack space for them for
2095 // possible use by the caller. In varargs or 64-bit calls, parameters are
2096 // assigned stack space in order, with padding so Altivec parameters are
2098 nAltivecParamsAtEnd = 0;
2099 for (unsigned i = 0; i != NumOps; ++i) {
2100 SDValue Arg = Outs[i].Val;
2101 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2102 EVT ArgVT = Arg.getValueType();
2103 // Varargs Altivec parameters are padded to a 16 byte boundary.
2104 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
2105 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
2106 if (!isVarArg && !isPPC64) {
2107 // Non-varargs Altivec parameters go after all the non-Altivec
2108 // parameters; handle those later so we know how much padding we need.
2109 nAltivecParamsAtEnd++;
2112 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
2113 NumBytes = ((NumBytes+15)/16)*16;
2115 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2118 // Allow for Altivec parameters at the end, if needed.
2119 if (nAltivecParamsAtEnd) {
2120 NumBytes = ((NumBytes+15)/16)*16;
2121 NumBytes += 16*nAltivecParamsAtEnd;
2124 // The prolog code of the callee may store up to 8 GPR argument registers to
2125 // the stack, allowing va_start to index over them in memory if its varargs.
2126 // Because we cannot tell if this is needed on the caller side, we have to
2127 // conservatively assume that it is needed. As such, make sure we have at
2128 // least enough stack space for the caller to store the 8 GPRs.
2129 NumBytes = std::max(NumBytes,
2130 PPCFrameInfo::getMinCallFrameSize(isPPC64, true));
2132 // Tail call needs the stack to be aligned.
2133 if (CC==CallingConv::Fast && PerformTailCallOpt) {
2134 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
2135 getStackAlignment();
2136 unsigned AlignMask = TargetAlign-1;
2137 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2143 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
2144 /// adjusted to accomodate the arguments for the tailcall.
2145 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool IsTailCall,
2146 unsigned ParamSize) {
2148 if (!IsTailCall) return 0;
2150 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
2151 unsigned CallerMinReservedArea = FI->getMinReservedArea();
2152 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
2153 // Remember only if the new adjustement is bigger.
2154 if (SPDiff < FI->getTailCallSPDelta())
2155 FI->setTailCallSPDelta(SPDiff);
2160 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2161 /// for tail call optimization. Targets which want to do tail call
2162 /// optimization should implement this function.
2164 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2167 const SmallVectorImpl<ISD::InputArg> &Ins,
2168 SelectionDAG& DAG) const {
2169 // Variable argument functions are not supported.
2173 MachineFunction &MF = DAG.getMachineFunction();
2174 unsigned CallerCC = MF.getFunction()->getCallingConv();
2175 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
2176 // Functions containing by val parameters are not supported.
2177 for (unsigned i = 0; i != Ins.size(); i++) {
2178 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2179 if (Flags.isByVal()) return false;
2182 // Non PIC/GOT tail calls are supported.
2183 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
2186 // At the moment we can only do local tail calls (in same module, hidden
2187 // or protected) if we are generating PIC.
2188 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2189 return G->getGlobal()->hasHiddenVisibility()
2190 || G->getGlobal()->hasProtectedVisibility();
2196 /// isCallCompatibleAddress - Return the immediate to use if the specified
2197 /// 32-bit value is representable in the immediate field of a BxA instruction.
2198 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
2199 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2202 int Addr = C->getZExtValue();
2203 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
2204 (Addr << 6 >> 6) != Addr)
2205 return 0; // Top 6 bits have to be sext of immediate.
2207 return DAG.getConstant((int)C->getZExtValue() >> 2,
2208 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
2213 struct TailCallArgumentInfo {
2218 TailCallArgumentInfo() : FrameIdx(0) {}
2223 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
2225 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
2227 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs,
2228 SmallVector<SDValue, 8> &MemOpChains,
2230 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
2231 SDValue Arg = TailCallArgs[i].Arg;
2232 SDValue FIN = TailCallArgs[i].FrameIdxOp;
2233 int FI = TailCallArgs[i].FrameIdx;
2234 // Store relative to framepointer.
2235 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
2236 PseudoSourceValue::getFixedStack(FI),
2241 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
2242 /// the appropriate stack slot for the tail call optimized function call.
2243 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
2244 MachineFunction &MF,
2253 // Calculate the new stack slot for the return address.
2254 int SlotSize = isPPC64 ? 8 : 4;
2255 int NewRetAddrLoc = SPDiff + PPCFrameInfo::getReturnSaveOffset(isPPC64,
2257 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
2259 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2260 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
2261 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
2262 PseudoSourceValue::getFixedStack(NewRetAddr), 0);
2264 // When using the SVR4 ABI there is no need to move the FP stack slot
2265 // as the FP is never overwritten.
2268 SPDiff + PPCFrameInfo::getFramePointerSaveOffset(isPPC64, isDarwinABI);
2269 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc);
2270 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
2271 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
2272 PseudoSourceValue::getFixedStack(NewFPIdx), 0);
2278 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
2279 /// the position of the argument.
2281 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
2282 SDValue Arg, int SPDiff, unsigned ArgOffset,
2283 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
2284 int Offset = ArgOffset + SPDiff;
2285 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
2286 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
2287 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2288 SDValue FIN = DAG.getFrameIndex(FI, VT);
2289 TailCallArgumentInfo Info;
2291 Info.FrameIdxOp = FIN;
2293 TailCallArguments.push_back(Info);
2296 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
2297 /// stack slot. Returns the chain as result and the loaded frame pointers in
2298 /// LROpOut/FPOpout. Used when tail calling.
2299 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
2307 // Load the LR and FP stack slot for later adjusting.
2308 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
2309 LROpOut = getReturnAddrFrameIndex(DAG);
2310 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, NULL, 0);
2311 Chain = SDValue(LROpOut.getNode(), 1);
2313 // When using the SVR4 ABI there is no need to load the FP stack slot
2314 // as the FP is never overwritten.
2316 FPOpOut = getFramePointerFrameIndex(DAG);
2317 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, NULL, 0);
2318 Chain = SDValue(FPOpOut.getNode(), 1);
2324 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2325 /// by "Src" to address "Dst" of size "Size". Alignment information is
2326 /// specified by the specific parameter attribute. The copy will be passed as
2327 /// a byval function parameter.
2328 /// Sometimes what we are copying is the end of a larger object, the part that
2329 /// does not fit in registers.
2331 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2332 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2334 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2335 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2336 false, NULL, 0, NULL, 0);
2339 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
2342 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
2343 SDValue Arg, SDValue PtrOff, int SPDiff,
2344 unsigned ArgOffset, bool isPPC64, bool isTailCall,
2345 bool isVector, SmallVector<SDValue, 8> &MemOpChains,
2346 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments,
2348 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2353 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
2355 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2356 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
2357 DAG.getConstant(ArgOffset, PtrVT));
2359 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0));
2360 // Calculate and remember argument location.
2361 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
2366 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
2367 DebugLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
2368 SDValue LROp, SDValue FPOp, bool isDarwinABI,
2369 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments) {
2370 MachineFunction &MF = DAG.getMachineFunction();
2372 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
2373 // might overwrite each other in case of tail call optimization.
2374 SmallVector<SDValue, 8> MemOpChains2;
2375 // Do not flag preceeding copytoreg stuff together with the following stuff.
2377 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
2379 if (!MemOpChains2.empty())
2380 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2381 &MemOpChains2[0], MemOpChains2.size());
2383 // Store the return address to the appropriate stack slot.
2384 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
2385 isPPC64, isDarwinABI, dl);
2387 // Emit callseq_end just before tailcall node.
2388 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2389 DAG.getIntPtrConstant(0, true), InFlag);
2390 InFlag = Chain.getValue(1);
2394 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
2395 SDValue &Chain, DebugLoc dl, int SPDiff, bool isTailCall,
2396 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
2397 SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys,
2399 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2400 NodeTys.push_back(MVT::Other); // Returns a chain
2401 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
2403 unsigned CallOpc = isSVR4ABI ? PPCISD::CALL_SVR4 : PPCISD::CALL_Darwin;
2405 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2406 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2407 // node so that legalize doesn't hack it.
2408 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2409 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
2410 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
2411 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType());
2412 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
2413 // If this is an absolute destination address, use the munged value.
2414 Callee = SDValue(Dest, 0);
2416 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
2417 // to do the call, we can't use PPCISD::CALL.
2418 SDValue MTCTROps[] = {Chain, Callee, InFlag};
2419 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps,
2420 2 + (InFlag.getNode() != 0));
2421 InFlag = Chain.getValue(1);
2424 NodeTys.push_back(MVT::Other);
2425 NodeTys.push_back(MVT::Flag);
2426 Ops.push_back(Chain);
2427 CallOpc = isSVR4ABI ? PPCISD::BCTRL_SVR4 : PPCISD::BCTRL_Darwin;
2429 // Add CTR register as callee so a bctr can be emitted later.
2431 Ops.push_back(DAG.getRegister(PPC::CTR, PtrVT));
2434 // If this is a direct call, pass the chain and the callee.
2435 if (Callee.getNode()) {
2436 Ops.push_back(Chain);
2437 Ops.push_back(Callee);
2439 // If this is a tail call add stack pointer delta.
2441 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
2443 // Add argument registers to the end of the list so that they are known live
2445 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2446 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2447 RegsToPass[i].second.getValueType()));
2453 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2454 unsigned CallConv, bool isVarArg,
2455 const SmallVectorImpl<ISD::InputArg> &Ins,
2456 DebugLoc dl, SelectionDAG &DAG,
2457 SmallVectorImpl<SDValue> &InVals) {
2459 SmallVector<CCValAssign, 16> RVLocs;
2460 CCState CCRetInfo(CallConv, isVarArg, getTargetMachine(),
2461 RVLocs, *DAG.getContext());
2462 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
2464 // Copy all of the result registers out of their specified physreg.
2465 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2466 CCValAssign &VA = RVLocs[i];
2467 EVT VT = VA.getValVT();
2468 assert(VA.isRegLoc() && "Can only return in registers!");
2469 Chain = DAG.getCopyFromReg(Chain, dl,
2470 VA.getLocReg(), VT, InFlag).getValue(1);
2471 InVals.push_back(Chain.getValue(0));
2472 InFlag = Chain.getValue(2);
2479 PPCTargetLowering::FinishCall(unsigned CallConv, DebugLoc dl, bool isTailCall,
2482 SmallVector<std::pair<unsigned, SDValue>, 8>
2484 SDValue InFlag, SDValue Chain,
2486 int SPDiff, unsigned NumBytes,
2487 const SmallVectorImpl<ISD::InputArg> &Ins,
2488 SmallVectorImpl<SDValue> &InVals) {
2490 std::vector<EVT> NodeTys;
2491 SmallVector<SDValue, 8> Ops;
2492 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
2493 isTailCall, RegsToPass, Ops, NodeTys,
2494 PPCSubTarget.isSVR4ABI());
2496 // When performing tail call optimization the callee pops its arguments off
2497 // the stack. Account for this here so these bytes can be pushed back on in
2498 // PPCRegisterInfo::eliminateCallFramePseudoInstr.
2499 int BytesCalleePops =
2500 (CallConv==CallingConv::Fast && PerformTailCallOpt) ? NumBytes : 0;
2502 if (InFlag.getNode())
2503 Ops.push_back(InFlag);
2507 // If this is the first return lowered for this function, add the regs
2508 // to the liveout set for the function.
2509 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
2510 SmallVector<CCValAssign, 16> RVLocs;
2511 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
2513 CCInfo.AnalyzeCallResult(Ins, RetCC_PPC);
2514 for (unsigned i = 0; i != RVLocs.size(); ++i)
2515 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
2518 assert(((Callee.getOpcode() == ISD::Register &&
2519 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
2520 Callee.getOpcode() == ISD::TargetExternalSymbol ||
2521 Callee.getOpcode() == ISD::TargetGlobalAddress ||
2522 isa<ConstantSDNode>(Callee)) &&
2523 "Expecting an global address, external symbol, absolute value or register");
2525 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size());
2528 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
2529 InFlag = Chain.getValue(1);
2531 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2532 DAG.getIntPtrConstant(BytesCalleePops, true),
2535 InFlag = Chain.getValue(1);
2537 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2538 Ins, dl, DAG, InVals);
2542 PPCTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
2543 unsigned CallConv, bool isVarArg,
2545 const SmallVectorImpl<ISD::OutputArg> &Outs,
2546 const SmallVectorImpl<ISD::InputArg> &Ins,
2547 DebugLoc dl, SelectionDAG &DAG,
2548 SmallVectorImpl<SDValue> &InVals) {
2549 if (PPCSubTarget.isSVR4ABI()) {
2550 return LowerCall_SVR4(Chain, Callee, CallConv, isVarArg,
2551 isTailCall, Outs, Ins,
2554 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
2555 isTailCall, Outs, Ins,
2561 PPCTargetLowering::LowerCall_SVR4(SDValue Chain, SDValue Callee,
2562 unsigned CallConv, bool isVarArg,
2564 const SmallVectorImpl<ISD::OutputArg> &Outs,
2565 const SmallVectorImpl<ISD::InputArg> &Ins,
2566 DebugLoc dl, SelectionDAG &DAG,
2567 SmallVectorImpl<SDValue> &InVals) {
2568 // See PPCTargetLowering::LowerFormalArguments_SVR4() for a description
2569 // of the SVR4 ABI stack frame layout.
2571 assert((!isTailCall ||
2572 (CallConv == CallingConv::Fast && PerformTailCallOpt)) &&
2573 "IsEligibleForTailCallOptimization missed a case!");
2575 assert((CallConv == CallingConv::C ||
2576 CallConv == CallingConv::Fast) && "Unknown calling convention!");
2578 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2579 unsigned PtrByteSize = 4;
2581 MachineFunction &MF = DAG.getMachineFunction();
2583 // Mark this function as potentially containing a function that contains a
2584 // tail call. As a consequence the frame pointer will be used for dynamicalloc
2585 // and restoring the callers stack pointer in this functions epilog. This is
2586 // done because by tail calling the called function might overwrite the value
2587 // in this function's (MF) stack pointer stack slot 0(SP).
2588 if (PerformTailCallOpt && CallConv==CallingConv::Fast)
2589 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
2591 // Count how many bytes are to be pushed on the stack, including the linkage
2592 // area, parameter list area and the part of the local variable space which
2593 // contains copies of aggregates which are passed by value.
2595 // Assign locations to all of the outgoing arguments.
2596 SmallVector<CCValAssign, 16> ArgLocs;
2597 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
2598 ArgLocs, *DAG.getContext());
2600 // Reserve space for the linkage area on the stack.
2601 CCInfo.AllocateStack(PPCFrameInfo::getLinkageSize(false, false), PtrByteSize);
2604 // Handle fixed and variable vector arguments differently.
2605 // Fixed vector arguments go into registers as long as registers are
2606 // available. Variable vector arguments always go into memory.
2607 unsigned NumArgs = Outs.size();
2609 for (unsigned i = 0; i != NumArgs; ++i) {
2610 EVT ArgVT = Outs[i].Val.getValueType();
2611 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2614 if (Outs[i].IsFixed) {
2615 Result = CC_PPC_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
2618 Result = CC_PPC_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
2624 cerr << "Call operand #" << i << " has unhandled type "
2625 << ArgVT.getEVTString() << "\n";
2627 llvm_unreachable(0);
2631 // All arguments are treated the same.
2632 CCInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4);
2635 // Assign locations to all of the outgoing aggregate by value arguments.
2636 SmallVector<CCValAssign, 16> ByValArgLocs;
2637 CCState CCByValInfo(CallConv, isVarArg, getTargetMachine(), ByValArgLocs,
2640 // Reserve stack space for the allocations in CCInfo.
2641 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2643 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4_ByVal);
2645 // Size of the linkage area, parameter list area and the part of the local
2646 // space variable where copies of aggregates which are passed by value are
2648 unsigned NumBytes = CCByValInfo.getNextStackOffset();
2650 // Calculate by how many bytes the stack has to be adjusted in case of tail
2651 // call optimization.
2652 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
2654 // Adjust the stack pointer for the new arguments...
2655 // These operations are automatically eliminated by the prolog/epilog pass
2656 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2657 SDValue CallSeqStart = Chain;
2659 // Load the return address and frame pointer so it can be moved somewhere else
2662 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
2665 // Set up a copy of the stack pointer for use loading and storing any
2666 // arguments that may not fit in the registers available for argument
2668 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2670 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2671 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
2672 SmallVector<SDValue, 8> MemOpChains;
2674 // Walk the register/memloc assignments, inserting copies/loads.
2675 for (unsigned i = 0, j = 0, e = ArgLocs.size();
2678 CCValAssign &VA = ArgLocs[i];
2679 SDValue Arg = Outs[i].Val;
2680 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2682 if (Flags.isByVal()) {
2683 // Argument is an aggregate which is passed by value, thus we need to
2684 // create a copy of it in the local variable space of the current stack
2685 // frame (which is the stack frame of the caller) and pass the address of
2686 // this copy to the callee.
2687 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
2688 CCValAssign &ByValVA = ByValArgLocs[j++];
2689 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
2691 // Memory reserved in the local variable space of the callers stack frame.
2692 unsigned LocMemOffset = ByValVA.getLocMemOffset();
2694 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2695 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2697 // Create a copy of the argument in the local area of the current
2699 SDValue MemcpyCall =
2700 CreateCopyOfByValArgument(Arg, PtrOff,
2701 CallSeqStart.getNode()->getOperand(0),
2704 // This must go outside the CALLSEQ_START..END.
2705 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
2706 CallSeqStart.getNode()->getOperand(1));
2707 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
2708 NewCallSeqStart.getNode());
2709 Chain = CallSeqStart = NewCallSeqStart;
2711 // Pass the address of the aggregate copy on the stack either in a
2712 // physical register or in the parameter list area of the current stack
2713 // frame to the callee.
2717 if (VA.isRegLoc()) {
2718 // Put argument in a physical register.
2719 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2721 // Put argument in the parameter list area of the current stack frame.
2722 assert(VA.isMemLoc());
2723 unsigned LocMemOffset = VA.getLocMemOffset();
2726 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2727 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2729 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
2730 PseudoSourceValue::getStack(), LocMemOffset));
2732 // Calculate and remember argument location.
2733 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
2739 if (!MemOpChains.empty())
2740 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2741 &MemOpChains[0], MemOpChains.size());
2743 // Build a sequence of copy-to-reg nodes chained together with token chain
2744 // and flag operands which copy the outgoing args into the appropriate regs.
2746 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2747 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2748 RegsToPass[i].second, InFlag);
2749 InFlag = Chain.getValue(1);
2752 // Set CR6 to true if this is a vararg call.
2754 SDValue SetCR(DAG.getTargetNode(PPC::CRSET, dl, MVT::i32), 0);
2755 Chain = DAG.getCopyToReg(Chain, dl, PPC::CR1EQ, SetCR, InFlag);
2756 InFlag = Chain.getValue(1);
2760 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
2761 false, TailCallArguments);
2764 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
2765 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
2770 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
2771 unsigned CallConv, bool isVarArg,
2773 const SmallVectorImpl<ISD::OutputArg> &Outs,
2774 const SmallVectorImpl<ISD::InputArg> &Ins,
2775 DebugLoc dl, SelectionDAG &DAG,
2776 SmallVectorImpl<SDValue> &InVals) {
2778 unsigned NumOps = Outs.size();
2780 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2781 bool isPPC64 = PtrVT == MVT::i64;
2782 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2784 MachineFunction &MF = DAG.getMachineFunction();
2786 // Mark this function as potentially containing a function that contains a
2787 // tail call. As a consequence the frame pointer will be used for dynamicalloc
2788 // and restoring the callers stack pointer in this functions epilog. This is
2789 // done because by tail calling the called function might overwrite the value
2790 // in this function's (MF) stack pointer stack slot 0(SP).
2791 if (PerformTailCallOpt && CallConv==CallingConv::Fast)
2792 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
2794 unsigned nAltivecParamsAtEnd = 0;
2796 // Count how many bytes are to be pushed on the stack, including the linkage
2797 // area, and parameter passing area. We start with 24/48 bytes, which is
2798 // prereserved space for [SP][CR][LR][3 x unused].
2800 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv,
2802 nAltivecParamsAtEnd);
2804 // Calculate by how many bytes the stack has to be adjusted in case of tail
2805 // call optimization.
2806 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
2808 // To protect arguments on the stack from being clobbered in a tail call,
2809 // force all the loads to happen before doing any other lowering.
2811 Chain = DAG.getStackArgumentTokenFactor(Chain);
2813 // Adjust the stack pointer for the new arguments...
2814 // These operations are automatically eliminated by the prolog/epilog pass
2815 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2816 SDValue CallSeqStart = Chain;
2818 // Load the return address and frame pointer so it can be move somewhere else
2821 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
2824 // Set up a copy of the stack pointer for use loading and storing any
2825 // arguments that may not fit in the registers available for argument
2829 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
2831 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2833 // Figure out which arguments are going to go in registers, and which in
2834 // memory. Also, if this is a vararg function, floating point operations
2835 // must be stored to our stack, and loaded into integer regs as well, if
2836 // any integer regs are available for argument passing.
2837 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, true);
2838 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2840 static const unsigned GPR_32[] = { // 32-bit registers.
2841 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2842 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2844 static const unsigned GPR_64[] = { // 64-bit registers.
2845 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2846 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2848 static const unsigned *FPR = GetFPR(PPCSubTarget);
2850 static const unsigned VR[] = {
2851 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2852 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2854 const unsigned NumGPRs = array_lengthof(GPR_32);
2855 const unsigned NumFPRs = 13;
2856 const unsigned NumVRs = array_lengthof(VR);
2858 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
2860 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2861 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
2863 SmallVector<SDValue, 8> MemOpChains;
2864 for (unsigned i = 0; i != NumOps; ++i) {
2866 SDValue Arg = Outs[i].Val;
2867 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2869 // PtrOff will be used to store the current argument to the stack if a
2870 // register cannot be found for it.
2873 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
2875 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
2877 // On PPC64, promote integers to 64-bit values.
2878 if (isPPC64 && Arg.getValueType() == MVT::i32) {
2879 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
2880 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
2881 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
2884 // FIXME memcpy is used way more than necessary. Correctness first.
2885 if (Flags.isByVal()) {
2886 unsigned Size = Flags.getByValSize();
2887 if (Size==1 || Size==2) {
2888 // Very small objects are passed right-justified.
2889 // Everything else is passed left-justified.
2890 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
2891 if (GPR_idx != NumGPRs) {
2892 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
2894 MemOpChains.push_back(Load.getValue(1));
2895 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
2897 ArgOffset += PtrByteSize;
2899 SDValue Const = DAG.getConstant(4 - Size, PtrOff.getValueType());
2900 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
2901 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr,
2902 CallSeqStart.getNode()->getOperand(0),
2904 // This must go outside the CALLSEQ_START..END.
2905 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
2906 CallSeqStart.getNode()->getOperand(1));
2907 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
2908 NewCallSeqStart.getNode());
2909 Chain = CallSeqStart = NewCallSeqStart;
2910 ArgOffset += PtrByteSize;
2914 // Copy entire object into memory. There are cases where gcc-generated
2915 // code assumes it is there, even if it could be put entirely into
2916 // registers. (This is not what the doc says.)
2917 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
2918 CallSeqStart.getNode()->getOperand(0),
2920 // This must go outside the CALLSEQ_START..END.
2921 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
2922 CallSeqStart.getNode()->getOperand(1));
2923 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), NewCallSeqStart.getNode());
2924 Chain = CallSeqStart = NewCallSeqStart;
2925 // And copy the pieces of it that fit into registers.
2926 for (unsigned j=0; j<Size; j+=PtrByteSize) {
2927 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
2928 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
2929 if (GPR_idx != NumGPRs) {
2930 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, NULL, 0);
2931 MemOpChains.push_back(Load.getValue(1));
2932 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
2933 ArgOffset += PtrByteSize;
2935 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
2942 switch (Arg.getValueType().getSimpleVT().SimpleTy) {
2943 default: llvm_unreachable("Unexpected ValueType for argument!");
2946 if (GPR_idx != NumGPRs) {
2947 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
2949 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
2950 isPPC64, isTailCall, false, MemOpChains,
2951 TailCallArguments, dl);
2954 ArgOffset += PtrByteSize;
2958 if (FPR_idx != NumFPRs) {
2959 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
2962 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0);
2963 MemOpChains.push_back(Store);
2965 // Float varargs are always shadowed in available integer registers
2966 if (GPR_idx != NumGPRs) {
2967 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, NULL, 0);
2968 MemOpChains.push_back(Load.getValue(1));
2969 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
2971 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
2972 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
2973 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
2974 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, NULL, 0);
2975 MemOpChains.push_back(Load.getValue(1));
2976 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
2979 // If we have any FPRs remaining, we may also have GPRs remaining.
2980 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
2982 if (GPR_idx != NumGPRs)
2984 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
2985 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
2989 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
2990 isPPC64, isTailCall, false, MemOpChains,
2991 TailCallArguments, dl);
2997 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
3004 // These go aligned on the stack, or in the corresponding R registers
3005 // when within range. The Darwin PPC ABI doc claims they also go in
3006 // V registers; in fact gcc does this only for arguments that are
3007 // prototyped, not for those that match the ... We do it for all
3008 // arguments, seems to work.
3009 while (ArgOffset % 16 !=0) {
3010 ArgOffset += PtrByteSize;
3011 if (GPR_idx != NumGPRs)
3014 // We could elide this store in the case where the object fits
3015 // entirely in R registers. Maybe later.
3016 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3017 DAG.getConstant(ArgOffset, PtrVT));
3018 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0);
3019 MemOpChains.push_back(Store);
3020 if (VR_idx != NumVRs) {
3021 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, NULL, 0);
3022 MemOpChains.push_back(Load.getValue(1));
3023 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
3026 for (unsigned i=0; i<16; i+=PtrByteSize) {
3027 if (GPR_idx == NumGPRs)
3029 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
3030 DAG.getConstant(i, PtrVT));
3031 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, NULL, 0);
3032 MemOpChains.push_back(Load.getValue(1));
3033 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3038 // Non-varargs Altivec params generally go in registers, but have
3039 // stack space allocated at the end.
3040 if (VR_idx != NumVRs) {
3041 // Doesn't have GPR space allocated.
3042 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
3043 } else if (nAltivecParamsAtEnd==0) {
3044 // We are emitting Altivec params in order.
3045 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3046 isPPC64, isTailCall, true, MemOpChains,
3047 TailCallArguments, dl);
3053 // If all Altivec parameters fit in registers, as they usually do,
3054 // they get stack space following the non-Altivec parameters. We
3055 // don't track this here because nobody below needs it.
3056 // If there are more Altivec parameters than fit in registers emit
3058 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
3060 // Offset is aligned; skip 1st 12 params which go in V registers.
3061 ArgOffset = ((ArgOffset+15)/16)*16;
3063 for (unsigned i = 0; i != NumOps; ++i) {
3064 SDValue Arg = Outs[i].Val;
3065 EVT ArgType = Arg.getValueType();
3066 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
3067 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
3070 // We are emitting Altivec params in order.
3071 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3072 isPPC64, isTailCall, true, MemOpChains,
3073 TailCallArguments, dl);
3080 if (!MemOpChains.empty())
3081 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3082 &MemOpChains[0], MemOpChains.size());
3084 // Build a sequence of copy-to-reg nodes chained together with token chain
3085 // and flag operands which copy the outgoing args into the appropriate regs.
3087 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3088 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3089 RegsToPass[i].second, InFlag);
3090 InFlag = Chain.getValue(1);
3094 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
3095 FPOp, true, TailCallArguments);
3098 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3099 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3104 PPCTargetLowering::LowerReturn(SDValue Chain,
3105 unsigned CallConv, bool isVarArg,
3106 const SmallVectorImpl<ISD::OutputArg> &Outs,
3107 DebugLoc dl, SelectionDAG &DAG) {
3109 SmallVector<CCValAssign, 16> RVLocs;
3110 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
3111 RVLocs, *DAG.getContext());
3112 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
3114 // If this is the first return lowered for this function, add the regs to the
3115 // liveout set for the function.
3116 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
3117 for (unsigned i = 0; i != RVLocs.size(); ++i)
3118 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
3123 // Copy the result values into the output registers.
3124 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3125 CCValAssign &VA = RVLocs[i];
3126 assert(VA.isRegLoc() && "Can only return in registers!");
3127 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3129 Flag = Chain.getValue(1);
3133 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
3135 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain);
3138 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
3139 const PPCSubtarget &Subtarget) {
3140 // When we pop the dynamic allocation we need to restore the SP link.
3141 DebugLoc dl = Op.getDebugLoc();
3143 // Get the corect type for pointers.
3144 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3146 // Construct the stack pointer operand.
3147 bool IsPPC64 = Subtarget.isPPC64();
3148 unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1;
3149 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
3151 // Get the operands for the STACKRESTORE.
3152 SDValue Chain = Op.getOperand(0);
3153 SDValue SaveSP = Op.getOperand(1);
3155 // Load the old link SP.
3156 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr, NULL, 0);
3158 // Restore the stack pointer.
3159 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
3161 // Store the old link SP.
3162 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, NULL, 0);
3168 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
3169 MachineFunction &MF = DAG.getMachineFunction();
3170 bool IsPPC64 = PPCSubTarget.isPPC64();
3171 bool isDarwinABI = PPCSubTarget.isDarwinABI();
3172 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3174 // Get current frame pointer save index. The users of this index will be
3175 // primarily DYNALLOC instructions.
3176 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
3177 int RASI = FI->getReturnAddrSaveIndex();
3179 // If the frame pointer save index hasn't been defined yet.
3181 // Find out what the fix offset of the frame pointer save area.
3182 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, isDarwinABI);
3183 // Allocate the frame index for frame pointer save area.
3184 RASI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, LROffset);
3186 FI->setReturnAddrSaveIndex(RASI);
3188 return DAG.getFrameIndex(RASI, PtrVT);
3192 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
3193 MachineFunction &MF = DAG.getMachineFunction();
3194 bool IsPPC64 = PPCSubTarget.isPPC64();
3195 bool isDarwinABI = PPCSubTarget.isDarwinABI();
3196 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3198 // Get current frame pointer save index. The users of this index will be
3199 // primarily DYNALLOC instructions.
3200 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
3201 int FPSI = FI->getFramePointerSaveIndex();
3203 // If the frame pointer save index hasn't been defined yet.
3205 // Find out what the fix offset of the frame pointer save area.
3206 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64,
3209 // Allocate the frame index for frame pointer save area.
3210 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
3212 FI->setFramePointerSaveIndex(FPSI);
3214 return DAG.getFrameIndex(FPSI, PtrVT);
3217 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
3219 const PPCSubtarget &Subtarget) {
3221 SDValue Chain = Op.getOperand(0);
3222 SDValue Size = Op.getOperand(1);
3223 DebugLoc dl = Op.getDebugLoc();
3225 // Get the corect type for pointers.
3226 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3228 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
3229 DAG.getConstant(0, PtrVT), Size);
3230 // Construct a node for the frame pointer save index.
3231 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
3232 // Build a DYNALLOC node.
3233 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
3234 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
3235 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3);
3238 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
3240 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
3241 // Not FP? Not a fsel.
3242 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
3243 !Op.getOperand(2).getValueType().isFloatingPoint())
3246 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3248 // Cannot handle SETEQ/SETNE.
3249 if (CC == ISD::SETEQ || CC == ISD::SETNE) return Op;
3251 EVT ResVT = Op.getValueType();
3252 EVT CmpVT = Op.getOperand(0).getValueType();
3253 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3254 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
3255 DebugLoc dl = Op.getDebugLoc();
3257 // If the RHS of the comparison is a 0.0, we don't need to do the
3258 // subtraction at all.
3259 if (isFloatingPointZero(RHS))
3261 default: break; // SETUO etc aren't handled by fsel.
3264 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
3267 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
3268 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
3269 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
3272 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
3275 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
3276 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
3277 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
3278 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
3283 default: break; // SETUO etc aren't handled by fsel.
3286 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
3287 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3288 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3289 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
3292 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
3293 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3294 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3295 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
3298 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
3299 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3300 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3301 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
3304 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
3305 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3306 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3307 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
3312 // FIXME: Split this code up when LegalizeDAGTypes lands.
3313 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
3315 assert(Op.getOperand(0).getValueType().isFloatingPoint());
3316 SDValue Src = Op.getOperand(0);
3317 if (Src.getValueType() == MVT::f32)
3318 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
3321 switch (Op.getValueType().getSimpleVT().SimpleTy) {
3322 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
3324 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
3329 Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src);
3333 // Convert the FP value to an int value through memory.
3334 SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64);
3336 // Emit a store to the stack slot.
3337 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr, NULL, 0);
3339 // Result is a load from the stack slot. If loading 4 bytes, make sure to
3341 if (Op.getValueType() == MVT::i32)
3342 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
3343 DAG.getConstant(4, FIPtr.getValueType()));
3344 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, NULL, 0);
3347 SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
3348 DebugLoc dl = Op.getDebugLoc();
3349 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
3350 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
3353 if (Op.getOperand(0).getValueType() == MVT::i64) {
3354 SDValue Bits = DAG.getNode(ISD::BIT_CONVERT, dl,
3355 MVT::f64, Op.getOperand(0));
3356 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits);
3357 if (Op.getValueType() == MVT::f32)
3358 FP = DAG.getNode(ISD::FP_ROUND, dl,
3359 MVT::f32, FP, DAG.getIntPtrConstant(0));
3363 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
3364 "Unhandled SINT_TO_FP type in custom expander!");
3365 // Since we only generate this in 64-bit mode, we can take advantage of
3366 // 64-bit registers. In particular, sign extend the input value into the
3367 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
3368 // then lfd it and fcfid it.
3369 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
3370 int FrameIdx = FrameInfo->CreateStackObject(8, 8);
3371 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3372 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
3374 SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, MVT::i32,
3377 // STD the extended value into the stack slot.
3378 MachineMemOperand MO(PseudoSourceValue::getFixedStack(FrameIdx),
3379 MachineMemOperand::MOStore, 0, 8, 8);
3380 SDValue Store = DAG.getNode(PPCISD::STD_32, dl, MVT::Other,
3381 DAG.getEntryNode(), Ext64, FIdx,
3382 DAG.getMemOperand(MO));
3383 // Load the value as a double.
3384 SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, NULL, 0);
3386 // FCFID it and return it.
3387 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld);
3388 if (Op.getValueType() == MVT::f32)
3389 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
3393 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
3394 DebugLoc dl = Op.getDebugLoc();
3396 The rounding mode is in bits 30:31 of FPSR, and has the following
3403 FLT_ROUNDS, on the other hand, expects the following:
3410 To perform the conversion, we do:
3411 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
3414 MachineFunction &MF = DAG.getMachineFunction();
3415 EVT VT = Op.getValueType();
3416 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3417 std::vector<EVT> NodeTys;
3418 SDValue MFFSreg, InFlag;
3420 // Save FP Control Word to register
3421 NodeTys.push_back(MVT::f64); // return register
3422 NodeTys.push_back(MVT::Flag); // unused in this context
3423 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
3425 // Save FP register to stack slot
3426 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
3427 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
3428 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
3429 StackSlot, NULL, 0);
3431 // Load FP Control Word from low 32 bits of stack slot.
3432 SDValue Four = DAG.getConstant(4, PtrVT);
3433 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
3434 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, NULL, 0);
3436 // Transform as necessary
3438 DAG.getNode(ISD::AND, dl, MVT::i32,
3439 CWD, DAG.getConstant(3, MVT::i32));
3441 DAG.getNode(ISD::SRL, dl, MVT::i32,
3442 DAG.getNode(ISD::AND, dl, MVT::i32,
3443 DAG.getNode(ISD::XOR, dl, MVT::i32,
3444 CWD, DAG.getConstant(3, MVT::i32)),
3445 DAG.getConstant(3, MVT::i32)),
3446 DAG.getConstant(1, MVT::i32));
3449 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
3451 return DAG.getNode((VT.getSizeInBits() < 16 ?
3452 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
3455 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) {
3456 EVT VT = Op.getValueType();
3457 unsigned BitWidth = VT.getSizeInBits();
3458 DebugLoc dl = Op.getDebugLoc();
3459 assert(Op.getNumOperands() == 3 &&
3460 VT == Op.getOperand(1).getValueType() &&
3463 // Expand into a bunch of logical ops. Note that these ops
3464 // depend on the PPC behavior for oversized shift amounts.
3465 SDValue Lo = Op.getOperand(0);
3466 SDValue Hi = Op.getOperand(1);
3467 SDValue Amt = Op.getOperand(2);
3468 EVT AmtVT = Amt.getValueType();
3470 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3471 DAG.getConstant(BitWidth, AmtVT), Amt);
3472 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
3473 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
3474 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
3475 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3476 DAG.getConstant(-BitWidth, AmtVT));
3477 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
3478 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
3479 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
3480 SDValue OutOps[] = { OutLo, OutHi };
3481 return DAG.getMergeValues(OutOps, 2, dl);
3484 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) {
3485 EVT VT = Op.getValueType();
3486 DebugLoc dl = Op.getDebugLoc();
3487 unsigned BitWidth = VT.getSizeInBits();
3488 assert(Op.getNumOperands() == 3 &&
3489 VT == Op.getOperand(1).getValueType() &&
3492 // Expand into a bunch of logical ops. Note that these ops
3493 // depend on the PPC behavior for oversized shift amounts.
3494 SDValue Lo = Op.getOperand(0);
3495 SDValue Hi = Op.getOperand(1);
3496 SDValue Amt = Op.getOperand(2);
3497 EVT AmtVT = Amt.getValueType();
3499 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3500 DAG.getConstant(BitWidth, AmtVT), Amt);
3501 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
3502 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
3503 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
3504 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3505 DAG.getConstant(-BitWidth, AmtVT));
3506 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
3507 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
3508 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
3509 SDValue OutOps[] = { OutLo, OutHi };
3510 return DAG.getMergeValues(OutOps, 2, dl);
3513 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) {
3514 DebugLoc dl = Op.getDebugLoc();
3515 EVT VT = Op.getValueType();
3516 unsigned BitWidth = VT.getSizeInBits();
3517 assert(Op.getNumOperands() == 3 &&
3518 VT == Op.getOperand(1).getValueType() &&
3521 // Expand into a bunch of logical ops, followed by a select_cc.
3522 SDValue Lo = Op.getOperand(0);
3523 SDValue Hi = Op.getOperand(1);
3524 SDValue Amt = Op.getOperand(2);
3525 EVT AmtVT = Amt.getValueType();
3527 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3528 DAG.getConstant(BitWidth, AmtVT), Amt);
3529 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
3530 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
3531 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
3532 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3533 DAG.getConstant(-BitWidth, AmtVT));
3534 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
3535 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
3536 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
3537 Tmp4, Tmp6, ISD::SETLE);
3538 SDValue OutOps[] = { OutLo, OutHi };
3539 return DAG.getMergeValues(OutOps, 2, dl);
3542 //===----------------------------------------------------------------------===//
3543 // Vector related lowering.
3546 /// BuildSplatI - Build a canonical splati of Val with an element size of
3547 /// SplatSize. Cast the result to VT.
3548 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
3549 SelectionDAG &DAG, DebugLoc dl) {
3550 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
3552 static const EVT VTys[] = { // canonical VT to use for each size.
3553 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
3556 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
3558 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
3562 EVT CanonicalVT = VTys[SplatSize-1];
3564 // Build a canonical splat for this value.
3565 SDValue Elt = DAG.getConstant(Val, MVT::i32);
3566 SmallVector<SDValue, 8> Ops;
3567 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
3568 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
3569 &Ops[0], Ops.size());
3570 return DAG.getNode(ISD::BIT_CONVERT, dl, ReqVT, Res);
3573 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
3574 /// specified intrinsic ID.
3575 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
3576 SelectionDAG &DAG, DebugLoc dl,
3577 EVT DestVT = MVT::Other) {
3578 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
3579 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
3580 DAG.getConstant(IID, MVT::i32), LHS, RHS);
3583 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
3584 /// specified intrinsic ID.
3585 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
3586 SDValue Op2, SelectionDAG &DAG,
3587 DebugLoc dl, EVT DestVT = MVT::Other) {
3588 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
3589 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
3590 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
3594 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
3595 /// amount. The result has the specified value type.
3596 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
3597 EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3598 // Force LHS/RHS to be the right type.
3599 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, LHS);
3600 RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, RHS);
3603 for (unsigned i = 0; i != 16; ++i)
3605 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
3606 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T);
3609 // If this is a case we can't handle, return null and let the default
3610 // expansion code take care of it. If we CAN select this case, and if it
3611 // selects to a single instruction, return Op. Otherwise, if we can codegen
3612 // this case more efficiently than a constant pool load, lower it to the
3613 // sequence of ops that should be used.
3614 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3615 DebugLoc dl = Op.getDebugLoc();
3616 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
3617 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
3619 // Check if this is a splat of a constant value.
3620 APInt APSplatBits, APSplatUndef;
3621 unsigned SplatBitSize;
3623 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
3624 HasAnyUndefs) || SplatBitSize > 32)
3627 unsigned SplatBits = APSplatBits.getZExtValue();
3628 unsigned SplatUndef = APSplatUndef.getZExtValue();
3629 unsigned SplatSize = SplatBitSize / 8;
3631 // First, handle single instruction cases.
3634 if (SplatBits == 0) {
3635 // Canonicalize all zero vectors to be v4i32.
3636 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
3637 SDValue Z = DAG.getConstant(0, MVT::i32);
3638 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
3639 Op = DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Z);
3644 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
3645 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
3647 if (SextVal >= -16 && SextVal <= 15)
3648 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
3651 // Two instruction sequences.
3653 // If this value is in the range [-32,30] and is even, use:
3654 // tmp = VSPLTI[bhw], result = add tmp, tmp
3655 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
3656 SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG, dl);
3657 Res = DAG.getNode(ISD::ADD, dl, Res.getValueType(), Res, Res);
3658 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3661 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
3662 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
3664 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
3665 // Make -1 and vspltisw -1:
3666 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
3668 // Make the VSLW intrinsic, computing 0x8000_0000.
3669 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
3672 // xor by OnesV to invert it.
3673 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
3674 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3677 // Check to see if this is a wide variety of vsplti*, binop self cases.
3678 static const signed char SplatCsts[] = {
3679 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
3680 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
3683 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
3684 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
3685 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
3686 int i = SplatCsts[idx];
3688 // Figure out what shift amount will be used by altivec if shifted by i in
3690 unsigned TypeShiftAmt = i & (SplatBitSize-1);
3692 // vsplti + shl self.
3693 if (SextVal == (i << (int)TypeShiftAmt)) {
3694 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3695 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3696 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
3697 Intrinsic::ppc_altivec_vslw
3699 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3700 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3703 // vsplti + srl self.
3704 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
3705 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3706 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3707 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
3708 Intrinsic::ppc_altivec_vsrw
3710 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3711 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3714 // vsplti + sra self.
3715 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
3716 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3717 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3718 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
3719 Intrinsic::ppc_altivec_vsraw
3721 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3722 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3725 // vsplti + rol self.
3726 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
3727 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
3728 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3729 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3730 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
3731 Intrinsic::ppc_altivec_vrlw
3733 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3734 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3737 // t = vsplti c, result = vsldoi t, t, 1
3738 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
3739 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3740 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
3742 // t = vsplti c, result = vsldoi t, t, 2
3743 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
3744 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3745 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
3747 // t = vsplti c, result = vsldoi t, t, 3
3748 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
3749 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3750 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
3754 // Three instruction sequences.
3756 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
3757 if (SextVal >= 0 && SextVal <= 31) {
3758 SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG, dl);
3759 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
3760 LHS = DAG.getNode(ISD::SUB, dl, LHS.getValueType(), LHS, RHS);
3761 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS);
3763 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
3764 if (SextVal >= -31 && SextVal <= 0) {
3765 SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG, dl);
3766 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
3767 LHS = DAG.getNode(ISD::ADD, dl, LHS.getValueType(), LHS, RHS);
3768 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS);
3774 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
3775 /// the specified operations to build the shuffle.
3776 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
3777 SDValue RHS, SelectionDAG &DAG,
3779 unsigned OpNum = (PFEntry >> 26) & 0x0F;
3780 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
3781 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
3784 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
3796 if (OpNum == OP_COPY) {
3797 if (LHSID == (1*9+2)*9+3) return LHS;
3798 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
3802 SDValue OpLHS, OpRHS;
3803 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
3804 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
3808 default: llvm_unreachable("Unknown i32 permute!");
3810 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
3811 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
3812 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
3813 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
3816 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
3817 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
3818 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
3819 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
3822 for (unsigned i = 0; i != 16; ++i)
3823 ShufIdxs[i] = (i&3)+0;
3826 for (unsigned i = 0; i != 16; ++i)
3827 ShufIdxs[i] = (i&3)+4;
3830 for (unsigned i = 0; i != 16; ++i)
3831 ShufIdxs[i] = (i&3)+8;
3834 for (unsigned i = 0; i != 16; ++i)
3835 ShufIdxs[i] = (i&3)+12;
3838 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
3840 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
3842 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
3844 EVT VT = OpLHS.getValueType();
3845 OpLHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OpLHS);
3846 OpRHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OpRHS);
3847 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
3848 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T);
3851 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
3852 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
3853 /// return the code it can be lowered into. Worst case, it can always be
3854 /// lowered into a vperm.
3855 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
3856 SelectionDAG &DAG) {
3857 DebugLoc dl = Op.getDebugLoc();
3858 SDValue V1 = Op.getOperand(0);
3859 SDValue V2 = Op.getOperand(1);
3860 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
3861 EVT VT = Op.getValueType();
3863 // Cases that are handled by instructions that take permute immediates
3864 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
3865 // selected by the instruction selector.
3866 if (V2.getOpcode() == ISD::UNDEF) {
3867 if (PPC::isSplatShuffleMask(SVOp, 1) ||
3868 PPC::isSplatShuffleMask(SVOp, 2) ||
3869 PPC::isSplatShuffleMask(SVOp, 4) ||
3870 PPC::isVPKUWUMShuffleMask(SVOp, true) ||
3871 PPC::isVPKUHUMShuffleMask(SVOp, true) ||
3872 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 ||
3873 PPC::isVMRGLShuffleMask(SVOp, 1, true) ||
3874 PPC::isVMRGLShuffleMask(SVOp, 2, true) ||
3875 PPC::isVMRGLShuffleMask(SVOp, 4, true) ||
3876 PPC::isVMRGHShuffleMask(SVOp, 1, true) ||
3877 PPC::isVMRGHShuffleMask(SVOp, 2, true) ||
3878 PPC::isVMRGHShuffleMask(SVOp, 4, true)) {
3883 // Altivec has a variety of "shuffle immediates" that take two vector inputs
3884 // and produce a fixed permutation. If any of these match, do not lower to
3886 if (PPC::isVPKUWUMShuffleMask(SVOp, false) ||
3887 PPC::isVPKUHUMShuffleMask(SVOp, false) ||
3888 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 ||
3889 PPC::isVMRGLShuffleMask(SVOp, 1, false) ||
3890 PPC::isVMRGLShuffleMask(SVOp, 2, false) ||
3891 PPC::isVMRGLShuffleMask(SVOp, 4, false) ||
3892 PPC::isVMRGHShuffleMask(SVOp, 1, false) ||
3893 PPC::isVMRGHShuffleMask(SVOp, 2, false) ||
3894 PPC::isVMRGHShuffleMask(SVOp, 4, false))
3897 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
3898 // perfect shuffle table to emit an optimal matching sequence.
3899 SmallVector<int, 16> PermMask;
3900 SVOp->getMask(PermMask);
3902 unsigned PFIndexes[4];
3903 bool isFourElementShuffle = true;
3904 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
3905 unsigned EltNo = 8; // Start out undef.
3906 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
3907 if (PermMask[i*4+j] < 0)
3908 continue; // Undef, ignore it.
3910 unsigned ByteSource = PermMask[i*4+j];
3911 if ((ByteSource & 3) != j) {
3912 isFourElementShuffle = false;
3917 EltNo = ByteSource/4;
3918 } else if (EltNo != ByteSource/4) {
3919 isFourElementShuffle = false;
3923 PFIndexes[i] = EltNo;
3926 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
3927 // perfect shuffle vector to determine if it is cost effective to do this as
3928 // discrete instructions, or whether we should use a vperm.
3929 if (isFourElementShuffle) {
3930 // Compute the index in the perfect shuffle table.
3931 unsigned PFTableIndex =
3932 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3934 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3935 unsigned Cost = (PFEntry >> 30);
3937 // Determining when to avoid vperm is tricky. Many things affect the cost
3938 // of vperm, particularly how many times the perm mask needs to be computed.
3939 // For example, if the perm mask can be hoisted out of a loop or is already
3940 // used (perhaps because there are multiple permutes with the same shuffle
3941 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
3942 // the loop requires an extra register.
3944 // As a compromise, we only emit discrete instructions if the shuffle can be
3945 // generated in 3 or fewer operations. When we have loop information
3946 // available, if this block is within a loop, we should avoid using vperm
3947 // for 3-operation perms and use a constant pool load instead.
3949 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
3952 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
3953 // vector that will get spilled to the constant pool.
3954 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
3956 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
3957 // that it is in input element units, not in bytes. Convert now.
3958 EVT EltVT = V1.getValueType().getVectorElementType();
3959 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
3961 SmallVector<SDValue, 16> ResultMask;
3962 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
3963 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
3965 for (unsigned j = 0; j != BytesPerElement; ++j)
3966 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
3970 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
3971 &ResultMask[0], ResultMask.size());
3972 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
3975 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
3976 /// altivec comparison. If it is, return true and fill in Opc/isDot with
3977 /// information about the intrinsic.
3978 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
3980 unsigned IntrinsicID =
3981 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
3984 switch (IntrinsicID) {
3985 default: return false;
3986 // Comparison predicates.
3987 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
3988 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
3989 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
3990 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
3991 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
3992 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
3993 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
3994 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
3995 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
3996 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
3997 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
3998 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
3999 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
4001 // Normal Comparisons.
4002 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
4003 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
4004 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
4005 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
4006 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
4007 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
4008 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
4009 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
4010 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
4011 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
4012 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
4013 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
4014 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
4019 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
4020 /// lower, do it, otherwise return null.
4021 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
4022 SelectionDAG &DAG) {
4023 // If this is a lowered altivec predicate compare, CompareOpc is set to the
4024 // opcode number of the comparison.
4025 DebugLoc dl = Op.getDebugLoc();
4028 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
4029 return SDValue(); // Don't custom lower most intrinsics.
4031 // If this is a non-dot comparison, make the VCMP node and we are done.
4033 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
4034 Op.getOperand(1), Op.getOperand(2),
4035 DAG.getConstant(CompareOpc, MVT::i32));
4036 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Tmp);
4039 // Create the PPCISD altivec 'dot' comparison node.
4041 Op.getOperand(2), // LHS
4042 Op.getOperand(3), // RHS
4043 DAG.getConstant(CompareOpc, MVT::i32)
4045 std::vector<EVT> VTs;
4046 VTs.push_back(Op.getOperand(2).getValueType());
4047 VTs.push_back(MVT::Flag);
4048 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
4050 // Now that we have the comparison, emit a copy from the CR to a GPR.
4051 // This is flagged to the above dot comparison.
4052 SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32,
4053 DAG.getRegister(PPC::CR6, MVT::i32),
4054 CompNode.getValue(1));
4056 // Unpack the result based on how the target uses it.
4057 unsigned BitNo; // Bit # of CR6.
4058 bool InvertBit; // Invert result?
4059 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
4060 default: // Can't happen, don't crash on invalid number though.
4061 case 0: // Return the value of the EQ bit of CR6.
4062 BitNo = 0; InvertBit = false;
4064 case 1: // Return the inverted value of the EQ bit of CR6.
4065 BitNo = 0; InvertBit = true;
4067 case 2: // Return the value of the LT bit of CR6.
4068 BitNo = 2; InvertBit = false;
4070 case 3: // Return the inverted value of the LT bit of CR6.
4071 BitNo = 2; InvertBit = true;
4075 // Shift the bit into the low position.
4076 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
4077 DAG.getConstant(8-(3-BitNo), MVT::i32));
4079 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
4080 DAG.getConstant(1, MVT::i32));
4082 // If we are supposed to, toggle the bit.
4084 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
4085 DAG.getConstant(1, MVT::i32));
4089 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
4090 SelectionDAG &DAG) {
4091 DebugLoc dl = Op.getDebugLoc();
4092 // Create a stack slot that is 16-byte aligned.
4093 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
4094 int FrameIdx = FrameInfo->CreateStackObject(16, 16);
4095 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4096 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4098 // Store the input value into Value#0 of the stack slot.
4099 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
4100 Op.getOperand(0), FIdx, NULL, 0);
4102 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, NULL, 0);
4105 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) {
4106 DebugLoc dl = Op.getDebugLoc();
4107 if (Op.getValueType() == MVT::v4i32) {
4108 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4110 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
4111 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
4113 SDValue RHSSwap = // = vrlw RHS, 16
4114 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
4116 // Shrinkify inputs to v8i16.
4117 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, LHS);
4118 RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHS);
4119 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHSSwap);
4121 // Low parts multiplied together, generating 32-bit results (we ignore the
4123 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
4124 LHS, RHS, DAG, dl, MVT::v4i32);
4126 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
4127 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
4128 // Shift the high parts up 16 bits.
4129 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
4131 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
4132 } else if (Op.getValueType() == MVT::v8i16) {
4133 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4135 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
4137 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
4138 LHS, RHS, Zero, DAG, dl);
4139 } else if (Op.getValueType() == MVT::v16i8) {
4140 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4142 // Multiply the even 8-bit parts, producing 16-bit sums.
4143 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
4144 LHS, RHS, DAG, dl, MVT::v8i16);
4145 EvenParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, EvenParts);
4147 // Multiply the odd 8-bit parts, producing 16-bit sums.
4148 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
4149 LHS, RHS, DAG, dl, MVT::v8i16);
4150 OddParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OddParts);
4152 // Merge the results together.
4154 for (unsigned i = 0; i != 8; ++i) {
4156 Ops[i*2+1] = 2*i+1+16;
4158 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
4160 llvm_unreachable("Unknown mul to lower!");
4164 /// LowerOperation - Provide custom lowering hooks for some operations.
4166 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
4167 switch (Op.getOpcode()) {
4168 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
4169 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
4170 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
4171 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
4172 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
4173 case ISD::SETCC: return LowerSETCC(Op, DAG);
4174 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
4176 return LowerVASTART(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
4177 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
4180 return LowerVAARG(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
4181 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
4183 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
4184 case ISD::DYNAMIC_STACKALLOC:
4185 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
4187 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
4188 case ISD::FP_TO_UINT:
4189 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
4191 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
4192 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
4194 // Lower 64-bit shifts.
4195 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
4196 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
4197 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
4199 // Vector-related lowering.
4200 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
4201 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
4202 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
4203 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
4204 case ISD::MUL: return LowerMUL(Op, DAG);
4206 // Frame & Return address.
4207 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4208 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
4213 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
4214 SmallVectorImpl<SDValue>&Results,
4215 SelectionDAG &DAG) {
4216 DebugLoc dl = N->getDebugLoc();
4217 switch (N->getOpcode()) {
4219 assert(false && "Do not know how to custom type legalize this operation!");
4221 case ISD::FP_ROUND_INREG: {
4222 assert(N->getValueType(0) == MVT::ppcf128);
4223 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
4224 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
4225 MVT::f64, N->getOperand(0),
4226 DAG.getIntPtrConstant(0));
4227 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
4228 MVT::f64, N->getOperand(0),
4229 DAG.getIntPtrConstant(1));
4231 // This sequence changes FPSCR to do round-to-zero, adds the two halves
4232 // of the long double, and puts FPSCR back the way it was. We do not
4233 // actually model FPSCR.
4234 std::vector<EVT> NodeTys;
4235 SDValue Ops[4], Result, MFFSreg, InFlag, FPreg;
4237 NodeTys.push_back(MVT::f64); // Return register
4238 NodeTys.push_back(MVT::Flag); // Returns a flag for later insns
4239 Result = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
4240 MFFSreg = Result.getValue(0);
4241 InFlag = Result.getValue(1);
4244 NodeTys.push_back(MVT::Flag); // Returns a flag
4245 Ops[0] = DAG.getConstant(31, MVT::i32);
4247 Result = DAG.getNode(PPCISD::MTFSB1, dl, NodeTys, Ops, 2);
4248 InFlag = Result.getValue(0);
4251 NodeTys.push_back(MVT::Flag); // Returns a flag
4252 Ops[0] = DAG.getConstant(30, MVT::i32);
4254 Result = DAG.getNode(PPCISD::MTFSB0, dl, NodeTys, Ops, 2);
4255 InFlag = Result.getValue(0);
4258 NodeTys.push_back(MVT::f64); // result of add
4259 NodeTys.push_back(MVT::Flag); // Returns a flag
4263 Result = DAG.getNode(PPCISD::FADDRTZ, dl, NodeTys, Ops, 3);
4264 FPreg = Result.getValue(0);
4265 InFlag = Result.getValue(1);
4268 NodeTys.push_back(MVT::f64);
4269 Ops[0] = DAG.getConstant(1, MVT::i32);
4273 Result = DAG.getNode(PPCISD::MTFSF, dl, NodeTys, Ops, 4);
4274 FPreg = Result.getValue(0);
4276 // We know the low half is about to be thrown away, so just use something
4278 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
4282 case ISD::FP_TO_SINT:
4283 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
4289 //===----------------------------------------------------------------------===//
4290 // Other Lowering Code
4291 //===----------------------------------------------------------------------===//
4294 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
4295 bool is64bit, unsigned BinOpcode) const {
4296 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4297 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4299 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4300 MachineFunction *F = BB->getParent();
4301 MachineFunction::iterator It = BB;
4304 unsigned dest = MI->getOperand(0).getReg();
4305 unsigned ptrA = MI->getOperand(1).getReg();
4306 unsigned ptrB = MI->getOperand(2).getReg();
4307 unsigned incr = MI->getOperand(3).getReg();
4308 DebugLoc dl = MI->getDebugLoc();
4310 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
4311 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4312 F->insert(It, loopMBB);
4313 F->insert(It, exitMBB);
4314 exitMBB->transferSuccessors(BB);
4316 MachineRegisterInfo &RegInfo = F->getRegInfo();
4317 unsigned TmpReg = (!BinOpcode) ? incr :
4318 RegInfo.createVirtualRegister(
4319 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4320 (const TargetRegisterClass *) &PPC::GPRCRegClass);
4324 // fallthrough --> loopMBB
4325 BB->addSuccessor(loopMBB);
4328 // l[wd]arx dest, ptr
4329 // add r0, dest, incr
4330 // st[wd]cx. r0, ptr
4332 // fallthrough --> exitMBB
4334 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
4335 .addReg(ptrA).addReg(ptrB);
4337 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
4338 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4339 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
4340 BuildMI(BB, dl, TII->get(PPC::BCC))
4341 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
4342 BB->addSuccessor(loopMBB);
4343 BB->addSuccessor(exitMBB);
4352 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
4353 MachineBasicBlock *BB,
4354 bool is8bit, // operation
4355 unsigned BinOpcode) const {
4356 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4357 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4358 // In 64 bit mode we have to use 64 bits for addresses, even though the
4359 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
4360 // registers without caring whether they're 32 or 64, but here we're
4361 // doing actual arithmetic on the addresses.
4362 bool is64bit = PPCSubTarget.isPPC64();
4364 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4365 MachineFunction *F = BB->getParent();
4366 MachineFunction::iterator It = BB;
4369 unsigned dest = MI->getOperand(0).getReg();
4370 unsigned ptrA = MI->getOperand(1).getReg();
4371 unsigned ptrB = MI->getOperand(2).getReg();
4372 unsigned incr = MI->getOperand(3).getReg();
4373 DebugLoc dl = MI->getDebugLoc();
4375 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
4376 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4377 F->insert(It, loopMBB);
4378 F->insert(It, exitMBB);
4379 exitMBB->transferSuccessors(BB);
4381 MachineRegisterInfo &RegInfo = F->getRegInfo();
4382 const TargetRegisterClass *RC =
4383 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4384 (const TargetRegisterClass *) &PPC::GPRCRegClass;
4385 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
4386 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
4387 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
4388 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
4389 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
4390 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
4391 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
4392 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
4393 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
4394 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
4395 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
4397 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
4401 // fallthrough --> loopMBB
4402 BB->addSuccessor(loopMBB);
4404 // The 4-byte load must be aligned, while a char or short may be
4405 // anywhere in the word. Hence all this nasty bookkeeping code.
4406 // add ptr1, ptrA, ptrB [copy if ptrA==0]
4407 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
4408 // xori shift, shift1, 24 [16]
4409 // rlwinm ptr, ptr1, 0, 0, 29
4410 // slw incr2, incr, shift
4411 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
4412 // slw mask, mask2, shift
4414 // lwarx tmpDest, ptr
4415 // add tmp, tmpDest, incr2
4416 // andc tmp2, tmpDest, mask
4417 // and tmp3, tmp, mask
4418 // or tmp4, tmp3, tmp2
4421 // fallthrough --> exitMBB
4422 // srw dest, tmpDest, shift
4424 if (ptrA!=PPC::R0) {
4425 Ptr1Reg = RegInfo.createVirtualRegister(RC);
4426 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
4427 .addReg(ptrA).addReg(ptrB);
4431 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
4432 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
4433 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
4434 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
4436 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
4437 .addReg(Ptr1Reg).addImm(0).addImm(61);
4439 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
4440 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
4441 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
4442 .addReg(incr).addReg(ShiftReg);
4444 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
4446 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
4447 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
4449 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
4450 .addReg(Mask2Reg).addReg(ShiftReg);
4453 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
4454 .addReg(PPC::R0).addReg(PtrReg);
4456 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
4457 .addReg(Incr2Reg).addReg(TmpDestReg);
4458 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
4459 .addReg(TmpDestReg).addReg(MaskReg);
4460 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
4461 .addReg(TmpReg).addReg(MaskReg);
4462 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
4463 .addReg(Tmp3Reg).addReg(Tmp2Reg);
4464 BuildMI(BB, dl, TII->get(PPC::STWCX))
4465 .addReg(Tmp4Reg).addReg(PPC::R0).addReg(PtrReg);
4466 BuildMI(BB, dl, TII->get(PPC::BCC))
4467 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
4468 BB->addSuccessor(loopMBB);
4469 BB->addSuccessor(exitMBB);
4474 BuildMI(BB, dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg).addReg(ShiftReg);
4479 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4480 MachineBasicBlock *BB) const {
4481 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4483 // To "insert" these instructions we actually have to insert their
4484 // control-flow patterns.
4485 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4486 MachineFunction::iterator It = BB;
4489 MachineFunction *F = BB->getParent();
4491 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
4492 MI->getOpcode() == PPC::SELECT_CC_I8 ||
4493 MI->getOpcode() == PPC::SELECT_CC_F4 ||
4494 MI->getOpcode() == PPC::SELECT_CC_F8 ||
4495 MI->getOpcode() == PPC::SELECT_CC_VRRC) {
4497 // The incoming instruction knows the destination vreg to set, the
4498 // condition code register to branch on, the true/false values to
4499 // select between, and a branch opcode to use.
4504 // cmpTY ccX, r1, r2
4506 // fallthrough --> copy0MBB
4507 MachineBasicBlock *thisMBB = BB;
4508 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4509 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4510 unsigned SelectPred = MI->getOperand(4).getImm();
4511 DebugLoc dl = MI->getDebugLoc();
4512 BuildMI(BB, dl, TII->get(PPC::BCC))
4513 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
4514 F->insert(It, copy0MBB);
4515 F->insert(It, sinkMBB);
4516 // Update machine-CFG edges by transferring all successors of the current
4517 // block to the new block which will contain the Phi node for the select.
4518 sinkMBB->transferSuccessors(BB);
4519 // Next, add the true and fallthrough blocks as its successors.
4520 BB->addSuccessor(copy0MBB);
4521 BB->addSuccessor(sinkMBB);
4524 // %FalseValue = ...
4525 // # fallthrough to sinkMBB
4528 // Update machine-CFG edges
4529 BB->addSuccessor(sinkMBB);
4532 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4535 BuildMI(BB, dl, TII->get(PPC::PHI), MI->getOperand(0).getReg())
4536 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
4537 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4539 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
4540 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
4541 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
4542 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
4543 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
4544 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
4545 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
4546 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
4548 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
4549 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
4550 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
4551 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
4552 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
4553 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
4554 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
4555 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
4557 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
4558 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
4559 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
4560 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
4561 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
4562 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
4563 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
4564 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
4566 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
4567 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
4568 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
4569 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
4570 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
4571 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
4572 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
4573 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
4575 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
4576 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
4577 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
4578 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
4579 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
4580 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
4581 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
4582 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
4584 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
4585 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
4586 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
4587 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
4588 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
4589 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
4590 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
4591 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
4593 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
4594 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
4595 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
4596 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
4597 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
4598 BB = EmitAtomicBinary(MI, BB, false, 0);
4599 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
4600 BB = EmitAtomicBinary(MI, BB, true, 0);
4602 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
4603 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
4604 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
4606 unsigned dest = MI->getOperand(0).getReg();
4607 unsigned ptrA = MI->getOperand(1).getReg();
4608 unsigned ptrB = MI->getOperand(2).getReg();
4609 unsigned oldval = MI->getOperand(3).getReg();
4610 unsigned newval = MI->getOperand(4).getReg();
4611 DebugLoc dl = MI->getDebugLoc();
4613 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
4614 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
4615 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
4616 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4617 F->insert(It, loop1MBB);
4618 F->insert(It, loop2MBB);
4619 F->insert(It, midMBB);
4620 F->insert(It, exitMBB);
4621 exitMBB->transferSuccessors(BB);
4625 // fallthrough --> loopMBB
4626 BB->addSuccessor(loop1MBB);
4629 // l[wd]arx dest, ptr
4630 // cmp[wd] dest, oldval
4633 // st[wd]cx. newval, ptr
4637 // st[wd]cx. dest, ptr
4640 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
4641 .addReg(ptrA).addReg(ptrB);
4642 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
4643 .addReg(oldval).addReg(dest);
4644 BuildMI(BB, dl, TII->get(PPC::BCC))
4645 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
4646 BB->addSuccessor(loop2MBB);
4647 BB->addSuccessor(midMBB);
4650 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4651 .addReg(newval).addReg(ptrA).addReg(ptrB);
4652 BuildMI(BB, dl, TII->get(PPC::BCC))
4653 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
4654 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
4655 BB->addSuccessor(loop1MBB);
4656 BB->addSuccessor(exitMBB);
4659 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4660 .addReg(dest).addReg(ptrA).addReg(ptrB);
4661 BB->addSuccessor(exitMBB);
4666 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
4667 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
4668 // We must use 64-bit registers for addresses when targeting 64-bit,
4669 // since we're actually doing arithmetic on them. Other registers
4671 bool is64bit = PPCSubTarget.isPPC64();
4672 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
4674 unsigned dest = MI->getOperand(0).getReg();
4675 unsigned ptrA = MI->getOperand(1).getReg();
4676 unsigned ptrB = MI->getOperand(2).getReg();
4677 unsigned oldval = MI->getOperand(3).getReg();
4678 unsigned newval = MI->getOperand(4).getReg();
4679 DebugLoc dl = MI->getDebugLoc();
4681 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
4682 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
4683 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
4684 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4685 F->insert(It, loop1MBB);
4686 F->insert(It, loop2MBB);
4687 F->insert(It, midMBB);
4688 F->insert(It, exitMBB);
4689 exitMBB->transferSuccessors(BB);
4691 MachineRegisterInfo &RegInfo = F->getRegInfo();
4692 const TargetRegisterClass *RC =
4693 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4694 (const TargetRegisterClass *) &PPC::GPRCRegClass;
4695 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
4696 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
4697 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
4698 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
4699 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
4700 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
4701 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
4702 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
4703 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
4704 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
4705 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
4706 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
4707 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
4709 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
4712 // fallthrough --> loopMBB
4713 BB->addSuccessor(loop1MBB);
4715 // The 4-byte load must be aligned, while a char or short may be
4716 // anywhere in the word. Hence all this nasty bookkeeping code.
4717 // add ptr1, ptrA, ptrB [copy if ptrA==0]
4718 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
4719 // xori shift, shift1, 24 [16]
4720 // rlwinm ptr, ptr1, 0, 0, 29
4721 // slw newval2, newval, shift
4722 // slw oldval2, oldval,shift
4723 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
4724 // slw mask, mask2, shift
4725 // and newval3, newval2, mask
4726 // and oldval3, oldval2, mask
4728 // lwarx tmpDest, ptr
4729 // and tmp, tmpDest, mask
4730 // cmpw tmp, oldval3
4733 // andc tmp2, tmpDest, mask
4734 // or tmp4, tmp2, newval3
4739 // stwcx. tmpDest, ptr
4741 // srw dest, tmpDest, shift
4742 if (ptrA!=PPC::R0) {
4743 Ptr1Reg = RegInfo.createVirtualRegister(RC);
4744 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
4745 .addReg(ptrA).addReg(ptrB);
4749 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
4750 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
4751 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
4752 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
4754 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
4755 .addReg(Ptr1Reg).addImm(0).addImm(61);
4757 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
4758 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
4759 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
4760 .addReg(newval).addReg(ShiftReg);
4761 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
4762 .addReg(oldval).addReg(ShiftReg);
4764 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
4766 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
4767 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
4768 .addReg(Mask3Reg).addImm(65535);
4770 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
4771 .addReg(Mask2Reg).addReg(ShiftReg);
4772 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
4773 .addReg(NewVal2Reg).addReg(MaskReg);
4774 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
4775 .addReg(OldVal2Reg).addReg(MaskReg);
4778 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
4779 .addReg(PPC::R0).addReg(PtrReg);
4780 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
4781 .addReg(TmpDestReg).addReg(MaskReg);
4782 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
4783 .addReg(TmpReg).addReg(OldVal3Reg);
4784 BuildMI(BB, dl, TII->get(PPC::BCC))
4785 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
4786 BB->addSuccessor(loop2MBB);
4787 BB->addSuccessor(midMBB);
4790 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
4791 .addReg(TmpDestReg).addReg(MaskReg);
4792 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
4793 .addReg(Tmp2Reg).addReg(NewVal3Reg);
4794 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
4795 .addReg(PPC::R0).addReg(PtrReg);
4796 BuildMI(BB, dl, TII->get(PPC::BCC))
4797 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
4798 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
4799 BB->addSuccessor(loop1MBB);
4800 BB->addSuccessor(exitMBB);
4803 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
4804 .addReg(PPC::R0).addReg(PtrReg);
4805 BB->addSuccessor(exitMBB);
4810 BuildMI(BB, dl, TII->get(PPC::SRW),dest).addReg(TmpReg).addReg(ShiftReg);
4812 llvm_unreachable("Unexpected instr type to insert");
4815 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
4819 //===----------------------------------------------------------------------===//
4820 // Target Optimization Hooks
4821 //===----------------------------------------------------------------------===//
4823 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
4824 DAGCombinerInfo &DCI) const {
4825 TargetMachine &TM = getTargetMachine();
4826 SelectionDAG &DAG = DCI.DAG;
4827 DebugLoc dl = N->getDebugLoc();
4828 switch (N->getOpcode()) {
4831 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
4832 if (C->getZExtValue() == 0) // 0 << V -> 0.
4833 return N->getOperand(0);
4837 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
4838 if (C->getZExtValue() == 0) // 0 >>u V -> 0.
4839 return N->getOperand(0);
4843 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
4844 if (C->getZExtValue() == 0 || // 0 >>s V -> 0.
4845 C->isAllOnesValue()) // -1 >>s V -> -1.
4846 return N->getOperand(0);
4850 case ISD::SINT_TO_FP:
4851 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
4852 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
4853 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
4854 // We allow the src/dst to be either f32/f64, but the intermediate
4855 // type must be i64.
4856 if (N->getOperand(0).getValueType() == MVT::i64 &&
4857 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
4858 SDValue Val = N->getOperand(0).getOperand(0);
4859 if (Val.getValueType() == MVT::f32) {
4860 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
4861 DCI.AddToWorklist(Val.getNode());
4864 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
4865 DCI.AddToWorklist(Val.getNode());
4866 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
4867 DCI.AddToWorklist(Val.getNode());
4868 if (N->getValueType(0) == MVT::f32) {
4869 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
4870 DAG.getIntPtrConstant(0));
4871 DCI.AddToWorklist(Val.getNode());
4874 } else if (N->getOperand(0).getValueType() == MVT::i32) {
4875 // If the intermediate type is i32, we can avoid the load/store here
4882 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
4883 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
4884 !cast<StoreSDNode>(N)->isTruncatingStore() &&
4885 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
4886 N->getOperand(1).getValueType() == MVT::i32 &&
4887 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
4888 SDValue Val = N->getOperand(1).getOperand(0);
4889 if (Val.getValueType() == MVT::f32) {
4890 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
4891 DCI.AddToWorklist(Val.getNode());
4893 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
4894 DCI.AddToWorklist(Val.getNode());
4896 Val = DAG.getNode(PPCISD::STFIWX, dl, MVT::Other, N->getOperand(0), Val,
4897 N->getOperand(2), N->getOperand(3));
4898 DCI.AddToWorklist(Val.getNode());
4902 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
4903 if (N->getOperand(1).getOpcode() == ISD::BSWAP &&
4904 N->getOperand(1).getNode()->hasOneUse() &&
4905 (N->getOperand(1).getValueType() == MVT::i32 ||
4906 N->getOperand(1).getValueType() == MVT::i16)) {
4907 SDValue BSwapOp = N->getOperand(1).getOperand(0);
4908 // Do an any-extend to 32-bits if this is a half-word input.
4909 if (BSwapOp.getValueType() == MVT::i16)
4910 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
4912 return DAG.getNode(PPCISD::STBRX, dl, MVT::Other, N->getOperand(0),
4913 BSwapOp, N->getOperand(2), N->getOperand(3),
4914 DAG.getValueType(N->getOperand(1).getValueType()));
4918 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
4919 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
4920 N->getOperand(0).hasOneUse() &&
4921 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
4922 SDValue Load = N->getOperand(0);
4923 LoadSDNode *LD = cast<LoadSDNode>(Load);
4924 // Create the byte-swapping load.
4925 std::vector<EVT> VTs;
4926 VTs.push_back(MVT::i32);
4927 VTs.push_back(MVT::Other);
4928 SDValue MO = DAG.getMemOperand(LD->getMemOperand());
4930 LD->getChain(), // Chain
4931 LD->getBasePtr(), // Ptr
4933 DAG.getValueType(N->getValueType(0)) // VT
4935 SDValue BSLoad = DAG.getNode(PPCISD::LBRX, dl, VTs, Ops, 4);
4937 // If this is an i16 load, insert the truncate.
4938 SDValue ResVal = BSLoad;
4939 if (N->getValueType(0) == MVT::i16)
4940 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
4942 // First, combine the bswap away. This makes the value produced by the
4944 DCI.CombineTo(N, ResVal);
4946 // Next, combine the load away, we give it a bogus result value but a real
4947 // chain result. The result value is dead because the bswap is dead.
4948 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
4950 // Return N so it doesn't get rechecked!
4951 return SDValue(N, 0);
4955 case PPCISD::VCMP: {
4956 // If a VCMPo node already exists with exactly the same operands as this
4957 // node, use its result instead of this node (VCMPo computes both a CR6 and
4958 // a normal output).
4960 if (!N->getOperand(0).hasOneUse() &&
4961 !N->getOperand(1).hasOneUse() &&
4962 !N->getOperand(2).hasOneUse()) {
4964 // Scan all of the users of the LHS, looking for VCMPo's that match.
4965 SDNode *VCMPoNode = 0;
4967 SDNode *LHSN = N->getOperand(0).getNode();
4968 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
4970 if (UI->getOpcode() == PPCISD::VCMPo &&
4971 UI->getOperand(1) == N->getOperand(1) &&
4972 UI->getOperand(2) == N->getOperand(2) &&
4973 UI->getOperand(0) == N->getOperand(0)) {
4978 // If there is no VCMPo node, or if the flag value has a single use, don't
4980 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
4983 // Look at the (necessarily single) use of the flag value. If it has a
4984 // chain, this transformation is more complex. Note that multiple things
4985 // could use the value result, which we should ignore.
4986 SDNode *FlagUser = 0;
4987 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
4988 FlagUser == 0; ++UI) {
4989 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
4991 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
4992 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
4999 // If the user is a MFCR instruction, we know this is safe. Otherwise we
5000 // give up for right now.
5001 if (FlagUser->getOpcode() == PPCISD::MFCR)
5002 return SDValue(VCMPoNode, 0);
5007 // If this is a branch on an altivec predicate comparison, lower this so
5008 // that we don't have to do a MFCR: instead, branch directly on CR6. This
5009 // lowering is done pre-legalize, because the legalizer lowers the predicate
5010 // compare down to code that is difficult to reassemble.
5011 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
5012 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
5016 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
5017 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
5018 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
5019 assert(isDot && "Can't compare against a vector result!");
5021 // If this is a comparison against something other than 0/1, then we know
5022 // that the condition is never/always true.
5023 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
5024 if (Val != 0 && Val != 1) {
5025 if (CC == ISD::SETEQ) // Cond never true, remove branch.
5026 return N->getOperand(0);
5027 // Always !=, turn it into an unconditional branch.
5028 return DAG.getNode(ISD::BR, dl, MVT::Other,
5029 N->getOperand(0), N->getOperand(4));
5032 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
5034 // Create the PPCISD altivec 'dot' comparison node.
5035 std::vector<EVT> VTs;
5037 LHS.getOperand(2), // LHS of compare
5038 LHS.getOperand(3), // RHS of compare
5039 DAG.getConstant(CompareOpc, MVT::i32)
5041 VTs.push_back(LHS.getOperand(2).getValueType());
5042 VTs.push_back(MVT::Flag);
5043 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
5045 // Unpack the result based on how the target uses it.
5046 PPC::Predicate CompOpc;
5047 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
5048 default: // Can't happen, don't crash on invalid number though.
5049 case 0: // Branch on the value of the EQ bit of CR6.
5050 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
5052 case 1: // Branch on the inverted value of the EQ bit of CR6.
5053 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
5055 case 2: // Branch on the value of the LT bit of CR6.
5056 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
5058 case 3: // Branch on the inverted value of the LT bit of CR6.
5059 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
5063 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
5064 DAG.getConstant(CompOpc, MVT::i32),
5065 DAG.getRegister(PPC::CR6, MVT::i32),
5066 N->getOperand(4), CompNode.getValue(1));
5075 //===----------------------------------------------------------------------===//
5076 // Inline Assembly Support
5077 //===----------------------------------------------------------------------===//
5079 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
5083 const SelectionDAG &DAG,
5084 unsigned Depth) const {
5085 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
5086 switch (Op.getOpcode()) {
5088 case PPCISD::LBRX: {
5089 // lhbrx is known to have the top bits cleared out.
5090 if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16)
5091 KnownZero = 0xFFFF0000;
5094 case ISD::INTRINSIC_WO_CHAIN: {
5095 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
5097 case Intrinsic::ppc_altivec_vcmpbfp_p:
5098 case Intrinsic::ppc_altivec_vcmpeqfp_p:
5099 case Intrinsic::ppc_altivec_vcmpequb_p:
5100 case Intrinsic::ppc_altivec_vcmpequh_p:
5101 case Intrinsic::ppc_altivec_vcmpequw_p:
5102 case Intrinsic::ppc_altivec_vcmpgefp_p:
5103 case Intrinsic::ppc_altivec_vcmpgtfp_p:
5104 case Intrinsic::ppc_altivec_vcmpgtsb_p:
5105 case Intrinsic::ppc_altivec_vcmpgtsh_p:
5106 case Intrinsic::ppc_altivec_vcmpgtsw_p:
5107 case Intrinsic::ppc_altivec_vcmpgtub_p:
5108 case Intrinsic::ppc_altivec_vcmpgtuh_p:
5109 case Intrinsic::ppc_altivec_vcmpgtuw_p:
5110 KnownZero = ~1U; // All bits but the low one are known to be zero.
5118 /// getConstraintType - Given a constraint, return the type of
5119 /// constraint it is for this target.
5120 PPCTargetLowering::ConstraintType
5121 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
5122 if (Constraint.size() == 1) {
5123 switch (Constraint[0]) {
5130 return C_RegisterClass;
5133 return TargetLowering::getConstraintType(Constraint);
5136 std::pair<unsigned, const TargetRegisterClass*>
5137 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
5139 if (Constraint.size() == 1) {
5140 // GCC RS6000 Constraint Letters
5141 switch (Constraint[0]) {
5144 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
5145 return std::make_pair(0U, PPC::G8RCRegisterClass);
5146 return std::make_pair(0U, PPC::GPRCRegisterClass);
5149 return std::make_pair(0U, PPC::F4RCRegisterClass);
5150 else if (VT == MVT::f64)
5151 return std::make_pair(0U, PPC::F8RCRegisterClass);
5154 return std::make_pair(0U, PPC::VRRCRegisterClass);
5156 return std::make_pair(0U, PPC::CRRCRegisterClass);
5160 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
5164 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
5165 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is true
5166 /// it means one of the asm constraint of the inline asm instruction being
5167 /// processed is 'm'.
5168 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, char Letter,
5170 std::vector<SDValue>&Ops,
5171 SelectionDAG &DAG) const {
5172 SDValue Result(0,0);
5183 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
5184 if (!CST) return; // Must be an immediate to match.
5185 unsigned Value = CST->getZExtValue();
5187 default: llvm_unreachable("Unknown constraint letter!");
5188 case 'I': // "I" is a signed 16-bit constant.
5189 if ((short)Value == (int)Value)
5190 Result = DAG.getTargetConstant(Value, Op.getValueType());
5192 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
5193 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
5194 if ((short)Value == 0)
5195 Result = DAG.getTargetConstant(Value, Op.getValueType());
5197 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
5198 if ((Value >> 16) == 0)
5199 Result = DAG.getTargetConstant(Value, Op.getValueType());
5201 case 'M': // "M" is a constant that is greater than 31.
5203 Result = DAG.getTargetConstant(Value, Op.getValueType());
5205 case 'N': // "N" is a positive constant that is an exact power of two.
5206 if ((int)Value > 0 && isPowerOf2_32(Value))
5207 Result = DAG.getTargetConstant(Value, Op.getValueType());
5209 case 'O': // "O" is the constant zero.
5211 Result = DAG.getTargetConstant(Value, Op.getValueType());
5213 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
5214 if ((short)-Value == (int)-Value)
5215 Result = DAG.getTargetConstant(Value, Op.getValueType());
5222 if (Result.getNode()) {
5223 Ops.push_back(Result);
5227 // Handle standard constraint letters.
5228 TargetLowering::LowerAsmOperandForConstraint(Op, Letter, hasMemory, Ops, DAG);
5231 // isLegalAddressingMode - Return true if the addressing mode represented
5232 // by AM is legal for this target, for a load/store of the specified type.
5233 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
5234 const Type *Ty) const {
5235 // FIXME: PPC does not allow r+i addressing modes for vectors!
5237 // PPC allows a sign-extended 16-bit immediate field.
5238 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
5241 // No global is ever allowed as a base.
5245 // PPC only support r+r,
5247 case 0: // "r+i" or just "i", depending on HasBaseReg.
5250 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
5252 // Otherwise we have r+r or r+i.
5255 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
5257 // Allow 2*r as r+r.
5260 // No other scales are supported.
5267 /// isLegalAddressImmediate - Return true if the integer value can be used
5268 /// as the offset of the target addressing mode for load / store of the
5270 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{
5271 // PPC allows a sign-extended 16-bit immediate field.
5272 return (V > -(1 << 16) && V < (1 << 16)-1);
5275 bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
5279 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
5280 DebugLoc dl = Op.getDebugLoc();
5281 // Depths > 0 not supported yet!
5282 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
5285 MachineFunction &MF = DAG.getMachineFunction();
5286 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
5288 // Just load the return address off the stack.
5289 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
5291 // Make sure the function really does not optimize away the store of the RA
5293 FuncInfo->setLRStoreRequired();
5294 return DAG.getLoad(getPointerTy(), dl,
5295 DAG.getEntryNode(), RetAddrFI, NULL, 0);
5298 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
5299 DebugLoc dl = Op.getDebugLoc();
5300 // Depths > 0 not supported yet!
5301 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
5304 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5305 bool isPPC64 = PtrVT == MVT::i64;
5307 MachineFunction &MF = DAG.getMachineFunction();
5308 MachineFrameInfo *MFI = MF.getFrameInfo();
5309 bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects())
5310 && MFI->getStackSize();
5313 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, is31 ? PPC::X31 : PPC::X1,
5316 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, is31 ? PPC::R31 : PPC::R1,
5321 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
5322 // The PowerPC target isn't yet aware of offsets.
5326 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
5327 bool isSrcConst, bool isSrcStr,
5328 SelectionDAG &DAG) const {
5329 if (this->PPCSubTarget.isPPC64()) {