1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCMachineFunctionInfo.h"
16 #include "PPCPerfectShuffle.h"
17 #include "PPCPredicates.h"
18 #include "PPCTargetMachine.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/VectorExtras.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/PseudoSourceValue.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
29 #include "llvm/CallingConv.h"
30 #include "llvm/Constants.h"
31 #include "llvm/Function.h"
32 #include "llvm/Intrinsics.h"
33 #include "llvm/Support/MathExtras.h"
34 #include "llvm/Target/TargetOptions.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/DerivedTypes.h"
41 static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
42 CCValAssign::LocInfo &LocInfo,
43 ISD::ArgFlagsTy &ArgFlags,
45 static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
47 CCValAssign::LocInfo &LocInfo,
48 ISD::ArgFlagsTy &ArgFlags,
50 static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
52 CCValAssign::LocInfo &LocInfo,
53 ISD::ArgFlagsTy &ArgFlags,
56 static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc",
57 cl::desc("enable preincrement load/store generation on PPC (experimental)"),
60 static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) {
61 if (TM.getSubtargetImpl()->isDarwin())
62 return new TargetLoweringObjectFileMachO();
64 return new TargetLoweringObjectFileELF();
67 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
68 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) {
72 // Use _setjmp/_longjmp instead of setjmp/longjmp.
73 setUseUnderscoreSetJmp(true);
74 setUseUnderscoreLongJmp(true);
76 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
77 // arguments are at least 4/8 bytes aligned.
78 setMinStackArgumentAlignment(TM.getSubtarget<PPCSubtarget>().isPPC64() ? 8:4);
80 // Set up the register classes.
81 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
82 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
83 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
85 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
86 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
87 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
89 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
91 // PowerPC has pre-inc load and store's.
92 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
93 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
94 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
95 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
96 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
99 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
100 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
101 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
103 // This is used in the ppcf128->int sequence. Note it has different semantics
104 // from FP_ROUND: that rounds to nearest, this rounds to zero.
105 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
107 // PowerPC has no SREM/UREM instructions
108 setOperationAction(ISD::SREM, MVT::i32, Expand);
109 setOperationAction(ISD::UREM, MVT::i32, Expand);
110 setOperationAction(ISD::SREM, MVT::i64, Expand);
111 setOperationAction(ISD::UREM, MVT::i64, Expand);
113 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
114 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
115 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
116 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
117 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
118 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
119 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
120 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
121 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
123 // We don't support sin/cos/sqrt/fmod/pow
124 setOperationAction(ISD::FSIN , MVT::f64, Expand);
125 setOperationAction(ISD::FCOS , MVT::f64, Expand);
126 setOperationAction(ISD::FREM , MVT::f64, Expand);
127 setOperationAction(ISD::FPOW , MVT::f64, Expand);
128 setOperationAction(ISD::FSIN , MVT::f32, Expand);
129 setOperationAction(ISD::FCOS , MVT::f32, Expand);
130 setOperationAction(ISD::FREM , MVT::f32, Expand);
131 setOperationAction(ISD::FPOW , MVT::f32, Expand);
133 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
135 // If we're enabling GP optimizations, use hardware square root
136 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
137 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
138 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
141 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
142 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
144 // PowerPC does not have BSWAP, CTPOP or CTTZ
145 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
146 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
147 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
148 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
149 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
150 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
152 // PowerPC does not have ROTR
153 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
154 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
156 // PowerPC does not have Select
157 setOperationAction(ISD::SELECT, MVT::i32, Expand);
158 setOperationAction(ISD::SELECT, MVT::i64, Expand);
159 setOperationAction(ISD::SELECT, MVT::f32, Expand);
160 setOperationAction(ISD::SELECT, MVT::f64, Expand);
162 // PowerPC wants to turn select_cc of FP into fsel when possible.
163 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
164 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
166 // PowerPC wants to optimize integer setcc a bit
167 setOperationAction(ISD::SETCC, MVT::i32, Custom);
169 // PowerPC does not have BRCOND which requires SetCC
170 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
172 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
174 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
175 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
177 // PowerPC does not have [U|S]INT_TO_FP
178 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
179 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
181 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
182 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
183 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
184 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
186 // We cannot sextinreg(i1). Expand to shifts.
187 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
189 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
190 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
191 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
192 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
195 // We want to legalize GlobalAddress and ConstantPool nodes into the
196 // appropriate instructions to materialize the address.
197 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
198 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
199 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
200 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
201 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
202 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
203 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
204 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
205 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
206 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
209 setOperationAction(ISD::TRAP, MVT::Other, Legal);
211 // TRAMPOLINE is custom lowered.
212 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
214 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
215 setOperationAction(ISD::VASTART , MVT::Other, Custom);
217 // VAARG is custom lowered with the 32-bit SVR4 ABI.
218 if ( TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
219 && !TM.getSubtarget<PPCSubtarget>().isPPC64())
220 setOperationAction(ISD::VAARG, MVT::Other, Custom);
222 setOperationAction(ISD::VAARG, MVT::Other, Expand);
224 // Use the default implementation.
225 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
226 setOperationAction(ISD::VAEND , MVT::Other, Expand);
227 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
228 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
229 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
230 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
232 // We want to custom lower some of our intrinsics.
233 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
235 // Comparisons that require checking two conditions.
236 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
237 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
238 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
239 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
240 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
241 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
242 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
243 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
244 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
245 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
246 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
247 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
249 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
250 // They also have instructions for converting between i64 and fp.
251 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
252 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
253 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
254 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
255 // This is just the low 32 bits of a (signed) fp->i64 conversion.
256 // We cannot do this with Promote because i64 is not a legal type.
257 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
259 // FIXME: disable this lowered code. This generates 64-bit register values,
260 // and we don't model the fact that the top part is clobbered by calls. We
261 // need to flag these together so that the value isn't live across a call.
262 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
264 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
265 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
268 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
269 // 64-bit PowerPC implementations can support i64 types directly
270 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
271 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
272 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
273 // 64-bit PowerPC wants to expand i128 shifts itself.
274 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
275 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
276 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
278 // 32-bit PowerPC wants to expand i64 shifts itself.
279 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
280 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
281 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
284 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
285 // First set operation action for all vector types to expand. Then we
286 // will selectively turn on ones that can be effectively codegen'd.
287 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
288 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
289 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
291 // add/sub are legal for all supported vector VT's.
292 setOperationAction(ISD::ADD , VT, Legal);
293 setOperationAction(ISD::SUB , VT, Legal);
295 // We promote all shuffles to v16i8.
296 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
297 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
299 // We promote all non-typed operations to v4i32.
300 setOperationAction(ISD::AND , VT, Promote);
301 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
302 setOperationAction(ISD::OR , VT, Promote);
303 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
304 setOperationAction(ISD::XOR , VT, Promote);
305 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
306 setOperationAction(ISD::LOAD , VT, Promote);
307 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
308 setOperationAction(ISD::SELECT, VT, Promote);
309 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
310 setOperationAction(ISD::STORE, VT, Promote);
311 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
313 // No other operations are legal.
314 setOperationAction(ISD::MUL , VT, Expand);
315 setOperationAction(ISD::SDIV, VT, Expand);
316 setOperationAction(ISD::SREM, VT, Expand);
317 setOperationAction(ISD::UDIV, VT, Expand);
318 setOperationAction(ISD::UREM, VT, Expand);
319 setOperationAction(ISD::FDIV, VT, Expand);
320 setOperationAction(ISD::FNEG, VT, Expand);
321 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
322 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
323 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
324 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
325 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
326 setOperationAction(ISD::UDIVREM, VT, Expand);
327 setOperationAction(ISD::SDIVREM, VT, Expand);
328 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
329 setOperationAction(ISD::FPOW, VT, Expand);
330 setOperationAction(ISD::CTPOP, VT, Expand);
331 setOperationAction(ISD::CTLZ, VT, Expand);
332 setOperationAction(ISD::CTTZ, VT, Expand);
335 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
336 // with merges, splats, etc.
337 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
339 setOperationAction(ISD::AND , MVT::v4i32, Legal);
340 setOperationAction(ISD::OR , MVT::v4i32, Legal);
341 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
342 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
343 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
344 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
346 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
347 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
348 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
349 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
351 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
352 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
353 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
354 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
356 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
357 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
359 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
360 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
361 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
362 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
365 setShiftAmountType(MVT::i32);
366 setBooleanContents(ZeroOrOneBooleanContent);
368 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
369 setStackPointerRegisterToSaveRestore(PPC::X1);
370 setExceptionPointerRegister(PPC::X3);
371 setExceptionSelectorRegister(PPC::X4);
373 setStackPointerRegisterToSaveRestore(PPC::R1);
374 setExceptionPointerRegister(PPC::R3);
375 setExceptionSelectorRegister(PPC::R4);
378 // We have target-specific dag combine patterns for the following nodes:
379 setTargetDAGCombine(ISD::SINT_TO_FP);
380 setTargetDAGCombine(ISD::STORE);
381 setTargetDAGCombine(ISD::BR_CC);
382 setTargetDAGCombine(ISD::BSWAP);
384 // Darwin long double math library functions have $LDBL128 appended.
385 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) {
386 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
387 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
388 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
389 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
390 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
391 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
392 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
393 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
394 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
395 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
398 computeRegisterProperties();
401 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
402 /// function arguments in the caller parameter area.
403 unsigned PPCTargetLowering::getByValTypeAlignment(const Type *Ty) const {
404 const TargetMachine &TM = getTargetMachine();
405 // Darwin passes everything on 4 byte boundary.
406 if (TM.getSubtarget<PPCSubtarget>().isDarwin())
412 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
415 case PPCISD::FSEL: return "PPCISD::FSEL";
416 case PPCISD::FCFID: return "PPCISD::FCFID";
417 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
418 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
419 case PPCISD::STFIWX: return "PPCISD::STFIWX";
420 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
421 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
422 case PPCISD::VPERM: return "PPCISD::VPERM";
423 case PPCISD::Hi: return "PPCISD::Hi";
424 case PPCISD::Lo: return "PPCISD::Lo";
425 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
426 case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE";
427 case PPCISD::LOAD: return "PPCISD::LOAD";
428 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
429 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
430 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
431 case PPCISD::SRL: return "PPCISD::SRL";
432 case PPCISD::SRA: return "PPCISD::SRA";
433 case PPCISD::SHL: return "PPCISD::SHL";
434 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
435 case PPCISD::STD_32: return "PPCISD::STD_32";
436 case PPCISD::CALL_SVR4: return "PPCISD::CALL_SVR4";
437 case PPCISD::CALL_Darwin: return "PPCISD::CALL_Darwin";
438 case PPCISD::NOP: return "PPCISD::NOP";
439 case PPCISD::MTCTR: return "PPCISD::MTCTR";
440 case PPCISD::BCTRL_Darwin: return "PPCISD::BCTRL_Darwin";
441 case PPCISD::BCTRL_SVR4: return "PPCISD::BCTRL_SVR4";
442 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
443 case PPCISD::MFCR: return "PPCISD::MFCR";
444 case PPCISD::VCMP: return "PPCISD::VCMP";
445 case PPCISD::VCMPo: return "PPCISD::VCMPo";
446 case PPCISD::LBRX: return "PPCISD::LBRX";
447 case PPCISD::STBRX: return "PPCISD::STBRX";
448 case PPCISD::LARX: return "PPCISD::LARX";
449 case PPCISD::STCX: return "PPCISD::STCX";
450 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
451 case PPCISD::MFFS: return "PPCISD::MFFS";
452 case PPCISD::MTFSB0: return "PPCISD::MTFSB0";
453 case PPCISD::MTFSB1: return "PPCISD::MTFSB1";
454 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
455 case PPCISD::MTFSF: return "PPCISD::MTFSF";
456 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
460 MVT::SimpleValueType PPCTargetLowering::getSetCCResultType(EVT VT) const {
464 /// getFunctionAlignment - Return the Log2 alignment of this function.
465 unsigned PPCTargetLowering::getFunctionAlignment(const Function *F) const {
466 if (getTargetMachine().getSubtarget<PPCSubtarget>().isDarwin())
467 return F->hasFnAttr(Attribute::OptimizeForSize) ? 2 : 4;
472 //===----------------------------------------------------------------------===//
473 // Node matching predicates, for use by the tblgen matching code.
474 //===----------------------------------------------------------------------===//
476 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
477 static bool isFloatingPointZero(SDValue Op) {
478 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
479 return CFP->getValueAPF().isZero();
480 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
481 // Maybe this has already been legalized into the constant pool?
482 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
483 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
484 return CFP->getValueAPF().isZero();
489 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
490 /// true if Op is undef or if it matches the specified value.
491 static bool isConstantOrUndef(int Op, int Val) {
492 return Op < 0 || Op == Val;
495 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
496 /// VPKUHUM instruction.
497 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
499 for (unsigned i = 0; i != 16; ++i)
500 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
503 for (unsigned i = 0; i != 8; ++i)
504 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) ||
505 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1))
511 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
512 /// VPKUWUM instruction.
513 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
515 for (unsigned i = 0; i != 16; i += 2)
516 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
517 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
520 for (unsigned i = 0; i != 8; i += 2)
521 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
522 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) ||
523 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) ||
524 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3))
530 /// isVMerge - Common function, used to match vmrg* shuffles.
532 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
533 unsigned LHSStart, unsigned RHSStart) {
534 assert(N->getValueType(0) == MVT::v16i8 &&
535 "PPC only supports shuffles by bytes!");
536 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
537 "Unsupported merge size!");
539 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
540 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
541 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
542 LHSStart+j+i*UnitSize) ||
543 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
544 RHSStart+j+i*UnitSize))
550 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
551 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
552 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
555 return isVMerge(N, UnitSize, 8, 24);
556 return isVMerge(N, UnitSize, 8, 8);
559 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
560 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
561 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
564 return isVMerge(N, UnitSize, 0, 16);
565 return isVMerge(N, UnitSize, 0, 0);
569 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
570 /// amount, otherwise return -1.
571 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
572 assert(N->getValueType(0) == MVT::v16i8 &&
573 "PPC only supports shuffles by bytes!");
575 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
577 // Find the first non-undef value in the shuffle mask.
579 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
582 if (i == 16) return -1; // all undef.
584 // Otherwise, check to see if the rest of the elements are consecutively
585 // numbered from this value.
586 unsigned ShiftAmt = SVOp->getMaskElt(i);
587 if (ShiftAmt < i) return -1;
591 // Check the rest of the elements to see if they are consecutive.
592 for (++i; i != 16; ++i)
593 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
596 // Check the rest of the elements to see if they are consecutive.
597 for (++i; i != 16; ++i)
598 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
604 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
605 /// specifies a splat of a single element that is suitable for input to
606 /// VSPLTB/VSPLTH/VSPLTW.
607 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
608 assert(N->getValueType(0) == MVT::v16i8 &&
609 (EltSize == 1 || EltSize == 2 || EltSize == 4));
611 // This is a splat operation if each element of the permute is the same, and
612 // if the value doesn't reference the second vector.
613 unsigned ElementBase = N->getMaskElt(0);
615 // FIXME: Handle UNDEF elements too!
616 if (ElementBase >= 16)
619 // Check that the indices are consecutive, in the case of a multi-byte element
620 // splatted with a v16i8 mask.
621 for (unsigned i = 1; i != EltSize; ++i)
622 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
625 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
626 if (N->getMaskElt(i) < 0) continue;
627 for (unsigned j = 0; j != EltSize; ++j)
628 if (N->getMaskElt(i+j) != N->getMaskElt(j))
634 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
636 bool PPC::isAllNegativeZeroVector(SDNode *N) {
637 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
639 APInt APVal, APUndef;
643 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
644 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
645 return CFP->getValueAPF().isNegZero();
650 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
651 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
652 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
653 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
654 assert(isSplatShuffleMask(SVOp, EltSize));
655 return SVOp->getMaskElt(0) / EltSize;
658 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
659 /// by using a vspltis[bhw] instruction of the specified element size, return
660 /// the constant being splatted. The ByteSize field indicates the number of
661 /// bytes of each element [124] -> [bhw].
662 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
665 // If ByteSize of the splat is bigger than the element size of the
666 // build_vector, then we have a case where we are checking for a splat where
667 // multiple elements of the buildvector are folded together into a single
668 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
669 unsigned EltSize = 16/N->getNumOperands();
670 if (EltSize < ByteSize) {
671 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
672 SDValue UniquedVals[4];
673 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
675 // See if all of the elements in the buildvector agree across.
676 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
677 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
678 // If the element isn't a constant, bail fully out.
679 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
682 if (UniquedVals[i&(Multiple-1)].getNode() == 0)
683 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
684 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
685 return SDValue(); // no match.
688 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
689 // either constant or undef values that are identical for each chunk. See
690 // if these chunks can form into a larger vspltis*.
692 // Check to see if all of the leading entries are either 0 or -1. If
693 // neither, then this won't fit into the immediate field.
694 bool LeadingZero = true;
695 bool LeadingOnes = true;
696 for (unsigned i = 0; i != Multiple-1; ++i) {
697 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs.
699 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
700 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
702 // Finally, check the least significant entry.
704 if (UniquedVals[Multiple-1].getNode() == 0)
705 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
706 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
708 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
711 if (UniquedVals[Multiple-1].getNode() == 0)
712 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
713 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
714 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
715 return DAG.getTargetConstant(Val, MVT::i32);
721 // Check to see if this buildvec has a single non-undef value in its elements.
722 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
723 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
724 if (OpVal.getNode() == 0)
725 OpVal = N->getOperand(i);
726 else if (OpVal != N->getOperand(i))
730 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def.
732 unsigned ValSizeInBytes = EltSize;
734 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
735 Value = CN->getZExtValue();
736 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
737 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
738 Value = FloatToBits(CN->getValueAPF().convertToFloat());
741 // If the splat value is larger than the element value, then we can never do
742 // this splat. The only case that we could fit the replicated bits into our
743 // immediate field for would be zero, and we prefer to use vxor for it.
744 if (ValSizeInBytes < ByteSize) return SDValue();
746 // If the element value is larger than the splat value, cut it in half and
747 // check to see if the two halves are equal. Continue doing this until we
748 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
749 while (ValSizeInBytes > ByteSize) {
750 ValSizeInBytes >>= 1;
752 // If the top half equals the bottom half, we're still ok.
753 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
754 (Value & ((1 << (8*ValSizeInBytes))-1)))
758 // Properly sign extend the value.
759 int ShAmt = (4-ByteSize)*8;
760 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
762 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
763 if (MaskVal == 0) return SDValue();
765 // Finally, if this value fits in a 5 bit sext field, return it
766 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
767 return DAG.getTargetConstant(MaskVal, MVT::i32);
771 //===----------------------------------------------------------------------===//
772 // Addressing Mode Selection
773 //===----------------------------------------------------------------------===//
775 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
776 /// or 64-bit immediate, and if the value can be accurately represented as a
777 /// sign extension from a 16-bit value. If so, this returns true and the
779 static bool isIntS16Immediate(SDNode *N, short &Imm) {
780 if (N->getOpcode() != ISD::Constant)
783 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
784 if (N->getValueType(0) == MVT::i32)
785 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
787 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
789 static bool isIntS16Immediate(SDValue Op, short &Imm) {
790 return isIntS16Immediate(Op.getNode(), Imm);
794 /// SelectAddressRegReg - Given the specified addressed, check to see if it
795 /// can be represented as an indexed [r+r] operation. Returns false if it
796 /// can be more efficiently represented with [r+imm].
797 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
799 SelectionDAG &DAG) const {
801 if (N.getOpcode() == ISD::ADD) {
802 if (isIntS16Immediate(N.getOperand(1), imm))
804 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
807 Base = N.getOperand(0);
808 Index = N.getOperand(1);
810 } else if (N.getOpcode() == ISD::OR) {
811 if (isIntS16Immediate(N.getOperand(1), imm))
812 return false; // r+i can fold it if we can.
814 // If this is an or of disjoint bitfields, we can codegen this as an add
815 // (for better address arithmetic) if the LHS and RHS of the OR are provably
817 APInt LHSKnownZero, LHSKnownOne;
818 APInt RHSKnownZero, RHSKnownOne;
819 DAG.ComputeMaskedBits(N.getOperand(0),
820 APInt::getAllOnesValue(N.getOperand(0)
821 .getValueSizeInBits()),
822 LHSKnownZero, LHSKnownOne);
824 if (LHSKnownZero.getBoolValue()) {
825 DAG.ComputeMaskedBits(N.getOperand(1),
826 APInt::getAllOnesValue(N.getOperand(1)
827 .getValueSizeInBits()),
828 RHSKnownZero, RHSKnownOne);
829 // If all of the bits are known zero on the LHS or RHS, the add won't
831 if (~(LHSKnownZero | RHSKnownZero) == 0) {
832 Base = N.getOperand(0);
833 Index = N.getOperand(1);
842 /// Returns true if the address N can be represented by a base register plus
843 /// a signed 16-bit displacement [r+imm], and if it is not better
844 /// represented as reg+reg.
845 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
847 SelectionDAG &DAG) const {
848 // FIXME dl should come from parent load or store, not from address
849 DebugLoc dl = N.getDebugLoc();
850 // If this can be more profitably realized as r+r, fail.
851 if (SelectAddressRegReg(N, Disp, Base, DAG))
854 if (N.getOpcode() == ISD::ADD) {
856 if (isIntS16Immediate(N.getOperand(1), imm)) {
857 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
858 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
859 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
861 Base = N.getOperand(0);
863 return true; // [r+i]
864 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
865 // Match LOAD (ADD (X, Lo(G))).
866 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
867 && "Cannot handle constant offsets yet!");
868 Disp = N.getOperand(1).getOperand(0); // The global address.
869 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
870 Disp.getOpcode() == ISD::TargetConstantPool ||
871 Disp.getOpcode() == ISD::TargetJumpTable);
872 Base = N.getOperand(0);
873 return true; // [&g+r]
875 } else if (N.getOpcode() == ISD::OR) {
877 if (isIntS16Immediate(N.getOperand(1), imm)) {
878 // If this is an or of disjoint bitfields, we can codegen this as an add
879 // (for better address arithmetic) if the LHS and RHS of the OR are
880 // provably disjoint.
881 APInt LHSKnownZero, LHSKnownOne;
882 DAG.ComputeMaskedBits(N.getOperand(0),
883 APInt::getAllOnesValue(N.getOperand(0)
884 .getValueSizeInBits()),
885 LHSKnownZero, LHSKnownOne);
887 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
888 // If all of the bits are known zero on the LHS or RHS, the add won't
890 Base = N.getOperand(0);
891 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
895 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
896 // Loading from a constant address.
898 // If this address fits entirely in a 16-bit sext immediate field, codegen
901 if (isIntS16Immediate(CN, Imm)) {
902 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
903 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
907 // Handle 32-bit sext immediates with LIS + addr mode.
908 if (CN->getValueType(0) == MVT::i32 ||
909 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
910 int Addr = (int)CN->getZExtValue();
912 // Otherwise, break this down into an LIS + disp.
913 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
915 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
916 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
917 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
922 Disp = DAG.getTargetConstant(0, getPointerTy());
923 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
924 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
927 return true; // [r+0]
930 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
931 /// represented as an indexed [r+r] operation.
932 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
934 SelectionDAG &DAG) const {
935 // Check to see if we can easily represent this as an [r+r] address. This
936 // will fail if it thinks that the address is more profitably represented as
937 // reg+imm, e.g. where imm = 0.
938 if (SelectAddressRegReg(N, Base, Index, DAG))
941 // If the operand is an addition, always emit this as [r+r], since this is
942 // better (for code size, and execution, as the memop does the add for free)
943 // than emitting an explicit add.
944 if (N.getOpcode() == ISD::ADD) {
945 Base = N.getOperand(0);
946 Index = N.getOperand(1);
950 // Otherwise, do it the hard way, using R0 as the base register.
951 Base = DAG.getRegister(PPC::R0, N.getValueType());
956 /// SelectAddressRegImmShift - Returns true if the address N can be
957 /// represented by a base register plus a signed 14-bit displacement
958 /// [r+imm*4]. Suitable for use by STD and friends.
959 bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp,
961 SelectionDAG &DAG) const {
962 // FIXME dl should come from the parent load or store, not the address
963 DebugLoc dl = N.getDebugLoc();
964 // If this can be more profitably realized as r+r, fail.
965 if (SelectAddressRegReg(N, Disp, Base, DAG))
968 if (N.getOpcode() == ISD::ADD) {
970 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
971 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
972 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
973 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
975 Base = N.getOperand(0);
977 return true; // [r+i]
978 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
979 // Match LOAD (ADD (X, Lo(G))).
980 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
981 && "Cannot handle constant offsets yet!");
982 Disp = N.getOperand(1).getOperand(0); // The global address.
983 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
984 Disp.getOpcode() == ISD::TargetConstantPool ||
985 Disp.getOpcode() == ISD::TargetJumpTable);
986 Base = N.getOperand(0);
987 return true; // [&g+r]
989 } else if (N.getOpcode() == ISD::OR) {
991 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
992 // If this is an or of disjoint bitfields, we can codegen this as an add
993 // (for better address arithmetic) if the LHS and RHS of the OR are
994 // provably disjoint.
995 APInt LHSKnownZero, LHSKnownOne;
996 DAG.ComputeMaskedBits(N.getOperand(0),
997 APInt::getAllOnesValue(N.getOperand(0)
998 .getValueSizeInBits()),
999 LHSKnownZero, LHSKnownOne);
1000 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1001 // If all of the bits are known zero on the LHS or RHS, the add won't
1003 Base = N.getOperand(0);
1004 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
1008 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1009 // Loading from a constant address. Verify low two bits are clear.
1010 if ((CN->getZExtValue() & 3) == 0) {
1011 // If this address fits entirely in a 14-bit sext immediate field, codegen
1014 if (isIntS16Immediate(CN, Imm)) {
1015 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
1016 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
1020 // Fold the low-part of 32-bit absolute addresses into addr mode.
1021 if (CN->getValueType(0) == MVT::i32 ||
1022 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
1023 int Addr = (int)CN->getZExtValue();
1025 // Otherwise, break this down into an LIS + disp.
1026 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
1027 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
1028 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1029 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base),0);
1035 Disp = DAG.getTargetConstant(0, getPointerTy());
1036 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
1037 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1040 return true; // [r+0]
1044 /// getPreIndexedAddressParts - returns true by value, base pointer and
1045 /// offset pointer and addressing mode by reference if the node's address
1046 /// can be legally represented as pre-indexed load / store address.
1047 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1049 ISD::MemIndexedMode &AM,
1050 SelectionDAG &DAG) const {
1051 // Disabled by default for now.
1052 if (!EnablePPCPreinc) return false;
1056 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1057 Ptr = LD->getBasePtr();
1058 VT = LD->getMemoryVT();
1060 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1062 Ptr = ST->getBasePtr();
1063 VT = ST->getMemoryVT();
1067 // PowerPC doesn't have preinc load/store instructions for vectors.
1071 // TODO: Check reg+reg first.
1073 // LDU/STU use reg+imm*4, others use reg+imm.
1074 if (VT != MVT::i64) {
1076 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
1080 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
1084 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1085 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1086 // sext i32 to i64 when addr mode is r+i.
1087 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1088 LD->getExtensionType() == ISD::SEXTLOAD &&
1089 isa<ConstantSDNode>(Offset))
1097 //===----------------------------------------------------------------------===//
1098 // LowerOperation implementation
1099 //===----------------------------------------------------------------------===//
1101 /// GetLabelAccessInfo - Return true if we should reference labels using a
1102 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1103 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1104 unsigned &LoOpFlags, const GlobalValue *GV = 0) {
1105 HiOpFlags = PPCII::MO_HA16;
1106 LoOpFlags = PPCII::MO_LO16;
1108 // Don't use the pic base if not in PIC relocation model. Or if we are on a
1109 // non-darwin platform. We don't support PIC on other platforms yet.
1110 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ &&
1111 TM.getSubtarget<PPCSubtarget>().isDarwin();
1113 HiOpFlags |= PPCII::MO_PIC_FLAG;
1114 LoOpFlags |= PPCII::MO_PIC_FLAG;
1117 // If this is a reference to a global value that requires a non-lazy-ptr, make
1118 // sure that instruction lowering adds it.
1119 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1120 HiOpFlags |= PPCII::MO_NLP_FLAG;
1121 LoOpFlags |= PPCII::MO_NLP_FLAG;
1123 if (GV->hasHiddenVisibility()) {
1124 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1125 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1132 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1133 SelectionDAG &DAG) {
1134 EVT PtrVT = HiPart.getValueType();
1135 SDValue Zero = DAG.getConstant(0, PtrVT);
1136 DebugLoc DL = HiPart.getDebugLoc();
1138 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1139 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1141 // With PIC, the first instruction is actually "GR+hi(&G)".
1143 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1144 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1146 // Generate non-pic code that has direct accesses to the constant pool.
1147 // The address of the global is just (hi(&g)+lo(&g)).
1148 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1151 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1152 SelectionDAG &DAG) const {
1153 EVT PtrVT = Op.getValueType();
1154 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1155 const Constant *C = CP->getConstVal();
1157 unsigned MOHiFlag, MOLoFlag;
1158 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1160 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1162 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1163 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1166 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1167 EVT PtrVT = Op.getValueType();
1168 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1170 unsigned MOHiFlag, MOLoFlag;
1171 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1172 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1173 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1174 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1177 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1178 SelectionDAG &DAG) const {
1179 EVT PtrVT = Op.getValueType();
1180 DebugLoc DL = Op.getDebugLoc();
1182 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1184 unsigned MOHiFlag, MOLoFlag;
1185 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1186 SDValue TgtBAHi = DAG.getBlockAddress(BA, PtrVT, /*isTarget=*/true, MOHiFlag);
1187 SDValue TgtBALo = DAG.getBlockAddress(BA, PtrVT, /*isTarget=*/true, MOLoFlag);
1188 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1191 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1192 SelectionDAG &DAG) const {
1193 EVT PtrVT = Op.getValueType();
1194 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1195 DebugLoc DL = GSDN->getDebugLoc();
1196 const GlobalValue *GV = GSDN->getGlobal();
1198 // 64-bit SVR4 ABI code is always position-independent.
1199 // The actual address of the GlobalValue is stored in the TOC.
1200 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1201 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1202 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1203 DAG.getRegister(PPC::X2, MVT::i64));
1206 unsigned MOHiFlag, MOLoFlag;
1207 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1210 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1212 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1214 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1216 // If the global reference is actually to a non-lazy-pointer, we have to do an
1217 // extra load to get the address of the global.
1218 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1219 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1224 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1225 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1226 DebugLoc dl = Op.getDebugLoc();
1228 // If we're comparing for equality to zero, expose the fact that this is
1229 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1230 // fold the new nodes.
1231 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1232 if (C->isNullValue() && CC == ISD::SETEQ) {
1233 EVT VT = Op.getOperand(0).getValueType();
1234 SDValue Zext = Op.getOperand(0);
1235 if (VT.bitsLT(MVT::i32)) {
1237 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1239 unsigned Log2b = Log2_32(VT.getSizeInBits());
1240 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1241 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1242 DAG.getConstant(Log2b, MVT::i32));
1243 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1245 // Leave comparisons against 0 and -1 alone for now, since they're usually
1246 // optimized. FIXME: revisit this when we can custom lower all setcc
1248 if (C->isAllOnesValue() || C->isNullValue())
1252 // If we have an integer seteq/setne, turn it into a compare against zero
1253 // by xor'ing the rhs with the lhs, which is faster than setting a
1254 // condition register, reading it back out, and masking the correct bit. The
1255 // normal approach here uses sub to do this instead of xor. Using xor exposes
1256 // the result to other bit-twiddling opportunities.
1257 EVT LHSVT = Op.getOperand(0).getValueType();
1258 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1259 EVT VT = Op.getValueType();
1260 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1262 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1267 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1268 const PPCSubtarget &Subtarget) const {
1270 llvm_unreachable("VAARG not yet implemented for the SVR4 ABI!");
1271 return SDValue(); // Not reached
1274 SDValue PPCTargetLowering::LowerTRAMPOLINE(SDValue Op,
1275 SelectionDAG &DAG) const {
1276 SDValue Chain = Op.getOperand(0);
1277 SDValue Trmp = Op.getOperand(1); // trampoline
1278 SDValue FPtr = Op.getOperand(2); // nested function
1279 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1280 DebugLoc dl = Op.getDebugLoc();
1282 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1283 bool isPPC64 = (PtrVT == MVT::i64);
1284 const Type *IntPtrTy =
1285 DAG.getTargetLoweringInfo().getTargetData()->getIntPtrType(
1288 TargetLowering::ArgListTy Args;
1289 TargetLowering::ArgListEntry Entry;
1291 Entry.Ty = IntPtrTy;
1292 Entry.Node = Trmp; Args.push_back(Entry);
1294 // TrampSize == (isPPC64 ? 48 : 40);
1295 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1296 isPPC64 ? MVT::i64 : MVT::i32);
1297 Args.push_back(Entry);
1299 Entry.Node = FPtr; Args.push_back(Entry);
1300 Entry.Node = Nest; Args.push_back(Entry);
1302 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1303 std::pair<SDValue, SDValue> CallResult =
1304 LowerCallTo(Chain, Op.getValueType().getTypeForEVT(*DAG.getContext()),
1305 false, false, false, false, 0, CallingConv::C, false,
1306 /*isReturnValueUsed=*/true,
1307 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1311 { CallResult.first, CallResult.second };
1313 return DAG.getMergeValues(Ops, 2, dl);
1316 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1317 const PPCSubtarget &Subtarget) const {
1318 MachineFunction &MF = DAG.getMachineFunction();
1319 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1321 DebugLoc dl = Op.getDebugLoc();
1323 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
1324 // vastart just stores the address of the VarArgsFrameIndex slot into the
1325 // memory location argument.
1326 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1327 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1328 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1329 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
1330 MachinePointerInfo(SV),
1334 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
1335 // We suppose the given va_list is already allocated.
1338 // char gpr; /* index into the array of 8 GPRs
1339 // * stored in the register save area
1340 // * gpr=0 corresponds to r3,
1341 // * gpr=1 to r4, etc.
1343 // char fpr; /* index into the array of 8 FPRs
1344 // * stored in the register save area
1345 // * fpr=0 corresponds to f1,
1346 // * fpr=1 to f2, etc.
1348 // char *overflow_arg_area;
1349 // /* location on stack that holds
1350 // * the next overflow argument
1352 // char *reg_save_area;
1353 // /* where r3:r10 and f1:f8 (if saved)
1359 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
1360 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
1363 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1365 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
1367 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1370 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
1371 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1373 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
1374 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1376 uint64_t FPROffset = 1;
1377 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1379 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1381 // Store first byte : number of int regs
1382 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
1384 MachinePointerInfo(SV),
1385 MVT::i8, false, false, 0);
1386 uint64_t nextOffset = FPROffset;
1387 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
1390 // Store second byte : number of float regs
1391 SDValue secondStore =
1392 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
1393 MachinePointerInfo(SV, nextOffset), MVT::i8,
1395 nextOffset += StackOffset;
1396 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
1398 // Store second word : arguments given on stack
1399 SDValue thirdStore =
1400 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
1401 MachinePointerInfo(SV, nextOffset),
1403 nextOffset += FrameOffset;
1404 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
1406 // Store third word : arguments given in registers
1407 return DAG.getStore(thirdStore, dl, FR, nextPtr,
1408 MachinePointerInfo(SV, nextOffset),
1413 #include "PPCGenCallingConv.inc"
1415 static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
1416 CCValAssign::LocInfo &LocInfo,
1417 ISD::ArgFlagsTy &ArgFlags,
1422 static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
1424 CCValAssign::LocInfo &LocInfo,
1425 ISD::ArgFlagsTy &ArgFlags,
1427 static const unsigned ArgRegs[] = {
1428 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1429 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1431 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1433 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1435 // Skip one register if the first unallocated register has an even register
1436 // number and there are still argument registers available which have not been
1437 // allocated yet. RegNum is actually an index into ArgRegs, which means we
1438 // need to skip a register if RegNum is odd.
1439 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
1440 State.AllocateReg(ArgRegs[RegNum]);
1443 // Always return false here, as this function only makes sure that the first
1444 // unallocated register has an odd register number and does not actually
1445 // allocate a register for the current argument.
1449 static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
1451 CCValAssign::LocInfo &LocInfo,
1452 ISD::ArgFlagsTy &ArgFlags,
1454 static const unsigned ArgRegs[] = {
1455 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1459 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1461 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1463 // If there is only one Floating-point register left we need to put both f64
1464 // values of a split ppc_fp128 value on the stack.
1465 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
1466 State.AllocateReg(ArgRegs[RegNum]);
1469 // Always return false here, as this function only makes sure that the two f64
1470 // values a ppc_fp128 value is split into are both passed in registers or both
1471 // passed on the stack and does not actually allocate a register for the
1472 // current argument.
1476 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1478 static const unsigned *GetFPR() {
1479 static const unsigned FPR[] = {
1480 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1481 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1487 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
1489 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
1490 unsigned PtrByteSize) {
1491 unsigned ArgSize = ArgVT.getSizeInBits()/8;
1492 if (Flags.isByVal())
1493 ArgSize = Flags.getByValSize();
1494 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1500 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
1501 CallingConv::ID CallConv, bool isVarArg,
1502 const SmallVectorImpl<ISD::InputArg>
1504 DebugLoc dl, SelectionDAG &DAG,
1505 SmallVectorImpl<SDValue> &InVals)
1507 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) {
1508 return LowerFormalArguments_SVR4(Chain, CallConv, isVarArg, Ins,
1511 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
1517 PPCTargetLowering::LowerFormalArguments_SVR4(
1519 CallingConv::ID CallConv, bool isVarArg,
1520 const SmallVectorImpl<ISD::InputArg>
1522 DebugLoc dl, SelectionDAG &DAG,
1523 SmallVectorImpl<SDValue> &InVals) const {
1525 // 32-bit SVR4 ABI Stack Frame Layout:
1526 // +-----------------------------------+
1527 // +--> | Back chain |
1528 // | +-----------------------------------+
1529 // | | Floating-point register save area |
1530 // | +-----------------------------------+
1531 // | | General register save area |
1532 // | +-----------------------------------+
1533 // | | CR save word |
1534 // | +-----------------------------------+
1535 // | | VRSAVE save word |
1536 // | +-----------------------------------+
1537 // | | Alignment padding |
1538 // | +-----------------------------------+
1539 // | | Vector register save area |
1540 // | +-----------------------------------+
1541 // | | Local variable space |
1542 // | +-----------------------------------+
1543 // | | Parameter list area |
1544 // | +-----------------------------------+
1545 // | | LR save word |
1546 // | +-----------------------------------+
1547 // SP--> +--- | Back chain |
1548 // +-----------------------------------+
1551 // System V Application Binary Interface PowerPC Processor Supplement
1552 // AltiVec Technology Programming Interface Manual
1554 MachineFunction &MF = DAG.getMachineFunction();
1555 MachineFrameInfo *MFI = MF.getFrameInfo();
1556 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1558 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1559 // Potential tail calls could cause overwriting of argument stack slots.
1560 bool isImmutable = !(GuaranteedTailCallOpt && (CallConv==CallingConv::Fast));
1561 unsigned PtrByteSize = 4;
1563 // Assign locations to all of the incoming arguments.
1564 SmallVector<CCValAssign, 16> ArgLocs;
1565 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1568 // Reserve space for the linkage area on the stack.
1569 CCInfo.AllocateStack(PPCFrameInfo::getLinkageSize(false, false), PtrByteSize);
1571 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4);
1573 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1574 CCValAssign &VA = ArgLocs[i];
1576 // Arguments stored in registers.
1577 if (VA.isRegLoc()) {
1578 TargetRegisterClass *RC;
1579 EVT ValVT = VA.getValVT();
1581 switch (ValVT.getSimpleVT().SimpleTy) {
1583 llvm_unreachable("ValVT not supported by formal arguments Lowering");
1585 RC = PPC::GPRCRegisterClass;
1588 RC = PPC::F4RCRegisterClass;
1591 RC = PPC::F8RCRegisterClass;
1597 RC = PPC::VRRCRegisterClass;
1601 // Transform the arguments stored in physical registers into virtual ones.
1602 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1603 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT);
1605 InVals.push_back(ArgValue);
1607 // Argument stored in memory.
1608 assert(VA.isMemLoc());
1610 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
1611 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
1614 // Create load nodes to retrieve arguments from the stack.
1615 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1616 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
1617 MachinePointerInfo(),
1622 // Assign locations to all of the incoming aggregate by value arguments.
1623 // Aggregates passed by value are stored in the local variable space of the
1624 // caller's stack frame, right above the parameter list area.
1625 SmallVector<CCValAssign, 16> ByValArgLocs;
1626 CCState CCByValInfo(CallConv, isVarArg, getTargetMachine(),
1627 ByValArgLocs, *DAG.getContext());
1629 // Reserve stack space for the allocations in CCInfo.
1630 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
1632 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4_ByVal);
1634 // Area that is at least reserved in the caller of this function.
1635 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
1637 // Set the size that is at least reserved in caller of this function. Tail
1638 // call optimized function's reserved stack space needs to be aligned so that
1639 // taking the difference between two stack areas will result in an aligned
1641 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1644 std::max(MinReservedArea,
1645 PPCFrameInfo::getMinCallFrameSize(false, false));
1647 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
1648 getStackAlignment();
1649 unsigned AlignMask = TargetAlign-1;
1650 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
1652 FI->setMinReservedArea(MinReservedArea);
1654 SmallVector<SDValue, 8> MemOps;
1656 // If the function takes variable number of arguments, make a frame index for
1657 // the start of the first vararg value... for expansion of llvm.va_start.
1659 static const unsigned GPArgRegs[] = {
1660 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1661 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1663 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
1665 static const unsigned FPArgRegs[] = {
1666 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1669 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
1671 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
1673 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
1676 // Make room for NumGPArgRegs and NumFPArgRegs.
1677 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
1678 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
1680 FuncInfo->setVarArgsStackOffset(
1681 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
1682 CCInfo.getNextStackOffset(), true));
1684 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
1685 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1687 // The fixed integer arguments of a variadic function are stored to the
1688 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
1689 // the result of va_next.
1690 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
1691 // Get an existing live-in vreg, or add a new one.
1692 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
1694 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
1696 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
1697 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
1698 MachinePointerInfo(), false, false, 0);
1699 MemOps.push_back(Store);
1700 // Increment the address by four for the next argument to store
1701 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
1702 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1705 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
1707 // The double arguments are stored to the VarArgsFrameIndex
1709 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
1710 // Get an existing live-in vreg, or add a new one.
1711 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
1713 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
1715 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
1716 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
1717 MachinePointerInfo(), false, false, 0);
1718 MemOps.push_back(Store);
1719 // Increment the address by eight for the next argument to store
1720 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
1722 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1726 if (!MemOps.empty())
1727 Chain = DAG.getNode(ISD::TokenFactor, dl,
1728 MVT::Other, &MemOps[0], MemOps.size());
1734 PPCTargetLowering::LowerFormalArguments_Darwin(
1736 CallingConv::ID CallConv, bool isVarArg,
1737 const SmallVectorImpl<ISD::InputArg>
1739 DebugLoc dl, SelectionDAG &DAG,
1740 SmallVectorImpl<SDValue> &InVals) const {
1741 // TODO: add description of PPC stack frame format, or at least some docs.
1743 MachineFunction &MF = DAG.getMachineFunction();
1744 MachineFrameInfo *MFI = MF.getFrameInfo();
1745 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1747 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1748 bool isPPC64 = PtrVT == MVT::i64;
1749 // Potential tail calls could cause overwriting of argument stack slots.
1750 bool isImmutable = !(GuaranteedTailCallOpt && (CallConv==CallingConv::Fast));
1751 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1753 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, true);
1754 // Area that is at least reserved in caller of this function.
1755 unsigned MinReservedArea = ArgOffset;
1757 static const unsigned GPR_32[] = { // 32-bit registers.
1758 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1759 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1761 static const unsigned GPR_64[] = { // 64-bit registers.
1762 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1763 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1766 static const unsigned *FPR = GetFPR();
1768 static const unsigned VR[] = {
1769 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1770 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1773 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
1774 const unsigned Num_FPR_Regs = 13;
1775 const unsigned Num_VR_Regs = array_lengthof( VR);
1777 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1779 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1781 // In 32-bit non-varargs functions, the stack space for vectors is after the
1782 // stack space for non-vectors. We do not use this space unless we have
1783 // too many vectors to fit in registers, something that only occurs in
1784 // constructed examples:), but we have to walk the arglist to figure
1785 // that out...for the pathological case, compute VecArgOffset as the
1786 // start of the vector parameter area. Computing VecArgOffset is the
1787 // entire point of the following loop.
1788 unsigned VecArgOffset = ArgOffset;
1789 if (!isVarArg && !isPPC64) {
1790 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
1792 EVT ObjectVT = Ins[ArgNo].VT;
1793 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
1794 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
1796 if (Flags.isByVal()) {
1797 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
1798 ObjSize = Flags.getByValSize();
1800 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1801 VecArgOffset += ArgSize;
1805 switch(ObjectVT.getSimpleVT().SimpleTy) {
1806 default: llvm_unreachable("Unhandled argument type!");
1809 VecArgOffset += isPPC64 ? 8 : 4;
1811 case MVT::i64: // PPC64
1819 // Nothing to do, we're only looking at Nonvector args here.
1824 // We've found where the vector parameter area in memory is. Skip the
1825 // first 12 parameters; these don't use that memory.
1826 VecArgOffset = ((VecArgOffset+15)/16)*16;
1827 VecArgOffset += 12*16;
1829 // Add DAG nodes to load the arguments or copy them out of registers. On
1830 // entry to a function on PPC, the arguments start after the linkage area,
1831 // although the first ones are often in registers.
1833 SmallVector<SDValue, 8> MemOps;
1834 unsigned nAltivecParamsAtEnd = 0;
1835 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
1837 bool needsLoad = false;
1838 EVT ObjectVT = Ins[ArgNo].VT;
1839 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
1840 unsigned ArgSize = ObjSize;
1841 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
1843 unsigned CurArgOffset = ArgOffset;
1845 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
1846 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
1847 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
1848 if (isVarArg || isPPC64) {
1849 MinReservedArea = ((MinReservedArea+15)/16)*16;
1850 MinReservedArea += CalculateStackSlotSize(ObjectVT,
1853 } else nAltivecParamsAtEnd++;
1855 // Calculate min reserved area.
1856 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
1860 // FIXME the codegen can be much improved in some cases.
1861 // We do not have to keep everything in memory.
1862 if (Flags.isByVal()) {
1863 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
1864 ObjSize = Flags.getByValSize();
1865 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1866 // Objects of size 1 and 2 are right justified, everything else is
1867 // left justified. This means the memory address is adjusted forwards.
1868 if (ObjSize==1 || ObjSize==2) {
1869 CurArgOffset = CurArgOffset + (4 - ObjSize);
1871 // The value of the object is its address.
1872 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
1873 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1874 InVals.push_back(FIN);
1875 if (ObjSize==1 || ObjSize==2) {
1876 if (GPR_idx != Num_GPR_Regs) {
1877 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
1878 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
1879 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
1880 MachinePointerInfo(),
1881 ObjSize==1 ? MVT::i8 : MVT::i16,
1883 MemOps.push_back(Store);
1887 ArgOffset += PtrByteSize;
1891 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
1892 // Store whatever pieces of the object are in registers
1893 // to memory. ArgVal will be address of the beginning of
1895 if (GPR_idx != Num_GPR_Regs) {
1896 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
1897 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
1898 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1899 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
1900 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
1901 MachinePointerInfo(),
1903 MemOps.push_back(Store);
1905 ArgOffset += PtrByteSize;
1907 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
1914 switch (ObjectVT.getSimpleVT().SimpleTy) {
1915 default: llvm_unreachable("Unhandled argument type!");
1918 if (GPR_idx != Num_GPR_Regs) {
1919 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
1920 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
1924 ArgSize = PtrByteSize;
1926 // All int arguments reserve stack space in the Darwin ABI.
1927 ArgOffset += PtrByteSize;
1931 case MVT::i64: // PPC64
1932 if (GPR_idx != Num_GPR_Regs) {
1933 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
1934 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1936 if (ObjectVT == MVT::i32) {
1937 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
1938 // value to MVT::i64 and then truncate to the correct register size.
1940 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
1941 DAG.getValueType(ObjectVT));
1942 else if (Flags.isZExt())
1943 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
1944 DAG.getValueType(ObjectVT));
1946 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
1952 ArgSize = PtrByteSize;
1954 // All int arguments reserve stack space in the Darwin ABI.
1960 // Every 4 bytes of argument space consumes one of the GPRs available for
1961 // argument passing.
1962 if (GPR_idx != Num_GPR_Regs) {
1964 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
1967 if (FPR_idx != Num_FPR_Regs) {
1970 if (ObjectVT == MVT::f32)
1971 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
1973 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
1975 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
1981 // All FP arguments reserve stack space in the Darwin ABI.
1982 ArgOffset += isPPC64 ? 8 : ObjSize;
1988 // Note that vector arguments in registers don't reserve stack space,
1989 // except in varargs functions.
1990 if (VR_idx != Num_VR_Regs) {
1991 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
1992 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
1994 while ((ArgOffset % 16) != 0) {
1995 ArgOffset += PtrByteSize;
1996 if (GPR_idx != Num_GPR_Regs)
2000 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2004 if (!isVarArg && !isPPC64) {
2005 // Vectors go after all the nonvectors.
2006 CurArgOffset = VecArgOffset;
2009 // Vectors are aligned.
2010 ArgOffset = ((ArgOffset+15)/16)*16;
2011 CurArgOffset = ArgOffset;
2019 // We need to load the argument to a virtual register if we determined above
2020 // that we ran out of physical registers of the appropriate type.
2022 int FI = MFI->CreateFixedObject(ObjSize,
2023 CurArgOffset + (ArgSize - ObjSize),
2025 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2026 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2030 InVals.push_back(ArgVal);
2033 // Set the size that is at least reserved in caller of this function. Tail
2034 // call optimized function's reserved stack space needs to be aligned so that
2035 // taking the difference between two stack areas will result in an aligned
2037 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2038 // Add the Altivec parameters at the end, if needed.
2039 if (nAltivecParamsAtEnd) {
2040 MinReservedArea = ((MinReservedArea+15)/16)*16;
2041 MinReservedArea += 16*nAltivecParamsAtEnd;
2044 std::max(MinReservedArea,
2045 PPCFrameInfo::getMinCallFrameSize(isPPC64, true));
2046 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
2047 getStackAlignment();
2048 unsigned AlignMask = TargetAlign-1;
2049 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2050 FI->setMinReservedArea(MinReservedArea);
2052 // If the function takes variable number of arguments, make a frame index for
2053 // the start of the first vararg value... for expansion of llvm.va_start.
2055 int Depth = ArgOffset;
2057 FuncInfo->setVarArgsFrameIndex(
2058 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2060 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2062 // If this function is vararg, store any remaining integer argument regs
2063 // to their spots on the stack so that they may be loaded by deferencing the
2064 // result of va_next.
2065 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2069 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2071 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2073 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2074 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2075 MachinePointerInfo(), false, false, 0);
2076 MemOps.push_back(Store);
2077 // Increment the address by four for the next argument to store
2078 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2079 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2083 if (!MemOps.empty())
2084 Chain = DAG.getNode(ISD::TokenFactor, dl,
2085 MVT::Other, &MemOps[0], MemOps.size());
2090 /// CalculateParameterAndLinkageAreaSize - Get the size of the paramter plus
2091 /// linkage area for the Darwin ABI.
2093 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
2097 const SmallVectorImpl<ISD::OutputArg>
2099 const SmallVectorImpl<SDValue> &OutVals,
2100 unsigned &nAltivecParamsAtEnd) {
2101 // Count how many bytes are to be pushed on the stack, including the linkage
2102 // area, and parameter passing area. We start with 24/48 bytes, which is
2103 // prereserved space for [SP][CR][LR][3 x unused].
2104 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, true);
2105 unsigned NumOps = Outs.size();
2106 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2108 // Add up all the space actually used.
2109 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
2110 // they all go in registers, but we must reserve stack space for them for
2111 // possible use by the caller. In varargs or 64-bit calls, parameters are
2112 // assigned stack space in order, with padding so Altivec parameters are
2114 nAltivecParamsAtEnd = 0;
2115 for (unsigned i = 0; i != NumOps; ++i) {
2116 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2117 EVT ArgVT = Outs[i].VT;
2118 // Varargs Altivec parameters are padded to a 16 byte boundary.
2119 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
2120 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
2121 if (!isVarArg && !isPPC64) {
2122 // Non-varargs Altivec parameters go after all the non-Altivec
2123 // parameters; handle those later so we know how much padding we need.
2124 nAltivecParamsAtEnd++;
2127 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
2128 NumBytes = ((NumBytes+15)/16)*16;
2130 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2133 // Allow for Altivec parameters at the end, if needed.
2134 if (nAltivecParamsAtEnd) {
2135 NumBytes = ((NumBytes+15)/16)*16;
2136 NumBytes += 16*nAltivecParamsAtEnd;
2139 // The prolog code of the callee may store up to 8 GPR argument registers to
2140 // the stack, allowing va_start to index over them in memory if its varargs.
2141 // Because we cannot tell if this is needed on the caller side, we have to
2142 // conservatively assume that it is needed. As such, make sure we have at
2143 // least enough stack space for the caller to store the 8 GPRs.
2144 NumBytes = std::max(NumBytes,
2145 PPCFrameInfo::getMinCallFrameSize(isPPC64, true));
2147 // Tail call needs the stack to be aligned.
2148 if (CC==CallingConv::Fast && GuaranteedTailCallOpt) {
2149 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
2150 getStackAlignment();
2151 unsigned AlignMask = TargetAlign-1;
2152 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2158 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
2159 /// adjusted to accomodate the arguments for the tailcall.
2160 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
2161 unsigned ParamSize) {
2163 if (!isTailCall) return 0;
2165 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
2166 unsigned CallerMinReservedArea = FI->getMinReservedArea();
2167 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
2168 // Remember only if the new adjustement is bigger.
2169 if (SPDiff < FI->getTailCallSPDelta())
2170 FI->setTailCallSPDelta(SPDiff);
2175 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2176 /// for tail call optimization. Targets which want to do tail call
2177 /// optimization should implement this function.
2179 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2180 CallingConv::ID CalleeCC,
2182 const SmallVectorImpl<ISD::InputArg> &Ins,
2183 SelectionDAG& DAG) const {
2184 if (!GuaranteedTailCallOpt)
2187 // Variable argument functions are not supported.
2191 MachineFunction &MF = DAG.getMachineFunction();
2192 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
2193 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
2194 // Functions containing by val parameters are not supported.
2195 for (unsigned i = 0; i != Ins.size(); i++) {
2196 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2197 if (Flags.isByVal()) return false;
2200 // Non PIC/GOT tail calls are supported.
2201 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
2204 // At the moment we can only do local tail calls (in same module, hidden
2205 // or protected) if we are generating PIC.
2206 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2207 return G->getGlobal()->hasHiddenVisibility()
2208 || G->getGlobal()->hasProtectedVisibility();
2214 /// isCallCompatibleAddress - Return the immediate to use if the specified
2215 /// 32-bit value is representable in the immediate field of a BxA instruction.
2216 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
2217 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2220 int Addr = C->getZExtValue();
2221 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
2222 (Addr << 6 >> 6) != Addr)
2223 return 0; // Top 6 bits have to be sext of immediate.
2225 return DAG.getConstant((int)C->getZExtValue() >> 2,
2226 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
2231 struct TailCallArgumentInfo {
2236 TailCallArgumentInfo() : FrameIdx(0) {}
2241 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
2243 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
2245 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs,
2246 SmallVector<SDValue, 8> &MemOpChains,
2248 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
2249 SDValue Arg = TailCallArgs[i].Arg;
2250 SDValue FIN = TailCallArgs[i].FrameIdxOp;
2251 int FI = TailCallArgs[i].FrameIdx;
2252 // Store relative to framepointer.
2253 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
2254 MachinePointerInfo::getFixedStack(FI),
2259 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
2260 /// the appropriate stack slot for the tail call optimized function call.
2261 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
2262 MachineFunction &MF,
2271 // Calculate the new stack slot for the return address.
2272 int SlotSize = isPPC64 ? 8 : 4;
2273 int NewRetAddrLoc = SPDiff + PPCFrameInfo::getReturnSaveOffset(isPPC64,
2275 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
2276 NewRetAddrLoc, true);
2277 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2278 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
2279 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
2280 MachinePointerInfo::getFixedStack(NewRetAddr),
2283 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
2284 // slot as the FP is never overwritten.
2287 SPDiff + PPCFrameInfo::getFramePointerSaveOffset(isPPC64, isDarwinABI);
2288 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
2290 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
2291 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
2292 MachinePointerInfo::getFixedStack(NewFPIdx),
2299 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
2300 /// the position of the argument.
2302 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
2303 SDValue Arg, int SPDiff, unsigned ArgOffset,
2304 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
2305 int Offset = ArgOffset + SPDiff;
2306 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
2307 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2308 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2309 SDValue FIN = DAG.getFrameIndex(FI, VT);
2310 TailCallArgumentInfo Info;
2312 Info.FrameIdxOp = FIN;
2314 TailCallArguments.push_back(Info);
2317 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
2318 /// stack slot. Returns the chain as result and the loaded frame pointers in
2319 /// LROpOut/FPOpout. Used when tail calling.
2320 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
2326 DebugLoc dl) const {
2328 // Load the LR and FP stack slot for later adjusting.
2329 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
2330 LROpOut = getReturnAddrFrameIndex(DAG);
2331 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
2333 Chain = SDValue(LROpOut.getNode(), 1);
2335 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
2336 // slot as the FP is never overwritten.
2338 FPOpOut = getFramePointerFrameIndex(DAG);
2339 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
2341 Chain = SDValue(FPOpOut.getNode(), 1);
2347 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2348 /// by "Src" to address "Dst" of size "Size". Alignment information is
2349 /// specified by the specific parameter attribute. The copy will be passed as
2350 /// a byval function parameter.
2351 /// Sometimes what we are copying is the end of a larger object, the part that
2352 /// does not fit in registers.
2354 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2355 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2357 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2358 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2359 false, false, MachinePointerInfo(0),
2360 MachinePointerInfo(0));
2363 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
2366 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
2367 SDValue Arg, SDValue PtrOff, int SPDiff,
2368 unsigned ArgOffset, bool isPPC64, bool isTailCall,
2369 bool isVector, SmallVector<SDValue, 8> &MemOpChains,
2370 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments,
2372 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2377 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
2379 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2380 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
2381 DAG.getConstant(ArgOffset, PtrVT));
2383 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
2384 MachinePointerInfo(), false, false, 0));
2385 // Calculate and remember argument location.
2386 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
2391 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
2392 DebugLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
2393 SDValue LROp, SDValue FPOp, bool isDarwinABI,
2394 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments) {
2395 MachineFunction &MF = DAG.getMachineFunction();
2397 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
2398 // might overwrite each other in case of tail call optimization.
2399 SmallVector<SDValue, 8> MemOpChains2;
2400 // Do not flag preceeding copytoreg stuff together with the following stuff.
2402 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
2404 if (!MemOpChains2.empty())
2405 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2406 &MemOpChains2[0], MemOpChains2.size());
2408 // Store the return address to the appropriate stack slot.
2409 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
2410 isPPC64, isDarwinABI, dl);
2412 // Emit callseq_end just before tailcall node.
2413 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2414 DAG.getIntPtrConstant(0, true), InFlag);
2415 InFlag = Chain.getValue(1);
2419 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
2420 SDValue &Chain, DebugLoc dl, int SPDiff, bool isTailCall,
2421 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
2422 SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys,
2423 const PPCSubtarget &PPCSubTarget) {
2425 bool isPPC64 = PPCSubTarget.isPPC64();
2426 bool isSVR4ABI = PPCSubTarget.isSVR4ABI();
2428 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2429 NodeTys.push_back(MVT::Other); // Returns a chain
2430 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
2432 unsigned CallOpc = isSVR4ABI ? PPCISD::CALL_SVR4 : PPCISD::CALL_Darwin;
2434 bool needIndirectCall = true;
2435 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
2436 // If this is an absolute destination address, use the munged value.
2437 Callee = SDValue(Dest, 0);
2438 needIndirectCall = false;
2441 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2442 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201
2443 // Use indirect calls for ALL functions calls in JIT mode, since the
2444 // far-call stubs may be outside relocation limits for a BL instruction.
2445 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
2446 unsigned OpFlags = 0;
2447 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
2448 PPCSubTarget.getDarwinVers() < 9 &&
2449 (G->getGlobal()->isDeclaration() ||
2450 G->getGlobal()->isWeakForLinker())) {
2451 // PC-relative references to external symbols should go through $stub,
2452 // unless we're building with the leopard linker or later, which
2453 // automatically synthesizes these stubs.
2454 OpFlags = PPCII::MO_DARWIN_STUB;
2457 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
2458 // every direct call is) turn it into a TargetGlobalAddress /
2459 // TargetExternalSymbol node so that legalize doesn't hack it.
2460 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
2461 Callee.getValueType(),
2463 needIndirectCall = false;
2467 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2468 unsigned char OpFlags = 0;
2470 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
2471 PPCSubTarget.getDarwinVers() < 9) {
2472 // PC-relative references to external symbols should go through $stub,
2473 // unless we're building with the leopard linker or later, which
2474 // automatically synthesizes these stubs.
2475 OpFlags = PPCII::MO_DARWIN_STUB;
2478 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
2480 needIndirectCall = false;
2483 if (needIndirectCall) {
2484 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
2485 // to do the call, we can't use PPCISD::CALL.
2486 SDValue MTCTROps[] = {Chain, Callee, InFlag};
2488 if (isSVR4ABI && isPPC64) {
2489 // Function pointers in the 64-bit SVR4 ABI do not point to the function
2490 // entry point, but to the function descriptor (the function entry point
2491 // address is part of the function descriptor though).
2492 // The function descriptor is a three doubleword structure with the
2493 // following fields: function entry point, TOC base address and
2494 // environment pointer.
2495 // Thus for a call through a function pointer, the following actions need
2497 // 1. Save the TOC of the caller in the TOC save area of its stack
2498 // frame (this is done in LowerCall_Darwin()).
2499 // 2. Load the address of the function entry point from the function
2501 // 3. Load the TOC of the callee from the function descriptor into r2.
2502 // 4. Load the environment pointer from the function descriptor into
2504 // 5. Branch to the function entry point address.
2505 // 6. On return of the callee, the TOC of the caller needs to be
2506 // restored (this is done in FinishCall()).
2508 // All those operations are flagged together to ensure that no other
2509 // operations can be scheduled in between. E.g. without flagging the
2510 // operations together, a TOC access in the caller could be scheduled
2511 // between the load of the callee TOC and the branch to the callee, which
2512 // results in the TOC access going through the TOC of the callee instead
2513 // of going through the TOC of the caller, which leads to incorrect code.
2515 // Load the address of the function entry point from the function
2517 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Flag);
2518 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps,
2519 InFlag.getNode() ? 3 : 2);
2520 Chain = LoadFuncPtr.getValue(1);
2521 InFlag = LoadFuncPtr.getValue(2);
2523 // Load environment pointer into r11.
2524 // Offset of the environment pointer within the function descriptor.
2525 SDValue PtrOff = DAG.getIntPtrConstant(16);
2527 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
2528 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
2530 Chain = LoadEnvPtr.getValue(1);
2531 InFlag = LoadEnvPtr.getValue(2);
2533 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
2535 Chain = EnvVal.getValue(0);
2536 InFlag = EnvVal.getValue(1);
2538 // Load TOC of the callee into r2. We are using a target-specific load
2539 // with r2 hard coded, because the result of a target-independent load
2540 // would never go directly into r2, since r2 is a reserved register (which
2541 // prevents the register allocator from allocating it), resulting in an
2542 // additional register being allocated and an unnecessary move instruction
2544 VTs = DAG.getVTList(MVT::Other, MVT::Flag);
2545 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
2547 Chain = LoadTOCPtr.getValue(0);
2548 InFlag = LoadTOCPtr.getValue(1);
2550 MTCTROps[0] = Chain;
2551 MTCTROps[1] = LoadFuncPtr;
2552 MTCTROps[2] = InFlag;
2555 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps,
2556 2 + (InFlag.getNode() != 0));
2557 InFlag = Chain.getValue(1);
2560 NodeTys.push_back(MVT::Other);
2561 NodeTys.push_back(MVT::Flag);
2562 Ops.push_back(Chain);
2563 CallOpc = isSVR4ABI ? PPCISD::BCTRL_SVR4 : PPCISD::BCTRL_Darwin;
2565 // Add CTR register as callee so a bctr can be emitted later.
2567 Ops.push_back(DAG.getRegister(PPC::CTR, PtrVT));
2570 // If this is a direct call, pass the chain and the callee.
2571 if (Callee.getNode()) {
2572 Ops.push_back(Chain);
2573 Ops.push_back(Callee);
2575 // If this is a tail call add stack pointer delta.
2577 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
2579 // Add argument registers to the end of the list so that they are known live
2581 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2582 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2583 RegsToPass[i].second.getValueType()));
2589 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2590 CallingConv::ID CallConv, bool isVarArg,
2591 const SmallVectorImpl<ISD::InputArg> &Ins,
2592 DebugLoc dl, SelectionDAG &DAG,
2593 SmallVectorImpl<SDValue> &InVals) const {
2595 SmallVector<CCValAssign, 16> RVLocs;
2596 CCState CCRetInfo(CallConv, isVarArg, getTargetMachine(),
2597 RVLocs, *DAG.getContext());
2598 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
2600 // Copy all of the result registers out of their specified physreg.
2601 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2602 CCValAssign &VA = RVLocs[i];
2603 EVT VT = VA.getValVT();
2604 assert(VA.isRegLoc() && "Can only return in registers!");
2605 Chain = DAG.getCopyFromReg(Chain, dl,
2606 VA.getLocReg(), VT, InFlag).getValue(1);
2607 InVals.push_back(Chain.getValue(0));
2608 InFlag = Chain.getValue(2);
2615 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, DebugLoc dl,
2616 bool isTailCall, bool isVarArg,
2618 SmallVector<std::pair<unsigned, SDValue>, 8>
2620 SDValue InFlag, SDValue Chain,
2622 int SPDiff, unsigned NumBytes,
2623 const SmallVectorImpl<ISD::InputArg> &Ins,
2624 SmallVectorImpl<SDValue> &InVals) const {
2625 std::vector<EVT> NodeTys;
2626 SmallVector<SDValue, 8> Ops;
2627 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
2628 isTailCall, RegsToPass, Ops, NodeTys,
2631 // When performing tail call optimization the callee pops its arguments off
2632 // the stack. Account for this here so these bytes can be pushed back on in
2633 // PPCRegisterInfo::eliminateCallFramePseudoInstr.
2634 int BytesCalleePops =
2635 (CallConv==CallingConv::Fast && GuaranteedTailCallOpt) ? NumBytes : 0;
2637 if (InFlag.getNode())
2638 Ops.push_back(InFlag);
2642 // If this is the first return lowered for this function, add the regs
2643 // to the liveout set for the function.
2644 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
2645 SmallVector<CCValAssign, 16> RVLocs;
2646 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
2648 CCInfo.AnalyzeCallResult(Ins, RetCC_PPC);
2649 for (unsigned i = 0; i != RVLocs.size(); ++i)
2650 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
2653 assert(((Callee.getOpcode() == ISD::Register &&
2654 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
2655 Callee.getOpcode() == ISD::TargetExternalSymbol ||
2656 Callee.getOpcode() == ISD::TargetGlobalAddress ||
2657 isa<ConstantSDNode>(Callee)) &&
2658 "Expecting an global address, external symbol, absolute value or register");
2660 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size());
2663 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
2664 InFlag = Chain.getValue(1);
2666 // Add a NOP immediately after the branch instruction when using the 64-bit
2667 // SVR4 ABI. At link time, if caller and callee are in a different module and
2668 // thus have a different TOC, the call will be replaced with a call to a stub
2669 // function which saves the current TOC, loads the TOC of the callee and
2670 // branches to the callee. The NOP will be replaced with a load instruction
2671 // which restores the TOC of the caller from the TOC save slot of the current
2672 // stack frame. If caller and callee belong to the same module (and have the
2673 // same TOC), the NOP will remain unchanged.
2674 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) {
2675 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Flag);
2676 if (CallOpc == PPCISD::BCTRL_SVR4) {
2677 // This is a call through a function pointer.
2678 // Restore the caller TOC from the save area into R2.
2679 // See PrepareCall() for more information about calls through function
2680 // pointers in the 64-bit SVR4 ABI.
2681 // We are using a target-specific load with r2 hard coded, because the
2682 // result of a target-independent load would never go directly into r2,
2683 // since r2 is a reserved register (which prevents the register allocator
2684 // from allocating it), resulting in an additional register being
2685 // allocated and an unnecessary move instruction being generated.
2686 Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag);
2687 InFlag = Chain.getValue(1);
2689 // Otherwise insert NOP.
2690 InFlag = DAG.getNode(PPCISD::NOP, dl, MVT::Flag, InFlag);
2694 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2695 DAG.getIntPtrConstant(BytesCalleePops, true),
2698 InFlag = Chain.getValue(1);
2700 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2701 Ins, dl, DAG, InVals);
2705 PPCTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
2706 CallingConv::ID CallConv, bool isVarArg,
2708 const SmallVectorImpl<ISD::OutputArg> &Outs,
2709 const SmallVectorImpl<SDValue> &OutVals,
2710 const SmallVectorImpl<ISD::InputArg> &Ins,
2711 DebugLoc dl, SelectionDAG &DAG,
2712 SmallVectorImpl<SDValue> &InVals) const {
2714 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
2717 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64())
2718 return LowerCall_SVR4(Chain, Callee, CallConv, isVarArg,
2719 isTailCall, Outs, OutVals, Ins,
2722 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
2723 isTailCall, Outs, OutVals, Ins,
2728 PPCTargetLowering::LowerCall_SVR4(SDValue Chain, SDValue Callee,
2729 CallingConv::ID CallConv, bool isVarArg,
2731 const SmallVectorImpl<ISD::OutputArg> &Outs,
2732 const SmallVectorImpl<SDValue> &OutVals,
2733 const SmallVectorImpl<ISD::InputArg> &Ins,
2734 DebugLoc dl, SelectionDAG &DAG,
2735 SmallVectorImpl<SDValue> &InVals) const {
2736 // See PPCTargetLowering::LowerFormalArguments_SVR4() for a description
2737 // of the 32-bit SVR4 ABI stack frame layout.
2739 assert((CallConv == CallingConv::C ||
2740 CallConv == CallingConv::Fast) && "Unknown calling convention!");
2742 unsigned PtrByteSize = 4;
2744 MachineFunction &MF = DAG.getMachineFunction();
2746 // Mark this function as potentially containing a function that contains a
2747 // tail call. As a consequence the frame pointer will be used for dynamicalloc
2748 // and restoring the callers stack pointer in this functions epilog. This is
2749 // done because by tail calling the called function might overwrite the value
2750 // in this function's (MF) stack pointer stack slot 0(SP).
2751 if (GuaranteedTailCallOpt && CallConv==CallingConv::Fast)
2752 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
2754 // Count how many bytes are to be pushed on the stack, including the linkage
2755 // area, parameter list area and the part of the local variable space which
2756 // contains copies of aggregates which are passed by value.
2758 // Assign locations to all of the outgoing arguments.
2759 SmallVector<CCValAssign, 16> ArgLocs;
2760 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
2761 ArgLocs, *DAG.getContext());
2763 // Reserve space for the linkage area on the stack.
2764 CCInfo.AllocateStack(PPCFrameInfo::getLinkageSize(false, false), PtrByteSize);
2767 // Handle fixed and variable vector arguments differently.
2768 // Fixed vector arguments go into registers as long as registers are
2769 // available. Variable vector arguments always go into memory.
2770 unsigned NumArgs = Outs.size();
2772 for (unsigned i = 0; i != NumArgs; ++i) {
2773 MVT ArgVT = Outs[i].VT;
2774 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2777 if (Outs[i].IsFixed) {
2778 Result = CC_PPC_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
2781 Result = CC_PPC_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
2787 errs() << "Call operand #" << i << " has unhandled type "
2788 << EVT(ArgVT).getEVTString() << "\n";
2790 llvm_unreachable(0);
2794 // All arguments are treated the same.
2795 CCInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4);
2798 // Assign locations to all of the outgoing aggregate by value arguments.
2799 SmallVector<CCValAssign, 16> ByValArgLocs;
2800 CCState CCByValInfo(CallConv, isVarArg, getTargetMachine(), ByValArgLocs,
2803 // Reserve stack space for the allocations in CCInfo.
2804 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2806 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4_ByVal);
2808 // Size of the linkage area, parameter list area and the part of the local
2809 // space variable where copies of aggregates which are passed by value are
2811 unsigned NumBytes = CCByValInfo.getNextStackOffset();
2813 // Calculate by how many bytes the stack has to be adjusted in case of tail
2814 // call optimization.
2815 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
2817 // Adjust the stack pointer for the new arguments...
2818 // These operations are automatically eliminated by the prolog/epilog pass
2819 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2820 SDValue CallSeqStart = Chain;
2822 // Load the return address and frame pointer so it can be moved somewhere else
2825 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
2828 // Set up a copy of the stack pointer for use loading and storing any
2829 // arguments that may not fit in the registers available for argument
2831 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2833 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2834 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
2835 SmallVector<SDValue, 8> MemOpChains;
2837 // Walk the register/memloc assignments, inserting copies/loads.
2838 for (unsigned i = 0, j = 0, e = ArgLocs.size();
2841 CCValAssign &VA = ArgLocs[i];
2842 SDValue Arg = OutVals[i];
2843 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2845 if (Flags.isByVal()) {
2846 // Argument is an aggregate which is passed by value, thus we need to
2847 // create a copy of it in the local variable space of the current stack
2848 // frame (which is the stack frame of the caller) and pass the address of
2849 // this copy to the callee.
2850 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
2851 CCValAssign &ByValVA = ByValArgLocs[j++];
2852 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
2854 // Memory reserved in the local variable space of the callers stack frame.
2855 unsigned LocMemOffset = ByValVA.getLocMemOffset();
2857 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2858 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2860 // Create a copy of the argument in the local area of the current
2862 SDValue MemcpyCall =
2863 CreateCopyOfByValArgument(Arg, PtrOff,
2864 CallSeqStart.getNode()->getOperand(0),
2867 // This must go outside the CALLSEQ_START..END.
2868 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
2869 CallSeqStart.getNode()->getOperand(1));
2870 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
2871 NewCallSeqStart.getNode());
2872 Chain = CallSeqStart = NewCallSeqStart;
2874 // Pass the address of the aggregate copy on the stack either in a
2875 // physical register or in the parameter list area of the current stack
2876 // frame to the callee.
2880 if (VA.isRegLoc()) {
2881 // Put argument in a physical register.
2882 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2884 // Put argument in the parameter list area of the current stack frame.
2885 assert(VA.isMemLoc());
2886 unsigned LocMemOffset = VA.getLocMemOffset();
2889 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2890 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2892 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
2893 MachinePointerInfo(),
2896 // Calculate and remember argument location.
2897 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
2903 if (!MemOpChains.empty())
2904 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2905 &MemOpChains[0], MemOpChains.size());
2907 // Build a sequence of copy-to-reg nodes chained together with token chain
2908 // and flag operands which copy the outgoing args into the appropriate regs.
2910 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2911 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2912 RegsToPass[i].second, InFlag);
2913 InFlag = Chain.getValue(1);
2916 // Set CR6 to true if this is a vararg call.
2918 SDValue SetCR(DAG.getMachineNode(PPC::CRSET, dl, MVT::i32), 0);
2919 Chain = DAG.getCopyToReg(Chain, dl, PPC::CR1EQ, SetCR, InFlag);
2920 InFlag = Chain.getValue(1);
2924 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
2925 false, TailCallArguments);
2927 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
2928 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
2933 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
2934 CallingConv::ID CallConv, bool isVarArg,
2936 const SmallVectorImpl<ISD::OutputArg> &Outs,
2937 const SmallVectorImpl<SDValue> &OutVals,
2938 const SmallVectorImpl<ISD::InputArg> &Ins,
2939 DebugLoc dl, SelectionDAG &DAG,
2940 SmallVectorImpl<SDValue> &InVals) const {
2942 unsigned NumOps = Outs.size();
2944 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2945 bool isPPC64 = PtrVT == MVT::i64;
2946 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2948 MachineFunction &MF = DAG.getMachineFunction();
2950 // Mark this function as potentially containing a function that contains a
2951 // tail call. As a consequence the frame pointer will be used for dynamicalloc
2952 // and restoring the callers stack pointer in this functions epilog. This is
2953 // done because by tail calling the called function might overwrite the value
2954 // in this function's (MF) stack pointer stack slot 0(SP).
2955 if (GuaranteedTailCallOpt && CallConv==CallingConv::Fast)
2956 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
2958 unsigned nAltivecParamsAtEnd = 0;
2960 // Count how many bytes are to be pushed on the stack, including the linkage
2961 // area, and parameter passing area. We start with 24/48 bytes, which is
2962 // prereserved space for [SP][CR][LR][3 x unused].
2964 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv,
2966 nAltivecParamsAtEnd);
2968 // Calculate by how many bytes the stack has to be adjusted in case of tail
2969 // call optimization.
2970 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
2972 // To protect arguments on the stack from being clobbered in a tail call,
2973 // force all the loads to happen before doing any other lowering.
2975 Chain = DAG.getStackArgumentTokenFactor(Chain);
2977 // Adjust the stack pointer for the new arguments...
2978 // These operations are automatically eliminated by the prolog/epilog pass
2979 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2980 SDValue CallSeqStart = Chain;
2982 // Load the return address and frame pointer so it can be move somewhere else
2985 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
2988 // Set up a copy of the stack pointer for use loading and storing any
2989 // arguments that may not fit in the registers available for argument
2993 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
2995 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2997 // Figure out which arguments are going to go in registers, and which in
2998 // memory. Also, if this is a vararg function, floating point operations
2999 // must be stored to our stack, and loaded into integer regs as well, if
3000 // any integer regs are available for argument passing.
3001 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, true);
3002 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3004 static const unsigned GPR_32[] = { // 32-bit registers.
3005 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3006 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3008 static const unsigned GPR_64[] = { // 64-bit registers.
3009 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3010 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3012 static const unsigned *FPR = GetFPR();
3014 static const unsigned VR[] = {
3015 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3016 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3018 const unsigned NumGPRs = array_lengthof(GPR_32);
3019 const unsigned NumFPRs = 13;
3020 const unsigned NumVRs = array_lengthof(VR);
3022 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
3024 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3025 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3027 SmallVector<SDValue, 8> MemOpChains;
3028 for (unsigned i = 0; i != NumOps; ++i) {
3029 SDValue Arg = OutVals[i];
3030 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3032 // PtrOff will be used to store the current argument to the stack if a
3033 // register cannot be found for it.
3036 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
3038 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
3040 // On PPC64, promote integers to 64-bit values.
3041 if (isPPC64 && Arg.getValueType() == MVT::i32) {
3042 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
3043 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3044 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
3047 // FIXME memcpy is used way more than necessary. Correctness first.
3048 if (Flags.isByVal()) {
3049 unsigned Size = Flags.getByValSize();
3050 if (Size==1 || Size==2) {
3051 // Very small objects are passed right-justified.
3052 // Everything else is passed left-justified.
3053 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
3054 if (GPR_idx != NumGPRs) {
3055 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, PtrVT, dl, Chain, Arg,
3056 MachinePointerInfo(), VT,
3058 MemOpChains.push_back(Load.getValue(1));
3059 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3061 ArgOffset += PtrByteSize;
3063 SDValue Const = DAG.getConstant(4 - Size, PtrOff.getValueType());
3064 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3065 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr,
3066 CallSeqStart.getNode()->getOperand(0),
3068 // This must go outside the CALLSEQ_START..END.
3069 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3070 CallSeqStart.getNode()->getOperand(1));
3071 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3072 NewCallSeqStart.getNode());
3073 Chain = CallSeqStart = NewCallSeqStart;
3074 ArgOffset += PtrByteSize;
3078 // Copy entire object into memory. There are cases where gcc-generated
3079 // code assumes it is there, even if it could be put entirely into
3080 // registers. (This is not what the doc says.)
3081 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
3082 CallSeqStart.getNode()->getOperand(0),
3084 // This must go outside the CALLSEQ_START..END.
3085 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3086 CallSeqStart.getNode()->getOperand(1));
3087 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), NewCallSeqStart.getNode());
3088 Chain = CallSeqStart = NewCallSeqStart;
3089 // And copy the pieces of it that fit into registers.
3090 for (unsigned j=0; j<Size; j+=PtrByteSize) {
3091 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
3092 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
3093 if (GPR_idx != NumGPRs) {
3094 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
3095 MachinePointerInfo(),
3097 MemOpChains.push_back(Load.getValue(1));
3098 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3099 ArgOffset += PtrByteSize;
3101 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
3108 switch (Arg.getValueType().getSimpleVT().SimpleTy) {
3109 default: llvm_unreachable("Unexpected ValueType for argument!");
3112 if (GPR_idx != NumGPRs) {
3113 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
3115 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3116 isPPC64, isTailCall, false, MemOpChains,
3117 TailCallArguments, dl);
3119 ArgOffset += PtrByteSize;
3123 if (FPR_idx != NumFPRs) {
3124 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
3127 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
3128 MachinePointerInfo(), false, false, 0);
3129 MemOpChains.push_back(Store);
3131 // Float varargs are always shadowed in available integer registers
3132 if (GPR_idx != NumGPRs) {
3133 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
3134 MachinePointerInfo(), false, false, 0);
3135 MemOpChains.push_back(Load.getValue(1));
3136 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3138 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
3139 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
3140 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
3141 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
3142 MachinePointerInfo(),
3144 MemOpChains.push_back(Load.getValue(1));
3145 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3148 // If we have any FPRs remaining, we may also have GPRs remaining.
3149 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
3151 if (GPR_idx != NumGPRs)
3153 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
3154 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
3158 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3159 isPPC64, isTailCall, false, MemOpChains,
3160 TailCallArguments, dl);
3165 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
3172 // These go aligned on the stack, or in the corresponding R registers
3173 // when within range. The Darwin PPC ABI doc claims they also go in
3174 // V registers; in fact gcc does this only for arguments that are
3175 // prototyped, not for those that match the ... We do it for all
3176 // arguments, seems to work.
3177 while (ArgOffset % 16 !=0) {
3178 ArgOffset += PtrByteSize;
3179 if (GPR_idx != NumGPRs)
3182 // We could elide this store in the case where the object fits
3183 // entirely in R registers. Maybe later.
3184 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3185 DAG.getConstant(ArgOffset, PtrVT));
3186 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
3187 MachinePointerInfo(), false, false, 0);
3188 MemOpChains.push_back(Store);
3189 if (VR_idx != NumVRs) {
3190 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
3191 MachinePointerInfo(),
3193 MemOpChains.push_back(Load.getValue(1));
3194 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
3197 for (unsigned i=0; i<16; i+=PtrByteSize) {
3198 if (GPR_idx == NumGPRs)
3200 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
3201 DAG.getConstant(i, PtrVT));
3202 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
3204 MemOpChains.push_back(Load.getValue(1));
3205 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3210 // Non-varargs Altivec params generally go in registers, but have
3211 // stack space allocated at the end.
3212 if (VR_idx != NumVRs) {
3213 // Doesn't have GPR space allocated.
3214 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
3215 } else if (nAltivecParamsAtEnd==0) {
3216 // We are emitting Altivec params in order.
3217 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3218 isPPC64, isTailCall, true, MemOpChains,
3219 TailCallArguments, dl);
3225 // If all Altivec parameters fit in registers, as they usually do,
3226 // they get stack space following the non-Altivec parameters. We
3227 // don't track this here because nobody below needs it.
3228 // If there are more Altivec parameters than fit in registers emit
3230 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
3232 // Offset is aligned; skip 1st 12 params which go in V registers.
3233 ArgOffset = ((ArgOffset+15)/16)*16;
3235 for (unsigned i = 0; i != NumOps; ++i) {
3236 SDValue Arg = OutVals[i];
3237 EVT ArgType = Outs[i].VT;
3238 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
3239 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
3242 // We are emitting Altivec params in order.
3243 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3244 isPPC64, isTailCall, true, MemOpChains,
3245 TailCallArguments, dl);
3252 if (!MemOpChains.empty())
3253 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3254 &MemOpChains[0], MemOpChains.size());
3256 // Check if this is an indirect call (MTCTR/BCTRL).
3257 // See PrepareCall() for more information about calls through function
3258 // pointers in the 64-bit SVR4 ABI.
3259 if (!isTailCall && isPPC64 && PPCSubTarget.isSVR4ABI() &&
3260 !dyn_cast<GlobalAddressSDNode>(Callee) &&
3261 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
3262 !isBLACompatibleAddress(Callee, DAG)) {
3263 // Load r2 into a virtual register and store it to the TOC save area.
3264 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
3265 // TOC save area offset.
3266 SDValue PtrOff = DAG.getIntPtrConstant(40);
3267 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
3268 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
3272 // On Darwin, R12 must contain the address of an indirect callee. This does
3273 // not mean the MTCTR instruction must use R12; it's easier to model this as
3274 // an extra parameter, so do that.
3276 !dyn_cast<GlobalAddressSDNode>(Callee) &&
3277 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
3278 !isBLACompatibleAddress(Callee, DAG))
3279 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
3280 PPC::R12), Callee));
3282 // Build a sequence of copy-to-reg nodes chained together with token chain
3283 // and flag operands which copy the outgoing args into the appropriate regs.
3285 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3286 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3287 RegsToPass[i].second, InFlag);
3288 InFlag = Chain.getValue(1);
3292 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
3293 FPOp, true, TailCallArguments);
3295 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3296 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3301 PPCTargetLowering::LowerReturn(SDValue Chain,
3302 CallingConv::ID CallConv, bool isVarArg,
3303 const SmallVectorImpl<ISD::OutputArg> &Outs,
3304 const SmallVectorImpl<SDValue> &OutVals,
3305 DebugLoc dl, SelectionDAG &DAG) const {
3307 SmallVector<CCValAssign, 16> RVLocs;
3308 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
3309 RVLocs, *DAG.getContext());
3310 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
3312 // If this is the first return lowered for this function, add the regs to the
3313 // liveout set for the function.
3314 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
3315 for (unsigned i = 0; i != RVLocs.size(); ++i)
3316 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
3321 // Copy the result values into the output registers.
3322 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3323 CCValAssign &VA = RVLocs[i];
3324 assert(VA.isRegLoc() && "Can only return in registers!");
3325 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3327 Flag = Chain.getValue(1);
3331 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
3333 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain);
3336 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
3337 const PPCSubtarget &Subtarget) const {
3338 // When we pop the dynamic allocation we need to restore the SP link.
3339 DebugLoc dl = Op.getDebugLoc();
3341 // Get the corect type for pointers.
3342 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3344 // Construct the stack pointer operand.
3345 bool isPPC64 = Subtarget.isPPC64();
3346 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
3347 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
3349 // Get the operands for the STACKRESTORE.
3350 SDValue Chain = Op.getOperand(0);
3351 SDValue SaveSP = Op.getOperand(1);
3353 // Load the old link SP.
3354 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
3355 MachinePointerInfo(),
3358 // Restore the stack pointer.
3359 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
3361 // Store the old link SP.
3362 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
3369 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
3370 MachineFunction &MF = DAG.getMachineFunction();
3371 bool isPPC64 = PPCSubTarget.isPPC64();
3372 bool isDarwinABI = PPCSubTarget.isDarwinABI();
3373 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3375 // Get current frame pointer save index. The users of this index will be
3376 // primarily DYNALLOC instructions.
3377 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
3378 int RASI = FI->getReturnAddrSaveIndex();
3380 // If the frame pointer save index hasn't been defined yet.
3382 // Find out what the fix offset of the frame pointer save area.
3383 int LROffset = PPCFrameInfo::getReturnSaveOffset(isPPC64, isDarwinABI);
3384 // Allocate the frame index for frame pointer save area.
3385 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
3387 FI->setReturnAddrSaveIndex(RASI);
3389 return DAG.getFrameIndex(RASI, PtrVT);
3393 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
3394 MachineFunction &MF = DAG.getMachineFunction();
3395 bool isPPC64 = PPCSubTarget.isPPC64();
3396 bool isDarwinABI = PPCSubTarget.isDarwinABI();
3397 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3399 // Get current frame pointer save index. The users of this index will be
3400 // primarily DYNALLOC instructions.
3401 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
3402 int FPSI = FI->getFramePointerSaveIndex();
3404 // If the frame pointer save index hasn't been defined yet.
3406 // Find out what the fix offset of the frame pointer save area.
3407 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(isPPC64,
3410 // Allocate the frame index for frame pointer save area.
3411 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
3413 FI->setFramePointerSaveIndex(FPSI);
3415 return DAG.getFrameIndex(FPSI, PtrVT);
3418 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
3420 const PPCSubtarget &Subtarget) const {
3422 SDValue Chain = Op.getOperand(0);
3423 SDValue Size = Op.getOperand(1);
3424 DebugLoc dl = Op.getDebugLoc();
3426 // Get the corect type for pointers.
3427 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3429 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
3430 DAG.getConstant(0, PtrVT), Size);
3431 // Construct a node for the frame pointer save index.
3432 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
3433 // Build a DYNALLOC node.
3434 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
3435 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
3436 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3);
3439 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
3441 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
3442 // Not FP? Not a fsel.
3443 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
3444 !Op.getOperand(2).getValueType().isFloatingPoint())
3447 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3449 // Cannot handle SETEQ/SETNE.
3450 if (CC == ISD::SETEQ || CC == ISD::SETNE) return Op;
3452 EVT ResVT = Op.getValueType();
3453 EVT CmpVT = Op.getOperand(0).getValueType();
3454 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3455 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
3456 DebugLoc dl = Op.getDebugLoc();
3458 // If the RHS of the comparison is a 0.0, we don't need to do the
3459 // subtraction at all.
3460 if (isFloatingPointZero(RHS))
3462 default: break; // SETUO etc aren't handled by fsel.
3465 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
3468 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
3469 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
3470 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
3473 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
3476 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
3477 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
3478 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
3479 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
3484 default: break; // SETUO etc aren't handled by fsel.
3487 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
3488 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3489 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3490 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
3493 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
3494 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3495 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3496 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
3499 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
3500 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3501 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3502 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
3505 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
3506 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3507 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3508 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
3513 // FIXME: Split this code up when LegalizeDAGTypes lands.
3514 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
3515 DebugLoc dl) const {
3516 assert(Op.getOperand(0).getValueType().isFloatingPoint());
3517 SDValue Src = Op.getOperand(0);
3518 if (Src.getValueType() == MVT::f32)
3519 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
3522 switch (Op.getValueType().getSimpleVT().SimpleTy) {
3523 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
3525 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
3530 Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src);
3534 // Convert the FP value to an int value through memory.
3535 SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64);
3537 // Emit a store to the stack slot.
3538 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
3539 MachinePointerInfo(), false, false, 0);
3541 // Result is a load from the stack slot. If loading 4 bytes, make sure to
3543 if (Op.getValueType() == MVT::i32)
3544 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
3545 DAG.getConstant(4, FIPtr.getValueType()));
3546 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MachinePointerInfo(),
3550 SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op,
3551 SelectionDAG &DAG) const {
3552 DebugLoc dl = Op.getDebugLoc();
3553 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
3554 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
3557 if (Op.getOperand(0).getValueType() == MVT::i64) {
3558 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op.getOperand(0));
3559 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits);
3560 if (Op.getValueType() == MVT::f32)
3561 FP = DAG.getNode(ISD::FP_ROUND, dl,
3562 MVT::f32, FP, DAG.getIntPtrConstant(0));
3566 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
3567 "Unhandled SINT_TO_FP type in custom expander!");
3568 // Since we only generate this in 64-bit mode, we can take advantage of
3569 // 64-bit registers. In particular, sign extend the input value into the
3570 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
3571 // then lfd it and fcfid it.
3572 MachineFunction &MF = DAG.getMachineFunction();
3573 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
3574 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
3575 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3576 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
3578 SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, MVT::i32,
3581 // STD the extended value into the stack slot.
3582 MachineMemOperand *MMO =
3583 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
3584 MachineMemOperand::MOStore, 8, 8);
3585 SDValue Ops[] = { DAG.getEntryNode(), Ext64, FIdx };
3587 DAG.getMemIntrinsicNode(PPCISD::STD_32, dl, DAG.getVTList(MVT::Other),
3588 Ops, 4, MVT::i64, MMO);
3589 // Load the value as a double.
3590 SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, MachinePointerInfo(),
3593 // FCFID it and return it.
3594 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld);
3595 if (Op.getValueType() == MVT::f32)
3596 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
3600 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
3601 SelectionDAG &DAG) const {
3602 DebugLoc dl = Op.getDebugLoc();
3604 The rounding mode is in bits 30:31 of FPSR, and has the following
3611 FLT_ROUNDS, on the other hand, expects the following:
3618 To perform the conversion, we do:
3619 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
3622 MachineFunction &MF = DAG.getMachineFunction();
3623 EVT VT = Op.getValueType();
3624 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3625 std::vector<EVT> NodeTys;
3626 SDValue MFFSreg, InFlag;
3628 // Save FP Control Word to register
3629 NodeTys.push_back(MVT::f64); // return register
3630 NodeTys.push_back(MVT::Flag); // unused in this context
3631 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
3633 // Save FP register to stack slot
3634 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
3635 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
3636 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
3637 StackSlot, MachinePointerInfo(), false, false,0);
3639 // Load FP Control Word from low 32 bits of stack slot.
3640 SDValue Four = DAG.getConstant(4, PtrVT);
3641 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
3642 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
3645 // Transform as necessary
3647 DAG.getNode(ISD::AND, dl, MVT::i32,
3648 CWD, DAG.getConstant(3, MVT::i32));
3650 DAG.getNode(ISD::SRL, dl, MVT::i32,
3651 DAG.getNode(ISD::AND, dl, MVT::i32,
3652 DAG.getNode(ISD::XOR, dl, MVT::i32,
3653 CWD, DAG.getConstant(3, MVT::i32)),
3654 DAG.getConstant(3, MVT::i32)),
3655 DAG.getConstant(1, MVT::i32));
3658 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
3660 return DAG.getNode((VT.getSizeInBits() < 16 ?
3661 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
3664 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
3665 EVT VT = Op.getValueType();
3666 unsigned BitWidth = VT.getSizeInBits();
3667 DebugLoc dl = Op.getDebugLoc();
3668 assert(Op.getNumOperands() == 3 &&
3669 VT == Op.getOperand(1).getValueType() &&
3672 // Expand into a bunch of logical ops. Note that these ops
3673 // depend on the PPC behavior for oversized shift amounts.
3674 SDValue Lo = Op.getOperand(0);
3675 SDValue Hi = Op.getOperand(1);
3676 SDValue Amt = Op.getOperand(2);
3677 EVT AmtVT = Amt.getValueType();
3679 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3680 DAG.getConstant(BitWidth, AmtVT), Amt);
3681 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
3682 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
3683 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
3684 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3685 DAG.getConstant(-BitWidth, AmtVT));
3686 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
3687 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
3688 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
3689 SDValue OutOps[] = { OutLo, OutHi };
3690 return DAG.getMergeValues(OutOps, 2, dl);
3693 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
3694 EVT VT = Op.getValueType();
3695 DebugLoc dl = Op.getDebugLoc();
3696 unsigned BitWidth = VT.getSizeInBits();
3697 assert(Op.getNumOperands() == 3 &&
3698 VT == Op.getOperand(1).getValueType() &&
3701 // Expand into a bunch of logical ops. Note that these ops
3702 // depend on the PPC behavior for oversized shift amounts.
3703 SDValue Lo = Op.getOperand(0);
3704 SDValue Hi = Op.getOperand(1);
3705 SDValue Amt = Op.getOperand(2);
3706 EVT AmtVT = Amt.getValueType();
3708 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3709 DAG.getConstant(BitWidth, AmtVT), Amt);
3710 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
3711 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
3712 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
3713 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3714 DAG.getConstant(-BitWidth, AmtVT));
3715 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
3716 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
3717 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
3718 SDValue OutOps[] = { OutLo, OutHi };
3719 return DAG.getMergeValues(OutOps, 2, dl);
3722 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
3723 DebugLoc dl = Op.getDebugLoc();
3724 EVT VT = Op.getValueType();
3725 unsigned BitWidth = VT.getSizeInBits();
3726 assert(Op.getNumOperands() == 3 &&
3727 VT == Op.getOperand(1).getValueType() &&
3730 // Expand into a bunch of logical ops, followed by a select_cc.
3731 SDValue Lo = Op.getOperand(0);
3732 SDValue Hi = Op.getOperand(1);
3733 SDValue Amt = Op.getOperand(2);
3734 EVT AmtVT = Amt.getValueType();
3736 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3737 DAG.getConstant(BitWidth, AmtVT), Amt);
3738 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
3739 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
3740 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
3741 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3742 DAG.getConstant(-BitWidth, AmtVT));
3743 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
3744 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
3745 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
3746 Tmp4, Tmp6, ISD::SETLE);
3747 SDValue OutOps[] = { OutLo, OutHi };
3748 return DAG.getMergeValues(OutOps, 2, dl);
3751 //===----------------------------------------------------------------------===//
3752 // Vector related lowering.
3755 /// BuildSplatI - Build a canonical splati of Val with an element size of
3756 /// SplatSize. Cast the result to VT.
3757 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
3758 SelectionDAG &DAG, DebugLoc dl) {
3759 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
3761 static const EVT VTys[] = { // canonical VT to use for each size.
3762 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
3765 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
3767 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
3771 EVT CanonicalVT = VTys[SplatSize-1];
3773 // Build a canonical splat for this value.
3774 SDValue Elt = DAG.getConstant(Val, MVT::i32);
3775 SmallVector<SDValue, 8> Ops;
3776 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
3777 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
3778 &Ops[0], Ops.size());
3779 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
3782 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
3783 /// specified intrinsic ID.
3784 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
3785 SelectionDAG &DAG, DebugLoc dl,
3786 EVT DestVT = MVT::Other) {
3787 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
3788 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
3789 DAG.getConstant(IID, MVT::i32), LHS, RHS);
3792 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
3793 /// specified intrinsic ID.
3794 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
3795 SDValue Op2, SelectionDAG &DAG,
3796 DebugLoc dl, EVT DestVT = MVT::Other) {
3797 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
3798 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
3799 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
3803 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
3804 /// amount. The result has the specified value type.
3805 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
3806 EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3807 // Force LHS/RHS to be the right type.
3808 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
3809 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
3812 for (unsigned i = 0; i != 16; ++i)
3814 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
3815 return DAG.getNode(ISD::BITCAST, dl, VT, T);
3818 // If this is a case we can't handle, return null and let the default
3819 // expansion code take care of it. If we CAN select this case, and if it
3820 // selects to a single instruction, return Op. Otherwise, if we can codegen
3821 // this case more efficiently than a constant pool load, lower it to the
3822 // sequence of ops that should be used.
3823 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
3824 SelectionDAG &DAG) const {
3825 DebugLoc dl = Op.getDebugLoc();
3826 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
3827 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
3829 // Check if this is a splat of a constant value.
3830 APInt APSplatBits, APSplatUndef;
3831 unsigned SplatBitSize;
3833 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
3834 HasAnyUndefs, 0, true) || SplatBitSize > 32)
3837 unsigned SplatBits = APSplatBits.getZExtValue();
3838 unsigned SplatUndef = APSplatUndef.getZExtValue();
3839 unsigned SplatSize = SplatBitSize / 8;
3841 // First, handle single instruction cases.
3844 if (SplatBits == 0) {
3845 // Canonicalize all zero vectors to be v4i32.
3846 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
3847 SDValue Z = DAG.getConstant(0, MVT::i32);
3848 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
3849 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
3854 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
3855 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
3857 if (SextVal >= -16 && SextVal <= 15)
3858 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
3861 // Two instruction sequences.
3863 // If this value is in the range [-32,30] and is even, use:
3864 // tmp = VSPLTI[bhw], result = add tmp, tmp
3865 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
3866 SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG, dl);
3867 Res = DAG.getNode(ISD::ADD, dl, Res.getValueType(), Res, Res);
3868 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
3871 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
3872 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
3874 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
3875 // Make -1 and vspltisw -1:
3876 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
3878 // Make the VSLW intrinsic, computing 0x8000_0000.
3879 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
3882 // xor by OnesV to invert it.
3883 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
3884 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
3887 // Check to see if this is a wide variety of vsplti*, binop self cases.
3888 static const signed char SplatCsts[] = {
3889 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
3890 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
3893 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
3894 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
3895 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
3896 int i = SplatCsts[idx];
3898 // Figure out what shift amount will be used by altivec if shifted by i in
3900 unsigned TypeShiftAmt = i & (SplatBitSize-1);
3902 // vsplti + shl self.
3903 if (SextVal == (i << (int)TypeShiftAmt)) {
3904 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3905 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3906 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
3907 Intrinsic::ppc_altivec_vslw
3909 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3910 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
3913 // vsplti + srl self.
3914 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
3915 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3916 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3917 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
3918 Intrinsic::ppc_altivec_vsrw
3920 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3921 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
3924 // vsplti + sra self.
3925 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
3926 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3927 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3928 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
3929 Intrinsic::ppc_altivec_vsraw
3931 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3932 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
3935 // vsplti + rol self.
3936 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
3937 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
3938 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3939 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3940 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
3941 Intrinsic::ppc_altivec_vrlw
3943 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3944 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
3947 // t = vsplti c, result = vsldoi t, t, 1
3948 if (SextVal == ((i << 8) | (i < 0 ? 0xFF : 0))) {
3949 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3950 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
3952 // t = vsplti c, result = vsldoi t, t, 2
3953 if (SextVal == ((i << 16) | (i < 0 ? 0xFFFF : 0))) {
3954 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3955 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
3957 // t = vsplti c, result = vsldoi t, t, 3
3958 if (SextVal == ((i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
3959 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3960 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
3964 // Three instruction sequences.
3966 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
3967 if (SextVal >= 0 && SextVal <= 31) {
3968 SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG, dl);
3969 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
3970 LHS = DAG.getNode(ISD::SUB, dl, LHS.getValueType(), LHS, RHS);
3971 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), LHS);
3973 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
3974 if (SextVal >= -31 && SextVal <= 0) {
3975 SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG, dl);
3976 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
3977 LHS = DAG.getNode(ISD::ADD, dl, LHS.getValueType(), LHS, RHS);
3978 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), LHS);
3984 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
3985 /// the specified operations to build the shuffle.
3986 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
3987 SDValue RHS, SelectionDAG &DAG,
3989 unsigned OpNum = (PFEntry >> 26) & 0x0F;
3990 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
3991 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
3994 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
4006 if (OpNum == OP_COPY) {
4007 if (LHSID == (1*9+2)*9+3) return LHS;
4008 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
4012 SDValue OpLHS, OpRHS;
4013 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
4014 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
4018 default: llvm_unreachable("Unknown i32 permute!");
4020 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
4021 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
4022 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
4023 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
4026 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
4027 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
4028 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
4029 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
4032 for (unsigned i = 0; i != 16; ++i)
4033 ShufIdxs[i] = (i&3)+0;
4036 for (unsigned i = 0; i != 16; ++i)
4037 ShufIdxs[i] = (i&3)+4;
4040 for (unsigned i = 0; i != 16; ++i)
4041 ShufIdxs[i] = (i&3)+8;
4044 for (unsigned i = 0; i != 16; ++i)
4045 ShufIdxs[i] = (i&3)+12;
4048 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
4050 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
4052 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
4054 EVT VT = OpLHS.getValueType();
4055 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
4056 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
4057 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
4058 return DAG.getNode(ISD::BITCAST, dl, VT, T);
4061 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
4062 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
4063 /// return the code it can be lowered into. Worst case, it can always be
4064 /// lowered into a vperm.
4065 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
4066 SelectionDAG &DAG) const {
4067 DebugLoc dl = Op.getDebugLoc();
4068 SDValue V1 = Op.getOperand(0);
4069 SDValue V2 = Op.getOperand(1);
4070 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4071 EVT VT = Op.getValueType();
4073 // Cases that are handled by instructions that take permute immediates
4074 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
4075 // selected by the instruction selector.
4076 if (V2.getOpcode() == ISD::UNDEF) {
4077 if (PPC::isSplatShuffleMask(SVOp, 1) ||
4078 PPC::isSplatShuffleMask(SVOp, 2) ||
4079 PPC::isSplatShuffleMask(SVOp, 4) ||
4080 PPC::isVPKUWUMShuffleMask(SVOp, true) ||
4081 PPC::isVPKUHUMShuffleMask(SVOp, true) ||
4082 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 ||
4083 PPC::isVMRGLShuffleMask(SVOp, 1, true) ||
4084 PPC::isVMRGLShuffleMask(SVOp, 2, true) ||
4085 PPC::isVMRGLShuffleMask(SVOp, 4, true) ||
4086 PPC::isVMRGHShuffleMask(SVOp, 1, true) ||
4087 PPC::isVMRGHShuffleMask(SVOp, 2, true) ||
4088 PPC::isVMRGHShuffleMask(SVOp, 4, true)) {
4093 // Altivec has a variety of "shuffle immediates" that take two vector inputs
4094 // and produce a fixed permutation. If any of these match, do not lower to
4096 if (PPC::isVPKUWUMShuffleMask(SVOp, false) ||
4097 PPC::isVPKUHUMShuffleMask(SVOp, false) ||
4098 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 ||
4099 PPC::isVMRGLShuffleMask(SVOp, 1, false) ||
4100 PPC::isVMRGLShuffleMask(SVOp, 2, false) ||
4101 PPC::isVMRGLShuffleMask(SVOp, 4, false) ||
4102 PPC::isVMRGHShuffleMask(SVOp, 1, false) ||
4103 PPC::isVMRGHShuffleMask(SVOp, 2, false) ||
4104 PPC::isVMRGHShuffleMask(SVOp, 4, false))
4107 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
4108 // perfect shuffle table to emit an optimal matching sequence.
4109 SmallVector<int, 16> PermMask;
4110 SVOp->getMask(PermMask);
4112 unsigned PFIndexes[4];
4113 bool isFourElementShuffle = true;
4114 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
4115 unsigned EltNo = 8; // Start out undef.
4116 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
4117 if (PermMask[i*4+j] < 0)
4118 continue; // Undef, ignore it.
4120 unsigned ByteSource = PermMask[i*4+j];
4121 if ((ByteSource & 3) != j) {
4122 isFourElementShuffle = false;
4127 EltNo = ByteSource/4;
4128 } else if (EltNo != ByteSource/4) {
4129 isFourElementShuffle = false;
4133 PFIndexes[i] = EltNo;
4136 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
4137 // perfect shuffle vector to determine if it is cost effective to do this as
4138 // discrete instructions, or whether we should use a vperm.
4139 if (isFourElementShuffle) {
4140 // Compute the index in the perfect shuffle table.
4141 unsigned PFTableIndex =
4142 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
4144 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4145 unsigned Cost = (PFEntry >> 30);
4147 // Determining when to avoid vperm is tricky. Many things affect the cost
4148 // of vperm, particularly how many times the perm mask needs to be computed.
4149 // For example, if the perm mask can be hoisted out of a loop or is already
4150 // used (perhaps because there are multiple permutes with the same shuffle
4151 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
4152 // the loop requires an extra register.
4154 // As a compromise, we only emit discrete instructions if the shuffle can be
4155 // generated in 3 or fewer operations. When we have loop information
4156 // available, if this block is within a loop, we should avoid using vperm
4157 // for 3-operation perms and use a constant pool load instead.
4159 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
4162 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
4163 // vector that will get spilled to the constant pool.
4164 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
4166 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
4167 // that it is in input element units, not in bytes. Convert now.
4168 EVT EltVT = V1.getValueType().getVectorElementType();
4169 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
4171 SmallVector<SDValue, 16> ResultMask;
4172 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
4173 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
4175 for (unsigned j = 0; j != BytesPerElement; ++j)
4176 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
4180 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
4181 &ResultMask[0], ResultMask.size());
4182 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
4185 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
4186 /// altivec comparison. If it is, return true and fill in Opc/isDot with
4187 /// information about the intrinsic.
4188 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
4190 unsigned IntrinsicID =
4191 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
4194 switch (IntrinsicID) {
4195 default: return false;
4196 // Comparison predicates.
4197 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
4198 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
4199 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
4200 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
4201 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
4202 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
4203 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
4204 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
4205 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
4206 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
4207 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
4208 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
4209 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
4211 // Normal Comparisons.
4212 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
4213 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
4214 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
4215 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
4216 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
4217 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
4218 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
4219 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
4220 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
4221 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
4222 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
4223 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
4224 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
4229 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
4230 /// lower, do it, otherwise return null.
4231 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
4232 SelectionDAG &DAG) const {
4233 // If this is a lowered altivec predicate compare, CompareOpc is set to the
4234 // opcode number of the comparison.
4235 DebugLoc dl = Op.getDebugLoc();
4238 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
4239 return SDValue(); // Don't custom lower most intrinsics.
4241 // If this is a non-dot comparison, make the VCMP node and we are done.
4243 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
4244 Op.getOperand(1), Op.getOperand(2),
4245 DAG.getConstant(CompareOpc, MVT::i32));
4246 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
4249 // Create the PPCISD altivec 'dot' comparison node.
4251 Op.getOperand(2), // LHS
4252 Op.getOperand(3), // RHS
4253 DAG.getConstant(CompareOpc, MVT::i32)
4255 std::vector<EVT> VTs;
4256 VTs.push_back(Op.getOperand(2).getValueType());
4257 VTs.push_back(MVT::Flag);
4258 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
4260 // Now that we have the comparison, emit a copy from the CR to a GPR.
4261 // This is flagged to the above dot comparison.
4262 SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32,
4263 DAG.getRegister(PPC::CR6, MVT::i32),
4264 CompNode.getValue(1));
4266 // Unpack the result based on how the target uses it.
4267 unsigned BitNo; // Bit # of CR6.
4268 bool InvertBit; // Invert result?
4269 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
4270 default: // Can't happen, don't crash on invalid number though.
4271 case 0: // Return the value of the EQ bit of CR6.
4272 BitNo = 0; InvertBit = false;
4274 case 1: // Return the inverted value of the EQ bit of CR6.
4275 BitNo = 0; InvertBit = true;
4277 case 2: // Return the value of the LT bit of CR6.
4278 BitNo = 2; InvertBit = false;
4280 case 3: // Return the inverted value of the LT bit of CR6.
4281 BitNo = 2; InvertBit = true;
4285 // Shift the bit into the low position.
4286 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
4287 DAG.getConstant(8-(3-BitNo), MVT::i32));
4289 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
4290 DAG.getConstant(1, MVT::i32));
4292 // If we are supposed to, toggle the bit.
4294 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
4295 DAG.getConstant(1, MVT::i32));
4299 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
4300 SelectionDAG &DAG) const {
4301 DebugLoc dl = Op.getDebugLoc();
4302 // Create a stack slot that is 16-byte aligned.
4303 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
4304 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
4305 EVT PtrVT = getPointerTy();
4306 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4308 // Store the input value into Value#0 of the stack slot.
4309 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
4310 Op.getOperand(0), FIdx, MachinePointerInfo(),
4313 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
4317 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
4318 DebugLoc dl = Op.getDebugLoc();
4319 if (Op.getValueType() == MVT::v4i32) {
4320 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4322 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
4323 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
4325 SDValue RHSSwap = // = vrlw RHS, 16
4326 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
4328 // Shrinkify inputs to v8i16.
4329 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
4330 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
4331 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
4333 // Low parts multiplied together, generating 32-bit results (we ignore the
4335 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
4336 LHS, RHS, DAG, dl, MVT::v4i32);
4338 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
4339 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
4340 // Shift the high parts up 16 bits.
4341 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
4343 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
4344 } else if (Op.getValueType() == MVT::v8i16) {
4345 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4347 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
4349 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
4350 LHS, RHS, Zero, DAG, dl);
4351 } else if (Op.getValueType() == MVT::v16i8) {
4352 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4354 // Multiply the even 8-bit parts, producing 16-bit sums.
4355 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
4356 LHS, RHS, DAG, dl, MVT::v8i16);
4357 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
4359 // Multiply the odd 8-bit parts, producing 16-bit sums.
4360 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
4361 LHS, RHS, DAG, dl, MVT::v8i16);
4362 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
4364 // Merge the results together.
4366 for (unsigned i = 0; i != 8; ++i) {
4368 Ops[i*2+1] = 2*i+1+16;
4370 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
4372 llvm_unreachable("Unknown mul to lower!");
4376 /// LowerOperation - Provide custom lowering hooks for some operations.
4378 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
4379 switch (Op.getOpcode()) {
4380 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
4381 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
4382 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
4383 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
4384 case ISD::GlobalTLSAddress: llvm_unreachable("TLS not implemented for PPC");
4385 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
4386 case ISD::SETCC: return LowerSETCC(Op, DAG);
4387 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
4389 return LowerVASTART(Op, DAG, PPCSubTarget);
4392 return LowerVAARG(Op, DAG, PPCSubTarget);
4394 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
4395 case ISD::DYNAMIC_STACKALLOC:
4396 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
4398 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
4399 case ISD::FP_TO_UINT:
4400 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
4402 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
4403 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
4405 // Lower 64-bit shifts.
4406 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
4407 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
4408 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
4410 // Vector-related lowering.
4411 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
4412 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
4413 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
4414 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
4415 case ISD::MUL: return LowerMUL(Op, DAG);
4417 // Frame & Return address.
4418 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4419 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
4424 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
4425 SmallVectorImpl<SDValue>&Results,
4426 SelectionDAG &DAG) const {
4427 DebugLoc dl = N->getDebugLoc();
4428 switch (N->getOpcode()) {
4430 assert(false && "Do not know how to custom type legalize this operation!");
4432 case ISD::FP_ROUND_INREG: {
4433 assert(N->getValueType(0) == MVT::ppcf128);
4434 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
4435 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
4436 MVT::f64, N->getOperand(0),
4437 DAG.getIntPtrConstant(0));
4438 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
4439 MVT::f64, N->getOperand(0),
4440 DAG.getIntPtrConstant(1));
4442 // This sequence changes FPSCR to do round-to-zero, adds the two halves
4443 // of the long double, and puts FPSCR back the way it was. We do not
4444 // actually model FPSCR.
4445 std::vector<EVT> NodeTys;
4446 SDValue Ops[4], Result, MFFSreg, InFlag, FPreg;
4448 NodeTys.push_back(MVT::f64); // Return register
4449 NodeTys.push_back(MVT::Flag); // Returns a flag for later insns
4450 Result = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
4451 MFFSreg = Result.getValue(0);
4452 InFlag = Result.getValue(1);
4455 NodeTys.push_back(MVT::Flag); // Returns a flag
4456 Ops[0] = DAG.getConstant(31, MVT::i32);
4458 Result = DAG.getNode(PPCISD::MTFSB1, dl, NodeTys, Ops, 2);
4459 InFlag = Result.getValue(0);
4462 NodeTys.push_back(MVT::Flag); // Returns a flag
4463 Ops[0] = DAG.getConstant(30, MVT::i32);
4465 Result = DAG.getNode(PPCISD::MTFSB0, dl, NodeTys, Ops, 2);
4466 InFlag = Result.getValue(0);
4469 NodeTys.push_back(MVT::f64); // result of add
4470 NodeTys.push_back(MVT::Flag); // Returns a flag
4474 Result = DAG.getNode(PPCISD::FADDRTZ, dl, NodeTys, Ops, 3);
4475 FPreg = Result.getValue(0);
4476 InFlag = Result.getValue(1);
4479 NodeTys.push_back(MVT::f64);
4480 Ops[0] = DAG.getConstant(1, MVT::i32);
4484 Result = DAG.getNode(PPCISD::MTFSF, dl, NodeTys, Ops, 4);
4485 FPreg = Result.getValue(0);
4487 // We know the low half is about to be thrown away, so just use something
4489 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
4493 case ISD::FP_TO_SINT:
4494 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
4500 //===----------------------------------------------------------------------===//
4501 // Other Lowering Code
4502 //===----------------------------------------------------------------------===//
4505 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
4506 bool is64bit, unsigned BinOpcode) const {
4507 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4508 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4510 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4511 MachineFunction *F = BB->getParent();
4512 MachineFunction::iterator It = BB;
4515 unsigned dest = MI->getOperand(0).getReg();
4516 unsigned ptrA = MI->getOperand(1).getReg();
4517 unsigned ptrB = MI->getOperand(2).getReg();
4518 unsigned incr = MI->getOperand(3).getReg();
4519 DebugLoc dl = MI->getDebugLoc();
4521 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
4522 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4523 F->insert(It, loopMBB);
4524 F->insert(It, exitMBB);
4525 exitMBB->splice(exitMBB->begin(), BB,
4526 llvm::next(MachineBasicBlock::iterator(MI)),
4528 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4530 MachineRegisterInfo &RegInfo = F->getRegInfo();
4531 unsigned TmpReg = (!BinOpcode) ? incr :
4532 RegInfo.createVirtualRegister(
4533 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4534 (const TargetRegisterClass *) &PPC::GPRCRegClass);
4538 // fallthrough --> loopMBB
4539 BB->addSuccessor(loopMBB);
4542 // l[wd]arx dest, ptr
4543 // add r0, dest, incr
4544 // st[wd]cx. r0, ptr
4546 // fallthrough --> exitMBB
4548 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
4549 .addReg(ptrA).addReg(ptrB);
4551 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
4552 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4553 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
4554 BuildMI(BB, dl, TII->get(PPC::BCC))
4555 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
4556 BB->addSuccessor(loopMBB);
4557 BB->addSuccessor(exitMBB);
4566 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
4567 MachineBasicBlock *BB,
4568 bool is8bit, // operation
4569 unsigned BinOpcode) const {
4570 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4571 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4572 // In 64 bit mode we have to use 64 bits for addresses, even though the
4573 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
4574 // registers without caring whether they're 32 or 64, but here we're
4575 // doing actual arithmetic on the addresses.
4576 bool is64bit = PPCSubTarget.isPPC64();
4578 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4579 MachineFunction *F = BB->getParent();
4580 MachineFunction::iterator It = BB;
4583 unsigned dest = MI->getOperand(0).getReg();
4584 unsigned ptrA = MI->getOperand(1).getReg();
4585 unsigned ptrB = MI->getOperand(2).getReg();
4586 unsigned incr = MI->getOperand(3).getReg();
4587 DebugLoc dl = MI->getDebugLoc();
4589 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
4590 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4591 F->insert(It, loopMBB);
4592 F->insert(It, exitMBB);
4593 exitMBB->splice(exitMBB->begin(), BB,
4594 llvm::next(MachineBasicBlock::iterator(MI)),
4596 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4598 MachineRegisterInfo &RegInfo = F->getRegInfo();
4599 const TargetRegisterClass *RC =
4600 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4601 (const TargetRegisterClass *) &PPC::GPRCRegClass;
4602 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
4603 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
4604 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
4605 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
4606 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
4607 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
4608 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
4609 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
4610 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
4611 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
4612 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
4614 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
4618 // fallthrough --> loopMBB
4619 BB->addSuccessor(loopMBB);
4621 // The 4-byte load must be aligned, while a char or short may be
4622 // anywhere in the word. Hence all this nasty bookkeeping code.
4623 // add ptr1, ptrA, ptrB [copy if ptrA==0]
4624 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
4625 // xori shift, shift1, 24 [16]
4626 // rlwinm ptr, ptr1, 0, 0, 29
4627 // slw incr2, incr, shift
4628 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
4629 // slw mask, mask2, shift
4631 // lwarx tmpDest, ptr
4632 // add tmp, tmpDest, incr2
4633 // andc tmp2, tmpDest, mask
4634 // and tmp3, tmp, mask
4635 // or tmp4, tmp3, tmp2
4638 // fallthrough --> exitMBB
4639 // srw dest, tmpDest, shift
4641 if (ptrA!=PPC::R0) {
4642 Ptr1Reg = RegInfo.createVirtualRegister(RC);
4643 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
4644 .addReg(ptrA).addReg(ptrB);
4648 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
4649 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
4650 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
4651 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
4653 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
4654 .addReg(Ptr1Reg).addImm(0).addImm(61);
4656 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
4657 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
4658 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
4659 .addReg(incr).addReg(ShiftReg);
4661 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
4663 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
4664 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
4666 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
4667 .addReg(Mask2Reg).addReg(ShiftReg);
4670 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
4671 .addReg(PPC::R0).addReg(PtrReg);
4673 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
4674 .addReg(Incr2Reg).addReg(TmpDestReg);
4675 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
4676 .addReg(TmpDestReg).addReg(MaskReg);
4677 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
4678 .addReg(TmpReg).addReg(MaskReg);
4679 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
4680 .addReg(Tmp3Reg).addReg(Tmp2Reg);
4681 BuildMI(BB, dl, TII->get(PPC::STWCX))
4682 .addReg(Tmp4Reg).addReg(PPC::R0).addReg(PtrReg);
4683 BuildMI(BB, dl, TII->get(PPC::BCC))
4684 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
4685 BB->addSuccessor(loopMBB);
4686 BB->addSuccessor(exitMBB);
4691 BuildMI(BB, dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg).addReg(ShiftReg);
4696 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4697 MachineBasicBlock *BB) const {
4698 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4700 // To "insert" these instructions we actually have to insert their
4701 // control-flow patterns.
4702 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4703 MachineFunction::iterator It = BB;
4706 MachineFunction *F = BB->getParent();
4708 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
4709 MI->getOpcode() == PPC::SELECT_CC_I8 ||
4710 MI->getOpcode() == PPC::SELECT_CC_F4 ||
4711 MI->getOpcode() == PPC::SELECT_CC_F8 ||
4712 MI->getOpcode() == PPC::SELECT_CC_VRRC) {
4714 // The incoming instruction knows the destination vreg to set, the
4715 // condition code register to branch on, the true/false values to
4716 // select between, and a branch opcode to use.
4721 // cmpTY ccX, r1, r2
4723 // fallthrough --> copy0MBB
4724 MachineBasicBlock *thisMBB = BB;
4725 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4726 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4727 unsigned SelectPred = MI->getOperand(4).getImm();
4728 DebugLoc dl = MI->getDebugLoc();
4729 F->insert(It, copy0MBB);
4730 F->insert(It, sinkMBB);
4732 // Transfer the remainder of BB and its successor edges to sinkMBB.
4733 sinkMBB->splice(sinkMBB->begin(), BB,
4734 llvm::next(MachineBasicBlock::iterator(MI)),
4736 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
4738 // Next, add the true and fallthrough blocks as its successors.
4739 BB->addSuccessor(copy0MBB);
4740 BB->addSuccessor(sinkMBB);
4742 BuildMI(BB, dl, TII->get(PPC::BCC))
4743 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
4746 // %FalseValue = ...
4747 // # fallthrough to sinkMBB
4750 // Update machine-CFG edges
4751 BB->addSuccessor(sinkMBB);
4754 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4757 BuildMI(*BB, BB->begin(), dl,
4758 TII->get(PPC::PHI), MI->getOperand(0).getReg())
4759 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
4760 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4762 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
4763 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
4764 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
4765 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
4766 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
4767 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
4768 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
4769 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
4771 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
4772 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
4773 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
4774 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
4775 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
4776 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
4777 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
4778 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
4780 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
4781 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
4782 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
4783 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
4784 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
4785 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
4786 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
4787 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
4789 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
4790 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
4791 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
4792 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
4793 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
4794 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
4795 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
4796 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
4798 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
4799 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
4800 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
4801 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
4802 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
4803 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
4804 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
4805 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
4807 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
4808 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
4809 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
4810 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
4811 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
4812 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
4813 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
4814 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
4816 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
4817 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
4818 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
4819 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
4820 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
4821 BB = EmitAtomicBinary(MI, BB, false, 0);
4822 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
4823 BB = EmitAtomicBinary(MI, BB, true, 0);
4825 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
4826 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
4827 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
4829 unsigned dest = MI->getOperand(0).getReg();
4830 unsigned ptrA = MI->getOperand(1).getReg();
4831 unsigned ptrB = MI->getOperand(2).getReg();
4832 unsigned oldval = MI->getOperand(3).getReg();
4833 unsigned newval = MI->getOperand(4).getReg();
4834 DebugLoc dl = MI->getDebugLoc();
4836 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
4837 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
4838 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
4839 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4840 F->insert(It, loop1MBB);
4841 F->insert(It, loop2MBB);
4842 F->insert(It, midMBB);
4843 F->insert(It, exitMBB);
4844 exitMBB->splice(exitMBB->begin(), BB,
4845 llvm::next(MachineBasicBlock::iterator(MI)),
4847 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4851 // fallthrough --> loopMBB
4852 BB->addSuccessor(loop1MBB);
4855 // l[wd]arx dest, ptr
4856 // cmp[wd] dest, oldval
4859 // st[wd]cx. newval, ptr
4863 // st[wd]cx. dest, ptr
4866 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
4867 .addReg(ptrA).addReg(ptrB);
4868 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
4869 .addReg(oldval).addReg(dest);
4870 BuildMI(BB, dl, TII->get(PPC::BCC))
4871 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
4872 BB->addSuccessor(loop2MBB);
4873 BB->addSuccessor(midMBB);
4876 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4877 .addReg(newval).addReg(ptrA).addReg(ptrB);
4878 BuildMI(BB, dl, TII->get(PPC::BCC))
4879 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
4880 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
4881 BB->addSuccessor(loop1MBB);
4882 BB->addSuccessor(exitMBB);
4885 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4886 .addReg(dest).addReg(ptrA).addReg(ptrB);
4887 BB->addSuccessor(exitMBB);
4892 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
4893 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
4894 // We must use 64-bit registers for addresses when targeting 64-bit,
4895 // since we're actually doing arithmetic on them. Other registers
4897 bool is64bit = PPCSubTarget.isPPC64();
4898 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
4900 unsigned dest = MI->getOperand(0).getReg();
4901 unsigned ptrA = MI->getOperand(1).getReg();
4902 unsigned ptrB = MI->getOperand(2).getReg();
4903 unsigned oldval = MI->getOperand(3).getReg();
4904 unsigned newval = MI->getOperand(4).getReg();
4905 DebugLoc dl = MI->getDebugLoc();
4907 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
4908 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
4909 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
4910 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4911 F->insert(It, loop1MBB);
4912 F->insert(It, loop2MBB);
4913 F->insert(It, midMBB);
4914 F->insert(It, exitMBB);
4915 exitMBB->splice(exitMBB->begin(), BB,
4916 llvm::next(MachineBasicBlock::iterator(MI)),
4918 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4920 MachineRegisterInfo &RegInfo = F->getRegInfo();
4921 const TargetRegisterClass *RC =
4922 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4923 (const TargetRegisterClass *) &PPC::GPRCRegClass;
4924 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
4925 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
4926 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
4927 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
4928 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
4929 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
4930 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
4931 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
4932 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
4933 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
4934 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
4935 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
4936 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
4938 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
4941 // fallthrough --> loopMBB
4942 BB->addSuccessor(loop1MBB);
4944 // The 4-byte load must be aligned, while a char or short may be
4945 // anywhere in the word. Hence all this nasty bookkeeping code.
4946 // add ptr1, ptrA, ptrB [copy if ptrA==0]
4947 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
4948 // xori shift, shift1, 24 [16]
4949 // rlwinm ptr, ptr1, 0, 0, 29
4950 // slw newval2, newval, shift
4951 // slw oldval2, oldval,shift
4952 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
4953 // slw mask, mask2, shift
4954 // and newval3, newval2, mask
4955 // and oldval3, oldval2, mask
4957 // lwarx tmpDest, ptr
4958 // and tmp, tmpDest, mask
4959 // cmpw tmp, oldval3
4962 // andc tmp2, tmpDest, mask
4963 // or tmp4, tmp2, newval3
4968 // stwcx. tmpDest, ptr
4970 // srw dest, tmpDest, shift
4971 if (ptrA!=PPC::R0) {
4972 Ptr1Reg = RegInfo.createVirtualRegister(RC);
4973 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
4974 .addReg(ptrA).addReg(ptrB);
4978 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
4979 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
4980 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
4981 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
4983 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
4984 .addReg(Ptr1Reg).addImm(0).addImm(61);
4986 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
4987 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
4988 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
4989 .addReg(newval).addReg(ShiftReg);
4990 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
4991 .addReg(oldval).addReg(ShiftReg);
4993 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
4995 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
4996 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
4997 .addReg(Mask3Reg).addImm(65535);
4999 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
5000 .addReg(Mask2Reg).addReg(ShiftReg);
5001 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
5002 .addReg(NewVal2Reg).addReg(MaskReg);
5003 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
5004 .addReg(OldVal2Reg).addReg(MaskReg);
5007 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
5008 .addReg(PPC::R0).addReg(PtrReg);
5009 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
5010 .addReg(TmpDestReg).addReg(MaskReg);
5011 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
5012 .addReg(TmpReg).addReg(OldVal3Reg);
5013 BuildMI(BB, dl, TII->get(PPC::BCC))
5014 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
5015 BB->addSuccessor(loop2MBB);
5016 BB->addSuccessor(midMBB);
5019 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
5020 .addReg(TmpDestReg).addReg(MaskReg);
5021 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
5022 .addReg(Tmp2Reg).addReg(NewVal3Reg);
5023 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
5024 .addReg(PPC::R0).addReg(PtrReg);
5025 BuildMI(BB, dl, TII->get(PPC::BCC))
5026 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
5027 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
5028 BB->addSuccessor(loop1MBB);
5029 BB->addSuccessor(exitMBB);
5032 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
5033 .addReg(PPC::R0).addReg(PtrReg);
5034 BB->addSuccessor(exitMBB);
5039 BuildMI(BB, dl, TII->get(PPC::SRW),dest).addReg(TmpReg).addReg(ShiftReg);
5041 llvm_unreachable("Unexpected instr type to insert");
5044 MI->eraseFromParent(); // The pseudo instruction is gone now.
5048 //===----------------------------------------------------------------------===//
5049 // Target Optimization Hooks
5050 //===----------------------------------------------------------------------===//
5052 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
5053 DAGCombinerInfo &DCI) const {
5054 const TargetMachine &TM = getTargetMachine();
5055 SelectionDAG &DAG = DCI.DAG;
5056 DebugLoc dl = N->getDebugLoc();
5057 switch (N->getOpcode()) {
5060 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
5061 if (C->isNullValue()) // 0 << V -> 0.
5062 return N->getOperand(0);
5066 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
5067 if (C->isNullValue()) // 0 >>u V -> 0.
5068 return N->getOperand(0);
5072 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
5073 if (C->isNullValue() || // 0 >>s V -> 0.
5074 C->isAllOnesValue()) // -1 >>s V -> -1.
5075 return N->getOperand(0);
5079 case ISD::SINT_TO_FP:
5080 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
5081 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
5082 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
5083 // We allow the src/dst to be either f32/f64, but the intermediate
5084 // type must be i64.
5085 if (N->getOperand(0).getValueType() == MVT::i64 &&
5086 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
5087 SDValue Val = N->getOperand(0).getOperand(0);
5088 if (Val.getValueType() == MVT::f32) {
5089 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
5090 DCI.AddToWorklist(Val.getNode());
5093 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
5094 DCI.AddToWorklist(Val.getNode());
5095 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
5096 DCI.AddToWorklist(Val.getNode());
5097 if (N->getValueType(0) == MVT::f32) {
5098 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
5099 DAG.getIntPtrConstant(0));
5100 DCI.AddToWorklist(Val.getNode());
5103 } else if (N->getOperand(0).getValueType() == MVT::i32) {
5104 // If the intermediate type is i32, we can avoid the load/store here
5111 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
5112 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
5113 !cast<StoreSDNode>(N)->isTruncatingStore() &&
5114 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
5115 N->getOperand(1).getValueType() == MVT::i32 &&
5116 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
5117 SDValue Val = N->getOperand(1).getOperand(0);
5118 if (Val.getValueType() == MVT::f32) {
5119 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
5120 DCI.AddToWorklist(Val.getNode());
5122 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
5123 DCI.AddToWorklist(Val.getNode());
5125 Val = DAG.getNode(PPCISD::STFIWX, dl, MVT::Other, N->getOperand(0), Val,
5126 N->getOperand(2), N->getOperand(3));
5127 DCI.AddToWorklist(Val.getNode());
5131 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
5132 if (cast<StoreSDNode>(N)->isUnindexed() &&
5133 N->getOperand(1).getOpcode() == ISD::BSWAP &&
5134 N->getOperand(1).getNode()->hasOneUse() &&
5135 (N->getOperand(1).getValueType() == MVT::i32 ||
5136 N->getOperand(1).getValueType() == MVT::i16)) {
5137 SDValue BSwapOp = N->getOperand(1).getOperand(0);
5138 // Do an any-extend to 32-bits if this is a half-word input.
5139 if (BSwapOp.getValueType() == MVT::i16)
5140 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
5143 N->getOperand(0), BSwapOp, N->getOperand(2),
5144 DAG.getValueType(N->getOperand(1).getValueType())
5147 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
5148 Ops, array_lengthof(Ops),
5149 cast<StoreSDNode>(N)->getMemoryVT(),
5150 cast<StoreSDNode>(N)->getMemOperand());
5154 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
5155 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
5156 N->getOperand(0).hasOneUse() &&
5157 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
5158 SDValue Load = N->getOperand(0);
5159 LoadSDNode *LD = cast<LoadSDNode>(Load);
5160 // Create the byte-swapping load.
5162 LD->getChain(), // Chain
5163 LD->getBasePtr(), // Ptr
5164 DAG.getValueType(N->getValueType(0)) // VT
5167 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
5168 DAG.getVTList(MVT::i32, MVT::Other), Ops, 3,
5169 LD->getMemoryVT(), LD->getMemOperand());
5171 // If this is an i16 load, insert the truncate.
5172 SDValue ResVal = BSLoad;
5173 if (N->getValueType(0) == MVT::i16)
5174 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
5176 // First, combine the bswap away. This makes the value produced by the
5178 DCI.CombineTo(N, ResVal);
5180 // Next, combine the load away, we give it a bogus result value but a real
5181 // chain result. The result value is dead because the bswap is dead.
5182 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
5184 // Return N so it doesn't get rechecked!
5185 return SDValue(N, 0);
5189 case PPCISD::VCMP: {
5190 // If a VCMPo node already exists with exactly the same operands as this
5191 // node, use its result instead of this node (VCMPo computes both a CR6 and
5192 // a normal output).
5194 if (!N->getOperand(0).hasOneUse() &&
5195 !N->getOperand(1).hasOneUse() &&
5196 !N->getOperand(2).hasOneUse()) {
5198 // Scan all of the users of the LHS, looking for VCMPo's that match.
5199 SDNode *VCMPoNode = 0;
5201 SDNode *LHSN = N->getOperand(0).getNode();
5202 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
5204 if (UI->getOpcode() == PPCISD::VCMPo &&
5205 UI->getOperand(1) == N->getOperand(1) &&
5206 UI->getOperand(2) == N->getOperand(2) &&
5207 UI->getOperand(0) == N->getOperand(0)) {
5212 // If there is no VCMPo node, or if the flag value has a single use, don't
5214 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
5217 // Look at the (necessarily single) use of the flag value. If it has a
5218 // chain, this transformation is more complex. Note that multiple things
5219 // could use the value result, which we should ignore.
5220 SDNode *FlagUser = 0;
5221 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
5222 FlagUser == 0; ++UI) {
5223 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
5225 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
5226 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
5233 // If the user is a MFCR instruction, we know this is safe. Otherwise we
5234 // give up for right now.
5235 if (FlagUser->getOpcode() == PPCISD::MFCR)
5236 return SDValue(VCMPoNode, 0);
5241 // If this is a branch on an altivec predicate comparison, lower this so
5242 // that we don't have to do a MFCR: instead, branch directly on CR6. This
5243 // lowering is done pre-legalize, because the legalizer lowers the predicate
5244 // compare down to code that is difficult to reassemble.
5245 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
5246 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
5250 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
5251 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
5252 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
5253 assert(isDot && "Can't compare against a vector result!");
5255 // If this is a comparison against something other than 0/1, then we know
5256 // that the condition is never/always true.
5257 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
5258 if (Val != 0 && Val != 1) {
5259 if (CC == ISD::SETEQ) // Cond never true, remove branch.
5260 return N->getOperand(0);
5261 // Always !=, turn it into an unconditional branch.
5262 return DAG.getNode(ISD::BR, dl, MVT::Other,
5263 N->getOperand(0), N->getOperand(4));
5266 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
5268 // Create the PPCISD altivec 'dot' comparison node.
5269 std::vector<EVT> VTs;
5271 LHS.getOperand(2), // LHS of compare
5272 LHS.getOperand(3), // RHS of compare
5273 DAG.getConstant(CompareOpc, MVT::i32)
5275 VTs.push_back(LHS.getOperand(2).getValueType());
5276 VTs.push_back(MVT::Flag);
5277 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
5279 // Unpack the result based on how the target uses it.
5280 PPC::Predicate CompOpc;
5281 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
5282 default: // Can't happen, don't crash on invalid number though.
5283 case 0: // Branch on the value of the EQ bit of CR6.
5284 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
5286 case 1: // Branch on the inverted value of the EQ bit of CR6.
5287 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
5289 case 2: // Branch on the value of the LT bit of CR6.
5290 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
5292 case 3: // Branch on the inverted value of the LT bit of CR6.
5293 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
5297 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
5298 DAG.getConstant(CompOpc, MVT::i32),
5299 DAG.getRegister(PPC::CR6, MVT::i32),
5300 N->getOperand(4), CompNode.getValue(1));
5309 //===----------------------------------------------------------------------===//
5310 // Inline Assembly Support
5311 //===----------------------------------------------------------------------===//
5313 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
5317 const SelectionDAG &DAG,
5318 unsigned Depth) const {
5319 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
5320 switch (Op.getOpcode()) {
5322 case PPCISD::LBRX: {
5323 // lhbrx is known to have the top bits cleared out.
5324 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
5325 KnownZero = 0xFFFF0000;
5328 case ISD::INTRINSIC_WO_CHAIN: {
5329 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
5331 case Intrinsic::ppc_altivec_vcmpbfp_p:
5332 case Intrinsic::ppc_altivec_vcmpeqfp_p:
5333 case Intrinsic::ppc_altivec_vcmpequb_p:
5334 case Intrinsic::ppc_altivec_vcmpequh_p:
5335 case Intrinsic::ppc_altivec_vcmpequw_p:
5336 case Intrinsic::ppc_altivec_vcmpgefp_p:
5337 case Intrinsic::ppc_altivec_vcmpgtfp_p:
5338 case Intrinsic::ppc_altivec_vcmpgtsb_p:
5339 case Intrinsic::ppc_altivec_vcmpgtsh_p:
5340 case Intrinsic::ppc_altivec_vcmpgtsw_p:
5341 case Intrinsic::ppc_altivec_vcmpgtub_p:
5342 case Intrinsic::ppc_altivec_vcmpgtuh_p:
5343 case Intrinsic::ppc_altivec_vcmpgtuw_p:
5344 KnownZero = ~1U; // All bits but the low one are known to be zero.
5352 /// getConstraintType - Given a constraint, return the type of
5353 /// constraint it is for this target.
5354 PPCTargetLowering::ConstraintType
5355 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
5356 if (Constraint.size() == 1) {
5357 switch (Constraint[0]) {
5364 return C_RegisterClass;
5367 return TargetLowering::getConstraintType(Constraint);
5370 /// Examine constraint type and operand type and determine a weight value.
5371 /// This object must already have been set up with the operand type
5372 /// and the current alternative constraint selected.
5373 TargetLowering::ConstraintWeight
5374 PPCTargetLowering::getSingleConstraintMatchWeight(
5375 AsmOperandInfo &info, const char *constraint) const {
5376 ConstraintWeight weight = CW_Invalid;
5377 Value *CallOperandVal = info.CallOperandVal;
5378 // If we don't have a value, we can't do a match,
5379 // but allow it at the lowest weight.
5380 if (CallOperandVal == NULL)
5382 const Type *type = CallOperandVal->getType();
5383 // Look at the constraint type.
5384 switch (*constraint) {
5386 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
5389 if (type->isIntegerTy())
5390 weight = CW_Register;
5393 if (type->isFloatTy())
5394 weight = CW_Register;
5397 if (type->isDoubleTy())
5398 weight = CW_Register;
5401 if (type->isVectorTy())
5402 weight = CW_Register;
5405 weight = CW_Register;
5411 std::pair<unsigned, const TargetRegisterClass*>
5412 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
5414 if (Constraint.size() == 1) {
5415 // GCC RS6000 Constraint Letters
5416 switch (Constraint[0]) {
5419 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
5420 return std::make_pair(0U, PPC::G8RCRegisterClass);
5421 return std::make_pair(0U, PPC::GPRCRegisterClass);
5424 return std::make_pair(0U, PPC::F4RCRegisterClass);
5425 else if (VT == MVT::f64)
5426 return std::make_pair(0U, PPC::F8RCRegisterClass);
5429 return std::make_pair(0U, PPC::VRRCRegisterClass);
5431 return std::make_pair(0U, PPC::CRRCRegisterClass);
5435 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
5439 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
5440 /// vector. If it is invalid, don't add anything to Ops.
5441 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, char Letter,
5442 std::vector<SDValue>&Ops,
5443 SelectionDAG &DAG) const {
5444 SDValue Result(0,0);
5455 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
5456 if (!CST) return; // Must be an immediate to match.
5457 unsigned Value = CST->getZExtValue();
5459 default: llvm_unreachable("Unknown constraint letter!");
5460 case 'I': // "I" is a signed 16-bit constant.
5461 if ((short)Value == (int)Value)
5462 Result = DAG.getTargetConstant(Value, Op.getValueType());
5464 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
5465 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
5466 if ((short)Value == 0)
5467 Result = DAG.getTargetConstant(Value, Op.getValueType());
5469 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
5470 if ((Value >> 16) == 0)
5471 Result = DAG.getTargetConstant(Value, Op.getValueType());
5473 case 'M': // "M" is a constant that is greater than 31.
5475 Result = DAG.getTargetConstant(Value, Op.getValueType());
5477 case 'N': // "N" is a positive constant that is an exact power of two.
5478 if ((int)Value > 0 && isPowerOf2_32(Value))
5479 Result = DAG.getTargetConstant(Value, Op.getValueType());
5481 case 'O': // "O" is the constant zero.
5483 Result = DAG.getTargetConstant(Value, Op.getValueType());
5485 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
5486 if ((short)-Value == (int)-Value)
5487 Result = DAG.getTargetConstant(Value, Op.getValueType());
5494 if (Result.getNode()) {
5495 Ops.push_back(Result);
5499 // Handle standard constraint letters.
5500 TargetLowering::LowerAsmOperandForConstraint(Op, Letter, Ops, DAG);
5503 // isLegalAddressingMode - Return true if the addressing mode represented
5504 // by AM is legal for this target, for a load/store of the specified type.
5505 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
5506 const Type *Ty) const {
5507 // FIXME: PPC does not allow r+i addressing modes for vectors!
5509 // PPC allows a sign-extended 16-bit immediate field.
5510 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
5513 // No global is ever allowed as a base.
5517 // PPC only support r+r,
5519 case 0: // "r+i" or just "i", depending on HasBaseReg.
5522 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
5524 // Otherwise we have r+r or r+i.
5527 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
5529 // Allow 2*r as r+r.
5532 // No other scales are supported.
5539 /// isLegalAddressImmediate - Return true if the integer value can be used
5540 /// as the offset of the target addressing mode for load / store of the
5542 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{
5543 // PPC allows a sign-extended 16-bit immediate field.
5544 return (V > -(1 << 16) && V < (1 << 16)-1);
5547 bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
5551 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
5552 SelectionDAG &DAG) const {
5553 MachineFunction &MF = DAG.getMachineFunction();
5554 MachineFrameInfo *MFI = MF.getFrameInfo();
5555 MFI->setReturnAddressIsTaken(true);
5557 DebugLoc dl = Op.getDebugLoc();
5558 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5560 // Make sure the function does not optimize away the store of the RA to
5562 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
5563 FuncInfo->setLRStoreRequired();
5564 bool isPPC64 = PPCSubTarget.isPPC64();
5565 bool isDarwinABI = PPCSubTarget.isDarwinABI();
5568 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
5571 DAG.getConstant(PPCFrameInfo::getReturnSaveOffset(isPPC64, isDarwinABI),
5572 isPPC64? MVT::i64 : MVT::i32);
5573 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
5574 DAG.getNode(ISD::ADD, dl, getPointerTy(),
5576 MachinePointerInfo(), false, false, 0);
5579 // Just load the return address off the stack.
5580 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
5581 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
5582 RetAddrFI, MachinePointerInfo(), false, false, 0);
5585 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
5586 SelectionDAG &DAG) const {
5587 DebugLoc dl = Op.getDebugLoc();
5588 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5590 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5591 bool isPPC64 = PtrVT == MVT::i64;
5593 MachineFunction &MF = DAG.getMachineFunction();
5594 MachineFrameInfo *MFI = MF.getFrameInfo();
5595 MFI->setFrameAddressIsTaken(true);
5596 bool is31 = (DisableFramePointerElim(MF) || MFI->hasVarSizedObjects()) &&
5597 MFI->getStackSize() &&
5598 !MF.getFunction()->hasFnAttr(Attribute::Naked);
5599 unsigned FrameReg = isPPC64 ? (is31 ? PPC::X31 : PPC::X1) :
5600 (is31 ? PPC::R31 : PPC::R1);
5601 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
5604 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
5605 FrameAddr, MachinePointerInfo(), false, false, 0);
5610 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
5611 // The PowerPC target isn't yet aware of offsets.
5615 /// getOptimalMemOpType - Returns the target specific optimal type for load
5616 /// and store operations as a result of memset, memcpy, and memmove
5617 /// lowering. If DstAlign is zero that means it's safe to destination
5618 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
5619 /// means there isn't a need to check it against alignment requirement,
5620 /// probably because the source does not need to be loaded. If
5621 /// 'NonScalarIntSafe' is true, that means it's safe to return a
5622 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
5623 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
5624 /// constant so it does not need to be loaded.
5625 /// It returns EVT::Other if the type should be determined using generic
5626 /// target-independent logic.
5627 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
5628 unsigned DstAlign, unsigned SrcAlign,
5629 bool NonScalarIntSafe,
5631 MachineFunction &MF) const {
5632 if (this->PPCSubTarget.isPPC64()) {