1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCTargetMachine.h"
16 #include "PPCPerfectShuffle.h"
17 #include "llvm/ADT/VectorExtras.h"
18 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SSARegMap.h"
24 #include "llvm/Constants.h"
25 #include "llvm/Function.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/Target/TargetOptions.h"
29 #include "llvm/Support/CommandLine.h"
32 static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc");
34 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
35 : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) {
37 // Fold away setcc operations if possible.
38 setSetCCIsExpensive();
41 // Use _setjmp/_longjmp instead of setjmp/longjmp.
42 setUseUnderscoreSetJmpLongJmp(true);
44 // Set up the register classes.
45 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
46 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
47 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
49 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
50 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand);
51 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand);
53 // PowerPC does not have truncstore for i1.
54 setStoreXAction(MVT::i1, Promote);
56 // PowerPC has pre-inc load and store's.
57 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
58 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
59 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
60 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
61 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
62 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
63 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
64 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
65 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
66 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
68 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
69 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
71 // PowerPC has no intrinsics for these particular operations
72 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
73 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
74 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
76 // PowerPC has no SREM/UREM instructions
77 setOperationAction(ISD::SREM, MVT::i32, Expand);
78 setOperationAction(ISD::UREM, MVT::i32, Expand);
79 setOperationAction(ISD::SREM, MVT::i64, Expand);
80 setOperationAction(ISD::UREM, MVT::i64, Expand);
82 // We don't support sin/cos/sqrt/fmod
83 setOperationAction(ISD::FSIN , MVT::f64, Expand);
84 setOperationAction(ISD::FCOS , MVT::f64, Expand);
85 setOperationAction(ISD::FREM , MVT::f64, Expand);
86 setOperationAction(ISD::FSIN , MVT::f32, Expand);
87 setOperationAction(ISD::FCOS , MVT::f32, Expand);
88 setOperationAction(ISD::FREM , MVT::f32, Expand);
90 // If we're enabling GP optimizations, use hardware square root
91 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
92 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
93 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
96 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
97 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
99 // PowerPC does not have BSWAP, CTPOP or CTTZ
100 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
101 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
102 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
103 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
104 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
105 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
107 // PowerPC does not have ROTR
108 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
110 // PowerPC does not have Select
111 setOperationAction(ISD::SELECT, MVT::i32, Expand);
112 setOperationAction(ISD::SELECT, MVT::i64, Expand);
113 setOperationAction(ISD::SELECT, MVT::f32, Expand);
114 setOperationAction(ISD::SELECT, MVT::f64, Expand);
116 // PowerPC wants to turn select_cc of FP into fsel when possible.
117 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
118 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
120 // PowerPC wants to optimize integer setcc a bit
121 setOperationAction(ISD::SETCC, MVT::i32, Custom);
123 // PowerPC does not have BRCOND which requires SetCC
124 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
126 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
128 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
129 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
131 // PowerPC does not have [U|S]INT_TO_FP
132 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
133 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
135 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
136 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
137 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
138 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
140 // We cannot sextinreg(i1). Expand to shifts.
141 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
144 // Support label based line numbers.
145 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
146 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
147 // FIXME - use subtarget debug flags
148 if (!TM.getSubtarget<PPCSubtarget>().isDarwin())
149 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
151 // We want to legalize GlobalAddress and ConstantPool nodes into the
152 // appropriate instructions to materialize the address.
153 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
154 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
155 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
156 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
157 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
158 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
160 // RET must be custom lowered, to meet ABI requirements
161 setOperationAction(ISD::RET , MVT::Other, Custom);
163 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
164 setOperationAction(ISD::VASTART , MVT::Other, Custom);
166 // Use the default implementation.
167 setOperationAction(ISD::VAARG , MVT::Other, Expand);
168 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
169 setOperationAction(ISD::VAEND , MVT::Other, Expand);
170 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
171 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
172 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
173 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Expand);
175 // We want to custom lower some of our intrinsics.
176 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
178 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
179 // They also have instructions for converting between i64 and fp.
180 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
181 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
183 // FIXME: disable this lowered code. This generates 64-bit register values,
184 // and we don't model the fact that the top part is clobbered by calls. We
185 // need to flag these together so that the value isn't live across a call.
186 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
188 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
189 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
191 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
192 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
195 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
196 // 64 bit PowerPC implementations can support i64 types directly
197 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
198 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
199 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
201 // 32 bit PowerPC wants to expand i64 shifts itself.
202 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
203 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
204 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
207 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
208 // First set operation action for all vector types to expand. Then we
209 // will selectively turn on ones that can be effectively codegen'd.
210 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
211 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
212 // add/sub are legal for all supported vector VT's.
213 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal);
214 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal);
216 // We promote all shuffles to v16i8.
217 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote);
218 AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8);
220 // We promote all non-typed operations to v4i32.
221 setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote);
222 AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32);
223 setOperationAction(ISD::OR , (MVT::ValueType)VT, Promote);
224 AddPromotedToType (ISD::OR , (MVT::ValueType)VT, MVT::v4i32);
225 setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote);
226 AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32);
227 setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote);
228 AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32);
229 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
230 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32);
231 setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote);
232 AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32);
234 // No other operations are legal.
235 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
236 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
237 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
238 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
239 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
240 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
241 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
242 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
243 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
245 setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand);
248 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
249 // with merges, splats, etc.
250 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
252 setOperationAction(ISD::AND , MVT::v4i32, Legal);
253 setOperationAction(ISD::OR , MVT::v4i32, Legal);
254 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
255 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
256 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
257 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
259 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
260 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
261 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
262 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
264 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
265 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
266 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
267 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
269 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
270 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
272 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
273 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
274 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
275 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
278 setSetCCResultType(MVT::i32);
279 setShiftAmountType(MVT::i32);
280 setSetCCResultContents(ZeroOrOneSetCCResult);
282 if (TM.getSubtarget<PPCSubtarget>().isPPC64())
283 setStackPointerRegisterToSaveRestore(PPC::X1);
285 setStackPointerRegisterToSaveRestore(PPC::R1);
287 // We have target-specific dag combine patterns for the following nodes:
288 setTargetDAGCombine(ISD::SINT_TO_FP);
289 setTargetDAGCombine(ISD::STORE);
290 setTargetDAGCombine(ISD::BR_CC);
291 setTargetDAGCombine(ISD::BSWAP);
293 computeRegisterProperties();
296 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
299 case PPCISD::FSEL: return "PPCISD::FSEL";
300 case PPCISD::FCFID: return "PPCISD::FCFID";
301 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
302 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
303 case PPCISD::STFIWX: return "PPCISD::STFIWX";
304 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
305 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
306 case PPCISD::VPERM: return "PPCISD::VPERM";
307 case PPCISD::Hi: return "PPCISD::Hi";
308 case PPCISD::Lo: return "PPCISD::Lo";
309 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
310 case PPCISD::SRL: return "PPCISD::SRL";
311 case PPCISD::SRA: return "PPCISD::SRA";
312 case PPCISD::SHL: return "PPCISD::SHL";
313 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
314 case PPCISD::STD_32: return "PPCISD::STD_32";
315 case PPCISD::CALL: return "PPCISD::CALL";
316 case PPCISD::MTCTR: return "PPCISD::MTCTR";
317 case PPCISD::BCTRL: return "PPCISD::BCTRL";
318 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
319 case PPCISD::MFCR: return "PPCISD::MFCR";
320 case PPCISD::VCMP: return "PPCISD::VCMP";
321 case PPCISD::VCMPo: return "PPCISD::VCMPo";
322 case PPCISD::LBRX: return "PPCISD::LBRX";
323 case PPCISD::STBRX: return "PPCISD::STBRX";
324 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
328 //===----------------------------------------------------------------------===//
329 // Node matching predicates, for use by the tblgen matching code.
330 //===----------------------------------------------------------------------===//
332 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
333 static bool isFloatingPointZero(SDOperand Op) {
334 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
335 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
336 else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
337 // Maybe this has already been legalized into the constant pool?
338 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
339 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
340 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
345 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
346 /// true if Op is undef or if it matches the specified value.
347 static bool isConstantOrUndef(SDOperand Op, unsigned Val) {
348 return Op.getOpcode() == ISD::UNDEF ||
349 cast<ConstantSDNode>(Op)->getValue() == Val;
352 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
353 /// VPKUHUM instruction.
354 bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) {
356 for (unsigned i = 0; i != 16; ++i)
357 if (!isConstantOrUndef(N->getOperand(i), i*2+1))
360 for (unsigned i = 0; i != 8; ++i)
361 if (!isConstantOrUndef(N->getOperand(i), i*2+1) ||
362 !isConstantOrUndef(N->getOperand(i+8), i*2+1))
368 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
369 /// VPKUWUM instruction.
370 bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) {
372 for (unsigned i = 0; i != 16; i += 2)
373 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
374 !isConstantOrUndef(N->getOperand(i+1), i*2+3))
377 for (unsigned i = 0; i != 8; i += 2)
378 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
379 !isConstantOrUndef(N->getOperand(i+1), i*2+3) ||
380 !isConstantOrUndef(N->getOperand(i+8), i*2+2) ||
381 !isConstantOrUndef(N->getOperand(i+9), i*2+3))
387 /// isVMerge - Common function, used to match vmrg* shuffles.
389 static bool isVMerge(SDNode *N, unsigned UnitSize,
390 unsigned LHSStart, unsigned RHSStart) {
391 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
392 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
393 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
394 "Unsupported merge size!");
396 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
397 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
398 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j),
399 LHSStart+j+i*UnitSize) ||
400 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j),
401 RHSStart+j+i*UnitSize))
407 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
408 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
409 bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
411 return isVMerge(N, UnitSize, 8, 24);
412 return isVMerge(N, UnitSize, 8, 8);
415 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
416 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
417 bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
419 return isVMerge(N, UnitSize, 0, 16);
420 return isVMerge(N, UnitSize, 0, 0);
424 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
425 /// amount, otherwise return -1.
426 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
427 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
428 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
429 // Find the first non-undef value in the shuffle mask.
431 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i)
434 if (i == 16) return -1; // all undef.
436 // Otherwise, check to see if the rest of the elements are consequtively
437 // numbered from this value.
438 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue();
439 if (ShiftAmt < i) return -1;
443 // Check the rest of the elements to see if they are consequtive.
444 for (++i; i != 16; ++i)
445 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i))
448 // Check the rest of the elements to see if they are consequtive.
449 for (++i; i != 16; ++i)
450 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15))
457 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
458 /// specifies a splat of a single element that is suitable for input to
459 /// VSPLTB/VSPLTH/VSPLTW.
460 bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) {
461 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
462 N->getNumOperands() == 16 &&
463 (EltSize == 1 || EltSize == 2 || EltSize == 4));
465 // This is a splat operation if each element of the permute is the same, and
466 // if the value doesn't reference the second vector.
467 unsigned ElementBase = 0;
468 SDOperand Elt = N->getOperand(0);
469 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt))
470 ElementBase = EltV->getValue();
472 return false; // FIXME: Handle UNDEF elements too!
474 if (cast<ConstantSDNode>(Elt)->getValue() >= 16)
477 // Check that they are consequtive.
478 for (unsigned i = 1; i != EltSize; ++i) {
479 if (!isa<ConstantSDNode>(N->getOperand(i)) ||
480 cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase)
484 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
485 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
486 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
487 assert(isa<ConstantSDNode>(N->getOperand(i)) &&
488 "Invalid VECTOR_SHUFFLE mask!");
489 for (unsigned j = 0; j != EltSize; ++j)
490 if (N->getOperand(i+j) != N->getOperand(j))
497 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
498 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
499 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
500 assert(isSplatShuffleMask(N, EltSize));
501 return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize;
504 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
505 /// by using a vspltis[bhw] instruction of the specified element size, return
506 /// the constant being splatted. The ByteSize field indicates the number of
507 /// bytes of each element [124] -> [bhw].
508 SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
509 SDOperand OpVal(0, 0);
511 // If ByteSize of the splat is bigger than the element size of the
512 // build_vector, then we have a case where we are checking for a splat where
513 // multiple elements of the buildvector are folded together into a single
514 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
515 unsigned EltSize = 16/N->getNumOperands();
516 if (EltSize < ByteSize) {
517 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
518 SDOperand UniquedVals[4];
519 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
521 // See if all of the elements in the buildvector agree across.
522 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
523 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
524 // If the element isn't a constant, bail fully out.
525 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand();
528 if (UniquedVals[i&(Multiple-1)].Val == 0)
529 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
530 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
531 return SDOperand(); // no match.
534 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
535 // either constant or undef values that are identical for each chunk. See
536 // if these chunks can form into a larger vspltis*.
538 // Check to see if all of the leading entries are either 0 or -1. If
539 // neither, then this won't fit into the immediate field.
540 bool LeadingZero = true;
541 bool LeadingOnes = true;
542 for (unsigned i = 0; i != Multiple-1; ++i) {
543 if (UniquedVals[i].Val == 0) continue; // Must have been undefs.
545 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
546 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
548 // Finally, check the least significant entry.
550 if (UniquedVals[Multiple-1].Val == 0)
551 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
552 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue();
554 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
557 if (UniquedVals[Multiple-1].Val == 0)
558 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
559 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended();
560 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
561 return DAG.getTargetConstant(Val, MVT::i32);
567 // Check to see if this buildvec has a single non-undef value in its elements.
568 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
569 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
571 OpVal = N->getOperand(i);
572 else if (OpVal != N->getOperand(i))
576 if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def.
578 unsigned ValSizeInBytes = 0;
580 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
581 Value = CN->getValue();
582 ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8;
583 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
584 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
585 Value = FloatToBits(CN->getValue());
589 // If the splat value is larger than the element value, then we can never do
590 // this splat. The only case that we could fit the replicated bits into our
591 // immediate field for would be zero, and we prefer to use vxor for it.
592 if (ValSizeInBytes < ByteSize) return SDOperand();
594 // If the element value is larger than the splat value, cut it in half and
595 // check to see if the two halves are equal. Continue doing this until we
596 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
597 while (ValSizeInBytes > ByteSize) {
598 ValSizeInBytes >>= 1;
600 // If the top half equals the bottom half, we're still ok.
601 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
602 (Value & ((1 << (8*ValSizeInBytes))-1)))
606 // Properly sign extend the value.
607 int ShAmt = (4-ByteSize)*8;
608 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
610 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
611 if (MaskVal == 0) return SDOperand();
613 // Finally, if this value fits in a 5 bit sext field, return it
614 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
615 return DAG.getTargetConstant(MaskVal, MVT::i32);
619 //===----------------------------------------------------------------------===//
620 // Addressing Mode Selection
621 //===----------------------------------------------------------------------===//
623 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
624 /// or 64-bit immediate, and if the value can be accurately represented as a
625 /// sign extension from a 16-bit value. If so, this returns true and the
627 static bool isIntS16Immediate(SDNode *N, short &Imm) {
628 if (N->getOpcode() != ISD::Constant)
631 Imm = (short)cast<ConstantSDNode>(N)->getValue();
632 if (N->getValueType(0) == MVT::i32)
633 return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue();
635 return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue();
637 static bool isIntS16Immediate(SDOperand Op, short &Imm) {
638 return isIntS16Immediate(Op.Val, Imm);
642 /// SelectAddressRegReg - Given the specified addressed, check to see if it
643 /// can be represented as an indexed [r+r] operation. Returns false if it
644 /// can be more efficiently represented with [r+imm].
645 bool PPCTargetLowering::SelectAddressRegReg(SDOperand N, SDOperand &Base,
649 if (N.getOpcode() == ISD::ADD) {
650 if (isIntS16Immediate(N.getOperand(1), imm))
652 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
655 Base = N.getOperand(0);
656 Index = N.getOperand(1);
658 } else if (N.getOpcode() == ISD::OR) {
659 if (isIntS16Immediate(N.getOperand(1), imm))
660 return false; // r+i can fold it if we can.
662 // If this is an or of disjoint bitfields, we can codegen this as an add
663 // (for better address arithmetic) if the LHS and RHS of the OR are provably
665 uint64_t LHSKnownZero, LHSKnownOne;
666 uint64_t RHSKnownZero, RHSKnownOne;
667 ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne);
670 ComputeMaskedBits(N.getOperand(1), ~0U, RHSKnownZero, RHSKnownOne);
671 // If all of the bits are known zero on the LHS or RHS, the add won't
673 if ((LHSKnownZero | RHSKnownZero) == ~0U) {
674 Base = N.getOperand(0);
675 Index = N.getOperand(1);
684 /// Returns true if the address N can be represented by a base register plus
685 /// a signed 16-bit displacement [r+imm], and if it is not better
686 /// represented as reg+reg.
687 bool PPCTargetLowering::SelectAddressRegImm(SDOperand N, SDOperand &Disp,
688 SDOperand &Base, SelectionDAG &DAG){
689 // If this can be more profitably realized as r+r, fail.
690 if (SelectAddressRegReg(N, Disp, Base, DAG))
693 if (N.getOpcode() == ISD::ADD) {
695 if (isIntS16Immediate(N.getOperand(1), imm)) {
696 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
697 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
698 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
700 Base = N.getOperand(0);
702 return true; // [r+i]
703 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
704 // Match LOAD (ADD (X, Lo(G))).
705 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
706 && "Cannot handle constant offsets yet!");
707 Disp = N.getOperand(1).getOperand(0); // The global address.
708 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
709 Disp.getOpcode() == ISD::TargetConstantPool ||
710 Disp.getOpcode() == ISD::TargetJumpTable);
711 Base = N.getOperand(0);
712 return true; // [&g+r]
714 } else if (N.getOpcode() == ISD::OR) {
716 if (isIntS16Immediate(N.getOperand(1), imm)) {
717 // If this is an or of disjoint bitfields, we can codegen this as an add
718 // (for better address arithmetic) if the LHS and RHS of the OR are
719 // provably disjoint.
720 uint64_t LHSKnownZero, LHSKnownOne;
721 ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne);
722 if ((LHSKnownZero|~(unsigned)imm) == ~0U) {
723 // If all of the bits are known zero on the LHS or RHS, the add won't
725 Base = N.getOperand(0);
726 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
730 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
731 // Loading from a constant address.
733 // If this address fits entirely in a 16-bit sext immediate field, codegen
736 if (isIntS16Immediate(CN, Imm)) {
737 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
738 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
742 // FIXME: Handle small sext constant offsets in PPC64 mode also!
743 if (CN->getValueType(0) == MVT::i32) {
744 int Addr = (int)CN->getValue();
746 // Otherwise, break this down into an LIS + disp.
747 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
748 Base = DAG.getConstant(Addr - (signed short)Addr, MVT::i32);
753 Disp = DAG.getTargetConstant(0, getPointerTy());
754 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
755 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
758 return true; // [r+0]
761 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
762 /// represented as an indexed [r+r] operation.
763 bool PPCTargetLowering::SelectAddressRegRegOnly(SDOperand N, SDOperand &Base,
766 // Check to see if we can easily represent this as an [r+r] address. This
767 // will fail if it thinks that the address is more profitably represented as
768 // reg+imm, e.g. where imm = 0.
769 if (SelectAddressRegReg(N, Base, Index, DAG))
772 // If the operand is an addition, always emit this as [r+r], since this is
773 // better (for code size, and execution, as the memop does the add for free)
774 // than emitting an explicit add.
775 if (N.getOpcode() == ISD::ADD) {
776 Base = N.getOperand(0);
777 Index = N.getOperand(1);
781 // Otherwise, do it the hard way, using R0 as the base register.
782 Base = DAG.getRegister(PPC::R0, N.getValueType());
787 /// SelectAddressRegImmShift - Returns true if the address N can be
788 /// represented by a base register plus a signed 14-bit displacement
789 /// [r+imm*4]. Suitable for use by STD and friends.
790 bool PPCTargetLowering::SelectAddressRegImmShift(SDOperand N, SDOperand &Disp,
793 // If this can be more profitably realized as r+r, fail.
794 if (SelectAddressRegReg(N, Disp, Base, DAG))
797 if (N.getOpcode() == ISD::ADD) {
799 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
800 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
801 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
802 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
804 Base = N.getOperand(0);
806 return true; // [r+i]
807 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
808 // Match LOAD (ADD (X, Lo(G))).
809 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
810 && "Cannot handle constant offsets yet!");
811 Disp = N.getOperand(1).getOperand(0); // The global address.
812 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
813 Disp.getOpcode() == ISD::TargetConstantPool ||
814 Disp.getOpcode() == ISD::TargetJumpTable);
815 Base = N.getOperand(0);
816 return true; // [&g+r]
818 } else if (N.getOpcode() == ISD::OR) {
820 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
821 // If this is an or of disjoint bitfields, we can codegen this as an add
822 // (for better address arithmetic) if the LHS and RHS of the OR are
823 // provably disjoint.
824 uint64_t LHSKnownZero, LHSKnownOne;
825 ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne);
826 if ((LHSKnownZero|~(unsigned)imm) == ~0U) {
827 // If all of the bits are known zero on the LHS or RHS, the add won't
829 Base = N.getOperand(0);
830 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
834 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
835 // Loading from a constant address.
837 // If this address fits entirely in a 14-bit sext immediate field, codegen
840 if (isIntS16Immediate(CN, Imm)) {
841 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
842 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
846 // FIXME: Handle small sext constant offsets in PPC64 mode also!
847 if (CN->getValueType(0) == MVT::i32) {
848 int Addr = (int)CN->getValue();
850 // Otherwise, break this down into an LIS + disp.
851 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
852 Base = DAG.getConstant(Addr - (signed short)Addr, MVT::i32);
857 Disp = DAG.getTargetConstant(0, getPointerTy());
858 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
859 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
862 return true; // [r+0]
866 /// getPreIndexedAddressParts - returns true by value, base pointer and
867 /// offset pointer and addressing mode by reference if the node's address
868 /// can be legally represented as pre-indexed load / store address.
869 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
871 ISD::MemIndexedMode &AM,
873 // Disabled by default for now.
874 if (!EnablePPCPreinc) return false;
878 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
879 Ptr = LD->getBasePtr();
880 VT = LD->getValueType(0);
881 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
883 Ptr = ST->getBasePtr();
884 VT = ST->getStoredVT();
885 return false; // TODO: Stores.
889 // PowerPC doesn't have preinc load/store instructions for vectors.
890 if (MVT::isVector(VT))
893 // TODO: Handle reg+reg.
894 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
897 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
898 // sext i32 to i64 when addr mode is r+i.
899 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
900 if (LD->getValueType(0) == MVT::i64 && LD->getLoadedVT() == MVT::i32 &&
901 LD->getExtensionType() == ISD::SEXTLOAD &&
902 isa<ConstantSDNode>(Offset))
910 //===----------------------------------------------------------------------===//
911 // LowerOperation implementation
912 //===----------------------------------------------------------------------===//
914 static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
915 MVT::ValueType PtrVT = Op.getValueType();
916 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
917 Constant *C = CP->getConstVal();
918 SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
919 SDOperand Zero = DAG.getConstant(0, PtrVT);
921 const TargetMachine &TM = DAG.getTarget();
923 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero);
924 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero);
926 // If this is a non-darwin platform, we don't support non-static relo models
928 if (TM.getRelocationModel() == Reloc::Static ||
929 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
930 // Generate non-pic code that has direct accesses to the constant pool.
931 // The address of the global is just (hi(&g)+lo(&g)).
932 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
935 if (TM.getRelocationModel() == Reloc::PIC_) {
936 // With PIC, the first instruction is actually "GR+hi(&G)".
937 Hi = DAG.getNode(ISD::ADD, PtrVT,
938 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
941 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
945 static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
946 MVT::ValueType PtrVT = Op.getValueType();
947 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
948 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
949 SDOperand Zero = DAG.getConstant(0, PtrVT);
951 const TargetMachine &TM = DAG.getTarget();
953 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero);
954 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero);
956 // If this is a non-darwin platform, we don't support non-static relo models
958 if (TM.getRelocationModel() == Reloc::Static ||
959 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
960 // Generate non-pic code that has direct accesses to the constant pool.
961 // The address of the global is just (hi(&g)+lo(&g)).
962 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
965 if (TM.getRelocationModel() == Reloc::PIC_) {
966 // With PIC, the first instruction is actually "GR+hi(&G)".
967 Hi = DAG.getNode(ISD::ADD, PtrVT,
968 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
971 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
975 static SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
976 MVT::ValueType PtrVT = Op.getValueType();
977 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
978 GlobalValue *GV = GSDN->getGlobal();
979 SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
980 SDOperand Zero = DAG.getConstant(0, PtrVT);
982 const TargetMachine &TM = DAG.getTarget();
984 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero);
985 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero);
987 // If this is a non-darwin platform, we don't support non-static relo models
989 if (TM.getRelocationModel() == Reloc::Static ||
990 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
991 // Generate non-pic code that has direct accesses to globals.
992 // The address of the global is just (hi(&g)+lo(&g)).
993 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
996 if (TM.getRelocationModel() == Reloc::PIC_) {
997 // With PIC, the first instruction is actually "GR+hi(&G)".
998 Hi = DAG.getNode(ISD::ADD, PtrVT,
999 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1002 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1004 if (!GV->hasWeakLinkage() && !GV->hasLinkOnceLinkage() &&
1005 (!GV->isExternal() || GV->hasNotBeenReadFromBytecode()))
1008 // If the global is weak or external, we have to go through the lazy
1010 return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0);
1013 static SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
1014 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1016 // If we're comparing for equality to zero, expose the fact that this is
1017 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1018 // fold the new nodes.
1019 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1020 if (C->isNullValue() && CC == ISD::SETEQ) {
1021 MVT::ValueType VT = Op.getOperand(0).getValueType();
1022 SDOperand Zext = Op.getOperand(0);
1023 if (VT < MVT::i32) {
1025 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0));
1027 unsigned Log2b = Log2_32(MVT::getSizeInBits(VT));
1028 SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext);
1029 SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz,
1030 DAG.getConstant(Log2b, MVT::i32));
1031 return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc);
1033 // Leave comparisons against 0 and -1 alone for now, since they're usually
1034 // optimized. FIXME: revisit this when we can custom lower all setcc
1036 if (C->isAllOnesValue() || C->isNullValue())
1040 // If we have an integer seteq/setne, turn it into a compare against zero
1041 // by xor'ing the rhs with the lhs, which is faster than setting a
1042 // condition register, reading it back out, and masking the correct bit. The
1043 // normal approach here uses sub to do this instead of xor. Using xor exposes
1044 // the result to other bit-twiddling opportunities.
1045 MVT::ValueType LHSVT = Op.getOperand(0).getValueType();
1046 if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1047 MVT::ValueType VT = Op.getValueType();
1048 SDOperand Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0),
1050 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC);
1055 static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
1056 unsigned VarArgsFrameIndex) {
1057 // vastart just stores the address of the VarArgsFrameIndex slot into the
1058 // memory location argument.
1059 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1060 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1061 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
1062 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(),
1066 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
1067 int &VarArgsFrameIndex) {
1068 // TODO: add description of PPC stack frame format, or at least some docs.
1070 MachineFunction &MF = DAG.getMachineFunction();
1071 MachineFrameInfo *MFI = MF.getFrameInfo();
1072 SSARegMap *RegMap = MF.getSSARegMap();
1073 SmallVector<SDOperand, 8> ArgValues;
1074 SDOperand Root = Op.getOperand(0);
1076 unsigned ArgOffset = 24;
1077 const unsigned Num_GPR_Regs = 8;
1078 const unsigned Num_FPR_Regs = 13;
1079 const unsigned Num_VR_Regs = 12;
1080 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1082 static const unsigned GPR_32[] = { // 32-bit registers.
1083 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1084 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1086 static const unsigned GPR_64[] = { // 64-bit registers.
1087 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1088 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1090 static const unsigned FPR[] = {
1091 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1092 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1094 static const unsigned VR[] = {
1095 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1096 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1099 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1100 bool isPPC64 = PtrVT == MVT::i64;
1101 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1103 // Add DAG nodes to load the arguments or copy them out of registers. On
1104 // entry to a function on PPC, the arguments start at offset 24, although the
1105 // first ones are often in registers.
1106 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
1108 bool needsLoad = false;
1109 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
1110 unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8;
1112 unsigned CurArgOffset = ArgOffset;
1114 default: assert(0 && "Unhandled argument type!");
1116 // All int arguments reserve stack space.
1117 ArgOffset += isPPC64 ? 8 : 4;
1119 if (GPR_idx != Num_GPR_Regs) {
1120 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
1121 MF.addLiveIn(GPR[GPR_idx], VReg);
1122 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32);
1128 case MVT::i64: // PPC64
1129 // All int arguments reserve stack space.
1132 if (GPR_idx != Num_GPR_Regs) {
1133 unsigned VReg = RegMap->createVirtualRegister(&PPC::G8RCRegClass);
1134 MF.addLiveIn(GPR[GPR_idx], VReg);
1135 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1143 // All FP arguments reserve stack space.
1144 ArgOffset += ObjSize;
1146 // Every 4 bytes of argument space consumes one of the GPRs available for
1147 // argument passing.
1148 if (GPR_idx != Num_GPR_Regs) {
1150 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs)
1153 if (FPR_idx != Num_FPR_Regs) {
1155 if (ObjectVT == MVT::f32)
1156 VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass);
1158 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass);
1159 MF.addLiveIn(FPR[FPR_idx], VReg);
1160 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
1170 // Note that vector arguments in registers don't reserve stack space.
1171 if (VR_idx != Num_VR_Regs) {
1172 unsigned VReg = RegMap->createVirtualRegister(&PPC::VRRCRegClass);
1173 MF.addLiveIn(VR[VR_idx], VReg);
1174 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
1177 // This should be simple, but requires getting 16-byte aligned stack
1179 assert(0 && "Loading VR argument not implemented yet!");
1185 // We need to load the argument to a virtual register if we determined above
1186 // that we ran out of physical registers of the appropriate type
1188 // If the argument is actually used, emit a load from the right stack
1190 if (!Op.Val->hasNUsesOfValue(0, ArgNo)) {
1191 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset);
1192 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
1193 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
1195 // Don't emit a dead load.
1196 ArgVal = DAG.getNode(ISD::UNDEF, ObjectVT);
1200 ArgValues.push_back(ArgVal);
1203 // If the function takes variable number of arguments, make a frame index for
1204 // the start of the first vararg value... for expansion of llvm.va_start.
1205 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1207 VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8,
1209 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1210 // If this function is vararg, store any remaining integer argument regs
1211 // to their spots on the stack so that they may be loaded by deferencing the
1212 // result of va_next.
1213 SmallVector<SDOperand, 8> MemOps;
1214 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
1215 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
1216 MF.addLiveIn(GPR[GPR_idx], VReg);
1217 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
1218 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1219 MemOps.push_back(Store);
1220 // Increment the address by four for the next argument to store
1221 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT);
1222 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1224 if (!MemOps.empty())
1225 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size());
1228 ArgValues.push_back(Root);
1230 // Return the new list of results.
1231 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
1232 Op.Val->value_end());
1233 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
1236 /// isCallCompatibleAddress - Return the immediate to use if the specified
1237 /// 32-bit value is representable in the immediate field of a BxA instruction.
1238 static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) {
1239 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
1242 int Addr = C->getValue();
1243 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
1244 (Addr << 6 >> 6) != Addr)
1245 return 0; // Top 6 bits have to be sext of immediate.
1247 return DAG.getConstant((int)C->getValue() >> 2, MVT::i32).Val;
1251 static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
1252 SDOperand Chain = Op.getOperand(0);
1253 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1254 SDOperand Callee = Op.getOperand(4);
1255 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
1257 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1258 bool isPPC64 = PtrVT == MVT::i64;
1259 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1262 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in
1263 // SelectExpr to use to put the arguments in the appropriate registers.
1264 std::vector<SDOperand> args_to_use;
1266 // Count how many bytes are to be pushed on the stack, including the linkage
1267 // area, and parameter passing area. We start with 24/48 bytes, which is
1268 // prereserved space for [SP][CR][LR][3 x unused].
1269 unsigned NumBytes = 6*PtrByteSize;
1271 // Add up all the space actually used.
1272 for (unsigned i = 0; i != NumOps; ++i)
1273 NumBytes += MVT::getSizeInBits(Op.getOperand(5+2*i).getValueType())/8;
1275 // The prolog code of the callee may store up to 8 GPR argument registers to
1276 // the stack, allowing va_start to index over them in memory if its varargs.
1277 // Because we cannot tell if this is needed on the caller side, we have to
1278 // conservatively assume that it is needed. As such, make sure we have at
1279 // least enough stack space for the caller to store the 8 GPRs.
1280 if (NumBytes < 6*PtrByteSize+8*PtrByteSize)
1281 NumBytes = 6*PtrByteSize+8*PtrByteSize;
1283 // Adjust the stack pointer for the new arguments...
1284 // These operations are automatically eliminated by the prolog/epilog pass
1285 Chain = DAG.getCALLSEQ_START(Chain,
1286 DAG.getConstant(NumBytes, PtrVT));
1288 // Set up a copy of the stack pointer for use loading and storing any
1289 // arguments that may not fit in the registers available for argument
1293 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
1295 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
1297 // Figure out which arguments are going to go in registers, and which in
1298 // memory. Also, if this is a vararg function, floating point operations
1299 // must be stored to our stack, and loaded into integer regs as well, if
1300 // any integer regs are available for argument passing.
1301 unsigned ArgOffset = 6*PtrByteSize;
1302 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1303 static const unsigned GPR_32[] = { // 32-bit registers.
1304 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1305 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1307 static const unsigned GPR_64[] = { // 64-bit registers.
1308 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1309 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1311 static const unsigned FPR[] = {
1312 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1313 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1315 static const unsigned VR[] = {
1316 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1317 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1319 const unsigned NumGPRs = sizeof(GPR_32)/sizeof(GPR_32[0]);
1320 const unsigned NumFPRs = sizeof(FPR)/sizeof(FPR[0]);
1321 const unsigned NumVRs = sizeof( VR)/sizeof( VR[0]);
1323 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1325 std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
1326 SmallVector<SDOperand, 8> MemOpChains;
1327 for (unsigned i = 0; i != NumOps; ++i) {
1328 SDOperand Arg = Op.getOperand(5+2*i);
1330 // PtrOff will be used to store the current argument to the stack if a
1331 // register cannot be found for it.
1332 SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
1333 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff);
1335 // On PPC64, promote integers to 64-bit values.
1336 if (isPPC64 && Arg.getValueType() == MVT::i32) {
1337 unsigned ExtOp = ISD::ZERO_EXTEND;
1338 if (cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue())
1339 ExtOp = ISD::SIGN_EXTEND;
1340 Arg = DAG.getNode(ExtOp, MVT::i64, Arg);
1343 switch (Arg.getValueType()) {
1344 default: assert(0 && "Unexpected ValueType for argument!");
1347 if (GPR_idx != NumGPRs) {
1348 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
1350 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1352 ArgOffset += PtrByteSize;
1356 if (FPR_idx != NumFPRs) {
1357 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
1360 SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
1361 MemOpChains.push_back(Store);
1363 // Float varargs are always shadowed in available integer registers
1364 if (GPR_idx != NumGPRs) {
1365 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
1366 MemOpChains.push_back(Load.getValue(1));
1367 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
1369 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64) {
1370 SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType());
1371 PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour);
1372 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
1373 MemOpChains.push_back(Load.getValue(1));
1374 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
1377 // If we have any FPRs remaining, we may also have GPRs remaining.
1378 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
1380 if (GPR_idx != NumGPRs)
1382 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64)
1386 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1391 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
1397 assert(!isVarArg && "Don't support passing vectors to varargs yet!");
1398 assert(VR_idx != NumVRs &&
1399 "Don't support passing more than 12 vector args yet!");
1400 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
1404 if (!MemOpChains.empty())
1405 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1406 &MemOpChains[0], MemOpChains.size());
1408 // Build a sequence of copy-to-reg nodes chained together with token chain
1409 // and flag operands which copy the outgoing args into the appropriate regs.
1411 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1412 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1414 InFlag = Chain.getValue(1);
1417 std::vector<MVT::ValueType> NodeTys;
1418 NodeTys.push_back(MVT::Other); // Returns a chain
1419 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
1421 SmallVector<SDOperand, 8> Ops;
1422 unsigned CallOpc = PPCISD::CALL;
1424 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1425 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1426 // node so that legalize doesn't hack it.
1427 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1428 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
1429 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1430 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType());
1431 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
1432 // If this is an absolute destination address, use the munged value.
1433 Callee = SDOperand(Dest, 0);
1435 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
1436 // to do the call, we can't use PPCISD::CALL.
1437 SDOperand MTCTROps[] = {Chain, Callee, InFlag};
1438 Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+(InFlag.Val!=0));
1439 InFlag = Chain.getValue(1);
1441 // Copy the callee address into R12 on darwin.
1442 Chain = DAG.getCopyToReg(Chain, PPC::R12, Callee, InFlag);
1443 InFlag = Chain.getValue(1);
1446 NodeTys.push_back(MVT::Other);
1447 NodeTys.push_back(MVT::Flag);
1448 Ops.push_back(Chain);
1449 CallOpc = PPCISD::BCTRL;
1453 // If this is a direct call, pass the chain and the callee.
1455 Ops.push_back(Chain);
1456 Ops.push_back(Callee);
1459 // Add argument registers to the end of the list so that they are known live
1461 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1462 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1463 RegsToPass[i].second.getValueType()));
1466 Ops.push_back(InFlag);
1467 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
1468 InFlag = Chain.getValue(1);
1470 SDOperand ResultVals[3];
1471 unsigned NumResults = 0;
1474 // If the call has results, copy the values out of the ret val registers.
1475 switch (Op.Val->getValueType(0)) {
1476 default: assert(0 && "Unexpected ret value!");
1477 case MVT::Other: break;
1479 if (Op.Val->getValueType(1) == MVT::i32) {
1480 Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32, InFlag).getValue(1);
1481 ResultVals[0] = Chain.getValue(0);
1482 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32,
1483 Chain.getValue(2)).getValue(1);
1484 ResultVals[1] = Chain.getValue(0);
1486 NodeTys.push_back(MVT::i32);
1488 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1);
1489 ResultVals[0] = Chain.getValue(0);
1492 NodeTys.push_back(MVT::i32);
1495 Chain = DAG.getCopyFromReg(Chain, PPC::X3, MVT::i64, InFlag).getValue(1);
1496 ResultVals[0] = Chain.getValue(0);
1498 NodeTys.push_back(MVT::i64);
1502 Chain = DAG.getCopyFromReg(Chain, PPC::F1, Op.Val->getValueType(0),
1503 InFlag).getValue(1);
1504 ResultVals[0] = Chain.getValue(0);
1506 NodeTys.push_back(Op.Val->getValueType(0));
1512 Chain = DAG.getCopyFromReg(Chain, PPC::V2, Op.Val->getValueType(0),
1513 InFlag).getValue(1);
1514 ResultVals[0] = Chain.getValue(0);
1516 NodeTys.push_back(Op.Val->getValueType(0));
1520 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
1521 DAG.getConstant(NumBytes, PtrVT));
1522 NodeTys.push_back(MVT::Other);
1524 // If the function returns void, just return the chain.
1525 if (NumResults == 0)
1528 // Otherwise, merge everything together with a MERGE_VALUES node.
1529 ResultVals[NumResults++] = Chain;
1530 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys,
1531 ResultVals, NumResults);
1532 return Res.getValue(Op.ResNo);
1535 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
1537 switch(Op.getNumOperands()) {
1539 assert(0 && "Do not know how to return this many arguments!");
1542 return SDOperand(); // ret void is legal
1544 MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
1546 if (ArgVT == MVT::i32) {
1548 } else if (ArgVT == MVT::i64) {
1550 } else if (MVT::isVector(ArgVT)) {
1553 assert(MVT::isFloatingPoint(ArgVT));
1557 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
1560 // If we haven't noted the R3/F1 are live out, do so now.
1561 if (DAG.getMachineFunction().liveout_empty())
1562 DAG.getMachineFunction().addLiveOut(ArgReg);
1566 Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(3),
1568 Copy = DAG.getCopyToReg(Copy, PPC::R4, Op.getOperand(1),Copy.getValue(1));
1569 // If we haven't noted the R3+R4 are live out, do so now.
1570 if (DAG.getMachineFunction().liveout_empty()) {
1571 DAG.getMachineFunction().addLiveOut(PPC::R3);
1572 DAG.getMachineFunction().addLiveOut(PPC::R4);
1576 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
1579 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
1581 static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
1582 // Not FP? Not a fsel.
1583 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) ||
1584 !MVT::isFloatingPoint(Op.getOperand(2).getValueType()))
1587 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1589 // Cannot handle SETEQ/SETNE.
1590 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand();
1592 MVT::ValueType ResVT = Op.getValueType();
1593 MVT::ValueType CmpVT = Op.getOperand(0).getValueType();
1594 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
1595 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3);
1597 // If the RHS of the comparison is a 0.0, we don't need to do the
1598 // subtraction at all.
1599 if (isFloatingPointZero(RHS))
1601 default: break; // SETUO etc aren't handled by fsel.
1605 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
1609 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
1610 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
1611 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
1615 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
1619 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
1620 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
1621 return DAG.getNode(PPCISD::FSEL, ResVT,
1622 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV);
1627 default: break; // SETUO etc aren't handled by fsel.
1631 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
1632 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1633 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1634 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
1638 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
1639 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1640 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1641 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
1645 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
1646 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1647 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1648 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
1652 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
1653 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1654 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1655 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
1660 static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
1661 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType()));
1662 SDOperand Src = Op.getOperand(0);
1663 if (Src.getValueType() == MVT::f32)
1664 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src);
1667 switch (Op.getValueType()) {
1668 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
1670 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src);
1673 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src);
1677 // Convert the FP value to an int value through memory.
1678 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Tmp);
1679 if (Op.getValueType() == MVT::i32)
1680 Bits = DAG.getNode(ISD::TRUNCATE, MVT::i32, Bits);
1684 static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
1685 if (Op.getOperand(0).getValueType() == MVT::i64) {
1686 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
1687 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
1688 if (Op.getValueType() == MVT::f32)
1689 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
1693 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
1694 "Unhandled SINT_TO_FP type in custom expander!");
1695 // Since we only generate this in 64-bit mode, we can take advantage of
1696 // 64-bit registers. In particular, sign extend the input value into the
1697 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
1698 // then lfd it and fcfid it.
1699 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
1700 int FrameIdx = FrameInfo->CreateStackObject(8, 8);
1701 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1702 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
1704 SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32,
1707 // STD the extended value into the stack slot.
1708 SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other,
1709 DAG.getEntryNode(), Ext64, FIdx,
1710 DAG.getSrcValue(NULL));
1711 // Load the value as a double.
1712 SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0);
1714 // FCFID it and return it.
1715 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld);
1716 if (Op.getValueType() == MVT::f32)
1717 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
1721 static SDOperand LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) {
1722 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
1723 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
1725 // Expand into a bunch of logical ops. Note that these ops
1726 // depend on the PPC behavior for oversized shift amounts.
1727 SDOperand Lo = Op.getOperand(0);
1728 SDOperand Hi = Op.getOperand(1);
1729 SDOperand Amt = Op.getOperand(2);
1731 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
1732 DAG.getConstant(32, MVT::i32), Amt);
1733 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt);
1734 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1);
1735 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
1736 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
1737 DAG.getConstant(-32U, MVT::i32));
1738 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5);
1739 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
1740 SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt);
1741 SDOperand OutOps[] = { OutLo, OutHi };
1742 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
1746 static SDOperand LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) {
1747 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
1748 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRL!");
1750 // Otherwise, expand into a bunch of logical ops. Note that these ops
1751 // depend on the PPC behavior for oversized shift amounts.
1752 SDOperand Lo = Op.getOperand(0);
1753 SDOperand Hi = Op.getOperand(1);
1754 SDOperand Amt = Op.getOperand(2);
1756 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
1757 DAG.getConstant(32, MVT::i32), Amt);
1758 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
1759 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
1760 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
1761 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
1762 DAG.getConstant(-32U, MVT::i32));
1763 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5);
1764 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
1765 SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt);
1766 SDOperand OutOps[] = { OutLo, OutHi };
1767 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
1771 static SDOperand LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) {
1772 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
1773 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!");
1775 // Otherwise, expand into a bunch of logical ops, followed by a select_cc.
1776 SDOperand Lo = Op.getOperand(0);
1777 SDOperand Hi = Op.getOperand(1);
1778 SDOperand Amt = Op.getOperand(2);
1780 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
1781 DAG.getConstant(32, MVT::i32), Amt);
1782 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
1783 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
1784 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
1785 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
1786 DAG.getConstant(-32U, MVT::i32));
1787 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5);
1788 SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt);
1789 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32),
1790 Tmp4, Tmp6, ISD::SETLE);
1791 SDOperand OutOps[] = { OutLo, OutHi };
1792 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
1796 //===----------------------------------------------------------------------===//
1797 // Vector related lowering.
1800 // If this is a vector of constants or undefs, get the bits. A bit in
1801 // UndefBits is set if the corresponding element of the vector is an
1802 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
1803 // zero. Return true if this is not an array of constants, false if it is.
1805 static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
1806 uint64_t UndefBits[2]) {
1807 // Start with zero'd results.
1808 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0;
1810 unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType());
1811 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
1812 SDOperand OpVal = BV->getOperand(i);
1814 unsigned PartNo = i >= e/2; // In the upper 128 bits?
1815 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t.
1817 uint64_t EltBits = 0;
1818 if (OpVal.getOpcode() == ISD::UNDEF) {
1819 uint64_t EltUndefBits = ~0U >> (32-EltBitSize);
1820 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize);
1822 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1823 EltBits = CN->getValue() & (~0U >> (32-EltBitSize));
1824 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1825 assert(CN->getValueType(0) == MVT::f32 &&
1826 "Only one legal FP vector type!");
1827 EltBits = FloatToBits(CN->getValue());
1829 // Nonconstant element.
1833 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize);
1836 //printf("%llx %llx %llx %llx\n",
1837 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]);
1841 // If this is a splat (repetition) of a value across the whole vector, return
1842 // the smallest size that splats it. For example, "0x01010101010101..." is a
1843 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
1844 // SplatSize = 1 byte.
1845 static bool isConstantSplat(const uint64_t Bits128[2],
1846 const uint64_t Undef128[2],
1847 unsigned &SplatBits, unsigned &SplatUndef,
1848 unsigned &SplatSize) {
1850 // Don't let undefs prevent splats from matching. See if the top 64-bits are
1851 // the same as the lower 64-bits, ignoring undefs.
1852 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0]))
1853 return false; // Can't be a splat if two pieces don't match.
1855 uint64_t Bits64 = Bits128[0] | Bits128[1];
1856 uint64_t Undef64 = Undef128[0] & Undef128[1];
1858 // Check that the top 32-bits are the same as the lower 32-bits, ignoring
1860 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64))
1861 return false; // Can't be a splat if two pieces don't match.
1863 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32);
1864 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32);
1866 // If the top 16-bits are different than the lower 16-bits, ignoring
1867 // undefs, we have an i32 splat.
1868 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) {
1870 SplatUndef = Undef32;
1875 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16);
1876 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16);
1878 // If the top 8-bits are different than the lower 8-bits, ignoring
1879 // undefs, we have an i16 splat.
1880 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) {
1882 SplatUndef = Undef16;
1887 // Otherwise, we have an 8-bit splat.
1888 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8);
1889 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8);
1894 /// BuildSplatI - Build a canonical splati of Val with an element size of
1895 /// SplatSize. Cast the result to VT.
1896 static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT,
1897 SelectionDAG &DAG) {
1898 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
1900 // Force vspltis[hw] -1 to vspltisb -1.
1901 if (Val == -1) SplatSize = 1;
1903 static const MVT::ValueType VTys[] = { // canonical VT to use for each size.
1904 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
1906 MVT::ValueType CanonicalVT = VTys[SplatSize-1];
1908 // Build a canonical splat for this value.
1909 SDOperand Elt = DAG.getConstant(Val, MVT::getVectorBaseType(CanonicalVT));
1910 SmallVector<SDOperand, 8> Ops;
1911 Ops.assign(MVT::getVectorNumElements(CanonicalVT), Elt);
1912 SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT,
1913 &Ops[0], Ops.size());
1914 return DAG.getNode(ISD::BIT_CONVERT, VT, Res);
1917 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
1918 /// specified intrinsic ID.
1919 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS,
1921 MVT::ValueType DestVT = MVT::Other) {
1922 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
1923 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
1924 DAG.getConstant(IID, MVT::i32), LHS, RHS);
1927 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
1928 /// specified intrinsic ID.
1929 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1,
1930 SDOperand Op2, SelectionDAG &DAG,
1931 MVT::ValueType DestVT = MVT::Other) {
1932 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
1933 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
1934 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
1938 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
1939 /// amount. The result has the specified value type.
1940 static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt,
1941 MVT::ValueType VT, SelectionDAG &DAG) {
1942 // Force LHS/RHS to be the right type.
1943 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS);
1944 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS);
1947 for (unsigned i = 0; i != 16; ++i)
1948 Ops[i] = DAG.getConstant(i+Amt, MVT::i32);
1949 SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS,
1950 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16));
1951 return DAG.getNode(ISD::BIT_CONVERT, VT, T);
1954 // If this is a case we can't handle, return null and let the default
1955 // expansion code take care of it. If we CAN select this case, and if it
1956 // selects to a single instruction, return Op. Otherwise, if we can codegen
1957 // this case more efficiently than a constant pool load, lower it to the
1958 // sequence of ops that should be used.
1959 static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
1960 // If this is a vector of constants or undefs, get the bits. A bit in
1961 // UndefBits is set if the corresponding element of the vector is an
1962 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
1964 uint64_t VectorBits[2];
1965 uint64_t UndefBits[2];
1966 if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits))
1967 return SDOperand(); // Not a constant vector.
1969 // If this is a splat (repetition) of a value across the whole vector, return
1970 // the smallest size that splats it. For example, "0x01010101010101..." is a
1971 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
1972 // SplatSize = 1 byte.
1973 unsigned SplatBits, SplatUndef, SplatSize;
1974 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){
1975 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0;
1977 // First, handle single instruction cases.
1980 if (SplatBits == 0) {
1981 // Canonicalize all zero vectors to be v4i32.
1982 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
1983 SDOperand Z = DAG.getConstant(0, MVT::i32);
1984 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z);
1985 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z);
1990 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
1991 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize);
1992 if (SextVal >= -16 && SextVal <= 15)
1993 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG);
1996 // Two instruction sequences.
1998 // If this value is in the range [-32,30] and is even, use:
1999 // tmp = VSPLTI[bhw], result = add tmp, tmp
2000 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
2001 Op = BuildSplatI(SextVal >> 1, SplatSize, Op.getValueType(), DAG);
2002 return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op);
2005 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
2006 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
2008 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
2009 // Make -1 and vspltisw -1:
2010 SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG);
2012 // Make the VSLW intrinsic, computing 0x8000_0000.
2013 SDOperand Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
2016 // xor by OnesV to invert it.
2017 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV);
2018 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2021 // Check to see if this is a wide variety of vsplti*, binop self cases.
2022 unsigned SplatBitSize = SplatSize*8;
2023 static const char SplatCsts[] = {
2024 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
2025 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
2027 for (unsigned idx = 0; idx < sizeof(SplatCsts)/sizeof(SplatCsts[0]); ++idx){
2028 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
2029 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
2030 int i = SplatCsts[idx];
2032 // Figure out what shift amount will be used by altivec if shifted by i in
2034 unsigned TypeShiftAmt = i & (SplatBitSize-1);
2036 // vsplti + shl self.
2037 if (SextVal == (i << (int)TypeShiftAmt)) {
2038 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
2039 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2040 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
2041 Intrinsic::ppc_altivec_vslw
2043 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
2046 // vsplti + srl self.
2047 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
2048 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
2049 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2050 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
2051 Intrinsic::ppc_altivec_vsrw
2053 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
2056 // vsplti + sra self.
2057 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
2058 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
2059 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2060 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
2061 Intrinsic::ppc_altivec_vsraw
2063 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
2066 // vsplti + rol self.
2067 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
2068 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
2069 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
2070 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2071 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
2072 Intrinsic::ppc_altivec_vrlw
2074 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
2077 // t = vsplti c, result = vsldoi t, t, 1
2078 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
2079 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2080 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG);
2082 // t = vsplti c, result = vsldoi t, t, 2
2083 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
2084 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2085 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG);
2087 // t = vsplti c, result = vsldoi t, t, 3
2088 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
2089 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2090 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG);
2094 // Three instruction sequences.
2096 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
2097 if (SextVal >= 0 && SextVal <= 31) {
2098 SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, Op.getValueType(),DAG);
2099 SDOperand RHS = BuildSplatI(-16, SplatSize, Op.getValueType(), DAG);
2100 return DAG.getNode(ISD::SUB, Op.getValueType(), LHS, RHS);
2102 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
2103 if (SextVal >= -31 && SextVal <= 0) {
2104 SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, Op.getValueType(),DAG);
2105 SDOperand RHS = BuildSplatI(-16, SplatSize, Op.getValueType(), DAG);
2106 return DAG.getNode(ISD::ADD, Op.getValueType(), LHS, RHS);
2113 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
2114 /// the specified operations to build the shuffle.
2115 static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS,
2116 SDOperand RHS, SelectionDAG &DAG) {
2117 unsigned OpNum = (PFEntry >> 26) & 0x0F;
2118 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
2119 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
2122 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
2134 if (OpNum == OP_COPY) {
2135 if (LHSID == (1*9+2)*9+3) return LHS;
2136 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
2140 SDOperand OpLHS, OpRHS;
2141 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG);
2142 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG);
2144 unsigned ShufIdxs[16];
2146 default: assert(0 && "Unknown i32 permute!");
2148 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
2149 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
2150 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
2151 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
2154 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
2155 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
2156 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
2157 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
2160 for (unsigned i = 0; i != 16; ++i)
2161 ShufIdxs[i] = (i&3)+0;
2164 for (unsigned i = 0; i != 16; ++i)
2165 ShufIdxs[i] = (i&3)+4;
2168 for (unsigned i = 0; i != 16; ++i)
2169 ShufIdxs[i] = (i&3)+8;
2172 for (unsigned i = 0; i != 16; ++i)
2173 ShufIdxs[i] = (i&3)+12;
2176 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG);
2178 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG);
2180 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG);
2183 for (unsigned i = 0; i != 16; ++i)
2184 Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i32);
2186 return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS,
2187 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
2190 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
2191 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
2192 /// return the code it can be lowered into. Worst case, it can always be
2193 /// lowered into a vperm.
2194 static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
2195 SDOperand V1 = Op.getOperand(0);
2196 SDOperand V2 = Op.getOperand(1);
2197 SDOperand PermMask = Op.getOperand(2);
2199 // Cases that are handled by instructions that take permute immediates
2200 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
2201 // selected by the instruction selector.
2202 if (V2.getOpcode() == ISD::UNDEF) {
2203 if (PPC::isSplatShuffleMask(PermMask.Val, 1) ||
2204 PPC::isSplatShuffleMask(PermMask.Val, 2) ||
2205 PPC::isSplatShuffleMask(PermMask.Val, 4) ||
2206 PPC::isVPKUWUMShuffleMask(PermMask.Val, true) ||
2207 PPC::isVPKUHUMShuffleMask(PermMask.Val, true) ||
2208 PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 ||
2209 PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) ||
2210 PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) ||
2211 PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) ||
2212 PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) ||
2213 PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) ||
2214 PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) {
2219 // Altivec has a variety of "shuffle immediates" that take two vector inputs
2220 // and produce a fixed permutation. If any of these match, do not lower to
2222 if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) ||
2223 PPC::isVPKUHUMShuffleMask(PermMask.Val, false) ||
2224 PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 ||
2225 PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) ||
2226 PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) ||
2227 PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) ||
2228 PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) ||
2229 PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) ||
2230 PPC::isVMRGHShuffleMask(PermMask.Val, 4, false))
2233 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
2234 // perfect shuffle table to emit an optimal matching sequence.
2235 unsigned PFIndexes[4];
2236 bool isFourElementShuffle = true;
2237 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
2238 unsigned EltNo = 8; // Start out undef.
2239 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
2240 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF)
2241 continue; // Undef, ignore it.
2243 unsigned ByteSource =
2244 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue();
2245 if ((ByteSource & 3) != j) {
2246 isFourElementShuffle = false;
2251 EltNo = ByteSource/4;
2252 } else if (EltNo != ByteSource/4) {
2253 isFourElementShuffle = false;
2257 PFIndexes[i] = EltNo;
2260 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
2261 // perfect shuffle vector to determine if it is cost effective to do this as
2262 // discrete instructions, or whether we should use a vperm.
2263 if (isFourElementShuffle) {
2264 // Compute the index in the perfect shuffle table.
2265 unsigned PFTableIndex =
2266 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
2268 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
2269 unsigned Cost = (PFEntry >> 30);
2271 // Determining when to avoid vperm is tricky. Many things affect the cost
2272 // of vperm, particularly how many times the perm mask needs to be computed.
2273 // For example, if the perm mask can be hoisted out of a loop or is already
2274 // used (perhaps because there are multiple permutes with the same shuffle
2275 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
2276 // the loop requires an extra register.
2278 // As a compromise, we only emit discrete instructions if the shuffle can be
2279 // generated in 3 or fewer operations. When we have loop information
2280 // available, if this block is within a loop, we should avoid using vperm
2281 // for 3-operation perms and use a constant pool load instead.
2283 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG);
2286 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
2287 // vector that will get spilled to the constant pool.
2288 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
2290 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
2291 // that it is in input element units, not in bytes. Convert now.
2292 MVT::ValueType EltVT = MVT::getVectorBaseType(V1.getValueType());
2293 unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8;
2295 SmallVector<SDOperand, 16> ResultMask;
2296 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
2298 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
2301 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue();
2303 for (unsigned j = 0; j != BytesPerElement; ++j)
2304 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
2308 SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8,
2309 &ResultMask[0], ResultMask.size());
2310 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
2313 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
2314 /// altivec comparison. If it is, return true and fill in Opc/isDot with
2315 /// information about the intrinsic.
2316 static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc,
2318 unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue();
2321 switch (IntrinsicID) {
2322 default: return false;
2323 // Comparison predicates.
2324 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
2325 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
2326 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
2327 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
2328 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
2329 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
2330 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
2331 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
2332 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
2333 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
2334 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
2335 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
2336 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
2338 // Normal Comparisons.
2339 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
2340 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
2341 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
2342 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
2343 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
2344 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
2345 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
2346 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
2347 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
2348 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
2349 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
2350 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
2351 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
2356 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
2357 /// lower, do it, otherwise return null.
2358 static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
2359 // If this is a lowered altivec predicate compare, CompareOpc is set to the
2360 // opcode number of the comparison.
2363 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
2364 return SDOperand(); // Don't custom lower most intrinsics.
2366 // If this is a non-dot comparison, make the VCMP node and we are done.
2368 SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(),
2369 Op.getOperand(1), Op.getOperand(2),
2370 DAG.getConstant(CompareOpc, MVT::i32));
2371 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp);
2374 // Create the PPCISD altivec 'dot' comparison node.
2376 Op.getOperand(2), // LHS
2377 Op.getOperand(3), // RHS
2378 DAG.getConstant(CompareOpc, MVT::i32)
2380 std::vector<MVT::ValueType> VTs;
2381 VTs.push_back(Op.getOperand(2).getValueType());
2382 VTs.push_back(MVT::Flag);
2383 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
2385 // Now that we have the comparison, emit a copy from the CR to a GPR.
2386 // This is flagged to the above dot comparison.
2387 SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32,
2388 DAG.getRegister(PPC::CR6, MVT::i32),
2389 CompNode.getValue(1));
2391 // Unpack the result based on how the target uses it.
2392 unsigned BitNo; // Bit # of CR6.
2393 bool InvertBit; // Invert result?
2394 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
2395 default: // Can't happen, don't crash on invalid number though.
2396 case 0: // Return the value of the EQ bit of CR6.
2397 BitNo = 0; InvertBit = false;
2399 case 1: // Return the inverted value of the EQ bit of CR6.
2400 BitNo = 0; InvertBit = true;
2402 case 2: // Return the value of the LT bit of CR6.
2403 BitNo = 2; InvertBit = false;
2405 case 3: // Return the inverted value of the LT bit of CR6.
2406 BitNo = 2; InvertBit = true;
2410 // Shift the bit into the low position.
2411 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags,
2412 DAG.getConstant(8-(3-BitNo), MVT::i32));
2414 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags,
2415 DAG.getConstant(1, MVT::i32));
2417 // If we are supposed to, toggle the bit.
2419 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags,
2420 DAG.getConstant(1, MVT::i32));
2424 static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2425 // Create a stack slot that is 16-byte aligned.
2426 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
2427 int FrameIdx = FrameInfo->CreateStackObject(16, 16);
2428 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2429 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
2431 // Store the input value into Value#0 of the stack slot.
2432 SDOperand Store = DAG.getStore(DAG.getEntryNode(),
2433 Op.getOperand(0), FIdx, NULL, 0);
2435 return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0);
2438 static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) {
2439 if (Op.getValueType() == MVT::v4i32) {
2440 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2442 SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG);
2443 SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt.
2445 SDOperand RHSSwap = // = vrlw RHS, 16
2446 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG);
2448 // Shrinkify inputs to v8i16.
2449 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS);
2450 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS);
2451 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap);
2453 // Low parts multiplied together, generating 32-bit results (we ignore the
2455 SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
2456 LHS, RHS, DAG, MVT::v4i32);
2458 SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
2459 LHS, RHSSwap, Zero, DAG, MVT::v4i32);
2460 // Shift the high parts up 16 bits.
2461 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG);
2462 return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd);
2463 } else if (Op.getValueType() == MVT::v8i16) {
2464 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2466 SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG);
2468 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
2469 LHS, RHS, Zero, DAG);
2470 } else if (Op.getValueType() == MVT::v16i8) {
2471 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2473 // Multiply the even 8-bit parts, producing 16-bit sums.
2474 SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
2475 LHS, RHS, DAG, MVT::v8i16);
2476 EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts);
2478 // Multiply the odd 8-bit parts, producing 16-bit sums.
2479 SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
2480 LHS, RHS, DAG, MVT::v8i16);
2481 OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts);
2483 // Merge the results together.
2485 for (unsigned i = 0; i != 8; ++i) {
2486 Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8);
2487 Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8);
2489 return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts,
2490 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
2492 assert(0 && "Unknown mul to lower!");
2497 /// LowerOperation - Provide custom lowering hooks for some operations.
2499 SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
2500 switch (Op.getOpcode()) {
2501 default: assert(0 && "Wasn't expecting to be able to lower this!");
2502 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2503 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
2504 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
2505 case ISD::SETCC: return LowerSETCC(Op, DAG);
2506 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
2507 case ISD::FORMAL_ARGUMENTS:
2508 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex);
2509 case ISD::CALL: return LowerCALL(Op, DAG);
2510 case ISD::RET: return LowerRET(Op, DAG);
2512 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
2513 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
2514 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
2516 // Lower 64-bit shifts.
2517 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
2518 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
2519 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
2521 // Vector-related lowering.
2522 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
2523 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2524 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2525 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
2526 case ISD::MUL: return LowerMUL(Op, DAG);
2531 //===----------------------------------------------------------------------===//
2532 // Other Lowering Code
2533 //===----------------------------------------------------------------------===//
2536 PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
2537 MachineBasicBlock *BB) {
2538 assert((MI->getOpcode() == PPC::SELECT_CC_I4 ||
2539 MI->getOpcode() == PPC::SELECT_CC_I8 ||
2540 MI->getOpcode() == PPC::SELECT_CC_F4 ||
2541 MI->getOpcode() == PPC::SELECT_CC_F8 ||
2542 MI->getOpcode() == PPC::SELECT_CC_VRRC) &&
2543 "Unexpected instr type to insert");
2545 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
2546 // control-flow pattern. The incoming instruction knows the destination vreg
2547 // to set, the condition code register to branch on, the true/false values to
2548 // select between, and a branch opcode to use.
2549 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2550 ilist<MachineBasicBlock>::iterator It = BB;
2556 // cmpTY ccX, r1, r2
2558 // fallthrough --> copy0MBB
2559 MachineBasicBlock *thisMBB = BB;
2560 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
2561 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
2562 BuildMI(BB, MI->getOperand(4).getImmedValue(), 2)
2563 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
2564 MachineFunction *F = BB->getParent();
2565 F->getBasicBlockList().insert(It, copy0MBB);
2566 F->getBasicBlockList().insert(It, sinkMBB);
2567 // Update machine-CFG edges by first adding all successors of the current
2568 // block to the new block which will contain the Phi node for the select.
2569 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
2570 e = BB->succ_end(); i != e; ++i)
2571 sinkMBB->addSuccessor(*i);
2572 // Next, remove all successors of the current block, and add the true
2573 // and fallthrough blocks as its successors.
2574 while(!BB->succ_empty())
2575 BB->removeSuccessor(BB->succ_begin());
2576 BB->addSuccessor(copy0MBB);
2577 BB->addSuccessor(sinkMBB);
2580 // %FalseValue = ...
2581 // # fallthrough to sinkMBB
2584 // Update machine-CFG edges
2585 BB->addSuccessor(sinkMBB);
2588 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
2591 BuildMI(BB, PPC::PHI, 4, MI->getOperand(0).getReg())
2592 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
2593 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
2595 delete MI; // The pseudo instruction is gone now.
2599 //===----------------------------------------------------------------------===//
2600 // Target Optimization Hooks
2601 //===----------------------------------------------------------------------===//
2603 SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
2604 DAGCombinerInfo &DCI) const {
2605 TargetMachine &TM = getTargetMachine();
2606 SelectionDAG &DAG = DCI.DAG;
2607 switch (N->getOpcode()) {
2610 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
2611 if (C->getValue() == 0) // 0 << V -> 0.
2612 return N->getOperand(0);
2616 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
2617 if (C->getValue() == 0) // 0 >>u V -> 0.
2618 return N->getOperand(0);
2622 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
2623 if (C->getValue() == 0 || // 0 >>s V -> 0.
2624 C->isAllOnesValue()) // -1 >>s V -> -1.
2625 return N->getOperand(0);
2629 case ISD::SINT_TO_FP:
2630 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
2631 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
2632 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
2633 // We allow the src/dst to be either f32/f64, but the intermediate
2634 // type must be i64.
2635 if (N->getOperand(0).getValueType() == MVT::i64) {
2636 SDOperand Val = N->getOperand(0).getOperand(0);
2637 if (Val.getValueType() == MVT::f32) {
2638 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
2639 DCI.AddToWorklist(Val.Val);
2642 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val);
2643 DCI.AddToWorklist(Val.Val);
2644 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val);
2645 DCI.AddToWorklist(Val.Val);
2646 if (N->getValueType(0) == MVT::f32) {
2647 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val);
2648 DCI.AddToWorklist(Val.Val);
2651 } else if (N->getOperand(0).getValueType() == MVT::i32) {
2652 // If the intermediate type is i32, we can avoid the load/store here
2659 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
2660 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
2661 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
2662 N->getOperand(1).getValueType() == MVT::i32) {
2663 SDOperand Val = N->getOperand(1).getOperand(0);
2664 if (Val.getValueType() == MVT::f32) {
2665 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
2666 DCI.AddToWorklist(Val.Val);
2668 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val);
2669 DCI.AddToWorklist(Val.Val);
2671 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val,
2672 N->getOperand(2), N->getOperand(3));
2673 DCI.AddToWorklist(Val.Val);
2677 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
2678 if (N->getOperand(1).getOpcode() == ISD::BSWAP &&
2679 N->getOperand(1).Val->hasOneUse() &&
2680 (N->getOperand(1).getValueType() == MVT::i32 ||
2681 N->getOperand(1).getValueType() == MVT::i16)) {
2682 SDOperand BSwapOp = N->getOperand(1).getOperand(0);
2683 // Do an any-extend to 32-bits if this is a half-word input.
2684 if (BSwapOp.getValueType() == MVT::i16)
2685 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp);
2687 return DAG.getNode(PPCISD::STBRX, MVT::Other, N->getOperand(0), BSwapOp,
2688 N->getOperand(2), N->getOperand(3),
2689 DAG.getValueType(N->getOperand(1).getValueType()));
2693 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
2694 if (ISD::isNON_EXTLoad(N->getOperand(0).Val) &&
2695 N->getOperand(0).hasOneUse() &&
2696 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
2697 SDOperand Load = N->getOperand(0);
2698 LoadSDNode *LD = cast<LoadSDNode>(Load);
2699 // Create the byte-swapping load.
2700 std::vector<MVT::ValueType> VTs;
2701 VTs.push_back(MVT::i32);
2702 VTs.push_back(MVT::Other);
2703 SDOperand SV = DAG.getSrcValue(LD->getSrcValue(), LD->getSrcValueOffset());
2705 LD->getChain(), // Chain
2706 LD->getBasePtr(), // Ptr
2708 DAG.getValueType(N->getValueType(0)) // VT
2710 SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4);
2712 // If this is an i16 load, insert the truncate.
2713 SDOperand ResVal = BSLoad;
2714 if (N->getValueType(0) == MVT::i16)
2715 ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad);
2717 // First, combine the bswap away. This makes the value produced by the
2719 DCI.CombineTo(N, ResVal);
2721 // Next, combine the load away, we give it a bogus result value but a real
2722 // chain result. The result value is dead because the bswap is dead.
2723 DCI.CombineTo(Load.Val, ResVal, BSLoad.getValue(1));
2725 // Return N so it doesn't get rechecked!
2726 return SDOperand(N, 0);
2730 case PPCISD::VCMP: {
2731 // If a VCMPo node already exists with exactly the same operands as this
2732 // node, use its result instead of this node (VCMPo computes both a CR6 and
2733 // a normal output).
2735 if (!N->getOperand(0).hasOneUse() &&
2736 !N->getOperand(1).hasOneUse() &&
2737 !N->getOperand(2).hasOneUse()) {
2739 // Scan all of the users of the LHS, looking for VCMPo's that match.
2740 SDNode *VCMPoNode = 0;
2742 SDNode *LHSN = N->getOperand(0).Val;
2743 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
2745 if ((*UI)->getOpcode() == PPCISD::VCMPo &&
2746 (*UI)->getOperand(1) == N->getOperand(1) &&
2747 (*UI)->getOperand(2) == N->getOperand(2) &&
2748 (*UI)->getOperand(0) == N->getOperand(0)) {
2753 // If there is no VCMPo node, or if the flag value has a single use, don't
2755 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
2758 // Look at the (necessarily single) use of the flag value. If it has a
2759 // chain, this transformation is more complex. Note that multiple things
2760 // could use the value result, which we should ignore.
2761 SDNode *FlagUser = 0;
2762 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
2763 FlagUser == 0; ++UI) {
2764 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
2766 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
2767 if (User->getOperand(i) == SDOperand(VCMPoNode, 1)) {
2774 // If the user is a MFCR instruction, we know this is safe. Otherwise we
2775 // give up for right now.
2776 if (FlagUser->getOpcode() == PPCISD::MFCR)
2777 return SDOperand(VCMPoNode, 0);
2782 // If this is a branch on an altivec predicate comparison, lower this so
2783 // that we don't have to do a MFCR: instead, branch directly on CR6. This
2784 // lowering is done pre-legalize, because the legalizer lowers the predicate
2785 // compare down to code that is difficult to reassemble.
2786 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
2787 SDOperand LHS = N->getOperand(2), RHS = N->getOperand(3);
2791 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
2792 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
2793 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
2794 assert(isDot && "Can't compare against a vector result!");
2796 // If this is a comparison against something other than 0/1, then we know
2797 // that the condition is never/always true.
2798 unsigned Val = cast<ConstantSDNode>(RHS)->getValue();
2799 if (Val != 0 && Val != 1) {
2800 if (CC == ISD::SETEQ) // Cond never true, remove branch.
2801 return N->getOperand(0);
2802 // Always !=, turn it into an unconditional branch.
2803 return DAG.getNode(ISD::BR, MVT::Other,
2804 N->getOperand(0), N->getOperand(4));
2807 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
2809 // Create the PPCISD altivec 'dot' comparison node.
2810 std::vector<MVT::ValueType> VTs;
2812 LHS.getOperand(2), // LHS of compare
2813 LHS.getOperand(3), // RHS of compare
2814 DAG.getConstant(CompareOpc, MVT::i32)
2816 VTs.push_back(LHS.getOperand(2).getValueType());
2817 VTs.push_back(MVT::Flag);
2818 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
2820 // Unpack the result based on how the target uses it.
2822 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) {
2823 default: // Can't happen, don't crash on invalid number though.
2824 case 0: // Branch on the value of the EQ bit of CR6.
2825 CompOpc = BranchOnWhenPredTrue ? PPC::BEQ : PPC::BNE;
2827 case 1: // Branch on the inverted value of the EQ bit of CR6.
2828 CompOpc = BranchOnWhenPredTrue ? PPC::BNE : PPC::BEQ;
2830 case 2: // Branch on the value of the LT bit of CR6.
2831 CompOpc = BranchOnWhenPredTrue ? PPC::BLT : PPC::BGE;
2833 case 3: // Branch on the inverted value of the LT bit of CR6.
2834 CompOpc = BranchOnWhenPredTrue ? PPC::BGE : PPC::BLT;
2838 return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0),
2839 DAG.getRegister(PPC::CR6, MVT::i32),
2840 DAG.getConstant(CompOpc, MVT::i32),
2841 N->getOperand(4), CompNode.getValue(1));
2850 //===----------------------------------------------------------------------===//
2851 // Inline Assembly Support
2852 //===----------------------------------------------------------------------===//
2854 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
2856 uint64_t &KnownZero,
2858 unsigned Depth) const {
2861 switch (Op.getOpcode()) {
2863 case PPCISD::LBRX: {
2864 // lhbrx is known to have the top bits cleared out.
2865 if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16)
2866 KnownZero = 0xFFFF0000;
2869 case ISD::INTRINSIC_WO_CHAIN: {
2870 switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) {
2872 case Intrinsic::ppc_altivec_vcmpbfp_p:
2873 case Intrinsic::ppc_altivec_vcmpeqfp_p:
2874 case Intrinsic::ppc_altivec_vcmpequb_p:
2875 case Intrinsic::ppc_altivec_vcmpequh_p:
2876 case Intrinsic::ppc_altivec_vcmpequw_p:
2877 case Intrinsic::ppc_altivec_vcmpgefp_p:
2878 case Intrinsic::ppc_altivec_vcmpgtfp_p:
2879 case Intrinsic::ppc_altivec_vcmpgtsb_p:
2880 case Intrinsic::ppc_altivec_vcmpgtsh_p:
2881 case Intrinsic::ppc_altivec_vcmpgtsw_p:
2882 case Intrinsic::ppc_altivec_vcmpgtub_p:
2883 case Intrinsic::ppc_altivec_vcmpgtuh_p:
2884 case Intrinsic::ppc_altivec_vcmpgtuw_p:
2885 KnownZero = ~1U; // All bits but the low one are known to be zero.
2893 /// getConstraintType - Given a constraint letter, return the type of
2894 /// constraint it is for this target.
2895 PPCTargetLowering::ConstraintType
2896 PPCTargetLowering::getConstraintType(char ConstraintLetter) const {
2897 switch (ConstraintLetter) {
2904 return C_RegisterClass;
2906 return TargetLowering::getConstraintType(ConstraintLetter);
2909 std::pair<unsigned, const TargetRegisterClass*>
2910 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
2911 MVT::ValueType VT) const {
2912 if (Constraint.size() == 1) {
2913 // GCC RS6000 Constraint Letters
2914 switch (Constraint[0]) {
2917 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
2918 return std::make_pair(0U, PPC::G8RCRegisterClass);
2919 return std::make_pair(0U, PPC::GPRCRegisterClass);
2922 return std::make_pair(0U, PPC::F4RCRegisterClass);
2923 else if (VT == MVT::f64)
2924 return std::make_pair(0U, PPC::F8RCRegisterClass);
2927 return std::make_pair(0U, PPC::VRRCRegisterClass);
2929 return std::make_pair(0U, PPC::CRRCRegisterClass);
2933 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
2937 // isOperandValidForConstraint
2938 SDOperand PPCTargetLowering::
2939 isOperandValidForConstraint(SDOperand Op, char Letter, SelectionDAG &DAG) {
2950 if (!isa<ConstantSDNode>(Op)) return SDOperand(0,0);// Must be an immediate.
2951 unsigned Value = cast<ConstantSDNode>(Op)->getValue();
2953 default: assert(0 && "Unknown constraint letter!");
2954 case 'I': // "I" is a signed 16-bit constant.
2955 if ((short)Value == (int)Value) return Op;
2957 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
2958 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
2959 if ((short)Value == 0) return Op;
2961 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
2962 if ((Value >> 16) == 0) return Op;
2964 case 'M': // "M" is a constant that is greater than 31.
2965 if (Value > 31) return Op;
2967 case 'N': // "N" is a positive constant that is an exact power of two.
2968 if ((int)Value > 0 && isPowerOf2_32(Value)) return Op;
2970 case 'O': // "O" is the constant zero.
2971 if (Value == 0) return Op;
2973 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
2974 if ((short)-Value == (int)-Value) return Op;
2981 // Handle standard constraint letters.
2982 return TargetLowering::isOperandValidForConstraint(Op, Letter, DAG);
2985 /// isLegalAddressImmediate - Return true if the integer value can be used
2986 /// as the offset of the target addressing mode.
2987 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V) const {
2988 // PPC allows a sign-extended 16-bit immediate field.
2989 return (V > -(1 << 16) && V < (1 << 16)-1);
2992 bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
2993 return TargetLowering::isLegalAddressImmediate(GV);