1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPerfectShuffle.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCTargetObjectFile.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/StringSwitch.h"
22 #include "llvm/ADT/Triple.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
30 #include "llvm/IR/CallingConv.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/DerivedTypes.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/IR/Intrinsics.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/Target/TargetOptions.h"
42 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
43 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
45 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
46 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
48 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
49 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
51 // FIXME: Remove this once the bug has been fixed!
52 extern cl::opt<bool> ANDIGlueBug;
54 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
55 // If it isn't a Mach-O file then it's going to be a linux ELF
58 return new TargetLoweringObjectFileMachO();
60 return new PPC64LinuxTargetObjectFile();
63 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
64 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))),
65 Subtarget(*TM.getSubtargetImpl()) {
68 // Use _setjmp/_longjmp instead of setjmp/longjmp.
69 setUseUnderscoreSetJmp(true);
70 setUseUnderscoreLongJmp(true);
72 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
73 // arguments are at least 4/8 bytes aligned.
74 bool isPPC64 = Subtarget.isPPC64();
75 setMinStackArgumentAlignment(isPPC64 ? 8:4);
77 // Set up the register classes.
78 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
79 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
80 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
82 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
83 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
84 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
86 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
88 // PowerPC has pre-inc load and store's.
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
91 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
92 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
93 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
100 if (Subtarget.useCRBits()) {
101 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
103 if (isPPC64 || Subtarget.hasFPCVT()) {
104 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
105 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
106 isPPC64 ? MVT::i64 : MVT::i32);
107 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
108 AddPromotedToType (ISD::UINT_TO_FP, MVT::i1,
109 isPPC64 ? MVT::i64 : MVT::i32);
111 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
112 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
115 // PowerPC does not support direct load / store of condition registers
116 setOperationAction(ISD::LOAD, MVT::i1, Custom);
117 setOperationAction(ISD::STORE, MVT::i1, Custom);
119 // FIXME: Remove this once the ANDI glue bug is fixed:
121 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
123 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
124 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
125 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
126 setTruncStoreAction(MVT::i32, MVT::i1, Expand);
127 setTruncStoreAction(MVT::i16, MVT::i1, Expand);
128 setTruncStoreAction(MVT::i8, MVT::i1, Expand);
130 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
133 // This is used in the ppcf128->int sequence. Note it has different semantics
134 // from FP_ROUND: that rounds to nearest, this rounds to zero.
135 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
137 // We do not currently implement these libm ops for PowerPC.
138 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
139 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
140 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
141 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
142 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
143 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
145 // PowerPC has no SREM/UREM instructions
146 setOperationAction(ISD::SREM, MVT::i32, Expand);
147 setOperationAction(ISD::UREM, MVT::i32, Expand);
148 setOperationAction(ISD::SREM, MVT::i64, Expand);
149 setOperationAction(ISD::UREM, MVT::i64, Expand);
151 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
152 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
153 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
154 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
155 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
156 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
157 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
158 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
159 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
161 // We don't support sin/cos/sqrt/fmod/pow
162 setOperationAction(ISD::FSIN , MVT::f64, Expand);
163 setOperationAction(ISD::FCOS , MVT::f64, Expand);
164 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
165 setOperationAction(ISD::FREM , MVT::f64, Expand);
166 setOperationAction(ISD::FPOW , MVT::f64, Expand);
167 setOperationAction(ISD::FMA , MVT::f64, Legal);
168 setOperationAction(ISD::FSIN , MVT::f32, Expand);
169 setOperationAction(ISD::FCOS , MVT::f32, Expand);
170 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
171 setOperationAction(ISD::FREM , MVT::f32, Expand);
172 setOperationAction(ISD::FPOW , MVT::f32, Expand);
173 setOperationAction(ISD::FMA , MVT::f32, Legal);
175 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
177 // If we're enabling GP optimizations, use hardware square root
178 if (!Subtarget.hasFSQRT() &&
179 !(TM.Options.UnsafeFPMath &&
180 Subtarget.hasFRSQRTE() && Subtarget.hasFRE()))
181 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
183 if (!Subtarget.hasFSQRT() &&
184 !(TM.Options.UnsafeFPMath &&
185 Subtarget.hasFRSQRTES() && Subtarget.hasFRES()))
186 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
188 if (Subtarget.hasFCPSGN()) {
189 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
190 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
192 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
193 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
196 if (Subtarget.hasFPRND()) {
197 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
198 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
199 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
200 setOperationAction(ISD::FROUND, MVT::f64, Legal);
202 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
203 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
204 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
205 setOperationAction(ISD::FROUND, MVT::f32, Legal);
208 // PowerPC does not have BSWAP, CTPOP or CTTZ
209 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
210 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
211 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
212 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
213 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
214 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
215 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
216 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
218 if (Subtarget.hasPOPCNTD()) {
219 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
220 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
222 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
223 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
226 // PowerPC does not have ROTR
227 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
228 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
230 if (!Subtarget.useCRBits()) {
231 // PowerPC does not have Select
232 setOperationAction(ISD::SELECT, MVT::i32, Expand);
233 setOperationAction(ISD::SELECT, MVT::i64, Expand);
234 setOperationAction(ISD::SELECT, MVT::f32, Expand);
235 setOperationAction(ISD::SELECT, MVT::f64, Expand);
238 // PowerPC wants to turn select_cc of FP into fsel when possible.
239 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
240 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
242 // PowerPC wants to optimize integer setcc a bit
243 if (!Subtarget.useCRBits())
244 setOperationAction(ISD::SETCC, MVT::i32, Custom);
246 // PowerPC does not have BRCOND which requires SetCC
247 if (!Subtarget.useCRBits())
248 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
250 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
252 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
253 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
255 // PowerPC does not have [U|S]INT_TO_FP
256 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
257 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
259 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
260 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
261 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
262 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
264 // We cannot sextinreg(i1). Expand to shifts.
265 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
267 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
268 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
269 // support continuation, user-level threading, and etc.. As a result, no
270 // other SjLj exception interfaces are implemented and please don't build
271 // your own exception handling based on them.
272 // LLVM/Clang supports zero-cost DWARF exception handling.
273 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
274 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
276 // We want to legalize GlobalAddress and ConstantPool nodes into the
277 // appropriate instructions to materialize the address.
278 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
279 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
280 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
281 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
282 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
283 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
284 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
285 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
286 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
287 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
290 setOperationAction(ISD::TRAP, MVT::Other, Legal);
292 // TRAMPOLINE is custom lowered.
293 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
294 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
296 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
297 setOperationAction(ISD::VASTART , MVT::Other, Custom);
299 if (Subtarget.isSVR4ABI()) {
301 // VAARG always uses double-word chunks, so promote anything smaller.
302 setOperationAction(ISD::VAARG, MVT::i1, Promote);
303 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
304 setOperationAction(ISD::VAARG, MVT::i8, Promote);
305 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
306 setOperationAction(ISD::VAARG, MVT::i16, Promote);
307 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
308 setOperationAction(ISD::VAARG, MVT::i32, Promote);
309 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
310 setOperationAction(ISD::VAARG, MVT::Other, Expand);
312 // VAARG is custom lowered with the 32-bit SVR4 ABI.
313 setOperationAction(ISD::VAARG, MVT::Other, Custom);
314 setOperationAction(ISD::VAARG, MVT::i64, Custom);
317 setOperationAction(ISD::VAARG, MVT::Other, Expand);
319 if (Subtarget.isSVR4ABI() && !isPPC64)
320 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
321 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
323 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
325 // Use the default implementation.
326 setOperationAction(ISD::VAEND , MVT::Other, Expand);
327 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
328 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
329 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
330 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
332 // We want to custom lower some of our intrinsics.
333 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
335 // To handle counter-based loop conditions.
336 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
338 // Comparisons that require checking two conditions.
339 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
340 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
341 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
342 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
343 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
344 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
345 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
346 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
347 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
348 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
349 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
350 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
352 if (Subtarget.has64BitSupport()) {
353 // They also have instructions for converting between i64 and fp.
354 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
355 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
356 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
357 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
358 // This is just the low 32 bits of a (signed) fp->i64 conversion.
359 // We cannot do this with Promote because i64 is not a legal type.
360 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
362 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
363 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
365 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
366 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
369 // With the instructions enabled under FPCVT, we can do everything.
370 if (Subtarget.hasFPCVT()) {
371 if (Subtarget.has64BitSupport()) {
372 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
373 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
374 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
375 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
378 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
379 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
380 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
381 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
384 if (Subtarget.use64BitRegs()) {
385 // 64-bit PowerPC implementations can support i64 types directly
386 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
387 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
388 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
389 // 64-bit PowerPC wants to expand i128 shifts itself.
390 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
391 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
392 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
394 // 32-bit PowerPC wants to expand i64 shifts itself.
395 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
396 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
397 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
400 if (Subtarget.hasAltivec()) {
401 // First set operation action for all vector types to expand. Then we
402 // will selectively turn on ones that can be effectively codegen'd.
403 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
404 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
405 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
407 // add/sub are legal for all supported vector VT's.
408 setOperationAction(ISD::ADD , VT, Legal);
409 setOperationAction(ISD::SUB , VT, Legal);
411 // We promote all shuffles to v16i8.
412 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
413 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
415 // We promote all non-typed operations to v4i32.
416 setOperationAction(ISD::AND , VT, Promote);
417 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
418 setOperationAction(ISD::OR , VT, Promote);
419 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
420 setOperationAction(ISD::XOR , VT, Promote);
421 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
422 setOperationAction(ISD::LOAD , VT, Promote);
423 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
424 setOperationAction(ISD::SELECT, VT, Promote);
425 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
426 setOperationAction(ISD::STORE, VT, Promote);
427 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
429 // No other operations are legal.
430 setOperationAction(ISD::MUL , VT, Expand);
431 setOperationAction(ISD::SDIV, VT, Expand);
432 setOperationAction(ISD::SREM, VT, Expand);
433 setOperationAction(ISD::UDIV, VT, Expand);
434 setOperationAction(ISD::UREM, VT, Expand);
435 setOperationAction(ISD::FDIV, VT, Expand);
436 setOperationAction(ISD::FREM, VT, Expand);
437 setOperationAction(ISD::FNEG, VT, Expand);
438 setOperationAction(ISD::FSQRT, VT, Expand);
439 setOperationAction(ISD::FLOG, VT, Expand);
440 setOperationAction(ISD::FLOG10, VT, Expand);
441 setOperationAction(ISD::FLOG2, VT, Expand);
442 setOperationAction(ISD::FEXP, VT, Expand);
443 setOperationAction(ISD::FEXP2, VT, Expand);
444 setOperationAction(ISD::FSIN, VT, Expand);
445 setOperationAction(ISD::FCOS, VT, Expand);
446 setOperationAction(ISD::FABS, VT, Expand);
447 setOperationAction(ISD::FPOWI, VT, Expand);
448 setOperationAction(ISD::FFLOOR, VT, Expand);
449 setOperationAction(ISD::FCEIL, VT, Expand);
450 setOperationAction(ISD::FTRUNC, VT, Expand);
451 setOperationAction(ISD::FRINT, VT, Expand);
452 setOperationAction(ISD::FNEARBYINT, VT, Expand);
453 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
454 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
455 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
456 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
457 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
458 setOperationAction(ISD::UDIVREM, VT, Expand);
459 setOperationAction(ISD::SDIVREM, VT, Expand);
460 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
461 setOperationAction(ISD::FPOW, VT, Expand);
462 setOperationAction(ISD::BSWAP, VT, Expand);
463 setOperationAction(ISD::CTPOP, VT, Expand);
464 setOperationAction(ISD::CTLZ, VT, Expand);
465 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
466 setOperationAction(ISD::CTTZ, VT, Expand);
467 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
468 setOperationAction(ISD::VSELECT, VT, Expand);
469 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
471 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
472 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
473 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
474 setTruncStoreAction(VT, InnerVT, Expand);
476 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
477 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
478 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
481 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
482 // with merges, splats, etc.
483 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
485 setOperationAction(ISD::AND , MVT::v4i32, Legal);
486 setOperationAction(ISD::OR , MVT::v4i32, Legal);
487 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
488 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
489 setOperationAction(ISD::SELECT, MVT::v4i32,
490 Subtarget.useCRBits() ? Legal : Expand);
491 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
492 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
493 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
494 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
495 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
496 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
497 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
498 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
499 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
501 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
502 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
503 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
504 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
506 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
507 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
509 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
510 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
511 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
514 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
515 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
516 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
518 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
519 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
521 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
522 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
523 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
524 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
526 // Altivec does not contain unordered floating-point compare instructions
527 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
528 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
529 setCondCodeAction(ISD::SETUGT, MVT::v4f32, Expand);
530 setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand);
531 setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand);
532 setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand);
534 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
535 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
537 if (Subtarget.hasVSX()) {
538 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
539 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
541 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
542 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
543 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
544 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
545 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
547 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
549 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
550 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
552 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
553 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
555 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
556 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
557 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
558 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
559 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
561 // Share the Altivec comparison restrictions.
562 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
563 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
564 setCondCodeAction(ISD::SETUGT, MVT::v2f64, Expand);
565 setCondCodeAction(ISD::SETUGE, MVT::v2f64, Expand);
566 setCondCodeAction(ISD::SETULT, MVT::v2f64, Expand);
567 setCondCodeAction(ISD::SETULE, MVT::v2f64, Expand);
569 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
570 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
572 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
573 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
575 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
577 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
579 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
580 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
582 // VSX v2i64 only supports non-arithmetic operations.
583 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
584 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
586 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
587 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
588 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
590 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
592 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
593 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
594 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
595 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
597 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
599 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
600 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
601 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
602 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
604 // Vector operation legalization checks the result type of
605 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
606 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
607 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
608 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
609 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
611 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
615 if (Subtarget.has64BitSupport()) {
616 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
617 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
620 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
621 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
622 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
623 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
625 setBooleanContents(ZeroOrOneBooleanContent);
626 // Altivec instructions set fields to all zeros or all ones.
627 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
630 setStackPointerRegisterToSaveRestore(PPC::X1);
631 setExceptionPointerRegister(PPC::X3);
632 setExceptionSelectorRegister(PPC::X4);
634 setStackPointerRegisterToSaveRestore(PPC::R1);
635 setExceptionPointerRegister(PPC::R3);
636 setExceptionSelectorRegister(PPC::R4);
639 // We have target-specific dag combine patterns for the following nodes:
640 setTargetDAGCombine(ISD::SINT_TO_FP);
641 setTargetDAGCombine(ISD::LOAD);
642 setTargetDAGCombine(ISD::STORE);
643 setTargetDAGCombine(ISD::BR_CC);
644 if (Subtarget.useCRBits())
645 setTargetDAGCombine(ISD::BRCOND);
646 setTargetDAGCombine(ISD::BSWAP);
647 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
649 setTargetDAGCombine(ISD::SIGN_EXTEND);
650 setTargetDAGCombine(ISD::ZERO_EXTEND);
651 setTargetDAGCombine(ISD::ANY_EXTEND);
653 if (Subtarget.useCRBits()) {
654 setTargetDAGCombine(ISD::TRUNCATE);
655 setTargetDAGCombine(ISD::SETCC);
656 setTargetDAGCombine(ISD::SELECT_CC);
659 // Use reciprocal estimates.
660 if (TM.Options.UnsafeFPMath) {
661 setTargetDAGCombine(ISD::FDIV);
662 setTargetDAGCombine(ISD::FSQRT);
665 // Darwin long double math library functions have $LDBL128 appended.
666 if (Subtarget.isDarwin()) {
667 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
668 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
669 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
670 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
671 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
672 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
673 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
674 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
675 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
676 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
679 // With 32 condition bits, we don't need to sink (and duplicate) compares
680 // aggressively in CodeGenPrep.
681 if (Subtarget.useCRBits())
682 setHasMultipleConditionRegisters();
684 setMinFunctionAlignment(2);
685 if (Subtarget.isDarwin())
686 setPrefFunctionAlignment(4);
688 if (isPPC64 && Subtarget.isJITCodeModel())
689 // Temporary workaround for the inability of PPC64 JIT to handle jump
691 setSupportJumpTables(false);
693 setInsertFencesForAtomic(true);
695 if (Subtarget.enableMachineScheduler())
696 setSchedulingPreference(Sched::Source);
698 setSchedulingPreference(Sched::Hybrid);
700 computeRegisterProperties();
702 // The Freescale cores does better with aggressive inlining of memcpy and
703 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores).
704 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
705 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
706 MaxStoresPerMemset = 32;
707 MaxStoresPerMemsetOptSize = 16;
708 MaxStoresPerMemcpy = 32;
709 MaxStoresPerMemcpyOptSize = 8;
710 MaxStoresPerMemmove = 32;
711 MaxStoresPerMemmoveOptSize = 8;
713 setPrefFunctionAlignment(4);
717 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
718 /// the desired ByVal argument alignment.
719 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
720 unsigned MaxMaxAlign) {
721 if (MaxAlign == MaxMaxAlign)
723 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
724 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
726 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
728 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
729 unsigned EltAlign = 0;
730 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
731 if (EltAlign > MaxAlign)
733 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
734 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
735 unsigned EltAlign = 0;
736 getMaxByValAlign(STy->getElementType(i), EltAlign, MaxMaxAlign);
737 if (EltAlign > MaxAlign)
739 if (MaxAlign == MaxMaxAlign)
745 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
746 /// function arguments in the caller parameter area.
747 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
748 // Darwin passes everything on 4 byte boundary.
749 if (Subtarget.isDarwin())
752 // 16byte and wider vectors are passed on 16byte boundary.
753 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
754 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
755 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
756 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
760 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
762 default: return nullptr;
763 case PPCISD::FSEL: return "PPCISD::FSEL";
764 case PPCISD::FCFID: return "PPCISD::FCFID";
765 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
766 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
767 case PPCISD::FRE: return "PPCISD::FRE";
768 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
769 case PPCISD::STFIWX: return "PPCISD::STFIWX";
770 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
771 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
772 case PPCISD::VPERM: return "PPCISD::VPERM";
773 case PPCISD::Hi: return "PPCISD::Hi";
774 case PPCISD::Lo: return "PPCISD::Lo";
775 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
776 case PPCISD::LOAD: return "PPCISD::LOAD";
777 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
778 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
779 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
780 case PPCISD::SRL: return "PPCISD::SRL";
781 case PPCISD::SRA: return "PPCISD::SRA";
782 case PPCISD::SHL: return "PPCISD::SHL";
783 case PPCISD::CALL: return "PPCISD::CALL";
784 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
785 case PPCISD::MTCTR: return "PPCISD::MTCTR";
786 case PPCISD::BCTRL: return "PPCISD::BCTRL";
787 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
788 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
789 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
790 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
791 case PPCISD::VCMP: return "PPCISD::VCMP";
792 case PPCISD::VCMPo: return "PPCISD::VCMPo";
793 case PPCISD::LBRX: return "PPCISD::LBRX";
794 case PPCISD::STBRX: return "PPCISD::STBRX";
795 case PPCISD::LARX: return "PPCISD::LARX";
796 case PPCISD::STCX: return "PPCISD::STCX";
797 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
798 case PPCISD::BDNZ: return "PPCISD::BDNZ";
799 case PPCISD::BDZ: return "PPCISD::BDZ";
800 case PPCISD::MFFS: return "PPCISD::MFFS";
801 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
802 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
803 case PPCISD::CR6SET: return "PPCISD::CR6SET";
804 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
805 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
806 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
807 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
808 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
809 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
810 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
811 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
812 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
813 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
814 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
815 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
816 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
817 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
818 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
819 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
820 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
821 case PPCISD::SC: return "PPCISD::SC";
825 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
827 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
828 return VT.changeVectorElementTypeToInteger();
831 //===----------------------------------------------------------------------===//
832 // Node matching predicates, for use by the tblgen matching code.
833 //===----------------------------------------------------------------------===//
835 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
836 static bool isFloatingPointZero(SDValue Op) {
837 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
838 return CFP->getValueAPF().isZero();
839 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
840 // Maybe this has already been legalized into the constant pool?
841 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
842 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
843 return CFP->getValueAPF().isZero();
848 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
849 /// true if Op is undef or if it matches the specified value.
850 static bool isConstantOrUndef(int Op, int Val) {
851 return Op < 0 || Op == Val;
854 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
855 /// VPKUHUM instruction.
856 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary,
858 unsigned j = DAG.getTarget().getDataLayout()->isLittleEndian() ? 0 : 1;
860 for (unsigned i = 0; i != 16; ++i)
861 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j))
864 for (unsigned i = 0; i != 8; ++i)
865 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
866 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
872 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
873 /// VPKUWUM instruction.
874 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary,
877 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
885 for (unsigned i = 0; i != 16; i += 2)
886 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
887 !isConstantOrUndef(N->getMaskElt(i+1), i*2+k))
890 for (unsigned i = 0; i != 8; i += 2)
891 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
892 !isConstantOrUndef(N->getMaskElt(i+1), i*2+k) ||
893 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
894 !isConstantOrUndef(N->getMaskElt(i+9), i*2+k))
900 /// isVMerge - Common function, used to match vmrg* shuffles.
902 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
903 unsigned LHSStart, unsigned RHSStart) {
904 if (N->getValueType(0) != MVT::v16i8)
906 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
907 "Unsupported merge size!");
909 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
910 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
911 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
912 LHSStart+j+i*UnitSize) ||
913 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
914 RHSStart+j+i*UnitSize))
920 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
921 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
922 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
923 bool isUnary, SelectionDAG &DAG) {
924 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
926 return isVMerge(N, UnitSize, 0, 16);
927 return isVMerge(N, UnitSize, 0, 0);
930 return isVMerge(N, UnitSize, 8, 24);
931 return isVMerge(N, UnitSize, 8, 8);
935 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
936 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
937 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
938 bool isUnary, SelectionDAG &DAG) {
939 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
941 return isVMerge(N, UnitSize, 8, 24);
942 return isVMerge(N, UnitSize, 8, 8);
945 return isVMerge(N, UnitSize, 0, 16);
946 return isVMerge(N, UnitSize, 0, 0);
951 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
952 /// amount, otherwise return -1.
953 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary, SelectionDAG &DAG) {
954 if (N->getValueType(0) != MVT::v16i8)
957 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
959 // Find the first non-undef value in the shuffle mask.
961 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
964 if (i == 16) return -1; // all undef.
966 // Otherwise, check to see if the rest of the elements are consecutively
967 // numbered from this value.
968 unsigned ShiftAmt = SVOp->getMaskElt(i);
969 if (ShiftAmt < i) return -1;
971 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
976 // Check the rest of the elements to see if they are consecutive.
977 for (++i; i != 16; ++i)
978 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt - i))
981 // Check the rest of the elements to see if they are consecutive.
982 for (++i; i != 16; ++i)
983 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt - i) & 15))
987 } else { // Big Endian
992 // Check the rest of the elements to see if they are consecutive.
993 for (++i; i != 16; ++i)
994 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
997 // Check the rest of the elements to see if they are consecutive.
998 for (++i; i != 16; ++i)
999 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1006 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1007 /// specifies a splat of a single element that is suitable for input to
1008 /// VSPLTB/VSPLTH/VSPLTW.
1009 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1010 assert(N->getValueType(0) == MVT::v16i8 &&
1011 (EltSize == 1 || EltSize == 2 || EltSize == 4));
1013 // This is a splat operation if each element of the permute is the same, and
1014 // if the value doesn't reference the second vector.
1015 unsigned ElementBase = N->getMaskElt(0);
1017 // FIXME: Handle UNDEF elements too!
1018 if (ElementBase >= 16)
1021 // Check that the indices are consecutive, in the case of a multi-byte element
1022 // splatted with a v16i8 mask.
1023 for (unsigned i = 1; i != EltSize; ++i)
1024 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1027 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1028 if (N->getMaskElt(i) < 0) continue;
1029 for (unsigned j = 0; j != EltSize; ++j)
1030 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1036 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
1038 bool PPC::isAllNegativeZeroVector(SDNode *N) {
1039 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
1041 APInt APVal, APUndef;
1045 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
1046 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
1047 return CFP->getValueAPF().isNegZero();
1052 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1053 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1054 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1055 SelectionDAG &DAG) {
1056 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1057 assert(isSplatShuffleMask(SVOp, EltSize));
1058 if (DAG.getTarget().getDataLayout()->isLittleEndian())
1059 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1061 return SVOp->getMaskElt(0) / EltSize;
1064 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1065 /// by using a vspltis[bhw] instruction of the specified element size, return
1066 /// the constant being splatted. The ByteSize field indicates the number of
1067 /// bytes of each element [124] -> [bhw].
1068 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1069 SDValue OpVal(nullptr, 0);
1071 // If ByteSize of the splat is bigger than the element size of the
1072 // build_vector, then we have a case where we are checking for a splat where
1073 // multiple elements of the buildvector are folded together into a single
1074 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1075 unsigned EltSize = 16/N->getNumOperands();
1076 if (EltSize < ByteSize) {
1077 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1078 SDValue UniquedVals[4];
1079 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1081 // See if all of the elements in the buildvector agree across.
1082 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1083 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1084 // If the element isn't a constant, bail fully out.
1085 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1088 if (!UniquedVals[i&(Multiple-1)].getNode())
1089 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1090 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1091 return SDValue(); // no match.
1094 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1095 // either constant or undef values that are identical for each chunk. See
1096 // if these chunks can form into a larger vspltis*.
1098 // Check to see if all of the leading entries are either 0 or -1. If
1099 // neither, then this won't fit into the immediate field.
1100 bool LeadingZero = true;
1101 bool LeadingOnes = true;
1102 for (unsigned i = 0; i != Multiple-1; ++i) {
1103 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1105 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
1106 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
1108 // Finally, check the least significant entry.
1110 if (!UniquedVals[Multiple-1].getNode())
1111 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
1112 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1114 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
1117 if (!UniquedVals[Multiple-1].getNode())
1118 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
1119 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1120 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1121 return DAG.getTargetConstant(Val, MVT::i32);
1127 // Check to see if this buildvec has a single non-undef value in its elements.
1128 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1129 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1130 if (!OpVal.getNode())
1131 OpVal = N->getOperand(i);
1132 else if (OpVal != N->getOperand(i))
1136 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1138 unsigned ValSizeInBytes = EltSize;
1140 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1141 Value = CN->getZExtValue();
1142 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1143 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1144 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1147 // If the splat value is larger than the element value, then we can never do
1148 // this splat. The only case that we could fit the replicated bits into our
1149 // immediate field for would be zero, and we prefer to use vxor for it.
1150 if (ValSizeInBytes < ByteSize) return SDValue();
1152 // If the element value is larger than the splat value, cut it in half and
1153 // check to see if the two halves are equal. Continue doing this until we
1154 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
1155 while (ValSizeInBytes > ByteSize) {
1156 ValSizeInBytes >>= 1;
1158 // If the top half equals the bottom half, we're still ok.
1159 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
1160 (Value & ((1 << (8*ValSizeInBytes))-1)))
1164 // Properly sign extend the value.
1165 int MaskVal = SignExtend32(Value, ByteSize * 8);
1167 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1168 if (MaskVal == 0) return SDValue();
1170 // Finally, if this value fits in a 5 bit sext field, return it
1171 if (SignExtend32<5>(MaskVal) == MaskVal)
1172 return DAG.getTargetConstant(MaskVal, MVT::i32);
1176 //===----------------------------------------------------------------------===//
1177 // Addressing Mode Selection
1178 //===----------------------------------------------------------------------===//
1180 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1181 /// or 64-bit immediate, and if the value can be accurately represented as a
1182 /// sign extension from a 16-bit value. If so, this returns true and the
1184 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1185 if (!isa<ConstantSDNode>(N))
1188 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1189 if (N->getValueType(0) == MVT::i32)
1190 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1192 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1194 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1195 return isIntS16Immediate(Op.getNode(), Imm);
1199 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1200 /// can be represented as an indexed [r+r] operation. Returns false if it
1201 /// can be more efficiently represented with [r+imm].
1202 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1204 SelectionDAG &DAG) const {
1206 if (N.getOpcode() == ISD::ADD) {
1207 if (isIntS16Immediate(N.getOperand(1), imm))
1208 return false; // r+i
1209 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1210 return false; // r+i
1212 Base = N.getOperand(0);
1213 Index = N.getOperand(1);
1215 } else if (N.getOpcode() == ISD::OR) {
1216 if (isIntS16Immediate(N.getOperand(1), imm))
1217 return false; // r+i can fold it if we can.
1219 // If this is an or of disjoint bitfields, we can codegen this as an add
1220 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1222 APInt LHSKnownZero, LHSKnownOne;
1223 APInt RHSKnownZero, RHSKnownOne;
1224 DAG.computeKnownBits(N.getOperand(0),
1225 LHSKnownZero, LHSKnownOne);
1227 if (LHSKnownZero.getBoolValue()) {
1228 DAG.computeKnownBits(N.getOperand(1),
1229 RHSKnownZero, RHSKnownOne);
1230 // If all of the bits are known zero on the LHS or RHS, the add won't
1232 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1233 Base = N.getOperand(0);
1234 Index = N.getOperand(1);
1243 // If we happen to be doing an i64 load or store into a stack slot that has
1244 // less than a 4-byte alignment, then the frame-index elimination may need to
1245 // use an indexed load or store instruction (because the offset may not be a
1246 // multiple of 4). The extra register needed to hold the offset comes from the
1247 // register scavenger, and it is possible that the scavenger will need to use
1248 // an emergency spill slot. As a result, we need to make sure that a spill slot
1249 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1251 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1252 // FIXME: This does not handle the LWA case.
1256 // NOTE: We'll exclude negative FIs here, which come from argument
1257 // lowering, because there are no known test cases triggering this problem
1258 // using packed structures (or similar). We can remove this exclusion if
1259 // we find such a test case. The reason why this is so test-case driven is
1260 // because this entire 'fixup' is only to prevent crashes (from the
1261 // register scavenger) on not-really-valid inputs. For example, if we have:
1263 // %b = bitcast i1* %a to i64*
1264 // store i64* a, i64 b
1265 // then the store should really be marked as 'align 1', but is not. If it
1266 // were marked as 'align 1' then the indexed form would have been
1267 // instruction-selected initially, and the problem this 'fixup' is preventing
1268 // won't happen regardless.
1272 MachineFunction &MF = DAG.getMachineFunction();
1273 MachineFrameInfo *MFI = MF.getFrameInfo();
1275 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1279 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1280 FuncInfo->setHasNonRISpills();
1283 /// Returns true if the address N can be represented by a base register plus
1284 /// a signed 16-bit displacement [r+imm], and if it is not better
1285 /// represented as reg+reg. If Aligned is true, only accept displacements
1286 /// suitable for STD and friends, i.e. multiples of 4.
1287 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1290 bool Aligned) const {
1291 // FIXME dl should come from parent load or store, not from address
1293 // If this can be more profitably realized as r+r, fail.
1294 if (SelectAddressRegReg(N, Disp, Base, DAG))
1297 if (N.getOpcode() == ISD::ADD) {
1299 if (isIntS16Immediate(N.getOperand(1), imm) &&
1300 (!Aligned || (imm & 3) == 0)) {
1301 Disp = DAG.getTargetConstant(imm, N.getValueType());
1302 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1303 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1304 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1306 Base = N.getOperand(0);
1308 return true; // [r+i]
1309 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1310 // Match LOAD (ADD (X, Lo(G))).
1311 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1312 && "Cannot handle constant offsets yet!");
1313 Disp = N.getOperand(1).getOperand(0); // The global address.
1314 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1315 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1316 Disp.getOpcode() == ISD::TargetConstantPool ||
1317 Disp.getOpcode() == ISD::TargetJumpTable);
1318 Base = N.getOperand(0);
1319 return true; // [&g+r]
1321 } else if (N.getOpcode() == ISD::OR) {
1323 if (isIntS16Immediate(N.getOperand(1), imm) &&
1324 (!Aligned || (imm & 3) == 0)) {
1325 // If this is an or of disjoint bitfields, we can codegen this as an add
1326 // (for better address arithmetic) if the LHS and RHS of the OR are
1327 // provably disjoint.
1328 APInt LHSKnownZero, LHSKnownOne;
1329 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1331 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1332 // If all of the bits are known zero on the LHS or RHS, the add won't
1334 Base = N.getOperand(0);
1335 Disp = DAG.getTargetConstant(imm, N.getValueType());
1339 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1340 // Loading from a constant address.
1342 // If this address fits entirely in a 16-bit sext immediate field, codegen
1345 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1346 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1347 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1348 CN->getValueType(0));
1352 // Handle 32-bit sext immediates with LIS + addr mode.
1353 if ((CN->getValueType(0) == MVT::i32 ||
1354 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1355 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1356 int Addr = (int)CN->getZExtValue();
1358 // Otherwise, break this down into an LIS + disp.
1359 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1361 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1362 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1363 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1368 Disp = DAG.getTargetConstant(0, getPointerTy());
1369 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1370 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1371 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1374 return true; // [r+0]
1377 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1378 /// represented as an indexed [r+r] operation.
1379 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1381 SelectionDAG &DAG) const {
1382 // Check to see if we can easily represent this as an [r+r] address. This
1383 // will fail if it thinks that the address is more profitably represented as
1384 // reg+imm, e.g. where imm = 0.
1385 if (SelectAddressRegReg(N, Base, Index, DAG))
1388 // If the operand is an addition, always emit this as [r+r], since this is
1389 // better (for code size, and execution, as the memop does the add for free)
1390 // than emitting an explicit add.
1391 if (N.getOpcode() == ISD::ADD) {
1392 Base = N.getOperand(0);
1393 Index = N.getOperand(1);
1397 // Otherwise, do it the hard way, using R0 as the base register.
1398 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1404 /// getPreIndexedAddressParts - returns true by value, base pointer and
1405 /// offset pointer and addressing mode by reference if the node's address
1406 /// can be legally represented as pre-indexed load / store address.
1407 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1409 ISD::MemIndexedMode &AM,
1410 SelectionDAG &DAG) const {
1411 if (DisablePPCPreinc) return false;
1417 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1418 Ptr = LD->getBasePtr();
1419 VT = LD->getMemoryVT();
1420 Alignment = LD->getAlignment();
1421 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1422 Ptr = ST->getBasePtr();
1423 VT = ST->getMemoryVT();
1424 Alignment = ST->getAlignment();
1429 // PowerPC doesn't have preinc load/store instructions for vectors.
1433 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1435 // Common code will reject creating a pre-inc form if the base pointer
1436 // is a frame index, or if N is a store and the base pointer is either
1437 // the same as or a predecessor of the value being stored. Check for
1438 // those situations here, and try with swapped Base/Offset instead.
1441 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1444 SDValue Val = cast<StoreSDNode>(N)->getValue();
1445 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1450 std::swap(Base, Offset);
1456 // LDU/STU can only handle immediates that are a multiple of 4.
1457 if (VT != MVT::i64) {
1458 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1461 // LDU/STU need an address with at least 4-byte alignment.
1465 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1469 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1470 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1471 // sext i32 to i64 when addr mode is r+i.
1472 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1473 LD->getExtensionType() == ISD::SEXTLOAD &&
1474 isa<ConstantSDNode>(Offset))
1482 //===----------------------------------------------------------------------===//
1483 // LowerOperation implementation
1484 //===----------------------------------------------------------------------===//
1486 /// GetLabelAccessInfo - Return true if we should reference labels using a
1487 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1488 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1489 unsigned &LoOpFlags,
1490 const GlobalValue *GV = nullptr) {
1491 HiOpFlags = PPCII::MO_HA;
1492 LoOpFlags = PPCII::MO_LO;
1494 // Don't use the pic base if not in PIC relocation model. Or if we are on a
1495 // non-darwin platform. We don't support PIC on other platforms yet.
1496 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ &&
1497 TM.getSubtarget<PPCSubtarget>().isDarwin();
1499 HiOpFlags |= PPCII::MO_PIC_FLAG;
1500 LoOpFlags |= PPCII::MO_PIC_FLAG;
1503 // If this is a reference to a global value that requires a non-lazy-ptr, make
1504 // sure that instruction lowering adds it.
1505 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1506 HiOpFlags |= PPCII::MO_NLP_FLAG;
1507 LoOpFlags |= PPCII::MO_NLP_FLAG;
1509 if (GV->hasHiddenVisibility()) {
1510 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1511 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1518 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1519 SelectionDAG &DAG) {
1520 EVT PtrVT = HiPart.getValueType();
1521 SDValue Zero = DAG.getConstant(0, PtrVT);
1524 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1525 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1527 // With PIC, the first instruction is actually "GR+hi(&G)".
1529 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1530 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1532 // Generate non-pic code that has direct accesses to the constant pool.
1533 // The address of the global is just (hi(&g)+lo(&g)).
1534 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1537 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1538 SelectionDAG &DAG) const {
1539 EVT PtrVT = Op.getValueType();
1540 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1541 const Constant *C = CP->getConstVal();
1543 // 64-bit SVR4 ABI code is always position-independent.
1544 // The actual address of the GlobalValue is stored in the TOC.
1545 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1546 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1547 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1548 DAG.getRegister(PPC::X2, MVT::i64));
1551 unsigned MOHiFlag, MOLoFlag;
1552 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1554 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1556 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1557 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1560 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1561 EVT PtrVT = Op.getValueType();
1562 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1564 // 64-bit SVR4 ABI code is always position-independent.
1565 // The actual address of the GlobalValue is stored in the TOC.
1566 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1567 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1568 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1569 DAG.getRegister(PPC::X2, MVT::i64));
1572 unsigned MOHiFlag, MOLoFlag;
1573 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1574 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1575 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1576 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1579 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1580 SelectionDAG &DAG) const {
1581 EVT PtrVT = Op.getValueType();
1583 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1585 unsigned MOHiFlag, MOLoFlag;
1586 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1587 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1588 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1589 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1592 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1593 SelectionDAG &DAG) const {
1595 // FIXME: TLS addresses currently use medium model code sequences,
1596 // which is the most useful form. Eventually support for small and
1597 // large models could be added if users need it, at the cost of
1598 // additional complexity.
1599 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1601 const GlobalValue *GV = GA->getGlobal();
1602 EVT PtrVT = getPointerTy();
1603 bool is64bit = Subtarget.isPPC64();
1605 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1607 if (Model == TLSModel::LocalExec) {
1608 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1609 PPCII::MO_TPREL_HA);
1610 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1611 PPCII::MO_TPREL_LO);
1612 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1613 is64bit ? MVT::i64 : MVT::i32);
1614 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1615 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1618 if (Model == TLSModel::InitialExec) {
1619 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1620 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1624 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1625 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1626 PtrVT, GOTReg, TGA);
1628 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
1629 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1630 PtrVT, TGA, GOTPtr);
1631 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
1634 if (Model == TLSModel::GeneralDynamic) {
1635 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1636 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1637 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1639 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1642 // We need a chain node, and don't have one handy. The underlying
1643 // call has no side effects, so using the function entry node
1645 SDValue Chain = DAG.getEntryNode();
1646 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1647 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1648 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl,
1649 PtrVT, ParmReg, TGA);
1650 // The return value from GET_TLS_ADDR really is in X3 already, but
1651 // some hacks are needed here to tie everything together. The extra
1652 // copies dissolve during subsequent transforms.
1653 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1654 return DAG.getCopyFromReg(Chain, dl, PPC::X3, PtrVT);
1657 if (Model == TLSModel::LocalDynamic) {
1658 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1659 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1660 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1662 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1665 // We need a chain node, and don't have one handy. The underlying
1666 // call has no side effects, so using the function entry node
1668 SDValue Chain = DAG.getEntryNode();
1669 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1670 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1671 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl,
1672 PtrVT, ParmReg, TGA);
1673 // The return value from GET_TLSLD_ADDR really is in X3 already, but
1674 // some hacks are needed here to tie everything together. The extra
1675 // copies dissolve during subsequent transforms.
1676 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1677 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1678 Chain, ParmReg, TGA);
1679 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1682 llvm_unreachable("Unknown TLS model!");
1685 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1686 SelectionDAG &DAG) const {
1687 EVT PtrVT = Op.getValueType();
1688 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1690 const GlobalValue *GV = GSDN->getGlobal();
1692 // 64-bit SVR4 ABI code is always position-independent.
1693 // The actual address of the GlobalValue is stored in the TOC.
1694 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1695 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1696 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1697 DAG.getRegister(PPC::X2, MVT::i64));
1700 unsigned MOHiFlag, MOLoFlag;
1701 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1704 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1706 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1708 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1710 // If the global reference is actually to a non-lazy-pointer, we have to do an
1711 // extra load to get the address of the global.
1712 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1713 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1714 false, false, false, 0);
1718 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1719 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1722 if (Op.getValueType() == MVT::v2i64) {
1723 // When the operands themselves are v2i64 values, we need to do something
1724 // special because VSX has no underlying comparison operations for these.
1725 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
1726 // Equality can be handled by casting to the legal type for Altivec
1727 // comparisons, everything else needs to be expanded.
1728 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1729 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
1730 DAG.getSetCC(dl, MVT::v4i32,
1731 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
1732 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
1739 // We handle most of these in the usual way.
1743 // If we're comparing for equality to zero, expose the fact that this is
1744 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1745 // fold the new nodes.
1746 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1747 if (C->isNullValue() && CC == ISD::SETEQ) {
1748 EVT VT = Op.getOperand(0).getValueType();
1749 SDValue Zext = Op.getOperand(0);
1750 if (VT.bitsLT(MVT::i32)) {
1752 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1754 unsigned Log2b = Log2_32(VT.getSizeInBits());
1755 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1756 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1757 DAG.getConstant(Log2b, MVT::i32));
1758 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1760 // Leave comparisons against 0 and -1 alone for now, since they're usually
1761 // optimized. FIXME: revisit this when we can custom lower all setcc
1763 if (C->isAllOnesValue() || C->isNullValue())
1767 // If we have an integer seteq/setne, turn it into a compare against zero
1768 // by xor'ing the rhs with the lhs, which is faster than setting a
1769 // condition register, reading it back out, and masking the correct bit. The
1770 // normal approach here uses sub to do this instead of xor. Using xor exposes
1771 // the result to other bit-twiddling opportunities.
1772 EVT LHSVT = Op.getOperand(0).getValueType();
1773 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1774 EVT VT = Op.getValueType();
1775 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1777 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1782 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1783 const PPCSubtarget &Subtarget) const {
1784 SDNode *Node = Op.getNode();
1785 EVT VT = Node->getValueType(0);
1786 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1787 SDValue InChain = Node->getOperand(0);
1788 SDValue VAListPtr = Node->getOperand(1);
1789 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1792 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1795 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1796 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1798 InChain = GprIndex.getValue(1);
1800 if (VT == MVT::i64) {
1801 // Check if GprIndex is even
1802 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1803 DAG.getConstant(1, MVT::i32));
1804 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1805 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1806 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1807 DAG.getConstant(1, MVT::i32));
1808 // Align GprIndex to be even if it isn't
1809 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1813 // fpr index is 1 byte after gpr
1814 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1815 DAG.getConstant(1, MVT::i32));
1818 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1819 FprPtr, MachinePointerInfo(SV), MVT::i8,
1821 InChain = FprIndex.getValue(1);
1823 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1824 DAG.getConstant(8, MVT::i32));
1826 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1827 DAG.getConstant(4, MVT::i32));
1830 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1831 MachinePointerInfo(), false, false,
1833 InChain = OverflowArea.getValue(1);
1835 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1836 MachinePointerInfo(), false, false,
1838 InChain = RegSaveArea.getValue(1);
1840 // select overflow_area if index > 8
1841 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1842 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1844 // adjustment constant gpr_index * 4/8
1845 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1846 VT.isInteger() ? GprIndex : FprIndex,
1847 DAG.getConstant(VT.isInteger() ? 4 : 8,
1850 // OurReg = RegSaveArea + RegConstant
1851 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1854 // Floating types are 32 bytes into RegSaveArea
1855 if (VT.isFloatingPoint())
1856 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1857 DAG.getConstant(32, MVT::i32));
1859 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1860 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1861 VT.isInteger() ? GprIndex : FprIndex,
1862 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1865 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1866 VT.isInteger() ? VAListPtr : FprPtr,
1867 MachinePointerInfo(SV),
1868 MVT::i8, false, false, 0);
1870 // determine if we should load from reg_save_area or overflow_area
1871 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1873 // increase overflow_area by 4/8 if gpr/fpr > 8
1874 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1875 DAG.getConstant(VT.isInteger() ? 4 : 8,
1878 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1881 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1883 MachinePointerInfo(),
1884 MVT::i32, false, false, 0);
1886 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1887 false, false, false, 0);
1890 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
1891 const PPCSubtarget &Subtarget) const {
1892 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
1894 // We have to copy the entire va_list struct:
1895 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
1896 return DAG.getMemcpy(Op.getOperand(0), Op,
1897 Op.getOperand(1), Op.getOperand(2),
1898 DAG.getConstant(12, MVT::i32), 8, false, true,
1899 MachinePointerInfo(), MachinePointerInfo());
1902 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
1903 SelectionDAG &DAG) const {
1904 return Op.getOperand(0);
1907 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
1908 SelectionDAG &DAG) const {
1909 SDValue Chain = Op.getOperand(0);
1910 SDValue Trmp = Op.getOperand(1); // trampoline
1911 SDValue FPtr = Op.getOperand(2); // nested function
1912 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1915 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1916 bool isPPC64 = (PtrVT == MVT::i64);
1918 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
1921 TargetLowering::ArgListTy Args;
1922 TargetLowering::ArgListEntry Entry;
1924 Entry.Ty = IntPtrTy;
1925 Entry.Node = Trmp; Args.push_back(Entry);
1927 // TrampSize == (isPPC64 ? 48 : 40);
1928 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1929 isPPC64 ? MVT::i64 : MVT::i32);
1930 Args.push_back(Entry);
1932 Entry.Node = FPtr; Args.push_back(Entry);
1933 Entry.Node = Nest; Args.push_back(Entry);
1935 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1936 TargetLowering::CallLoweringInfo CLI(DAG);
1937 CLI.setDebugLoc(dl).setChain(Chain)
1938 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
1939 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1940 std::move(Args), 0);
1942 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1943 return CallResult.second;
1946 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1947 const PPCSubtarget &Subtarget) const {
1948 MachineFunction &MF = DAG.getMachineFunction();
1949 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1953 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
1954 // vastart just stores the address of the VarArgsFrameIndex slot into the
1955 // memory location argument.
1956 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1957 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1958 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1959 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
1960 MachinePointerInfo(SV),
1964 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
1965 // We suppose the given va_list is already allocated.
1968 // char gpr; /* index into the array of 8 GPRs
1969 // * stored in the register save area
1970 // * gpr=0 corresponds to r3,
1971 // * gpr=1 to r4, etc.
1973 // char fpr; /* index into the array of 8 FPRs
1974 // * stored in the register save area
1975 // * fpr=0 corresponds to f1,
1976 // * fpr=1 to f2, etc.
1978 // char *overflow_arg_area;
1979 // /* location on stack that holds
1980 // * the next overflow argument
1982 // char *reg_save_area;
1983 // /* where r3:r10 and f1:f8 (if saved)
1989 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
1990 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
1993 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1995 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
1997 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2000 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2001 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
2003 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2004 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
2006 uint64_t FPROffset = 1;
2007 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
2009 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2011 // Store first byte : number of int regs
2012 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
2014 MachinePointerInfo(SV),
2015 MVT::i8, false, false, 0);
2016 uint64_t nextOffset = FPROffset;
2017 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2020 // Store second byte : number of float regs
2021 SDValue secondStore =
2022 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2023 MachinePointerInfo(SV, nextOffset), MVT::i8,
2025 nextOffset += StackOffset;
2026 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2028 // Store second word : arguments given on stack
2029 SDValue thirdStore =
2030 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2031 MachinePointerInfo(SV, nextOffset),
2033 nextOffset += FrameOffset;
2034 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2036 // Store third word : arguments given in registers
2037 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2038 MachinePointerInfo(SV, nextOffset),
2043 #include "PPCGenCallingConv.inc"
2045 // Function whose sole purpose is to kill compiler warnings
2046 // stemming from unused functions included from PPCGenCallingConv.inc.
2047 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2048 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2051 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2052 CCValAssign::LocInfo &LocInfo,
2053 ISD::ArgFlagsTy &ArgFlags,
2058 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2060 CCValAssign::LocInfo &LocInfo,
2061 ISD::ArgFlagsTy &ArgFlags,
2063 static const MCPhysReg ArgRegs[] = {
2064 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2065 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2067 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2069 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2071 // Skip one register if the first unallocated register has an even register
2072 // number and there are still argument registers available which have not been
2073 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2074 // need to skip a register if RegNum is odd.
2075 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2076 State.AllocateReg(ArgRegs[RegNum]);
2079 // Always return false here, as this function only makes sure that the first
2080 // unallocated register has an odd register number and does not actually
2081 // allocate a register for the current argument.
2085 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2087 CCValAssign::LocInfo &LocInfo,
2088 ISD::ArgFlagsTy &ArgFlags,
2090 static const MCPhysReg ArgRegs[] = {
2091 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2095 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2097 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2099 // If there is only one Floating-point register left we need to put both f64
2100 // values of a split ppc_fp128 value on the stack.
2101 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2102 State.AllocateReg(ArgRegs[RegNum]);
2105 // Always return false here, as this function only makes sure that the two f64
2106 // values a ppc_fp128 value is split into are both passed in registers or both
2107 // passed on the stack and does not actually allocate a register for the
2108 // current argument.
2112 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
2114 static const MCPhysReg *GetFPR() {
2115 static const MCPhysReg FPR[] = {
2116 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2117 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
2123 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2125 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2126 unsigned PtrByteSize) {
2127 unsigned ArgSize = ArgVT.getStoreSize();
2128 if (Flags.isByVal())
2129 ArgSize = Flags.getByValSize();
2130 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2135 /// CalculateStackSlotAlignment - Calculates the alignment of this argument
2137 static unsigned CalculateStackSlotAlignment(EVT ArgVT, ISD::ArgFlagsTy Flags,
2138 unsigned PtrByteSize) {
2139 unsigned Align = PtrByteSize;
2141 // Altivec parameters are padded to a 16 byte boundary.
2142 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2143 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2144 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2147 // ByVal parameters are aligned as requested.
2148 if (Flags.isByVal()) {
2149 unsigned BVAlign = Flags.getByValAlign();
2150 if (BVAlign > PtrByteSize) {
2151 if (BVAlign % PtrByteSize != 0)
2153 "ByVal alignment is not a multiple of the pointer size");
2162 /// EnsureStackAlignment - Round stack frame size up from NumBytes to
2163 /// ensure minimum alignment required for target.
2164 static unsigned EnsureStackAlignment(const TargetMachine &Target,
2165 unsigned NumBytes) {
2166 unsigned TargetAlign = Target.getFrameLowering()->getStackAlignment();
2167 unsigned AlignMask = TargetAlign - 1;
2168 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2173 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
2174 CallingConv::ID CallConv, bool isVarArg,
2175 const SmallVectorImpl<ISD::InputArg>
2177 SDLoc dl, SelectionDAG &DAG,
2178 SmallVectorImpl<SDValue> &InVals)
2180 if (Subtarget.isSVR4ABI()) {
2181 if (Subtarget.isPPC64())
2182 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2185 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2188 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2194 PPCTargetLowering::LowerFormalArguments_32SVR4(
2196 CallingConv::ID CallConv, bool isVarArg,
2197 const SmallVectorImpl<ISD::InputArg>
2199 SDLoc dl, SelectionDAG &DAG,
2200 SmallVectorImpl<SDValue> &InVals) const {
2202 // 32-bit SVR4 ABI Stack Frame Layout:
2203 // +-----------------------------------+
2204 // +--> | Back chain |
2205 // | +-----------------------------------+
2206 // | | Floating-point register save area |
2207 // | +-----------------------------------+
2208 // | | General register save area |
2209 // | +-----------------------------------+
2210 // | | CR save word |
2211 // | +-----------------------------------+
2212 // | | VRSAVE save word |
2213 // | +-----------------------------------+
2214 // | | Alignment padding |
2215 // | +-----------------------------------+
2216 // | | Vector register save area |
2217 // | +-----------------------------------+
2218 // | | Local variable space |
2219 // | +-----------------------------------+
2220 // | | Parameter list area |
2221 // | +-----------------------------------+
2222 // | | LR save word |
2223 // | +-----------------------------------+
2224 // SP--> +--- | Back chain |
2225 // +-----------------------------------+
2228 // System V Application Binary Interface PowerPC Processor Supplement
2229 // AltiVec Technology Programming Interface Manual
2231 MachineFunction &MF = DAG.getMachineFunction();
2232 MachineFrameInfo *MFI = MF.getFrameInfo();
2233 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2235 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2236 // Potential tail calls could cause overwriting of argument stack slots.
2237 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2238 (CallConv == CallingConv::Fast));
2239 unsigned PtrByteSize = 4;
2241 // Assign locations to all of the incoming arguments.
2242 SmallVector<CCValAssign, 16> ArgLocs;
2243 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2244 getTargetMachine(), ArgLocs, *DAG.getContext());
2246 // Reserve space for the linkage area on the stack.
2247 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(false, false);
2248 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
2250 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2252 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2253 CCValAssign &VA = ArgLocs[i];
2255 // Arguments stored in registers.
2256 if (VA.isRegLoc()) {
2257 const TargetRegisterClass *RC;
2258 EVT ValVT = VA.getValVT();
2260 switch (ValVT.getSimpleVT().SimpleTy) {
2262 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2265 RC = &PPC::GPRCRegClass;
2268 RC = &PPC::F4RCRegClass;
2271 if (Subtarget.hasVSX())
2272 RC = &PPC::VSFRCRegClass;
2274 RC = &PPC::F8RCRegClass;
2280 RC = &PPC::VRRCRegClass;
2284 RC = &PPC::VSHRCRegClass;
2288 // Transform the arguments stored in physical registers into virtual ones.
2289 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2290 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2291 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2293 if (ValVT == MVT::i1)
2294 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2296 InVals.push_back(ArgValue);
2298 // Argument stored in memory.
2299 assert(VA.isMemLoc());
2301 unsigned ArgSize = VA.getLocVT().getStoreSize();
2302 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2305 // Create load nodes to retrieve arguments from the stack.
2306 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2307 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2308 MachinePointerInfo(),
2309 false, false, false, 0));
2313 // Assign locations to all of the incoming aggregate by value arguments.
2314 // Aggregates passed by value are stored in the local variable space of the
2315 // caller's stack frame, right above the parameter list area.
2316 SmallVector<CCValAssign, 16> ByValArgLocs;
2317 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2318 getTargetMachine(), ByValArgLocs, *DAG.getContext());
2320 // Reserve stack space for the allocations in CCInfo.
2321 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2323 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2325 // Area that is at least reserved in the caller of this function.
2326 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2327 MinReservedArea = std::max(MinReservedArea, LinkageSize);
2329 // Set the size that is at least reserved in caller of this function. Tail
2330 // call optimized function's reserved stack space needs to be aligned so that
2331 // taking the difference between two stack areas will result in an aligned
2333 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2334 FuncInfo->setMinReservedArea(MinReservedArea);
2336 SmallVector<SDValue, 8> MemOps;
2338 // If the function takes variable number of arguments, make a frame index for
2339 // the start of the first vararg value... for expansion of llvm.va_start.
2341 static const MCPhysReg GPArgRegs[] = {
2342 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2343 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2345 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2347 static const MCPhysReg FPArgRegs[] = {
2348 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2351 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2353 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2355 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2358 // Make room for NumGPArgRegs and NumFPArgRegs.
2359 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2360 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
2362 FuncInfo->setVarArgsStackOffset(
2363 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2364 CCInfo.getNextStackOffset(), true));
2366 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2367 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2369 // The fixed integer arguments of a variadic function are stored to the
2370 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2371 // the result of va_next.
2372 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2373 // Get an existing live-in vreg, or add a new one.
2374 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2376 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2378 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2379 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2380 MachinePointerInfo(), false, false, 0);
2381 MemOps.push_back(Store);
2382 // Increment the address by four for the next argument to store
2383 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2384 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2387 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2389 // The double arguments are stored to the VarArgsFrameIndex
2391 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2392 // Get an existing live-in vreg, or add a new one.
2393 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2395 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2397 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2398 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2399 MachinePointerInfo(), false, false, 0);
2400 MemOps.push_back(Store);
2401 // Increment the address by eight for the next argument to store
2402 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
2404 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2408 if (!MemOps.empty())
2409 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2414 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2415 // value to MVT::i64 and then truncate to the correct register size.
2417 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2418 SelectionDAG &DAG, SDValue ArgVal,
2421 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2422 DAG.getValueType(ObjectVT));
2423 else if (Flags.isZExt())
2424 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2425 DAG.getValueType(ObjectVT));
2427 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
2431 PPCTargetLowering::LowerFormalArguments_64SVR4(
2433 CallingConv::ID CallConv, bool isVarArg,
2434 const SmallVectorImpl<ISD::InputArg>
2436 SDLoc dl, SelectionDAG &DAG,
2437 SmallVectorImpl<SDValue> &InVals) const {
2438 // TODO: add description of PPC stack frame format, or at least some docs.
2440 bool isLittleEndian = Subtarget.isLittleEndian();
2441 MachineFunction &MF = DAG.getMachineFunction();
2442 MachineFrameInfo *MFI = MF.getFrameInfo();
2443 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2445 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2446 // Potential tail calls could cause overwriting of argument stack slots.
2447 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2448 (CallConv == CallingConv::Fast));
2449 unsigned PtrByteSize = 8;
2451 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false);
2452 unsigned ArgOffset = LinkageSize;
2454 static const MCPhysReg GPR[] = {
2455 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2456 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2459 static const MCPhysReg *FPR = GetFPR();
2461 static const MCPhysReg VR[] = {
2462 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2463 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2465 static const MCPhysReg VSRH[] = {
2466 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
2467 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
2470 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2471 const unsigned Num_FPR_Regs = 13;
2472 const unsigned Num_VR_Regs = array_lengthof(VR);
2474 unsigned GPR_idx, FPR_idx = 0, VR_idx = 0;
2476 // Add DAG nodes to load the arguments or copy them out of registers. On
2477 // entry to a function on PPC, the arguments start after the linkage area,
2478 // although the first ones are often in registers.
2480 SmallVector<SDValue, 8> MemOps;
2481 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2482 unsigned CurArgIdx = 0;
2483 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2485 bool needsLoad = false;
2486 EVT ObjectVT = Ins[ArgNo].VT;
2487 unsigned ObjSize = ObjectVT.getStoreSize();
2488 unsigned ArgSize = ObjSize;
2489 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2490 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2491 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2493 /* Respect alignment of argument on the stack. */
2495 CalculateStackSlotAlignment(ObjectVT, Flags, PtrByteSize);
2496 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2497 unsigned CurArgOffset = ArgOffset;
2499 /* Compute GPR index associated with argument offset. */
2500 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2501 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
2503 // FIXME the codegen can be much improved in some cases.
2504 // We do not have to keep everything in memory.
2505 if (Flags.isByVal()) {
2506 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2507 ObjSize = Flags.getByValSize();
2508 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2509 // Empty aggregate parameters do not take up registers. Examples:
2513 // etc. However, we have to provide a place-holder in InVals, so
2514 // pretend we have an 8-byte item at the current address for that
2517 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2518 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2519 InVals.push_back(FIN);
2523 // All aggregates smaller than 8 bytes must be passed right-justified.
2524 if (ObjSize < PtrByteSize && !isLittleEndian)
2525 CurArgOffset = CurArgOffset + (PtrByteSize - ObjSize);
2526 // The value of the object is its address.
2527 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2528 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2529 InVals.push_back(FIN);
2532 if (GPR_idx != Num_GPR_Regs) {
2533 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2534 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2537 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2538 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2539 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2540 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2541 MachinePointerInfo(FuncArg),
2542 ObjType, false, false, 0);
2544 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2545 // store the whole register as-is to the parameter save area
2546 // slot. The address of the parameter was already calculated
2547 // above (InVals.push_back(FIN)) to be the right-justified
2548 // offset within the slot. For this store, we need a new
2549 // frame index that points at the beginning of the slot.
2550 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2551 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2552 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2553 MachinePointerInfo(FuncArg),
2557 MemOps.push_back(Store);
2559 // Whether we copied from a register or not, advance the offset
2560 // into the parameter save area by a full doubleword.
2561 ArgOffset += PtrByteSize;
2565 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2566 // Store whatever pieces of the object are in registers
2567 // to memory. ArgOffset will be the address of the beginning
2569 if (GPR_idx != Num_GPR_Regs) {
2571 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2572 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2573 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2574 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2575 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2576 MachinePointerInfo(FuncArg, j),
2578 MemOps.push_back(Store);
2580 ArgOffset += PtrByteSize;
2582 ArgOffset += ArgSize - j;
2589 switch (ObjectVT.getSimpleVT().SimpleTy) {
2590 default: llvm_unreachable("Unhandled argument type!");
2594 if (GPR_idx != Num_GPR_Regs) {
2595 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2596 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2598 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
2599 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2600 // value to MVT::i64 and then truncate to the correct register size.
2601 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2604 ArgSize = PtrByteSize;
2611 if (FPR_idx != Num_FPR_Regs) {
2614 if (ObjectVT == MVT::f32)
2615 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2617 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX() ?
2618 &PPC::VSFRCRegClass :
2619 &PPC::F8RCRegClass);
2621 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2625 ArgSize = PtrByteSize;
2636 if (VR_idx != Num_VR_Regs) {
2637 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
2638 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
2639 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2640 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2649 // We need to load the argument to a virtual register if we determined
2650 // above that we ran out of physical registers of the appropriate type.
2652 if (ObjSize < ArgSize && !isLittleEndian)
2653 CurArgOffset += ArgSize - ObjSize;
2654 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
2655 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2656 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2657 false, false, false, 0);
2660 InVals.push_back(ArgVal);
2663 // Area that is at least reserved in the caller of this function.
2664 unsigned MinReservedArea;
2665 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
2667 // Set the size that is at least reserved in caller of this function. Tail
2668 // call optimized functions' reserved stack space needs to be aligned so that
2669 // taking the difference between two stack areas will result in an aligned
2671 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2672 FuncInfo->setMinReservedArea(MinReservedArea);
2674 // If the function takes variable number of arguments, make a frame index for
2675 // the start of the first vararg value... for expansion of llvm.va_start.
2677 int Depth = ArgOffset;
2679 FuncInfo->setVarArgsFrameIndex(
2680 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2681 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2683 // If this function is vararg, store any remaining integer argument regs
2684 // to their spots on the stack so that they may be loaded by deferencing the
2685 // result of va_next.
2686 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2687 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
2688 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2689 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2690 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2691 MachinePointerInfo(), false, false, 0);
2692 MemOps.push_back(Store);
2693 // Increment the address by four for the next argument to store
2694 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2695 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2699 if (!MemOps.empty())
2700 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2706 PPCTargetLowering::LowerFormalArguments_Darwin(
2708 CallingConv::ID CallConv, bool isVarArg,
2709 const SmallVectorImpl<ISD::InputArg>
2711 SDLoc dl, SelectionDAG &DAG,
2712 SmallVectorImpl<SDValue> &InVals) const {
2713 // TODO: add description of PPC stack frame format, or at least some docs.
2715 MachineFunction &MF = DAG.getMachineFunction();
2716 MachineFrameInfo *MFI = MF.getFrameInfo();
2717 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2719 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2720 bool isPPC64 = PtrVT == MVT::i64;
2721 // Potential tail calls could cause overwriting of argument stack slots.
2722 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2723 (CallConv == CallingConv::Fast));
2724 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2726 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true);
2727 unsigned ArgOffset = LinkageSize;
2728 // Area that is at least reserved in caller of this function.
2729 unsigned MinReservedArea = ArgOffset;
2731 static const MCPhysReg GPR_32[] = { // 32-bit registers.
2732 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2733 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2735 static const MCPhysReg GPR_64[] = { // 64-bit registers.
2736 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2737 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2740 static const MCPhysReg *FPR = GetFPR();
2742 static const MCPhysReg VR[] = {
2743 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2744 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2747 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2748 const unsigned Num_FPR_Regs = 13;
2749 const unsigned Num_VR_Regs = array_lengthof( VR);
2751 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2753 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
2755 // In 32-bit non-varargs functions, the stack space for vectors is after the
2756 // stack space for non-vectors. We do not use this space unless we have
2757 // too many vectors to fit in registers, something that only occurs in
2758 // constructed examples:), but we have to walk the arglist to figure
2759 // that out...for the pathological case, compute VecArgOffset as the
2760 // start of the vector parameter area. Computing VecArgOffset is the
2761 // entire point of the following loop.
2762 unsigned VecArgOffset = ArgOffset;
2763 if (!isVarArg && !isPPC64) {
2764 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
2766 EVT ObjectVT = Ins[ArgNo].VT;
2767 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2769 if (Flags.isByVal()) {
2770 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
2771 unsigned ObjSize = Flags.getByValSize();
2773 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2774 VecArgOffset += ArgSize;
2778 switch(ObjectVT.getSimpleVT().SimpleTy) {
2779 default: llvm_unreachable("Unhandled argument type!");
2785 case MVT::i64: // PPC64
2787 // FIXME: We are guaranteed to be !isPPC64 at this point.
2788 // Does MVT::i64 apply?
2795 // Nothing to do, we're only looking at Nonvector args here.
2800 // We've found where the vector parameter area in memory is. Skip the
2801 // first 12 parameters; these don't use that memory.
2802 VecArgOffset = ((VecArgOffset+15)/16)*16;
2803 VecArgOffset += 12*16;
2805 // Add DAG nodes to load the arguments or copy them out of registers. On
2806 // entry to a function on PPC, the arguments start after the linkage area,
2807 // although the first ones are often in registers.
2809 SmallVector<SDValue, 8> MemOps;
2810 unsigned nAltivecParamsAtEnd = 0;
2811 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2812 unsigned CurArgIdx = 0;
2813 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2815 bool needsLoad = false;
2816 EVT ObjectVT = Ins[ArgNo].VT;
2817 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2818 unsigned ArgSize = ObjSize;
2819 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2820 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2821 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2823 unsigned CurArgOffset = ArgOffset;
2825 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2826 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2827 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2828 if (isVarArg || isPPC64) {
2829 MinReservedArea = ((MinReservedArea+15)/16)*16;
2830 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2833 } else nAltivecParamsAtEnd++;
2835 // Calculate min reserved area.
2836 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2840 // FIXME the codegen can be much improved in some cases.
2841 // We do not have to keep everything in memory.
2842 if (Flags.isByVal()) {
2843 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2844 ObjSize = Flags.getByValSize();
2845 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2846 // Objects of size 1 and 2 are right justified, everything else is
2847 // left justified. This means the memory address is adjusted forwards.
2848 if (ObjSize==1 || ObjSize==2) {
2849 CurArgOffset = CurArgOffset + (4 - ObjSize);
2851 // The value of the object is its address.
2852 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2853 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2854 InVals.push_back(FIN);
2855 if (ObjSize==1 || ObjSize==2) {
2856 if (GPR_idx != Num_GPR_Regs) {
2859 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2861 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2862 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2863 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
2864 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2865 MachinePointerInfo(FuncArg),
2866 ObjType, false, false, 0);
2867 MemOps.push_back(Store);
2871 ArgOffset += PtrByteSize;
2875 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2876 // Store whatever pieces of the object are in registers
2877 // to memory. ArgOffset will be the address of the beginning
2879 if (GPR_idx != Num_GPR_Regs) {
2882 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2884 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2885 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2886 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2887 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2888 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2889 MachinePointerInfo(FuncArg, j),
2891 MemOps.push_back(Store);
2893 ArgOffset += PtrByteSize;
2895 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
2902 switch (ObjectVT.getSimpleVT().SimpleTy) {
2903 default: llvm_unreachable("Unhandled argument type!");
2907 if (GPR_idx != Num_GPR_Regs) {
2908 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2909 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2911 if (ObjectVT == MVT::i1)
2912 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
2917 ArgSize = PtrByteSize;
2919 // All int arguments reserve stack space in the Darwin ABI.
2920 ArgOffset += PtrByteSize;
2924 case MVT::i64: // PPC64
2925 if (GPR_idx != Num_GPR_Regs) {
2926 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2927 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2929 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
2930 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2931 // value to MVT::i64 and then truncate to the correct register size.
2932 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2937 ArgSize = PtrByteSize;
2939 // All int arguments reserve stack space in the Darwin ABI.
2945 // Every 4 bytes of argument space consumes one of the GPRs available for
2946 // argument passing.
2947 if (GPR_idx != Num_GPR_Regs) {
2949 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
2952 if (FPR_idx != Num_FPR_Regs) {
2955 if (ObjectVT == MVT::f32)
2956 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2958 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2960 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2966 // All FP arguments reserve stack space in the Darwin ABI.
2967 ArgOffset += isPPC64 ? 8 : ObjSize;
2973 // Note that vector arguments in registers don't reserve stack space,
2974 // except in varargs functions.
2975 if (VR_idx != Num_VR_Regs) {
2976 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2977 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2979 while ((ArgOffset % 16) != 0) {
2980 ArgOffset += PtrByteSize;
2981 if (GPR_idx != Num_GPR_Regs)
2985 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2989 if (!isVarArg && !isPPC64) {
2990 // Vectors go after all the nonvectors.
2991 CurArgOffset = VecArgOffset;
2994 // Vectors are aligned.
2995 ArgOffset = ((ArgOffset+15)/16)*16;
2996 CurArgOffset = ArgOffset;
3004 // We need to load the argument to a virtual register if we determined above
3005 // that we ran out of physical registers of the appropriate type.
3007 int FI = MFI->CreateFixedObject(ObjSize,
3008 CurArgOffset + (ArgSize - ObjSize),
3010 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3011 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3012 false, false, false, 0);
3015 InVals.push_back(ArgVal);
3018 // Allow for Altivec parameters at the end, if needed.
3019 if (nAltivecParamsAtEnd) {
3020 MinReservedArea = ((MinReservedArea+15)/16)*16;
3021 MinReservedArea += 16*nAltivecParamsAtEnd;
3024 // Area that is at least reserved in the caller of this function.
3025 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
3027 // Set the size that is at least reserved in caller of this function. Tail
3028 // call optimized functions' reserved stack space needs to be aligned so that
3029 // taking the difference between two stack areas will result in an aligned
3031 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
3032 FuncInfo->setMinReservedArea(MinReservedArea);
3034 // If the function takes variable number of arguments, make a frame index for
3035 // the start of the first vararg value... for expansion of llvm.va_start.
3037 int Depth = ArgOffset;
3039 FuncInfo->setVarArgsFrameIndex(
3040 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3042 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3044 // If this function is vararg, store any remaining integer argument regs
3045 // to their spots on the stack so that they may be loaded by deferencing the
3046 // result of va_next.
3047 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3051 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3053 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3055 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3056 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3057 MachinePointerInfo(), false, false, 0);
3058 MemOps.push_back(Store);
3059 // Increment the address by four for the next argument to store
3060 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
3061 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3065 if (!MemOps.empty())
3066 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3071 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3072 /// adjusted to accommodate the arguments for the tailcall.
3073 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3074 unsigned ParamSize) {
3076 if (!isTailCall) return 0;
3078 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3079 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3080 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3081 // Remember only if the new adjustement is bigger.
3082 if (SPDiff < FI->getTailCallSPDelta())
3083 FI->setTailCallSPDelta(SPDiff);
3088 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3089 /// for tail call optimization. Targets which want to do tail call
3090 /// optimization should implement this function.
3092 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3093 CallingConv::ID CalleeCC,
3095 const SmallVectorImpl<ISD::InputArg> &Ins,
3096 SelectionDAG& DAG) const {
3097 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3100 // Variable argument functions are not supported.
3104 MachineFunction &MF = DAG.getMachineFunction();
3105 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3106 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3107 // Functions containing by val parameters are not supported.
3108 for (unsigned i = 0; i != Ins.size(); i++) {
3109 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3110 if (Flags.isByVal()) return false;
3113 // Non-PIC/GOT tail calls are supported.
3114 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3117 // At the moment we can only do local tail calls (in same module, hidden
3118 // or protected) if we are generating PIC.
3119 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3120 return G->getGlobal()->hasHiddenVisibility()
3121 || G->getGlobal()->hasProtectedVisibility();
3127 /// isCallCompatibleAddress - Return the immediate to use if the specified
3128 /// 32-bit value is representable in the immediate field of a BxA instruction.
3129 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3130 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3131 if (!C) return nullptr;
3133 int Addr = C->getZExtValue();
3134 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3135 SignExtend32<26>(Addr) != Addr)
3136 return nullptr; // Top 6 bits have to be sext of immediate.
3138 return DAG.getConstant((int)C->getZExtValue() >> 2,
3139 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
3144 struct TailCallArgumentInfo {
3149 TailCallArgumentInfo() : FrameIdx(0) {}
3154 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3156 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3158 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3159 SmallVectorImpl<SDValue> &MemOpChains,
3161 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3162 SDValue Arg = TailCallArgs[i].Arg;
3163 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3164 int FI = TailCallArgs[i].FrameIdx;
3165 // Store relative to framepointer.
3166 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
3167 MachinePointerInfo::getFixedStack(FI),
3172 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3173 /// the appropriate stack slot for the tail call optimized function call.
3174 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3175 MachineFunction &MF,
3184 // Calculate the new stack slot for the return address.
3185 int SlotSize = isPPC64 ? 8 : 4;
3186 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
3188 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3189 NewRetAddrLoc, true);
3190 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3191 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3192 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3193 MachinePointerInfo::getFixedStack(NewRetAddr),
3196 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3197 // slot as the FP is never overwritten.
3200 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
3201 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3203 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3204 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3205 MachinePointerInfo::getFixedStack(NewFPIdx),
3212 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3213 /// the position of the argument.
3215 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3216 SDValue Arg, int SPDiff, unsigned ArgOffset,
3217 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3218 int Offset = ArgOffset + SPDiff;
3219 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3220 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3221 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3222 SDValue FIN = DAG.getFrameIndex(FI, VT);
3223 TailCallArgumentInfo Info;
3225 Info.FrameIdxOp = FIN;
3227 TailCallArguments.push_back(Info);
3230 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3231 /// stack slot. Returns the chain as result and the loaded frame pointers in
3232 /// LROpOut/FPOpout. Used when tail calling.
3233 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3241 // Load the LR and FP stack slot for later adjusting.
3242 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
3243 LROpOut = getReturnAddrFrameIndex(DAG);
3244 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3245 false, false, false, 0);
3246 Chain = SDValue(LROpOut.getNode(), 1);
3248 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3249 // slot as the FP is never overwritten.
3251 FPOpOut = getFramePointerFrameIndex(DAG);
3252 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3253 false, false, false, 0);
3254 Chain = SDValue(FPOpOut.getNode(), 1);
3260 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3261 /// by "Src" to address "Dst" of size "Size". Alignment information is
3262 /// specified by the specific parameter attribute. The copy will be passed as
3263 /// a byval function parameter.
3264 /// Sometimes what we are copying is the end of a larger object, the part that
3265 /// does not fit in registers.
3267 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3268 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3270 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3271 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3272 false, false, MachinePointerInfo(),
3273 MachinePointerInfo());
3276 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3279 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3280 SDValue Arg, SDValue PtrOff, int SPDiff,
3281 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3282 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
3283 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
3285 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3290 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3292 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3293 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3294 DAG.getConstant(ArgOffset, PtrVT));
3296 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3297 MachinePointerInfo(), false, false, 0));
3298 // Calculate and remember argument location.
3299 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3304 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3305 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3306 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3307 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
3308 MachineFunction &MF = DAG.getMachineFunction();
3310 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3311 // might overwrite each other in case of tail call optimization.
3312 SmallVector<SDValue, 8> MemOpChains2;
3313 // Do not flag preceding copytoreg stuff together with the following stuff.
3315 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3317 if (!MemOpChains2.empty())
3318 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3320 // Store the return address to the appropriate stack slot.
3321 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3322 isPPC64, isDarwinABI, dl);
3324 // Emit callseq_end just before tailcall node.
3325 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3326 DAG.getIntPtrConstant(0, true), InFlag, dl);
3327 InFlag = Chain.getValue(1);
3331 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3332 SDValue &Chain, SDLoc dl, int SPDiff, bool isTailCall,
3333 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
3334 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
3335 const PPCSubtarget &Subtarget) {
3337 bool isPPC64 = Subtarget.isPPC64();
3338 bool isSVR4ABI = Subtarget.isSVR4ABI();
3340 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3341 NodeTys.push_back(MVT::Other); // Returns a chain
3342 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3344 unsigned CallOpc = PPCISD::CALL;
3346 bool needIndirectCall = true;
3347 if (!isSVR4ABI || !isPPC64)
3348 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3349 // If this is an absolute destination address, use the munged value.
3350 Callee = SDValue(Dest, 0);
3351 needIndirectCall = false;
3354 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3355 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201
3356 // Use indirect calls for ALL functions calls in JIT mode, since the
3357 // far-call stubs may be outside relocation limits for a BL instruction.
3358 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
3359 unsigned OpFlags = 0;
3360 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3361 (Subtarget.getTargetTriple().isMacOSX() &&
3362 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3363 (G->getGlobal()->isDeclaration() ||
3364 G->getGlobal()->isWeakForLinker())) {
3365 // PC-relative references to external symbols should go through $stub,
3366 // unless we're building with the leopard linker or later, which
3367 // automatically synthesizes these stubs.
3368 OpFlags = PPCII::MO_DARWIN_STUB;
3371 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3372 // every direct call is) turn it into a TargetGlobalAddress /
3373 // TargetExternalSymbol node so that legalize doesn't hack it.
3374 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3375 Callee.getValueType(),
3377 needIndirectCall = false;
3381 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3382 unsigned char OpFlags = 0;
3384 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3385 (Subtarget.getTargetTriple().isMacOSX() &&
3386 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) {
3387 // PC-relative references to external symbols should go through $stub,
3388 // unless we're building with the leopard linker or later, which
3389 // automatically synthesizes these stubs.
3390 OpFlags = PPCII::MO_DARWIN_STUB;
3393 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3395 needIndirectCall = false;
3398 if (needIndirectCall) {
3399 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3400 // to do the call, we can't use PPCISD::CALL.
3401 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3403 if (isSVR4ABI && isPPC64) {
3404 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3405 // entry point, but to the function descriptor (the function entry point
3406 // address is part of the function descriptor though).
3407 // The function descriptor is a three doubleword structure with the
3408 // following fields: function entry point, TOC base address and
3409 // environment pointer.
3410 // Thus for a call through a function pointer, the following actions need
3412 // 1. Save the TOC of the caller in the TOC save area of its stack
3413 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3414 // 2. Load the address of the function entry point from the function
3416 // 3. Load the TOC of the callee from the function descriptor into r2.
3417 // 4. Load the environment pointer from the function descriptor into
3419 // 5. Branch to the function entry point address.
3420 // 6. On return of the callee, the TOC of the caller needs to be
3421 // restored (this is done in FinishCall()).
3423 // All those operations are flagged together to ensure that no other
3424 // operations can be scheduled in between. E.g. without flagging the
3425 // operations together, a TOC access in the caller could be scheduled
3426 // between the load of the callee TOC and the branch to the callee, which
3427 // results in the TOC access going through the TOC of the callee instead
3428 // of going through the TOC of the caller, which leads to incorrect code.
3430 // Load the address of the function entry point from the function
3432 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3433 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs,
3434 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3435 Chain = LoadFuncPtr.getValue(1);
3436 InFlag = LoadFuncPtr.getValue(2);
3438 // Load environment pointer into r11.
3439 // Offset of the environment pointer within the function descriptor.
3440 SDValue PtrOff = DAG.getIntPtrConstant(16);
3442 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3443 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
3445 Chain = LoadEnvPtr.getValue(1);
3446 InFlag = LoadEnvPtr.getValue(2);
3448 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3450 Chain = EnvVal.getValue(0);
3451 InFlag = EnvVal.getValue(1);
3453 // Load TOC of the callee into r2. We are using a target-specific load
3454 // with r2 hard coded, because the result of a target-independent load
3455 // would never go directly into r2, since r2 is a reserved register (which
3456 // prevents the register allocator from allocating it), resulting in an
3457 // additional register being allocated and an unnecessary move instruction
3459 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3460 SDValue TOCOff = DAG.getIntPtrConstant(8);
3461 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
3462 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
3464 Chain = LoadTOCPtr.getValue(0);
3465 InFlag = LoadTOCPtr.getValue(1);
3467 MTCTROps[0] = Chain;
3468 MTCTROps[1] = LoadFuncPtr;
3469 MTCTROps[2] = InFlag;
3472 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
3473 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3474 InFlag = Chain.getValue(1);
3477 NodeTys.push_back(MVT::Other);
3478 NodeTys.push_back(MVT::Glue);
3479 Ops.push_back(Chain);
3480 CallOpc = PPCISD::BCTRL;
3481 Callee.setNode(nullptr);
3482 // Add use of X11 (holding environment pointer)
3483 if (isSVR4ABI && isPPC64)
3484 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3485 // Add CTR register as callee so a bctr can be emitted later.
3487 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3490 // If this is a direct call, pass the chain and the callee.
3491 if (Callee.getNode()) {
3492 Ops.push_back(Chain);
3493 Ops.push_back(Callee);
3495 // If this is a tail call add stack pointer delta.
3497 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3499 // Add argument registers to the end of the list so that they are known live
3501 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3502 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3503 RegsToPass[i].second.getValueType()));
3509 bool isLocalCall(const SDValue &Callee)
3511 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3512 return !G->getGlobal()->isDeclaration() &&
3513 !G->getGlobal()->isWeakForLinker();
3518 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3519 CallingConv::ID CallConv, bool isVarArg,
3520 const SmallVectorImpl<ISD::InputArg> &Ins,
3521 SDLoc dl, SelectionDAG &DAG,
3522 SmallVectorImpl<SDValue> &InVals) const {
3524 SmallVector<CCValAssign, 16> RVLocs;
3525 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3526 getTargetMachine(), RVLocs, *DAG.getContext());
3527 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3529 // Copy all of the result registers out of their specified physreg.
3530 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3531 CCValAssign &VA = RVLocs[i];
3532 assert(VA.isRegLoc() && "Can only return in registers!");
3534 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3535 VA.getLocReg(), VA.getLocVT(), InFlag);
3536 Chain = Val.getValue(1);
3537 InFlag = Val.getValue(2);
3539 switch (VA.getLocInfo()) {
3540 default: llvm_unreachable("Unknown loc info!");
3541 case CCValAssign::Full: break;
3542 case CCValAssign::AExt:
3543 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3545 case CCValAssign::ZExt:
3546 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3547 DAG.getValueType(VA.getValVT()));
3548 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3550 case CCValAssign::SExt:
3551 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3552 DAG.getValueType(VA.getValVT()));
3553 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3557 InVals.push_back(Val);
3564 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
3565 bool isTailCall, bool isVarArg,
3567 SmallVector<std::pair<unsigned, SDValue>, 8>
3569 SDValue InFlag, SDValue Chain,
3571 int SPDiff, unsigned NumBytes,
3572 const SmallVectorImpl<ISD::InputArg> &Ins,
3573 SmallVectorImpl<SDValue> &InVals) const {
3574 std::vector<EVT> NodeTys;
3575 SmallVector<SDValue, 8> Ops;
3576 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
3577 isTailCall, RegsToPass, Ops, NodeTys,
3580 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3581 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
3582 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3584 // When performing tail call optimization the callee pops its arguments off
3585 // the stack. Account for this here so these bytes can be pushed back on in
3586 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3587 int BytesCalleePops =
3588 (CallConv == CallingConv::Fast &&
3589 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3591 // Add a register mask operand representing the call-preserved registers.
3592 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
3593 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3594 assert(Mask && "Missing call preserved mask for calling convention");
3595 Ops.push_back(DAG.getRegisterMask(Mask));
3597 if (InFlag.getNode())
3598 Ops.push_back(InFlag);
3602 assert(((Callee.getOpcode() == ISD::Register &&
3603 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3604 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3605 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3606 isa<ConstantSDNode>(Callee)) &&
3607 "Expecting an global address, external symbol, absolute value or register");
3609 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
3612 // Add a NOP immediately after the branch instruction when using the 64-bit
3613 // SVR4 ABI. At link time, if caller and callee are in a different module and
3614 // thus have a different TOC, the call will be replaced with a call to a stub
3615 // function which saves the current TOC, loads the TOC of the callee and
3616 // branches to the callee. The NOP will be replaced with a load instruction
3617 // which restores the TOC of the caller from the TOC save slot of the current
3618 // stack frame. If caller and callee belong to the same module (and have the
3619 // same TOC), the NOP will remain unchanged.
3621 bool needsTOCRestore = false;
3622 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64()) {
3623 if (CallOpc == PPCISD::BCTRL) {
3624 // This is a call through a function pointer.
3625 // Restore the caller TOC from the save area into R2.
3626 // See PrepareCall() for more information about calls through function
3627 // pointers in the 64-bit SVR4 ABI.
3628 // We are using a target-specific load with r2 hard coded, because the
3629 // result of a target-independent load would never go directly into r2,
3630 // since r2 is a reserved register (which prevents the register allocator
3631 // from allocating it), resulting in an additional register being
3632 // allocated and an unnecessary move instruction being generated.
3633 needsTOCRestore = true;
3634 } else if ((CallOpc == PPCISD::CALL) &&
3635 (!isLocalCall(Callee) ||
3636 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3637 // Otherwise insert NOP for non-local calls.
3638 CallOpc = PPCISD::CALL_NOP;
3642 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
3643 InFlag = Chain.getValue(1);
3645 if (needsTOCRestore) {
3646 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3647 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3648 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
3649 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset();
3650 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset);
3651 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
3652 Chain = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain, AddTOC, InFlag);
3653 InFlag = Chain.getValue(1);
3656 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3657 DAG.getIntPtrConstant(BytesCalleePops, true),
3660 InFlag = Chain.getValue(1);
3662 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3663 Ins, dl, DAG, InVals);
3667 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3668 SmallVectorImpl<SDValue> &InVals) const {
3669 SelectionDAG &DAG = CLI.DAG;
3671 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3672 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3673 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3674 SDValue Chain = CLI.Chain;
3675 SDValue Callee = CLI.Callee;
3676 bool &isTailCall = CLI.IsTailCall;
3677 CallingConv::ID CallConv = CLI.CallConv;
3678 bool isVarArg = CLI.IsVarArg;
3681 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3684 if (!isTailCall && CLI.CS && CLI.CS->isMustTailCall())
3685 report_fatal_error("failed to perform tail call elimination on a call "
3686 "site marked musttail");
3688 if (Subtarget.isSVR4ABI()) {
3689 if (Subtarget.isPPC64())
3690 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3691 isTailCall, Outs, OutVals, Ins,
3694 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3695 isTailCall, Outs, OutVals, Ins,
3699 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
3700 isTailCall, Outs, OutVals, Ins,
3705 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
3706 CallingConv::ID CallConv, bool isVarArg,
3708 const SmallVectorImpl<ISD::OutputArg> &Outs,
3709 const SmallVectorImpl<SDValue> &OutVals,
3710 const SmallVectorImpl<ISD::InputArg> &Ins,
3711 SDLoc dl, SelectionDAG &DAG,
3712 SmallVectorImpl<SDValue> &InVals) const {
3713 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
3714 // of the 32-bit SVR4 ABI stack frame layout.
3716 assert((CallConv == CallingConv::C ||
3717 CallConv == CallingConv::Fast) && "Unknown calling convention!");
3719 unsigned PtrByteSize = 4;
3721 MachineFunction &MF = DAG.getMachineFunction();
3723 // Mark this function as potentially containing a function that contains a
3724 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3725 // and restoring the callers stack pointer in this functions epilog. This is
3726 // done because by tail calling the called function might overwrite the value
3727 // in this function's (MF) stack pointer stack slot 0(SP).
3728 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3729 CallConv == CallingConv::Fast)
3730 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3732 // Count how many bytes are to be pushed on the stack, including the linkage
3733 // area, parameter list area and the part of the local variable space which
3734 // contains copies of aggregates which are passed by value.
3736 // Assign locations to all of the outgoing arguments.
3737 SmallVector<CCValAssign, 16> ArgLocs;
3738 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3739 getTargetMachine(), ArgLocs, *DAG.getContext());
3741 // Reserve space for the linkage area on the stack.
3742 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
3745 // Handle fixed and variable vector arguments differently.
3746 // Fixed vector arguments go into registers as long as registers are
3747 // available. Variable vector arguments always go into memory.
3748 unsigned NumArgs = Outs.size();
3750 for (unsigned i = 0; i != NumArgs; ++i) {
3751 MVT ArgVT = Outs[i].VT;
3752 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3755 if (Outs[i].IsFixed) {
3756 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
3759 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
3765 errs() << "Call operand #" << i << " has unhandled type "
3766 << EVT(ArgVT).getEVTString() << "\n";
3768 llvm_unreachable(nullptr);
3772 // All arguments are treated the same.
3773 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
3776 // Assign locations to all of the outgoing aggregate by value arguments.
3777 SmallVector<CCValAssign, 16> ByValArgLocs;
3778 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3779 getTargetMachine(), ByValArgLocs, *DAG.getContext());
3781 // Reserve stack space for the allocations in CCInfo.
3782 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
3784 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
3786 // Size of the linkage area, parameter list area and the part of the local
3787 // space variable where copies of aggregates which are passed by value are
3789 unsigned NumBytes = CCByValInfo.getNextStackOffset();
3791 // Calculate by how many bytes the stack has to be adjusted in case of tail
3792 // call optimization.
3793 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3795 // Adjust the stack pointer for the new arguments...
3796 // These operations are automatically eliminated by the prolog/epilog pass
3797 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
3799 SDValue CallSeqStart = Chain;
3801 // Load the return address and frame pointer so it can be moved somewhere else
3804 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
3807 // Set up a copy of the stack pointer for use loading and storing any
3808 // arguments that may not fit in the registers available for argument
3810 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3812 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3813 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3814 SmallVector<SDValue, 8> MemOpChains;
3816 bool seenFloatArg = false;
3817 // Walk the register/memloc assignments, inserting copies/loads.
3818 for (unsigned i = 0, j = 0, e = ArgLocs.size();
3821 CCValAssign &VA = ArgLocs[i];
3822 SDValue Arg = OutVals[i];
3823 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3825 if (Flags.isByVal()) {
3826 // Argument is an aggregate which is passed by value, thus we need to
3827 // create a copy of it in the local variable space of the current stack
3828 // frame (which is the stack frame of the caller) and pass the address of
3829 // this copy to the callee.
3830 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
3831 CCValAssign &ByValVA = ByValArgLocs[j++];
3832 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
3834 // Memory reserved in the local variable space of the callers stack frame.
3835 unsigned LocMemOffset = ByValVA.getLocMemOffset();
3837 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3838 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3840 // Create a copy of the argument in the local area of the current
3842 SDValue MemcpyCall =
3843 CreateCopyOfByValArgument(Arg, PtrOff,
3844 CallSeqStart.getNode()->getOperand(0),
3847 // This must go outside the CALLSEQ_START..END.
3848 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3849 CallSeqStart.getNode()->getOperand(1),
3851 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3852 NewCallSeqStart.getNode());
3853 Chain = CallSeqStart = NewCallSeqStart;
3855 // Pass the address of the aggregate copy on the stack either in a
3856 // physical register or in the parameter list area of the current stack
3857 // frame to the callee.
3861 if (VA.isRegLoc()) {
3862 if (Arg.getValueType() == MVT::i1)
3863 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
3865 seenFloatArg |= VA.getLocVT().isFloatingPoint();
3866 // Put argument in a physical register.
3867 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3869 // Put argument in the parameter list area of the current stack frame.
3870 assert(VA.isMemLoc());
3871 unsigned LocMemOffset = VA.getLocMemOffset();
3874 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3875 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3877 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3878 MachinePointerInfo(),
3881 // Calculate and remember argument location.
3882 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
3888 if (!MemOpChains.empty())
3889 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3891 // Build a sequence of copy-to-reg nodes chained together with token chain
3892 // and flag operands which copy the outgoing args into the appropriate regs.
3894 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3895 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3896 RegsToPass[i].second, InFlag);
3897 InFlag = Chain.getValue(1);
3900 // Set CR bit 6 to true if this is a vararg call with floating args passed in
3903 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3904 SDValue Ops[] = { Chain, InFlag };
3906 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
3907 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
3909 InFlag = Chain.getValue(1);
3913 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
3914 false, TailCallArguments);
3916 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3917 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3921 // Copy an argument into memory, being careful to do this outside the
3922 // call sequence for the call to which the argument belongs.
3924 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
3925 SDValue CallSeqStart,
3926 ISD::ArgFlagsTy Flags,
3929 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
3930 CallSeqStart.getNode()->getOperand(0),
3932 // The MEMCPY must go outside the CALLSEQ_START..END.
3933 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3934 CallSeqStart.getNode()->getOperand(1),
3936 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3937 NewCallSeqStart.getNode());
3938 return NewCallSeqStart;
3942 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
3943 CallingConv::ID CallConv, bool isVarArg,
3945 const SmallVectorImpl<ISD::OutputArg> &Outs,
3946 const SmallVectorImpl<SDValue> &OutVals,
3947 const SmallVectorImpl<ISD::InputArg> &Ins,
3948 SDLoc dl, SelectionDAG &DAG,
3949 SmallVectorImpl<SDValue> &InVals) const {
3951 bool isLittleEndian = Subtarget.isLittleEndian();
3952 unsigned NumOps = Outs.size();
3954 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3955 unsigned PtrByteSize = 8;
3957 MachineFunction &MF = DAG.getMachineFunction();
3959 // Mark this function as potentially containing a function that contains a
3960 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3961 // and restoring the callers stack pointer in this functions epilog. This is
3962 // done because by tail calling the called function might overwrite the value
3963 // in this function's (MF) stack pointer stack slot 0(SP).
3964 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3965 CallConv == CallingConv::Fast)
3966 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3968 // Count how many bytes are to be pushed on the stack, including the linkage
3969 // area, and parameter passing area. We start with at least 48 bytes, which
3970 // is reserved space for [SP][CR][LR][3 x unused].
3971 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false);
3972 unsigned NumBytes = LinkageSize;
3974 // Add up all the space actually used.
3975 for (unsigned i = 0; i != NumOps; ++i) {
3976 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3977 EVT ArgVT = Outs[i].VT;
3979 /* Respect alignment of argument on the stack. */
3980 unsigned Align = CalculateStackSlotAlignment(ArgVT, Flags, PtrByteSize);
3981 NumBytes = ((NumBytes + Align - 1) / Align) * Align;
3983 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
3986 unsigned NumBytesActuallyUsed = NumBytes;
3988 // The prolog code of the callee may store up to 8 GPR argument registers to
3989 // the stack, allowing va_start to index over them in memory if its varargs.
3990 // Because we cannot tell if this is needed on the caller side, we have to
3991 // conservatively assume that it is needed. As such, make sure we have at
3992 // least enough stack space for the caller to store the 8 GPRs.
3993 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
3995 // Tail call needs the stack to be aligned.
3996 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3997 CallConv == CallingConv::Fast)
3998 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
4000 // Calculate by how many bytes the stack has to be adjusted in case of tail
4001 // call optimization.
4002 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4004 // To protect arguments on the stack from being clobbered in a tail call,
4005 // force all the loads to happen before doing any other lowering.
4007 Chain = DAG.getStackArgumentTokenFactor(Chain);
4009 // Adjust the stack pointer for the new arguments...
4010 // These operations are automatically eliminated by the prolog/epilog pass
4011 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4013 SDValue CallSeqStart = Chain;
4015 // Load the return address and frame pointer so it can be move somewhere else
4018 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4021 // Set up a copy of the stack pointer for use loading and storing any
4022 // arguments that may not fit in the registers available for argument
4024 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4026 // Figure out which arguments are going to go in registers, and which in
4027 // memory. Also, if this is a vararg function, floating point operations
4028 // must be stored to our stack, and loaded into integer regs as well, if
4029 // any integer regs are available for argument passing.
4030 unsigned ArgOffset = LinkageSize;
4031 unsigned GPR_idx, FPR_idx = 0, VR_idx = 0;
4033 static const MCPhysReg GPR[] = {
4034 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4035 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4037 static const MCPhysReg *FPR = GetFPR();
4039 static const MCPhysReg VR[] = {
4040 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4041 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4043 static const MCPhysReg VSRH[] = {
4044 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4045 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4048 const unsigned NumGPRs = array_lengthof(GPR);
4049 const unsigned NumFPRs = 13;
4050 const unsigned NumVRs = array_lengthof(VR);
4052 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4053 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4055 SmallVector<SDValue, 8> MemOpChains;
4056 for (unsigned i = 0; i != NumOps; ++i) {
4057 SDValue Arg = OutVals[i];
4058 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4060 /* Respect alignment of argument on the stack. */
4062 CalculateStackSlotAlignment(Outs[i].VT, Flags, PtrByteSize);
4063 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
4065 /* Compute GPR index associated with argument offset. */
4066 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4067 GPR_idx = std::min(GPR_idx, NumGPRs);
4069 // PtrOff will be used to store the current argument to the stack if a
4070 // register cannot be found for it.
4073 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4075 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4077 // Promote integers to 64-bit values.
4078 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4079 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4080 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4081 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4084 // FIXME memcpy is used way more than necessary. Correctness first.
4085 // Note: "by value" is code for passing a structure by value, not
4087 if (Flags.isByVal()) {
4088 // Note: Size includes alignment padding, so
4089 // struct x { short a; char b; }
4090 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4091 // These are the proper values we need for right-justifying the
4092 // aggregate in a parameter register.
4093 unsigned Size = Flags.getByValSize();
4095 // An empty aggregate parameter takes up no storage and no
4100 // All aggregates smaller than 8 bytes must be passed right-justified.
4101 if (Size==1 || Size==2 || Size==4) {
4102 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4103 if (GPR_idx != NumGPRs) {
4104 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4105 MachinePointerInfo(), VT,
4107 MemOpChains.push_back(Load.getValue(1));
4108 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Load));
4110 ArgOffset += PtrByteSize;
4115 if (GPR_idx == NumGPRs && Size < 8) {
4116 SDValue AddPtr = PtrOff;
4117 if (!isLittleEndian) {
4118 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4119 PtrOff.getValueType());
4120 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4122 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4125 ArgOffset += PtrByteSize;
4128 // Copy entire object into memory. There are cases where gcc-generated
4129 // code assumes it is there, even if it could be put entirely into
4130 // registers. (This is not what the doc says.)
4132 // FIXME: The above statement is likely due to a misunderstanding of the
4133 // documents. All arguments must be copied into the parameter area BY
4134 // THE CALLEE in the event that the callee takes the address of any
4135 // formal argument. That has not yet been implemented. However, it is
4136 // reasonable to use the stack area as a staging area for the register
4139 // Skip this for small aggregates, as we will use the same slot for a
4140 // right-justified copy, below.
4142 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4146 // When a register is available, pass a small aggregate right-justified.
4147 if (Size < 8 && GPR_idx != NumGPRs) {
4148 // The easiest way to get this right-justified in a register
4149 // is to copy the structure into the rightmost portion of a
4150 // local variable slot, then load the whole slot into the
4152 // FIXME: The memcpy seems to produce pretty awful code for
4153 // small aggregates, particularly for packed ones.
4154 // FIXME: It would be preferable to use the slot in the
4155 // parameter save area instead of a new local variable.
4156 SDValue AddPtr = PtrOff;
4157 if (!isLittleEndian) {
4158 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
4159 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4161 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4165 // Load the slot into the register.
4166 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
4167 MachinePointerInfo(),
4168 false, false, false, 0);
4169 MemOpChains.push_back(Load.getValue(1));
4170 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Load));
4172 // Done with this argument.
4173 ArgOffset += PtrByteSize;
4177 // For aggregates larger than PtrByteSize, copy the pieces of the
4178 // object that fit into registers from the parameter save area.
4179 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4180 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4181 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4182 if (GPR_idx != NumGPRs) {
4183 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4184 MachinePointerInfo(),
4185 false, false, false, 0);
4186 MemOpChains.push_back(Load.getValue(1));
4187 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4188 ArgOffset += PtrByteSize;
4190 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4197 switch (Arg.getSimpleValueType().SimpleTy) {
4198 default: llvm_unreachable("Unexpected ValueType for argument!");
4202 if (GPR_idx != NumGPRs) {
4203 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Arg));
4205 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4206 true, isTailCall, false, MemOpChains,
4207 TailCallArguments, dl);
4209 ArgOffset += PtrByteSize;
4213 if (FPR_idx != NumFPRs) {
4214 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4217 // A single float or an aggregate containing only a single float
4218 // must be passed right-justified in the stack doubleword, and
4219 // in the GPR, if one is available.
4221 if (Arg.getSimpleValueType().SimpleTy == MVT::f32 &&
4223 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4224 StoreOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4228 SDValue Store = DAG.getStore(Chain, dl, Arg, StoreOff,
4229 MachinePointerInfo(), false, false, 0);
4230 MemOpChains.push_back(Store);
4232 // Float varargs are always shadowed in available integer registers
4233 if (GPR_idx != NumGPRs) {
4234 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4235 MachinePointerInfo(), false, false,
4237 MemOpChains.push_back(Load.getValue(1));
4238 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Load));
4242 // Single-precision floating-point values are mapped to the
4243 // second (rightmost) word of the stack doubleword.
4244 if (Arg.getValueType() == MVT::f32 && !isLittleEndian) {
4245 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4246 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4249 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4250 true, isTailCall, false, MemOpChains,
4251 TailCallArguments, dl);
4261 // For a varargs call, named arguments go into VRs or on the stack as
4262 // usual; unnamed arguments always go to the stack or the corresponding
4263 // GPRs when within range. For now, we always put the value in both
4264 // locations (or even all three).
4266 // We could elide this store in the case where the object fits
4267 // entirely in R registers. Maybe later.
4268 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4269 MachinePointerInfo(), false, false, 0);
4270 MemOpChains.push_back(Store);
4271 if (VR_idx != NumVRs) {
4272 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4273 MachinePointerInfo(),
4274 false, false, false, 0);
4275 MemOpChains.push_back(Load.getValue(1));
4277 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4278 Arg.getSimpleValueType() == MVT::v2i64) ?
4279 VSRH[VR_idx] : VR[VR_idx];
4282 RegsToPass.push_back(std::make_pair(VReg, Load));
4285 for (unsigned i=0; i<16; i+=PtrByteSize) {
4286 if (GPR_idx == NumGPRs)
4288 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4289 DAG.getConstant(i, PtrVT));
4290 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4291 false, false, false, 0);
4292 MemOpChains.push_back(Load.getValue(1));
4293 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4298 // Non-varargs Altivec params go into VRs or on the stack.
4299 if (VR_idx != NumVRs) {
4300 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4301 Arg.getSimpleValueType() == MVT::v2i64) ?
4302 VSRH[VR_idx] : VR[VR_idx];
4305 RegsToPass.push_back(std::make_pair(VReg, Arg));
4307 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4308 true, isTailCall, true, MemOpChains,
4309 TailCallArguments, dl);
4316 assert(NumBytesActuallyUsed == ArgOffset);
4318 if (!MemOpChains.empty())
4319 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4321 // Check if this is an indirect call (MTCTR/BCTRL).
4322 // See PrepareCall() for more information about calls through function
4323 // pointers in the 64-bit SVR4 ABI.
4325 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4326 !dyn_cast<ExternalSymbolSDNode>(Callee)) {
4327 // Load r2 into a virtual register and store it to the TOC save area.
4328 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4329 // TOC save area offset.
4330 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset();
4331 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset);
4332 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4333 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
4337 // Build a sequence of copy-to-reg nodes chained together with token chain
4338 // and flag operands which copy the outgoing args into the appropriate regs.
4340 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4341 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4342 RegsToPass[i].second, InFlag);
4343 InFlag = Chain.getValue(1);
4347 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4348 FPOp, true, TailCallArguments);
4350 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4351 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4356 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4357 CallingConv::ID CallConv, bool isVarArg,
4359 const SmallVectorImpl<ISD::OutputArg> &Outs,
4360 const SmallVectorImpl<SDValue> &OutVals,
4361 const SmallVectorImpl<ISD::InputArg> &Ins,
4362 SDLoc dl, SelectionDAG &DAG,
4363 SmallVectorImpl<SDValue> &InVals) const {
4365 unsigned NumOps = Outs.size();
4367 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4368 bool isPPC64 = PtrVT == MVT::i64;
4369 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4371 MachineFunction &MF = DAG.getMachineFunction();
4373 // Mark this function as potentially containing a function that contains a
4374 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4375 // and restoring the callers stack pointer in this functions epilog. This is
4376 // done because by tail calling the called function might overwrite the value
4377 // in this function's (MF) stack pointer stack slot 0(SP).
4378 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4379 CallConv == CallingConv::Fast)
4380 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4382 // Count how many bytes are to be pushed on the stack, including the linkage
4383 // area, and parameter passing area. We start with 24/48 bytes, which is
4384 // prereserved space for [SP][CR][LR][3 x unused].
4385 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true);
4386 unsigned NumBytes = LinkageSize;
4388 // Add up all the space actually used.
4389 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
4390 // they all go in registers, but we must reserve stack space for them for
4391 // possible use by the caller. In varargs or 64-bit calls, parameters are
4392 // assigned stack space in order, with padding so Altivec parameters are
4394 unsigned nAltivecParamsAtEnd = 0;
4395 for (unsigned i = 0; i != NumOps; ++i) {
4396 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4397 EVT ArgVT = Outs[i].VT;
4398 // Varargs Altivec parameters are padded to a 16 byte boundary.
4399 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
4400 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
4401 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) {
4402 if (!isVarArg && !isPPC64) {
4403 // Non-varargs Altivec parameters go after all the non-Altivec
4404 // parameters; handle those later so we know how much padding we need.
4405 nAltivecParamsAtEnd++;
4408 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
4409 NumBytes = ((NumBytes+15)/16)*16;
4411 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4414 // Allow for Altivec parameters at the end, if needed.
4415 if (nAltivecParamsAtEnd) {
4416 NumBytes = ((NumBytes+15)/16)*16;
4417 NumBytes += 16*nAltivecParamsAtEnd;
4420 // The prolog code of the callee may store up to 8 GPR argument registers to
4421 // the stack, allowing va_start to index over them in memory if its varargs.
4422 // Because we cannot tell if this is needed on the caller side, we have to
4423 // conservatively assume that it is needed. As such, make sure we have at
4424 // least enough stack space for the caller to store the 8 GPRs.
4425 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4427 // Tail call needs the stack to be aligned.
4428 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4429 CallConv == CallingConv::Fast)
4430 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
4432 // Calculate by how many bytes the stack has to be adjusted in case of tail
4433 // call optimization.
4434 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4436 // To protect arguments on the stack from being clobbered in a tail call,
4437 // force all the loads to happen before doing any other lowering.
4439 Chain = DAG.getStackArgumentTokenFactor(Chain);
4441 // Adjust the stack pointer for the new arguments...
4442 // These operations are automatically eliminated by the prolog/epilog pass
4443 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4445 SDValue CallSeqStart = Chain;
4447 // Load the return address and frame pointer so it can be move somewhere else
4450 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4453 // Set up a copy of the stack pointer for use loading and storing any
4454 // arguments that may not fit in the registers available for argument
4458 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4460 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4462 // Figure out which arguments are going to go in registers, and which in
4463 // memory. Also, if this is a vararg function, floating point operations
4464 // must be stored to our stack, and loaded into integer regs as well, if
4465 // any integer regs are available for argument passing.
4466 unsigned ArgOffset = LinkageSize;
4467 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4469 static const MCPhysReg GPR_32[] = { // 32-bit registers.
4470 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4471 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4473 static const MCPhysReg GPR_64[] = { // 64-bit registers.
4474 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4475 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4477 static const MCPhysReg *FPR = GetFPR();
4479 static const MCPhysReg VR[] = {
4480 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4481 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4483 const unsigned NumGPRs = array_lengthof(GPR_32);
4484 const unsigned NumFPRs = 13;
4485 const unsigned NumVRs = array_lengthof(VR);
4487 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
4489 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4490 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4492 SmallVector<SDValue, 8> MemOpChains;
4493 for (unsigned i = 0; i != NumOps; ++i) {
4494 SDValue Arg = OutVals[i];
4495 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4497 // PtrOff will be used to store the current argument to the stack if a
4498 // register cannot be found for it.
4501 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4503 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4505 // On PPC64, promote integers to 64-bit values.
4506 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4507 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4508 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4509 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4512 // FIXME memcpy is used way more than necessary. Correctness first.
4513 // Note: "by value" is code for passing a structure by value, not
4515 if (Flags.isByVal()) {
4516 unsigned Size = Flags.getByValSize();
4517 // Very small objects are passed right-justified. Everything else is
4518 // passed left-justified.
4519 if (Size==1 || Size==2) {
4520 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4521 if (GPR_idx != NumGPRs) {
4522 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4523 MachinePointerInfo(), VT,
4525 MemOpChains.push_back(Load.getValue(1));
4526 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4528 ArgOffset += PtrByteSize;
4530 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4531 PtrOff.getValueType());
4532 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4533 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4536 ArgOffset += PtrByteSize;
4540 // Copy entire object into memory. There are cases where gcc-generated
4541 // code assumes it is there, even if it could be put entirely into
4542 // registers. (This is not what the doc says.)
4543 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4547 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4548 // copy the pieces of the object that fit into registers from the
4549 // parameter save area.
4550 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4551 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4552 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4553 if (GPR_idx != NumGPRs) {
4554 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4555 MachinePointerInfo(),
4556 false, false, false, 0);
4557 MemOpChains.push_back(Load.getValue(1));
4558 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4559 ArgOffset += PtrByteSize;
4561 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4568 switch (Arg.getSimpleValueType().SimpleTy) {
4569 default: llvm_unreachable("Unexpected ValueType for argument!");
4573 if (GPR_idx != NumGPRs) {
4574 if (Arg.getValueType() == MVT::i1)
4575 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
4577 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4579 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4580 isPPC64, isTailCall, false, MemOpChains,
4581 TailCallArguments, dl);
4583 ArgOffset += PtrByteSize;
4587 if (FPR_idx != NumFPRs) {
4588 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4591 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4592 MachinePointerInfo(), false, false, 0);
4593 MemOpChains.push_back(Store);
4595 // Float varargs are always shadowed in available integer registers
4596 if (GPR_idx != NumGPRs) {
4597 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4598 MachinePointerInfo(), false, false,
4600 MemOpChains.push_back(Load.getValue(1));
4601 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4603 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4604 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4605 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4606 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4607 MachinePointerInfo(),
4608 false, false, false, 0);
4609 MemOpChains.push_back(Load.getValue(1));
4610 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4613 // If we have any FPRs remaining, we may also have GPRs remaining.
4614 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4616 if (GPR_idx != NumGPRs)
4618 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4619 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4623 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4624 isPPC64, isTailCall, false, MemOpChains,
4625 TailCallArguments, dl);
4629 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4636 // These go aligned on the stack, or in the corresponding R registers
4637 // when within range. The Darwin PPC ABI doc claims they also go in
4638 // V registers; in fact gcc does this only for arguments that are
4639 // prototyped, not for those that match the ... We do it for all
4640 // arguments, seems to work.
4641 while (ArgOffset % 16 !=0) {
4642 ArgOffset += PtrByteSize;
4643 if (GPR_idx != NumGPRs)
4646 // We could elide this store in the case where the object fits
4647 // entirely in R registers. Maybe later.
4648 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4649 DAG.getConstant(ArgOffset, PtrVT));
4650 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4651 MachinePointerInfo(), false, false, 0);
4652 MemOpChains.push_back(Store);
4653 if (VR_idx != NumVRs) {
4654 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4655 MachinePointerInfo(),
4656 false, false, false, 0);
4657 MemOpChains.push_back(Load.getValue(1));
4658 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4661 for (unsigned i=0; i<16; i+=PtrByteSize) {
4662 if (GPR_idx == NumGPRs)
4664 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4665 DAG.getConstant(i, PtrVT));
4666 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4667 false, false, false, 0);
4668 MemOpChains.push_back(Load.getValue(1));
4669 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4674 // Non-varargs Altivec params generally go in registers, but have
4675 // stack space allocated at the end.
4676 if (VR_idx != NumVRs) {
4677 // Doesn't have GPR space allocated.
4678 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4679 } else if (nAltivecParamsAtEnd==0) {
4680 // We are emitting Altivec params in order.
4681 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4682 isPPC64, isTailCall, true, MemOpChains,
4683 TailCallArguments, dl);
4689 // If all Altivec parameters fit in registers, as they usually do,
4690 // they get stack space following the non-Altivec parameters. We
4691 // don't track this here because nobody below needs it.
4692 // If there are more Altivec parameters than fit in registers emit
4694 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
4696 // Offset is aligned; skip 1st 12 params which go in V registers.
4697 ArgOffset = ((ArgOffset+15)/16)*16;
4699 for (unsigned i = 0; i != NumOps; ++i) {
4700 SDValue Arg = OutVals[i];
4701 EVT ArgType = Outs[i].VT;
4702 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
4703 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
4706 // We are emitting Altivec params in order.
4707 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4708 isPPC64, isTailCall, true, MemOpChains,
4709 TailCallArguments, dl);
4716 if (!MemOpChains.empty())
4717 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4719 // On Darwin, R12 must contain the address of an indirect callee. This does
4720 // not mean the MTCTR instruction must use R12; it's easier to model this as
4721 // an extra parameter, so do that.
4723 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4724 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4725 !isBLACompatibleAddress(Callee, DAG))
4726 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
4727 PPC::R12), Callee));
4729 // Build a sequence of copy-to-reg nodes chained together with token chain
4730 // and flag operands which copy the outgoing args into the appropriate regs.
4732 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4733 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4734 RegsToPass[i].second, InFlag);
4735 InFlag = Chain.getValue(1);
4739 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
4740 FPOp, true, TailCallArguments);
4742 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4743 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4748 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
4749 MachineFunction &MF, bool isVarArg,
4750 const SmallVectorImpl<ISD::OutputArg> &Outs,
4751 LLVMContext &Context) const {
4752 SmallVector<CCValAssign, 16> RVLocs;
4753 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
4755 return CCInfo.CheckReturn(Outs, RetCC_PPC);
4759 PPCTargetLowering::LowerReturn(SDValue Chain,
4760 CallingConv::ID CallConv, bool isVarArg,
4761 const SmallVectorImpl<ISD::OutputArg> &Outs,
4762 const SmallVectorImpl<SDValue> &OutVals,
4763 SDLoc dl, SelectionDAG &DAG) const {
4765 SmallVector<CCValAssign, 16> RVLocs;
4766 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4767 getTargetMachine(), RVLocs, *DAG.getContext());
4768 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
4771 SmallVector<SDValue, 4> RetOps(1, Chain);
4773 // Copy the result values into the output registers.
4774 for (unsigned i = 0; i != RVLocs.size(); ++i) {
4775 CCValAssign &VA = RVLocs[i];
4776 assert(VA.isRegLoc() && "Can only return in registers!");
4778 SDValue Arg = OutVals[i];
4780 switch (VA.getLocInfo()) {
4781 default: llvm_unreachable("Unknown loc info!");
4782 case CCValAssign::Full: break;
4783 case CCValAssign::AExt:
4784 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
4786 case CCValAssign::ZExt:
4787 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
4789 case CCValAssign::SExt:
4790 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
4794 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
4795 Flag = Chain.getValue(1);
4796 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
4799 RetOps[0] = Chain; // Update chain.
4801 // Add the flag if we have it.
4803 RetOps.push_back(Flag);
4805 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
4808 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
4809 const PPCSubtarget &Subtarget) const {
4810 // When we pop the dynamic allocation we need to restore the SP link.
4813 // Get the corect type for pointers.
4814 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4816 // Construct the stack pointer operand.
4817 bool isPPC64 = Subtarget.isPPC64();
4818 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
4819 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
4821 // Get the operands for the STACKRESTORE.
4822 SDValue Chain = Op.getOperand(0);
4823 SDValue SaveSP = Op.getOperand(1);
4825 // Load the old link SP.
4826 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
4827 MachinePointerInfo(),
4828 false, false, false, 0);
4830 // Restore the stack pointer.
4831 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
4833 // Store the old link SP.
4834 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
4841 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
4842 MachineFunction &MF = DAG.getMachineFunction();
4843 bool isPPC64 = Subtarget.isPPC64();
4844 bool isDarwinABI = Subtarget.isDarwinABI();
4845 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4847 // Get current frame pointer save index. The users of this index will be
4848 // primarily DYNALLOC instructions.
4849 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4850 int RASI = FI->getReturnAddrSaveIndex();
4852 // If the frame pointer save index hasn't been defined yet.
4854 // Find out what the fix offset of the frame pointer save area.
4855 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
4856 // Allocate the frame index for frame pointer save area.
4857 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
4859 FI->setReturnAddrSaveIndex(RASI);
4861 return DAG.getFrameIndex(RASI, PtrVT);
4865 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
4866 MachineFunction &MF = DAG.getMachineFunction();
4867 bool isPPC64 = Subtarget.isPPC64();
4868 bool isDarwinABI = Subtarget.isDarwinABI();
4869 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4871 // Get current frame pointer save index. The users of this index will be
4872 // primarily DYNALLOC instructions.
4873 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4874 int FPSI = FI->getFramePointerSaveIndex();
4876 // If the frame pointer save index hasn't been defined yet.
4878 // Find out what the fix offset of the frame pointer save area.
4879 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
4882 // Allocate the frame index for frame pointer save area.
4883 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
4885 FI->setFramePointerSaveIndex(FPSI);
4887 return DAG.getFrameIndex(FPSI, PtrVT);
4890 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
4892 const PPCSubtarget &Subtarget) const {
4894 SDValue Chain = Op.getOperand(0);
4895 SDValue Size = Op.getOperand(1);
4898 // Get the corect type for pointers.
4899 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4901 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
4902 DAG.getConstant(0, PtrVT), Size);
4903 // Construct a node for the frame pointer save index.
4904 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
4905 // Build a DYNALLOC node.
4906 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
4907 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
4908 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
4911 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
4912 SelectionDAG &DAG) const {
4914 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
4915 DAG.getVTList(MVT::i32, MVT::Other),
4916 Op.getOperand(0), Op.getOperand(1));
4919 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
4920 SelectionDAG &DAG) const {
4922 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
4923 Op.getOperand(0), Op.getOperand(1));
4926 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
4927 assert(Op.getValueType() == MVT::i1 &&
4928 "Custom lowering only for i1 loads");
4930 // First, load 8 bits into 32 bits, then truncate to 1 bit.
4933 LoadSDNode *LD = cast<LoadSDNode>(Op);
4935 SDValue Chain = LD->getChain();
4936 SDValue BasePtr = LD->getBasePtr();
4937 MachineMemOperand *MMO = LD->getMemOperand();
4939 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(), Chain,
4940 BasePtr, MVT::i8, MMO);
4941 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
4943 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
4944 return DAG.getMergeValues(Ops, dl);
4947 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
4948 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
4949 "Custom lowering only for i1 stores");
4951 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
4954 StoreSDNode *ST = cast<StoreSDNode>(Op);
4956 SDValue Chain = ST->getChain();
4957 SDValue BasePtr = ST->getBasePtr();
4958 SDValue Value = ST->getValue();
4959 MachineMemOperand *MMO = ST->getMemOperand();
4961 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(), Value);
4962 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
4965 // FIXME: Remove this once the ANDI glue bug is fixed:
4966 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
4967 assert(Op.getValueType() == MVT::i1 &&
4968 "Custom lowering only for i1 results");
4971 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
4975 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
4977 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
4978 // Not FP? Not a fsel.
4979 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
4980 !Op.getOperand(2).getValueType().isFloatingPoint())
4983 // We might be able to do better than this under some circumstances, but in
4984 // general, fsel-based lowering of select is a finite-math-only optimization.
4985 // For more information, see section F.3 of the 2.06 ISA specification.
4986 if (!DAG.getTarget().Options.NoInfsFPMath ||
4987 !DAG.getTarget().Options.NoNaNsFPMath)
4990 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4992 EVT ResVT = Op.getValueType();
4993 EVT CmpVT = Op.getOperand(0).getValueType();
4994 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4995 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
4998 // If the RHS of the comparison is a 0.0, we don't need to do the
4999 // subtraction at all.
5001 if (isFloatingPointZero(RHS))
5003 default: break; // SETUO etc aren't handled by fsel.
5007 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5008 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5009 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5010 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5011 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5012 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5013 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
5016 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5019 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5020 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5021 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5024 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5027 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5028 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5029 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5030 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
5035 default: break; // SETUO etc aren't handled by fsel.
5039 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5040 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5041 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5042 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5043 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5044 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5045 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5046 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
5049 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5050 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5051 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5052 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5055 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5056 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5057 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5058 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5061 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5062 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5063 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5064 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5067 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5068 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5069 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5070 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5075 // FIXME: Split this code up when LegalizeDAGTypes lands.
5076 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
5078 assert(Op.getOperand(0).getValueType().isFloatingPoint());
5079 SDValue Src = Op.getOperand(0);
5080 if (Src.getValueType() == MVT::f32)
5081 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
5084 switch (Op.getSimpleValueType().SimpleTy) {
5085 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
5087 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
5088 (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ :
5093 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
5094 "i64 FP_TO_UINT is supported only with FPCVT");
5095 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
5101 // Convert the FP value to an int value through memory.
5102 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
5103 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
5104 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
5105 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
5106 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
5108 // Emit a store to the stack slot.
5111 MachineFunction &MF = DAG.getMachineFunction();
5112 MachineMemOperand *MMO =
5113 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
5114 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
5115 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
5116 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
5118 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
5119 MPI, false, false, 0);
5121 // Result is a load from the stack slot. If loading 4 bytes, make sure to
5123 if (Op.getValueType() == MVT::i32 && !i32Stack) {
5124 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
5125 DAG.getConstant(4, FIPtr.getValueType()));
5126 MPI = MachinePointerInfo();
5129 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MPI,
5130 false, false, false, 0);
5133 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
5134 SelectionDAG &DAG) const {
5136 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
5137 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
5140 if (Op.getOperand(0).getValueType() == MVT::i1)
5141 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
5142 DAG.getConstantFP(1.0, Op.getValueType()),
5143 DAG.getConstantFP(0.0, Op.getValueType()));
5145 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
5146 "UINT_TO_FP is supported only with FPCVT");
5148 // If we have FCFIDS, then use it when converting to single-precision.
5149 // Otherwise, convert to double-precision and then round.
5150 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5151 (Op.getOpcode() == ISD::UINT_TO_FP ?
5152 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
5153 (Op.getOpcode() == ISD::UINT_TO_FP ?
5154 PPCISD::FCFIDU : PPCISD::FCFID);
5155 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5156 MVT::f32 : MVT::f64;
5158 if (Op.getOperand(0).getValueType() == MVT::i64) {
5159 SDValue SINT = Op.getOperand(0);
5160 // When converting to single-precision, we actually need to convert
5161 // to double-precision first and then round to single-precision.
5162 // To avoid double-rounding effects during that operation, we have
5163 // to prepare the input operand. Bits that might be truncated when
5164 // converting to double-precision are replaced by a bit that won't
5165 // be lost at this stage, but is below the single-precision rounding
5168 // However, if -enable-unsafe-fp-math is in effect, accept double
5169 // rounding to avoid the extra overhead.
5170 if (Op.getValueType() == MVT::f32 &&
5171 !Subtarget.hasFPCVT() &&
5172 !DAG.getTarget().Options.UnsafeFPMath) {
5174 // Twiddle input to make sure the low 11 bits are zero. (If this
5175 // is the case, we are guaranteed the value will fit into the 53 bit
5176 // mantissa of an IEEE double-precision value without rounding.)
5177 // If any of those low 11 bits were not zero originally, make sure
5178 // bit 12 (value 2048) is set instead, so that the final rounding
5179 // to single-precision gets the correct result.
5180 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5181 SINT, DAG.getConstant(2047, MVT::i64));
5182 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
5183 Round, DAG.getConstant(2047, MVT::i64));
5184 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
5185 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5186 Round, DAG.getConstant(-2048, MVT::i64));
5188 // However, we cannot use that value unconditionally: if the magnitude
5189 // of the input value is small, the bit-twiddling we did above might
5190 // end up visibly changing the output. Fortunately, in that case, we
5191 // don't need to twiddle bits since the original input will convert
5192 // exactly to double-precision floating-point already. Therefore,
5193 // construct a conditional to use the original value if the top 11
5194 // bits are all sign-bit copies, and use the rounded value computed
5196 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
5197 SINT, DAG.getConstant(53, MVT::i32));
5198 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
5199 Cond, DAG.getConstant(1, MVT::i64));
5200 Cond = DAG.getSetCC(dl, MVT::i32,
5201 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
5203 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
5206 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
5207 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
5209 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5210 FP = DAG.getNode(ISD::FP_ROUND, dl,
5211 MVT::f32, FP, DAG.getIntPtrConstant(0));
5215 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
5216 "Unhandled INT_TO_FP type in custom expander!");
5217 // Since we only generate this in 64-bit mode, we can take advantage of
5218 // 64-bit registers. In particular, sign extend the input value into the
5219 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
5220 // then lfd it and fcfid it.
5221 MachineFunction &MF = DAG.getMachineFunction();
5222 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
5223 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5226 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
5227 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
5228 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5230 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
5231 MachinePointerInfo::getFixedStack(FrameIdx),
5234 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
5235 "Expected an i32 store");
5236 MachineMemOperand *MMO =
5237 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
5238 MachineMemOperand::MOLoad, 4, 4);
5239 SDValue Ops[] = { Store, FIdx };
5240 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
5241 PPCISD::LFIWZX : PPCISD::LFIWAX,
5242 dl, DAG.getVTList(MVT::f64, MVT::Other),
5243 Ops, MVT::i32, MMO);
5245 assert(Subtarget.isPPC64() &&
5246 "i32->FP without LFIWAX supported only on PPC64");
5248 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
5249 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5251 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
5254 // STD the extended value into the stack slot.
5255 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
5256 MachinePointerInfo::getFixedStack(FrameIdx),
5259 // Load the value as a double.
5260 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
5261 MachinePointerInfo::getFixedStack(FrameIdx),
5262 false, false, false, 0);
5265 // FCFID it and return it.
5266 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
5267 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5268 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
5272 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
5273 SelectionDAG &DAG) const {
5276 The rounding mode is in bits 30:31 of FPSR, and has the following
5283 FLT_ROUNDS, on the other hand, expects the following:
5290 To perform the conversion, we do:
5291 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
5294 MachineFunction &MF = DAG.getMachineFunction();
5295 EVT VT = Op.getValueType();
5296 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5298 // Save FP Control Word to register
5300 MVT::f64, // return register
5301 MVT::Glue // unused in this context
5303 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
5305 // Save FP register to stack slot
5306 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5307 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
5308 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
5309 StackSlot, MachinePointerInfo(), false, false,0);
5311 // Load FP Control Word from low 32 bits of stack slot.
5312 SDValue Four = DAG.getConstant(4, PtrVT);
5313 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
5314 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
5315 false, false, false, 0);
5317 // Transform as necessary
5319 DAG.getNode(ISD::AND, dl, MVT::i32,
5320 CWD, DAG.getConstant(3, MVT::i32));
5322 DAG.getNode(ISD::SRL, dl, MVT::i32,
5323 DAG.getNode(ISD::AND, dl, MVT::i32,
5324 DAG.getNode(ISD::XOR, dl, MVT::i32,
5325 CWD, DAG.getConstant(3, MVT::i32)),
5326 DAG.getConstant(3, MVT::i32)),
5327 DAG.getConstant(1, MVT::i32));
5330 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
5332 return DAG.getNode((VT.getSizeInBits() < 16 ?
5333 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
5336 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5337 EVT VT = Op.getValueType();
5338 unsigned BitWidth = VT.getSizeInBits();
5340 assert(Op.getNumOperands() == 3 &&
5341 VT == Op.getOperand(1).getValueType() &&
5344 // Expand into a bunch of logical ops. Note that these ops
5345 // depend on the PPC behavior for oversized shift amounts.
5346 SDValue Lo = Op.getOperand(0);
5347 SDValue Hi = Op.getOperand(1);
5348 SDValue Amt = Op.getOperand(2);
5349 EVT AmtVT = Amt.getValueType();
5351 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5352 DAG.getConstant(BitWidth, AmtVT), Amt);
5353 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
5354 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5355 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5356 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5357 DAG.getConstant(-BitWidth, AmtVT));
5358 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5359 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5360 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
5361 SDValue OutOps[] = { OutLo, OutHi };
5362 return DAG.getMergeValues(OutOps, dl);
5365 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5366 EVT VT = Op.getValueType();
5368 unsigned BitWidth = VT.getSizeInBits();
5369 assert(Op.getNumOperands() == 3 &&
5370 VT == Op.getOperand(1).getValueType() &&
5373 // Expand into a bunch of logical ops. Note that these ops
5374 // depend on the PPC behavior for oversized shift amounts.
5375 SDValue Lo = Op.getOperand(0);
5376 SDValue Hi = Op.getOperand(1);
5377 SDValue Amt = Op.getOperand(2);
5378 EVT AmtVT = Amt.getValueType();
5380 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5381 DAG.getConstant(BitWidth, AmtVT), Amt);
5382 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5383 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5384 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5385 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5386 DAG.getConstant(-BitWidth, AmtVT));
5387 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
5388 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5389 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
5390 SDValue OutOps[] = { OutLo, OutHi };
5391 return DAG.getMergeValues(OutOps, dl);
5394 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
5396 EVT VT = Op.getValueType();
5397 unsigned BitWidth = VT.getSizeInBits();
5398 assert(Op.getNumOperands() == 3 &&
5399 VT == Op.getOperand(1).getValueType() &&
5402 // Expand into a bunch of logical ops, followed by a select_cc.
5403 SDValue Lo = Op.getOperand(0);
5404 SDValue Hi = Op.getOperand(1);
5405 SDValue Amt = Op.getOperand(2);
5406 EVT AmtVT = Amt.getValueType();
5408 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5409 DAG.getConstant(BitWidth, AmtVT), Amt);
5410 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5411 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5412 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5413 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5414 DAG.getConstant(-BitWidth, AmtVT));
5415 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
5416 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
5417 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
5418 Tmp4, Tmp6, ISD::SETLE);
5419 SDValue OutOps[] = { OutLo, OutHi };
5420 return DAG.getMergeValues(OutOps, dl);
5423 //===----------------------------------------------------------------------===//
5424 // Vector related lowering.
5427 /// BuildSplatI - Build a canonical splati of Val with an element size of
5428 /// SplatSize. Cast the result to VT.
5429 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
5430 SelectionDAG &DAG, SDLoc dl) {
5431 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
5433 static const EVT VTys[] = { // canonical VT to use for each size.
5434 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
5437 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
5439 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
5443 EVT CanonicalVT = VTys[SplatSize-1];
5445 // Build a canonical splat for this value.
5446 SDValue Elt = DAG.getConstant(Val, MVT::i32);
5447 SmallVector<SDValue, 8> Ops;
5448 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
5449 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
5450 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
5453 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
5454 /// specified intrinsic ID.
5455 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
5456 SelectionDAG &DAG, SDLoc dl,
5457 EVT DestVT = MVT::Other) {
5458 if (DestVT == MVT::Other) DestVT = Op.getValueType();
5459 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5460 DAG.getConstant(IID, MVT::i32), Op);
5463 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
5464 /// specified intrinsic ID.
5465 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
5466 SelectionDAG &DAG, SDLoc dl,
5467 EVT DestVT = MVT::Other) {
5468 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
5469 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5470 DAG.getConstant(IID, MVT::i32), LHS, RHS);
5473 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
5474 /// specified intrinsic ID.
5475 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
5476 SDValue Op2, SelectionDAG &DAG,
5477 SDLoc dl, EVT DestVT = MVT::Other) {
5478 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
5479 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5480 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
5484 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
5485 /// amount. The result has the specified value type.
5486 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
5487 EVT VT, SelectionDAG &DAG, SDLoc dl) {
5488 // Force LHS/RHS to be the right type.
5489 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
5490 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
5493 for (unsigned i = 0; i != 16; ++i)
5495 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
5496 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5499 // If this is a case we can't handle, return null and let the default
5500 // expansion code take care of it. If we CAN select this case, and if it
5501 // selects to a single instruction, return Op. Otherwise, if we can codegen
5502 // this case more efficiently than a constant pool load, lower it to the
5503 // sequence of ops that should be used.
5504 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
5505 SelectionDAG &DAG) const {
5507 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5508 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
5510 // Check if this is a splat of a constant value.
5511 APInt APSplatBits, APSplatUndef;
5512 unsigned SplatBitSize;
5514 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
5515 HasAnyUndefs, 0, true) || SplatBitSize > 32)
5518 unsigned SplatBits = APSplatBits.getZExtValue();
5519 unsigned SplatUndef = APSplatUndef.getZExtValue();
5520 unsigned SplatSize = SplatBitSize / 8;
5522 // First, handle single instruction cases.
5525 if (SplatBits == 0) {
5526 // Canonicalize all zero vectors to be v4i32.
5527 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5528 SDValue Z = DAG.getConstant(0, MVT::i32);
5529 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5530 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
5535 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
5536 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
5538 if (SextVal >= -16 && SextVal <= 15)
5539 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
5542 // Two instruction sequences.
5544 // If this value is in the range [-32,30] and is even, use:
5545 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
5546 // If this value is in the range [17,31] and is odd, use:
5547 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
5548 // If this value is in the range [-31,-17] and is odd, use:
5549 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
5550 // Note the last two are three-instruction sequences.
5551 if (SextVal >= -32 && SextVal <= 31) {
5552 // To avoid having these optimizations undone by constant folding,
5553 // we convert to a pseudo that will be expanded later into one of
5555 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
5556 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
5557 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
5558 SDValue EltSize = DAG.getConstant(SplatSize, MVT::i32);
5559 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
5560 if (VT == Op.getValueType())
5563 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
5566 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
5567 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
5569 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
5570 // Make -1 and vspltisw -1:
5571 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
5573 // Make the VSLW intrinsic, computing 0x8000_0000.
5574 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
5577 // xor by OnesV to invert it.
5578 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5579 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5582 // The remaining cases assume either big endian element order or
5583 // a splat-size that equates to the element size of the vector
5584 // to be built. An example that doesn't work for little endian is
5585 // {0, -1, 0, -1, 0, -1, 0, -1} which has a splat size of 32 bits
5586 // and a vector element size of 16 bits. The code below will
5587 // produce the vector in big endian element order, which for little
5588 // endian is {-1, 0, -1, 0, -1, 0, -1, 0}.
5590 // For now, just avoid these optimizations in that case.
5591 // FIXME: Develop correct optimizations for LE with mismatched
5592 // splat and element sizes.
5594 if (Subtarget.isLittleEndian() &&
5595 SplatSize != Op.getValueType().getVectorElementType().getSizeInBits())
5598 // Check to see if this is a wide variety of vsplti*, binop self cases.
5599 static const signed char SplatCsts[] = {
5600 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
5601 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
5604 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
5605 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
5606 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
5607 int i = SplatCsts[idx];
5609 // Figure out what shift amount will be used by altivec if shifted by i in
5611 unsigned TypeShiftAmt = i & (SplatBitSize-1);
5613 // vsplti + shl self.
5614 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
5615 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5616 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5617 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
5618 Intrinsic::ppc_altivec_vslw
5620 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5621 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5624 // vsplti + srl self.
5625 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5626 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5627 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5628 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
5629 Intrinsic::ppc_altivec_vsrw
5631 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5632 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5635 // vsplti + sra self.
5636 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5637 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5638 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5639 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
5640 Intrinsic::ppc_altivec_vsraw
5642 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5643 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5646 // vsplti + rol self.
5647 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
5648 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
5649 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5650 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5651 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
5652 Intrinsic::ppc_altivec_vrlw
5654 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5655 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5658 // t = vsplti c, result = vsldoi t, t, 1
5659 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
5660 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5661 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
5663 // t = vsplti c, result = vsldoi t, t, 2
5664 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
5665 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5666 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
5668 // t = vsplti c, result = vsldoi t, t, 3
5669 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
5670 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5671 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
5678 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5679 /// the specified operations to build the shuffle.
5680 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5681 SDValue RHS, SelectionDAG &DAG,
5683 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5684 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5685 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5688 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5700 if (OpNum == OP_COPY) {
5701 if (LHSID == (1*9+2)*9+3) return LHS;
5702 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5706 SDValue OpLHS, OpRHS;
5707 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5708 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5712 default: llvm_unreachable("Unknown i32 permute!");
5714 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
5715 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
5716 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
5717 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
5720 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
5721 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
5722 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
5723 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
5726 for (unsigned i = 0; i != 16; ++i)
5727 ShufIdxs[i] = (i&3)+0;
5730 for (unsigned i = 0; i != 16; ++i)
5731 ShufIdxs[i] = (i&3)+4;
5734 for (unsigned i = 0; i != 16; ++i)
5735 ShufIdxs[i] = (i&3)+8;
5738 for (unsigned i = 0; i != 16; ++i)
5739 ShufIdxs[i] = (i&3)+12;
5742 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
5744 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
5746 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
5748 EVT VT = OpLHS.getValueType();
5749 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
5750 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
5751 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
5752 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5755 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
5756 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
5757 /// return the code it can be lowered into. Worst case, it can always be
5758 /// lowered into a vperm.
5759 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5760 SelectionDAG &DAG) const {
5762 SDValue V1 = Op.getOperand(0);
5763 SDValue V2 = Op.getOperand(1);
5764 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5765 EVT VT = Op.getValueType();
5766 bool isLittleEndian = Subtarget.isLittleEndian();
5768 // Cases that are handled by instructions that take permute immediates
5769 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
5770 // selected by the instruction selector.
5771 if (V2.getOpcode() == ISD::UNDEF) {
5772 if (PPC::isSplatShuffleMask(SVOp, 1) ||
5773 PPC::isSplatShuffleMask(SVOp, 2) ||
5774 PPC::isSplatShuffleMask(SVOp, 4) ||
5775 PPC::isVPKUWUMShuffleMask(SVOp, true, DAG) ||
5776 PPC::isVPKUHUMShuffleMask(SVOp, true, DAG) ||
5777 PPC::isVSLDOIShuffleMask(SVOp, true, DAG) != -1 ||
5778 PPC::isVMRGLShuffleMask(SVOp, 1, true, DAG) ||
5779 PPC::isVMRGLShuffleMask(SVOp, 2, true, DAG) ||
5780 PPC::isVMRGLShuffleMask(SVOp, 4, true, DAG) ||
5781 PPC::isVMRGHShuffleMask(SVOp, 1, true, DAG) ||
5782 PPC::isVMRGHShuffleMask(SVOp, 2, true, DAG) ||
5783 PPC::isVMRGHShuffleMask(SVOp, 4, true, DAG)) {
5788 // Altivec has a variety of "shuffle immediates" that take two vector inputs
5789 // and produce a fixed permutation. If any of these match, do not lower to
5791 if (PPC::isVPKUWUMShuffleMask(SVOp, false, DAG) ||
5792 PPC::isVPKUHUMShuffleMask(SVOp, false, DAG) ||
5793 PPC::isVSLDOIShuffleMask(SVOp, false, DAG) != -1 ||
5794 PPC::isVMRGLShuffleMask(SVOp, 1, false, DAG) ||
5795 PPC::isVMRGLShuffleMask(SVOp, 2, false, DAG) ||
5796 PPC::isVMRGLShuffleMask(SVOp, 4, false, DAG) ||
5797 PPC::isVMRGHShuffleMask(SVOp, 1, false, DAG) ||
5798 PPC::isVMRGHShuffleMask(SVOp, 2, false, DAG) ||
5799 PPC::isVMRGHShuffleMask(SVOp, 4, false, DAG))
5802 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
5803 // perfect shuffle table to emit an optimal matching sequence.
5804 ArrayRef<int> PermMask = SVOp->getMask();
5806 unsigned PFIndexes[4];
5807 bool isFourElementShuffle = true;
5808 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
5809 unsigned EltNo = 8; // Start out undef.
5810 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
5811 if (PermMask[i*4+j] < 0)
5812 continue; // Undef, ignore it.
5814 unsigned ByteSource = PermMask[i*4+j];
5815 if ((ByteSource & 3) != j) {
5816 isFourElementShuffle = false;
5821 EltNo = ByteSource/4;
5822 } else if (EltNo != ByteSource/4) {
5823 isFourElementShuffle = false;
5827 PFIndexes[i] = EltNo;
5830 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
5831 // perfect shuffle vector to determine if it is cost effective to do this as
5832 // discrete instructions, or whether we should use a vperm.
5833 // For now, we skip this for little endian until such time as we have a
5834 // little-endian perfect shuffle table.
5835 if (isFourElementShuffle && !isLittleEndian) {
5836 // Compute the index in the perfect shuffle table.
5837 unsigned PFTableIndex =
5838 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5840 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5841 unsigned Cost = (PFEntry >> 30);
5843 // Determining when to avoid vperm is tricky. Many things affect the cost
5844 // of vperm, particularly how many times the perm mask needs to be computed.
5845 // For example, if the perm mask can be hoisted out of a loop or is already
5846 // used (perhaps because there are multiple permutes with the same shuffle
5847 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
5848 // the loop requires an extra register.
5850 // As a compromise, we only emit discrete instructions if the shuffle can be
5851 // generated in 3 or fewer operations. When we have loop information
5852 // available, if this block is within a loop, we should avoid using vperm
5853 // for 3-operation perms and use a constant pool load instead.
5855 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5858 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
5859 // vector that will get spilled to the constant pool.
5860 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
5862 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
5863 // that it is in input element units, not in bytes. Convert now.
5865 // For little endian, the order of the input vectors is reversed, and
5866 // the permutation mask is complemented with respect to 31. This is
5867 // necessary to produce proper semantics with the big-endian-biased vperm
5869 EVT EltVT = V1.getValueType().getVectorElementType();
5870 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
5872 SmallVector<SDValue, 16> ResultMask;
5873 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
5874 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
5876 for (unsigned j = 0; j != BytesPerElement; ++j)
5878 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement+j),
5881 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
5885 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
5888 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
5891 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
5895 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
5896 /// altivec comparison. If it is, return true and fill in Opc/isDot with
5897 /// information about the intrinsic.
5898 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
5900 unsigned IntrinsicID =
5901 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
5904 switch (IntrinsicID) {
5905 default: return false;
5906 // Comparison predicates.
5907 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
5908 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
5909 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
5910 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
5911 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
5912 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
5913 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
5914 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
5915 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
5916 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
5917 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
5918 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
5919 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
5921 // Normal Comparisons.
5922 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
5923 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
5924 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
5925 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
5926 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
5927 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
5928 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
5929 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
5930 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
5931 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
5932 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
5933 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
5934 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
5939 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
5940 /// lower, do it, otherwise return null.
5941 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
5942 SelectionDAG &DAG) const {
5943 // If this is a lowered altivec predicate compare, CompareOpc is set to the
5944 // opcode number of the comparison.
5948 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
5949 return SDValue(); // Don't custom lower most intrinsics.
5951 // If this is a non-dot comparison, make the VCMP node and we are done.
5953 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
5954 Op.getOperand(1), Op.getOperand(2),
5955 DAG.getConstant(CompareOpc, MVT::i32));
5956 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
5959 // Create the PPCISD altivec 'dot' comparison node.
5961 Op.getOperand(2), // LHS
5962 Op.getOperand(3), // RHS
5963 DAG.getConstant(CompareOpc, MVT::i32)
5965 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
5966 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
5968 // Now that we have the comparison, emit a copy from the CR to a GPR.
5969 // This is flagged to the above dot comparison.
5970 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
5971 DAG.getRegister(PPC::CR6, MVT::i32),
5972 CompNode.getValue(1));
5974 // Unpack the result based on how the target uses it.
5975 unsigned BitNo; // Bit # of CR6.
5976 bool InvertBit; // Invert result?
5977 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
5978 default: // Can't happen, don't crash on invalid number though.
5979 case 0: // Return the value of the EQ bit of CR6.
5980 BitNo = 0; InvertBit = false;
5982 case 1: // Return the inverted value of the EQ bit of CR6.
5983 BitNo = 0; InvertBit = true;
5985 case 2: // Return the value of the LT bit of CR6.
5986 BitNo = 2; InvertBit = false;
5988 case 3: // Return the inverted value of the LT bit of CR6.
5989 BitNo = 2; InvertBit = true;
5993 // Shift the bit into the low position.
5994 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
5995 DAG.getConstant(8-(3-BitNo), MVT::i32));
5997 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
5998 DAG.getConstant(1, MVT::i32));
6000 // If we are supposed to, toggle the bit.
6002 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
6003 DAG.getConstant(1, MVT::i32));
6007 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
6008 SelectionDAG &DAG) const {
6010 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
6011 // instructions), but for smaller types, we need to first extend up to v2i32
6012 // before doing going farther.
6013 if (Op.getValueType() == MVT::v2i64) {
6014 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
6015 if (ExtVT != MVT::v2i32) {
6016 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
6017 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
6018 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
6019 ExtVT.getVectorElementType(), 4)));
6020 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
6021 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
6022 DAG.getValueType(MVT::v2i32));
6031 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
6032 SelectionDAG &DAG) const {
6034 // Create a stack slot that is 16-byte aligned.
6035 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6036 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
6037 EVT PtrVT = getPointerTy();
6038 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6040 // Store the input value into Value#0 of the stack slot.
6041 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
6042 Op.getOperand(0), FIdx, MachinePointerInfo(),
6045 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
6046 false, false, false, 0);
6049 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
6051 if (Op.getValueType() == MVT::v4i32) {
6052 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6054 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
6055 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
6057 SDValue RHSSwap = // = vrlw RHS, 16
6058 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
6060 // Shrinkify inputs to v8i16.
6061 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
6062 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
6063 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
6065 // Low parts multiplied together, generating 32-bit results (we ignore the
6067 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
6068 LHS, RHS, DAG, dl, MVT::v4i32);
6070 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
6071 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
6072 // Shift the high parts up 16 bits.
6073 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
6075 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
6076 } else if (Op.getValueType() == MVT::v8i16) {
6077 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6079 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
6081 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
6082 LHS, RHS, Zero, DAG, dl);
6083 } else if (Op.getValueType() == MVT::v16i8) {
6084 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6085 bool isLittleEndian = Subtarget.isLittleEndian();
6087 // Multiply the even 8-bit parts, producing 16-bit sums.
6088 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
6089 LHS, RHS, DAG, dl, MVT::v8i16);
6090 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
6092 // Multiply the odd 8-bit parts, producing 16-bit sums.
6093 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
6094 LHS, RHS, DAG, dl, MVT::v8i16);
6095 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
6097 // Merge the results together. Because vmuleub and vmuloub are
6098 // instructions with a big-endian bias, we must reverse the
6099 // element numbering and reverse the meaning of "odd" and "even"
6100 // when generating little endian code.
6102 for (unsigned i = 0; i != 8; ++i) {
6103 if (isLittleEndian) {
6105 Ops[i*2+1] = 2*i+16;
6108 Ops[i*2+1] = 2*i+1+16;
6112 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
6114 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
6116 llvm_unreachable("Unknown mul to lower!");
6120 /// LowerOperation - Provide custom lowering hooks for some operations.
6122 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6123 switch (Op.getOpcode()) {
6124 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
6125 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6126 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
6127 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6128 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6129 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6130 case ISD::SETCC: return LowerSETCC(Op, DAG);
6131 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
6132 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
6134 return LowerVASTART(Op, DAG, Subtarget);
6137 return LowerVAARG(Op, DAG, Subtarget);
6140 return LowerVACOPY(Op, DAG, Subtarget);
6142 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget);
6143 case ISD::DYNAMIC_STACKALLOC:
6144 return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget);
6146 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
6147 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
6149 case ISD::LOAD: return LowerLOAD(Op, DAG);
6150 case ISD::STORE: return LowerSTORE(Op, DAG);
6151 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
6152 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6153 case ISD::FP_TO_UINT:
6154 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
6156 case ISD::UINT_TO_FP:
6157 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6158 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6160 // Lower 64-bit shifts.
6161 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
6162 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
6163 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
6165 // Vector-related lowering.
6166 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6167 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6168 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6169 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6170 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
6171 case ISD::MUL: return LowerMUL(Op, DAG);
6173 // For counter-based loop handling.
6174 case ISD::INTRINSIC_W_CHAIN: return SDValue();
6176 // Frame & Return address.
6177 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6178 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6182 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
6183 SmallVectorImpl<SDValue>&Results,
6184 SelectionDAG &DAG) const {
6185 const TargetMachine &TM = getTargetMachine();
6187 switch (N->getOpcode()) {
6189 llvm_unreachable("Do not know how to custom type legalize this operation!");
6190 case ISD::INTRINSIC_W_CHAIN: {
6191 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
6192 Intrinsic::ppc_is_decremented_ctr_nonzero)
6195 assert(N->getValueType(0) == MVT::i1 &&
6196 "Unexpected result type for CTR decrement intrinsic");
6197 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
6198 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
6199 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
6202 Results.push_back(NewInt);
6203 Results.push_back(NewInt.getValue(1));
6207 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
6208 || TM.getSubtarget<PPCSubtarget>().isPPC64())
6211 EVT VT = N->getValueType(0);
6213 if (VT == MVT::i64) {
6214 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget);
6216 Results.push_back(NewNode);
6217 Results.push_back(NewNode.getValue(1));
6221 case ISD::FP_ROUND_INREG: {
6222 assert(N->getValueType(0) == MVT::ppcf128);
6223 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
6224 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6225 MVT::f64, N->getOperand(0),
6226 DAG.getIntPtrConstant(0));
6227 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6228 MVT::f64, N->getOperand(0),
6229 DAG.getIntPtrConstant(1));
6231 // Add the two halves of the long double in round-to-zero mode.
6232 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
6234 // We know the low half is about to be thrown away, so just use something
6236 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
6240 case ISD::FP_TO_SINT:
6241 // LowerFP_TO_INT() can only handle f32 and f64.
6242 if (N->getOperand(0).getValueType() == MVT::ppcf128)
6244 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
6250 //===----------------------------------------------------------------------===//
6251 // Other Lowering Code
6252 //===----------------------------------------------------------------------===//
6255 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
6256 bool is64bit, unsigned BinOpcode) const {
6257 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6258 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6260 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6261 MachineFunction *F = BB->getParent();
6262 MachineFunction::iterator It = BB;
6265 unsigned dest = MI->getOperand(0).getReg();
6266 unsigned ptrA = MI->getOperand(1).getReg();
6267 unsigned ptrB = MI->getOperand(2).getReg();
6268 unsigned incr = MI->getOperand(3).getReg();
6269 DebugLoc dl = MI->getDebugLoc();
6271 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6272 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6273 F->insert(It, loopMBB);
6274 F->insert(It, exitMBB);
6275 exitMBB->splice(exitMBB->begin(), BB,
6276 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6277 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6279 MachineRegisterInfo &RegInfo = F->getRegInfo();
6280 unsigned TmpReg = (!BinOpcode) ? incr :
6281 RegInfo.createVirtualRegister(
6282 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6283 (const TargetRegisterClass *) &PPC::GPRCRegClass);
6287 // fallthrough --> loopMBB
6288 BB->addSuccessor(loopMBB);
6291 // l[wd]arx dest, ptr
6292 // add r0, dest, incr
6293 // st[wd]cx. r0, ptr
6295 // fallthrough --> exitMBB
6297 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6298 .addReg(ptrA).addReg(ptrB);
6300 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
6301 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6302 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
6303 BuildMI(BB, dl, TII->get(PPC::BCC))
6304 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6305 BB->addSuccessor(loopMBB);
6306 BB->addSuccessor(exitMBB);
6315 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
6316 MachineBasicBlock *BB,
6317 bool is8bit, // operation
6318 unsigned BinOpcode) const {
6319 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6320 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6321 // In 64 bit mode we have to use 64 bits for addresses, even though the
6322 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
6323 // registers without caring whether they're 32 or 64, but here we're
6324 // doing actual arithmetic on the addresses.
6325 bool is64bit = Subtarget.isPPC64();
6326 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6328 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6329 MachineFunction *F = BB->getParent();
6330 MachineFunction::iterator It = BB;
6333 unsigned dest = MI->getOperand(0).getReg();
6334 unsigned ptrA = MI->getOperand(1).getReg();
6335 unsigned ptrB = MI->getOperand(2).getReg();
6336 unsigned incr = MI->getOperand(3).getReg();
6337 DebugLoc dl = MI->getDebugLoc();
6339 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6340 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6341 F->insert(It, loopMBB);
6342 F->insert(It, exitMBB);
6343 exitMBB->splice(exitMBB->begin(), BB,
6344 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6345 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6347 MachineRegisterInfo &RegInfo = F->getRegInfo();
6348 const TargetRegisterClass *RC =
6349 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6350 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6351 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6352 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6353 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6354 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
6355 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6356 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6357 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6358 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6359 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
6360 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6361 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6363 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
6367 // fallthrough --> loopMBB
6368 BB->addSuccessor(loopMBB);
6370 // The 4-byte load must be aligned, while a char or short may be
6371 // anywhere in the word. Hence all this nasty bookkeeping code.
6372 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6373 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6374 // xori shift, shift1, 24 [16]
6375 // rlwinm ptr, ptr1, 0, 0, 29
6376 // slw incr2, incr, shift
6377 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6378 // slw mask, mask2, shift
6380 // lwarx tmpDest, ptr
6381 // add tmp, tmpDest, incr2
6382 // andc tmp2, tmpDest, mask
6383 // and tmp3, tmp, mask
6384 // or tmp4, tmp3, tmp2
6387 // fallthrough --> exitMBB
6388 // srw dest, tmpDest, shift
6389 if (ptrA != ZeroReg) {
6390 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6391 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6392 .addReg(ptrA).addReg(ptrB);
6396 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6397 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6398 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6399 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6401 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6402 .addReg(Ptr1Reg).addImm(0).addImm(61);
6404 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6405 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6406 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
6407 .addReg(incr).addReg(ShiftReg);
6409 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6411 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6412 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
6414 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6415 .addReg(Mask2Reg).addReg(ShiftReg);
6418 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6419 .addReg(ZeroReg).addReg(PtrReg);
6421 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
6422 .addReg(Incr2Reg).addReg(TmpDestReg);
6423 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
6424 .addReg(TmpDestReg).addReg(MaskReg);
6425 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
6426 .addReg(TmpReg).addReg(MaskReg);
6427 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
6428 .addReg(Tmp3Reg).addReg(Tmp2Reg);
6429 BuildMI(BB, dl, TII->get(PPC::STWCX))
6430 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
6431 BuildMI(BB, dl, TII->get(PPC::BCC))
6432 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6433 BB->addSuccessor(loopMBB);
6434 BB->addSuccessor(exitMBB);
6439 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
6444 llvm::MachineBasicBlock*
6445 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
6446 MachineBasicBlock *MBB) const {
6447 DebugLoc DL = MI->getDebugLoc();
6448 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6450 MachineFunction *MF = MBB->getParent();
6451 MachineRegisterInfo &MRI = MF->getRegInfo();
6453 const BasicBlock *BB = MBB->getBasicBlock();
6454 MachineFunction::iterator I = MBB;
6458 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6459 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6461 unsigned DstReg = MI->getOperand(0).getReg();
6462 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
6463 assert(RC->hasType(MVT::i32) && "Invalid destination!");
6464 unsigned mainDstReg = MRI.createVirtualRegister(RC);
6465 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
6467 MVT PVT = getPointerTy();
6468 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6469 "Invalid Pointer Size!");
6470 // For v = setjmp(buf), we generate
6473 // SjLjSetup mainMBB
6479 // buf[LabelOffset] = LR
6483 // v = phi(main, restore)
6486 MachineBasicBlock *thisMBB = MBB;
6487 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
6488 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
6489 MF->insert(I, mainMBB);
6490 MF->insert(I, sinkMBB);
6492 MachineInstrBuilder MIB;
6494 // Transfer the remainder of BB and its successor edges to sinkMBB.
6495 sinkMBB->splice(sinkMBB->begin(), MBB,
6496 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
6497 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
6499 // Note that the structure of the jmp_buf used here is not compatible
6500 // with that used by libc, and is not designed to be. Specifically, it
6501 // stores only those 'reserved' registers that LLVM does not otherwise
6502 // understand how to spill. Also, by convention, by the time this
6503 // intrinsic is called, Clang has already stored the frame address in the
6504 // first slot of the buffer and stack address in the third. Following the
6505 // X86 target code, we'll store the jump address in the second slot. We also
6506 // need to save the TOC pointer (R2) to handle jumps between shared
6507 // libraries, and that will be stored in the fourth slot. The thread
6508 // identifier (R13) is not affected.
6511 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6512 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6513 const int64_t BPOffset = 4 * PVT.getStoreSize();
6515 // Prepare IP either in reg.
6516 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
6517 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
6518 unsigned BufReg = MI->getOperand(1).getReg();
6520 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
6521 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
6525 MIB.setMemRefs(MMOBegin, MMOEnd);
6528 // Naked functions never have a base pointer, and so we use r1. For all
6529 // other functions, this decision must be delayed until during PEI.
6531 if (MF->getFunction()->getAttributes().hasAttribute(
6532 AttributeSet::FunctionIndex, Attribute::Naked))
6533 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
6535 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
6537 MIB = BuildMI(*thisMBB, MI, DL,
6538 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
6542 MIB.setMemRefs(MMOBegin, MMOEnd);
6545 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
6546 const PPCRegisterInfo *TRI =
6547 static_cast<const PPCRegisterInfo*>(getTargetMachine().getRegisterInfo());
6548 MIB.addRegMask(TRI->getNoPreservedMask());
6550 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
6552 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
6554 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
6556 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
6557 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
6561 MIB = BuildMI(mainMBB, DL,
6562 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
6565 if (Subtarget.isPPC64()) {
6566 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
6568 .addImm(LabelOffset)
6571 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
6573 .addImm(LabelOffset)
6577 MIB.setMemRefs(MMOBegin, MMOEnd);
6579 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
6580 mainMBB->addSuccessor(sinkMBB);
6583 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
6584 TII->get(PPC::PHI), DstReg)
6585 .addReg(mainDstReg).addMBB(mainMBB)
6586 .addReg(restoreDstReg).addMBB(thisMBB);
6588 MI->eraseFromParent();
6593 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
6594 MachineBasicBlock *MBB) const {
6595 DebugLoc DL = MI->getDebugLoc();
6596 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6598 MachineFunction *MF = MBB->getParent();
6599 MachineRegisterInfo &MRI = MF->getRegInfo();
6602 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6603 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6605 MVT PVT = getPointerTy();
6606 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6607 "Invalid Pointer Size!");
6609 const TargetRegisterClass *RC =
6610 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6611 unsigned Tmp = MRI.createVirtualRegister(RC);
6612 // Since FP is only updated here but NOT referenced, it's treated as GPR.
6613 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6614 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6615 unsigned BP = (PVT == MVT::i64) ? PPC::X30 : PPC::R30;
6617 MachineInstrBuilder MIB;
6619 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6620 const int64_t SPOffset = 2 * PVT.getStoreSize();
6621 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6622 const int64_t BPOffset = 4 * PVT.getStoreSize();
6624 unsigned BufReg = MI->getOperand(0).getReg();
6626 // Reload FP (the jumped-to function may not have had a
6627 // frame pointer, and if so, then its r31 will be restored
6629 if (PVT == MVT::i64) {
6630 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
6634 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
6638 MIB.setMemRefs(MMOBegin, MMOEnd);
6641 if (PVT == MVT::i64) {
6642 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
6643 .addImm(LabelOffset)
6646 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
6647 .addImm(LabelOffset)
6650 MIB.setMemRefs(MMOBegin, MMOEnd);
6653 if (PVT == MVT::i64) {
6654 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
6658 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
6662 MIB.setMemRefs(MMOBegin, MMOEnd);
6665 if (PVT == MVT::i64) {
6666 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
6670 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
6674 MIB.setMemRefs(MMOBegin, MMOEnd);
6677 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
6678 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
6682 MIB.setMemRefs(MMOBegin, MMOEnd);
6686 BuildMI(*MBB, MI, DL,
6687 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
6688 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
6690 MI->eraseFromParent();
6695 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6696 MachineBasicBlock *BB) const {
6697 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
6698 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
6699 return emitEHSjLjSetJmp(MI, BB);
6700 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
6701 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
6702 return emitEHSjLjLongJmp(MI, BB);
6705 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6707 // To "insert" these instructions we actually have to insert their
6708 // control-flow patterns.
6709 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6710 MachineFunction::iterator It = BB;
6713 MachineFunction *F = BB->getParent();
6715 if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6716 MI->getOpcode() == PPC::SELECT_CC_I8 ||
6717 MI->getOpcode() == PPC::SELECT_I4 ||
6718 MI->getOpcode() == PPC::SELECT_I8)) {
6719 SmallVector<MachineOperand, 2> Cond;
6720 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6721 MI->getOpcode() == PPC::SELECT_CC_I8)
6722 Cond.push_back(MI->getOperand(4));
6724 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
6725 Cond.push_back(MI->getOperand(1));
6727 DebugLoc dl = MI->getDebugLoc();
6728 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6729 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
6730 Cond, MI->getOperand(2).getReg(),
6731 MI->getOperand(3).getReg());
6732 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6733 MI->getOpcode() == PPC::SELECT_CC_I8 ||
6734 MI->getOpcode() == PPC::SELECT_CC_F4 ||
6735 MI->getOpcode() == PPC::SELECT_CC_F8 ||
6736 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
6737 MI->getOpcode() == PPC::SELECT_I4 ||
6738 MI->getOpcode() == PPC::SELECT_I8 ||
6739 MI->getOpcode() == PPC::SELECT_F4 ||
6740 MI->getOpcode() == PPC::SELECT_F8 ||
6741 MI->getOpcode() == PPC::SELECT_VRRC) {
6742 // The incoming instruction knows the destination vreg to set, the
6743 // condition code register to branch on, the true/false values to
6744 // select between, and a branch opcode to use.
6749 // cmpTY ccX, r1, r2
6751 // fallthrough --> copy0MBB
6752 MachineBasicBlock *thisMBB = BB;
6753 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
6754 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
6755 DebugLoc dl = MI->getDebugLoc();
6756 F->insert(It, copy0MBB);
6757 F->insert(It, sinkMBB);
6759 // Transfer the remainder of BB and its successor edges to sinkMBB.
6760 sinkMBB->splice(sinkMBB->begin(), BB,
6761 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6762 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
6764 // Next, add the true and fallthrough blocks as its successors.
6765 BB->addSuccessor(copy0MBB);
6766 BB->addSuccessor(sinkMBB);
6768 if (MI->getOpcode() == PPC::SELECT_I4 ||
6769 MI->getOpcode() == PPC::SELECT_I8 ||
6770 MI->getOpcode() == PPC::SELECT_F4 ||
6771 MI->getOpcode() == PPC::SELECT_F8 ||
6772 MI->getOpcode() == PPC::SELECT_VRRC) {
6773 BuildMI(BB, dl, TII->get(PPC::BC))
6774 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
6776 unsigned SelectPred = MI->getOperand(4).getImm();
6777 BuildMI(BB, dl, TII->get(PPC::BCC))
6778 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
6782 // %FalseValue = ...
6783 // # fallthrough to sinkMBB
6786 // Update machine-CFG edges
6787 BB->addSuccessor(sinkMBB);
6790 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
6793 BuildMI(*BB, BB->begin(), dl,
6794 TII->get(PPC::PHI), MI->getOperand(0).getReg())
6795 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
6796 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
6798 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
6799 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
6800 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
6801 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
6802 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
6803 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
6804 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
6805 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
6807 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
6808 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
6809 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
6810 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
6811 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
6812 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
6813 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
6814 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
6816 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
6817 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
6818 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
6819 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
6820 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
6821 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
6822 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
6823 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
6825 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
6826 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
6827 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
6828 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
6829 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
6830 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
6831 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
6832 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
6834 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
6835 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
6836 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
6837 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
6838 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
6839 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
6840 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
6841 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
6843 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
6844 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
6845 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
6846 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
6847 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
6848 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
6849 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
6850 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
6852 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
6853 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
6854 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
6855 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
6856 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
6857 BB = EmitAtomicBinary(MI, BB, false, 0);
6858 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
6859 BB = EmitAtomicBinary(MI, BB, true, 0);
6861 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
6862 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
6863 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
6865 unsigned dest = MI->getOperand(0).getReg();
6866 unsigned ptrA = MI->getOperand(1).getReg();
6867 unsigned ptrB = MI->getOperand(2).getReg();
6868 unsigned oldval = MI->getOperand(3).getReg();
6869 unsigned newval = MI->getOperand(4).getReg();
6870 DebugLoc dl = MI->getDebugLoc();
6872 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6873 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6874 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6875 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6876 F->insert(It, loop1MBB);
6877 F->insert(It, loop2MBB);
6878 F->insert(It, midMBB);
6879 F->insert(It, exitMBB);
6880 exitMBB->splice(exitMBB->begin(), BB,
6881 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6882 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6886 // fallthrough --> loopMBB
6887 BB->addSuccessor(loop1MBB);
6890 // l[wd]arx dest, ptr
6891 // cmp[wd] dest, oldval
6894 // st[wd]cx. newval, ptr
6898 // st[wd]cx. dest, ptr
6901 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6902 .addReg(ptrA).addReg(ptrB);
6903 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
6904 .addReg(oldval).addReg(dest);
6905 BuildMI(BB, dl, TII->get(PPC::BCC))
6906 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6907 BB->addSuccessor(loop2MBB);
6908 BB->addSuccessor(midMBB);
6911 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6912 .addReg(newval).addReg(ptrA).addReg(ptrB);
6913 BuildMI(BB, dl, TII->get(PPC::BCC))
6914 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6915 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6916 BB->addSuccessor(loop1MBB);
6917 BB->addSuccessor(exitMBB);
6920 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6921 .addReg(dest).addReg(ptrA).addReg(ptrB);
6922 BB->addSuccessor(exitMBB);
6927 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
6928 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
6929 // We must use 64-bit registers for addresses when targeting 64-bit,
6930 // since we're actually doing arithmetic on them. Other registers
6932 bool is64bit = Subtarget.isPPC64();
6933 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
6935 unsigned dest = MI->getOperand(0).getReg();
6936 unsigned ptrA = MI->getOperand(1).getReg();
6937 unsigned ptrB = MI->getOperand(2).getReg();
6938 unsigned oldval = MI->getOperand(3).getReg();
6939 unsigned newval = MI->getOperand(4).getReg();
6940 DebugLoc dl = MI->getDebugLoc();
6942 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6943 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6944 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6945 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6946 F->insert(It, loop1MBB);
6947 F->insert(It, loop2MBB);
6948 F->insert(It, midMBB);
6949 F->insert(It, exitMBB);
6950 exitMBB->splice(exitMBB->begin(), BB,
6951 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6952 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6954 MachineRegisterInfo &RegInfo = F->getRegInfo();
6955 const TargetRegisterClass *RC =
6956 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6957 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6958 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6959 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6960 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6961 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
6962 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
6963 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
6964 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
6965 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6966 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6967 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6968 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6969 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6970 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6972 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
6973 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6976 // fallthrough --> loopMBB
6977 BB->addSuccessor(loop1MBB);
6979 // The 4-byte load must be aligned, while a char or short may be
6980 // anywhere in the word. Hence all this nasty bookkeeping code.
6981 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6982 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6983 // xori shift, shift1, 24 [16]
6984 // rlwinm ptr, ptr1, 0, 0, 29
6985 // slw newval2, newval, shift
6986 // slw oldval2, oldval,shift
6987 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6988 // slw mask, mask2, shift
6989 // and newval3, newval2, mask
6990 // and oldval3, oldval2, mask
6992 // lwarx tmpDest, ptr
6993 // and tmp, tmpDest, mask
6994 // cmpw tmp, oldval3
6997 // andc tmp2, tmpDest, mask
6998 // or tmp4, tmp2, newval3
7003 // stwcx. tmpDest, ptr
7005 // srw dest, tmpDest, shift
7006 if (ptrA != ZeroReg) {
7007 Ptr1Reg = RegInfo.createVirtualRegister(RC);
7008 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
7009 .addReg(ptrA).addReg(ptrB);
7013 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
7014 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
7015 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
7016 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
7018 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
7019 .addReg(Ptr1Reg).addImm(0).addImm(61);
7021 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
7022 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
7023 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
7024 .addReg(newval).addReg(ShiftReg);
7025 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
7026 .addReg(oldval).addReg(ShiftReg);
7028 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
7030 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
7031 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
7032 .addReg(Mask3Reg).addImm(65535);
7034 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
7035 .addReg(Mask2Reg).addReg(ShiftReg);
7036 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
7037 .addReg(NewVal2Reg).addReg(MaskReg);
7038 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
7039 .addReg(OldVal2Reg).addReg(MaskReg);
7042 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
7043 .addReg(ZeroReg).addReg(PtrReg);
7044 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
7045 .addReg(TmpDestReg).addReg(MaskReg);
7046 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
7047 .addReg(TmpReg).addReg(OldVal3Reg);
7048 BuildMI(BB, dl, TII->get(PPC::BCC))
7049 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7050 BB->addSuccessor(loop2MBB);
7051 BB->addSuccessor(midMBB);
7054 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
7055 .addReg(TmpDestReg).addReg(MaskReg);
7056 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
7057 .addReg(Tmp2Reg).addReg(NewVal3Reg);
7058 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
7059 .addReg(ZeroReg).addReg(PtrReg);
7060 BuildMI(BB, dl, TII->get(PPC::BCC))
7061 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7062 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7063 BB->addSuccessor(loop1MBB);
7064 BB->addSuccessor(exitMBB);
7067 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
7068 .addReg(ZeroReg).addReg(PtrReg);
7069 BB->addSuccessor(exitMBB);
7074 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
7076 } else if (MI->getOpcode() == PPC::FADDrtz) {
7077 // This pseudo performs an FADD with rounding mode temporarily forced
7078 // to round-to-zero. We emit this via custom inserter since the FPSCR
7079 // is not modeled at the SelectionDAG level.
7080 unsigned Dest = MI->getOperand(0).getReg();
7081 unsigned Src1 = MI->getOperand(1).getReg();
7082 unsigned Src2 = MI->getOperand(2).getReg();
7083 DebugLoc dl = MI->getDebugLoc();
7085 MachineRegisterInfo &RegInfo = F->getRegInfo();
7086 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
7088 // Save FPSCR value.
7089 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
7091 // Set rounding mode to round-to-zero.
7092 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
7093 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
7095 // Perform addition.
7096 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
7098 // Restore FPSCR value.
7099 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg);
7100 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7101 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
7102 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7103 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
7104 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7105 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
7106 PPC::ANDIo8 : PPC::ANDIo;
7107 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7108 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
7110 MachineRegisterInfo &RegInfo = F->getRegInfo();
7111 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
7112 &PPC::GPRCRegClass :
7113 &PPC::G8RCRegClass);
7115 DebugLoc dl = MI->getDebugLoc();
7116 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
7117 .addReg(MI->getOperand(1).getReg()).addImm(1);
7118 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
7119 MI->getOperand(0).getReg())
7120 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
7122 llvm_unreachable("Unexpected instr type to insert");
7125 MI->eraseFromParent(); // The pseudo instruction is gone now.
7129 //===----------------------------------------------------------------------===//
7130 // Target Optimization Hooks
7131 //===----------------------------------------------------------------------===//
7133 SDValue PPCTargetLowering::DAGCombineFastRecip(SDValue Op,
7134 DAGCombinerInfo &DCI) const {
7135 if (DCI.isAfterLegalizeVectorOps())
7138 EVT VT = Op.getValueType();
7140 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
7141 (VT == MVT::f64 && Subtarget.hasFRE()) ||
7142 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7143 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7145 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
7146 // For the reciprocal, we need to find the zero of the function:
7147 // F(X) = A X - 1 [which has a zero at X = 1/A]
7149 // X_{i+1} = X_i (2 - A X_i) = X_i + X_i (1 - A X_i) [this second form
7150 // does not require additional intermediate precision]
7152 // Convergence is quadratic, so we essentially double the number of digits
7153 // correct after every iteration. The minimum architected relative
7154 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
7155 // 23 digits and double has 52 digits.
7156 int Iterations = Subtarget.hasRecipPrec() ? 1 : 3;
7157 if (VT.getScalarType() == MVT::f64)
7160 SelectionDAG &DAG = DCI.DAG;
7164 DAG.getConstantFP(1.0, VT.getScalarType());
7165 if (VT.isVector()) {
7166 assert(VT.getVectorNumElements() == 4 &&
7167 "Unknown vector type");
7168 FPOne = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
7169 FPOne, FPOne, FPOne, FPOne);
7172 SDValue Est = DAG.getNode(PPCISD::FRE, dl, VT, Op);
7173 DCI.AddToWorklist(Est.getNode());
7175 // Newton iterations: Est = Est + Est (1 - Arg * Est)
7176 for (int i = 0; i < Iterations; ++i) {
7177 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Op, Est);
7178 DCI.AddToWorklist(NewEst.getNode());
7180 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPOne, NewEst);
7181 DCI.AddToWorklist(NewEst.getNode());
7183 NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
7184 DCI.AddToWorklist(NewEst.getNode());
7186 Est = DAG.getNode(ISD::FADD, dl, VT, Est, NewEst);
7187 DCI.AddToWorklist(Est.getNode());
7196 SDValue PPCTargetLowering::DAGCombineFastRecipFSQRT(SDValue Op,
7197 DAGCombinerInfo &DCI) const {
7198 if (DCI.isAfterLegalizeVectorOps())
7201 EVT VT = Op.getValueType();
7203 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
7204 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
7205 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7206 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7208 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
7209 // For the reciprocal sqrt, we need to find the zero of the function:
7210 // F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
7212 // X_{i+1} = X_i (1.5 - A X_i^2 / 2)
7213 // As a result, we precompute A/2 prior to the iteration loop.
7215 // Convergence is quadratic, so we essentially double the number of digits
7216 // correct after every iteration. The minimum architected relative
7217 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
7218 // 23 digits and double has 52 digits.
7219 int Iterations = Subtarget.hasRecipPrec() ? 1 : 3;
7220 if (VT.getScalarType() == MVT::f64)
7223 SelectionDAG &DAG = DCI.DAG;
7226 SDValue FPThreeHalves =
7227 DAG.getConstantFP(1.5, VT.getScalarType());
7228 if (VT.isVector()) {
7229 assert(VT.getVectorNumElements() == 4 &&
7230 "Unknown vector type");
7231 FPThreeHalves = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
7232 FPThreeHalves, FPThreeHalves,
7233 FPThreeHalves, FPThreeHalves);
7236 SDValue Est = DAG.getNode(PPCISD::FRSQRTE, dl, VT, Op);
7237 DCI.AddToWorklist(Est.getNode());
7239 // We now need 0.5*Arg which we can write as (1.5*Arg - Arg) so that
7240 // this entire sequence requires only one FP constant.
7241 SDValue HalfArg = DAG.getNode(ISD::FMUL, dl, VT, FPThreeHalves, Op);
7242 DCI.AddToWorklist(HalfArg.getNode());
7244 HalfArg = DAG.getNode(ISD::FSUB, dl, VT, HalfArg, Op);
7245 DCI.AddToWorklist(HalfArg.getNode());
7247 // Newton iterations: Est = Est * (1.5 - HalfArg * Est * Est)
7248 for (int i = 0; i < Iterations; ++i) {
7249 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, Est);
7250 DCI.AddToWorklist(NewEst.getNode());
7252 NewEst = DAG.getNode(ISD::FMUL, dl, VT, HalfArg, NewEst);
7253 DCI.AddToWorklist(NewEst.getNode());
7255 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPThreeHalves, NewEst);
7256 DCI.AddToWorklist(NewEst.getNode());
7258 Est = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
7259 DCI.AddToWorklist(Est.getNode());
7268 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
7269 // not enforce equality of the chain operands.
7270 static bool isConsecutiveLS(LSBaseSDNode *LS, LSBaseSDNode *Base,
7271 unsigned Bytes, int Dist,
7272 SelectionDAG &DAG) {
7273 EVT VT = LS->getMemoryVT();
7274 if (VT.getSizeInBits() / 8 != Bytes)
7277 SDValue Loc = LS->getBasePtr();
7278 SDValue BaseLoc = Base->getBasePtr();
7279 if (Loc.getOpcode() == ISD::FrameIndex) {
7280 if (BaseLoc.getOpcode() != ISD::FrameIndex)
7282 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7283 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
7284 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
7285 int FS = MFI->getObjectSize(FI);
7286 int BFS = MFI->getObjectSize(BFI);
7287 if (FS != BFS || FS != (int)Bytes) return false;
7288 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
7292 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
7293 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
7296 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7297 const GlobalValue *GV1 = nullptr;
7298 const GlobalValue *GV2 = nullptr;
7299 int64_t Offset1 = 0;
7300 int64_t Offset2 = 0;
7301 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
7302 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
7303 if (isGA1 && isGA2 && GV1 == GV2)
7304 return Offset1 == (Offset2 + Dist*Bytes);
7308 // Return true is there is a nearyby consecutive load to the one provided
7309 // (regardless of alignment). We search up and down the chain, looking though
7310 // token factors and other loads (but nothing else). As a result, a true
7311 // results indicates that it is safe to create a new consecutive load adjacent
7312 // to the load provided.
7313 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
7314 SDValue Chain = LD->getChain();
7315 EVT VT = LD->getMemoryVT();
7317 SmallSet<SDNode *, 16> LoadRoots;
7318 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
7319 SmallSet<SDNode *, 16> Visited;
7321 // First, search up the chain, branching to follow all token-factor operands.
7322 // If we find a consecutive load, then we're done, otherwise, record all
7323 // nodes just above the top-level loads and token factors.
7324 while (!Queue.empty()) {
7325 SDNode *ChainNext = Queue.pop_back_val();
7326 if (!Visited.insert(ChainNext))
7329 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(ChainNext)) {
7330 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7333 if (!Visited.count(ChainLD->getChain().getNode()))
7334 Queue.push_back(ChainLD->getChain().getNode());
7335 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
7336 for (const SDUse &O : ChainNext->ops())
7337 if (!Visited.count(O.getNode()))
7338 Queue.push_back(O.getNode());
7340 LoadRoots.insert(ChainNext);
7343 // Second, search down the chain, starting from the top-level nodes recorded
7344 // in the first phase. These top-level nodes are the nodes just above all
7345 // loads and token factors. Starting with their uses, recursively look though
7346 // all loads (just the chain uses) and token factors to find a consecutive
7351 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
7352 IE = LoadRoots.end(); I != IE; ++I) {
7353 Queue.push_back(*I);
7355 while (!Queue.empty()) {
7356 SDNode *LoadRoot = Queue.pop_back_val();
7357 if (!Visited.insert(LoadRoot))
7360 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(LoadRoot))
7361 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7364 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
7365 UE = LoadRoot->use_end(); UI != UE; ++UI)
7366 if (((isa<LoadSDNode>(*UI) &&
7367 cast<LoadSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
7368 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
7369 Queue.push_back(*UI);
7376 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
7377 DAGCombinerInfo &DCI) const {
7378 SelectionDAG &DAG = DCI.DAG;
7381 assert(Subtarget.useCRBits() &&
7382 "Expecting to be tracking CR bits");
7383 // If we're tracking CR bits, we need to be careful that we don't have:
7384 // trunc(binary-ops(zext(x), zext(y)))
7386 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
7387 // such that we're unnecessarily moving things into GPRs when it would be
7388 // better to keep them in CR bits.
7390 // Note that trunc here can be an actual i1 trunc, or can be the effective
7391 // truncation that comes from a setcc or select_cc.
7392 if (N->getOpcode() == ISD::TRUNCATE &&
7393 N->getValueType(0) != MVT::i1)
7396 if (N->getOperand(0).getValueType() != MVT::i32 &&
7397 N->getOperand(0).getValueType() != MVT::i64)
7400 if (N->getOpcode() == ISD::SETCC ||
7401 N->getOpcode() == ISD::SELECT_CC) {
7402 // If we're looking at a comparison, then we need to make sure that the
7403 // high bits (all except for the first) don't matter the result.
7405 cast<CondCodeSDNode>(N->getOperand(
7406 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
7407 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
7409 if (ISD::isSignedIntSetCC(CC)) {
7410 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
7411 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
7413 } else if (ISD::isUnsignedIntSetCC(CC)) {
7414 if (!DAG.MaskedValueIsZero(N->getOperand(0),
7415 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
7416 !DAG.MaskedValueIsZero(N->getOperand(1),
7417 APInt::getHighBitsSet(OpBits, OpBits-1)))
7420 // This is neither a signed nor an unsigned comparison, just make sure
7421 // that the high bits are equal.
7422 APInt Op1Zero, Op1One;
7423 APInt Op2Zero, Op2One;
7424 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
7425 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
7427 // We don't really care about what is known about the first bit (if
7428 // anything), so clear it in all masks prior to comparing them.
7429 Op1Zero.clearBit(0); Op1One.clearBit(0);
7430 Op2Zero.clearBit(0); Op2One.clearBit(0);
7432 if (Op1Zero != Op2Zero || Op1One != Op2One)
7437 // We now know that the higher-order bits are irrelevant, we just need to
7438 // make sure that all of the intermediate operations are bit operations, and
7439 // all inputs are extensions.
7440 if (N->getOperand(0).getOpcode() != ISD::AND &&
7441 N->getOperand(0).getOpcode() != ISD::OR &&
7442 N->getOperand(0).getOpcode() != ISD::XOR &&
7443 N->getOperand(0).getOpcode() != ISD::SELECT &&
7444 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
7445 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
7446 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
7447 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
7448 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
7451 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
7452 N->getOperand(1).getOpcode() != ISD::AND &&
7453 N->getOperand(1).getOpcode() != ISD::OR &&
7454 N->getOperand(1).getOpcode() != ISD::XOR &&
7455 N->getOperand(1).getOpcode() != ISD::SELECT &&
7456 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
7457 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
7458 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
7459 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
7460 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
7463 SmallVector<SDValue, 4> Inputs;
7464 SmallVector<SDValue, 8> BinOps, PromOps;
7465 SmallPtrSet<SDNode *, 16> Visited;
7467 for (unsigned i = 0; i < 2; ++i) {
7468 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7469 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7470 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7471 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7472 isa<ConstantSDNode>(N->getOperand(i)))
7473 Inputs.push_back(N->getOperand(i));
7475 BinOps.push_back(N->getOperand(i));
7477 if (N->getOpcode() == ISD::TRUNCATE)
7481 // Visit all inputs, collect all binary operations (and, or, xor and
7482 // select) that are all fed by extensions.
7483 while (!BinOps.empty()) {
7484 SDValue BinOp = BinOps.back();
7487 if (!Visited.insert(BinOp.getNode()))
7490 PromOps.push_back(BinOp);
7492 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
7493 // The condition of the select is not promoted.
7494 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
7496 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
7499 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7500 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7501 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7502 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7503 isa<ConstantSDNode>(BinOp.getOperand(i))) {
7504 Inputs.push_back(BinOp.getOperand(i));
7505 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
7506 BinOp.getOperand(i).getOpcode() == ISD::OR ||
7507 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
7508 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
7509 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
7510 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
7511 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7512 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7513 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
7514 BinOps.push_back(BinOp.getOperand(i));
7516 // We have an input that is not an extension or another binary
7517 // operation; we'll abort this transformation.
7523 // Make sure that this is a self-contained cluster of operations (which
7524 // is not quite the same thing as saying that everything has only one
7526 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7527 if (isa<ConstantSDNode>(Inputs[i]))
7530 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
7531 UE = Inputs[i].getNode()->use_end();
7534 if (User != N && !Visited.count(User))
7537 // Make sure that we're not going to promote the non-output-value
7538 // operand(s) or SELECT or SELECT_CC.
7539 // FIXME: Although we could sometimes handle this, and it does occur in
7540 // practice that one of the condition inputs to the select is also one of
7541 // the outputs, we currently can't deal with this.
7542 if (User->getOpcode() == ISD::SELECT) {
7543 if (User->getOperand(0) == Inputs[i])
7545 } else if (User->getOpcode() == ISD::SELECT_CC) {
7546 if (User->getOperand(0) == Inputs[i] ||
7547 User->getOperand(1) == Inputs[i])
7553 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
7554 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
7555 UE = PromOps[i].getNode()->use_end();
7558 if (User != N && !Visited.count(User))
7561 // Make sure that we're not going to promote the non-output-value
7562 // operand(s) or SELECT or SELECT_CC.
7563 // FIXME: Although we could sometimes handle this, and it does occur in
7564 // practice that one of the condition inputs to the select is also one of
7565 // the outputs, we currently can't deal with this.
7566 if (User->getOpcode() == ISD::SELECT) {
7567 if (User->getOperand(0) == PromOps[i])
7569 } else if (User->getOpcode() == ISD::SELECT_CC) {
7570 if (User->getOperand(0) == PromOps[i] ||
7571 User->getOperand(1) == PromOps[i])
7577 // Replace all inputs with the extension operand.
7578 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7579 // Constants may have users outside the cluster of to-be-promoted nodes,
7580 // and so we need to replace those as we do the promotions.
7581 if (isa<ConstantSDNode>(Inputs[i]))
7584 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
7587 // Replace all operations (these are all the same, but have a different
7588 // (i1) return type). DAG.getNode will validate that the types of
7589 // a binary operator match, so go through the list in reverse so that
7590 // we've likely promoted both operands first. Any intermediate truncations or
7591 // extensions disappear.
7592 while (!PromOps.empty()) {
7593 SDValue PromOp = PromOps.back();
7596 if (PromOp.getOpcode() == ISD::TRUNCATE ||
7597 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
7598 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
7599 PromOp.getOpcode() == ISD::ANY_EXTEND) {
7600 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
7601 PromOp.getOperand(0).getValueType() != MVT::i1) {
7602 // The operand is not yet ready (see comment below).
7603 PromOps.insert(PromOps.begin(), PromOp);
7607 SDValue RepValue = PromOp.getOperand(0);
7608 if (isa<ConstantSDNode>(RepValue))
7609 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
7611 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
7616 switch (PromOp.getOpcode()) {
7617 default: C = 0; break;
7618 case ISD::SELECT: C = 1; break;
7619 case ISD::SELECT_CC: C = 2; break;
7622 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
7623 PromOp.getOperand(C).getValueType() != MVT::i1) ||
7624 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
7625 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
7626 // The to-be-promoted operands of this node have not yet been
7627 // promoted (this should be rare because we're going through the
7628 // list backward, but if one of the operands has several users in
7629 // this cluster of to-be-promoted nodes, it is possible).
7630 PromOps.insert(PromOps.begin(), PromOp);
7634 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
7635 PromOp.getNode()->op_end());
7637 // If there are any constant inputs, make sure they're replaced now.
7638 for (unsigned i = 0; i < 2; ++i)
7639 if (isa<ConstantSDNode>(Ops[C+i]))
7640 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
7642 DAG.ReplaceAllUsesOfValueWith(PromOp,
7643 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
7646 // Now we're left with the initial truncation itself.
7647 if (N->getOpcode() == ISD::TRUNCATE)
7648 return N->getOperand(0);
7650 // Otherwise, this is a comparison. The operands to be compared have just
7651 // changed type (to i1), but everything else is the same.
7652 return SDValue(N, 0);
7655 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
7656 DAGCombinerInfo &DCI) const {
7657 SelectionDAG &DAG = DCI.DAG;
7660 // If we're tracking CR bits, we need to be careful that we don't have:
7661 // zext(binary-ops(trunc(x), trunc(y)))
7663 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
7664 // such that we're unnecessarily moving things into CR bits that can more
7665 // efficiently stay in GPRs. Note that if we're not certain that the high
7666 // bits are set as required by the final extension, we still may need to do
7667 // some masking to get the proper behavior.
7669 // This same functionality is important on PPC64 when dealing with
7670 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
7671 // the return values of functions. Because it is so similar, it is handled
7674 if (N->getValueType(0) != MVT::i32 &&
7675 N->getValueType(0) != MVT::i64)
7678 if (!((N->getOperand(0).getValueType() == MVT::i1 &&
7679 Subtarget.useCRBits()) ||
7680 (N->getOperand(0).getValueType() == MVT::i32 &&
7681 Subtarget.isPPC64())))
7684 if (N->getOperand(0).getOpcode() != ISD::AND &&
7685 N->getOperand(0).getOpcode() != ISD::OR &&
7686 N->getOperand(0).getOpcode() != ISD::XOR &&
7687 N->getOperand(0).getOpcode() != ISD::SELECT &&
7688 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
7691 SmallVector<SDValue, 4> Inputs;
7692 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
7693 SmallPtrSet<SDNode *, 16> Visited;
7695 // Visit all inputs, collect all binary operations (and, or, xor and
7696 // select) that are all fed by truncations.
7697 while (!BinOps.empty()) {
7698 SDValue BinOp = BinOps.back();
7701 if (!Visited.insert(BinOp.getNode()))
7704 PromOps.push_back(BinOp);
7706 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
7707 // The condition of the select is not promoted.
7708 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
7710 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
7713 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
7714 isa<ConstantSDNode>(BinOp.getOperand(i))) {
7715 Inputs.push_back(BinOp.getOperand(i));
7716 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
7717 BinOp.getOperand(i).getOpcode() == ISD::OR ||
7718 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
7719 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
7720 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
7721 BinOps.push_back(BinOp.getOperand(i));
7723 // We have an input that is not a truncation or another binary
7724 // operation; we'll abort this transformation.
7730 // Make sure that this is a self-contained cluster of operations (which
7731 // is not quite the same thing as saying that everything has only one
7733 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7734 if (isa<ConstantSDNode>(Inputs[i]))
7737 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
7738 UE = Inputs[i].getNode()->use_end();
7741 if (User != N && !Visited.count(User))
7744 // Make sure that we're not going to promote the non-output-value
7745 // operand(s) or SELECT or SELECT_CC.
7746 // FIXME: Although we could sometimes handle this, and it does occur in
7747 // practice that one of the condition inputs to the select is also one of
7748 // the outputs, we currently can't deal with this.
7749 if (User->getOpcode() == ISD::SELECT) {
7750 if (User->getOperand(0) == Inputs[i])
7752 } else if (User->getOpcode() == ISD::SELECT_CC) {
7753 if (User->getOperand(0) == Inputs[i] ||
7754 User->getOperand(1) == Inputs[i])
7760 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
7761 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
7762 UE = PromOps[i].getNode()->use_end();
7765 if (User != N && !Visited.count(User))
7768 // Make sure that we're not going to promote the non-output-value
7769 // operand(s) or SELECT or SELECT_CC.
7770 // FIXME: Although we could sometimes handle this, and it does occur in
7771 // practice that one of the condition inputs to the select is also one of
7772 // the outputs, we currently can't deal with this.
7773 if (User->getOpcode() == ISD::SELECT) {
7774 if (User->getOperand(0) == PromOps[i])
7776 } else if (User->getOpcode() == ISD::SELECT_CC) {
7777 if (User->getOperand(0) == PromOps[i] ||
7778 User->getOperand(1) == PromOps[i])
7784 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
7785 bool ReallyNeedsExt = false;
7786 if (N->getOpcode() != ISD::ANY_EXTEND) {
7787 // If all of the inputs are not already sign/zero extended, then
7788 // we'll still need to do that at the end.
7789 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7790 if (isa<ConstantSDNode>(Inputs[i]))
7794 Inputs[i].getOperand(0).getValueSizeInBits();
7795 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
7797 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
7798 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
7799 APInt::getHighBitsSet(OpBits,
7800 OpBits-PromBits))) ||
7801 (N->getOpcode() == ISD::SIGN_EXTEND &&
7802 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
7803 (OpBits-(PromBits-1)))) {
7804 ReallyNeedsExt = true;
7810 // Replace all inputs, either with the truncation operand, or a
7811 // truncation or extension to the final output type.
7812 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7813 // Constant inputs need to be replaced with the to-be-promoted nodes that
7814 // use them because they might have users outside of the cluster of
7816 if (isa<ConstantSDNode>(Inputs[i]))
7819 SDValue InSrc = Inputs[i].getOperand(0);
7820 if (Inputs[i].getValueType() == N->getValueType(0))
7821 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
7822 else if (N->getOpcode() == ISD::SIGN_EXTEND)
7823 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
7824 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
7825 else if (N->getOpcode() == ISD::ZERO_EXTEND)
7826 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
7827 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
7829 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
7830 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
7833 // Replace all operations (these are all the same, but have a different
7834 // (promoted) return type). DAG.getNode will validate that the types of
7835 // a binary operator match, so go through the list in reverse so that
7836 // we've likely promoted both operands first.
7837 while (!PromOps.empty()) {
7838 SDValue PromOp = PromOps.back();
7842 switch (PromOp.getOpcode()) {
7843 default: C = 0; break;
7844 case ISD::SELECT: C = 1; break;
7845 case ISD::SELECT_CC: C = 2; break;
7848 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
7849 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
7850 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
7851 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
7852 // The to-be-promoted operands of this node have not yet been
7853 // promoted (this should be rare because we're going through the
7854 // list backward, but if one of the operands has several users in
7855 // this cluster of to-be-promoted nodes, it is possible).
7856 PromOps.insert(PromOps.begin(), PromOp);
7860 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
7861 PromOp.getNode()->op_end());
7863 // If this node has constant inputs, then they'll need to be promoted here.
7864 for (unsigned i = 0; i < 2; ++i) {
7865 if (!isa<ConstantSDNode>(Ops[C+i]))
7867 if (Ops[C+i].getValueType() == N->getValueType(0))
7870 if (N->getOpcode() == ISD::SIGN_EXTEND)
7871 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
7872 else if (N->getOpcode() == ISD::ZERO_EXTEND)
7873 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
7875 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
7878 DAG.ReplaceAllUsesOfValueWith(PromOp,
7879 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
7882 // Now we're left with the initial extension itself.
7883 if (!ReallyNeedsExt)
7884 return N->getOperand(0);
7886 // To zero extend, just mask off everything except for the first bit (in the
7888 if (N->getOpcode() == ISD::ZERO_EXTEND)
7889 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
7890 DAG.getConstant(APInt::getLowBitsSet(
7891 N->getValueSizeInBits(0), PromBits),
7892 N->getValueType(0)));
7894 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
7895 "Invalid extension type");
7896 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0));
7898 DAG.getConstant(N->getValueSizeInBits(0)-PromBits, ShiftAmountTy);
7899 return DAG.getNode(ISD::SRA, dl, N->getValueType(0),
7900 DAG.getNode(ISD::SHL, dl, N->getValueType(0),
7901 N->getOperand(0), ShiftCst), ShiftCst);
7904 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
7905 DAGCombinerInfo &DCI) const {
7906 const TargetMachine &TM = getTargetMachine();
7907 SelectionDAG &DAG = DCI.DAG;
7909 switch (N->getOpcode()) {
7912 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
7913 if (C->isNullValue()) // 0 << V -> 0.
7914 return N->getOperand(0);
7918 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
7919 if (C->isNullValue()) // 0 >>u V -> 0.
7920 return N->getOperand(0);
7924 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
7925 if (C->isNullValue() || // 0 >>s V -> 0.
7926 C->isAllOnesValue()) // -1 >>s V -> -1.
7927 return N->getOperand(0);
7930 case ISD::SIGN_EXTEND:
7931 case ISD::ZERO_EXTEND:
7932 case ISD::ANY_EXTEND:
7933 return DAGCombineExtBoolTrunc(N, DCI);
7936 case ISD::SELECT_CC:
7937 return DAGCombineTruncBoolExt(N, DCI);
7939 assert(TM.Options.UnsafeFPMath &&
7940 "Reciprocal estimates require UnsafeFPMath");
7942 if (N->getOperand(1).getOpcode() == ISD::FSQRT) {
7944 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0), DCI);
7946 DCI.AddToWorklist(RV.getNode());
7947 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7948 N->getOperand(0), RV);
7950 } else if (N->getOperand(1).getOpcode() == ISD::FP_EXTEND &&
7951 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
7953 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
7956 DCI.AddToWorklist(RV.getNode());
7957 RV = DAG.getNode(ISD::FP_EXTEND, SDLoc(N->getOperand(1)),
7958 N->getValueType(0), RV);
7959 DCI.AddToWorklist(RV.getNode());
7960 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7961 N->getOperand(0), RV);
7963 } else if (N->getOperand(1).getOpcode() == ISD::FP_ROUND &&
7964 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
7966 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
7969 DCI.AddToWorklist(RV.getNode());
7970 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N->getOperand(1)),
7971 N->getValueType(0), RV,
7972 N->getOperand(1).getOperand(1));
7973 DCI.AddToWorklist(RV.getNode());
7974 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7975 N->getOperand(0), RV);
7979 SDValue RV = DAGCombineFastRecip(N->getOperand(1), DCI);
7981 DCI.AddToWorklist(RV.getNode());
7982 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7983 N->getOperand(0), RV);
7989 assert(TM.Options.UnsafeFPMath &&
7990 "Reciprocal estimates require UnsafeFPMath");
7992 // Compute this as 1/(1/sqrt(X)), which is the reciprocal of the
7994 SDValue RV = DAGCombineFastRecipFSQRT(N->getOperand(0), DCI);
7996 DCI.AddToWorklist(RV.getNode());
7997 RV = DAGCombineFastRecip(RV, DCI);
7999 // Unfortunately, RV is now NaN if the input was exactly 0. Select out
8000 // this case and force the answer to 0.
8002 EVT VT = RV.getValueType();
8004 SDValue Zero = DAG.getConstantFP(0.0, VT.getScalarType());
8005 if (VT.isVector()) {
8006 assert(VT.getVectorNumElements() == 4 && "Unknown vector type");
8007 Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Zero, Zero, Zero, Zero);
8011 DAG.getSetCC(dl, getSetCCResultType(*DAG.getContext(), VT),
8012 N->getOperand(0), Zero, ISD::SETEQ);
8013 DCI.AddToWorklist(ZeroCmp.getNode());
8014 DCI.AddToWorklist(RV.getNode());
8016 RV = DAG.getNode(VT.isVector() ? ISD::VSELECT : ISD::SELECT, dl, VT,
8024 case ISD::SINT_TO_FP:
8025 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
8026 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
8027 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
8028 // We allow the src/dst to be either f32/f64, but the intermediate
8029 // type must be i64.
8030 if (N->getOperand(0).getValueType() == MVT::i64 &&
8031 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
8032 SDValue Val = N->getOperand(0).getOperand(0);
8033 if (Val.getValueType() == MVT::f32) {
8034 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8035 DCI.AddToWorklist(Val.getNode());
8038 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
8039 DCI.AddToWorklist(Val.getNode());
8040 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
8041 DCI.AddToWorklist(Val.getNode());
8042 if (N->getValueType(0) == MVT::f32) {
8043 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
8044 DAG.getIntPtrConstant(0));
8045 DCI.AddToWorklist(Val.getNode());
8048 } else if (N->getOperand(0).getValueType() == MVT::i32) {
8049 // If the intermediate type is i32, we can avoid the load/store here
8056 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
8057 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
8058 !cast<StoreSDNode>(N)->isTruncatingStore() &&
8059 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
8060 N->getOperand(1).getValueType() == MVT::i32 &&
8061 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
8062 SDValue Val = N->getOperand(1).getOperand(0);
8063 if (Val.getValueType() == MVT::f32) {
8064 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8065 DCI.AddToWorklist(Val.getNode());
8067 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
8068 DCI.AddToWorklist(Val.getNode());
8071 N->getOperand(0), Val, N->getOperand(2),
8072 DAG.getValueType(N->getOperand(1).getValueType())
8075 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
8076 DAG.getVTList(MVT::Other), Ops,
8077 cast<StoreSDNode>(N)->getMemoryVT(),
8078 cast<StoreSDNode>(N)->getMemOperand());
8079 DCI.AddToWorklist(Val.getNode());
8083 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
8084 if (cast<StoreSDNode>(N)->isUnindexed() &&
8085 N->getOperand(1).getOpcode() == ISD::BSWAP &&
8086 N->getOperand(1).getNode()->hasOneUse() &&
8087 (N->getOperand(1).getValueType() == MVT::i32 ||
8088 N->getOperand(1).getValueType() == MVT::i16 ||
8089 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8090 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8091 N->getOperand(1).getValueType() == MVT::i64))) {
8092 SDValue BSwapOp = N->getOperand(1).getOperand(0);
8093 // Do an any-extend to 32-bits if this is a half-word input.
8094 if (BSwapOp.getValueType() == MVT::i16)
8095 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
8098 N->getOperand(0), BSwapOp, N->getOperand(2),
8099 DAG.getValueType(N->getOperand(1).getValueType())
8102 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
8103 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
8104 cast<StoreSDNode>(N)->getMemOperand());
8108 LoadSDNode *LD = cast<LoadSDNode>(N);
8109 EVT VT = LD->getValueType(0);
8110 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
8111 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
8112 if (ISD::isNON_EXTLoad(N) && VT.isVector() &&
8113 TM.getSubtarget<PPCSubtarget>().hasAltivec() &&
8114 (VT == MVT::v16i8 || VT == MVT::v8i16 ||
8115 VT == MVT::v4i32 || VT == MVT::v4f32) &&
8116 LD->getAlignment() < ABIAlignment) {
8117 // This is a type-legal unaligned Altivec load.
8118 SDValue Chain = LD->getChain();
8119 SDValue Ptr = LD->getBasePtr();
8120 bool isLittleEndian = Subtarget.isLittleEndian();
8122 // This implements the loading of unaligned vectors as described in
8123 // the venerable Apple Velocity Engine overview. Specifically:
8124 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
8125 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
8127 // The general idea is to expand a sequence of one or more unaligned
8128 // loads into an alignment-based permutation-control instruction (lvsl
8129 // or lvsr), a series of regular vector loads (which always truncate
8130 // their input address to an aligned address), and a series of
8131 // permutations. The results of these permutations are the requested
8132 // loaded values. The trick is that the last "extra" load is not taken
8133 // from the address you might suspect (sizeof(vector) bytes after the
8134 // last requested load), but rather sizeof(vector) - 1 bytes after the
8135 // last requested vector. The point of this is to avoid a page fault if
8136 // the base address happened to be aligned. This works because if the
8137 // base address is aligned, then adding less than a full vector length
8138 // will cause the last vector in the sequence to be (re)loaded.
8139 // Otherwise, the next vector will be fetched as you might suspect was
8142 // We might be able to reuse the permutation generation from
8143 // a different base address offset from this one by an aligned amount.
8144 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
8145 // optimization later.
8146 Intrinsic::ID Intr = (isLittleEndian ?
8147 Intrinsic::ppc_altivec_lvsr :
8148 Intrinsic::ppc_altivec_lvsl);
8149 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, MVT::v16i8);
8151 // Refine the alignment of the original load (a "new" load created here
8152 // which was identical to the first except for the alignment would be
8153 // merged with the existing node regardless).
8154 MachineFunction &MF = DAG.getMachineFunction();
8155 MachineMemOperand *MMO =
8156 MF.getMachineMemOperand(LD->getPointerInfo(),
8157 LD->getMemOperand()->getFlags(),
8158 LD->getMemoryVT().getStoreSize(),
8160 LD->refineAlignment(MMO);
8161 SDValue BaseLoad = SDValue(LD, 0);
8163 // Note that the value of IncOffset (which is provided to the next
8164 // load's pointer info offset value, and thus used to calculate the
8165 // alignment), and the value of IncValue (which is actually used to
8166 // increment the pointer value) are different! This is because we
8167 // require the next load to appear to be aligned, even though it
8168 // is actually offset from the base pointer by a lesser amount.
8169 int IncOffset = VT.getSizeInBits() / 8;
8170 int IncValue = IncOffset;
8172 // Walk (both up and down) the chain looking for another load at the real
8173 // (aligned) offset (the alignment of the other load does not matter in
8174 // this case). If found, then do not use the offset reduction trick, as
8175 // that will prevent the loads from being later combined (as they would
8176 // otherwise be duplicates).
8177 if (!findConsecutiveLoad(LD, DAG))
8180 SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
8181 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
8184 DAG.getLoad(VT, dl, Chain, Ptr,
8185 LD->getPointerInfo().getWithOffset(IncOffset),
8186 LD->isVolatile(), LD->isNonTemporal(),
8187 LD->isInvariant(), ABIAlignment);
8189 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
8190 BaseLoad.getValue(1), ExtraLoad.getValue(1));
8192 if (BaseLoad.getValueType() != MVT::v4i32)
8193 BaseLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, BaseLoad);
8195 if (ExtraLoad.getValueType() != MVT::v4i32)
8196 ExtraLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, ExtraLoad);
8198 // Because vperm has a big-endian bias, we must reverse the order
8199 // of the input vectors and complement the permute control vector
8200 // when generating little endian code. We have already handled the
8201 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
8202 // and ExtraLoad here.
8205 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8206 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
8208 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8209 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
8211 if (VT != MVT::v4i32)
8212 Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm);
8214 // Now we need to be really careful about how we update the users of the
8215 // original load. We cannot just call DCI.CombineTo (or
8216 // DAG.ReplaceAllUsesWith for that matter), because the load still has
8217 // uses created here (the permutation for example) that need to stay.
8218 SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
8220 SDUse &Use = UI.getUse();
8222 // Note: BaseLoad is checked here because it might not be N, but a
8224 if (User == Perm.getNode() || User == BaseLoad.getNode() ||
8225 User == TF.getNode() || Use.getResNo() > 1) {
8230 SDValue To = Use.getResNo() ? TF : Perm;
8233 SmallVector<SDValue, 8> Ops;
8234 for (const SDUse &O : User->ops()) {
8241 DAG.UpdateNodeOperands(User, Ops);
8244 return SDValue(N, 0);
8248 case ISD::INTRINSIC_WO_CHAIN: {
8249 bool isLittleEndian = Subtarget.isLittleEndian();
8250 Intrinsic::ID Intr = (isLittleEndian ?
8251 Intrinsic::ppc_altivec_lvsr :
8252 Intrinsic::ppc_altivec_lvsl);
8253 if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() == Intr &&
8254 N->getOperand(1)->getOpcode() == ISD::ADD) {
8255 SDValue Add = N->getOperand(1);
8257 if (DAG.MaskedValueIsZero(Add->getOperand(1),
8258 APInt::getAllOnesValue(4 /* 16 byte alignment */).zext(
8259 Add.getValueType().getScalarType().getSizeInBits()))) {
8260 SDNode *BasePtr = Add->getOperand(0).getNode();
8261 for (SDNode::use_iterator UI = BasePtr->use_begin(),
8262 UE = BasePtr->use_end(); UI != UE; ++UI) {
8263 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8264 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() ==
8266 // We've found another LVSL/LVSR, and this address is an aligned
8267 // multiple of that one. The results will be the same, so use the
8268 // one we've just found instead.
8270 return SDValue(*UI, 0);
8279 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
8280 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
8281 N->getOperand(0).hasOneUse() &&
8282 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
8283 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8284 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8285 N->getValueType(0) == MVT::i64))) {
8286 SDValue Load = N->getOperand(0);
8287 LoadSDNode *LD = cast<LoadSDNode>(Load);
8288 // Create the byte-swapping load.
8290 LD->getChain(), // Chain
8291 LD->getBasePtr(), // Ptr
8292 DAG.getValueType(N->getValueType(0)) // VT
8295 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
8296 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
8297 MVT::i64 : MVT::i32, MVT::Other),
8298 Ops, LD->getMemoryVT(), LD->getMemOperand());
8300 // If this is an i16 load, insert the truncate.
8301 SDValue ResVal = BSLoad;
8302 if (N->getValueType(0) == MVT::i16)
8303 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
8305 // First, combine the bswap away. This makes the value produced by the
8307 DCI.CombineTo(N, ResVal);
8309 // Next, combine the load away, we give it a bogus result value but a real
8310 // chain result. The result value is dead because the bswap is dead.
8311 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
8313 // Return N so it doesn't get rechecked!
8314 return SDValue(N, 0);
8318 case PPCISD::VCMP: {
8319 // If a VCMPo node already exists with exactly the same operands as this
8320 // node, use its result instead of this node (VCMPo computes both a CR6 and
8321 // a normal output).
8323 if (!N->getOperand(0).hasOneUse() &&
8324 !N->getOperand(1).hasOneUse() &&
8325 !N->getOperand(2).hasOneUse()) {
8327 // Scan all of the users of the LHS, looking for VCMPo's that match.
8328 SDNode *VCMPoNode = nullptr;
8330 SDNode *LHSN = N->getOperand(0).getNode();
8331 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
8333 if (UI->getOpcode() == PPCISD::VCMPo &&
8334 UI->getOperand(1) == N->getOperand(1) &&
8335 UI->getOperand(2) == N->getOperand(2) &&
8336 UI->getOperand(0) == N->getOperand(0)) {
8341 // If there is no VCMPo node, or if the flag value has a single use, don't
8343 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
8346 // Look at the (necessarily single) use of the flag value. If it has a
8347 // chain, this transformation is more complex. Note that multiple things
8348 // could use the value result, which we should ignore.
8349 SDNode *FlagUser = nullptr;
8350 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
8351 FlagUser == nullptr; ++UI) {
8352 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
8354 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
8355 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
8362 // If the user is a MFOCRF instruction, we know this is safe.
8363 // Otherwise we give up for right now.
8364 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
8365 return SDValue(VCMPoNode, 0);
8370 SDValue Cond = N->getOperand(1);
8371 SDValue Target = N->getOperand(2);
8373 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8374 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
8375 Intrinsic::ppc_is_decremented_ctr_nonzero) {
8377 // We now need to make the intrinsic dead (it cannot be instruction
8379 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
8380 assert(Cond.getNode()->hasOneUse() &&
8381 "Counter decrement has more than one use");
8383 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
8384 N->getOperand(0), Target);
8389 // If this is a branch on an altivec predicate comparison, lower this so
8390 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
8391 // lowering is done pre-legalize, because the legalizer lowers the predicate
8392 // compare down to code that is difficult to reassemble.
8393 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
8394 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
8396 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
8397 // value. If so, pass-through the AND to get to the intrinsic.
8398 if (LHS.getOpcode() == ISD::AND &&
8399 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8400 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
8401 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8402 isa<ConstantSDNode>(LHS.getOperand(1)) &&
8403 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
8405 LHS = LHS.getOperand(0);
8407 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8408 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
8409 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8410 isa<ConstantSDNode>(RHS)) {
8411 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
8412 "Counter decrement comparison is not EQ or NE");
8414 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8415 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
8416 (CC == ISD::SETNE && !Val);
8418 // We now need to make the intrinsic dead (it cannot be instruction
8420 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
8421 assert(LHS.getNode()->hasOneUse() &&
8422 "Counter decrement has more than one use");
8424 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
8425 N->getOperand(0), N->getOperand(4));
8431 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8432 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
8433 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
8434 assert(isDot && "Can't compare against a vector result!");
8436 // If this is a comparison against something other than 0/1, then we know
8437 // that the condition is never/always true.
8438 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8439 if (Val != 0 && Val != 1) {
8440 if (CC == ISD::SETEQ) // Cond never true, remove branch.
8441 return N->getOperand(0);
8442 // Always !=, turn it into an unconditional branch.
8443 return DAG.getNode(ISD::BR, dl, MVT::Other,
8444 N->getOperand(0), N->getOperand(4));
8447 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
8449 // Create the PPCISD altivec 'dot' comparison node.
8451 LHS.getOperand(2), // LHS of compare
8452 LHS.getOperand(3), // RHS of compare
8453 DAG.getConstant(CompareOpc, MVT::i32)
8455 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
8456 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
8458 // Unpack the result based on how the target uses it.
8459 PPC::Predicate CompOpc;
8460 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
8461 default: // Can't happen, don't crash on invalid number though.
8462 case 0: // Branch on the value of the EQ bit of CR6.
8463 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
8465 case 1: // Branch on the inverted value of the EQ bit of CR6.
8466 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
8468 case 2: // Branch on the value of the LT bit of CR6.
8469 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
8471 case 3: // Branch on the inverted value of the LT bit of CR6.
8472 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
8476 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
8477 DAG.getConstant(CompOpc, MVT::i32),
8478 DAG.getRegister(PPC::CR6, MVT::i32),
8479 N->getOperand(4), CompNode.getValue(1));
8488 //===----------------------------------------------------------------------===//
8489 // Inline Assembly Support
8490 //===----------------------------------------------------------------------===//
8492 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
8495 const SelectionDAG &DAG,
8496 unsigned Depth) const {
8497 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
8498 switch (Op.getOpcode()) {
8500 case PPCISD::LBRX: {
8501 // lhbrx is known to have the top bits cleared out.
8502 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
8503 KnownZero = 0xFFFF0000;
8506 case ISD::INTRINSIC_WO_CHAIN: {
8507 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
8509 case Intrinsic::ppc_altivec_vcmpbfp_p:
8510 case Intrinsic::ppc_altivec_vcmpeqfp_p:
8511 case Intrinsic::ppc_altivec_vcmpequb_p:
8512 case Intrinsic::ppc_altivec_vcmpequh_p:
8513 case Intrinsic::ppc_altivec_vcmpequw_p:
8514 case Intrinsic::ppc_altivec_vcmpgefp_p:
8515 case Intrinsic::ppc_altivec_vcmpgtfp_p:
8516 case Intrinsic::ppc_altivec_vcmpgtsb_p:
8517 case Intrinsic::ppc_altivec_vcmpgtsh_p:
8518 case Intrinsic::ppc_altivec_vcmpgtsw_p:
8519 case Intrinsic::ppc_altivec_vcmpgtub_p:
8520 case Intrinsic::ppc_altivec_vcmpgtuh_p:
8521 case Intrinsic::ppc_altivec_vcmpgtuw_p:
8522 KnownZero = ~1U; // All bits but the low one are known to be zero.
8530 /// getConstraintType - Given a constraint, return the type of
8531 /// constraint it is for this target.
8532 PPCTargetLowering::ConstraintType
8533 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
8534 if (Constraint.size() == 1) {
8535 switch (Constraint[0]) {
8542 return C_RegisterClass;
8544 // FIXME: While Z does indicate a memory constraint, it specifically
8545 // indicates an r+r address (used in conjunction with the 'y' modifier
8546 // in the replacement string). Currently, we're forcing the base
8547 // register to be r0 in the asm printer (which is interpreted as zero)
8548 // and forming the complete address in the second register. This is
8552 } else if (Constraint == "wc") { // individual CR bits.
8553 return C_RegisterClass;
8554 } else if (Constraint == "wa" || Constraint == "wd" ||
8555 Constraint == "wf" || Constraint == "ws") {
8556 return C_RegisterClass; // VSX registers.
8558 return TargetLowering::getConstraintType(Constraint);
8561 /// Examine constraint type and operand type and determine a weight value.
8562 /// This object must already have been set up with the operand type
8563 /// and the current alternative constraint selected.
8564 TargetLowering::ConstraintWeight
8565 PPCTargetLowering::getSingleConstraintMatchWeight(
8566 AsmOperandInfo &info, const char *constraint) const {
8567 ConstraintWeight weight = CW_Invalid;
8568 Value *CallOperandVal = info.CallOperandVal;
8569 // If we don't have a value, we can't do a match,
8570 // but allow it at the lowest weight.
8571 if (!CallOperandVal)
8573 Type *type = CallOperandVal->getType();
8575 // Look at the constraint type.
8576 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
8577 return CW_Register; // an individual CR bit.
8578 else if ((StringRef(constraint) == "wa" ||
8579 StringRef(constraint) == "wd" ||
8580 StringRef(constraint) == "wf") &&
8583 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
8586 switch (*constraint) {
8588 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
8591 if (type->isIntegerTy())
8592 weight = CW_Register;
8595 if (type->isFloatTy())
8596 weight = CW_Register;
8599 if (type->isDoubleTy())
8600 weight = CW_Register;
8603 if (type->isVectorTy())
8604 weight = CW_Register;
8607 weight = CW_Register;
8616 std::pair<unsigned, const TargetRegisterClass*>
8617 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
8619 if (Constraint.size() == 1) {
8620 // GCC RS6000 Constraint Letters
8621 switch (Constraint[0]) {
8623 if (VT == MVT::i64 && Subtarget.isPPC64())
8624 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
8625 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
8627 if (VT == MVT::i64 && Subtarget.isPPC64())
8628 return std::make_pair(0U, &PPC::G8RCRegClass);
8629 return std::make_pair(0U, &PPC::GPRCRegClass);
8631 if (VT == MVT::f32 || VT == MVT::i32)
8632 return std::make_pair(0U, &PPC::F4RCRegClass);
8633 if (VT == MVT::f64 || VT == MVT::i64)
8634 return std::make_pair(0U, &PPC::F8RCRegClass);
8637 return std::make_pair(0U, &PPC::VRRCRegClass);
8639 return std::make_pair(0U, &PPC::CRRCRegClass);
8641 } else if (Constraint == "wc") { // an individual CR bit.
8642 return std::make_pair(0U, &PPC::CRBITRCRegClass);
8643 } else if (Constraint == "wa" || Constraint == "wd" ||
8644 Constraint == "wf") {
8645 return std::make_pair(0U, &PPC::VSRCRegClass);
8646 } else if (Constraint == "ws") {
8647 return std::make_pair(0U, &PPC::VSFRCRegClass);
8650 std::pair<unsigned, const TargetRegisterClass*> R =
8651 TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
8653 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
8654 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
8655 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
8657 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
8658 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
8659 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
8660 PPC::GPRCRegClass.contains(R.first)) {
8661 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
8662 return std::make_pair(TRI->getMatchingSuperReg(R.first,
8663 PPC::sub_32, &PPC::G8RCRegClass),
8664 &PPC::G8RCRegClass);
8671 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
8672 /// vector. If it is invalid, don't add anything to Ops.
8673 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
8674 std::string &Constraint,
8675 std::vector<SDValue>&Ops,
8676 SelectionDAG &DAG) const {
8679 // Only support length 1 constraints.
8680 if (Constraint.length() > 1) return;
8682 char Letter = Constraint[0];
8693 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
8694 if (!CST) return; // Must be an immediate to match.
8695 unsigned Value = CST->getZExtValue();
8697 default: llvm_unreachable("Unknown constraint letter!");
8698 case 'I': // "I" is a signed 16-bit constant.
8699 if ((short)Value == (int)Value)
8700 Result = DAG.getTargetConstant(Value, Op.getValueType());
8702 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
8703 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
8704 if ((short)Value == 0)
8705 Result = DAG.getTargetConstant(Value, Op.getValueType());
8707 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
8708 if ((Value >> 16) == 0)
8709 Result = DAG.getTargetConstant(Value, Op.getValueType());
8711 case 'M': // "M" is a constant that is greater than 31.
8713 Result = DAG.getTargetConstant(Value, Op.getValueType());
8715 case 'N': // "N" is a positive constant that is an exact power of two.
8716 if ((int)Value > 0 && isPowerOf2_32(Value))
8717 Result = DAG.getTargetConstant(Value, Op.getValueType());
8719 case 'O': // "O" is the constant zero.
8721 Result = DAG.getTargetConstant(Value, Op.getValueType());
8723 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
8724 if ((short)-Value == (int)-Value)
8725 Result = DAG.getTargetConstant(Value, Op.getValueType());
8732 if (Result.getNode()) {
8733 Ops.push_back(Result);
8737 // Handle standard constraint letters.
8738 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
8741 // isLegalAddressingMode - Return true if the addressing mode represented
8742 // by AM is legal for this target, for a load/store of the specified type.
8743 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
8745 // FIXME: PPC does not allow r+i addressing modes for vectors!
8747 // PPC allows a sign-extended 16-bit immediate field.
8748 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
8751 // No global is ever allowed as a base.
8755 // PPC only support r+r,
8757 case 0: // "r+i" or just "i", depending on HasBaseReg.
8760 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
8762 // Otherwise we have r+r or r+i.
8765 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
8767 // Allow 2*r as r+r.
8770 // No other scales are supported.
8777 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
8778 SelectionDAG &DAG) const {
8779 MachineFunction &MF = DAG.getMachineFunction();
8780 MachineFrameInfo *MFI = MF.getFrameInfo();
8781 MFI->setReturnAddressIsTaken(true);
8783 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
8787 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8789 // Make sure the function does not optimize away the store of the RA to
8791 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
8792 FuncInfo->setLRStoreRequired();
8793 bool isPPC64 = Subtarget.isPPC64();
8794 bool isDarwinABI = Subtarget.isDarwinABI();
8797 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
8800 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
8801 isPPC64? MVT::i64 : MVT::i32);
8802 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
8803 DAG.getNode(ISD::ADD, dl, getPointerTy(),
8805 MachinePointerInfo(), false, false, false, 0);
8808 // Just load the return address off the stack.
8809 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
8810 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
8811 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
8814 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
8815 SelectionDAG &DAG) const {
8817 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8819 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
8820 bool isPPC64 = PtrVT == MVT::i64;
8822 MachineFunction &MF = DAG.getMachineFunction();
8823 MachineFrameInfo *MFI = MF.getFrameInfo();
8824 MFI->setFrameAddressIsTaken(true);
8826 // Naked functions never have a frame pointer, and so we use r1. For all
8827 // other functions, this decision must be delayed until during PEI.
8829 if (MF.getFunction()->getAttributes().hasAttribute(
8830 AttributeSet::FunctionIndex, Attribute::Naked))
8831 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
8833 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
8835 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
8838 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
8839 FrameAddr, MachinePointerInfo(), false, false,
8844 // FIXME? Maybe this could be a TableGen attribute on some registers and
8845 // this table could be generated automatically from RegInfo.
8846 unsigned PPCTargetLowering::getRegisterByName(const char* RegName,
8848 bool isPPC64 = Subtarget.isPPC64();
8849 bool isDarwinABI = Subtarget.isDarwinABI();
8851 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
8852 (!isPPC64 && VT != MVT::i32))
8853 report_fatal_error("Invalid register global variable type");
8855 bool is64Bit = isPPC64 && VT == MVT::i64;
8856 unsigned Reg = StringSwitch<unsigned>(RegName)
8857 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
8858 .Case("r2", isDarwinABI ? 0 : (is64Bit ? PPC::X2 : PPC::R2))
8859 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
8860 (is64Bit ? PPC::X13 : PPC::R13))
8865 report_fatal_error("Invalid register name global variable");
8869 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
8870 // The PowerPC target isn't yet aware of offsets.
8874 /// getOptimalMemOpType - Returns the target specific optimal type for load
8875 /// and store operations as a result of memset, memcpy, and memmove
8876 /// lowering. If DstAlign is zero that means it's safe to destination
8877 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
8878 /// means there isn't a need to check it against alignment requirement,
8879 /// probably because the source does not need to be loaded. If 'IsMemset' is
8880 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
8881 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
8882 /// source is constant so it does not need to be loaded.
8883 /// It returns EVT::Other if the type should be determined using generic
8884 /// target-independent logic.
8885 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
8886 unsigned DstAlign, unsigned SrcAlign,
8887 bool IsMemset, bool ZeroMemset,
8889 MachineFunction &MF) const {
8890 if (Subtarget.isPPC64()) {
8897 /// \brief Returns true if it is beneficial to convert a load of a constant
8898 /// to just the constant itself.
8899 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
8901 assert(Ty->isIntegerTy());
8903 unsigned BitSize = Ty->getPrimitiveSizeInBits();
8904 if (BitSize == 0 || BitSize > 64)
8909 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
8910 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
8912 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
8913 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
8914 return NumBits1 == 64 && NumBits2 == 32;
8917 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
8918 if (!VT1.isInteger() || !VT2.isInteger())
8920 unsigned NumBits1 = VT1.getSizeInBits();
8921 unsigned NumBits2 = VT2.getSizeInBits();
8922 return NumBits1 == 64 && NumBits2 == 32;
8925 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
8926 return isInt<16>(Imm) || isUInt<16>(Imm);
8929 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
8930 return isInt<16>(Imm) || isUInt<16>(Imm);
8933 bool PPCTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
8936 if (DisablePPCUnaligned)
8939 // PowerPC supports unaligned memory access for simple non-vector types.
8940 // Although accessing unaligned addresses is not as efficient as accessing
8941 // aligned addresses, it is generally more efficient than manual expansion,
8942 // and generally only traps for software emulation when crossing page
8948 if (VT.getSimpleVT().isVector()) {
8949 if (Subtarget.hasVSX()) {
8950 if (VT != MVT::v2f64 && VT != MVT::v2i64)
8957 if (VT == MVT::ppcf128)
8966 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
8967 VT = VT.getScalarType();
8972 switch (VT.getSimpleVT().SimpleTy) {
8984 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
8985 EVT VT , unsigned DefinedValues) const {
8986 if (VT == MVT::v2i64)
8989 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
8992 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
8993 if (DisableILPPref || Subtarget.enableMachineScheduler())
8994 return TargetLowering::getSchedulingPreference(N);
8999 // Create a fast isel object.
9001 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
9002 const TargetLibraryInfo *LibInfo) const {
9003 return PPC::createFastISel(FuncInfo, LibInfo);