1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCCallingConv.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCPerfectShuffle.h"
19 #include "PPCTargetMachine.h"
20 #include "PPCTargetObjectFile.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringSwitch.h"
23 #include "llvm/ADT/Triple.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineLoopInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAG.h"
31 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/Constants.h"
34 #include "llvm/IR/DerivedTypes.h"
35 #include "llvm/IR/Function.h"
36 #include "llvm/IR/Intrinsics.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/Target/TargetOptions.h"
45 // FIXME: Remove this once soft-float is supported.
46 static cl::opt<bool> DisablePPCFloatInVariadic("disable-ppc-float-in-variadic",
47 cl::desc("disable saving float registers for va_start on PPC"), cl::Hidden);
49 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
50 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
52 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
53 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
55 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
56 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
58 // FIXME: Remove this once the bug has been fixed!
59 extern cl::opt<bool> ANDIGlueBug;
61 PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
62 const PPCSubtarget &STI)
63 : TargetLowering(TM), Subtarget(STI) {
64 // Use _setjmp/_longjmp instead of setjmp/longjmp.
65 setUseUnderscoreSetJmp(true);
66 setUseUnderscoreLongJmp(true);
68 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
69 // arguments are at least 4/8 bytes aligned.
70 bool isPPC64 = Subtarget.isPPC64();
71 setMinStackArgumentAlignment(isPPC64 ? 8:4);
73 // Set up the register classes.
74 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
75 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
76 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
78 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
79 for (MVT VT : MVT::integer_valuetypes()) {
80 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
81 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
84 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
86 // PowerPC has pre-inc load and store's.
87 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
91 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
92 setIndexedLoadAction(ISD::PRE_INC, MVT::f32, Legal);
93 setIndexedLoadAction(ISD::PRE_INC, MVT::f64, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
99 setIndexedStoreAction(ISD::PRE_INC, MVT::f32, Legal);
100 setIndexedStoreAction(ISD::PRE_INC, MVT::f64, Legal);
102 if (Subtarget.useCRBits()) {
103 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
105 if (isPPC64 || Subtarget.hasFPCVT()) {
106 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
107 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
108 isPPC64 ? MVT::i64 : MVT::i32);
109 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
110 AddPromotedToType (ISD::UINT_TO_FP, MVT::i1,
111 isPPC64 ? MVT::i64 : MVT::i32);
113 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
114 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
117 // PowerPC does not support direct load / store of condition registers
118 setOperationAction(ISD::LOAD, MVT::i1, Custom);
119 setOperationAction(ISD::STORE, MVT::i1, Custom);
121 // FIXME: Remove this once the ANDI glue bug is fixed:
123 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
125 for (MVT VT : MVT::integer_valuetypes()) {
126 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
127 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
128 setTruncStoreAction(VT, MVT::i1, Expand);
131 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
134 // This is used in the ppcf128->int sequence. Note it has different semantics
135 // from FP_ROUND: that rounds to nearest, this rounds to zero.
136 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
138 // We do not currently implement these libm ops for PowerPC.
139 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
140 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
141 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
142 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
143 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
144 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
146 // PowerPC has no SREM/UREM instructions
147 setOperationAction(ISD::SREM, MVT::i32, Expand);
148 setOperationAction(ISD::UREM, MVT::i32, Expand);
149 setOperationAction(ISD::SREM, MVT::i64, Expand);
150 setOperationAction(ISD::UREM, MVT::i64, Expand);
152 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
153 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
154 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
155 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
156 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
157 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
158 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
159 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
160 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
162 // We don't support sin/cos/sqrt/fmod/pow
163 setOperationAction(ISD::FSIN , MVT::f64, Expand);
164 setOperationAction(ISD::FCOS , MVT::f64, Expand);
165 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
166 setOperationAction(ISD::FREM , MVT::f64, Expand);
167 setOperationAction(ISD::FPOW , MVT::f64, Expand);
168 setOperationAction(ISD::FMA , MVT::f64, Legal);
169 setOperationAction(ISD::FSIN , MVT::f32, Expand);
170 setOperationAction(ISD::FCOS , MVT::f32, Expand);
171 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
172 setOperationAction(ISD::FREM , MVT::f32, Expand);
173 setOperationAction(ISD::FPOW , MVT::f32, Expand);
174 setOperationAction(ISD::FMA , MVT::f32, Legal);
176 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
178 // If we're enabling GP optimizations, use hardware square root
179 if (!Subtarget.hasFSQRT() &&
180 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() &&
182 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
184 if (!Subtarget.hasFSQRT() &&
185 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTES() &&
186 Subtarget.hasFRES()))
187 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
189 if (Subtarget.hasFCPSGN()) {
190 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
191 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
193 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
194 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
197 if (Subtarget.hasFPRND()) {
198 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
199 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
200 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
201 setOperationAction(ISD::FROUND, MVT::f64, Legal);
203 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
204 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
205 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
206 setOperationAction(ISD::FROUND, MVT::f32, Legal);
209 // PowerPC does not have BSWAP, CTPOP or CTTZ
210 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
211 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
212 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
213 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
214 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
215 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
216 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
217 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
219 if (Subtarget.hasPOPCNTD()) {
220 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
221 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
223 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
224 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
227 // PowerPC does not have ROTR
228 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
229 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
231 if (!Subtarget.useCRBits()) {
232 // PowerPC does not have Select
233 setOperationAction(ISD::SELECT, MVT::i32, Expand);
234 setOperationAction(ISD::SELECT, MVT::i64, Expand);
235 setOperationAction(ISD::SELECT, MVT::f32, Expand);
236 setOperationAction(ISD::SELECT, MVT::f64, Expand);
239 // PowerPC wants to turn select_cc of FP into fsel when possible.
240 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
241 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
243 // PowerPC wants to optimize integer setcc a bit
244 if (!Subtarget.useCRBits())
245 setOperationAction(ISD::SETCC, MVT::i32, Custom);
247 // PowerPC does not have BRCOND which requires SetCC
248 if (!Subtarget.useCRBits())
249 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
251 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
253 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
254 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
256 // PowerPC does not have [U|S]INT_TO_FP
257 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
258 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
260 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
261 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
262 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
263 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
265 // We cannot sextinreg(i1). Expand to shifts.
266 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
268 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
269 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
270 // support continuation, user-level threading, and etc.. As a result, no
271 // other SjLj exception interfaces are implemented and please don't build
272 // your own exception handling based on them.
273 // LLVM/Clang supports zero-cost DWARF exception handling.
274 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
275 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
277 // We want to legalize GlobalAddress and ConstantPool nodes into the
278 // appropriate instructions to materialize the address.
279 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
280 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
281 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
282 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
283 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
284 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
285 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
286 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
287 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
288 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
291 setOperationAction(ISD::TRAP, MVT::Other, Legal);
293 // TRAMPOLINE is custom lowered.
294 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
295 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
297 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
298 setOperationAction(ISD::VASTART , MVT::Other, Custom);
300 if (Subtarget.isSVR4ABI()) {
302 // VAARG always uses double-word chunks, so promote anything smaller.
303 setOperationAction(ISD::VAARG, MVT::i1, Promote);
304 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
305 setOperationAction(ISD::VAARG, MVT::i8, Promote);
306 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
307 setOperationAction(ISD::VAARG, MVT::i16, Promote);
308 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
309 setOperationAction(ISD::VAARG, MVT::i32, Promote);
310 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
311 setOperationAction(ISD::VAARG, MVT::Other, Expand);
313 // VAARG is custom lowered with the 32-bit SVR4 ABI.
314 setOperationAction(ISD::VAARG, MVT::Other, Custom);
315 setOperationAction(ISD::VAARG, MVT::i64, Custom);
318 setOperationAction(ISD::VAARG, MVT::Other, Expand);
320 if (Subtarget.isSVR4ABI() && !isPPC64)
321 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
322 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
324 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
326 // Use the default implementation.
327 setOperationAction(ISD::VAEND , MVT::Other, Expand);
328 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
329 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
330 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
331 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
333 // We want to custom lower some of our intrinsics.
334 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
336 // To handle counter-based loop conditions.
337 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
339 // Comparisons that require checking two conditions.
340 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
341 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
342 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
343 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
344 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
345 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
346 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
347 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
348 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
349 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
350 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
351 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
353 if (Subtarget.has64BitSupport()) {
354 // They also have instructions for converting between i64 and fp.
355 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
356 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
357 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
358 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
359 // This is just the low 32 bits of a (signed) fp->i64 conversion.
360 // We cannot do this with Promote because i64 is not a legal type.
361 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
363 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
364 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
366 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
367 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
370 // With the instructions enabled under FPCVT, we can do everything.
371 if (Subtarget.hasFPCVT()) {
372 if (Subtarget.has64BitSupport()) {
373 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
374 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
375 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
376 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
379 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
380 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
381 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
382 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
385 if (Subtarget.use64BitRegs()) {
386 // 64-bit PowerPC implementations can support i64 types directly
387 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
388 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
389 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
390 // 64-bit PowerPC wants to expand i128 shifts itself.
391 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
392 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
393 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
395 // 32-bit PowerPC wants to expand i64 shifts itself.
396 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
397 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
398 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
401 if (Subtarget.hasAltivec()) {
402 // First set operation action for all vector types to expand. Then we
403 // will selectively turn on ones that can be effectively codegen'd.
404 for (MVT VT : MVT::vector_valuetypes()) {
405 // add/sub are legal for all supported vector VT's.
406 setOperationAction(ISD::ADD , VT, Legal);
407 setOperationAction(ISD::SUB , VT, Legal);
409 // Vector instructions introduced in P8
410 if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) {
411 setOperationAction(ISD::CTPOP, VT, Legal);
412 setOperationAction(ISD::CTLZ, VT, Legal);
415 setOperationAction(ISD::CTPOP, VT, Expand);
416 setOperationAction(ISD::CTLZ, VT, Expand);
419 // We promote all shuffles to v16i8.
420 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
421 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
423 // We promote all non-typed operations to v4i32.
424 setOperationAction(ISD::AND , VT, Promote);
425 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
426 setOperationAction(ISD::OR , VT, Promote);
427 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
428 setOperationAction(ISD::XOR , VT, Promote);
429 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
430 setOperationAction(ISD::LOAD , VT, Promote);
431 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
432 setOperationAction(ISD::SELECT, VT, Promote);
433 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
434 setOperationAction(ISD::STORE, VT, Promote);
435 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
437 // No other operations are legal.
438 setOperationAction(ISD::MUL , VT, Expand);
439 setOperationAction(ISD::SDIV, VT, Expand);
440 setOperationAction(ISD::SREM, VT, Expand);
441 setOperationAction(ISD::UDIV, VT, Expand);
442 setOperationAction(ISD::UREM, VT, Expand);
443 setOperationAction(ISD::FDIV, VT, Expand);
444 setOperationAction(ISD::FREM, VT, Expand);
445 setOperationAction(ISD::FNEG, VT, Expand);
446 setOperationAction(ISD::FSQRT, VT, Expand);
447 setOperationAction(ISD::FLOG, VT, Expand);
448 setOperationAction(ISD::FLOG10, VT, Expand);
449 setOperationAction(ISD::FLOG2, VT, Expand);
450 setOperationAction(ISD::FEXP, VT, Expand);
451 setOperationAction(ISD::FEXP2, VT, Expand);
452 setOperationAction(ISD::FSIN, VT, Expand);
453 setOperationAction(ISD::FCOS, VT, Expand);
454 setOperationAction(ISD::FABS, VT, Expand);
455 setOperationAction(ISD::FPOWI, VT, Expand);
456 setOperationAction(ISD::FFLOOR, VT, Expand);
457 setOperationAction(ISD::FCEIL, VT, Expand);
458 setOperationAction(ISD::FTRUNC, VT, Expand);
459 setOperationAction(ISD::FRINT, VT, Expand);
460 setOperationAction(ISD::FNEARBYINT, VT, Expand);
461 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
462 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
463 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
464 setOperationAction(ISD::MULHU, VT, Expand);
465 setOperationAction(ISD::MULHS, VT, Expand);
466 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
467 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
468 setOperationAction(ISD::UDIVREM, VT, Expand);
469 setOperationAction(ISD::SDIVREM, VT, Expand);
470 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
471 setOperationAction(ISD::FPOW, VT, Expand);
472 setOperationAction(ISD::BSWAP, VT, Expand);
473 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
474 setOperationAction(ISD::CTTZ, VT, Expand);
475 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
476 setOperationAction(ISD::VSELECT, VT, Expand);
477 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
479 for (MVT InnerVT : MVT::vector_valuetypes()) {
480 setTruncStoreAction(VT, InnerVT, Expand);
481 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
482 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
483 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
487 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
488 // with merges, splats, etc.
489 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
491 setOperationAction(ISD::AND , MVT::v4i32, Legal);
492 setOperationAction(ISD::OR , MVT::v4i32, Legal);
493 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
494 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
495 setOperationAction(ISD::SELECT, MVT::v4i32,
496 Subtarget.useCRBits() ? Legal : Expand);
497 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
498 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
499 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
500 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
501 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
502 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
503 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
504 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
505 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
507 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
508 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
509 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
510 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
512 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
513 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
515 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
516 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
517 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
521 if (Subtarget.hasP8Altivec())
522 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
524 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
526 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
527 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
529 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
530 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
532 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
533 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
534 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
535 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
537 // Altivec does not contain unordered floating-point compare instructions
538 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
539 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
540 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
541 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
543 if (Subtarget.hasVSX()) {
544 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
545 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
547 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
548 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
549 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
550 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
551 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
553 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
555 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
556 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
558 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
559 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
561 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
562 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
563 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
564 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
565 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
567 // Share the Altivec comparison restrictions.
568 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
569 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
570 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
571 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
573 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
574 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
576 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
578 if (Subtarget.hasP8Vector())
579 addRegisterClass(MVT::f32, &PPC::VSSRCRegClass);
581 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
583 addRegisterClass(MVT::v4i32, &PPC::VSRCRegClass);
584 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
585 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
587 if (Subtarget.hasP8Altivec()) {
588 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
589 setOperationAction(ISD::SRA, MVT::v2i64, Legal);
590 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
592 setOperationAction(ISD::SETCC, MVT::v2i64, Legal);
595 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
596 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
597 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
599 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
601 // VSX v2i64 only supports non-arithmetic operations.
602 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
603 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
606 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
607 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
608 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
609 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
611 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
613 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
614 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
615 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
616 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
618 // Vector operation legalization checks the result type of
619 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
620 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
621 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
622 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
623 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
625 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
628 if (Subtarget.hasP8Altivec()) {
629 addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass);
630 addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass);
634 if (Subtarget.hasQPX()) {
635 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
636 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
637 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
638 setOperationAction(ISD::FREM, MVT::v4f64, Expand);
640 setOperationAction(ISD::FCOPYSIGN, MVT::v4f64, Legal);
641 setOperationAction(ISD::FGETSIGN, MVT::v4f64, Expand);
643 setOperationAction(ISD::LOAD , MVT::v4f64, Custom);
644 setOperationAction(ISD::STORE , MVT::v4f64, Custom);
646 setTruncStoreAction(MVT::v4f64, MVT::v4f32, Custom);
647 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Custom);
649 if (!Subtarget.useCRBits())
650 setOperationAction(ISD::SELECT, MVT::v4f64, Expand);
651 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
653 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f64, Legal);
654 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f64, Expand);
655 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f64, Expand);
656 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f64, Expand);
657 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f64, Custom);
658 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f64, Legal);
659 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
661 setOperationAction(ISD::FP_TO_SINT , MVT::v4f64, Legal);
662 setOperationAction(ISD::FP_TO_UINT , MVT::v4f64, Expand);
664 setOperationAction(ISD::FP_ROUND , MVT::v4f32, Legal);
665 setOperationAction(ISD::FP_ROUND_INREG , MVT::v4f32, Expand);
666 setOperationAction(ISD::FP_EXTEND, MVT::v4f64, Legal);
668 setOperationAction(ISD::FNEG , MVT::v4f64, Legal);
669 setOperationAction(ISD::FABS , MVT::v4f64, Legal);
670 setOperationAction(ISD::FSIN , MVT::v4f64, Expand);
671 setOperationAction(ISD::FCOS , MVT::v4f64, Expand);
672 setOperationAction(ISD::FPOWI , MVT::v4f64, Expand);
673 setOperationAction(ISD::FPOW , MVT::v4f64, Expand);
674 setOperationAction(ISD::FLOG , MVT::v4f64, Expand);
675 setOperationAction(ISD::FLOG2 , MVT::v4f64, Expand);
676 setOperationAction(ISD::FLOG10 , MVT::v4f64, Expand);
677 setOperationAction(ISD::FEXP , MVT::v4f64, Expand);
678 setOperationAction(ISD::FEXP2 , MVT::v4f64, Expand);
680 setOperationAction(ISD::FMINNUM, MVT::v4f64, Legal);
681 setOperationAction(ISD::FMAXNUM, MVT::v4f64, Legal);
683 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f64, Legal);
684 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f64, Legal);
686 addRegisterClass(MVT::v4f64, &PPC::QFRCRegClass);
688 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
689 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
690 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
691 setOperationAction(ISD::FREM, MVT::v4f32, Expand);
693 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Legal);
694 setOperationAction(ISD::FGETSIGN, MVT::v4f32, Expand);
696 setOperationAction(ISD::LOAD , MVT::v4f32, Custom);
697 setOperationAction(ISD::STORE , MVT::v4f32, Custom);
699 if (!Subtarget.useCRBits())
700 setOperationAction(ISD::SELECT, MVT::v4f32, Expand);
701 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
703 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f32, Legal);
704 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f32, Expand);
705 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f32, Expand);
706 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f32, Expand);
707 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f32, Custom);
708 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
709 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
711 setOperationAction(ISD::FP_TO_SINT , MVT::v4f32, Legal);
712 setOperationAction(ISD::FP_TO_UINT , MVT::v4f32, Expand);
714 setOperationAction(ISD::FNEG , MVT::v4f32, Legal);
715 setOperationAction(ISD::FABS , MVT::v4f32, Legal);
716 setOperationAction(ISD::FSIN , MVT::v4f32, Expand);
717 setOperationAction(ISD::FCOS , MVT::v4f32, Expand);
718 setOperationAction(ISD::FPOWI , MVT::v4f32, Expand);
719 setOperationAction(ISD::FPOW , MVT::v4f32, Expand);
720 setOperationAction(ISD::FLOG , MVT::v4f32, Expand);
721 setOperationAction(ISD::FLOG2 , MVT::v4f32, Expand);
722 setOperationAction(ISD::FLOG10 , MVT::v4f32, Expand);
723 setOperationAction(ISD::FEXP , MVT::v4f32, Expand);
724 setOperationAction(ISD::FEXP2 , MVT::v4f32, Expand);
726 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
727 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
729 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f32, Legal);
730 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f32, Legal);
732 addRegisterClass(MVT::v4f32, &PPC::QSRCRegClass);
734 setOperationAction(ISD::AND , MVT::v4i1, Legal);
735 setOperationAction(ISD::OR , MVT::v4i1, Legal);
736 setOperationAction(ISD::XOR , MVT::v4i1, Legal);
738 if (!Subtarget.useCRBits())
739 setOperationAction(ISD::SELECT, MVT::v4i1, Expand);
740 setOperationAction(ISD::VSELECT, MVT::v4i1, Legal);
742 setOperationAction(ISD::LOAD , MVT::v4i1, Custom);
743 setOperationAction(ISD::STORE , MVT::v4i1, Custom);
745 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4i1, Custom);
746 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4i1, Expand);
747 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4i1, Expand);
748 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4i1, Expand);
749 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4i1, Custom);
750 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i1, Expand);
751 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
753 setOperationAction(ISD::SINT_TO_FP, MVT::v4i1, Custom);
754 setOperationAction(ISD::UINT_TO_FP, MVT::v4i1, Custom);
756 addRegisterClass(MVT::v4i1, &PPC::QBRCRegClass);
758 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
759 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
760 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
761 setOperationAction(ISD::FROUND, MVT::v4f64, Legal);
763 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
764 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
765 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
766 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
768 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Expand);
769 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
771 // These need to set FE_INEXACT, and so cannot be vectorized here.
772 setOperationAction(ISD::FRINT, MVT::v4f64, Expand);
773 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
775 if (TM.Options.UnsafeFPMath) {
776 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
777 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
779 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
780 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
782 setOperationAction(ISD::FDIV, MVT::v4f64, Expand);
783 setOperationAction(ISD::FSQRT, MVT::v4f64, Expand);
785 setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
786 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
790 if (Subtarget.has64BitSupport())
791 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
793 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
796 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
797 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
800 setBooleanContents(ZeroOrOneBooleanContent);
802 if (Subtarget.hasAltivec()) {
803 // Altivec instructions set fields to all zeros or all ones.
804 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
808 // These libcalls are not available in 32-bit.
809 setLibcallName(RTLIB::SHL_I128, nullptr);
810 setLibcallName(RTLIB::SRL_I128, nullptr);
811 setLibcallName(RTLIB::SRA_I128, nullptr);
815 setStackPointerRegisterToSaveRestore(PPC::X1);
816 setExceptionPointerRegister(PPC::X3);
817 setExceptionSelectorRegister(PPC::X4);
819 setStackPointerRegisterToSaveRestore(PPC::R1);
820 setExceptionPointerRegister(PPC::R3);
821 setExceptionSelectorRegister(PPC::R4);
824 // We have target-specific dag combine patterns for the following nodes:
825 setTargetDAGCombine(ISD::SINT_TO_FP);
826 if (Subtarget.hasFPCVT())
827 setTargetDAGCombine(ISD::UINT_TO_FP);
828 setTargetDAGCombine(ISD::LOAD);
829 setTargetDAGCombine(ISD::STORE);
830 setTargetDAGCombine(ISD::BR_CC);
831 if (Subtarget.useCRBits())
832 setTargetDAGCombine(ISD::BRCOND);
833 setTargetDAGCombine(ISD::BSWAP);
834 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
835 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
836 setTargetDAGCombine(ISD::INTRINSIC_VOID);
838 setTargetDAGCombine(ISD::SIGN_EXTEND);
839 setTargetDAGCombine(ISD::ZERO_EXTEND);
840 setTargetDAGCombine(ISD::ANY_EXTEND);
842 if (Subtarget.useCRBits()) {
843 setTargetDAGCombine(ISD::TRUNCATE);
844 setTargetDAGCombine(ISD::SETCC);
845 setTargetDAGCombine(ISD::SELECT_CC);
848 // Use reciprocal estimates.
849 if (TM.Options.UnsafeFPMath) {
850 setTargetDAGCombine(ISD::FDIV);
851 setTargetDAGCombine(ISD::FSQRT);
854 // Darwin long double math library functions have $LDBL128 appended.
855 if (Subtarget.isDarwin()) {
856 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
857 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
858 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
859 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
860 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
861 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
862 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
863 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
864 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
865 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
868 // With 32 condition bits, we don't need to sink (and duplicate) compares
869 // aggressively in CodeGenPrep.
870 if (Subtarget.useCRBits()) {
871 setHasMultipleConditionRegisters();
872 setJumpIsExpensive();
875 setMinFunctionAlignment(2);
876 if (Subtarget.isDarwin())
877 setPrefFunctionAlignment(4);
879 switch (Subtarget.getDarwinDirective()) {
883 case PPC::DIR_E500mc:
892 setPrefFunctionAlignment(4);
893 setPrefLoopAlignment(4);
897 setInsertFencesForAtomic(true);
899 if (Subtarget.enableMachineScheduler())
900 setSchedulingPreference(Sched::Source);
902 setSchedulingPreference(Sched::Hybrid);
904 computeRegisterProperties(STI.getRegisterInfo());
906 // The Freescale cores do better with aggressive inlining of memcpy and
907 // friends. GCC uses same threshold of 128 bytes (= 32 word stores).
908 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
909 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
910 MaxStoresPerMemset = 32;
911 MaxStoresPerMemsetOptSize = 16;
912 MaxStoresPerMemcpy = 32;
913 MaxStoresPerMemcpyOptSize = 8;
914 MaxStoresPerMemmove = 32;
915 MaxStoresPerMemmoveOptSize = 8;
916 } else if (Subtarget.getDarwinDirective() == PPC::DIR_A2) {
917 // The A2 also benefits from (very) aggressive inlining of memcpy and
918 // friends. The overhead of a the function call, even when warm, can be
919 // over one hundred cycles.
920 MaxStoresPerMemset = 128;
921 MaxStoresPerMemcpy = 128;
922 MaxStoresPerMemmove = 128;
926 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
927 /// the desired ByVal argument alignment.
928 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
929 unsigned MaxMaxAlign) {
930 if (MaxAlign == MaxMaxAlign)
932 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
933 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
935 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
937 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
938 unsigned EltAlign = 0;
939 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
940 if (EltAlign > MaxAlign)
942 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
943 for (auto *EltTy : STy->elements()) {
944 unsigned EltAlign = 0;
945 getMaxByValAlign(EltTy, EltAlign, MaxMaxAlign);
946 if (EltAlign > MaxAlign)
948 if (MaxAlign == MaxMaxAlign)
954 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
955 /// function arguments in the caller parameter area.
956 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty,
957 const DataLayout &DL) const {
958 // Darwin passes everything on 4 byte boundary.
959 if (Subtarget.isDarwin())
962 // 16byte and wider vectors are passed on 16byte boundary.
963 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
964 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
965 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
966 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
970 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
971 switch ((PPCISD::NodeType)Opcode) {
972 case PPCISD::FIRST_NUMBER: break;
973 case PPCISD::FSEL: return "PPCISD::FSEL";
974 case PPCISD::FCFID: return "PPCISD::FCFID";
975 case PPCISD::FCFIDU: return "PPCISD::FCFIDU";
976 case PPCISD::FCFIDS: return "PPCISD::FCFIDS";
977 case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS";
978 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
979 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
980 case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ";
981 case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ";
982 case PPCISD::FRE: return "PPCISD::FRE";
983 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
984 case PPCISD::STFIWX: return "PPCISD::STFIWX";
985 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
986 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
987 case PPCISD::VPERM: return "PPCISD::VPERM";
988 case PPCISD::CMPB: return "PPCISD::CMPB";
989 case PPCISD::Hi: return "PPCISD::Hi";
990 case PPCISD::Lo: return "PPCISD::Lo";
991 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
992 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
993 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
994 case PPCISD::SRL: return "PPCISD::SRL";
995 case PPCISD::SRA: return "PPCISD::SRA";
996 case PPCISD::SHL: return "PPCISD::SHL";
997 case PPCISD::SRA_ADDZE: return "PPCISD::SRA_ADDZE";
998 case PPCISD::CALL: return "PPCISD::CALL";
999 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
1000 case PPCISD::MTCTR: return "PPCISD::MTCTR";
1001 case PPCISD::BCTRL: return "PPCISD::BCTRL";
1002 case PPCISD::BCTRL_LOAD_TOC: return "PPCISD::BCTRL_LOAD_TOC";
1003 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
1004 case PPCISD::READ_TIME_BASE: return "PPCISD::READ_TIME_BASE";
1005 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
1006 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
1007 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
1008 case PPCISD::MFVSR: return "PPCISD::MFVSR";
1009 case PPCISD::MTVSRA: return "PPCISD::MTVSRA";
1010 case PPCISD::MTVSRZ: return "PPCISD::MTVSRZ";
1011 case PPCISD::ANDIo_1_EQ_BIT: return "PPCISD::ANDIo_1_EQ_BIT";
1012 case PPCISD::ANDIo_1_GT_BIT: return "PPCISD::ANDIo_1_GT_BIT";
1013 case PPCISD::VCMP: return "PPCISD::VCMP";
1014 case PPCISD::VCMPo: return "PPCISD::VCMPo";
1015 case PPCISD::LBRX: return "PPCISD::LBRX";
1016 case PPCISD::STBRX: return "PPCISD::STBRX";
1017 case PPCISD::LFIWAX: return "PPCISD::LFIWAX";
1018 case PPCISD::LFIWZX: return "PPCISD::LFIWZX";
1019 case PPCISD::LXVD2X: return "PPCISD::LXVD2X";
1020 case PPCISD::STXVD2X: return "PPCISD::STXVD2X";
1021 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
1022 case PPCISD::BDNZ: return "PPCISD::BDNZ";
1023 case PPCISD::BDZ: return "PPCISD::BDZ";
1024 case PPCISD::MFFS: return "PPCISD::MFFS";
1025 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
1026 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
1027 case PPCISD::CR6SET: return "PPCISD::CR6SET";
1028 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
1029 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
1030 case PPCISD::PPC32_PICGOT: return "PPCISD::PPC32_PICGOT";
1031 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
1032 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
1033 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
1034 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
1035 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
1036 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
1037 case PPCISD::ADDI_TLSGD_L_ADDR: return "PPCISD::ADDI_TLSGD_L_ADDR";
1038 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
1039 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
1040 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
1041 case PPCISD::ADDI_TLSLD_L_ADDR: return "PPCISD::ADDI_TLSLD_L_ADDR";
1042 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
1043 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
1044 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
1045 case PPCISD::SC: return "PPCISD::SC";
1046 case PPCISD::CLRBHRB: return "PPCISD::CLRBHRB";
1047 case PPCISD::MFBHRBE: return "PPCISD::MFBHRBE";
1048 case PPCISD::RFEBB: return "PPCISD::RFEBB";
1049 case PPCISD::XXSWAPD: return "PPCISD::XXSWAPD";
1050 case PPCISD::QVFPERM: return "PPCISD::QVFPERM";
1051 case PPCISD::QVGPCI: return "PPCISD::QVGPCI";
1052 case PPCISD::QVALIGNI: return "PPCISD::QVALIGNI";
1053 case PPCISD::QVESPLATI: return "PPCISD::QVESPLATI";
1054 case PPCISD::QBFLT: return "PPCISD::QBFLT";
1055 case PPCISD::QVLFSb: return "PPCISD::QVLFSb";
1060 EVT PPCTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &C,
1063 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
1065 if (Subtarget.hasQPX())
1066 return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements());
1068 return VT.changeVectorElementTypeToInteger();
1071 bool PPCTargetLowering::enableAggressiveFMAFusion(EVT VT) const {
1072 assert(VT.isFloatingPoint() && "Non-floating-point FMA?");
1076 //===----------------------------------------------------------------------===//
1077 // Node matching predicates, for use by the tblgen matching code.
1078 //===----------------------------------------------------------------------===//
1080 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
1081 static bool isFloatingPointZero(SDValue Op) {
1082 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1083 return CFP->getValueAPF().isZero();
1084 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1085 // Maybe this has already been legalized into the constant pool?
1086 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
1087 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1088 return CFP->getValueAPF().isZero();
1093 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
1094 /// true if Op is undef or if it matches the specified value.
1095 static bool isConstantOrUndef(int Op, int Val) {
1096 return Op < 0 || Op == Val;
1099 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
1100 /// VPKUHUM instruction.
1101 /// The ShuffleKind distinguishes between big-endian operations with
1102 /// two different inputs (0), either-endian operations with two identical
1103 /// inputs (1), and little-endian operations with two different inputs (2).
1104 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1105 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1106 SelectionDAG &DAG) {
1107 bool IsLE = DAG.getDataLayout().isLittleEndian();
1108 if (ShuffleKind == 0) {
1111 for (unsigned i = 0; i != 16; ++i)
1112 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
1114 } else if (ShuffleKind == 2) {
1117 for (unsigned i = 0; i != 16; ++i)
1118 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
1120 } else if (ShuffleKind == 1) {
1121 unsigned j = IsLE ? 0 : 1;
1122 for (unsigned i = 0; i != 8; ++i)
1123 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
1124 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
1130 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
1131 /// VPKUWUM instruction.
1132 /// The ShuffleKind distinguishes between big-endian operations with
1133 /// two different inputs (0), either-endian operations with two identical
1134 /// inputs (1), and little-endian operations with two different inputs (2).
1135 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1136 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1137 SelectionDAG &DAG) {
1138 bool IsLE = DAG.getDataLayout().isLittleEndian();
1139 if (ShuffleKind == 0) {
1142 for (unsigned i = 0; i != 16; i += 2)
1143 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
1144 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
1146 } else if (ShuffleKind == 2) {
1149 for (unsigned i = 0; i != 16; i += 2)
1150 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1151 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
1153 } else if (ShuffleKind == 1) {
1154 unsigned j = IsLE ? 0 : 2;
1155 for (unsigned i = 0; i != 8; i += 2)
1156 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1157 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1158 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1159 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
1165 /// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
1166 /// VPKUDUM instruction, AND the VPKUDUM instruction exists for the
1167 /// current subtarget.
1169 /// The ShuffleKind distinguishes between big-endian operations with
1170 /// two different inputs (0), either-endian operations with two identical
1171 /// inputs (1), and little-endian operations with two different inputs (2).
1172 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1173 bool PPC::isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1174 SelectionDAG &DAG) {
1175 const PPCSubtarget& Subtarget =
1176 static_cast<const PPCSubtarget&>(DAG.getSubtarget());
1177 if (!Subtarget.hasP8Vector())
1180 bool IsLE = DAG.getDataLayout().isLittleEndian();
1181 if (ShuffleKind == 0) {
1184 for (unsigned i = 0; i != 16; i += 4)
1185 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+4) ||
1186 !isConstantOrUndef(N->getMaskElt(i+1), i*2+5) ||
1187 !isConstantOrUndef(N->getMaskElt(i+2), i*2+6) ||
1188 !isConstantOrUndef(N->getMaskElt(i+3), i*2+7))
1190 } else if (ShuffleKind == 2) {
1193 for (unsigned i = 0; i != 16; i += 4)
1194 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1195 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1) ||
1196 !isConstantOrUndef(N->getMaskElt(i+2), i*2+2) ||
1197 !isConstantOrUndef(N->getMaskElt(i+3), i*2+3))
1199 } else if (ShuffleKind == 1) {
1200 unsigned j = IsLE ? 0 : 4;
1201 for (unsigned i = 0; i != 8; i += 4)
1202 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1203 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1204 !isConstantOrUndef(N->getMaskElt(i+2), i*2+j+2) ||
1205 !isConstantOrUndef(N->getMaskElt(i+3), i*2+j+3) ||
1206 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1207 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1) ||
1208 !isConstantOrUndef(N->getMaskElt(i+10), i*2+j+2) ||
1209 !isConstantOrUndef(N->getMaskElt(i+11), i*2+j+3))
1215 /// isVMerge - Common function, used to match vmrg* shuffles.
1217 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
1218 unsigned LHSStart, unsigned RHSStart) {
1219 if (N->getValueType(0) != MVT::v16i8)
1221 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
1222 "Unsupported merge size!");
1224 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
1225 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
1226 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
1227 LHSStart+j+i*UnitSize) ||
1228 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
1229 RHSStart+j+i*UnitSize))
1235 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
1236 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
1237 /// The ShuffleKind distinguishes between big-endian merges with two
1238 /// different inputs (0), either-endian merges with two identical inputs (1),
1239 /// and little-endian merges with two different inputs (2). For the latter,
1240 /// the input operands are swapped (see PPCInstrAltivec.td).
1241 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1242 unsigned ShuffleKind, SelectionDAG &DAG) {
1243 if (DAG.getDataLayout().isLittleEndian()) {
1244 if (ShuffleKind == 1) // unary
1245 return isVMerge(N, UnitSize, 0, 0);
1246 else if (ShuffleKind == 2) // swapped
1247 return isVMerge(N, UnitSize, 0, 16);
1251 if (ShuffleKind == 1) // unary
1252 return isVMerge(N, UnitSize, 8, 8);
1253 else if (ShuffleKind == 0) // normal
1254 return isVMerge(N, UnitSize, 8, 24);
1260 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
1261 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
1262 /// The ShuffleKind distinguishes between big-endian merges with two
1263 /// different inputs (0), either-endian merges with two identical inputs (1),
1264 /// and little-endian merges with two different inputs (2). For the latter,
1265 /// the input operands are swapped (see PPCInstrAltivec.td).
1266 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1267 unsigned ShuffleKind, SelectionDAG &DAG) {
1268 if (DAG.getDataLayout().isLittleEndian()) {
1269 if (ShuffleKind == 1) // unary
1270 return isVMerge(N, UnitSize, 8, 8);
1271 else if (ShuffleKind == 2) // swapped
1272 return isVMerge(N, UnitSize, 8, 24);
1276 if (ShuffleKind == 1) // unary
1277 return isVMerge(N, UnitSize, 0, 0);
1278 else if (ShuffleKind == 0) // normal
1279 return isVMerge(N, UnitSize, 0, 16);
1286 * \brief Common function used to match vmrgew and vmrgow shuffles
1288 * The indexOffset determines whether to look for even or odd words in
1289 * the shuffle mask. This is based on the of the endianness of the target
1292 * - Use offset of 0 to check for odd elements
1293 * - Use offset of 4 to check for even elements
1295 * - Use offset of 0 to check for even elements
1296 * - Use offset of 4 to check for odd elements
1297 * A detailed description of the vector element ordering for little endian and
1298 * big endian can be found at
1299 * http://www.ibm.com/developerworks/library/l-ibm-xl-c-cpp-compiler/index.html
1300 * Targeting your applications - what little endian and big endian IBM XL C/C++
1301 * compiler differences mean to you
1303 * The mask to the shuffle vector instruction specifies the indices of the
1304 * elements from the two input vectors to place in the result. The elements are
1305 * numbered in array-access order, starting with the first vector. These vectors
1306 * are always of type v16i8, thus each vector will contain 16 elements of size
1307 * 8. More info on the shuffle vector can be found in the
1308 * http://llvm.org/docs/LangRef.html#shufflevector-instruction
1309 * Language Reference.
1311 * The RHSStartValue indicates whether the same input vectors are used (unary)
1312 * or two different input vectors are used, based on the following:
1313 * - If the instruction uses the same vector for both inputs, the range of the
1314 * indices will be 0 to 15. In this case, the RHSStart value passed should
1316 * - If the instruction has two different vectors then the range of the
1317 * indices will be 0 to 31. In this case, the RHSStart value passed should
1318 * be 16 (indices 0-15 specify elements in the first vector while indices 16
1319 * to 31 specify elements in the second vector).
1321 * \param[in] N The shuffle vector SD Node to analyze
1322 * \param[in] IndexOffset Specifies whether to look for even or odd elements
1323 * \param[in] RHSStartValue Specifies the starting index for the righthand input
1324 * vector to the shuffle_vector instruction
1325 * \return true iff this shuffle vector represents an even or odd word merge
1327 static bool isVMerge(ShuffleVectorSDNode *N, unsigned IndexOffset,
1328 unsigned RHSStartValue) {
1329 if (N->getValueType(0) != MVT::v16i8)
1332 for (unsigned i = 0; i < 2; ++i)
1333 for (unsigned j = 0; j < 4; ++j)
1334 if (!isConstantOrUndef(N->getMaskElt(i*4+j),
1335 i*RHSStartValue+j+IndexOffset) ||
1336 !isConstantOrUndef(N->getMaskElt(i*4+j+8),
1337 i*RHSStartValue+j+IndexOffset+8))
1343 * \brief Determine if the specified shuffle mask is suitable for the vmrgew or
1344 * vmrgow instructions.
1346 * \param[in] N The shuffle vector SD Node to analyze
1347 * \param[in] CheckEven Check for an even merge (true) or an odd merge (false)
1348 * \param[in] ShuffleKind Identify the type of merge:
1349 * - 0 = big-endian merge with two different inputs;
1350 * - 1 = either-endian merge with two identical inputs;
1351 * - 2 = little-endian merge with two different inputs (inputs are swapped for
1352 * little-endian merges).
1353 * \param[in] DAG The current SelectionDAG
1354 * \return true iff this shuffle mask
1356 bool PPC::isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven,
1357 unsigned ShuffleKind, SelectionDAG &DAG) {
1358 if (DAG.getDataLayout().isLittleEndian()) {
1359 unsigned indexOffset = CheckEven ? 4 : 0;
1360 if (ShuffleKind == 1) // Unary
1361 return isVMerge(N, indexOffset, 0);
1362 else if (ShuffleKind == 2) // swapped
1363 return isVMerge(N, indexOffset, 16);
1368 unsigned indexOffset = CheckEven ? 0 : 4;
1369 if (ShuffleKind == 1) // Unary
1370 return isVMerge(N, indexOffset, 0);
1371 else if (ShuffleKind == 0) // Normal
1372 return isVMerge(N, indexOffset, 16);
1379 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
1380 /// amount, otherwise return -1.
1381 /// The ShuffleKind distinguishes between big-endian operations with two
1382 /// different inputs (0), either-endian operations with two identical inputs
1383 /// (1), and little-endian operations with two different inputs (2). For the
1384 /// latter, the input operands are swapped (see PPCInstrAltivec.td).
1385 int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
1386 SelectionDAG &DAG) {
1387 if (N->getValueType(0) != MVT::v16i8)
1390 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1392 // Find the first non-undef value in the shuffle mask.
1394 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
1397 if (i == 16) return -1; // all undef.
1399 // Otherwise, check to see if the rest of the elements are consecutively
1400 // numbered from this value.
1401 unsigned ShiftAmt = SVOp->getMaskElt(i);
1402 if (ShiftAmt < i) return -1;
1405 bool isLE = DAG.getDataLayout().isLittleEndian();
1407 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
1408 // Check the rest of the elements to see if they are consecutive.
1409 for (++i; i != 16; ++i)
1410 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1412 } else if (ShuffleKind == 1) {
1413 // Check the rest of the elements to see if they are consecutive.
1414 for (++i; i != 16; ++i)
1415 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1421 ShiftAmt = 16 - ShiftAmt;
1426 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1427 /// specifies a splat of a single element that is suitable for input to
1428 /// VSPLTB/VSPLTH/VSPLTW.
1429 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1430 assert(N->getValueType(0) == MVT::v16i8 &&
1431 (EltSize == 1 || EltSize == 2 || EltSize == 4));
1433 // This is a splat operation if each element of the permute is the same, and
1434 // if the value doesn't reference the second vector.
1435 unsigned ElementBase = N->getMaskElt(0);
1437 // FIXME: Handle UNDEF elements too!
1438 if (ElementBase >= 16)
1441 // Check that the indices are consecutive, in the case of a multi-byte element
1442 // splatted with a v16i8 mask.
1443 for (unsigned i = 1; i != EltSize; ++i)
1444 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1447 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1448 if (N->getMaskElt(i) < 0) continue;
1449 for (unsigned j = 0; j != EltSize; ++j)
1450 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1456 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1457 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1458 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1459 SelectionDAG &DAG) {
1460 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1461 assert(isSplatShuffleMask(SVOp, EltSize));
1462 if (DAG.getDataLayout().isLittleEndian())
1463 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1465 return SVOp->getMaskElt(0) / EltSize;
1468 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1469 /// by using a vspltis[bhw] instruction of the specified element size, return
1470 /// the constant being splatted. The ByteSize field indicates the number of
1471 /// bytes of each element [124] -> [bhw].
1472 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1473 SDValue OpVal(nullptr, 0);
1475 // If ByteSize of the splat is bigger than the element size of the
1476 // build_vector, then we have a case where we are checking for a splat where
1477 // multiple elements of the buildvector are folded together into a single
1478 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1479 unsigned EltSize = 16/N->getNumOperands();
1480 if (EltSize < ByteSize) {
1481 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1482 SDValue UniquedVals[4];
1483 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1485 // See if all of the elements in the buildvector agree across.
1486 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1487 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1488 // If the element isn't a constant, bail fully out.
1489 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1492 if (!UniquedVals[i&(Multiple-1)].getNode())
1493 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1494 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1495 return SDValue(); // no match.
1498 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1499 // either constant or undef values that are identical for each chunk. See
1500 // if these chunks can form into a larger vspltis*.
1502 // Check to see if all of the leading entries are either 0 or -1. If
1503 // neither, then this won't fit into the immediate field.
1504 bool LeadingZero = true;
1505 bool LeadingOnes = true;
1506 for (unsigned i = 0; i != Multiple-1; ++i) {
1507 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1509 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
1510 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
1512 // Finally, check the least significant entry.
1514 if (!UniquedVals[Multiple-1].getNode())
1515 return DAG.getTargetConstant(0, SDLoc(N), MVT::i32); // 0,0,0,undef
1516 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1517 if (Val < 16) // 0,0,0,4 -> vspltisw(4)
1518 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
1521 if (!UniquedVals[Multiple-1].getNode())
1522 return DAG.getTargetConstant(~0U, SDLoc(N), MVT::i32); // -1,-1,-1,undef
1523 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1524 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1525 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
1531 // Check to see if this buildvec has a single non-undef value in its elements.
1532 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1533 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1534 if (!OpVal.getNode())
1535 OpVal = N->getOperand(i);
1536 else if (OpVal != N->getOperand(i))
1540 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1542 unsigned ValSizeInBytes = EltSize;
1544 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1545 Value = CN->getZExtValue();
1546 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1547 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1548 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1551 // If the splat value is larger than the element value, then we can never do
1552 // this splat. The only case that we could fit the replicated bits into our
1553 // immediate field for would be zero, and we prefer to use vxor for it.
1554 if (ValSizeInBytes < ByteSize) return SDValue();
1556 // If the element value is larger than the splat value, check if it consists
1557 // of a repeated bit pattern of size ByteSize.
1558 if (!APInt(ValSizeInBytes * 8, Value).isSplat(ByteSize * 8))
1561 // Properly sign extend the value.
1562 int MaskVal = SignExtend32(Value, ByteSize * 8);
1564 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1565 if (MaskVal == 0) return SDValue();
1567 // Finally, if this value fits in a 5 bit sext field, return it
1568 if (SignExtend32<5>(MaskVal) == MaskVal)
1569 return DAG.getTargetConstant(MaskVal, SDLoc(N), MVT::i32);
1573 /// isQVALIGNIShuffleMask - If this is a qvaligni shuffle mask, return the shift
1574 /// amount, otherwise return -1.
1575 int PPC::isQVALIGNIShuffleMask(SDNode *N) {
1576 EVT VT = N->getValueType(0);
1577 if (VT != MVT::v4f64 && VT != MVT::v4f32 && VT != MVT::v4i1)
1580 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1582 // Find the first non-undef value in the shuffle mask.
1584 for (i = 0; i != 4 && SVOp->getMaskElt(i) < 0; ++i)
1587 if (i == 4) return -1; // all undef.
1589 // Otherwise, check to see if the rest of the elements are consecutively
1590 // numbered from this value.
1591 unsigned ShiftAmt = SVOp->getMaskElt(i);
1592 if (ShiftAmt < i) return -1;
1595 // Check the rest of the elements to see if they are consecutive.
1596 for (++i; i != 4; ++i)
1597 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1603 //===----------------------------------------------------------------------===//
1604 // Addressing Mode Selection
1605 //===----------------------------------------------------------------------===//
1607 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1608 /// or 64-bit immediate, and if the value can be accurately represented as a
1609 /// sign extension from a 16-bit value. If so, this returns true and the
1611 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1612 if (!isa<ConstantSDNode>(N))
1615 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1616 if (N->getValueType(0) == MVT::i32)
1617 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1619 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1621 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1622 return isIntS16Immediate(Op.getNode(), Imm);
1626 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1627 /// can be represented as an indexed [r+r] operation. Returns false if it
1628 /// can be more efficiently represented with [r+imm].
1629 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1631 SelectionDAG &DAG) const {
1633 if (N.getOpcode() == ISD::ADD) {
1634 if (isIntS16Immediate(N.getOperand(1), imm))
1635 return false; // r+i
1636 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1637 return false; // r+i
1639 Base = N.getOperand(0);
1640 Index = N.getOperand(1);
1642 } else if (N.getOpcode() == ISD::OR) {
1643 if (isIntS16Immediate(N.getOperand(1), imm))
1644 return false; // r+i can fold it if we can.
1646 // If this is an or of disjoint bitfields, we can codegen this as an add
1647 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1649 APInt LHSKnownZero, LHSKnownOne;
1650 APInt RHSKnownZero, RHSKnownOne;
1651 DAG.computeKnownBits(N.getOperand(0),
1652 LHSKnownZero, LHSKnownOne);
1654 if (LHSKnownZero.getBoolValue()) {
1655 DAG.computeKnownBits(N.getOperand(1),
1656 RHSKnownZero, RHSKnownOne);
1657 // If all of the bits are known zero on the LHS or RHS, the add won't
1659 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1660 Base = N.getOperand(0);
1661 Index = N.getOperand(1);
1670 // If we happen to be doing an i64 load or store into a stack slot that has
1671 // less than a 4-byte alignment, then the frame-index elimination may need to
1672 // use an indexed load or store instruction (because the offset may not be a
1673 // multiple of 4). The extra register needed to hold the offset comes from the
1674 // register scavenger, and it is possible that the scavenger will need to use
1675 // an emergency spill slot. As a result, we need to make sure that a spill slot
1676 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1678 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1679 // FIXME: This does not handle the LWA case.
1683 // NOTE: We'll exclude negative FIs here, which come from argument
1684 // lowering, because there are no known test cases triggering this problem
1685 // using packed structures (or similar). We can remove this exclusion if
1686 // we find such a test case. The reason why this is so test-case driven is
1687 // because this entire 'fixup' is only to prevent crashes (from the
1688 // register scavenger) on not-really-valid inputs. For example, if we have:
1690 // %b = bitcast i1* %a to i64*
1691 // store i64* a, i64 b
1692 // then the store should really be marked as 'align 1', but is not. If it
1693 // were marked as 'align 1' then the indexed form would have been
1694 // instruction-selected initially, and the problem this 'fixup' is preventing
1695 // won't happen regardless.
1699 MachineFunction &MF = DAG.getMachineFunction();
1700 MachineFrameInfo *MFI = MF.getFrameInfo();
1702 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1706 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1707 FuncInfo->setHasNonRISpills();
1710 /// Returns true if the address N can be represented by a base register plus
1711 /// a signed 16-bit displacement [r+imm], and if it is not better
1712 /// represented as reg+reg. If Aligned is true, only accept displacements
1713 /// suitable for STD and friends, i.e. multiples of 4.
1714 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1717 bool Aligned) const {
1718 // FIXME dl should come from parent load or store, not from address
1720 // If this can be more profitably realized as r+r, fail.
1721 if (SelectAddressRegReg(N, Disp, Base, DAG))
1724 if (N.getOpcode() == ISD::ADD) {
1726 if (isIntS16Immediate(N.getOperand(1), imm) &&
1727 (!Aligned || (imm & 3) == 0)) {
1728 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
1729 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1730 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1731 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1733 Base = N.getOperand(0);
1735 return true; // [r+i]
1736 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1737 // Match LOAD (ADD (X, Lo(G))).
1738 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1739 && "Cannot handle constant offsets yet!");
1740 Disp = N.getOperand(1).getOperand(0); // The global address.
1741 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1742 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1743 Disp.getOpcode() == ISD::TargetConstantPool ||
1744 Disp.getOpcode() == ISD::TargetJumpTable);
1745 Base = N.getOperand(0);
1746 return true; // [&g+r]
1748 } else if (N.getOpcode() == ISD::OR) {
1750 if (isIntS16Immediate(N.getOperand(1), imm) &&
1751 (!Aligned || (imm & 3) == 0)) {
1752 // If this is an or of disjoint bitfields, we can codegen this as an add
1753 // (for better address arithmetic) if the LHS and RHS of the OR are
1754 // provably disjoint.
1755 APInt LHSKnownZero, LHSKnownOne;
1756 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1758 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1759 // If all of the bits are known zero on the LHS or RHS, the add won't
1761 if (FrameIndexSDNode *FI =
1762 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1763 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1764 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1766 Base = N.getOperand(0);
1768 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
1772 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1773 // Loading from a constant address.
1775 // If this address fits entirely in a 16-bit sext immediate field, codegen
1778 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1779 Disp = DAG.getTargetConstant(Imm, dl, CN->getValueType(0));
1780 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1781 CN->getValueType(0));
1785 // Handle 32-bit sext immediates with LIS + addr mode.
1786 if ((CN->getValueType(0) == MVT::i32 ||
1787 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1788 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1789 int Addr = (int)CN->getZExtValue();
1791 // Otherwise, break this down into an LIS + disp.
1792 Disp = DAG.getTargetConstant((short)Addr, dl, MVT::i32);
1794 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, dl,
1796 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1797 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1802 Disp = DAG.getTargetConstant(0, dl, getPointerTy(DAG.getDataLayout()));
1803 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1804 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1805 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1808 return true; // [r+0]
1811 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1812 /// represented as an indexed [r+r] operation.
1813 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1815 SelectionDAG &DAG) const {
1816 // Check to see if we can easily represent this as an [r+r] address. This
1817 // will fail if it thinks that the address is more profitably represented as
1818 // reg+imm, e.g. where imm = 0.
1819 if (SelectAddressRegReg(N, Base, Index, DAG))
1822 // If the operand is an addition, always emit this as [r+r], since this is
1823 // better (for code size, and execution, as the memop does the add for free)
1824 // than emitting an explicit add.
1825 if (N.getOpcode() == ISD::ADD) {
1826 Base = N.getOperand(0);
1827 Index = N.getOperand(1);
1831 // Otherwise, do it the hard way, using R0 as the base register.
1832 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1838 /// getPreIndexedAddressParts - returns true by value, base pointer and
1839 /// offset pointer and addressing mode by reference if the node's address
1840 /// can be legally represented as pre-indexed load / store address.
1841 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1843 ISD::MemIndexedMode &AM,
1844 SelectionDAG &DAG) const {
1845 if (DisablePPCPreinc) return false;
1851 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1852 Ptr = LD->getBasePtr();
1853 VT = LD->getMemoryVT();
1854 Alignment = LD->getAlignment();
1855 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1856 Ptr = ST->getBasePtr();
1857 VT = ST->getMemoryVT();
1858 Alignment = ST->getAlignment();
1863 // PowerPC doesn't have preinc load/store instructions for vectors (except
1864 // for QPX, which does have preinc r+r forms).
1865 if (VT.isVector()) {
1866 if (!Subtarget.hasQPX() || (VT != MVT::v4f64 && VT != MVT::v4f32)) {
1868 } else if (SelectAddressRegRegOnly(Ptr, Offset, Base, DAG)) {
1874 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1876 // Common code will reject creating a pre-inc form if the base pointer
1877 // is a frame index, or if N is a store and the base pointer is either
1878 // the same as or a predecessor of the value being stored. Check for
1879 // those situations here, and try with swapped Base/Offset instead.
1882 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1885 SDValue Val = cast<StoreSDNode>(N)->getValue();
1886 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1891 std::swap(Base, Offset);
1897 // LDU/STU can only handle immediates that are a multiple of 4.
1898 if (VT != MVT::i64) {
1899 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1902 // LDU/STU need an address with at least 4-byte alignment.
1906 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1910 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1911 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1912 // sext i32 to i64 when addr mode is r+i.
1913 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1914 LD->getExtensionType() == ISD::SEXTLOAD &&
1915 isa<ConstantSDNode>(Offset))
1923 //===----------------------------------------------------------------------===//
1924 // LowerOperation implementation
1925 //===----------------------------------------------------------------------===//
1927 /// GetLabelAccessInfo - Return true if we should reference labels using a
1928 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1929 static bool GetLabelAccessInfo(const TargetMachine &TM,
1930 const PPCSubtarget &Subtarget,
1931 unsigned &HiOpFlags, unsigned &LoOpFlags,
1932 const GlobalValue *GV = nullptr) {
1933 HiOpFlags = PPCII::MO_HA;
1934 LoOpFlags = PPCII::MO_LO;
1936 // Don't use the pic base if not in PIC relocation model.
1937 bool isPIC = TM.getRelocationModel() == Reloc::PIC_;
1940 HiOpFlags |= PPCII::MO_PIC_FLAG;
1941 LoOpFlags |= PPCII::MO_PIC_FLAG;
1944 // If this is a reference to a global value that requires a non-lazy-ptr, make
1945 // sure that instruction lowering adds it.
1946 if (GV && Subtarget.hasLazyResolverStub(GV)) {
1947 HiOpFlags |= PPCII::MO_NLP_FLAG;
1948 LoOpFlags |= PPCII::MO_NLP_FLAG;
1950 if (GV->hasHiddenVisibility()) {
1951 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1952 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1959 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1960 SelectionDAG &DAG) {
1962 EVT PtrVT = HiPart.getValueType();
1963 SDValue Zero = DAG.getConstant(0, DL, PtrVT);
1965 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1966 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1968 // With PIC, the first instruction is actually "GR+hi(&G)".
1970 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1971 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1973 // Generate non-pic code that has direct accesses to the constant pool.
1974 // The address of the global is just (hi(&g)+lo(&g)).
1975 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1978 static void setUsesTOCBasePtr(MachineFunction &MF) {
1979 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1980 FuncInfo->setUsesTOCBasePtr();
1983 static void setUsesTOCBasePtr(SelectionDAG &DAG) {
1984 setUsesTOCBasePtr(DAG.getMachineFunction());
1987 static SDValue getTOCEntry(SelectionDAG &DAG, SDLoc dl, bool Is64Bit,
1989 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1990 SDValue Reg = Is64Bit ? DAG.getRegister(PPC::X2, VT) :
1991 DAG.getNode(PPCISD::GlobalBaseReg, dl, VT);
1993 SDValue Ops[] = { GA, Reg };
1994 return DAG.getMemIntrinsicNode(PPCISD::TOC_ENTRY, dl,
1995 DAG.getVTList(VT, MVT::Other), Ops, VT,
1996 MachinePointerInfo::getGOT(), 0, false, true,
2000 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
2001 SelectionDAG &DAG) const {
2002 EVT PtrVT = Op.getValueType();
2003 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2004 const Constant *C = CP->getConstVal();
2006 // 64-bit SVR4 ABI code is always position-independent.
2007 // The actual address of the GlobalValue is stored in the TOC.
2008 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2009 setUsesTOCBasePtr(DAG);
2010 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
2011 return getTOCEntry(DAG, SDLoc(CP), true, GA);
2014 unsigned MOHiFlag, MOLoFlag;
2016 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
2018 if (isPIC && Subtarget.isSVR4ABI()) {
2019 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
2020 PPCII::MO_PIC_FLAG);
2021 return getTOCEntry(DAG, SDLoc(CP), false, GA);
2025 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
2027 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
2028 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
2031 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
2032 EVT PtrVT = Op.getValueType();
2033 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
2035 // 64-bit SVR4 ABI code is always position-independent.
2036 // The actual address of the GlobalValue is stored in the TOC.
2037 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2038 setUsesTOCBasePtr(DAG);
2039 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
2040 return getTOCEntry(DAG, SDLoc(JT), true, GA);
2043 unsigned MOHiFlag, MOLoFlag;
2045 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
2047 if (isPIC && Subtarget.isSVR4ABI()) {
2048 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
2049 PPCII::MO_PIC_FLAG);
2050 return getTOCEntry(DAG, SDLoc(GA), false, GA);
2053 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
2054 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
2055 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
2058 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
2059 SelectionDAG &DAG) const {
2060 EVT PtrVT = Op.getValueType();
2061 BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
2062 const BlockAddress *BA = BASDN->getBlockAddress();
2064 // 64-bit SVR4 ABI code is always position-independent.
2065 // The actual BlockAddress is stored in the TOC.
2066 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2067 setUsesTOCBasePtr(DAG);
2068 SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
2069 return getTOCEntry(DAG, SDLoc(BASDN), true, GA);
2072 unsigned MOHiFlag, MOLoFlag;
2074 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
2075 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
2076 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
2077 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
2080 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
2081 SelectionDAG &DAG) const {
2083 // FIXME: TLS addresses currently use medium model code sequences,
2084 // which is the most useful form. Eventually support for small and
2085 // large models could be added if users need it, at the cost of
2086 // additional complexity.
2087 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2088 if (DAG.getTarget().Options.EmulatedTLS)
2089 return LowerToTLSEmulatedModel(GA, DAG);
2092 const GlobalValue *GV = GA->getGlobal();
2093 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2094 bool is64bit = Subtarget.isPPC64();
2095 const Module *M = DAG.getMachineFunction().getFunction()->getParent();
2096 PICLevel::Level picLevel = M->getPICLevel();
2098 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
2100 if (Model == TLSModel::LocalExec) {
2101 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2102 PPCII::MO_TPREL_HA);
2103 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2104 PPCII::MO_TPREL_LO);
2105 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
2106 is64bit ? MVT::i64 : MVT::i32);
2107 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
2108 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
2111 if (Model == TLSModel::InitialExec) {
2112 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2113 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2117 setUsesTOCBasePtr(DAG);
2118 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2119 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
2120 PtrVT, GOTReg, TGA);
2122 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
2123 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
2124 PtrVT, TGA, GOTPtr);
2125 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
2128 if (Model == TLSModel::GeneralDynamic) {
2129 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2132 setUsesTOCBasePtr(DAG);
2133 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2134 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
2137 if (picLevel == PICLevel::Small)
2138 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
2140 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
2142 return DAG.getNode(PPCISD::ADDI_TLSGD_L_ADDR, dl, PtrVT,
2146 if (Model == TLSModel::LocalDynamic) {
2147 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2150 setUsesTOCBasePtr(DAG);
2151 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2152 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
2155 if (picLevel == PICLevel::Small)
2156 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
2158 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
2160 SDValue TLSAddr = DAG.getNode(PPCISD::ADDI_TLSLD_L_ADDR, dl,
2161 PtrVT, GOTPtr, TGA, TGA);
2162 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl,
2163 PtrVT, TLSAddr, TGA);
2164 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
2167 llvm_unreachable("Unknown TLS model!");
2170 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
2171 SelectionDAG &DAG) const {
2172 EVT PtrVT = Op.getValueType();
2173 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
2175 const GlobalValue *GV = GSDN->getGlobal();
2177 // 64-bit SVR4 ABI code is always position-independent.
2178 // The actual address of the GlobalValue is stored in the TOC.
2179 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2180 setUsesTOCBasePtr(DAG);
2181 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
2182 return getTOCEntry(DAG, DL, true, GA);
2185 unsigned MOHiFlag, MOLoFlag;
2187 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag, GV);
2189 if (isPIC && Subtarget.isSVR4ABI()) {
2190 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
2192 PPCII::MO_PIC_FLAG);
2193 return getTOCEntry(DAG, DL, false, GA);
2197 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
2199 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
2201 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
2203 // If the global reference is actually to a non-lazy-pointer, we have to do an
2204 // extra load to get the address of the global.
2205 if (MOHiFlag & PPCII::MO_NLP_FLAG)
2206 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
2207 false, false, false, 0);
2211 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
2212 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2215 if (Op.getValueType() == MVT::v2i64) {
2216 // When the operands themselves are v2i64 values, we need to do something
2217 // special because VSX has no underlying comparison operations for these.
2218 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
2219 // Equality can be handled by casting to the legal type for Altivec
2220 // comparisons, everything else needs to be expanded.
2221 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
2222 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
2223 DAG.getSetCC(dl, MVT::v4i32,
2224 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
2225 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
2232 // We handle most of these in the usual way.
2236 // If we're comparing for equality to zero, expose the fact that this is
2237 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
2238 // fold the new nodes.
2239 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
2240 if (C->isNullValue() && CC == ISD::SETEQ) {
2241 EVT VT = Op.getOperand(0).getValueType();
2242 SDValue Zext = Op.getOperand(0);
2243 if (VT.bitsLT(MVT::i32)) {
2245 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
2247 unsigned Log2b = Log2_32(VT.getSizeInBits());
2248 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
2249 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
2250 DAG.getConstant(Log2b, dl, MVT::i32));
2251 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
2253 // Leave comparisons against 0 and -1 alone for now, since they're usually
2254 // optimized. FIXME: revisit this when we can custom lower all setcc
2256 if (C->isAllOnesValue() || C->isNullValue())
2260 // If we have an integer seteq/setne, turn it into a compare against zero
2261 // by xor'ing the rhs with the lhs, which is faster than setting a
2262 // condition register, reading it back out, and masking the correct bit. The
2263 // normal approach here uses sub to do this instead of xor. Using xor exposes
2264 // the result to other bit-twiddling opportunities.
2265 EVT LHSVT = Op.getOperand(0).getValueType();
2266 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
2267 EVT VT = Op.getValueType();
2268 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
2270 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, dl, LHSVT), CC);
2275 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
2276 const PPCSubtarget &Subtarget) const {
2277 SDNode *Node = Op.getNode();
2278 EVT VT = Node->getValueType(0);
2279 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
2280 SDValue InChain = Node->getOperand(0);
2281 SDValue VAListPtr = Node->getOperand(1);
2282 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2285 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
2288 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
2289 VAListPtr, MachinePointerInfo(SV), MVT::i8,
2290 false, false, false, 0);
2291 InChain = GprIndex.getValue(1);
2293 if (VT == MVT::i64) {
2294 // Check if GprIndex is even
2295 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
2296 DAG.getConstant(1, dl, MVT::i32));
2297 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
2298 DAG.getConstant(0, dl, MVT::i32), ISD::SETNE);
2299 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
2300 DAG.getConstant(1, dl, MVT::i32));
2301 // Align GprIndex to be even if it isn't
2302 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
2306 // fpr index is 1 byte after gpr
2307 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2308 DAG.getConstant(1, dl, MVT::i32));
2311 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
2312 FprPtr, MachinePointerInfo(SV), MVT::i8,
2313 false, false, false, 0);
2314 InChain = FprIndex.getValue(1);
2316 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2317 DAG.getConstant(8, dl, MVT::i32));
2319 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2320 DAG.getConstant(4, dl, MVT::i32));
2323 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
2324 MachinePointerInfo(), false, false,
2326 InChain = OverflowArea.getValue(1);
2328 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
2329 MachinePointerInfo(), false, false,
2331 InChain = RegSaveArea.getValue(1);
2333 // select overflow_area if index > 8
2334 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
2335 DAG.getConstant(8, dl, MVT::i32), ISD::SETLT);
2337 // adjustment constant gpr_index * 4/8
2338 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
2339 VT.isInteger() ? GprIndex : FprIndex,
2340 DAG.getConstant(VT.isInteger() ? 4 : 8, dl,
2343 // OurReg = RegSaveArea + RegConstant
2344 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
2347 // Floating types are 32 bytes into RegSaveArea
2348 if (VT.isFloatingPoint())
2349 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
2350 DAG.getConstant(32, dl, MVT::i32));
2352 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
2353 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
2354 VT.isInteger() ? GprIndex : FprIndex,
2355 DAG.getConstant(VT == MVT::i64 ? 2 : 1, dl,
2358 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
2359 VT.isInteger() ? VAListPtr : FprPtr,
2360 MachinePointerInfo(SV),
2361 MVT::i8, false, false, 0);
2363 // determine if we should load from reg_save_area or overflow_area
2364 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
2366 // increase overflow_area by 4/8 if gpr/fpr > 8
2367 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
2368 DAG.getConstant(VT.isInteger() ? 4 : 8,
2371 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
2374 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
2376 MachinePointerInfo(),
2377 MVT::i32, false, false, 0);
2379 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
2380 false, false, false, 0);
2383 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
2384 const PPCSubtarget &Subtarget) const {
2385 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
2387 // We have to copy the entire va_list struct:
2388 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
2389 return DAG.getMemcpy(Op.getOperand(0), Op,
2390 Op.getOperand(1), Op.getOperand(2),
2391 DAG.getConstant(12, SDLoc(Op), MVT::i32), 8, false, true,
2392 false, MachinePointerInfo(), MachinePointerInfo());
2395 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
2396 SelectionDAG &DAG) const {
2397 return Op.getOperand(0);
2400 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
2401 SelectionDAG &DAG) const {
2402 SDValue Chain = Op.getOperand(0);
2403 SDValue Trmp = Op.getOperand(1); // trampoline
2404 SDValue FPtr = Op.getOperand(2); // nested function
2405 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
2408 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
2409 bool isPPC64 = (PtrVT == MVT::i64);
2410 Type *IntPtrTy = DAG.getDataLayout().getIntPtrType(*DAG.getContext());
2412 TargetLowering::ArgListTy Args;
2413 TargetLowering::ArgListEntry Entry;
2415 Entry.Ty = IntPtrTy;
2416 Entry.Node = Trmp; Args.push_back(Entry);
2418 // TrampSize == (isPPC64 ? 48 : 40);
2419 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, dl,
2420 isPPC64 ? MVT::i64 : MVT::i32);
2421 Args.push_back(Entry);
2423 Entry.Node = FPtr; Args.push_back(Entry);
2424 Entry.Node = Nest; Args.push_back(Entry);
2426 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
2427 TargetLowering::CallLoweringInfo CLI(DAG);
2428 CLI.setDebugLoc(dl).setChain(Chain)
2429 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
2430 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
2431 std::move(Args), 0);
2433 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2434 return CallResult.second;
2437 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
2438 const PPCSubtarget &Subtarget) const {
2439 MachineFunction &MF = DAG.getMachineFunction();
2440 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2444 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
2445 // vastart just stores the address of the VarArgsFrameIndex slot into the
2446 // memory location argument.
2447 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
2448 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2449 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2450 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2451 MachinePointerInfo(SV),
2455 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
2456 // We suppose the given va_list is already allocated.
2459 // char gpr; /* index into the array of 8 GPRs
2460 // * stored in the register save area
2461 // * gpr=0 corresponds to r3,
2462 // * gpr=1 to r4, etc.
2464 // char fpr; /* index into the array of 8 FPRs
2465 // * stored in the register save area
2466 // * fpr=0 corresponds to f1,
2467 // * fpr=1 to f2, etc.
2469 // char *overflow_arg_area;
2470 // /* location on stack that holds
2471 // * the next overflow argument
2473 // char *reg_save_area;
2474 // /* where r3:r10 and f1:f8 (if saved)
2480 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), dl, MVT::i32);
2481 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), dl, MVT::i32);
2483 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
2485 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
2487 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2490 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2491 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, dl, PtrVT);
2493 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2494 SDValue ConstStackOffset = DAG.getConstant(StackOffset, dl, PtrVT);
2496 uint64_t FPROffset = 1;
2497 SDValue ConstFPROffset = DAG.getConstant(FPROffset, dl, PtrVT);
2499 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2501 // Store first byte : number of int regs
2502 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
2504 MachinePointerInfo(SV),
2505 MVT::i8, false, false, 0);
2506 uint64_t nextOffset = FPROffset;
2507 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2510 // Store second byte : number of float regs
2511 SDValue secondStore =
2512 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2513 MachinePointerInfo(SV, nextOffset), MVT::i8,
2515 nextOffset += StackOffset;
2516 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2518 // Store second word : arguments given on stack
2519 SDValue thirdStore =
2520 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2521 MachinePointerInfo(SV, nextOffset),
2523 nextOffset += FrameOffset;
2524 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2526 // Store third word : arguments given in registers
2527 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2528 MachinePointerInfo(SV, nextOffset),
2533 #include "PPCGenCallingConv.inc"
2535 // Function whose sole purpose is to kill compiler warnings
2536 // stemming from unused functions included from PPCGenCallingConv.inc.
2537 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2538 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2541 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2542 CCValAssign::LocInfo &LocInfo,
2543 ISD::ArgFlagsTy &ArgFlags,
2548 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2550 CCValAssign::LocInfo &LocInfo,
2551 ISD::ArgFlagsTy &ArgFlags,
2553 static const MCPhysReg ArgRegs[] = {
2554 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2555 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2557 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2559 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
2561 // Skip one register if the first unallocated register has an even register
2562 // number and there are still argument registers available which have not been
2563 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2564 // need to skip a register if RegNum is odd.
2565 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2566 State.AllocateReg(ArgRegs[RegNum]);
2569 // Always return false here, as this function only makes sure that the first
2570 // unallocated register has an odd register number and does not actually
2571 // allocate a register for the current argument.
2575 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2577 CCValAssign::LocInfo &LocInfo,
2578 ISD::ArgFlagsTy &ArgFlags,
2580 static const MCPhysReg ArgRegs[] = {
2581 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2585 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2587 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
2589 // If there is only one Floating-point register left we need to put both f64
2590 // values of a split ppc_fp128 value on the stack.
2591 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2592 State.AllocateReg(ArgRegs[RegNum]);
2595 // Always return false here, as this function only makes sure that the two f64
2596 // values a ppc_fp128 value is split into are both passed in registers or both
2597 // passed on the stack and does not actually allocate a register for the
2598 // current argument.
2602 /// FPR - The set of FP registers that should be allocated for arguments,
2604 static const MCPhysReg FPR[] = {PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5,
2605 PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10,
2606 PPC::F11, PPC::F12, PPC::F13};
2608 /// QFPR - The set of QPX registers that should be allocated for arguments.
2609 static const MCPhysReg QFPR[] = {
2610 PPC::QF1, PPC::QF2, PPC::QF3, PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7,
2611 PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11, PPC::QF12, PPC::QF13};
2613 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2615 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2616 unsigned PtrByteSize) {
2617 unsigned ArgSize = ArgVT.getStoreSize();
2618 if (Flags.isByVal())
2619 ArgSize = Flags.getByValSize();
2621 // Round up to multiples of the pointer size, except for array members,
2622 // which are always packed.
2623 if (!Flags.isInConsecutiveRegs())
2624 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2629 /// CalculateStackSlotAlignment - Calculates the alignment of this argument
2631 static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
2632 ISD::ArgFlagsTy Flags,
2633 unsigned PtrByteSize) {
2634 unsigned Align = PtrByteSize;
2636 // Altivec parameters are padded to a 16 byte boundary.
2637 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2638 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2639 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
2640 ArgVT == MVT::v1i128)
2642 // QPX vector types stored in double-precision are padded to a 32 byte
2644 else if (ArgVT == MVT::v4f64 || ArgVT == MVT::v4i1)
2647 // ByVal parameters are aligned as requested.
2648 if (Flags.isByVal()) {
2649 unsigned BVAlign = Flags.getByValAlign();
2650 if (BVAlign > PtrByteSize) {
2651 if (BVAlign % PtrByteSize != 0)
2653 "ByVal alignment is not a multiple of the pointer size");
2659 // Array members are always packed to their original alignment.
2660 if (Flags.isInConsecutiveRegs()) {
2661 // If the array member was split into multiple registers, the first
2662 // needs to be aligned to the size of the full type. (Except for
2663 // ppcf128, which is only aligned as its f64 components.)
2664 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
2665 Align = OrigVT.getStoreSize();
2667 Align = ArgVT.getStoreSize();
2673 /// CalculateStackSlotUsed - Return whether this argument will use its
2674 /// stack slot (instead of being passed in registers). ArgOffset,
2675 /// AvailableFPRs, and AvailableVRs must hold the current argument
2676 /// position, and will be updated to account for this argument.
2677 static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT,
2678 ISD::ArgFlagsTy Flags,
2679 unsigned PtrByteSize,
2680 unsigned LinkageSize,
2681 unsigned ParamAreaSize,
2682 unsigned &ArgOffset,
2683 unsigned &AvailableFPRs,
2684 unsigned &AvailableVRs, bool HasQPX) {
2685 bool UseMemory = false;
2687 // Respect alignment of argument on the stack.
2689 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
2690 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2691 // If there's no space left in the argument save area, we must
2692 // use memory (this check also catches zero-sized arguments).
2693 if (ArgOffset >= LinkageSize + ParamAreaSize)
2696 // Allocate argument on the stack.
2697 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2698 if (Flags.isInConsecutiveRegsLast())
2699 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2700 // If we overran the argument save area, we must use memory
2701 // (this check catches arguments passed partially in memory)
2702 if (ArgOffset > LinkageSize + ParamAreaSize)
2705 // However, if the argument is actually passed in an FPR or a VR,
2706 // we don't use memory after all.
2707 if (!Flags.isByVal()) {
2708 if (ArgVT == MVT::f32 || ArgVT == MVT::f64 ||
2709 // QPX registers overlap with the scalar FP registers.
2710 (HasQPX && (ArgVT == MVT::v4f32 ||
2711 ArgVT == MVT::v4f64 ||
2712 ArgVT == MVT::v4i1)))
2713 if (AvailableFPRs > 0) {
2717 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2718 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2719 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
2720 ArgVT == MVT::v1i128)
2721 if (AvailableVRs > 0) {
2730 /// EnsureStackAlignment - Round stack frame size up from NumBytes to
2731 /// ensure minimum alignment required for target.
2732 static unsigned EnsureStackAlignment(const PPCFrameLowering *Lowering,
2733 unsigned NumBytes) {
2734 unsigned TargetAlign = Lowering->getStackAlignment();
2735 unsigned AlignMask = TargetAlign - 1;
2736 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2741 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
2742 CallingConv::ID CallConv, bool isVarArg,
2743 const SmallVectorImpl<ISD::InputArg>
2745 SDLoc dl, SelectionDAG &DAG,
2746 SmallVectorImpl<SDValue> &InVals)
2748 if (Subtarget.isSVR4ABI()) {
2749 if (Subtarget.isPPC64())
2750 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2753 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2756 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2762 PPCTargetLowering::LowerFormalArguments_32SVR4(
2764 CallingConv::ID CallConv, bool isVarArg,
2765 const SmallVectorImpl<ISD::InputArg>
2767 SDLoc dl, SelectionDAG &DAG,
2768 SmallVectorImpl<SDValue> &InVals) const {
2770 // 32-bit SVR4 ABI Stack Frame Layout:
2771 // +-----------------------------------+
2772 // +--> | Back chain |
2773 // | +-----------------------------------+
2774 // | | Floating-point register save area |
2775 // | +-----------------------------------+
2776 // | | General register save area |
2777 // | +-----------------------------------+
2778 // | | CR save word |
2779 // | +-----------------------------------+
2780 // | | VRSAVE save word |
2781 // | +-----------------------------------+
2782 // | | Alignment padding |
2783 // | +-----------------------------------+
2784 // | | Vector register save area |
2785 // | +-----------------------------------+
2786 // | | Local variable space |
2787 // | +-----------------------------------+
2788 // | | Parameter list area |
2789 // | +-----------------------------------+
2790 // | | LR save word |
2791 // | +-----------------------------------+
2792 // SP--> +--- | Back chain |
2793 // +-----------------------------------+
2796 // System V Application Binary Interface PowerPC Processor Supplement
2797 // AltiVec Technology Programming Interface Manual
2799 MachineFunction &MF = DAG.getMachineFunction();
2800 MachineFrameInfo *MFI = MF.getFrameInfo();
2801 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2803 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
2804 // Potential tail calls could cause overwriting of argument stack slots.
2805 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2806 (CallConv == CallingConv::Fast));
2807 unsigned PtrByteSize = 4;
2809 // Assign locations to all of the incoming arguments.
2810 SmallVector<CCValAssign, 16> ArgLocs;
2811 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2814 // Reserve space for the linkage area on the stack.
2815 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
2816 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
2818 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2820 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2821 CCValAssign &VA = ArgLocs[i];
2823 // Arguments stored in registers.
2824 if (VA.isRegLoc()) {
2825 const TargetRegisterClass *RC;
2826 EVT ValVT = VA.getValVT();
2828 switch (ValVT.getSimpleVT().SimpleTy) {
2830 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2833 RC = &PPC::GPRCRegClass;
2836 if (Subtarget.hasP8Vector())
2837 RC = &PPC::VSSRCRegClass;
2839 RC = &PPC::F4RCRegClass;
2842 if (Subtarget.hasVSX())
2843 RC = &PPC::VSFRCRegClass;
2845 RC = &PPC::F8RCRegClass;
2850 RC = &PPC::VRRCRegClass;
2853 RC = Subtarget.hasQPX() ? &PPC::QSRCRegClass : &PPC::VRRCRegClass;
2857 RC = &PPC::VSHRCRegClass;
2860 RC = &PPC::QFRCRegClass;
2863 RC = &PPC::QBRCRegClass;
2867 // Transform the arguments stored in physical registers into virtual ones.
2868 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2869 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2870 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2872 if (ValVT == MVT::i1)
2873 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2875 InVals.push_back(ArgValue);
2877 // Argument stored in memory.
2878 assert(VA.isMemLoc());
2880 unsigned ArgSize = VA.getLocVT().getStoreSize();
2881 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2884 // Create load nodes to retrieve arguments from the stack.
2885 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2886 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2887 MachinePointerInfo(),
2888 false, false, false, 0));
2892 // Assign locations to all of the incoming aggregate by value arguments.
2893 // Aggregates passed by value are stored in the local variable space of the
2894 // caller's stack frame, right above the parameter list area.
2895 SmallVector<CCValAssign, 16> ByValArgLocs;
2896 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2897 ByValArgLocs, *DAG.getContext());
2899 // Reserve stack space for the allocations in CCInfo.
2900 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2902 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2904 // Area that is at least reserved in the caller of this function.
2905 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2906 MinReservedArea = std::max(MinReservedArea, LinkageSize);
2908 // Set the size that is at least reserved in caller of this function. Tail
2909 // call optimized function's reserved stack space needs to be aligned so that
2910 // taking the difference between two stack areas will result in an aligned
2913 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
2914 FuncInfo->setMinReservedArea(MinReservedArea);
2916 SmallVector<SDValue, 8> MemOps;
2918 // If the function takes variable number of arguments, make a frame index for
2919 // the start of the first vararg value... for expansion of llvm.va_start.
2921 static const MCPhysReg GPArgRegs[] = {
2922 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2923 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2925 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2927 static const MCPhysReg FPArgRegs[] = {
2928 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2931 unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2932 if (DisablePPCFloatInVariadic)
2935 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs));
2936 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs));
2938 // Make room for NumGPArgRegs and NumFPArgRegs.
2939 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2940 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8;
2942 FuncInfo->setVarArgsStackOffset(
2943 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2944 CCInfo.getNextStackOffset(), true));
2946 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2947 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2949 // The fixed integer arguments of a variadic function are stored to the
2950 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2951 // the result of va_next.
2952 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2953 // Get an existing live-in vreg, or add a new one.
2954 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2956 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2958 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2959 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2960 MachinePointerInfo(), false, false, 0);
2961 MemOps.push_back(Store);
2962 // Increment the address by four for the next argument to store
2963 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
2964 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2967 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2969 // The double arguments are stored to the VarArgsFrameIndex
2971 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2972 // Get an existing live-in vreg, or add a new one.
2973 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2975 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2977 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2978 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2979 MachinePointerInfo(), false, false, 0);
2980 MemOps.push_back(Store);
2981 // Increment the address by eight for the next argument to store
2982 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, dl,
2984 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2988 if (!MemOps.empty())
2989 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2994 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2995 // value to MVT::i64 and then truncate to the correct register size.
2997 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2998 SelectionDAG &DAG, SDValue ArgVal,
3001 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
3002 DAG.getValueType(ObjectVT));
3003 else if (Flags.isZExt())
3004 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
3005 DAG.getValueType(ObjectVT));
3007 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
3011 PPCTargetLowering::LowerFormalArguments_64SVR4(
3013 CallingConv::ID CallConv, bool isVarArg,
3014 const SmallVectorImpl<ISD::InputArg>
3016 SDLoc dl, SelectionDAG &DAG,
3017 SmallVectorImpl<SDValue> &InVals) const {
3018 // TODO: add description of PPC stack frame format, or at least some docs.
3020 bool isELFv2ABI = Subtarget.isELFv2ABI();
3021 bool isLittleEndian = Subtarget.isLittleEndian();
3022 MachineFunction &MF = DAG.getMachineFunction();
3023 MachineFrameInfo *MFI = MF.getFrameInfo();
3024 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3026 assert(!(CallConv == CallingConv::Fast && isVarArg) &&
3027 "fastcc not supported on varargs functions");
3029 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
3030 // Potential tail calls could cause overwriting of argument stack slots.
3031 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3032 (CallConv == CallingConv::Fast));
3033 unsigned PtrByteSize = 8;
3034 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3036 static const MCPhysReg GPR[] = {
3037 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3038 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3040 static const MCPhysReg VR[] = {
3041 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3042 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3044 static const MCPhysReg VSRH[] = {
3045 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
3046 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
3049 const unsigned Num_GPR_Regs = array_lengthof(GPR);
3050 const unsigned Num_FPR_Regs = 13;
3051 const unsigned Num_VR_Regs = array_lengthof(VR);
3052 const unsigned Num_QFPR_Regs = Num_FPR_Regs;
3054 // Do a first pass over the arguments to determine whether the ABI
3055 // guarantees that our caller has allocated the parameter save area
3056 // on its stack frame. In the ELFv1 ABI, this is always the case;
3057 // in the ELFv2 ABI, it is true if this is a vararg function or if
3058 // any parameter is located in a stack slot.
3060 bool HasParameterArea = !isELFv2ABI || isVarArg;
3061 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
3062 unsigned NumBytes = LinkageSize;
3063 unsigned AvailableFPRs = Num_FPR_Regs;
3064 unsigned AvailableVRs = Num_VR_Regs;
3065 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3066 if (Ins[i].Flags.isNest())
3069 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
3070 PtrByteSize, LinkageSize, ParamAreaSize,
3071 NumBytes, AvailableFPRs, AvailableVRs,
3072 Subtarget.hasQPX()))
3073 HasParameterArea = true;
3076 // Add DAG nodes to load the arguments or copy them out of registers. On
3077 // entry to a function on PPC, the arguments start after the linkage area,
3078 // although the first ones are often in registers.
3080 unsigned ArgOffset = LinkageSize;
3081 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3082 unsigned &QFPR_idx = FPR_idx;
3083 SmallVector<SDValue, 8> MemOps;
3084 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3085 unsigned CurArgIdx = 0;
3086 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3088 bool needsLoad = false;
3089 EVT ObjectVT = Ins[ArgNo].VT;
3090 EVT OrigVT = Ins[ArgNo].ArgVT;
3091 unsigned ObjSize = ObjectVT.getStoreSize();
3092 unsigned ArgSize = ObjSize;
3093 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3094 if (Ins[ArgNo].isOrigArg()) {
3095 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
3096 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
3098 // We re-align the argument offset for each argument, except when using the
3099 // fast calling convention, when we need to make sure we do that only when
3100 // we'll actually use a stack slot.
3101 unsigned CurArgOffset, Align;
3102 auto ComputeArgOffset = [&]() {
3103 /* Respect alignment of argument on the stack. */
3104 Align = CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
3105 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
3106 CurArgOffset = ArgOffset;
3109 if (CallConv != CallingConv::Fast) {
3112 /* Compute GPR index associated with argument offset. */
3113 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
3114 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
3117 // FIXME the codegen can be much improved in some cases.
3118 // We do not have to keep everything in memory.
3119 if (Flags.isByVal()) {
3120 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit");
3122 if (CallConv == CallingConv::Fast)
3125 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3126 ObjSize = Flags.getByValSize();
3127 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3128 // Empty aggregate parameters do not take up registers. Examples:
3132 // etc. However, we have to provide a place-holder in InVals, so
3133 // pretend we have an 8-byte item at the current address for that
3136 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3137 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3138 InVals.push_back(FIN);
3142 // Create a stack object covering all stack doublewords occupied
3143 // by the argument. If the argument is (fully or partially) on
3144 // the stack, or if the argument is fully in registers but the
3145 // caller has allocated the parameter save anyway, we can refer
3146 // directly to the caller's stack frame. Otherwise, create a
3147 // local copy in our own frame.
3149 if (HasParameterArea ||
3150 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
3151 FI = MFI->CreateFixedObject(ArgSize, ArgOffset, false, true);
3153 FI = MFI->CreateStackObject(ArgSize, Align, false);
3154 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3156 // Handle aggregates smaller than 8 bytes.
3157 if (ObjSize < PtrByteSize) {
3158 // The value of the object is its address, which differs from the
3159 // address of the enclosing doubleword on big-endian systems.
3161 if (!isLittleEndian) {
3162 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, dl, PtrVT);
3163 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
3165 InVals.push_back(Arg);
3167 if (GPR_idx != Num_GPR_Regs) {
3168 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3169 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3172 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
3173 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
3174 (ObjSize == 2 ? MVT::i16 : MVT::i32));
3175 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
3176 MachinePointerInfo(FuncArg),
3177 ObjType, false, false, 0);
3179 // For sizes that don't fit a truncating store (3, 5, 6, 7),
3180 // store the whole register as-is to the parameter save area
3182 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3183 MachinePointerInfo(FuncArg),
3187 MemOps.push_back(Store);
3189 // Whether we copied from a register or not, advance the offset
3190 // into the parameter save area by a full doubleword.
3191 ArgOffset += PtrByteSize;
3195 // The value of the object is its address, which is the address of
3196 // its first stack doubleword.
3197 InVals.push_back(FIN);
3199 // Store whatever pieces of the object are in registers to memory.
3200 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3201 if (GPR_idx == Num_GPR_Regs)
3204 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3205 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3208 SDValue Off = DAG.getConstant(j, dl, PtrVT);
3209 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
3211 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
3212 MachinePointerInfo(FuncArg, j),
3214 MemOps.push_back(Store);
3217 ArgOffset += ArgSize;
3221 switch (ObjectVT.getSimpleVT().SimpleTy) {
3222 default: llvm_unreachable("Unhandled argument type!");
3226 if (Flags.isNest()) {
3227 // The 'nest' parameter, if any, is passed in R11.
3228 unsigned VReg = MF.addLiveIn(PPC::X11, &PPC::G8RCRegClass);
3229 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3231 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3232 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3237 // These can be scalar arguments or elements of an integer array type
3238 // passed directly. Clang may use those instead of "byval" aggregate
3239 // types to avoid forcing arguments to memory unnecessarily.
3240 if (GPR_idx != Num_GPR_Regs) {
3241 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3242 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3244 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3245 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3246 // value to MVT::i64 and then truncate to the correct register size.
3247 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3249 if (CallConv == CallingConv::Fast)
3253 ArgSize = PtrByteSize;
3255 if (CallConv != CallingConv::Fast || needsLoad)
3261 // These can be scalar arguments or elements of a float array type
3262 // passed directly. The latter are used to implement ELFv2 homogenous
3263 // float aggregates.
3264 if (FPR_idx != Num_FPR_Regs) {
3267 if (ObjectVT == MVT::f32)
3268 VReg = MF.addLiveIn(FPR[FPR_idx],
3269 Subtarget.hasP8Vector()
3270 ? &PPC::VSSRCRegClass
3271 : &PPC::F4RCRegClass);
3273 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX()
3274 ? &PPC::VSFRCRegClass
3275 : &PPC::F8RCRegClass);
3277 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3279 } else if (GPR_idx != Num_GPR_Regs && CallConv != CallingConv::Fast) {
3280 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
3281 // once we support fp <-> gpr moves.
3283 // This can only ever happen in the presence of f32 array types,
3284 // since otherwise we never run out of FPRs before running out
3286 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3287 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3289 if (ObjectVT == MVT::f32) {
3290 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
3291 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
3292 DAG.getConstant(32, dl, MVT::i32));
3293 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
3296 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
3298 if (CallConv == CallingConv::Fast)
3304 // When passing an array of floats, the array occupies consecutive
3305 // space in the argument area; only round up to the next doubleword
3306 // at the end of the array. Otherwise, each float takes 8 bytes.
3307 if (CallConv != CallingConv::Fast || needsLoad) {
3308 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
3309 ArgOffset += ArgSize;
3310 if (Flags.isInConsecutiveRegsLast())
3311 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3321 if (!Subtarget.hasQPX()) {
3322 // These can be scalar arguments or elements of a vector array type
3323 // passed directly. The latter are used to implement ELFv2 homogenous
3324 // vector aggregates.
3325 if (VR_idx != Num_VR_Regs) {
3326 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
3327 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
3328 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3329 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3332 if (CallConv == CallingConv::Fast)
3337 if (CallConv != CallingConv::Fast || needsLoad)
3342 assert(ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 &&
3343 "Invalid QPX parameter type");
3348 // QPX vectors are treated like their scalar floating-point subregisters
3349 // (except that they're larger).
3350 unsigned Sz = ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 ? 16 : 32;
3351 if (QFPR_idx != Num_QFPR_Regs) {
3352 const TargetRegisterClass *RC;
3353 switch (ObjectVT.getSimpleVT().SimpleTy) {
3354 case MVT::v4f64: RC = &PPC::QFRCRegClass; break;
3355 case MVT::v4f32: RC = &PPC::QSRCRegClass; break;
3356 default: RC = &PPC::QBRCRegClass; break;
3359 unsigned VReg = MF.addLiveIn(QFPR[QFPR_idx], RC);
3360 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3363 if (CallConv == CallingConv::Fast)
3367 if (CallConv != CallingConv::Fast || needsLoad)
3372 // We need to load the argument to a virtual register if we determined
3373 // above that we ran out of physical registers of the appropriate type.
3375 if (ObjSize < ArgSize && !isLittleEndian)
3376 CurArgOffset += ArgSize - ObjSize;
3377 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
3378 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3379 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3380 false, false, false, 0);
3383 InVals.push_back(ArgVal);
3386 // Area that is at least reserved in the caller of this function.
3387 unsigned MinReservedArea;
3388 if (HasParameterArea)
3389 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
3391 MinReservedArea = LinkageSize;
3393 // Set the size that is at least reserved in caller of this function. Tail
3394 // call optimized functions' reserved stack space needs to be aligned so that
3395 // taking the difference between two stack areas will result in an aligned
3398 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3399 FuncInfo->setMinReservedArea(MinReservedArea);
3401 // If the function takes variable number of arguments, make a frame index for
3402 // the start of the first vararg value... for expansion of llvm.va_start.
3404 int Depth = ArgOffset;
3406 FuncInfo->setVarArgsFrameIndex(
3407 MFI->CreateFixedObject(PtrByteSize, Depth, true));
3408 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3410 // If this function is vararg, store any remaining integer argument regs
3411 // to their spots on the stack so that they may be loaded by deferencing the
3412 // result of va_next.
3413 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
3414 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
3415 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3416 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3417 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3418 MachinePointerInfo(), false, false, 0);
3419 MemOps.push_back(Store);
3420 // Increment the address by four for the next argument to store
3421 SDValue PtrOff = DAG.getConstant(PtrByteSize, dl, PtrVT);
3422 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3426 if (!MemOps.empty())
3427 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3433 PPCTargetLowering::LowerFormalArguments_Darwin(
3435 CallingConv::ID CallConv, bool isVarArg,
3436 const SmallVectorImpl<ISD::InputArg>
3438 SDLoc dl, SelectionDAG &DAG,
3439 SmallVectorImpl<SDValue> &InVals) const {
3440 // TODO: add description of PPC stack frame format, or at least some docs.
3442 MachineFunction &MF = DAG.getMachineFunction();
3443 MachineFrameInfo *MFI = MF.getFrameInfo();
3444 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3446 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
3447 bool isPPC64 = PtrVT == MVT::i64;
3448 // Potential tail calls could cause overwriting of argument stack slots.
3449 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3450 (CallConv == CallingConv::Fast));
3451 unsigned PtrByteSize = isPPC64 ? 8 : 4;
3452 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3453 unsigned ArgOffset = LinkageSize;
3454 // Area that is at least reserved in caller of this function.
3455 unsigned MinReservedArea = ArgOffset;
3457 static const MCPhysReg GPR_32[] = { // 32-bit registers.
3458 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3459 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3461 static const MCPhysReg GPR_64[] = { // 64-bit registers.
3462 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3463 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3465 static const MCPhysReg VR[] = {
3466 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3467 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3470 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
3471 const unsigned Num_FPR_Regs = 13;
3472 const unsigned Num_VR_Regs = array_lengthof( VR);
3474 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3476 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
3478 // In 32-bit non-varargs functions, the stack space for vectors is after the
3479 // stack space for non-vectors. We do not use this space unless we have
3480 // too many vectors to fit in registers, something that only occurs in
3481 // constructed examples:), but we have to walk the arglist to figure
3482 // that out...for the pathological case, compute VecArgOffset as the
3483 // start of the vector parameter area. Computing VecArgOffset is the
3484 // entire point of the following loop.
3485 unsigned VecArgOffset = ArgOffset;
3486 if (!isVarArg && !isPPC64) {
3487 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
3489 EVT ObjectVT = Ins[ArgNo].VT;
3490 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3492 if (Flags.isByVal()) {
3493 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
3494 unsigned ObjSize = Flags.getByValSize();
3496 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3497 VecArgOffset += ArgSize;
3501 switch(ObjectVT.getSimpleVT().SimpleTy) {
3502 default: llvm_unreachable("Unhandled argument type!");
3508 case MVT::i64: // PPC64
3510 // FIXME: We are guaranteed to be !isPPC64 at this point.
3511 // Does MVT::i64 apply?
3518 // Nothing to do, we're only looking at Nonvector args here.
3523 // We've found where the vector parameter area in memory is. Skip the
3524 // first 12 parameters; these don't use that memory.
3525 VecArgOffset = ((VecArgOffset+15)/16)*16;
3526 VecArgOffset += 12*16;
3528 // Add DAG nodes to load the arguments or copy them out of registers. On
3529 // entry to a function on PPC, the arguments start after the linkage area,
3530 // although the first ones are often in registers.
3532 SmallVector<SDValue, 8> MemOps;
3533 unsigned nAltivecParamsAtEnd = 0;
3534 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3535 unsigned CurArgIdx = 0;
3536 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3538 bool needsLoad = false;
3539 EVT ObjectVT = Ins[ArgNo].VT;
3540 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
3541 unsigned ArgSize = ObjSize;
3542 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3543 if (Ins[ArgNo].isOrigArg()) {
3544 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
3545 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
3547 unsigned CurArgOffset = ArgOffset;
3549 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
3550 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
3551 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
3552 if (isVarArg || isPPC64) {
3553 MinReservedArea = ((MinReservedArea+15)/16)*16;
3554 MinReservedArea += CalculateStackSlotSize(ObjectVT,
3557 } else nAltivecParamsAtEnd++;
3559 // Calculate min reserved area.
3560 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
3564 // FIXME the codegen can be much improved in some cases.
3565 // We do not have to keep everything in memory.
3566 if (Flags.isByVal()) {
3567 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit");
3569 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3570 ObjSize = Flags.getByValSize();
3571 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3572 // Objects of size 1 and 2 are right justified, everything else is
3573 // left justified. This means the memory address is adjusted forwards.
3574 if (ObjSize==1 || ObjSize==2) {
3575 CurArgOffset = CurArgOffset + (4 - ObjSize);
3577 // The value of the object is its address.
3578 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, false, true);
3579 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3580 InVals.push_back(FIN);
3581 if (ObjSize==1 || ObjSize==2) {
3582 if (GPR_idx != Num_GPR_Regs) {
3585 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3587 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3588 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3589 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
3590 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
3591 MachinePointerInfo(FuncArg),
3592 ObjType, false, false, 0);
3593 MemOps.push_back(Store);
3597 ArgOffset += PtrByteSize;
3601 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3602 // Store whatever pieces of the object are in registers
3603 // to memory. ArgOffset will be the address of the beginning
3605 if (GPR_idx != Num_GPR_Regs) {
3608 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3610 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3611 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3612 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3613 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3614 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3615 MachinePointerInfo(FuncArg, j),
3617 MemOps.push_back(Store);
3619 ArgOffset += PtrByteSize;
3621 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
3628 switch (ObjectVT.getSimpleVT().SimpleTy) {
3629 default: llvm_unreachable("Unhandled argument type!");
3633 if (GPR_idx != Num_GPR_Regs) {
3634 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3635 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3637 if (ObjectVT == MVT::i1)
3638 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
3643 ArgSize = PtrByteSize;
3645 // All int arguments reserve stack space in the Darwin ABI.
3646 ArgOffset += PtrByteSize;
3650 case MVT::i64: // PPC64
3651 if (GPR_idx != Num_GPR_Regs) {
3652 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3653 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3655 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3656 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3657 // value to MVT::i64 and then truncate to the correct register size.
3658 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3663 ArgSize = PtrByteSize;
3665 // All int arguments reserve stack space in the Darwin ABI.
3671 // Every 4 bytes of argument space consumes one of the GPRs available for
3672 // argument passing.
3673 if (GPR_idx != Num_GPR_Regs) {
3675 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
3678 if (FPR_idx != Num_FPR_Regs) {
3681 if (ObjectVT == MVT::f32)
3682 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
3684 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
3686 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3692 // All FP arguments reserve stack space in the Darwin ABI.
3693 ArgOffset += isPPC64 ? 8 : ObjSize;
3699 // Note that vector arguments in registers don't reserve stack space,
3700 // except in varargs functions.
3701 if (VR_idx != Num_VR_Regs) {
3702 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3703 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3705 while ((ArgOffset % 16) != 0) {
3706 ArgOffset += PtrByteSize;
3707 if (GPR_idx != Num_GPR_Regs)
3711 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
3715 if (!isVarArg && !isPPC64) {
3716 // Vectors go after all the nonvectors.
3717 CurArgOffset = VecArgOffset;
3720 // Vectors are aligned.
3721 ArgOffset = ((ArgOffset+15)/16)*16;
3722 CurArgOffset = ArgOffset;
3730 // We need to load the argument to a virtual register if we determined above
3731 // that we ran out of physical registers of the appropriate type.
3733 int FI = MFI->CreateFixedObject(ObjSize,
3734 CurArgOffset + (ArgSize - ObjSize),
3736 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3737 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3738 false, false, false, 0);
3741 InVals.push_back(ArgVal);
3744 // Allow for Altivec parameters at the end, if needed.
3745 if (nAltivecParamsAtEnd) {
3746 MinReservedArea = ((MinReservedArea+15)/16)*16;
3747 MinReservedArea += 16*nAltivecParamsAtEnd;
3750 // Area that is at least reserved in the caller of this function.
3751 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
3753 // Set the size that is at least reserved in caller of this function. Tail
3754 // call optimized functions' reserved stack space needs to be aligned so that
3755 // taking the difference between two stack areas will result in an aligned
3758 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3759 FuncInfo->setMinReservedArea(MinReservedArea);
3761 // If the function takes variable number of arguments, make a frame index for
3762 // the start of the first vararg value... for expansion of llvm.va_start.
3764 int Depth = ArgOffset;
3766 FuncInfo->setVarArgsFrameIndex(
3767 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3769 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3771 // If this function is vararg, store any remaining integer argument regs
3772 // to their spots on the stack so that they may be loaded by deferencing the
3773 // result of va_next.
3774 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3778 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3780 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3782 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3783 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3784 MachinePointerInfo(), false, false, 0);
3785 MemOps.push_back(Store);
3786 // Increment the address by four for the next argument to store
3787 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
3788 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3792 if (!MemOps.empty())
3793 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3798 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3799 /// adjusted to accommodate the arguments for the tailcall.
3800 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3801 unsigned ParamSize) {
3803 if (!isTailCall) return 0;
3805 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3806 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3807 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3808 // Remember only if the new adjustement is bigger.
3809 if (SPDiff < FI->getTailCallSPDelta())
3810 FI->setTailCallSPDelta(SPDiff);
3815 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3816 /// for tail call optimization. Targets which want to do tail call
3817 /// optimization should implement this function.
3819 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3820 CallingConv::ID CalleeCC,
3822 const SmallVectorImpl<ISD::InputArg> &Ins,
3823 SelectionDAG& DAG) const {
3824 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3827 // Variable argument functions are not supported.
3831 MachineFunction &MF = DAG.getMachineFunction();
3832 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3833 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3834 // Functions containing by val parameters are not supported.
3835 for (unsigned i = 0; i != Ins.size(); i++) {
3836 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3837 if (Flags.isByVal()) return false;
3840 // Non-PIC/GOT tail calls are supported.
3841 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3844 // At the moment we can only do local tail calls (in same module, hidden
3845 // or protected) if we are generating PIC.
3846 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3847 return G->getGlobal()->hasHiddenVisibility()
3848 || G->getGlobal()->hasProtectedVisibility();
3854 /// isCallCompatibleAddress - Return the immediate to use if the specified
3855 /// 32-bit value is representable in the immediate field of a BxA instruction.
3856 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3857 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3858 if (!C) return nullptr;
3860 int Addr = C->getZExtValue();
3861 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3862 SignExtend32<26>(Addr) != Addr)
3863 return nullptr; // Top 6 bits have to be sext of immediate.
3865 return DAG.getConstant((int)C->getZExtValue() >> 2, SDLoc(Op),
3866 DAG.getTargetLoweringInfo().getPointerTy(
3867 DAG.getDataLayout())).getNode();
3872 struct TailCallArgumentInfo {
3877 TailCallArgumentInfo() : FrameIdx(0) {}
3882 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3884 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3886 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3887 SmallVectorImpl<SDValue> &MemOpChains,
3889 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3890 SDValue Arg = TailCallArgs[i].Arg;
3891 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3892 int FI = TailCallArgs[i].FrameIdx;
3893 // Store relative to framepointer.
3894 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
3895 MachinePointerInfo::getFixedStack(FI),
3900 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3901 /// the appropriate stack slot for the tail call optimized function call.
3902 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3903 MachineFunction &MF,
3912 // Calculate the new stack slot for the return address.
3913 int SlotSize = isPPC64 ? 8 : 4;
3914 const PPCFrameLowering *FL =
3915 MF.getSubtarget<PPCSubtarget>().getFrameLowering();
3916 int NewRetAddrLoc = SPDiff + FL->getReturnSaveOffset();
3917 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3918 NewRetAddrLoc, true);
3919 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3920 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3921 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3922 MachinePointerInfo::getFixedStack(NewRetAddr),
3925 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3926 // slot as the FP is never overwritten.
3928 int NewFPLoc = SPDiff + FL->getFramePointerSaveOffset();
3929 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3931 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3932 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3933 MachinePointerInfo::getFixedStack(NewFPIdx),
3940 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3941 /// the position of the argument.
3943 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3944 SDValue Arg, int SPDiff, unsigned ArgOffset,
3945 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3946 int Offset = ArgOffset + SPDiff;
3947 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3948 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3949 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3950 SDValue FIN = DAG.getFrameIndex(FI, VT);
3951 TailCallArgumentInfo Info;
3953 Info.FrameIdxOp = FIN;
3955 TailCallArguments.push_back(Info);
3958 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3959 /// stack slot. Returns the chain as result and the loaded frame pointers in
3960 /// LROpOut/FPOpout. Used when tail calling.
3961 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3969 // Load the LR and FP stack slot for later adjusting.
3970 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
3971 LROpOut = getReturnAddrFrameIndex(DAG);
3972 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3973 false, false, false, 0);
3974 Chain = SDValue(LROpOut.getNode(), 1);
3976 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3977 // slot as the FP is never overwritten.
3979 FPOpOut = getFramePointerFrameIndex(DAG);
3980 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3981 false, false, false, 0);
3982 Chain = SDValue(FPOpOut.getNode(), 1);
3988 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3989 /// by "Src" to address "Dst" of size "Size". Alignment information is
3990 /// specified by the specific parameter attribute. The copy will be passed as
3991 /// a byval function parameter.
3992 /// Sometimes what we are copying is the end of a larger object, the part that
3993 /// does not fit in registers.
3995 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3996 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3998 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
3999 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
4000 false, false, false, MachinePointerInfo(),
4001 MachinePointerInfo());
4004 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
4007 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
4008 SDValue Arg, SDValue PtrOff, int SPDiff,
4009 unsigned ArgOffset, bool isPPC64, bool isTailCall,
4010 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
4011 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
4013 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4018 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4020 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4021 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4022 DAG.getConstant(ArgOffset, dl, PtrVT));
4024 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4025 MachinePointerInfo(), false, false, 0));
4026 // Calculate and remember argument location.
4027 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
4032 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
4033 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
4034 SDValue LROp, SDValue FPOp, bool isDarwinABI,
4035 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
4036 MachineFunction &MF = DAG.getMachineFunction();
4038 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
4039 // might overwrite each other in case of tail call optimization.
4040 SmallVector<SDValue, 8> MemOpChains2;
4041 // Do not flag preceding copytoreg stuff together with the following stuff.
4043 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
4045 if (!MemOpChains2.empty())
4046 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
4048 // Store the return address to the appropriate stack slot.
4049 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
4050 isPPC64, isDarwinABI, dl);
4052 // Emit callseq_end just before tailcall node.
4053 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4054 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
4055 InFlag = Chain.getValue(1);
4058 // Is this global address that of a function that can be called by name? (as
4059 // opposed to something that must hold a descriptor for an indirect call).
4060 static bool isFunctionGlobalAddress(SDValue Callee) {
4061 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
4062 if (Callee.getOpcode() == ISD::GlobalTLSAddress ||
4063 Callee.getOpcode() == ISD::TargetGlobalTLSAddress)
4066 return G->getGlobal()->getType()->getElementType()->isFunctionTy();
4073 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
4074 SDValue &Chain, SDValue CallSeqStart, SDLoc dl, int SPDiff,
4075 bool isTailCall, bool IsPatchPoint, bool hasNest,
4076 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
4077 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
4078 ImmutableCallSite *CS, const PPCSubtarget &Subtarget) {
4080 bool isPPC64 = Subtarget.isPPC64();
4081 bool isSVR4ABI = Subtarget.isSVR4ABI();
4082 bool isELFv2ABI = Subtarget.isELFv2ABI();
4084 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4085 NodeTys.push_back(MVT::Other); // Returns a chain
4086 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
4088 unsigned CallOpc = PPCISD::CALL;
4090 bool needIndirectCall = true;
4091 if (!isSVR4ABI || !isPPC64)
4092 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
4093 // If this is an absolute destination address, use the munged value.
4094 Callee = SDValue(Dest, 0);
4095 needIndirectCall = false;
4098 if (isFunctionGlobalAddress(Callee)) {
4099 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Callee);
4100 // A call to a TLS address is actually an indirect call to a
4101 // thread-specific pointer.
4102 unsigned OpFlags = 0;
4103 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
4104 (Subtarget.getTargetTriple().isMacOSX() &&
4105 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
4106 !G->getGlobal()->isStrongDefinitionForLinker()) ||
4107 (Subtarget.isTargetELF() && !isPPC64 &&
4108 !G->getGlobal()->hasLocalLinkage() &&
4109 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
4110 // PC-relative references to external symbols should go through $stub,
4111 // unless we're building with the leopard linker or later, which
4112 // automatically synthesizes these stubs.
4113 OpFlags = PPCII::MO_PLT_OR_STUB;
4116 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
4117 // every direct call is) turn it into a TargetGlobalAddress /
4118 // TargetExternalSymbol node so that legalize doesn't hack it.
4119 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
4120 Callee.getValueType(), 0, OpFlags);
4121 needIndirectCall = false;
4124 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
4125 unsigned char OpFlags = 0;
4127 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
4128 (Subtarget.getTargetTriple().isMacOSX() &&
4129 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) ||
4130 (Subtarget.isTargetELF() && !isPPC64 &&
4131 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
4132 // PC-relative references to external symbols should go through $stub,
4133 // unless we're building with the leopard linker or later, which
4134 // automatically synthesizes these stubs.
4135 OpFlags = PPCII::MO_PLT_OR_STUB;
4138 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
4140 needIndirectCall = false;
4144 // We'll form an invalid direct call when lowering a patchpoint; the full
4145 // sequence for an indirect call is complicated, and many of the
4146 // instructions introduced might have side effects (and, thus, can't be
4147 // removed later). The call itself will be removed as soon as the
4148 // argument/return lowering is complete, so the fact that it has the wrong
4149 // kind of operands should not really matter.
4150 needIndirectCall = false;
4153 if (needIndirectCall) {
4154 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
4155 // to do the call, we can't use PPCISD::CALL.
4156 SDValue MTCTROps[] = {Chain, Callee, InFlag};
4158 if (isSVR4ABI && isPPC64 && !isELFv2ABI) {
4159 // Function pointers in the 64-bit SVR4 ABI do not point to the function
4160 // entry point, but to the function descriptor (the function entry point
4161 // address is part of the function descriptor though).
4162 // The function descriptor is a three doubleword structure with the
4163 // following fields: function entry point, TOC base address and
4164 // environment pointer.
4165 // Thus for a call through a function pointer, the following actions need
4167 // 1. Save the TOC of the caller in the TOC save area of its stack
4168 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
4169 // 2. Load the address of the function entry point from the function
4171 // 3. Load the TOC of the callee from the function descriptor into r2.
4172 // 4. Load the environment pointer from the function descriptor into
4174 // 5. Branch to the function entry point address.
4175 // 6. On return of the callee, the TOC of the caller needs to be
4176 // restored (this is done in FinishCall()).
4178 // The loads are scheduled at the beginning of the call sequence, and the
4179 // register copies are flagged together to ensure that no other
4180 // operations can be scheduled in between. E.g. without flagging the
4181 // copies together, a TOC access in the caller could be scheduled between
4182 // the assignment of the callee TOC and the branch to the callee, which
4183 // results in the TOC access going through the TOC of the callee instead
4184 // of going through the TOC of the caller, which leads to incorrect code.
4186 // Load the address of the function entry point from the function
4188 SDValue LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-1);
4189 if (LDChain.getValueType() == MVT::Glue)
4190 LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-2);
4192 bool LoadsInv = Subtarget.hasInvariantFunctionDescriptors();
4194 MachinePointerInfo MPI(CS ? CS->getCalledValue() : nullptr);
4195 SDValue LoadFuncPtr = DAG.getLoad(MVT::i64, dl, LDChain, Callee, MPI,
4196 false, false, LoadsInv, 8);
4198 // Load environment pointer into r11.
4199 SDValue PtrOff = DAG.getIntPtrConstant(16, dl);
4200 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
4201 SDValue LoadEnvPtr = DAG.getLoad(MVT::i64, dl, LDChain, AddPtr,
4202 MPI.getWithOffset(16), false, false,
4205 SDValue TOCOff = DAG.getIntPtrConstant(8, dl);
4206 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
4207 SDValue TOCPtr = DAG.getLoad(MVT::i64, dl, LDChain, AddTOC,
4208 MPI.getWithOffset(8), false, false,
4211 setUsesTOCBasePtr(DAG);
4212 SDValue TOCVal = DAG.getCopyToReg(Chain, dl, PPC::X2, TOCPtr,
4214 Chain = TOCVal.getValue(0);
4215 InFlag = TOCVal.getValue(1);
4217 // If the function call has an explicit 'nest' parameter, it takes the
4218 // place of the environment pointer.
4220 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
4223 Chain = EnvVal.getValue(0);
4224 InFlag = EnvVal.getValue(1);
4227 MTCTROps[0] = Chain;
4228 MTCTROps[1] = LoadFuncPtr;
4229 MTCTROps[2] = InFlag;
4232 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
4233 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
4234 InFlag = Chain.getValue(1);
4237 NodeTys.push_back(MVT::Other);
4238 NodeTys.push_back(MVT::Glue);
4239 Ops.push_back(Chain);
4240 CallOpc = PPCISD::BCTRL;
4241 Callee.setNode(nullptr);
4242 // Add use of X11 (holding environment pointer)
4243 if (isSVR4ABI && isPPC64 && !isELFv2ABI && !hasNest)
4244 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
4245 // Add CTR register as callee so a bctr can be emitted later.
4247 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
4250 // If this is a direct call, pass the chain and the callee.
4251 if (Callee.getNode()) {
4252 Ops.push_back(Chain);
4253 Ops.push_back(Callee);
4255 // If this is a tail call add stack pointer delta.
4257 Ops.push_back(DAG.getConstant(SPDiff, dl, MVT::i32));
4259 // Add argument registers to the end of the list so that they are known live
4261 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
4262 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
4263 RegsToPass[i].second.getValueType()));
4265 // All calls, in both the ELF V1 and V2 ABIs, need the TOC register live
4267 if (isSVR4ABI && isPPC64 && !IsPatchPoint) {
4268 setUsesTOCBasePtr(DAG);
4269 Ops.push_back(DAG.getRegister(PPC::X2, PtrVT));
4276 bool isLocalCall(const SDValue &Callee)
4278 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
4279 return G->getGlobal()->isStrongDefinitionForLinker();
4284 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
4285 CallingConv::ID CallConv, bool isVarArg,
4286 const SmallVectorImpl<ISD::InputArg> &Ins,
4287 SDLoc dl, SelectionDAG &DAG,
4288 SmallVectorImpl<SDValue> &InVals) const {
4290 SmallVector<CCValAssign, 16> RVLocs;
4291 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
4293 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
4295 // Copy all of the result registers out of their specified physreg.
4296 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
4297 CCValAssign &VA = RVLocs[i];
4298 assert(VA.isRegLoc() && "Can only return in registers!");
4300 SDValue Val = DAG.getCopyFromReg(Chain, dl,
4301 VA.getLocReg(), VA.getLocVT(), InFlag);
4302 Chain = Val.getValue(1);
4303 InFlag = Val.getValue(2);
4305 switch (VA.getLocInfo()) {
4306 default: llvm_unreachable("Unknown loc info!");
4307 case CCValAssign::Full: break;
4308 case CCValAssign::AExt:
4309 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4311 case CCValAssign::ZExt:
4312 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
4313 DAG.getValueType(VA.getValVT()));
4314 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4316 case CCValAssign::SExt:
4317 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
4318 DAG.getValueType(VA.getValVT()));
4319 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4323 InVals.push_back(Val);
4330 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
4331 bool isTailCall, bool isVarArg, bool IsPatchPoint,
4332 bool hasNest, SelectionDAG &DAG,
4333 SmallVector<std::pair<unsigned, SDValue>, 8>
4335 SDValue InFlag, SDValue Chain,
4336 SDValue CallSeqStart, SDValue &Callee,
4337 int SPDiff, unsigned NumBytes,
4338 const SmallVectorImpl<ISD::InputArg> &Ins,
4339 SmallVectorImpl<SDValue> &InVals,
4340 ImmutableCallSite *CS) const {
4342 std::vector<EVT> NodeTys;
4343 SmallVector<SDValue, 8> Ops;
4344 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, CallSeqStart, dl,
4345 SPDiff, isTailCall, IsPatchPoint, hasNest,
4346 RegsToPass, Ops, NodeTys, CS, Subtarget);
4348 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
4349 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
4350 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
4352 // When performing tail call optimization the callee pops its arguments off
4353 // the stack. Account for this here so these bytes can be pushed back on in
4354 // PPCFrameLowering::eliminateCallFramePseudoInstr.
4355 int BytesCalleePops =
4356 (CallConv == CallingConv::Fast &&
4357 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
4359 // Add a register mask operand representing the call-preserved registers.
4360 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
4361 const uint32_t *Mask =
4362 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
4363 assert(Mask && "Missing call preserved mask for calling convention");
4364 Ops.push_back(DAG.getRegisterMask(Mask));
4366 if (InFlag.getNode())
4367 Ops.push_back(InFlag);
4371 assert(((Callee.getOpcode() == ISD::Register &&
4372 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
4373 Callee.getOpcode() == ISD::TargetExternalSymbol ||
4374 Callee.getOpcode() == ISD::TargetGlobalAddress ||
4375 isa<ConstantSDNode>(Callee)) &&
4376 "Expecting an global address, external symbol, absolute value or register");
4378 DAG.getMachineFunction().getFrameInfo()->setHasTailCall();
4379 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
4382 // Add a NOP immediately after the branch instruction when using the 64-bit
4383 // SVR4 ABI. At link time, if caller and callee are in a different module and
4384 // thus have a different TOC, the call will be replaced with a call to a stub
4385 // function which saves the current TOC, loads the TOC of the callee and
4386 // branches to the callee. The NOP will be replaced with a load instruction
4387 // which restores the TOC of the caller from the TOC save slot of the current
4388 // stack frame. If caller and callee belong to the same module (and have the
4389 // same TOC), the NOP will remain unchanged.
4391 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64() &&
4393 if (CallOpc == PPCISD::BCTRL) {
4394 // This is a call through a function pointer.
4395 // Restore the caller TOC from the save area into R2.
4396 // See PrepareCall() for more information about calls through function
4397 // pointers in the 64-bit SVR4 ABI.
4398 // We are using a target-specific load with r2 hard coded, because the
4399 // result of a target-independent load would never go directly into r2,
4400 // since r2 is a reserved register (which prevents the register allocator
4401 // from allocating it), resulting in an additional register being
4402 // allocated and an unnecessary move instruction being generated.
4403 CallOpc = PPCISD::BCTRL_LOAD_TOC;
4405 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4406 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
4407 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
4408 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset, dl);
4409 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
4411 // The address needs to go after the chain input but before the flag (or
4412 // any other variadic arguments).
4413 Ops.insert(std::next(Ops.begin()), AddTOC);
4414 } else if ((CallOpc == PPCISD::CALL) &&
4415 (!isLocalCall(Callee) ||
4416 DAG.getTarget().getRelocationModel() == Reloc::PIC_))
4417 // Otherwise insert NOP for non-local calls.
4418 CallOpc = PPCISD::CALL_NOP;
4421 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
4422 InFlag = Chain.getValue(1);
4424 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4425 DAG.getIntPtrConstant(BytesCalleePops, dl, true),
4428 InFlag = Chain.getValue(1);
4430 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
4431 Ins, dl, DAG, InVals);
4435 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
4436 SmallVectorImpl<SDValue> &InVals) const {
4437 SelectionDAG &DAG = CLI.DAG;
4439 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
4440 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
4441 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
4442 SDValue Chain = CLI.Chain;
4443 SDValue Callee = CLI.Callee;
4444 bool &isTailCall = CLI.IsTailCall;
4445 CallingConv::ID CallConv = CLI.CallConv;
4446 bool isVarArg = CLI.IsVarArg;
4447 bool IsPatchPoint = CLI.IsPatchPoint;
4448 ImmutableCallSite *CS = CLI.CS;
4451 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
4454 if (!isTailCall && CS && CS->isMustTailCall())
4455 report_fatal_error("failed to perform tail call elimination on a call "
4456 "site marked musttail");
4458 if (Subtarget.isSVR4ABI()) {
4459 if (Subtarget.isPPC64())
4460 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
4461 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4462 dl, DAG, InVals, CS);
4464 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
4465 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4466 dl, DAG, InVals, CS);
4469 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
4470 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4471 dl, DAG, InVals, CS);
4475 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
4476 CallingConv::ID CallConv, bool isVarArg,
4477 bool isTailCall, bool IsPatchPoint,
4478 const SmallVectorImpl<ISD::OutputArg> &Outs,
4479 const SmallVectorImpl<SDValue> &OutVals,
4480 const SmallVectorImpl<ISD::InputArg> &Ins,
4481 SDLoc dl, SelectionDAG &DAG,
4482 SmallVectorImpl<SDValue> &InVals,
4483 ImmutableCallSite *CS) const {
4484 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
4485 // of the 32-bit SVR4 ABI stack frame layout.
4487 assert((CallConv == CallingConv::C ||
4488 CallConv == CallingConv::Fast) && "Unknown calling convention!");
4490 unsigned PtrByteSize = 4;
4492 MachineFunction &MF = DAG.getMachineFunction();
4494 // Mark this function as potentially containing a function that contains a
4495 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4496 // and restoring the callers stack pointer in this functions epilog. This is
4497 // done because by tail calling the called function might overwrite the value
4498 // in this function's (MF) stack pointer stack slot 0(SP).
4499 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4500 CallConv == CallingConv::Fast)
4501 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4503 // Count how many bytes are to be pushed on the stack, including the linkage
4504 // area, parameter list area and the part of the local variable space which
4505 // contains copies of aggregates which are passed by value.
4507 // Assign locations to all of the outgoing arguments.
4508 SmallVector<CCValAssign, 16> ArgLocs;
4509 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
4512 // Reserve space for the linkage area on the stack.
4513 CCInfo.AllocateStack(Subtarget.getFrameLowering()->getLinkageSize(),
4517 // Handle fixed and variable vector arguments differently.
4518 // Fixed vector arguments go into registers as long as registers are
4519 // available. Variable vector arguments always go into memory.
4520 unsigned NumArgs = Outs.size();
4522 for (unsigned i = 0; i != NumArgs; ++i) {
4523 MVT ArgVT = Outs[i].VT;
4524 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
4527 if (Outs[i].IsFixed) {
4528 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
4531 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
4537 errs() << "Call operand #" << i << " has unhandled type "
4538 << EVT(ArgVT).getEVTString() << "\n";
4540 llvm_unreachable(nullptr);
4544 // All arguments are treated the same.
4545 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
4548 // Assign locations to all of the outgoing aggregate by value arguments.
4549 SmallVector<CCValAssign, 16> ByValArgLocs;
4550 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4551 ByValArgLocs, *DAG.getContext());
4553 // Reserve stack space for the allocations in CCInfo.
4554 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
4556 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
4558 // Size of the linkage area, parameter list area and the part of the local
4559 // space variable where copies of aggregates which are passed by value are
4561 unsigned NumBytes = CCByValInfo.getNextStackOffset();
4563 // Calculate by how many bytes the stack has to be adjusted in case of tail
4564 // call optimization.
4565 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4567 // Adjust the stack pointer for the new arguments...
4568 // These operations are automatically eliminated by the prolog/epilog pass
4569 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4571 SDValue CallSeqStart = Chain;
4573 // Load the return address and frame pointer so it can be moved somewhere else
4576 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
4579 // Set up a copy of the stack pointer for use loading and storing any
4580 // arguments that may not fit in the registers available for argument
4582 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4584 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4585 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4586 SmallVector<SDValue, 8> MemOpChains;
4588 bool seenFloatArg = false;
4589 // Walk the register/memloc assignments, inserting copies/loads.
4590 for (unsigned i = 0, j = 0, e = ArgLocs.size();
4593 CCValAssign &VA = ArgLocs[i];
4594 SDValue Arg = OutVals[i];
4595 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4597 if (Flags.isByVal()) {
4598 // Argument is an aggregate which is passed by value, thus we need to
4599 // create a copy of it in the local variable space of the current stack
4600 // frame (which is the stack frame of the caller) and pass the address of
4601 // this copy to the callee.
4602 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
4603 CCValAssign &ByValVA = ByValArgLocs[j++];
4604 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
4606 // Memory reserved in the local variable space of the callers stack frame.
4607 unsigned LocMemOffset = ByValVA.getLocMemOffset();
4609 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
4610 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(MF.getDataLayout()),
4613 // Create a copy of the argument in the local area of the current
4615 SDValue MemcpyCall =
4616 CreateCopyOfByValArgument(Arg, PtrOff,
4617 CallSeqStart.getNode()->getOperand(0),
4620 // This must go outside the CALLSEQ_START..END.
4621 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4622 CallSeqStart.getNode()->getOperand(1),
4624 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4625 NewCallSeqStart.getNode());
4626 Chain = CallSeqStart = NewCallSeqStart;
4628 // Pass the address of the aggregate copy on the stack either in a
4629 // physical register or in the parameter list area of the current stack
4630 // frame to the callee.
4634 if (VA.isRegLoc()) {
4635 if (Arg.getValueType() == MVT::i1)
4636 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
4638 seenFloatArg |= VA.getLocVT().isFloatingPoint();
4639 // Put argument in a physical register.
4640 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
4642 // Put argument in the parameter list area of the current stack frame.
4643 assert(VA.isMemLoc());
4644 unsigned LocMemOffset = VA.getLocMemOffset();
4647 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
4648 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(MF.getDataLayout()),
4651 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4652 MachinePointerInfo(),
4655 // Calculate and remember argument location.
4656 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
4662 if (!MemOpChains.empty())
4663 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4665 // Build a sequence of copy-to-reg nodes chained together with token chain
4666 // and flag operands which copy the outgoing args into the appropriate regs.
4668 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4669 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4670 RegsToPass[i].second, InFlag);
4671 InFlag = Chain.getValue(1);
4674 // Set CR bit 6 to true if this is a vararg call with floating args passed in
4677 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
4678 SDValue Ops[] = { Chain, InFlag };
4680 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
4681 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
4683 InFlag = Chain.getValue(1);
4687 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
4688 false, TailCallArguments);
4690 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint,
4691 /* unused except on PPC64 ELFv1 */ false, DAG,
4692 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
4693 NumBytes, Ins, InVals, CS);
4696 // Copy an argument into memory, being careful to do this outside the
4697 // call sequence for the call to which the argument belongs.
4699 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
4700 SDValue CallSeqStart,
4701 ISD::ArgFlagsTy Flags,
4704 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
4705 CallSeqStart.getNode()->getOperand(0),
4707 // The MEMCPY must go outside the CALLSEQ_START..END.
4708 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4709 CallSeqStart.getNode()->getOperand(1),
4711 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4712 NewCallSeqStart.getNode());
4713 return NewCallSeqStart;
4717 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
4718 CallingConv::ID CallConv, bool isVarArg,
4719 bool isTailCall, bool IsPatchPoint,
4720 const SmallVectorImpl<ISD::OutputArg> &Outs,
4721 const SmallVectorImpl<SDValue> &OutVals,
4722 const SmallVectorImpl<ISD::InputArg> &Ins,
4723 SDLoc dl, SelectionDAG &DAG,
4724 SmallVectorImpl<SDValue> &InVals,
4725 ImmutableCallSite *CS) const {
4727 bool isELFv2ABI = Subtarget.isELFv2ABI();
4728 bool isLittleEndian = Subtarget.isLittleEndian();
4729 unsigned NumOps = Outs.size();
4730 bool hasNest = false;
4732 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4733 unsigned PtrByteSize = 8;
4735 MachineFunction &MF = DAG.getMachineFunction();
4737 // Mark this function as potentially containing a function that contains a
4738 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4739 // and restoring the callers stack pointer in this functions epilog. This is
4740 // done because by tail calling the called function might overwrite the value
4741 // in this function's (MF) stack pointer stack slot 0(SP).
4742 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4743 CallConv == CallingConv::Fast)
4744 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4746 assert(!(CallConv == CallingConv::Fast && isVarArg) &&
4747 "fastcc not supported on varargs functions");
4749 // Count how many bytes are to be pushed on the stack, including the linkage
4750 // area, and parameter passing area. On ELFv1, the linkage area is 48 bytes
4751 // reserved space for [SP][CR][LR][2 x unused][TOC]; on ELFv2, the linkage
4752 // area is 32 bytes reserved space for [SP][CR][LR][TOC].
4753 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
4754 unsigned NumBytes = LinkageSize;
4755 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4756 unsigned &QFPR_idx = FPR_idx;
4758 static const MCPhysReg GPR[] = {
4759 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4760 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4762 static const MCPhysReg VR[] = {
4763 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4764 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4766 static const MCPhysReg VSRH[] = {
4767 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4768 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4771 const unsigned NumGPRs = array_lengthof(GPR);
4772 const unsigned NumFPRs = 13;
4773 const unsigned NumVRs = array_lengthof(VR);
4774 const unsigned NumQFPRs = NumFPRs;
4776 // When using the fast calling convention, we don't provide backing for
4777 // arguments that will be in registers.
4778 unsigned NumGPRsUsed = 0, NumFPRsUsed = 0, NumVRsUsed = 0;
4780 // Add up all the space actually used.
4781 for (unsigned i = 0; i != NumOps; ++i) {
4782 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4783 EVT ArgVT = Outs[i].VT;
4784 EVT OrigVT = Outs[i].ArgVT;
4789 if (CallConv == CallingConv::Fast) {
4790 if (Flags.isByVal())
4791 NumGPRsUsed += (Flags.getByValSize()+7)/8;
4793 switch (ArgVT.getSimpleVT().SimpleTy) {
4794 default: llvm_unreachable("Unexpected ValueType for argument!");
4798 if (++NumGPRsUsed <= NumGPRs)
4807 if (++NumVRsUsed <= NumVRs)
4811 // When using QPX, this is handled like a FP register, otherwise, it
4812 // is an Altivec register.
4813 if (Subtarget.hasQPX()) {
4814 if (++NumFPRsUsed <= NumFPRs)
4817 if (++NumVRsUsed <= NumVRs)
4823 case MVT::v4f64: // QPX
4824 case MVT::v4i1: // QPX
4825 if (++NumFPRsUsed <= NumFPRs)
4831 /* Respect alignment of argument on the stack. */
4833 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4834 NumBytes = ((NumBytes + Align - 1) / Align) * Align;
4836 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4837 if (Flags.isInConsecutiveRegsLast())
4838 NumBytes = ((NumBytes + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4841 unsigned NumBytesActuallyUsed = NumBytes;
4843 // The prolog code of the callee may store up to 8 GPR argument registers to
4844 // the stack, allowing va_start to index over them in memory if its varargs.
4845 // Because we cannot tell if this is needed on the caller side, we have to
4846 // conservatively assume that it is needed. As such, make sure we have at
4847 // least enough stack space for the caller to store the 8 GPRs.
4848 // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
4849 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4851 // Tail call needs the stack to be aligned.
4852 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4853 CallConv == CallingConv::Fast)
4854 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes);
4856 // Calculate by how many bytes the stack has to be adjusted in case of tail
4857 // call optimization.
4858 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4860 // To protect arguments on the stack from being clobbered in a tail call,
4861 // force all the loads to happen before doing any other lowering.
4863 Chain = DAG.getStackArgumentTokenFactor(Chain);
4865 // Adjust the stack pointer for the new arguments...
4866 // These operations are automatically eliminated by the prolog/epilog pass
4867 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4869 SDValue CallSeqStart = Chain;
4871 // Load the return address and frame pointer so it can be move somewhere else
4874 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4877 // Set up a copy of the stack pointer for use loading and storing any
4878 // arguments that may not fit in the registers available for argument
4880 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4882 // Figure out which arguments are going to go in registers, and which in
4883 // memory. Also, if this is a vararg function, floating point operations
4884 // must be stored to our stack, and loaded into integer regs as well, if
4885 // any integer regs are available for argument passing.
4886 unsigned ArgOffset = LinkageSize;
4888 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4889 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4891 SmallVector<SDValue, 8> MemOpChains;
4892 for (unsigned i = 0; i != NumOps; ++i) {
4893 SDValue Arg = OutVals[i];
4894 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4895 EVT ArgVT = Outs[i].VT;
4896 EVT OrigVT = Outs[i].ArgVT;
4898 // PtrOff will be used to store the current argument to the stack if a
4899 // register cannot be found for it.
4902 // We re-align the argument offset for each argument, except when using the
4903 // fast calling convention, when we need to make sure we do that only when
4904 // we'll actually use a stack slot.
4905 auto ComputePtrOff = [&]() {
4906 /* Respect alignment of argument on the stack. */
4908 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4909 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
4911 PtrOff = DAG.getConstant(ArgOffset, dl, StackPtr.getValueType());
4913 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4916 if (CallConv != CallingConv::Fast) {
4919 /* Compute GPR index associated with argument offset. */
4920 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4921 GPR_idx = std::min(GPR_idx, NumGPRs);
4924 // Promote integers to 64-bit values.
4925 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4926 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4927 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4928 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4931 // FIXME memcpy is used way more than necessary. Correctness first.
4932 // Note: "by value" is code for passing a structure by value, not
4934 if (Flags.isByVal()) {
4935 // Note: Size includes alignment padding, so
4936 // struct x { short a; char b; }
4937 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4938 // These are the proper values we need for right-justifying the
4939 // aggregate in a parameter register.
4940 unsigned Size = Flags.getByValSize();
4942 // An empty aggregate parameter takes up no storage and no
4947 if (CallConv == CallingConv::Fast)
4950 // All aggregates smaller than 8 bytes must be passed right-justified.
4951 if (Size==1 || Size==2 || Size==4) {
4952 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4953 if (GPR_idx != NumGPRs) {
4954 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4955 MachinePointerInfo(), VT,
4956 false, false, false, 0);
4957 MemOpChains.push_back(Load.getValue(1));
4958 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4960 ArgOffset += PtrByteSize;
4965 if (GPR_idx == NumGPRs && Size < 8) {
4966 SDValue AddPtr = PtrOff;
4967 if (!isLittleEndian) {
4968 SDValue Const = DAG.getConstant(PtrByteSize - Size, dl,
4969 PtrOff.getValueType());
4970 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4972 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4975 ArgOffset += PtrByteSize;
4978 // Copy entire object into memory. There are cases where gcc-generated
4979 // code assumes it is there, even if it could be put entirely into
4980 // registers. (This is not what the doc says.)
4982 // FIXME: The above statement is likely due to a misunderstanding of the
4983 // documents. All arguments must be copied into the parameter area BY
4984 // THE CALLEE in the event that the callee takes the address of any
4985 // formal argument. That has not yet been implemented. However, it is
4986 // reasonable to use the stack area as a staging area for the register
4989 // Skip this for small aggregates, as we will use the same slot for a
4990 // right-justified copy, below.
4992 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4996 // When a register is available, pass a small aggregate right-justified.
4997 if (Size < 8 && GPR_idx != NumGPRs) {
4998 // The easiest way to get this right-justified in a register
4999 // is to copy the structure into the rightmost portion of a
5000 // local variable slot, then load the whole slot into the
5002 // FIXME: The memcpy seems to produce pretty awful code for
5003 // small aggregates, particularly for packed ones.
5004 // FIXME: It would be preferable to use the slot in the
5005 // parameter save area instead of a new local variable.
5006 SDValue AddPtr = PtrOff;
5007 if (!isLittleEndian) {
5008 SDValue Const = DAG.getConstant(8 - Size, dl, PtrOff.getValueType());
5009 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
5011 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
5015 // Load the slot into the register.
5016 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
5017 MachinePointerInfo(),
5018 false, false, false, 0);
5019 MemOpChains.push_back(Load.getValue(1));
5020 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5022 // Done with this argument.
5023 ArgOffset += PtrByteSize;
5027 // For aggregates larger than PtrByteSize, copy the pieces of the
5028 // object that fit into registers from the parameter save area.
5029 for (unsigned j=0; j<Size; j+=PtrByteSize) {
5030 SDValue Const = DAG.getConstant(j, dl, PtrOff.getValueType());
5031 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
5032 if (GPR_idx != NumGPRs) {
5033 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
5034 MachinePointerInfo(),
5035 false, false, false, 0);
5036 MemOpChains.push_back(Load.getValue(1));
5037 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5038 ArgOffset += PtrByteSize;
5040 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
5047 switch (Arg.getSimpleValueType().SimpleTy) {
5048 default: llvm_unreachable("Unexpected ValueType for argument!");
5052 if (Flags.isNest()) {
5053 // The 'nest' parameter, if any, is passed in R11.
5054 RegsToPass.push_back(std::make_pair(PPC::X11, Arg));
5059 // These can be scalar arguments or elements of an integer array type
5060 // passed directly. Clang may use those instead of "byval" aggregate
5061 // types to avoid forcing arguments to memory unnecessarily.
5062 if (GPR_idx != NumGPRs) {
5063 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
5065 if (CallConv == CallingConv::Fast)
5068 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5069 true, isTailCall, false, MemOpChains,
5070 TailCallArguments, dl);
5071 if (CallConv == CallingConv::Fast)
5072 ArgOffset += PtrByteSize;
5074 if (CallConv != CallingConv::Fast)
5075 ArgOffset += PtrByteSize;
5079 // These can be scalar arguments or elements of a float array type
5080 // passed directly. The latter are used to implement ELFv2 homogenous
5081 // float aggregates.
5083 // Named arguments go into FPRs first, and once they overflow, the
5084 // remaining arguments go into GPRs and then the parameter save area.
5085 // Unnamed arguments for vararg functions always go to GPRs and
5086 // then the parameter save area. For now, put all arguments to vararg
5087 // routines always in both locations (FPR *and* GPR or stack slot).
5088 bool NeedGPROrStack = isVarArg || FPR_idx == NumFPRs;
5089 bool NeededLoad = false;
5091 // First load the argument into the next available FPR.
5092 if (FPR_idx != NumFPRs)
5093 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
5095 // Next, load the argument into GPR or stack slot if needed.
5096 if (!NeedGPROrStack)
5098 else if (GPR_idx != NumGPRs && CallConv != CallingConv::Fast) {
5099 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
5100 // once we support fp <-> gpr moves.
5102 // In the non-vararg case, this can only ever happen in the
5103 // presence of f32 array types, since otherwise we never run
5104 // out of FPRs before running out of GPRs.
5107 // Double values are always passed in a single GPR.
5108 if (Arg.getValueType() != MVT::f32) {
5109 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
5111 // Non-array float values are extended and passed in a GPR.
5112 } else if (!Flags.isInConsecutiveRegs()) {
5113 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
5114 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
5116 // If we have an array of floats, we collect every odd element
5117 // together with its predecessor into one GPR.
5118 } else if (ArgOffset % PtrByteSize != 0) {
5120 Lo = DAG.getNode(ISD::BITCAST, dl, MVT::i32, OutVals[i - 1]);
5121 Hi = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
5122 if (!isLittleEndian)
5124 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
5126 // The final element, if even, goes into the first half of a GPR.
5127 } else if (Flags.isInConsecutiveRegsLast()) {
5128 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
5129 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
5130 if (!isLittleEndian)
5131 ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal,
5132 DAG.getConstant(32, dl, MVT::i32));
5134 // Non-final even elements are skipped; they will be handled
5135 // together the with subsequent argument on the next go-around.
5139 if (ArgVal.getNode())
5140 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], ArgVal));
5142 if (CallConv == CallingConv::Fast)
5145 // Single-precision floating-point values are mapped to the
5146 // second (rightmost) word of the stack doubleword.
5147 if (Arg.getValueType() == MVT::f32 &&
5148 !isLittleEndian && !Flags.isInConsecutiveRegs()) {
5149 SDValue ConstFour = DAG.getConstant(4, dl, PtrOff.getValueType());
5150 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
5153 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5154 true, isTailCall, false, MemOpChains,
5155 TailCallArguments, dl);
5159 // When passing an array of floats, the array occupies consecutive
5160 // space in the argument area; only round up to the next doubleword
5161 // at the end of the array. Otherwise, each float takes 8 bytes.
5162 if (CallConv != CallingConv::Fast || NeededLoad) {
5163 ArgOffset += (Arg.getValueType() == MVT::f32 &&
5164 Flags.isInConsecutiveRegs()) ? 4 : 8;
5165 if (Flags.isInConsecutiveRegsLast())
5166 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
5177 if (!Subtarget.hasQPX()) {
5178 // These can be scalar arguments or elements of a vector array type
5179 // passed directly. The latter are used to implement ELFv2 homogenous
5180 // vector aggregates.
5182 // For a varargs call, named arguments go into VRs or on the stack as
5183 // usual; unnamed arguments always go to the stack or the corresponding
5184 // GPRs when within range. For now, we always put the value in both
5185 // locations (or even all three).
5187 // We could elide this store in the case where the object fits
5188 // entirely in R registers. Maybe later.
5189 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5190 MachinePointerInfo(), false, false, 0);
5191 MemOpChains.push_back(Store);
5192 if (VR_idx != NumVRs) {
5193 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
5194 MachinePointerInfo(),
5195 false, false, false, 0);
5196 MemOpChains.push_back(Load.getValue(1));
5198 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
5199 Arg.getSimpleValueType() == MVT::v2i64) ?
5200 VSRH[VR_idx] : VR[VR_idx];
5203 RegsToPass.push_back(std::make_pair(VReg, Load));
5206 for (unsigned i=0; i<16; i+=PtrByteSize) {
5207 if (GPR_idx == NumGPRs)
5209 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5210 DAG.getConstant(i, dl, PtrVT));
5211 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5212 false, false, false, 0);
5213 MemOpChains.push_back(Load.getValue(1));
5214 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5219 // Non-varargs Altivec params go into VRs or on the stack.
5220 if (VR_idx != NumVRs) {
5221 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
5222 Arg.getSimpleValueType() == MVT::v2i64) ?
5223 VSRH[VR_idx] : VR[VR_idx];
5226 RegsToPass.push_back(std::make_pair(VReg, Arg));
5228 if (CallConv == CallingConv::Fast)
5231 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5232 true, isTailCall, true, MemOpChains,
5233 TailCallArguments, dl);
5234 if (CallConv == CallingConv::Fast)
5238 if (CallConv != CallingConv::Fast)
5243 assert(Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32 &&
5244 "Invalid QPX parameter type");
5249 bool IsF32 = Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32;
5251 // We could elide this store in the case where the object fits
5252 // entirely in R registers. Maybe later.
5253 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5254 MachinePointerInfo(), false, false, 0);
5255 MemOpChains.push_back(Store);
5256 if (QFPR_idx != NumQFPRs) {
5257 SDValue Load = DAG.getLoad(IsF32 ? MVT::v4f32 : MVT::v4f64, dl,
5258 Store, PtrOff, MachinePointerInfo(),
5259 false, false, false, 0);
5260 MemOpChains.push_back(Load.getValue(1));
5261 RegsToPass.push_back(std::make_pair(QFPR[QFPR_idx++], Load));
5263 ArgOffset += (IsF32 ? 16 : 32);
5264 for (unsigned i = 0; i < (IsF32 ? 16U : 32U); i += PtrByteSize) {
5265 if (GPR_idx == NumGPRs)
5267 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5268 DAG.getConstant(i, dl, PtrVT));
5269 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5270 false, false, false, 0);
5271 MemOpChains.push_back(Load.getValue(1));
5272 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5277 // Non-varargs QPX params go into registers or on the stack.
5278 if (QFPR_idx != NumQFPRs) {
5279 RegsToPass.push_back(std::make_pair(QFPR[QFPR_idx++], Arg));
5281 if (CallConv == CallingConv::Fast)
5284 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5285 true, isTailCall, true, MemOpChains,
5286 TailCallArguments, dl);
5287 if (CallConv == CallingConv::Fast)
5288 ArgOffset += (IsF32 ? 16 : 32);
5291 if (CallConv != CallingConv::Fast)
5292 ArgOffset += (IsF32 ? 16 : 32);
5298 assert(NumBytesActuallyUsed == ArgOffset);
5299 (void)NumBytesActuallyUsed;
5301 if (!MemOpChains.empty())
5302 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5304 // Check if this is an indirect call (MTCTR/BCTRL).
5305 // See PrepareCall() for more information about calls through function
5306 // pointers in the 64-bit SVR4 ABI.
5307 if (!isTailCall && !IsPatchPoint &&
5308 !isFunctionGlobalAddress(Callee) &&
5309 !isa<ExternalSymbolSDNode>(Callee)) {
5310 // Load r2 into a virtual register and store it to the TOC save area.
5311 setUsesTOCBasePtr(DAG);
5312 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
5313 // TOC save area offset.
5314 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
5315 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset, dl);
5316 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
5317 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr,
5318 MachinePointerInfo::getStack(TOCSaveOffset),
5320 // In the ELFv2 ABI, R12 must contain the address of an indirect callee.
5321 // This does not mean the MTCTR instruction must use R12; it's easier
5322 // to model this as an extra parameter, so do that.
5323 if (isELFv2ABI && !IsPatchPoint)
5324 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
5327 // Build a sequence of copy-to-reg nodes chained together with token chain
5328 // and flag operands which copy the outgoing args into the appropriate regs.
5330 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5331 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5332 RegsToPass[i].second, InFlag);
5333 InFlag = Chain.getValue(1);
5337 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
5338 FPOp, true, TailCallArguments);
5340 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint,
5341 hasNest, DAG, RegsToPass, InFlag, Chain, CallSeqStart,
5342 Callee, SPDiff, NumBytes, Ins, InVals, CS);
5346 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
5347 CallingConv::ID CallConv, bool isVarArg,
5348 bool isTailCall, bool IsPatchPoint,
5349 const SmallVectorImpl<ISD::OutputArg> &Outs,
5350 const SmallVectorImpl<SDValue> &OutVals,
5351 const SmallVectorImpl<ISD::InputArg> &Ins,
5352 SDLoc dl, SelectionDAG &DAG,
5353 SmallVectorImpl<SDValue> &InVals,
5354 ImmutableCallSite *CS) const {
5356 unsigned NumOps = Outs.size();
5358 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
5359 bool isPPC64 = PtrVT == MVT::i64;
5360 unsigned PtrByteSize = isPPC64 ? 8 : 4;
5362 MachineFunction &MF = DAG.getMachineFunction();
5364 // Mark this function as potentially containing a function that contains a
5365 // tail call. As a consequence the frame pointer will be used for dynamicalloc
5366 // and restoring the callers stack pointer in this functions epilog. This is
5367 // done because by tail calling the called function might overwrite the value
5368 // in this function's (MF) stack pointer stack slot 0(SP).
5369 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5370 CallConv == CallingConv::Fast)
5371 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
5373 // Count how many bytes are to be pushed on the stack, including the linkage
5374 // area, and parameter passing area. We start with 24/48 bytes, which is
5375 // prereserved space for [SP][CR][LR][3 x unused].
5376 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
5377 unsigned NumBytes = LinkageSize;
5379 // Add up all the space actually used.
5380 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
5381 // they all go in registers, but we must reserve stack space for them for
5382 // possible use by the caller. In varargs or 64-bit calls, parameters are
5383 // assigned stack space in order, with padding so Altivec parameters are
5385 unsigned nAltivecParamsAtEnd = 0;
5386 for (unsigned i = 0; i != NumOps; ++i) {
5387 ISD::ArgFlagsTy Flags = Outs[i].Flags;
5388 EVT ArgVT = Outs[i].VT;
5389 // Varargs Altivec parameters are padded to a 16 byte boundary.
5390 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
5391 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
5392 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) {
5393 if (!isVarArg && !isPPC64) {
5394 // Non-varargs Altivec parameters go after all the non-Altivec
5395 // parameters; handle those later so we know how much padding we need.
5396 nAltivecParamsAtEnd++;
5399 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
5400 NumBytes = ((NumBytes+15)/16)*16;
5402 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
5405 // Allow for Altivec parameters at the end, if needed.
5406 if (nAltivecParamsAtEnd) {
5407 NumBytes = ((NumBytes+15)/16)*16;
5408 NumBytes += 16*nAltivecParamsAtEnd;
5411 // The prolog code of the callee may store up to 8 GPR argument registers to
5412 // the stack, allowing va_start to index over them in memory if its varargs.
5413 // Because we cannot tell if this is needed on the caller side, we have to
5414 // conservatively assume that it is needed. As such, make sure we have at
5415 // least enough stack space for the caller to store the 8 GPRs.
5416 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
5418 // Tail call needs the stack to be aligned.
5419 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5420 CallConv == CallingConv::Fast)
5421 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes);
5423 // Calculate by how many bytes the stack has to be adjusted in case of tail
5424 // call optimization.
5425 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
5427 // To protect arguments on the stack from being clobbered in a tail call,
5428 // force all the loads to happen before doing any other lowering.
5430 Chain = DAG.getStackArgumentTokenFactor(Chain);
5432 // Adjust the stack pointer for the new arguments...
5433 // These operations are automatically eliminated by the prolog/epilog pass
5434 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
5436 SDValue CallSeqStart = Chain;
5438 // Load the return address and frame pointer so it can be move somewhere else
5441 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
5444 // Set up a copy of the stack pointer for use loading and storing any
5445 // arguments that may not fit in the registers available for argument
5449 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
5451 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
5453 // Figure out which arguments are going to go in registers, and which in
5454 // memory. Also, if this is a vararg function, floating point operations
5455 // must be stored to our stack, and loaded into integer regs as well, if
5456 // any integer regs are available for argument passing.
5457 unsigned ArgOffset = LinkageSize;
5458 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
5460 static const MCPhysReg GPR_32[] = { // 32-bit registers.
5461 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
5462 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
5464 static const MCPhysReg GPR_64[] = { // 64-bit registers.
5465 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
5466 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
5468 static const MCPhysReg VR[] = {
5469 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
5470 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
5472 const unsigned NumGPRs = array_lengthof(GPR_32);
5473 const unsigned NumFPRs = 13;
5474 const unsigned NumVRs = array_lengthof(VR);
5476 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
5478 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
5479 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
5481 SmallVector<SDValue, 8> MemOpChains;
5482 for (unsigned i = 0; i != NumOps; ++i) {
5483 SDValue Arg = OutVals[i];
5484 ISD::ArgFlagsTy Flags = Outs[i].Flags;
5486 // PtrOff will be used to store the current argument to the stack if a
5487 // register cannot be found for it.
5490 PtrOff = DAG.getConstant(ArgOffset, dl, StackPtr.getValueType());
5492 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
5494 // On PPC64, promote integers to 64-bit values.
5495 if (isPPC64 && Arg.getValueType() == MVT::i32) {
5496 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
5497 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
5498 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
5501 // FIXME memcpy is used way more than necessary. Correctness first.
5502 // Note: "by value" is code for passing a structure by value, not
5504 if (Flags.isByVal()) {
5505 unsigned Size = Flags.getByValSize();
5506 // Very small objects are passed right-justified. Everything else is
5507 // passed left-justified.
5508 if (Size==1 || Size==2) {
5509 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
5510 if (GPR_idx != NumGPRs) {
5511 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
5512 MachinePointerInfo(), VT,
5513 false, false, false, 0);
5514 MemOpChains.push_back(Load.getValue(1));
5515 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5517 ArgOffset += PtrByteSize;
5519 SDValue Const = DAG.getConstant(PtrByteSize - Size, dl,
5520 PtrOff.getValueType());
5521 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
5522 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
5525 ArgOffset += PtrByteSize;
5529 // Copy entire object into memory. There are cases where gcc-generated
5530 // code assumes it is there, even if it could be put entirely into
5531 // registers. (This is not what the doc says.)
5532 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
5536 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
5537 // copy the pieces of the object that fit into registers from the
5538 // parameter save area.
5539 for (unsigned j=0; j<Size; j+=PtrByteSize) {
5540 SDValue Const = DAG.getConstant(j, dl, PtrOff.getValueType());
5541 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
5542 if (GPR_idx != NumGPRs) {
5543 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
5544 MachinePointerInfo(),
5545 false, false, false, 0);
5546 MemOpChains.push_back(Load.getValue(1));
5547 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5548 ArgOffset += PtrByteSize;
5550 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
5557 switch (Arg.getSimpleValueType().SimpleTy) {
5558 default: llvm_unreachable("Unexpected ValueType for argument!");
5562 if (GPR_idx != NumGPRs) {
5563 if (Arg.getValueType() == MVT::i1)
5564 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
5566 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
5568 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5569 isPPC64, isTailCall, false, MemOpChains,
5570 TailCallArguments, dl);
5572 ArgOffset += PtrByteSize;
5576 if (FPR_idx != NumFPRs) {
5577 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
5580 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5581 MachinePointerInfo(), false, false, 0);
5582 MemOpChains.push_back(Store);
5584 // Float varargs are always shadowed in available integer registers
5585 if (GPR_idx != NumGPRs) {
5586 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
5587 MachinePointerInfo(), false, false,
5589 MemOpChains.push_back(Load.getValue(1));
5590 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5592 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
5593 SDValue ConstFour = DAG.getConstant(4, dl, PtrOff.getValueType());
5594 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
5595 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
5596 MachinePointerInfo(),
5597 false, false, false, 0);
5598 MemOpChains.push_back(Load.getValue(1));
5599 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5602 // If we have any FPRs remaining, we may also have GPRs remaining.
5603 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
5605 if (GPR_idx != NumGPRs)
5607 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
5608 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
5612 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5613 isPPC64, isTailCall, false, MemOpChains,
5614 TailCallArguments, dl);
5618 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
5625 // These go aligned on the stack, or in the corresponding R registers
5626 // when within range. The Darwin PPC ABI doc claims they also go in
5627 // V registers; in fact gcc does this only for arguments that are
5628 // prototyped, not for those that match the ... We do it for all
5629 // arguments, seems to work.
5630 while (ArgOffset % 16 !=0) {
5631 ArgOffset += PtrByteSize;
5632 if (GPR_idx != NumGPRs)
5635 // We could elide this store in the case where the object fits
5636 // entirely in R registers. Maybe later.
5637 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
5638 DAG.getConstant(ArgOffset, dl, PtrVT));
5639 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5640 MachinePointerInfo(), false, false, 0);
5641 MemOpChains.push_back(Store);
5642 if (VR_idx != NumVRs) {
5643 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
5644 MachinePointerInfo(),
5645 false, false, false, 0);
5646 MemOpChains.push_back(Load.getValue(1));
5647 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
5650 for (unsigned i=0; i<16; i+=PtrByteSize) {
5651 if (GPR_idx == NumGPRs)
5653 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5654 DAG.getConstant(i, dl, PtrVT));
5655 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5656 false, false, false, 0);
5657 MemOpChains.push_back(Load.getValue(1));
5658 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5663 // Non-varargs Altivec params generally go in registers, but have
5664 // stack space allocated at the end.
5665 if (VR_idx != NumVRs) {
5666 // Doesn't have GPR space allocated.
5667 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
5668 } else if (nAltivecParamsAtEnd==0) {
5669 // We are emitting Altivec params in order.
5670 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5671 isPPC64, isTailCall, true, MemOpChains,
5672 TailCallArguments, dl);
5678 // If all Altivec parameters fit in registers, as they usually do,
5679 // they get stack space following the non-Altivec parameters. We
5680 // don't track this here because nobody below needs it.
5681 // If there are more Altivec parameters than fit in registers emit
5683 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
5685 // Offset is aligned; skip 1st 12 params which go in V registers.
5686 ArgOffset = ((ArgOffset+15)/16)*16;
5688 for (unsigned i = 0; i != NumOps; ++i) {
5689 SDValue Arg = OutVals[i];
5690 EVT ArgType = Outs[i].VT;
5691 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
5692 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
5695 // We are emitting Altivec params in order.
5696 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5697 isPPC64, isTailCall, true, MemOpChains,
5698 TailCallArguments, dl);
5705 if (!MemOpChains.empty())
5706 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5708 // On Darwin, R12 must contain the address of an indirect callee. This does
5709 // not mean the MTCTR instruction must use R12; it's easier to model this as
5710 // an extra parameter, so do that.
5712 !isFunctionGlobalAddress(Callee) &&
5713 !isa<ExternalSymbolSDNode>(Callee) &&
5714 !isBLACompatibleAddress(Callee, DAG))
5715 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
5716 PPC::R12), Callee));
5718 // Build a sequence of copy-to-reg nodes chained together with token chain
5719 // and flag operands which copy the outgoing args into the appropriate regs.
5721 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5722 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5723 RegsToPass[i].second, InFlag);
5724 InFlag = Chain.getValue(1);
5728 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
5729 FPOp, true, TailCallArguments);
5731 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint,
5732 /* unused except on PPC64 ELFv1 */ false, DAG,
5733 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
5734 NumBytes, Ins, InVals, CS);
5738 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
5739 MachineFunction &MF, bool isVarArg,
5740 const SmallVectorImpl<ISD::OutputArg> &Outs,
5741 LLVMContext &Context) const {
5742 SmallVector<CCValAssign, 16> RVLocs;
5743 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
5744 return CCInfo.CheckReturn(Outs, RetCC_PPC);
5748 PPCTargetLowering::LowerReturn(SDValue Chain,
5749 CallingConv::ID CallConv, bool isVarArg,
5750 const SmallVectorImpl<ISD::OutputArg> &Outs,
5751 const SmallVectorImpl<SDValue> &OutVals,
5752 SDLoc dl, SelectionDAG &DAG) const {
5754 SmallVector<CCValAssign, 16> RVLocs;
5755 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
5757 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
5760 SmallVector<SDValue, 4> RetOps(1, Chain);
5762 // Copy the result values into the output registers.
5763 for (unsigned i = 0; i != RVLocs.size(); ++i) {
5764 CCValAssign &VA = RVLocs[i];
5765 assert(VA.isRegLoc() && "Can only return in registers!");
5767 SDValue Arg = OutVals[i];
5769 switch (VA.getLocInfo()) {
5770 default: llvm_unreachable("Unknown loc info!");
5771 case CCValAssign::Full: break;
5772 case CCValAssign::AExt:
5773 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
5775 case CCValAssign::ZExt:
5776 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
5778 case CCValAssign::SExt:
5779 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
5783 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
5784 Flag = Chain.getValue(1);
5785 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
5788 RetOps[0] = Chain; // Update chain.
5790 // Add the flag if we have it.
5792 RetOps.push_back(Flag);
5794 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
5797 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
5798 const PPCSubtarget &Subtarget) const {
5799 // When we pop the dynamic allocation we need to restore the SP link.
5802 // Get the corect type for pointers.
5803 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
5805 // Construct the stack pointer operand.
5806 bool isPPC64 = Subtarget.isPPC64();
5807 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
5808 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
5810 // Get the operands for the STACKRESTORE.
5811 SDValue Chain = Op.getOperand(0);
5812 SDValue SaveSP = Op.getOperand(1);
5814 // Load the old link SP.
5815 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
5816 MachinePointerInfo(),
5817 false, false, false, 0);
5819 // Restore the stack pointer.
5820 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
5822 // Store the old link SP.
5823 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
5830 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
5831 MachineFunction &MF = DAG.getMachineFunction();
5832 bool isPPC64 = Subtarget.isPPC64();
5833 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
5835 // Get current frame pointer save index. The users of this index will be
5836 // primarily DYNALLOC instructions.
5837 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5838 int RASI = FI->getReturnAddrSaveIndex();
5840 // If the frame pointer save index hasn't been defined yet.
5842 // Find out what the fix offset of the frame pointer save area.
5843 int LROffset = Subtarget.getFrameLowering()->getReturnSaveOffset();
5844 // Allocate the frame index for frame pointer save area.
5845 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, false);
5847 FI->setReturnAddrSaveIndex(RASI);
5849 return DAG.getFrameIndex(RASI, PtrVT);
5853 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
5854 MachineFunction &MF = DAG.getMachineFunction();
5855 bool isPPC64 = Subtarget.isPPC64();
5856 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
5858 // Get current frame pointer save index. The users of this index will be
5859 // primarily DYNALLOC instructions.
5860 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5861 int FPSI = FI->getFramePointerSaveIndex();
5863 // If the frame pointer save index hasn't been defined yet.
5865 // Find out what the fix offset of the frame pointer save area.
5866 int FPOffset = Subtarget.getFrameLowering()->getFramePointerSaveOffset();
5867 // Allocate the frame index for frame pointer save area.
5868 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
5870 FI->setFramePointerSaveIndex(FPSI);
5872 return DAG.getFrameIndex(FPSI, PtrVT);
5875 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5877 const PPCSubtarget &Subtarget) const {
5879 SDValue Chain = Op.getOperand(0);
5880 SDValue Size = Op.getOperand(1);
5883 // Get the corect type for pointers.
5884 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
5886 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
5887 DAG.getConstant(0, dl, PtrVT), Size);
5888 // Construct a node for the frame pointer save index.
5889 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
5890 // Build a DYNALLOC node.
5891 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
5892 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
5893 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
5896 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
5897 SelectionDAG &DAG) const {
5899 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
5900 DAG.getVTList(MVT::i32, MVT::Other),
5901 Op.getOperand(0), Op.getOperand(1));
5904 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
5905 SelectionDAG &DAG) const {
5907 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
5908 Op.getOperand(0), Op.getOperand(1));
5911 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
5912 if (Op.getValueType().isVector())
5913 return LowerVectorLoad(Op, DAG);
5915 assert(Op.getValueType() == MVT::i1 &&
5916 "Custom lowering only for i1 loads");
5918 // First, load 8 bits into 32 bits, then truncate to 1 bit.
5921 LoadSDNode *LD = cast<LoadSDNode>(Op);
5923 SDValue Chain = LD->getChain();
5924 SDValue BasePtr = LD->getBasePtr();
5925 MachineMemOperand *MMO = LD->getMemOperand();
5928 DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(DAG.getDataLayout()), Chain,
5929 BasePtr, MVT::i8, MMO);
5930 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
5932 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
5933 return DAG.getMergeValues(Ops, dl);
5936 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
5937 if (Op.getOperand(1).getValueType().isVector())
5938 return LowerVectorStore(Op, DAG);
5940 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
5941 "Custom lowering only for i1 stores");
5943 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
5946 StoreSDNode *ST = cast<StoreSDNode>(Op);
5948 SDValue Chain = ST->getChain();
5949 SDValue BasePtr = ST->getBasePtr();
5950 SDValue Value = ST->getValue();
5951 MachineMemOperand *MMO = ST->getMemOperand();
5953 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(DAG.getDataLayout()),
5955 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
5958 // FIXME: Remove this once the ANDI glue bug is fixed:
5959 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
5960 assert(Op.getValueType() == MVT::i1 &&
5961 "Custom lowering only for i1 results");
5964 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
5968 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
5970 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5971 // Not FP? Not a fsel.
5972 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
5973 !Op.getOperand(2).getValueType().isFloatingPoint())
5976 // We might be able to do better than this under some circumstances, but in
5977 // general, fsel-based lowering of select is a finite-math-only optimization.
5978 // For more information, see section F.3 of the 2.06 ISA specification.
5979 if (!DAG.getTarget().Options.NoInfsFPMath ||
5980 !DAG.getTarget().Options.NoNaNsFPMath)
5983 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5985 EVT ResVT = Op.getValueType();
5986 EVT CmpVT = Op.getOperand(0).getValueType();
5987 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5988 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
5991 // If the RHS of the comparison is a 0.0, we don't need to do the
5992 // subtraction at all.
5994 if (isFloatingPointZero(RHS))
5996 default: break; // SETUO etc aren't handled by fsel.
6000 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
6001 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
6002 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
6003 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
6004 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
6005 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
6006 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
6009 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
6012 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
6013 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
6014 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
6017 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
6020 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
6021 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
6022 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
6023 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
6028 default: break; // SETUO etc aren't handled by fsel.
6032 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
6033 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6034 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6035 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
6036 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
6037 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
6038 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
6039 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
6042 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
6043 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6044 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6045 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
6048 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
6049 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6050 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6051 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
6054 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
6055 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6056 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6057 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
6060 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
6061 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6062 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6063 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
6068 void PPCTargetLowering::LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
6071 assert(Op.getOperand(0).getValueType().isFloatingPoint());
6072 SDValue Src = Op.getOperand(0);
6073 if (Src.getValueType() == MVT::f32)
6074 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
6077 switch (Op.getSimpleValueType().SimpleTy) {
6078 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
6081 Op.getOpcode() == ISD::FP_TO_SINT
6083 : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ),
6087 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
6088 "i64 FP_TO_UINT is supported only with FPCVT");
6089 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
6095 // Convert the FP value to an int value through memory.
6096 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
6097 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
6098 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
6099 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
6100 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
6102 // Emit a store to the stack slot.
6105 MachineFunction &MF = DAG.getMachineFunction();
6106 MachineMemOperand *MMO =
6107 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
6108 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
6109 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
6110 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
6112 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
6113 MPI, false, false, 0);
6115 // Result is a load from the stack slot. If loading 4 bytes, make sure to
6117 if (Op.getValueType() == MVT::i32 && !i32Stack) {
6118 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
6119 DAG.getConstant(4, dl, FIPtr.getValueType()));
6120 MPI = MPI.getWithOffset(4);
6128 /// \brief Custom lowers floating point to integer conversions to use
6129 /// the direct move instructions available in ISA 2.07 to avoid the
6130 /// need for load/store combinations.
6131 SDValue PPCTargetLowering::LowerFP_TO_INTDirectMove(SDValue Op,
6134 assert(Op.getOperand(0).getValueType().isFloatingPoint());
6135 SDValue Src = Op.getOperand(0);
6137 if (Src.getValueType() == MVT::f32)
6138 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
6141 switch (Op.getSimpleValueType().SimpleTy) {
6142 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
6145 Op.getOpcode() == ISD::FP_TO_SINT
6147 : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ),
6149 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i32, Tmp);
6152 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
6153 "i64 FP_TO_UINT is supported only with FPCVT");
6154 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
6157 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i64, Tmp);
6163 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
6165 if (Subtarget.hasDirectMove() && Subtarget.isPPC64())
6166 return LowerFP_TO_INTDirectMove(Op, DAG, dl);
6169 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
6171 return DAG.getLoad(Op.getValueType(), dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
6172 false, RLI.IsInvariant, RLI.Alignment, RLI.AAInfo,
6176 // We're trying to insert a regular store, S, and then a load, L. If the
6177 // incoming value, O, is a load, we might just be able to have our load use the
6178 // address used by O. However, we don't know if anything else will store to
6179 // that address before we can load from it. To prevent this situation, we need
6180 // to insert our load, L, into the chain as a peer of O. To do this, we give L
6181 // the same chain operand as O, we create a token factor from the chain results
6182 // of O and L, and we replace all uses of O's chain result with that token
6183 // factor (see spliceIntoChain below for this last part).
6184 bool PPCTargetLowering::canReuseLoadAddress(SDValue Op, EVT MemVT,
6187 ISD::LoadExtType ET) const {
6189 if (ET == ISD::NON_EXTLOAD &&
6190 (Op.getOpcode() == ISD::FP_TO_UINT ||
6191 Op.getOpcode() == ISD::FP_TO_SINT) &&
6192 isOperationLegalOrCustom(Op.getOpcode(),
6193 Op.getOperand(0).getValueType())) {
6195 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
6199 LoadSDNode *LD = dyn_cast<LoadSDNode>(Op);
6200 if (!LD || LD->getExtensionType() != ET || LD->isVolatile() ||
6201 LD->isNonTemporal())
6203 if (LD->getMemoryVT() != MemVT)
6206 RLI.Ptr = LD->getBasePtr();
6207 if (LD->isIndexed() && LD->getOffset().getOpcode() != ISD::UNDEF) {
6208 assert(LD->getAddressingMode() == ISD::PRE_INC &&
6209 "Non-pre-inc AM on PPC?");
6210 RLI.Ptr = DAG.getNode(ISD::ADD, dl, RLI.Ptr.getValueType(), RLI.Ptr,
6214 RLI.Chain = LD->getChain();
6215 RLI.MPI = LD->getPointerInfo();
6216 RLI.IsInvariant = LD->isInvariant();
6217 RLI.Alignment = LD->getAlignment();
6218 RLI.AAInfo = LD->getAAInfo();
6219 RLI.Ranges = LD->getRanges();
6221 RLI.ResChain = SDValue(LD, LD->isIndexed() ? 2 : 1);
6225 // Given the head of the old chain, ResChain, insert a token factor containing
6226 // it and NewResChain, and make users of ResChain now be users of that token
6228 void PPCTargetLowering::spliceIntoChain(SDValue ResChain,
6229 SDValue NewResChain,
6230 SelectionDAG &DAG) const {
6234 SDLoc dl(NewResChain);
6236 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6237 NewResChain, DAG.getUNDEF(MVT::Other));
6238 assert(TF.getNode() != NewResChain.getNode() &&
6239 "A new TF really is required here");
6241 DAG.ReplaceAllUsesOfValueWith(ResChain, TF);
6242 DAG.UpdateNodeOperands(TF.getNode(), ResChain, NewResChain);
6245 /// \brief Custom lowers integer to floating point conversions to use
6246 /// the direct move instructions available in ISA 2.07 to avoid the
6247 /// need for load/store combinations.
6248 SDValue PPCTargetLowering::LowerINT_TO_FPDirectMove(SDValue Op,
6251 assert((Op.getValueType() == MVT::f32 ||
6252 Op.getValueType() == MVT::f64) &&
6253 "Invalid floating point type as target of conversion");
6254 assert(Subtarget.hasFPCVT() &&
6255 "Int to FP conversions with direct moves require FPCVT");
6257 SDValue Src = Op.getOperand(0);
6258 bool SinglePrec = Op.getValueType() == MVT::f32;
6259 bool WordInt = Src.getSimpleValueType().SimpleTy == MVT::i32;
6260 bool Signed = Op.getOpcode() == ISD::SINT_TO_FP;
6261 unsigned ConvOp = Signed ? (SinglePrec ? PPCISD::FCFIDS : PPCISD::FCFID) :
6262 (SinglePrec ? PPCISD::FCFIDUS : PPCISD::FCFIDU);
6265 FP = DAG.getNode(Signed ? PPCISD::MTVSRA : PPCISD::MTVSRZ,
6267 FP = DAG.getNode(ConvOp, dl, SinglePrec ? MVT::f32 : MVT::f64, FP);
6270 FP = DAG.getNode(PPCISD::MTVSRA, dl, MVT::f64, Src);
6271 FP = DAG.getNode(ConvOp, dl, SinglePrec ? MVT::f32 : MVT::f64, FP);
6277 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
6278 SelectionDAG &DAG) const {
6281 if (Subtarget.hasQPX() && Op.getOperand(0).getValueType() == MVT::v4i1) {
6282 if (Op.getValueType() != MVT::v4f32 && Op.getValueType() != MVT::v4f64)
6285 SDValue Value = Op.getOperand(0);
6286 // The values are now known to be -1 (false) or 1 (true). To convert this
6287 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
6288 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
6289 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
6291 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::f64);
6292 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
6293 FPHalfs, FPHalfs, FPHalfs, FPHalfs);
6295 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
6297 if (Op.getValueType() != MVT::v4f64)
6298 Value = DAG.getNode(ISD::FP_ROUND, dl,
6299 Op.getValueType(), Value,
6300 DAG.getIntPtrConstant(1, dl));
6304 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
6305 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
6308 if (Op.getOperand(0).getValueType() == MVT::i1)
6309 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
6310 DAG.getConstantFP(1.0, dl, Op.getValueType()),
6311 DAG.getConstantFP(0.0, dl, Op.getValueType()));
6313 // If we have direct moves, we can do all the conversion, skip the store/load
6314 // however, without FPCVT we can't do most conversions.
6315 if (Subtarget.hasDirectMove() && Subtarget.isPPC64() && Subtarget.hasFPCVT())
6316 return LowerINT_TO_FPDirectMove(Op, DAG, dl);
6318 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
6319 "UINT_TO_FP is supported only with FPCVT");
6321 // If we have FCFIDS, then use it when converting to single-precision.
6322 // Otherwise, convert to double-precision and then round.
6323 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
6324 ? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
6326 : (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
6328 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
6332 if (Op.getOperand(0).getValueType() == MVT::i64) {
6333 SDValue SINT = Op.getOperand(0);
6334 // When converting to single-precision, we actually need to convert
6335 // to double-precision first and then round to single-precision.
6336 // To avoid double-rounding effects during that operation, we have
6337 // to prepare the input operand. Bits that might be truncated when
6338 // converting to double-precision are replaced by a bit that won't
6339 // be lost at this stage, but is below the single-precision rounding
6342 // However, if -enable-unsafe-fp-math is in effect, accept double
6343 // rounding to avoid the extra overhead.
6344 if (Op.getValueType() == MVT::f32 &&
6345 !Subtarget.hasFPCVT() &&
6346 !DAG.getTarget().Options.UnsafeFPMath) {
6348 // Twiddle input to make sure the low 11 bits are zero. (If this
6349 // is the case, we are guaranteed the value will fit into the 53 bit
6350 // mantissa of an IEEE double-precision value without rounding.)
6351 // If any of those low 11 bits were not zero originally, make sure
6352 // bit 12 (value 2048) is set instead, so that the final rounding
6353 // to single-precision gets the correct result.
6354 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
6355 SINT, DAG.getConstant(2047, dl, MVT::i64));
6356 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
6357 Round, DAG.getConstant(2047, dl, MVT::i64));
6358 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
6359 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
6360 Round, DAG.getConstant(-2048, dl, MVT::i64));
6362 // However, we cannot use that value unconditionally: if the magnitude
6363 // of the input value is small, the bit-twiddling we did above might
6364 // end up visibly changing the output. Fortunately, in that case, we
6365 // don't need to twiddle bits since the original input will convert
6366 // exactly to double-precision floating-point already. Therefore,
6367 // construct a conditional to use the original value if the top 11
6368 // bits are all sign-bit copies, and use the rounded value computed
6370 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
6371 SINT, DAG.getConstant(53, dl, MVT::i32));
6372 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
6373 Cond, DAG.getConstant(1, dl, MVT::i64));
6374 Cond = DAG.getSetCC(dl, MVT::i32,
6375 Cond, DAG.getConstant(1, dl, MVT::i64), ISD::SETUGT);
6377 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
6383 MachineFunction &MF = DAG.getMachineFunction();
6384 if (canReuseLoadAddress(SINT, MVT::i64, RLI, DAG)) {
6385 Bits = DAG.getLoad(MVT::f64, dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
6386 false, RLI.IsInvariant, RLI.Alignment, RLI.AAInfo,
6388 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
6389 } else if (Subtarget.hasLFIWAX() &&
6390 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::SEXTLOAD)) {
6391 MachineMemOperand *MMO =
6392 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6393 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6394 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6395 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWAX, dl,
6396 DAG.getVTList(MVT::f64, MVT::Other),
6397 Ops, MVT::i32, MMO);
6398 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
6399 } else if (Subtarget.hasFPCVT() &&
6400 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::ZEXTLOAD)) {
6401 MachineMemOperand *MMO =
6402 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6403 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6404 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6405 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWZX, dl,
6406 DAG.getVTList(MVT::f64, MVT::Other),
6407 Ops, MVT::i32, MMO);
6408 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
6409 } else if (((Subtarget.hasLFIWAX() &&
6410 SINT.getOpcode() == ISD::SIGN_EXTEND) ||
6411 (Subtarget.hasFPCVT() &&
6412 SINT.getOpcode() == ISD::ZERO_EXTEND)) &&
6413 SINT.getOperand(0).getValueType() == MVT::i32) {
6414 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
6415 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
6417 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
6418 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6421 DAG.getStore(DAG.getEntryNode(), dl, SINT.getOperand(0), FIdx,
6422 MachinePointerInfo::getFixedStack(FrameIdx),
6425 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
6426 "Expected an i32 store");
6430 RLI.MPI = MachinePointerInfo::getFixedStack(FrameIdx);
6433 MachineMemOperand *MMO =
6434 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6435 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6436 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6437 Bits = DAG.getMemIntrinsicNode(SINT.getOpcode() == ISD::ZERO_EXTEND ?
6438 PPCISD::LFIWZX : PPCISD::LFIWAX,
6439 dl, DAG.getVTList(MVT::f64, MVT::Other),
6440 Ops, MVT::i32, MMO);
6442 Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
6444 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
6446 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
6447 FP = DAG.getNode(ISD::FP_ROUND, dl,
6448 MVT::f32, FP, DAG.getIntPtrConstant(0, dl));
6452 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
6453 "Unhandled INT_TO_FP type in custom expander!");
6454 // Since we only generate this in 64-bit mode, we can take advantage of
6455 // 64-bit registers. In particular, sign extend the input value into the
6456 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
6457 // then lfd it and fcfid it.
6458 MachineFunction &MF = DAG.getMachineFunction();
6459 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
6460 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
6463 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
6466 if (!(ReusingLoad = canReuseLoadAddress(Op.getOperand(0), MVT::i32, RLI,
6468 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
6469 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6471 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
6472 MachinePointerInfo::getFixedStack(FrameIdx),
6475 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
6476 "Expected an i32 store");
6480 RLI.MPI = MachinePointerInfo::getFixedStack(FrameIdx);
6484 MachineMemOperand *MMO =
6485 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6486 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6487 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6488 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
6489 PPCISD::LFIWZX : PPCISD::LFIWAX,
6490 dl, DAG.getVTList(MVT::f64, MVT::Other),
6491 Ops, MVT::i32, MMO);
6493 spliceIntoChain(RLI.ResChain, Ld.getValue(1), DAG);
6495 assert(Subtarget.isPPC64() &&
6496 "i32->FP without LFIWAX supported only on PPC64");
6498 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
6499 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6501 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
6504 // STD the extended value into the stack slot.
6505 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
6506 MachinePointerInfo::getFixedStack(FrameIdx),
6509 // Load the value as a double.
6510 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
6511 MachinePointerInfo::getFixedStack(FrameIdx),
6512 false, false, false, 0);
6515 // FCFID it and return it.
6516 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
6517 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
6518 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP,
6519 DAG.getIntPtrConstant(0, dl));
6523 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
6524 SelectionDAG &DAG) const {
6527 The rounding mode is in bits 30:31 of FPSR, and has the following
6534 FLT_ROUNDS, on the other hand, expects the following:
6541 To perform the conversion, we do:
6542 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
6545 MachineFunction &MF = DAG.getMachineFunction();
6546 EVT VT = Op.getValueType();
6547 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
6549 // Save FP Control Word to register
6551 MVT::f64, // return register
6552 MVT::Glue // unused in this context
6554 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
6556 // Save FP register to stack slot
6557 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
6558 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
6559 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
6560 StackSlot, MachinePointerInfo(), false, false,0);
6562 // Load FP Control Word from low 32 bits of stack slot.
6563 SDValue Four = DAG.getConstant(4, dl, PtrVT);
6564 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
6565 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
6566 false, false, false, 0);
6568 // Transform as necessary
6570 DAG.getNode(ISD::AND, dl, MVT::i32,
6571 CWD, DAG.getConstant(3, dl, MVT::i32));
6573 DAG.getNode(ISD::SRL, dl, MVT::i32,
6574 DAG.getNode(ISD::AND, dl, MVT::i32,
6575 DAG.getNode(ISD::XOR, dl, MVT::i32,
6576 CWD, DAG.getConstant(3, dl, MVT::i32)),
6577 DAG.getConstant(3, dl, MVT::i32)),
6578 DAG.getConstant(1, dl, MVT::i32));
6581 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
6583 return DAG.getNode((VT.getSizeInBits() < 16 ?
6584 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
6587 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
6588 EVT VT = Op.getValueType();
6589 unsigned BitWidth = VT.getSizeInBits();
6591 assert(Op.getNumOperands() == 3 &&
6592 VT == Op.getOperand(1).getValueType() &&
6595 // Expand into a bunch of logical ops. Note that these ops
6596 // depend on the PPC behavior for oversized shift amounts.
6597 SDValue Lo = Op.getOperand(0);
6598 SDValue Hi = Op.getOperand(1);
6599 SDValue Amt = Op.getOperand(2);
6600 EVT AmtVT = Amt.getValueType();
6602 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6603 DAG.getConstant(BitWidth, dl, AmtVT), Amt);
6604 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
6605 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
6606 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
6607 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6608 DAG.getConstant(-BitWidth, dl, AmtVT));
6609 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
6610 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
6611 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
6612 SDValue OutOps[] = { OutLo, OutHi };
6613 return DAG.getMergeValues(OutOps, dl);
6616 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
6617 EVT VT = Op.getValueType();
6619 unsigned BitWidth = VT.getSizeInBits();
6620 assert(Op.getNumOperands() == 3 &&
6621 VT == Op.getOperand(1).getValueType() &&
6624 // Expand into a bunch of logical ops. Note that these ops
6625 // depend on the PPC behavior for oversized shift amounts.
6626 SDValue Lo = Op.getOperand(0);
6627 SDValue Hi = Op.getOperand(1);
6628 SDValue Amt = Op.getOperand(2);
6629 EVT AmtVT = Amt.getValueType();
6631 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6632 DAG.getConstant(BitWidth, dl, AmtVT), Amt);
6633 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
6634 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
6635 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
6636 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6637 DAG.getConstant(-BitWidth, dl, AmtVT));
6638 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
6639 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
6640 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
6641 SDValue OutOps[] = { OutLo, OutHi };
6642 return DAG.getMergeValues(OutOps, dl);
6645 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
6647 EVT VT = Op.getValueType();
6648 unsigned BitWidth = VT.getSizeInBits();
6649 assert(Op.getNumOperands() == 3 &&
6650 VT == Op.getOperand(1).getValueType() &&
6653 // Expand into a bunch of logical ops, followed by a select_cc.
6654 SDValue Lo = Op.getOperand(0);
6655 SDValue Hi = Op.getOperand(1);
6656 SDValue Amt = Op.getOperand(2);
6657 EVT AmtVT = Amt.getValueType();
6659 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6660 DAG.getConstant(BitWidth, dl, AmtVT), Amt);
6661 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
6662 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
6663 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
6664 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6665 DAG.getConstant(-BitWidth, dl, AmtVT));
6666 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
6667 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
6668 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, dl, AmtVT),
6669 Tmp4, Tmp6, ISD::SETLE);
6670 SDValue OutOps[] = { OutLo, OutHi };
6671 return DAG.getMergeValues(OutOps, dl);
6674 //===----------------------------------------------------------------------===//
6675 // Vector related lowering.
6678 /// BuildSplatI - Build a canonical splati of Val with an element size of
6679 /// SplatSize. Cast the result to VT.
6680 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
6681 SelectionDAG &DAG, SDLoc dl) {
6682 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
6684 static const MVT VTys[] = { // canonical VT to use for each size.
6685 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
6688 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
6690 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
6694 EVT CanonicalVT = VTys[SplatSize-1];
6696 // Build a canonical splat for this value.
6697 SDValue Elt = DAG.getConstant(Val, dl, MVT::i32);
6698 SmallVector<SDValue, 8> Ops;
6699 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
6700 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
6701 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
6704 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
6705 /// specified intrinsic ID.
6706 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
6707 SelectionDAG &DAG, SDLoc dl,
6708 EVT DestVT = MVT::Other) {
6709 if (DestVT == MVT::Other) DestVT = Op.getValueType();
6710 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6711 DAG.getConstant(IID, dl, MVT::i32), Op);
6714 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
6715 /// specified intrinsic ID.
6716 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
6717 SelectionDAG &DAG, SDLoc dl,
6718 EVT DestVT = MVT::Other) {
6719 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
6720 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6721 DAG.getConstant(IID, dl, MVT::i32), LHS, RHS);
6724 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
6725 /// specified intrinsic ID.
6726 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
6727 SDValue Op2, SelectionDAG &DAG,
6728 SDLoc dl, EVT DestVT = MVT::Other) {
6729 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
6730 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6731 DAG.getConstant(IID, dl, MVT::i32), Op0, Op1, Op2);
6735 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
6736 /// amount. The result has the specified value type.
6737 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
6738 EVT VT, SelectionDAG &DAG, SDLoc dl) {
6739 // Force LHS/RHS to be the right type.
6740 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
6741 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
6744 for (unsigned i = 0; i != 16; ++i)
6746 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
6747 return DAG.getNode(ISD::BITCAST, dl, VT, T);
6750 // If this is a case we can't handle, return null and let the default
6751 // expansion code take care of it. If we CAN select this case, and if it
6752 // selects to a single instruction, return Op. Otherwise, if we can codegen
6753 // this case more efficiently than a constant pool load, lower it to the
6754 // sequence of ops that should be used.
6755 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
6756 SelectionDAG &DAG) const {
6758 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6759 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
6761 if (Subtarget.hasQPX() && Op.getValueType() == MVT::v4i1) {
6762 // We first build an i32 vector, load it into a QPX register,
6763 // then convert it to a floating-point vector and compare it
6764 // to a zero vector to get the boolean result.
6765 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6766 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
6767 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FrameIdx);
6768 EVT PtrVT = getPointerTy(DAG.getDataLayout());
6769 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6771 assert(BVN->getNumOperands() == 4 &&
6772 "BUILD_VECTOR for v4i1 does not have 4 operands");
6774 bool IsConst = true;
6775 for (unsigned i = 0; i < 4; ++i) {
6776 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF) continue;
6777 if (!isa<ConstantSDNode>(BVN->getOperand(i))) {
6785 ConstantFP::get(Type::getFloatTy(*DAG.getContext()), 1.0);
6787 ConstantFP::get(Type::getFloatTy(*DAG.getContext()), -1.0);
6789 SmallVector<Constant*, 4> CV(4, NegOne);
6790 for (unsigned i = 0; i < 4; ++i) {
6791 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF)
6792 CV[i] = UndefValue::get(Type::getFloatTy(*DAG.getContext()));
6793 else if (cast<ConstantSDNode>(BVN->getOperand(i))->
6794 getConstantIntValue()->isZero())
6800 Constant *CP = ConstantVector::get(CV);
6801 SDValue CPIdx = DAG.getConstantPool(CP, getPointerTy(DAG.getDataLayout()),
6802 16 /* alignment */);
6804 SmallVector<SDValue, 2> Ops;
6805 Ops.push_back(DAG.getEntryNode());
6806 Ops.push_back(CPIdx);
6808 SmallVector<EVT, 2> ValueVTs;
6809 ValueVTs.push_back(MVT::v4i1);
6810 ValueVTs.push_back(MVT::Other); // chain
6811 SDVTList VTs = DAG.getVTList(ValueVTs);
6813 return DAG.getMemIntrinsicNode(PPCISD::QVLFSb,
6814 dl, VTs, Ops, MVT::v4f32,
6815 MachinePointerInfo::getConstantPool());
6818 SmallVector<SDValue, 4> Stores;
6819 for (unsigned i = 0; i < 4; ++i) {
6820 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF) continue;
6822 unsigned Offset = 4*i;
6823 SDValue Idx = DAG.getConstant(Offset, dl, FIdx.getValueType());
6824 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
6826 unsigned StoreSize = BVN->getOperand(i).getValueType().getStoreSize();
6827 if (StoreSize > 4) {
6828 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
6829 BVN->getOperand(i), Idx,
6830 PtrInfo.getWithOffset(Offset),
6831 MVT::i32, false, false, 0));
6833 SDValue StoreValue = BVN->getOperand(i);
6835 StoreValue = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, StoreValue);
6837 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
6839 PtrInfo.getWithOffset(Offset),
6845 if (!Stores.empty())
6846 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
6848 StoreChain = DAG.getEntryNode();
6850 // Now load from v4i32 into the QPX register; this will extend it to
6851 // v4i64 but not yet convert it to a floating point. Nevertheless, this
6852 // is typed as v4f64 because the QPX register integer states are not
6853 // explicitly represented.
6855 SmallVector<SDValue, 2> Ops;
6856 Ops.push_back(StoreChain);
6857 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvlfiwz, dl, MVT::i32));
6858 Ops.push_back(FIdx);
6860 SmallVector<EVT, 2> ValueVTs;
6861 ValueVTs.push_back(MVT::v4f64);
6862 ValueVTs.push_back(MVT::Other); // chain
6863 SDVTList VTs = DAG.getVTList(ValueVTs);
6865 SDValue LoadedVect = DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN,
6866 dl, VTs, Ops, MVT::v4i32, PtrInfo);
6867 LoadedVect = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
6868 DAG.getConstant(Intrinsic::ppc_qpx_qvfcfidu, dl, MVT::i32),
6871 SDValue FPZeros = DAG.getConstantFP(0.0, dl, MVT::f64);
6872 FPZeros = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
6873 FPZeros, FPZeros, FPZeros, FPZeros);
6875 return DAG.getSetCC(dl, MVT::v4i1, LoadedVect, FPZeros, ISD::SETEQ);
6878 // All other QPX vectors are handled by generic code.
6879 if (Subtarget.hasQPX())
6882 // Check if this is a splat of a constant value.
6883 APInt APSplatBits, APSplatUndef;
6884 unsigned SplatBitSize;
6886 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
6887 HasAnyUndefs, 0, !Subtarget.isLittleEndian()) ||
6891 unsigned SplatBits = APSplatBits.getZExtValue();
6892 unsigned SplatUndef = APSplatUndef.getZExtValue();
6893 unsigned SplatSize = SplatBitSize / 8;
6895 // First, handle single instruction cases.
6898 if (SplatBits == 0) {
6899 // Canonicalize all zero vectors to be v4i32.
6900 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
6901 SDValue Z = DAG.getConstant(0, dl, MVT::i32);
6902 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
6903 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
6908 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
6909 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
6911 if (SextVal >= -16 && SextVal <= 15)
6912 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
6915 // Two instruction sequences.
6917 // If this value is in the range [-32,30] and is even, use:
6918 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
6919 // If this value is in the range [17,31] and is odd, use:
6920 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
6921 // If this value is in the range [-31,-17] and is odd, use:
6922 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
6923 // Note the last two are three-instruction sequences.
6924 if (SextVal >= -32 && SextVal <= 31) {
6925 // To avoid having these optimizations undone by constant folding,
6926 // we convert to a pseudo that will be expanded later into one of
6928 SDValue Elt = DAG.getConstant(SextVal, dl, MVT::i32);
6929 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
6930 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
6931 SDValue EltSize = DAG.getConstant(SplatSize, dl, MVT::i32);
6932 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
6933 if (VT == Op.getValueType())
6936 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
6939 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
6940 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
6942 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
6943 // Make -1 and vspltisw -1:
6944 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
6946 // Make the VSLW intrinsic, computing 0x8000_0000.
6947 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
6950 // xor by OnesV to invert it.
6951 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
6952 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6955 // Check to see if this is a wide variety of vsplti*, binop self cases.
6956 static const signed char SplatCsts[] = {
6957 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
6958 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
6961 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
6962 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
6963 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
6964 int i = SplatCsts[idx];
6966 // Figure out what shift amount will be used by altivec if shifted by i in
6968 unsigned TypeShiftAmt = i & (SplatBitSize-1);
6970 // vsplti + shl self.
6971 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
6972 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6973 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6974 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
6975 Intrinsic::ppc_altivec_vslw
6977 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6978 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6981 // vsplti + srl self.
6982 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
6983 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6984 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6985 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
6986 Intrinsic::ppc_altivec_vsrw
6988 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6989 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6992 // vsplti + sra self.
6993 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
6994 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6995 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6996 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
6997 Intrinsic::ppc_altivec_vsraw
6999 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
7000 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7003 // vsplti + rol self.
7004 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
7005 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
7006 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
7007 static const unsigned IIDs[] = { // Intrinsic to use for each size.
7008 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
7009 Intrinsic::ppc_altivec_vrlw
7011 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
7012 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7015 // t = vsplti c, result = vsldoi t, t, 1
7016 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
7017 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
7018 unsigned Amt = Subtarget.isLittleEndian() ? 15 : 1;
7019 return BuildVSLDOI(T, T, Amt, Op.getValueType(), DAG, dl);
7021 // t = vsplti c, result = vsldoi t, t, 2
7022 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
7023 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
7024 unsigned Amt = Subtarget.isLittleEndian() ? 14 : 2;
7025 return BuildVSLDOI(T, T, Amt, Op.getValueType(), DAG, dl);
7027 // t = vsplti c, result = vsldoi t, t, 3
7028 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
7029 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
7030 unsigned Amt = Subtarget.isLittleEndian() ? 13 : 3;
7031 return BuildVSLDOI(T, T, Amt, Op.getValueType(), DAG, dl);
7038 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
7039 /// the specified operations to build the shuffle.
7040 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
7041 SDValue RHS, SelectionDAG &DAG,
7043 unsigned OpNum = (PFEntry >> 26) & 0x0F;
7044 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
7045 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
7048 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
7060 if (OpNum == OP_COPY) {
7061 if (LHSID == (1*9+2)*9+3) return LHS;
7062 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
7066 SDValue OpLHS, OpRHS;
7067 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
7068 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
7072 default: llvm_unreachable("Unknown i32 permute!");
7074 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
7075 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
7076 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
7077 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
7080 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
7081 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
7082 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
7083 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
7086 for (unsigned i = 0; i != 16; ++i)
7087 ShufIdxs[i] = (i&3)+0;
7090 for (unsigned i = 0; i != 16; ++i)
7091 ShufIdxs[i] = (i&3)+4;
7094 for (unsigned i = 0; i != 16; ++i)
7095 ShufIdxs[i] = (i&3)+8;
7098 for (unsigned i = 0; i != 16; ++i)
7099 ShufIdxs[i] = (i&3)+12;
7102 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
7104 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
7106 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
7108 EVT VT = OpLHS.getValueType();
7109 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
7110 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
7111 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
7112 return DAG.getNode(ISD::BITCAST, dl, VT, T);
7115 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
7116 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
7117 /// return the code it can be lowered into. Worst case, it can always be
7118 /// lowered into a vperm.
7119 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
7120 SelectionDAG &DAG) const {
7122 SDValue V1 = Op.getOperand(0);
7123 SDValue V2 = Op.getOperand(1);
7124 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7125 EVT VT = Op.getValueType();
7126 bool isLittleEndian = Subtarget.isLittleEndian();
7128 if (Subtarget.hasQPX()) {
7129 if (VT.getVectorNumElements() != 4)
7132 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
7134 int AlignIdx = PPC::isQVALIGNIShuffleMask(SVOp);
7135 if (AlignIdx != -1) {
7136 return DAG.getNode(PPCISD::QVALIGNI, dl, VT, V1, V2,
7137 DAG.getConstant(AlignIdx, dl, MVT::i32));
7138 } else if (SVOp->isSplat()) {
7139 int SplatIdx = SVOp->getSplatIndex();
7140 if (SplatIdx >= 4) {
7145 // FIXME: If SplatIdx == 0 and the input came from a load, then there is
7148 return DAG.getNode(PPCISD::QVESPLATI, dl, VT, V1,
7149 DAG.getConstant(SplatIdx, dl, MVT::i32));
7152 // Lower this into a qvgpci/qvfperm pair.
7154 // Compute the qvgpci literal
7156 for (unsigned i = 0; i < 4; ++i) {
7157 int m = SVOp->getMaskElt(i);
7158 unsigned mm = m >= 0 ? (unsigned) m : i;
7159 idx |= mm << (3-i)*3;
7162 SDValue V3 = DAG.getNode(PPCISD::QVGPCI, dl, MVT::v4f64,
7163 DAG.getConstant(idx, dl, MVT::i32));
7164 return DAG.getNode(PPCISD::QVFPERM, dl, VT, V1, V2, V3);
7167 // Cases that are handled by instructions that take permute immediates
7168 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
7169 // selected by the instruction selector.
7170 if (V2.getOpcode() == ISD::UNDEF) {
7171 if (PPC::isSplatShuffleMask(SVOp, 1) ||
7172 PPC::isSplatShuffleMask(SVOp, 2) ||
7173 PPC::isSplatShuffleMask(SVOp, 4) ||
7174 PPC::isVPKUWUMShuffleMask(SVOp, 1, DAG) ||
7175 PPC::isVPKUHUMShuffleMask(SVOp, 1, DAG) ||
7176 PPC::isVPKUDUMShuffleMask(SVOp, 1, DAG) ||
7177 PPC::isVSLDOIShuffleMask(SVOp, 1, DAG) != -1 ||
7178 PPC::isVMRGLShuffleMask(SVOp, 1, 1, DAG) ||
7179 PPC::isVMRGLShuffleMask(SVOp, 2, 1, DAG) ||
7180 PPC::isVMRGLShuffleMask(SVOp, 4, 1, DAG) ||
7181 PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) ||
7182 PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) ||
7183 PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG) ||
7184 PPC::isVMRGEOShuffleMask(SVOp, true, 1, DAG) ||
7185 PPC::isVMRGEOShuffleMask(SVOp, false, 1, DAG)) {
7190 // Altivec has a variety of "shuffle immediates" that take two vector inputs
7191 // and produce a fixed permutation. If any of these match, do not lower to
7193 unsigned int ShuffleKind = isLittleEndian ? 2 : 0;
7194 if (PPC::isVPKUWUMShuffleMask(SVOp, ShuffleKind, DAG) ||
7195 PPC::isVPKUHUMShuffleMask(SVOp, ShuffleKind, DAG) ||
7196 PPC::isVPKUDUMShuffleMask(SVOp, ShuffleKind, DAG) ||
7197 PPC::isVSLDOIShuffleMask(SVOp, ShuffleKind, DAG) != -1 ||
7198 PPC::isVMRGLShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
7199 PPC::isVMRGLShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
7200 PPC::isVMRGLShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
7201 PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
7202 PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
7203 PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
7204 PPC::isVMRGEOShuffleMask(SVOp, true, ShuffleKind, DAG) ||
7205 PPC::isVMRGEOShuffleMask(SVOp, false, ShuffleKind, DAG))
7208 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
7209 // perfect shuffle table to emit an optimal matching sequence.
7210 ArrayRef<int> PermMask = SVOp->getMask();
7212 unsigned PFIndexes[4];
7213 bool isFourElementShuffle = true;
7214 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
7215 unsigned EltNo = 8; // Start out undef.
7216 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
7217 if (PermMask[i*4+j] < 0)
7218 continue; // Undef, ignore it.
7220 unsigned ByteSource = PermMask[i*4+j];
7221 if ((ByteSource & 3) != j) {
7222 isFourElementShuffle = false;
7227 EltNo = ByteSource/4;
7228 } else if (EltNo != ByteSource/4) {
7229 isFourElementShuffle = false;
7233 PFIndexes[i] = EltNo;
7236 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
7237 // perfect shuffle vector to determine if it is cost effective to do this as
7238 // discrete instructions, or whether we should use a vperm.
7239 // For now, we skip this for little endian until such time as we have a
7240 // little-endian perfect shuffle table.
7241 if (isFourElementShuffle && !isLittleEndian) {
7242 // Compute the index in the perfect shuffle table.
7243 unsigned PFTableIndex =
7244 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
7246 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
7247 unsigned Cost = (PFEntry >> 30);
7249 // Determining when to avoid vperm is tricky. Many things affect the cost
7250 // of vperm, particularly how many times the perm mask needs to be computed.
7251 // For example, if the perm mask can be hoisted out of a loop or is already
7252 // used (perhaps because there are multiple permutes with the same shuffle
7253 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
7254 // the loop requires an extra register.
7256 // As a compromise, we only emit discrete instructions if the shuffle can be
7257 // generated in 3 or fewer operations. When we have loop information
7258 // available, if this block is within a loop, we should avoid using vperm
7259 // for 3-operation perms and use a constant pool load instead.
7261 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
7264 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
7265 // vector that will get spilled to the constant pool.
7266 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
7268 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
7269 // that it is in input element units, not in bytes. Convert now.
7271 // For little endian, the order of the input vectors is reversed, and
7272 // the permutation mask is complemented with respect to 31. This is
7273 // necessary to produce proper semantics with the big-endian-biased vperm
7275 EVT EltVT = V1.getValueType().getVectorElementType();
7276 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
7278 SmallVector<SDValue, 16> ResultMask;
7279 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
7280 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
7282 for (unsigned j = 0; j != BytesPerElement; ++j)
7284 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement + j),
7287 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement + j, dl,
7291 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
7294 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
7297 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
7301 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
7302 /// altivec comparison. If it is, return true and fill in Opc/isDot with
7303 /// information about the intrinsic.
7304 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
7305 bool &isDot, const PPCSubtarget &Subtarget) {
7306 unsigned IntrinsicID =
7307 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
7310 switch (IntrinsicID) {
7311 default: return false;
7312 // Comparison predicates.
7313 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
7314 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
7315 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
7316 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
7317 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
7318 case Intrinsic::ppc_altivec_vcmpequd_p:
7319 if (Subtarget.hasP8Altivec()) {
7327 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
7328 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
7329 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
7330 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
7331 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
7332 case Intrinsic::ppc_altivec_vcmpgtsd_p:
7333 if (Subtarget.hasP8Altivec()) {
7341 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
7342 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
7343 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
7344 case Intrinsic::ppc_altivec_vcmpgtud_p:
7345 if (Subtarget.hasP8Altivec()) {
7354 // Normal Comparisons.
7355 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
7356 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
7357 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
7358 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
7359 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
7360 case Intrinsic::ppc_altivec_vcmpequd:
7361 if (Subtarget.hasP8Altivec()) {
7369 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
7370 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
7371 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
7372 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
7373 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
7374 case Intrinsic::ppc_altivec_vcmpgtsd:
7375 if (Subtarget.hasP8Altivec()) {
7383 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
7384 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
7385 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
7386 case Intrinsic::ppc_altivec_vcmpgtud:
7387 if (Subtarget.hasP8Altivec()) {
7399 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
7400 /// lower, do it, otherwise return null.
7401 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
7402 SelectionDAG &DAG) const {
7403 // If this is a lowered altivec predicate compare, CompareOpc is set to the
7404 // opcode number of the comparison.
7408 if (!getAltivecCompareInfo(Op, CompareOpc, isDot, Subtarget))
7409 return SDValue(); // Don't custom lower most intrinsics.
7411 // If this is a non-dot comparison, make the VCMP node and we are done.
7413 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
7414 Op.getOperand(1), Op.getOperand(2),
7415 DAG.getConstant(CompareOpc, dl, MVT::i32));
7416 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
7419 // Create the PPCISD altivec 'dot' comparison node.
7421 Op.getOperand(2), // LHS
7422 Op.getOperand(3), // RHS
7423 DAG.getConstant(CompareOpc, dl, MVT::i32)
7425 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
7426 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
7428 // Now that we have the comparison, emit a copy from the CR to a GPR.
7429 // This is flagged to the above dot comparison.
7430 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
7431 DAG.getRegister(PPC::CR6, MVT::i32),
7432 CompNode.getValue(1));
7434 // Unpack the result based on how the target uses it.
7435 unsigned BitNo; // Bit # of CR6.
7436 bool InvertBit; // Invert result?
7437 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
7438 default: // Can't happen, don't crash on invalid number though.
7439 case 0: // Return the value of the EQ bit of CR6.
7440 BitNo = 0; InvertBit = false;
7442 case 1: // Return the inverted value of the EQ bit of CR6.
7443 BitNo = 0; InvertBit = true;
7445 case 2: // Return the value of the LT bit of CR6.
7446 BitNo = 2; InvertBit = false;
7448 case 3: // Return the inverted value of the LT bit of CR6.
7449 BitNo = 2; InvertBit = true;
7453 // Shift the bit into the low position.
7454 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
7455 DAG.getConstant(8 - (3 - BitNo), dl, MVT::i32));
7457 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
7458 DAG.getConstant(1, dl, MVT::i32));
7460 // If we are supposed to, toggle the bit.
7462 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
7463 DAG.getConstant(1, dl, MVT::i32));
7467 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
7468 SelectionDAG &DAG) const {
7470 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
7471 // instructions), but for smaller types, we need to first extend up to v2i32
7472 // before doing going farther.
7473 if (Op.getValueType() == MVT::v2i64) {
7474 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
7475 if (ExtVT != MVT::v2i32) {
7476 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
7477 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
7478 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
7479 ExtVT.getVectorElementType(), 4)));
7480 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
7481 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
7482 DAG.getValueType(MVT::v2i32));
7491 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
7492 SelectionDAG &DAG) const {
7494 // Create a stack slot that is 16-byte aligned.
7495 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
7496 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
7497 EVT PtrVT = getPointerTy(DAG.getDataLayout());
7498 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
7500 // Store the input value into Value#0 of the stack slot.
7501 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
7502 Op.getOperand(0), FIdx, MachinePointerInfo(),
7505 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
7506 false, false, false, 0);
7509 SDValue PPCTargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
7510 SelectionDAG &DAG) const {
7512 SDNode *N = Op.getNode();
7514 assert(N->getOperand(0).getValueType() == MVT::v4i1 &&
7515 "Unknown extract_vector_elt type");
7517 SDValue Value = N->getOperand(0);
7519 // The first part of this is like the store lowering except that we don't
7520 // need to track the chain.
7522 // The values are now known to be -1 (false) or 1 (true). To convert this
7523 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
7524 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
7525 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
7527 // FIXME: We can make this an f32 vector, but the BUILD_VECTOR code needs to
7528 // understand how to form the extending load.
7529 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::f64);
7530 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
7531 FPHalfs, FPHalfs, FPHalfs, FPHalfs);
7533 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
7535 // Now convert to an integer and store.
7536 Value = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
7537 DAG.getConstant(Intrinsic::ppc_qpx_qvfctiwu, dl, MVT::i32),
7540 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
7541 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
7542 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FrameIdx);
7543 EVT PtrVT = getPointerTy(DAG.getDataLayout());
7544 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
7546 SDValue StoreChain = DAG.getEntryNode();
7547 SmallVector<SDValue, 2> Ops;
7548 Ops.push_back(StoreChain);
7549 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvstfiw, dl, MVT::i32));
7550 Ops.push_back(Value);
7551 Ops.push_back(FIdx);
7553 SmallVector<EVT, 2> ValueVTs;
7554 ValueVTs.push_back(MVT::Other); // chain
7555 SDVTList VTs = DAG.getVTList(ValueVTs);
7557 StoreChain = DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID,
7558 dl, VTs, Ops, MVT::v4i32, PtrInfo);
7560 // Extract the value requested.
7561 unsigned Offset = 4*cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
7562 SDValue Idx = DAG.getConstant(Offset, dl, FIdx.getValueType());
7563 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
7565 SDValue IntVal = DAG.getLoad(MVT::i32, dl, StoreChain, Idx,
7566 PtrInfo.getWithOffset(Offset),
7567 false, false, false, 0);
7569 if (!Subtarget.useCRBits())
7572 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, IntVal);
7575 /// Lowering for QPX v4i1 loads
7576 SDValue PPCTargetLowering::LowerVectorLoad(SDValue Op,
7577 SelectionDAG &DAG) const {
7579 LoadSDNode *LN = cast<LoadSDNode>(Op.getNode());
7580 SDValue LoadChain = LN->getChain();
7581 SDValue BasePtr = LN->getBasePtr();
7583 if (Op.getValueType() == MVT::v4f64 ||
7584 Op.getValueType() == MVT::v4f32) {
7585 EVT MemVT = LN->getMemoryVT();
7586 unsigned Alignment = LN->getAlignment();
7588 // If this load is properly aligned, then it is legal.
7589 if (Alignment >= MemVT.getStoreSize())
7592 EVT ScalarVT = Op.getValueType().getScalarType(),
7593 ScalarMemVT = MemVT.getScalarType();
7594 unsigned Stride = ScalarMemVT.getStoreSize();
7596 SmallVector<SDValue, 8> Vals, LoadChains;
7597 for (unsigned Idx = 0; Idx < 4; ++Idx) {
7599 if (ScalarVT != ScalarMemVT)
7601 DAG.getExtLoad(LN->getExtensionType(), dl, ScalarVT, LoadChain,
7603 LN->getPointerInfo().getWithOffset(Idx*Stride),
7604 ScalarMemVT, LN->isVolatile(), LN->isNonTemporal(),
7605 LN->isInvariant(), MinAlign(Alignment, Idx*Stride),
7609 DAG.getLoad(ScalarVT, dl, LoadChain, BasePtr,
7610 LN->getPointerInfo().getWithOffset(Idx*Stride),
7611 LN->isVolatile(), LN->isNonTemporal(),
7612 LN->isInvariant(), MinAlign(Alignment, Idx*Stride),
7615 if (Idx == 0 && LN->isIndexed()) {
7616 assert(LN->getAddressingMode() == ISD::PRE_INC &&
7617 "Unknown addressing mode on vector load");
7618 Load = DAG.getIndexedLoad(Load, dl, BasePtr, LN->getOffset(),
7619 LN->getAddressingMode());
7622 Vals.push_back(Load);
7623 LoadChains.push_back(Load.getValue(1));
7625 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
7626 DAG.getConstant(Stride, dl,
7627 BasePtr.getValueType()));
7630 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
7631 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl,
7632 Op.getValueType(), Vals);
7634 if (LN->isIndexed()) {
7635 SDValue RetOps[] = { Value, Vals[0].getValue(1), TF };
7636 return DAG.getMergeValues(RetOps, dl);
7639 SDValue RetOps[] = { Value, TF };
7640 return DAG.getMergeValues(RetOps, dl);
7643 assert(Op.getValueType() == MVT::v4i1 && "Unknown load to lower");
7644 assert(LN->isUnindexed() && "Indexed v4i1 loads are not supported");
7646 // To lower v4i1 from a byte array, we load the byte elements of the
7647 // vector and then reuse the BUILD_VECTOR logic.
7649 SmallVector<SDValue, 4> VectElmts, VectElmtChains;
7650 for (unsigned i = 0; i < 4; ++i) {
7651 SDValue Idx = DAG.getConstant(i, dl, BasePtr.getValueType());
7652 Idx = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, Idx);
7654 VectElmts.push_back(DAG.getExtLoad(ISD::EXTLOAD,
7655 dl, MVT::i32, LoadChain, Idx,
7656 LN->getPointerInfo().getWithOffset(i),
7657 MVT::i8 /* memory type */,
7658 LN->isVolatile(), LN->isNonTemporal(),
7660 1 /* alignment */, LN->getAAInfo()));
7661 VectElmtChains.push_back(VectElmts[i].getValue(1));
7664 LoadChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, VectElmtChains);
7665 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i1, VectElmts);
7667 SDValue RVals[] = { Value, LoadChain };
7668 return DAG.getMergeValues(RVals, dl);
7671 /// Lowering for QPX v4i1 stores
7672 SDValue PPCTargetLowering::LowerVectorStore(SDValue Op,
7673 SelectionDAG &DAG) const {
7675 StoreSDNode *SN = cast<StoreSDNode>(Op.getNode());
7676 SDValue StoreChain = SN->getChain();
7677 SDValue BasePtr = SN->getBasePtr();
7678 SDValue Value = SN->getValue();
7680 if (Value.getValueType() == MVT::v4f64 ||
7681 Value.getValueType() == MVT::v4f32) {
7682 EVT MemVT = SN->getMemoryVT();
7683 unsigned Alignment = SN->getAlignment();
7685 // If this store is properly aligned, then it is legal.
7686 if (Alignment >= MemVT.getStoreSize())
7689 EVT ScalarVT = Value.getValueType().getScalarType(),
7690 ScalarMemVT = MemVT.getScalarType();
7691 unsigned Stride = ScalarMemVT.getStoreSize();
7693 SmallVector<SDValue, 8> Stores;
7694 for (unsigned Idx = 0; Idx < 4; ++Idx) {
7695 SDValue Ex = DAG.getNode(
7696 ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, Value,
7697 DAG.getConstant(Idx, dl, getVectorIdxTy(DAG.getDataLayout())));
7699 if (ScalarVT != ScalarMemVT)
7701 DAG.getTruncStore(StoreChain, dl, Ex, BasePtr,
7702 SN->getPointerInfo().getWithOffset(Idx*Stride),
7703 ScalarMemVT, SN->isVolatile(), SN->isNonTemporal(),
7704 MinAlign(Alignment, Idx*Stride), SN->getAAInfo());
7707 DAG.getStore(StoreChain, dl, Ex, BasePtr,
7708 SN->getPointerInfo().getWithOffset(Idx*Stride),
7709 SN->isVolatile(), SN->isNonTemporal(),
7710 MinAlign(Alignment, Idx*Stride), SN->getAAInfo());
7712 if (Idx == 0 && SN->isIndexed()) {
7713 assert(SN->getAddressingMode() == ISD::PRE_INC &&
7714 "Unknown addressing mode on vector store");
7715 Store = DAG.getIndexedStore(Store, dl, BasePtr, SN->getOffset(),
7716 SN->getAddressingMode());
7719 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
7720 DAG.getConstant(Stride, dl,
7721 BasePtr.getValueType()));
7722 Stores.push_back(Store);
7725 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
7727 if (SN->isIndexed()) {
7728 SDValue RetOps[] = { TF, Stores[0].getValue(1) };
7729 return DAG.getMergeValues(RetOps, dl);
7735 assert(SN->isUnindexed() && "Indexed v4i1 stores are not supported");
7736 assert(Value.getValueType() == MVT::v4i1 && "Unknown store to lower");
7738 // The values are now known to be -1 (false) or 1 (true). To convert this
7739 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
7740 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
7741 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
7743 // FIXME: We can make this an f32 vector, but the BUILD_VECTOR code needs to
7744 // understand how to form the extending load.
7745 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::f64);
7746 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
7747 FPHalfs, FPHalfs, FPHalfs, FPHalfs);
7749 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
7751 // Now convert to an integer and store.
7752 Value = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
7753 DAG.getConstant(Intrinsic::ppc_qpx_qvfctiwu, dl, MVT::i32),
7756 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
7757 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
7758 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FrameIdx);
7759 EVT PtrVT = getPointerTy(DAG.getDataLayout());
7760 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
7762 SmallVector<SDValue, 2> Ops;
7763 Ops.push_back(StoreChain);
7764 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvstfiw, dl, MVT::i32));
7765 Ops.push_back(Value);
7766 Ops.push_back(FIdx);
7768 SmallVector<EVT, 2> ValueVTs;
7769 ValueVTs.push_back(MVT::Other); // chain
7770 SDVTList VTs = DAG.getVTList(ValueVTs);
7772 StoreChain = DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID,
7773 dl, VTs, Ops, MVT::v4i32, PtrInfo);
7775 // Move data into the byte array.
7776 SmallVector<SDValue, 4> Loads, LoadChains;
7777 for (unsigned i = 0; i < 4; ++i) {
7778 unsigned Offset = 4*i;
7779 SDValue Idx = DAG.getConstant(Offset, dl, FIdx.getValueType());
7780 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
7782 Loads.push_back(DAG.getLoad(MVT::i32, dl, StoreChain, Idx,
7783 PtrInfo.getWithOffset(Offset),
7784 false, false, false, 0));
7785 LoadChains.push_back(Loads[i].getValue(1));
7788 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
7790 SmallVector<SDValue, 4> Stores;
7791 for (unsigned i = 0; i < 4; ++i) {
7792 SDValue Idx = DAG.getConstant(i, dl, BasePtr.getValueType());
7793 Idx = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, Idx);
7795 Stores.push_back(DAG.getTruncStore(StoreChain, dl, Loads[i], Idx,
7796 SN->getPointerInfo().getWithOffset(i),
7797 MVT::i8 /* memory type */,
7798 SN->isNonTemporal(), SN->isVolatile(),
7799 1 /* alignment */, SN->getAAInfo()));
7802 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
7807 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
7809 if (Op.getValueType() == MVT::v4i32) {
7810 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
7812 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
7813 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
7815 SDValue RHSSwap = // = vrlw RHS, 16
7816 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
7818 // Shrinkify inputs to v8i16.
7819 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
7820 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
7821 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
7823 // Low parts multiplied together, generating 32-bit results (we ignore the
7825 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
7826 LHS, RHS, DAG, dl, MVT::v4i32);
7828 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
7829 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
7830 // Shift the high parts up 16 bits.
7831 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
7833 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
7834 } else if (Op.getValueType() == MVT::v8i16) {
7835 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
7837 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
7839 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
7840 LHS, RHS, Zero, DAG, dl);
7841 } else if (Op.getValueType() == MVT::v16i8) {
7842 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
7843 bool isLittleEndian = Subtarget.isLittleEndian();
7845 // Multiply the even 8-bit parts, producing 16-bit sums.
7846 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
7847 LHS, RHS, DAG, dl, MVT::v8i16);
7848 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
7850 // Multiply the odd 8-bit parts, producing 16-bit sums.
7851 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
7852 LHS, RHS, DAG, dl, MVT::v8i16);
7853 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
7855 // Merge the results together. Because vmuleub and vmuloub are
7856 // instructions with a big-endian bias, we must reverse the
7857 // element numbering and reverse the meaning of "odd" and "even"
7858 // when generating little endian code.
7860 for (unsigned i = 0; i != 8; ++i) {
7861 if (isLittleEndian) {
7863 Ops[i*2+1] = 2*i+16;
7866 Ops[i*2+1] = 2*i+1+16;
7870 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
7872 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
7874 llvm_unreachable("Unknown mul to lower!");
7878 /// LowerOperation - Provide custom lowering hooks for some operations.
7880 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7881 switch (Op.getOpcode()) {
7882 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
7883 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
7884 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
7885 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
7886 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
7887 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
7888 case ISD::SETCC: return LowerSETCC(Op, DAG);
7889 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
7890 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
7892 return LowerVASTART(Op, DAG, Subtarget);
7895 return LowerVAARG(Op, DAG, Subtarget);
7898 return LowerVACOPY(Op, DAG, Subtarget);
7900 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget);
7901 case ISD::DYNAMIC_STACKALLOC:
7902 return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget);
7904 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
7905 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
7907 case ISD::LOAD: return LowerLOAD(Op, DAG);
7908 case ISD::STORE: return LowerSTORE(Op, DAG);
7909 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
7910 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
7911 case ISD::FP_TO_UINT:
7912 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
7914 case ISD::UINT_TO_FP:
7915 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
7916 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
7918 // Lower 64-bit shifts.
7919 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
7920 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
7921 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
7923 // Vector-related lowering.
7924 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
7925 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
7926 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
7927 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
7928 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
7929 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
7930 case ISD::MUL: return LowerMUL(Op, DAG);
7932 // For counter-based loop handling.
7933 case ISD::INTRINSIC_W_CHAIN: return SDValue();
7935 // Frame & Return address.
7936 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
7937 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
7941 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
7942 SmallVectorImpl<SDValue>&Results,
7943 SelectionDAG &DAG) const {
7945 switch (N->getOpcode()) {
7947 llvm_unreachable("Do not know how to custom type legalize this operation!");
7948 case ISD::READCYCLECOUNTER: {
7949 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
7950 SDValue RTB = DAG.getNode(PPCISD::READ_TIME_BASE, dl, VTs, N->getOperand(0));
7952 Results.push_back(RTB);
7953 Results.push_back(RTB.getValue(1));
7954 Results.push_back(RTB.getValue(2));
7957 case ISD::INTRINSIC_W_CHAIN: {
7958 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
7959 Intrinsic::ppc_is_decremented_ctr_nonzero)
7962 assert(N->getValueType(0) == MVT::i1 &&
7963 "Unexpected result type for CTR decrement intrinsic");
7964 EVT SVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
7965 N->getValueType(0));
7966 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
7967 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
7970 Results.push_back(NewInt);
7971 Results.push_back(NewInt.getValue(1));
7975 if (!Subtarget.isSVR4ABI() || Subtarget.isPPC64())
7978 EVT VT = N->getValueType(0);
7980 if (VT == MVT::i64) {
7981 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget);
7983 Results.push_back(NewNode);
7984 Results.push_back(NewNode.getValue(1));
7988 case ISD::FP_ROUND_INREG: {
7989 assert(N->getValueType(0) == MVT::ppcf128);
7990 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
7991 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
7992 MVT::f64, N->getOperand(0),
7993 DAG.getIntPtrConstant(0, dl));
7994 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
7995 MVT::f64, N->getOperand(0),
7996 DAG.getIntPtrConstant(1, dl));
7998 // Add the two halves of the long double in round-to-zero mode.
7999 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
8001 // We know the low half is about to be thrown away, so just use something
8003 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
8007 case ISD::FP_TO_SINT:
8008 case ISD::FP_TO_UINT:
8009 // LowerFP_TO_INT() can only handle f32 and f64.
8010 if (N->getOperand(0).getValueType() == MVT::ppcf128)
8012 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
8018 //===----------------------------------------------------------------------===//
8019 // Other Lowering Code
8020 //===----------------------------------------------------------------------===//
8022 static Instruction* callIntrinsic(IRBuilder<> &Builder, Intrinsic::ID Id) {
8023 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
8024 Function *Func = Intrinsic::getDeclaration(M, Id);
8025 return Builder.CreateCall(Func, {});
8028 // The mappings for emitLeading/TrailingFence is taken from
8029 // http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
8030 Instruction* PPCTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
8031 AtomicOrdering Ord, bool IsStore,
8032 bool IsLoad) const {
8033 if (Ord == SequentiallyConsistent)
8034 return callIntrinsic(Builder, Intrinsic::ppc_sync);
8035 if (isAtLeastRelease(Ord))
8036 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
8040 Instruction* PPCTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
8041 AtomicOrdering Ord, bool IsStore,
8042 bool IsLoad) const {
8043 if (IsLoad && isAtLeastAcquire(Ord))
8044 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
8045 // FIXME: this is too conservative, a dependent branch + isync is enough.
8046 // See http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html and
8047 // http://www.rdrop.com/users/paulmck/scalability/paper/N2745r.2011.03.04a.html
8048 // and http://www.cl.cam.ac.uk/~pes20/cppppc/ for justification.
8053 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
8054 unsigned AtomicSize,
8055 unsigned BinOpcode) const {
8056 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
8057 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8059 auto LoadMnemonic = PPC::LDARX;
8060 auto StoreMnemonic = PPC::STDCX;
8061 switch (AtomicSize) {
8063 llvm_unreachable("Unexpected size of atomic entity");
8065 LoadMnemonic = PPC::LBARX;
8066 StoreMnemonic = PPC::STBCX;
8067 assert(Subtarget.hasPartwordAtomics() && "Call this only with size >=4");
8070 LoadMnemonic = PPC::LHARX;
8071 StoreMnemonic = PPC::STHCX;
8072 assert(Subtarget.hasPartwordAtomics() && "Call this only with size >=4");
8075 LoadMnemonic = PPC::LWARX;
8076 StoreMnemonic = PPC::STWCX;
8079 LoadMnemonic = PPC::LDARX;
8080 StoreMnemonic = PPC::STDCX;
8084 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8085 MachineFunction *F = BB->getParent();
8086 MachineFunction::iterator It = BB;
8089 unsigned dest = MI->getOperand(0).getReg();
8090 unsigned ptrA = MI->getOperand(1).getReg();
8091 unsigned ptrB = MI->getOperand(2).getReg();
8092 unsigned incr = MI->getOperand(3).getReg();
8093 DebugLoc dl = MI->getDebugLoc();
8095 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
8096 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8097 F->insert(It, loopMBB);
8098 F->insert(It, exitMBB);
8099 exitMBB->splice(exitMBB->begin(), BB,
8100 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8101 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8103 MachineRegisterInfo &RegInfo = F->getRegInfo();
8104 unsigned TmpReg = (!BinOpcode) ? incr :
8105 RegInfo.createVirtualRegister( AtomicSize == 8 ? &PPC::G8RCRegClass
8106 : &PPC::GPRCRegClass);
8110 // fallthrough --> loopMBB
8111 BB->addSuccessor(loopMBB);
8114 // l[wd]arx dest, ptr
8115 // add r0, dest, incr
8116 // st[wd]cx. r0, ptr
8118 // fallthrough --> exitMBB
8120 BuildMI(BB, dl, TII->get(LoadMnemonic), dest)
8121 .addReg(ptrA).addReg(ptrB);
8123 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
8124 BuildMI(BB, dl, TII->get(StoreMnemonic))
8125 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
8126 BuildMI(BB, dl, TII->get(PPC::BCC))
8127 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
8128 BB->addSuccessor(loopMBB);
8129 BB->addSuccessor(exitMBB);
8138 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
8139 MachineBasicBlock *BB,
8140 bool is8bit, // operation
8141 unsigned BinOpcode) const {
8142 // If we support part-word atomic mnemonics, just use them
8143 if (Subtarget.hasPartwordAtomics())
8144 return EmitAtomicBinary(MI, BB, is8bit ? 1 : 2, BinOpcode);
8146 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
8147 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8148 // In 64 bit mode we have to use 64 bits for addresses, even though the
8149 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
8150 // registers without caring whether they're 32 or 64, but here we're
8151 // doing actual arithmetic on the addresses.
8152 bool is64bit = Subtarget.isPPC64();
8153 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
8155 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8156 MachineFunction *F = BB->getParent();
8157 MachineFunction::iterator It = BB;
8160 unsigned dest = MI->getOperand(0).getReg();
8161 unsigned ptrA = MI->getOperand(1).getReg();
8162 unsigned ptrB = MI->getOperand(2).getReg();
8163 unsigned incr = MI->getOperand(3).getReg();
8164 DebugLoc dl = MI->getDebugLoc();
8166 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
8167 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8168 F->insert(It, loopMBB);
8169 F->insert(It, exitMBB);
8170 exitMBB->splice(exitMBB->begin(), BB,
8171 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8172 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8174 MachineRegisterInfo &RegInfo = F->getRegInfo();
8175 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
8176 : &PPC::GPRCRegClass;
8177 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
8178 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
8179 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
8180 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
8181 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
8182 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
8183 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
8184 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
8185 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
8186 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
8187 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
8189 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
8193 // fallthrough --> loopMBB
8194 BB->addSuccessor(loopMBB);
8196 // The 4-byte load must be aligned, while a char or short may be
8197 // anywhere in the word. Hence all this nasty bookkeeping code.
8198 // add ptr1, ptrA, ptrB [copy if ptrA==0]
8199 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
8200 // xori shift, shift1, 24 [16]
8201 // rlwinm ptr, ptr1, 0, 0, 29
8202 // slw incr2, incr, shift
8203 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
8204 // slw mask, mask2, shift
8206 // lwarx tmpDest, ptr
8207 // add tmp, tmpDest, incr2
8208 // andc tmp2, tmpDest, mask
8209 // and tmp3, tmp, mask
8210 // or tmp4, tmp3, tmp2
8213 // fallthrough --> exitMBB
8214 // srw dest, tmpDest, shift
8215 if (ptrA != ZeroReg) {
8216 Ptr1Reg = RegInfo.createVirtualRegister(RC);
8217 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
8218 .addReg(ptrA).addReg(ptrB);
8222 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
8223 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
8224 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
8225 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
8227 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
8228 .addReg(Ptr1Reg).addImm(0).addImm(61);
8230 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
8231 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
8232 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
8233 .addReg(incr).addReg(ShiftReg);
8235 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
8237 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
8238 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
8240 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
8241 .addReg(Mask2Reg).addReg(ShiftReg);
8244 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
8245 .addReg(ZeroReg).addReg(PtrReg);
8247 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
8248 .addReg(Incr2Reg).addReg(TmpDestReg);
8249 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
8250 .addReg(TmpDestReg).addReg(MaskReg);
8251 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
8252 .addReg(TmpReg).addReg(MaskReg);
8253 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
8254 .addReg(Tmp3Reg).addReg(Tmp2Reg);
8255 BuildMI(BB, dl, TII->get(PPC::STWCX))
8256 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
8257 BuildMI(BB, dl, TII->get(PPC::BCC))
8258 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
8259 BB->addSuccessor(loopMBB);
8260 BB->addSuccessor(exitMBB);
8265 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
8270 llvm::MachineBasicBlock*
8271 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
8272 MachineBasicBlock *MBB) const {
8273 DebugLoc DL = MI->getDebugLoc();
8274 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8276 MachineFunction *MF = MBB->getParent();
8277 MachineRegisterInfo &MRI = MF->getRegInfo();
8279 const BasicBlock *BB = MBB->getBasicBlock();
8280 MachineFunction::iterator I = MBB;
8284 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
8285 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
8287 unsigned DstReg = MI->getOperand(0).getReg();
8288 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
8289 assert(RC->hasType(MVT::i32) && "Invalid destination!");
8290 unsigned mainDstReg = MRI.createVirtualRegister(RC);
8291 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
8293 MVT PVT = getPointerTy(MF->getDataLayout());
8294 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
8295 "Invalid Pointer Size!");
8296 // For v = setjmp(buf), we generate
8299 // SjLjSetup mainMBB
8305 // buf[LabelOffset] = LR
8309 // v = phi(main, restore)
8312 MachineBasicBlock *thisMBB = MBB;
8313 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
8314 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
8315 MF->insert(I, mainMBB);
8316 MF->insert(I, sinkMBB);
8318 MachineInstrBuilder MIB;
8320 // Transfer the remainder of BB and its successor edges to sinkMBB.
8321 sinkMBB->splice(sinkMBB->begin(), MBB,
8322 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
8323 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
8325 // Note that the structure of the jmp_buf used here is not compatible
8326 // with that used by libc, and is not designed to be. Specifically, it
8327 // stores only those 'reserved' registers that LLVM does not otherwise
8328 // understand how to spill. Also, by convention, by the time this
8329 // intrinsic is called, Clang has already stored the frame address in the
8330 // first slot of the buffer and stack address in the third. Following the
8331 // X86 target code, we'll store the jump address in the second slot. We also
8332 // need to save the TOC pointer (R2) to handle jumps between shared
8333 // libraries, and that will be stored in the fourth slot. The thread
8334 // identifier (R13) is not affected.
8337 const int64_t LabelOffset = 1 * PVT.getStoreSize();
8338 const int64_t TOCOffset = 3 * PVT.getStoreSize();
8339 const int64_t BPOffset = 4 * PVT.getStoreSize();
8341 // Prepare IP either in reg.
8342 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
8343 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
8344 unsigned BufReg = MI->getOperand(1).getReg();
8346 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
8347 setUsesTOCBasePtr(*MBB->getParent());
8348 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
8352 MIB.setMemRefs(MMOBegin, MMOEnd);
8355 // Naked functions never have a base pointer, and so we use r1. For all
8356 // other functions, this decision must be delayed until during PEI.
8358 if (MF->getFunction()->hasFnAttribute(Attribute::Naked))
8359 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
8361 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
8363 MIB = BuildMI(*thisMBB, MI, DL,
8364 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
8368 MIB.setMemRefs(MMOBegin, MMOEnd);
8371 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
8372 const PPCRegisterInfo *TRI = Subtarget.getRegisterInfo();
8373 MIB.addRegMask(TRI->getNoPreservedMask());
8375 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
8377 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
8379 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
8381 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
8382 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
8387 BuildMI(mainMBB, DL,
8388 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
8391 if (Subtarget.isPPC64()) {
8392 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
8394 .addImm(LabelOffset)
8397 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
8399 .addImm(LabelOffset)
8403 MIB.setMemRefs(MMOBegin, MMOEnd);
8405 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
8406 mainMBB->addSuccessor(sinkMBB);
8409 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
8410 TII->get(PPC::PHI), DstReg)
8411 .addReg(mainDstReg).addMBB(mainMBB)
8412 .addReg(restoreDstReg).addMBB(thisMBB);
8414 MI->eraseFromParent();
8419 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
8420 MachineBasicBlock *MBB) const {
8421 DebugLoc DL = MI->getDebugLoc();
8422 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8424 MachineFunction *MF = MBB->getParent();
8425 MachineRegisterInfo &MRI = MF->getRegInfo();
8428 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
8429 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
8431 MVT PVT = getPointerTy(MF->getDataLayout());
8432 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
8433 "Invalid Pointer Size!");
8435 const TargetRegisterClass *RC =
8436 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
8437 unsigned Tmp = MRI.createVirtualRegister(RC);
8438 // Since FP is only updated here but NOT referenced, it's treated as GPR.
8439 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
8440 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
8444 : (Subtarget.isSVR4ABI() &&
8445 MF->getTarget().getRelocationModel() == Reloc::PIC_
8449 MachineInstrBuilder MIB;
8451 const int64_t LabelOffset = 1 * PVT.getStoreSize();
8452 const int64_t SPOffset = 2 * PVT.getStoreSize();
8453 const int64_t TOCOffset = 3 * PVT.getStoreSize();
8454 const int64_t BPOffset = 4 * PVT.getStoreSize();
8456 unsigned BufReg = MI->getOperand(0).getReg();
8458 // Reload FP (the jumped-to function may not have had a
8459 // frame pointer, and if so, then its r31 will be restored
8461 if (PVT == MVT::i64) {
8462 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
8466 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
8470 MIB.setMemRefs(MMOBegin, MMOEnd);
8473 if (PVT == MVT::i64) {
8474 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
8475 .addImm(LabelOffset)
8478 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
8479 .addImm(LabelOffset)
8482 MIB.setMemRefs(MMOBegin, MMOEnd);
8485 if (PVT == MVT::i64) {
8486 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
8490 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
8494 MIB.setMemRefs(MMOBegin, MMOEnd);
8497 if (PVT == MVT::i64) {
8498 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
8502 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
8506 MIB.setMemRefs(MMOBegin, MMOEnd);
8509 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
8510 setUsesTOCBasePtr(*MBB->getParent());
8511 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
8515 MIB.setMemRefs(MMOBegin, MMOEnd);
8519 BuildMI(*MBB, MI, DL,
8520 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
8521 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
8523 MI->eraseFromParent();
8528 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
8529 MachineBasicBlock *BB) const {
8530 if (MI->getOpcode() == TargetOpcode::STACKMAP ||
8531 MI->getOpcode() == TargetOpcode::PATCHPOINT) {
8532 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI() &&
8533 MI->getOpcode() == TargetOpcode::PATCHPOINT) {
8534 // Call lowering should have added an r2 operand to indicate a dependence
8535 // on the TOC base pointer value. It can't however, because there is no
8536 // way to mark the dependence as implicit there, and so the stackmap code
8537 // will confuse it with a regular operand. Instead, add the dependence
8539 setUsesTOCBasePtr(*BB->getParent());
8540 MI->addOperand(MachineOperand::CreateReg(PPC::X2, false, true));
8543 return emitPatchPoint(MI, BB);
8546 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
8547 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
8548 return emitEHSjLjSetJmp(MI, BB);
8549 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
8550 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
8551 return emitEHSjLjLongJmp(MI, BB);
8554 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8556 // To "insert" these instructions we actually have to insert their
8557 // control-flow patterns.
8558 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8559 MachineFunction::iterator It = BB;
8562 MachineFunction *F = BB->getParent();
8564 if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
8565 MI->getOpcode() == PPC::SELECT_CC_I8 ||
8566 MI->getOpcode() == PPC::SELECT_I4 ||
8567 MI->getOpcode() == PPC::SELECT_I8)) {
8568 SmallVector<MachineOperand, 2> Cond;
8569 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
8570 MI->getOpcode() == PPC::SELECT_CC_I8)
8571 Cond.push_back(MI->getOperand(4));
8573 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
8574 Cond.push_back(MI->getOperand(1));
8576 DebugLoc dl = MI->getDebugLoc();
8577 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
8578 Cond, MI->getOperand(2).getReg(),
8579 MI->getOperand(3).getReg());
8580 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
8581 MI->getOpcode() == PPC::SELECT_CC_I8 ||
8582 MI->getOpcode() == PPC::SELECT_CC_F4 ||
8583 MI->getOpcode() == PPC::SELECT_CC_F8 ||
8584 MI->getOpcode() == PPC::SELECT_CC_QFRC ||
8585 MI->getOpcode() == PPC::SELECT_CC_QSRC ||
8586 MI->getOpcode() == PPC::SELECT_CC_QBRC ||
8587 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
8588 MI->getOpcode() == PPC::SELECT_CC_VSFRC ||
8589 MI->getOpcode() == PPC::SELECT_CC_VSSRC ||
8590 MI->getOpcode() == PPC::SELECT_CC_VSRC ||
8591 MI->getOpcode() == PPC::SELECT_I4 ||
8592 MI->getOpcode() == PPC::SELECT_I8 ||
8593 MI->getOpcode() == PPC::SELECT_F4 ||
8594 MI->getOpcode() == PPC::SELECT_F8 ||
8595 MI->getOpcode() == PPC::SELECT_QFRC ||
8596 MI->getOpcode() == PPC::SELECT_QSRC ||
8597 MI->getOpcode() == PPC::SELECT_QBRC ||
8598 MI->getOpcode() == PPC::SELECT_VRRC ||
8599 MI->getOpcode() == PPC::SELECT_VSFRC ||
8600 MI->getOpcode() == PPC::SELECT_VSSRC ||
8601 MI->getOpcode() == PPC::SELECT_VSRC) {
8602 // The incoming instruction knows the destination vreg to set, the
8603 // condition code register to branch on, the true/false values to
8604 // select between, and a branch opcode to use.
8609 // cmpTY ccX, r1, r2
8611 // fallthrough --> copy0MBB
8612 MachineBasicBlock *thisMBB = BB;
8613 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
8614 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8615 DebugLoc dl = MI->getDebugLoc();
8616 F->insert(It, copy0MBB);
8617 F->insert(It, sinkMBB);
8619 // Transfer the remainder of BB and its successor edges to sinkMBB.
8620 sinkMBB->splice(sinkMBB->begin(), BB,
8621 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8622 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
8624 // Next, add the true and fallthrough blocks as its successors.
8625 BB->addSuccessor(copy0MBB);
8626 BB->addSuccessor(sinkMBB);
8628 if (MI->getOpcode() == PPC::SELECT_I4 ||
8629 MI->getOpcode() == PPC::SELECT_I8 ||
8630 MI->getOpcode() == PPC::SELECT_F4 ||
8631 MI->getOpcode() == PPC::SELECT_F8 ||
8632 MI->getOpcode() == PPC::SELECT_QFRC ||
8633 MI->getOpcode() == PPC::SELECT_QSRC ||
8634 MI->getOpcode() == PPC::SELECT_QBRC ||
8635 MI->getOpcode() == PPC::SELECT_VRRC ||
8636 MI->getOpcode() == PPC::SELECT_VSFRC ||
8637 MI->getOpcode() == PPC::SELECT_VSSRC ||
8638 MI->getOpcode() == PPC::SELECT_VSRC) {
8639 BuildMI(BB, dl, TII->get(PPC::BC))
8640 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
8642 unsigned SelectPred = MI->getOperand(4).getImm();
8643 BuildMI(BB, dl, TII->get(PPC::BCC))
8644 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
8648 // %FalseValue = ...
8649 // # fallthrough to sinkMBB
8652 // Update machine-CFG edges
8653 BB->addSuccessor(sinkMBB);
8656 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
8659 BuildMI(*BB, BB->begin(), dl,
8660 TII->get(PPC::PHI), MI->getOperand(0).getReg())
8661 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
8662 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
8663 } else if (MI->getOpcode() == PPC::ReadTB) {
8664 // To read the 64-bit time-base register on a 32-bit target, we read the
8665 // two halves. Should the counter have wrapped while it was being read, we
8666 // need to try again.
8669 // mfspr Rx,TBU # load from TBU
8670 // mfspr Ry,TB # load from TB
8671 // mfspr Rz,TBU # load from TBU
8672 // cmpw crX,Rx,Rz # check if ‘old’=’new’
8673 // bne readLoop # branch if they're not equal
8676 MachineBasicBlock *readMBB = F->CreateMachineBasicBlock(LLVM_BB);
8677 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8678 DebugLoc dl = MI->getDebugLoc();
8679 F->insert(It, readMBB);
8680 F->insert(It, sinkMBB);
8682 // Transfer the remainder of BB and its successor edges to sinkMBB.
8683 sinkMBB->splice(sinkMBB->begin(), BB,
8684 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8685 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
8687 BB->addSuccessor(readMBB);
8690 MachineRegisterInfo &RegInfo = F->getRegInfo();
8691 unsigned ReadAgainReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
8692 unsigned LoReg = MI->getOperand(0).getReg();
8693 unsigned HiReg = MI->getOperand(1).getReg();
8695 BuildMI(BB, dl, TII->get(PPC::MFSPR), HiReg).addImm(269);
8696 BuildMI(BB, dl, TII->get(PPC::MFSPR), LoReg).addImm(268);
8697 BuildMI(BB, dl, TII->get(PPC::MFSPR), ReadAgainReg).addImm(269);
8699 unsigned CmpReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
8701 BuildMI(BB, dl, TII->get(PPC::CMPW), CmpReg)
8702 .addReg(HiReg).addReg(ReadAgainReg);
8703 BuildMI(BB, dl, TII->get(PPC::BCC))
8704 .addImm(PPC::PRED_NE).addReg(CmpReg).addMBB(readMBB);
8706 BB->addSuccessor(readMBB);
8707 BB->addSuccessor(sinkMBB);
8709 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
8710 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
8711 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
8712 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
8713 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
8714 BB = EmitAtomicBinary(MI, BB, 4, PPC::ADD4);
8715 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
8716 BB = EmitAtomicBinary(MI, BB, 8, PPC::ADD8);
8718 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
8719 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
8720 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
8721 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
8722 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
8723 BB = EmitAtomicBinary(MI, BB, 4, PPC::AND);
8724 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
8725 BB = EmitAtomicBinary(MI, BB, 8, PPC::AND8);
8727 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
8728 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
8729 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
8730 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
8731 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
8732 BB = EmitAtomicBinary(MI, BB, 4, PPC::OR);
8733 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
8734 BB = EmitAtomicBinary(MI, BB, 8, PPC::OR8);
8736 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
8737 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
8738 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
8739 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
8740 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
8741 BB = EmitAtomicBinary(MI, BB, 4, PPC::XOR);
8742 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
8743 BB = EmitAtomicBinary(MI, BB, 8, PPC::XOR8);
8745 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
8746 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND);
8747 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
8748 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND);
8749 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
8750 BB = EmitAtomicBinary(MI, BB, 4, PPC::NAND);
8751 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
8752 BB = EmitAtomicBinary(MI, BB, 8, PPC::NAND8);
8754 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
8755 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
8756 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
8757 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
8758 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
8759 BB = EmitAtomicBinary(MI, BB, 4, PPC::SUBF);
8760 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
8761 BB = EmitAtomicBinary(MI, BB, 8, PPC::SUBF8);
8763 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
8764 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
8765 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
8766 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
8767 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
8768 BB = EmitAtomicBinary(MI, BB, 4, 0);
8769 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
8770 BB = EmitAtomicBinary(MI, BB, 8, 0);
8772 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
8773 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64 ||
8774 (Subtarget.hasPartwordAtomics() &&
8775 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8) ||
8776 (Subtarget.hasPartwordAtomics() &&
8777 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16)) {
8778 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
8780 auto LoadMnemonic = PPC::LDARX;
8781 auto StoreMnemonic = PPC::STDCX;
8782 switch(MI->getOpcode()) {
8784 llvm_unreachable("Compare and swap of unknown size");
8785 case PPC::ATOMIC_CMP_SWAP_I8:
8786 LoadMnemonic = PPC::LBARX;
8787 StoreMnemonic = PPC::STBCX;
8788 assert(Subtarget.hasPartwordAtomics() && "No support partword atomics.");
8790 case PPC::ATOMIC_CMP_SWAP_I16:
8791 LoadMnemonic = PPC::LHARX;
8792 StoreMnemonic = PPC::STHCX;
8793 assert(Subtarget.hasPartwordAtomics() && "No support partword atomics.");
8795 case PPC::ATOMIC_CMP_SWAP_I32:
8796 LoadMnemonic = PPC::LWARX;
8797 StoreMnemonic = PPC::STWCX;
8799 case PPC::ATOMIC_CMP_SWAP_I64:
8800 LoadMnemonic = PPC::LDARX;
8801 StoreMnemonic = PPC::STDCX;
8804 unsigned dest = MI->getOperand(0).getReg();
8805 unsigned ptrA = MI->getOperand(1).getReg();
8806 unsigned ptrB = MI->getOperand(2).getReg();
8807 unsigned oldval = MI->getOperand(3).getReg();
8808 unsigned newval = MI->getOperand(4).getReg();
8809 DebugLoc dl = MI->getDebugLoc();
8811 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
8812 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
8813 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
8814 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8815 F->insert(It, loop1MBB);
8816 F->insert(It, loop2MBB);
8817 F->insert(It, midMBB);
8818 F->insert(It, exitMBB);
8819 exitMBB->splice(exitMBB->begin(), BB,
8820 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8821 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8825 // fallthrough --> loopMBB
8826 BB->addSuccessor(loop1MBB);
8829 // l[bhwd]arx dest, ptr
8830 // cmp[wd] dest, oldval
8833 // st[bhwd]cx. newval, ptr
8837 // st[bhwd]cx. dest, ptr
8840 BuildMI(BB, dl, TII->get(LoadMnemonic), dest)
8841 .addReg(ptrA).addReg(ptrB);
8842 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
8843 .addReg(oldval).addReg(dest);
8844 BuildMI(BB, dl, TII->get(PPC::BCC))
8845 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
8846 BB->addSuccessor(loop2MBB);
8847 BB->addSuccessor(midMBB);
8850 BuildMI(BB, dl, TII->get(StoreMnemonic))
8851 .addReg(newval).addReg(ptrA).addReg(ptrB);
8852 BuildMI(BB, dl, TII->get(PPC::BCC))
8853 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
8854 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
8855 BB->addSuccessor(loop1MBB);
8856 BB->addSuccessor(exitMBB);
8859 BuildMI(BB, dl, TII->get(StoreMnemonic))
8860 .addReg(dest).addReg(ptrA).addReg(ptrB);
8861 BB->addSuccessor(exitMBB);
8866 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
8867 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
8868 // We must use 64-bit registers for addresses when targeting 64-bit,
8869 // since we're actually doing arithmetic on them. Other registers
8871 bool is64bit = Subtarget.isPPC64();
8872 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
8874 unsigned dest = MI->getOperand(0).getReg();
8875 unsigned ptrA = MI->getOperand(1).getReg();
8876 unsigned ptrB = MI->getOperand(2).getReg();
8877 unsigned oldval = MI->getOperand(3).getReg();
8878 unsigned newval = MI->getOperand(4).getReg();
8879 DebugLoc dl = MI->getDebugLoc();
8881 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
8882 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
8883 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
8884 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8885 F->insert(It, loop1MBB);
8886 F->insert(It, loop2MBB);
8887 F->insert(It, midMBB);
8888 F->insert(It, exitMBB);
8889 exitMBB->splice(exitMBB->begin(), BB,
8890 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8891 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8893 MachineRegisterInfo &RegInfo = F->getRegInfo();
8894 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
8895 : &PPC::GPRCRegClass;
8896 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
8897 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
8898 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
8899 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
8900 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
8901 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
8902 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
8903 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
8904 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
8905 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
8906 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
8907 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
8908 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
8910 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
8911 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
8914 // fallthrough --> loopMBB
8915 BB->addSuccessor(loop1MBB);
8917 // The 4-byte load must be aligned, while a char or short may be
8918 // anywhere in the word. Hence all this nasty bookkeeping code.
8919 // add ptr1, ptrA, ptrB [copy if ptrA==0]
8920 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
8921 // xori shift, shift1, 24 [16]
8922 // rlwinm ptr, ptr1, 0, 0, 29
8923 // slw newval2, newval, shift
8924 // slw oldval2, oldval,shift
8925 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
8926 // slw mask, mask2, shift
8927 // and newval3, newval2, mask
8928 // and oldval3, oldval2, mask
8930 // lwarx tmpDest, ptr
8931 // and tmp, tmpDest, mask
8932 // cmpw tmp, oldval3
8935 // andc tmp2, tmpDest, mask
8936 // or tmp4, tmp2, newval3
8941 // stwcx. tmpDest, ptr
8943 // srw dest, tmpDest, shift
8944 if (ptrA != ZeroReg) {
8945 Ptr1Reg = RegInfo.createVirtualRegister(RC);
8946 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
8947 .addReg(ptrA).addReg(ptrB);
8951 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
8952 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
8953 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
8954 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
8956 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
8957 .addReg(Ptr1Reg).addImm(0).addImm(61);
8959 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
8960 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
8961 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
8962 .addReg(newval).addReg(ShiftReg);
8963 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
8964 .addReg(oldval).addReg(ShiftReg);
8966 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
8968 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
8969 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
8970 .addReg(Mask3Reg).addImm(65535);
8972 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
8973 .addReg(Mask2Reg).addReg(ShiftReg);
8974 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
8975 .addReg(NewVal2Reg).addReg(MaskReg);
8976 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
8977 .addReg(OldVal2Reg).addReg(MaskReg);
8980 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
8981 .addReg(ZeroReg).addReg(PtrReg);
8982 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
8983 .addReg(TmpDestReg).addReg(MaskReg);
8984 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
8985 .addReg(TmpReg).addReg(OldVal3Reg);
8986 BuildMI(BB, dl, TII->get(PPC::BCC))
8987 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
8988 BB->addSuccessor(loop2MBB);
8989 BB->addSuccessor(midMBB);
8992 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
8993 .addReg(TmpDestReg).addReg(MaskReg);
8994 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
8995 .addReg(Tmp2Reg).addReg(NewVal3Reg);
8996 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
8997 .addReg(ZeroReg).addReg(PtrReg);
8998 BuildMI(BB, dl, TII->get(PPC::BCC))
8999 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
9000 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
9001 BB->addSuccessor(loop1MBB);
9002 BB->addSuccessor(exitMBB);
9005 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
9006 .addReg(ZeroReg).addReg(PtrReg);
9007 BB->addSuccessor(exitMBB);
9012 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
9014 } else if (MI->getOpcode() == PPC::FADDrtz) {
9015 // This pseudo performs an FADD with rounding mode temporarily forced
9016 // to round-to-zero. We emit this via custom inserter since the FPSCR
9017 // is not modeled at the SelectionDAG level.
9018 unsigned Dest = MI->getOperand(0).getReg();
9019 unsigned Src1 = MI->getOperand(1).getReg();
9020 unsigned Src2 = MI->getOperand(2).getReg();
9021 DebugLoc dl = MI->getDebugLoc();
9023 MachineRegisterInfo &RegInfo = F->getRegInfo();
9024 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
9026 // Save FPSCR value.
9027 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
9029 // Set rounding mode to round-to-zero.
9030 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
9031 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
9033 // Perform addition.
9034 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
9036 // Restore FPSCR value.
9037 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSFb)).addImm(1).addReg(MFFSReg);
9038 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
9039 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
9040 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
9041 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
9042 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
9043 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
9044 PPC::ANDIo8 : PPC::ANDIo;
9045 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
9046 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
9048 MachineRegisterInfo &RegInfo = F->getRegInfo();
9049 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
9050 &PPC::GPRCRegClass :
9051 &PPC::G8RCRegClass);
9053 DebugLoc dl = MI->getDebugLoc();
9054 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
9055 .addReg(MI->getOperand(1).getReg()).addImm(1);
9056 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
9057 MI->getOperand(0).getReg())
9058 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
9059 } else if (MI->getOpcode() == PPC::TCHECK_RET) {
9060 DebugLoc Dl = MI->getDebugLoc();
9061 MachineRegisterInfo &RegInfo = F->getRegInfo();
9062 unsigned CRReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
9063 BuildMI(*BB, MI, Dl, TII->get(PPC::TCHECK), CRReg);
9066 llvm_unreachable("Unexpected instr type to insert");
9069 MI->eraseFromParent(); // The pseudo instruction is gone now.
9073 //===----------------------------------------------------------------------===//
9074 // Target Optimization Hooks
9075 //===----------------------------------------------------------------------===//
9077 static std::string getRecipOp(const char *Base, EVT VT) {
9078 std::string RecipOp(Base);
9079 if (VT.getScalarType() == MVT::f64)
9085 RecipOp = "vec-" + RecipOp;
9090 SDValue PPCTargetLowering::getRsqrtEstimate(SDValue Operand,
9091 DAGCombinerInfo &DCI,
9092 unsigned &RefinementSteps,
9093 bool &UseOneConstNR) const {
9094 EVT VT = Operand.getValueType();
9095 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
9096 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
9097 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
9098 (VT == MVT::v2f64 && Subtarget.hasVSX()) ||
9099 (VT == MVT::v4f32 && Subtarget.hasQPX()) ||
9100 (VT == MVT::v4f64 && Subtarget.hasQPX())) {
9101 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
9102 std::string RecipOp = getRecipOp("sqrt", VT);
9103 if (!Recips.isEnabled(RecipOp))
9106 RefinementSteps = Recips.getRefinementSteps(RecipOp);
9107 UseOneConstNR = true;
9108 return DCI.DAG.getNode(PPCISD::FRSQRTE, SDLoc(Operand), VT, Operand);
9113 SDValue PPCTargetLowering::getRecipEstimate(SDValue Operand,
9114 DAGCombinerInfo &DCI,
9115 unsigned &RefinementSteps) const {
9116 EVT VT = Operand.getValueType();
9117 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
9118 (VT == MVT::f64 && Subtarget.hasFRE()) ||
9119 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
9120 (VT == MVT::v2f64 && Subtarget.hasVSX()) ||
9121 (VT == MVT::v4f32 && Subtarget.hasQPX()) ||
9122 (VT == MVT::v4f64 && Subtarget.hasQPX())) {
9123 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
9124 std::string RecipOp = getRecipOp("div", VT);
9125 if (!Recips.isEnabled(RecipOp))
9128 RefinementSteps = Recips.getRefinementSteps(RecipOp);
9129 return DCI.DAG.getNode(PPCISD::FRE, SDLoc(Operand), VT, Operand);
9134 bool PPCTargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
9135 // Note: This functionality is used only when unsafe-fp-math is enabled, and
9136 // on cores with reciprocal estimates (which are used when unsafe-fp-math is
9137 // enabled for division), this functionality is redundant with the default
9138 // combiner logic (once the division -> reciprocal/multiply transformation
9139 // has taken place). As a result, this matters more for older cores than for
9142 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
9143 // reciprocal if there are two or more FDIVs (for embedded cores with only
9144 // one FP pipeline) for three or more FDIVs (for generic OOO cores).
9145 switch (Subtarget.getDarwinDirective()) {
9147 return NumUsers > 2;
9150 case PPC::DIR_E500mc:
9151 case PPC::DIR_E5500:
9152 return NumUsers > 1;
9156 static bool isConsecutiveLSLoc(SDValue Loc, EVT VT, LSBaseSDNode *Base,
9157 unsigned Bytes, int Dist,
9158 SelectionDAG &DAG) {
9159 if (VT.getSizeInBits() / 8 != Bytes)
9162 SDValue BaseLoc = Base->getBasePtr();
9163 if (Loc.getOpcode() == ISD::FrameIndex) {
9164 if (BaseLoc.getOpcode() != ISD::FrameIndex)
9166 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9167 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
9168 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
9169 int FS = MFI->getObjectSize(FI);
9170 int BFS = MFI->getObjectSize(BFI);
9171 if (FS != BFS || FS != (int)Bytes) return false;
9172 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
9176 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
9177 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
9180 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9181 const GlobalValue *GV1 = nullptr;
9182 const GlobalValue *GV2 = nullptr;
9183 int64_t Offset1 = 0;
9184 int64_t Offset2 = 0;
9185 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
9186 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
9187 if (isGA1 && isGA2 && GV1 == GV2)
9188 return Offset1 == (Offset2 + Dist*Bytes);
9192 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
9193 // not enforce equality of the chain operands.
9194 static bool isConsecutiveLS(SDNode *N, LSBaseSDNode *Base,
9195 unsigned Bytes, int Dist,
9196 SelectionDAG &DAG) {
9197 if (LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(N)) {
9198 EVT VT = LS->getMemoryVT();
9199 SDValue Loc = LS->getBasePtr();
9200 return isConsecutiveLSLoc(Loc, VT, Base, Bytes, Dist, DAG);
9203 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
9205 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9206 default: return false;
9207 case Intrinsic::ppc_qpx_qvlfd:
9208 case Intrinsic::ppc_qpx_qvlfda:
9211 case Intrinsic::ppc_qpx_qvlfs:
9212 case Intrinsic::ppc_qpx_qvlfsa:
9215 case Intrinsic::ppc_qpx_qvlfcd:
9216 case Intrinsic::ppc_qpx_qvlfcda:
9219 case Intrinsic::ppc_qpx_qvlfcs:
9220 case Intrinsic::ppc_qpx_qvlfcsa:
9223 case Intrinsic::ppc_qpx_qvlfiwa:
9224 case Intrinsic::ppc_qpx_qvlfiwz:
9225 case Intrinsic::ppc_altivec_lvx:
9226 case Intrinsic::ppc_altivec_lvxl:
9227 case Intrinsic::ppc_vsx_lxvw4x:
9230 case Intrinsic::ppc_vsx_lxvd2x:
9233 case Intrinsic::ppc_altivec_lvebx:
9236 case Intrinsic::ppc_altivec_lvehx:
9239 case Intrinsic::ppc_altivec_lvewx:
9244 return isConsecutiveLSLoc(N->getOperand(2), VT, Base, Bytes, Dist, DAG);
9247 if (N->getOpcode() == ISD::INTRINSIC_VOID) {
9249 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9250 default: return false;
9251 case Intrinsic::ppc_qpx_qvstfd:
9252 case Intrinsic::ppc_qpx_qvstfda:
9255 case Intrinsic::ppc_qpx_qvstfs:
9256 case Intrinsic::ppc_qpx_qvstfsa:
9259 case Intrinsic::ppc_qpx_qvstfcd:
9260 case Intrinsic::ppc_qpx_qvstfcda:
9263 case Intrinsic::ppc_qpx_qvstfcs:
9264 case Intrinsic::ppc_qpx_qvstfcsa:
9267 case Intrinsic::ppc_qpx_qvstfiw:
9268 case Intrinsic::ppc_qpx_qvstfiwa:
9269 case Intrinsic::ppc_altivec_stvx:
9270 case Intrinsic::ppc_altivec_stvxl:
9271 case Intrinsic::ppc_vsx_stxvw4x:
9274 case Intrinsic::ppc_vsx_stxvd2x:
9277 case Intrinsic::ppc_altivec_stvebx:
9280 case Intrinsic::ppc_altivec_stvehx:
9283 case Intrinsic::ppc_altivec_stvewx:
9288 return isConsecutiveLSLoc(N->getOperand(3), VT, Base, Bytes, Dist, DAG);
9294 // Return true is there is a nearyby consecutive load to the one provided
9295 // (regardless of alignment). We search up and down the chain, looking though
9296 // token factors and other loads (but nothing else). As a result, a true result
9297 // indicates that it is safe to create a new consecutive load adjacent to the
9299 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
9300 SDValue Chain = LD->getChain();
9301 EVT VT = LD->getMemoryVT();
9303 SmallSet<SDNode *, 16> LoadRoots;
9304 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
9305 SmallSet<SDNode *, 16> Visited;
9307 // First, search up the chain, branching to follow all token-factor operands.
9308 // If we find a consecutive load, then we're done, otherwise, record all
9309 // nodes just above the top-level loads and token factors.
9310 while (!Queue.empty()) {
9311 SDNode *ChainNext = Queue.pop_back_val();
9312 if (!Visited.insert(ChainNext).second)
9315 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(ChainNext)) {
9316 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
9319 if (!Visited.count(ChainLD->getChain().getNode()))
9320 Queue.push_back(ChainLD->getChain().getNode());
9321 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
9322 for (const SDUse &O : ChainNext->ops())
9323 if (!Visited.count(O.getNode()))
9324 Queue.push_back(O.getNode());
9326 LoadRoots.insert(ChainNext);
9329 // Second, search down the chain, starting from the top-level nodes recorded
9330 // in the first phase. These top-level nodes are the nodes just above all
9331 // loads and token factors. Starting with their uses, recursively look though
9332 // all loads (just the chain uses) and token factors to find a consecutive
9337 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
9338 IE = LoadRoots.end(); I != IE; ++I) {
9339 Queue.push_back(*I);
9341 while (!Queue.empty()) {
9342 SDNode *LoadRoot = Queue.pop_back_val();
9343 if (!Visited.insert(LoadRoot).second)
9346 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(LoadRoot))
9347 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
9350 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
9351 UE = LoadRoot->use_end(); UI != UE; ++UI)
9352 if (((isa<MemSDNode>(*UI) &&
9353 cast<MemSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
9354 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
9355 Queue.push_back(*UI);
9362 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
9363 DAGCombinerInfo &DCI) const {
9364 SelectionDAG &DAG = DCI.DAG;
9367 assert(Subtarget.useCRBits() && "Expecting to be tracking CR bits");
9368 // If we're tracking CR bits, we need to be careful that we don't have:
9369 // trunc(binary-ops(zext(x), zext(y)))
9371 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
9372 // such that we're unnecessarily moving things into GPRs when it would be
9373 // better to keep them in CR bits.
9375 // Note that trunc here can be an actual i1 trunc, or can be the effective
9376 // truncation that comes from a setcc or select_cc.
9377 if (N->getOpcode() == ISD::TRUNCATE &&
9378 N->getValueType(0) != MVT::i1)
9381 if (N->getOperand(0).getValueType() != MVT::i32 &&
9382 N->getOperand(0).getValueType() != MVT::i64)
9385 if (N->getOpcode() == ISD::SETCC ||
9386 N->getOpcode() == ISD::SELECT_CC) {
9387 // If we're looking at a comparison, then we need to make sure that the
9388 // high bits (all except for the first) don't matter the result.
9390 cast<CondCodeSDNode>(N->getOperand(
9391 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
9392 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
9394 if (ISD::isSignedIntSetCC(CC)) {
9395 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
9396 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
9398 } else if (ISD::isUnsignedIntSetCC(CC)) {
9399 if (!DAG.MaskedValueIsZero(N->getOperand(0),
9400 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
9401 !DAG.MaskedValueIsZero(N->getOperand(1),
9402 APInt::getHighBitsSet(OpBits, OpBits-1)))
9405 // This is neither a signed nor an unsigned comparison, just make sure
9406 // that the high bits are equal.
9407 APInt Op1Zero, Op1One;
9408 APInt Op2Zero, Op2One;
9409 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
9410 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
9412 // We don't really care about what is known about the first bit (if
9413 // anything), so clear it in all masks prior to comparing them.
9414 Op1Zero.clearBit(0); Op1One.clearBit(0);
9415 Op2Zero.clearBit(0); Op2One.clearBit(0);
9417 if (Op1Zero != Op2Zero || Op1One != Op2One)
9422 // We now know that the higher-order bits are irrelevant, we just need to
9423 // make sure that all of the intermediate operations are bit operations, and
9424 // all inputs are extensions.
9425 if (N->getOperand(0).getOpcode() != ISD::AND &&
9426 N->getOperand(0).getOpcode() != ISD::OR &&
9427 N->getOperand(0).getOpcode() != ISD::XOR &&
9428 N->getOperand(0).getOpcode() != ISD::SELECT &&
9429 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
9430 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
9431 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
9432 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
9433 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
9436 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
9437 N->getOperand(1).getOpcode() != ISD::AND &&
9438 N->getOperand(1).getOpcode() != ISD::OR &&
9439 N->getOperand(1).getOpcode() != ISD::XOR &&
9440 N->getOperand(1).getOpcode() != ISD::SELECT &&
9441 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
9442 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
9443 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
9444 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
9445 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
9448 SmallVector<SDValue, 4> Inputs;
9449 SmallVector<SDValue, 8> BinOps, PromOps;
9450 SmallPtrSet<SDNode *, 16> Visited;
9452 for (unsigned i = 0; i < 2; ++i) {
9453 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
9454 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
9455 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
9456 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
9457 isa<ConstantSDNode>(N->getOperand(i)))
9458 Inputs.push_back(N->getOperand(i));
9460 BinOps.push_back(N->getOperand(i));
9462 if (N->getOpcode() == ISD::TRUNCATE)
9466 // Visit all inputs, collect all binary operations (and, or, xor and
9467 // select) that are all fed by extensions.
9468 while (!BinOps.empty()) {
9469 SDValue BinOp = BinOps.back();
9472 if (!Visited.insert(BinOp.getNode()).second)
9475 PromOps.push_back(BinOp);
9477 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
9478 // The condition of the select is not promoted.
9479 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
9481 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
9484 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
9485 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
9486 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
9487 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
9488 isa<ConstantSDNode>(BinOp.getOperand(i))) {
9489 Inputs.push_back(BinOp.getOperand(i));
9490 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
9491 BinOp.getOperand(i).getOpcode() == ISD::OR ||
9492 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
9493 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
9494 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
9495 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
9496 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
9497 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
9498 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
9499 BinOps.push_back(BinOp.getOperand(i));
9501 // We have an input that is not an extension or another binary
9502 // operation; we'll abort this transformation.
9508 // Make sure that this is a self-contained cluster of operations (which
9509 // is not quite the same thing as saying that everything has only one
9511 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9512 if (isa<ConstantSDNode>(Inputs[i]))
9515 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
9516 UE = Inputs[i].getNode()->use_end();
9519 if (User != N && !Visited.count(User))
9522 // Make sure that we're not going to promote the non-output-value
9523 // operand(s) or SELECT or SELECT_CC.
9524 // FIXME: Although we could sometimes handle this, and it does occur in
9525 // practice that one of the condition inputs to the select is also one of
9526 // the outputs, we currently can't deal with this.
9527 if (User->getOpcode() == ISD::SELECT) {
9528 if (User->getOperand(0) == Inputs[i])
9530 } else if (User->getOpcode() == ISD::SELECT_CC) {
9531 if (User->getOperand(0) == Inputs[i] ||
9532 User->getOperand(1) == Inputs[i])
9538 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
9539 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
9540 UE = PromOps[i].getNode()->use_end();
9543 if (User != N && !Visited.count(User))
9546 // Make sure that we're not going to promote the non-output-value
9547 // operand(s) or SELECT or SELECT_CC.
9548 // FIXME: Although we could sometimes handle this, and it does occur in
9549 // practice that one of the condition inputs to the select is also one of
9550 // the outputs, we currently can't deal with this.
9551 if (User->getOpcode() == ISD::SELECT) {
9552 if (User->getOperand(0) == PromOps[i])
9554 } else if (User->getOpcode() == ISD::SELECT_CC) {
9555 if (User->getOperand(0) == PromOps[i] ||
9556 User->getOperand(1) == PromOps[i])
9562 // Replace all inputs with the extension operand.
9563 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9564 // Constants may have users outside the cluster of to-be-promoted nodes,
9565 // and so we need to replace those as we do the promotions.
9566 if (isa<ConstantSDNode>(Inputs[i]))
9569 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
9572 // Replace all operations (these are all the same, but have a different
9573 // (i1) return type). DAG.getNode will validate that the types of
9574 // a binary operator match, so go through the list in reverse so that
9575 // we've likely promoted both operands first. Any intermediate truncations or
9576 // extensions disappear.
9577 while (!PromOps.empty()) {
9578 SDValue PromOp = PromOps.back();
9581 if (PromOp.getOpcode() == ISD::TRUNCATE ||
9582 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
9583 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
9584 PromOp.getOpcode() == ISD::ANY_EXTEND) {
9585 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
9586 PromOp.getOperand(0).getValueType() != MVT::i1) {
9587 // The operand is not yet ready (see comment below).
9588 PromOps.insert(PromOps.begin(), PromOp);
9592 SDValue RepValue = PromOp.getOperand(0);
9593 if (isa<ConstantSDNode>(RepValue))
9594 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
9596 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
9601 switch (PromOp.getOpcode()) {
9602 default: C = 0; break;
9603 case ISD::SELECT: C = 1; break;
9604 case ISD::SELECT_CC: C = 2; break;
9607 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
9608 PromOp.getOperand(C).getValueType() != MVT::i1) ||
9609 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
9610 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
9611 // The to-be-promoted operands of this node have not yet been
9612 // promoted (this should be rare because we're going through the
9613 // list backward, but if one of the operands has several users in
9614 // this cluster of to-be-promoted nodes, it is possible).
9615 PromOps.insert(PromOps.begin(), PromOp);
9619 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
9620 PromOp.getNode()->op_end());
9622 // If there are any constant inputs, make sure they're replaced now.
9623 for (unsigned i = 0; i < 2; ++i)
9624 if (isa<ConstantSDNode>(Ops[C+i]))
9625 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
9627 DAG.ReplaceAllUsesOfValueWith(PromOp,
9628 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
9631 // Now we're left with the initial truncation itself.
9632 if (N->getOpcode() == ISD::TRUNCATE)
9633 return N->getOperand(0);
9635 // Otherwise, this is a comparison. The operands to be compared have just
9636 // changed type (to i1), but everything else is the same.
9637 return SDValue(N, 0);
9640 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
9641 DAGCombinerInfo &DCI) const {
9642 SelectionDAG &DAG = DCI.DAG;
9645 // If we're tracking CR bits, we need to be careful that we don't have:
9646 // zext(binary-ops(trunc(x), trunc(y)))
9648 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
9649 // such that we're unnecessarily moving things into CR bits that can more
9650 // efficiently stay in GPRs. Note that if we're not certain that the high
9651 // bits are set as required by the final extension, we still may need to do
9652 // some masking to get the proper behavior.
9654 // This same functionality is important on PPC64 when dealing with
9655 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
9656 // the return values of functions. Because it is so similar, it is handled
9659 if (N->getValueType(0) != MVT::i32 &&
9660 N->getValueType(0) != MVT::i64)
9663 if (!((N->getOperand(0).getValueType() == MVT::i1 && Subtarget.useCRBits()) ||
9664 (N->getOperand(0).getValueType() == MVT::i32 && Subtarget.isPPC64())))
9667 if (N->getOperand(0).getOpcode() != ISD::AND &&
9668 N->getOperand(0).getOpcode() != ISD::OR &&
9669 N->getOperand(0).getOpcode() != ISD::XOR &&
9670 N->getOperand(0).getOpcode() != ISD::SELECT &&
9671 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
9674 SmallVector<SDValue, 4> Inputs;
9675 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
9676 SmallPtrSet<SDNode *, 16> Visited;
9678 // Visit all inputs, collect all binary operations (and, or, xor and
9679 // select) that are all fed by truncations.
9680 while (!BinOps.empty()) {
9681 SDValue BinOp = BinOps.back();
9684 if (!Visited.insert(BinOp.getNode()).second)
9687 PromOps.push_back(BinOp);
9689 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
9690 // The condition of the select is not promoted.
9691 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
9693 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
9696 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
9697 isa<ConstantSDNode>(BinOp.getOperand(i))) {
9698 Inputs.push_back(BinOp.getOperand(i));
9699 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
9700 BinOp.getOperand(i).getOpcode() == ISD::OR ||
9701 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
9702 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
9703 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
9704 BinOps.push_back(BinOp.getOperand(i));
9706 // We have an input that is not a truncation or another binary
9707 // operation; we'll abort this transformation.
9713 // The operands of a select that must be truncated when the select is
9714 // promoted because the operand is actually part of the to-be-promoted set.
9715 DenseMap<SDNode *, EVT> SelectTruncOp[2];
9717 // Make sure that this is a self-contained cluster of operations (which
9718 // is not quite the same thing as saying that everything has only one
9720 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9721 if (isa<ConstantSDNode>(Inputs[i]))
9724 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
9725 UE = Inputs[i].getNode()->use_end();
9728 if (User != N && !Visited.count(User))
9731 // If we're going to promote the non-output-value operand(s) or SELECT or
9732 // SELECT_CC, record them for truncation.
9733 if (User->getOpcode() == ISD::SELECT) {
9734 if (User->getOperand(0) == Inputs[i])
9735 SelectTruncOp[0].insert(std::make_pair(User,
9736 User->getOperand(0).getValueType()));
9737 } else if (User->getOpcode() == ISD::SELECT_CC) {
9738 if (User->getOperand(0) == Inputs[i])
9739 SelectTruncOp[0].insert(std::make_pair(User,
9740 User->getOperand(0).getValueType()));
9741 if (User->getOperand(1) == Inputs[i])
9742 SelectTruncOp[1].insert(std::make_pair(User,
9743 User->getOperand(1).getValueType()));
9748 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
9749 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
9750 UE = PromOps[i].getNode()->use_end();
9753 if (User != N && !Visited.count(User))
9756 // If we're going to promote the non-output-value operand(s) or SELECT or
9757 // SELECT_CC, record them for truncation.
9758 if (User->getOpcode() == ISD::SELECT) {
9759 if (User->getOperand(0) == PromOps[i])
9760 SelectTruncOp[0].insert(std::make_pair(User,
9761 User->getOperand(0).getValueType()));
9762 } else if (User->getOpcode() == ISD::SELECT_CC) {
9763 if (User->getOperand(0) == PromOps[i])
9764 SelectTruncOp[0].insert(std::make_pair(User,
9765 User->getOperand(0).getValueType()));
9766 if (User->getOperand(1) == PromOps[i])
9767 SelectTruncOp[1].insert(std::make_pair(User,
9768 User->getOperand(1).getValueType()));
9773 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
9774 bool ReallyNeedsExt = false;
9775 if (N->getOpcode() != ISD::ANY_EXTEND) {
9776 // If all of the inputs are not already sign/zero extended, then
9777 // we'll still need to do that at the end.
9778 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9779 if (isa<ConstantSDNode>(Inputs[i]))
9783 Inputs[i].getOperand(0).getValueSizeInBits();
9784 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
9786 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
9787 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
9788 APInt::getHighBitsSet(OpBits,
9789 OpBits-PromBits))) ||
9790 (N->getOpcode() == ISD::SIGN_EXTEND &&
9791 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
9792 (OpBits-(PromBits-1)))) {
9793 ReallyNeedsExt = true;
9799 // Replace all inputs, either with the truncation operand, or a
9800 // truncation or extension to the final output type.
9801 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9802 // Constant inputs need to be replaced with the to-be-promoted nodes that
9803 // use them because they might have users outside of the cluster of
9805 if (isa<ConstantSDNode>(Inputs[i]))
9808 SDValue InSrc = Inputs[i].getOperand(0);
9809 if (Inputs[i].getValueType() == N->getValueType(0))
9810 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
9811 else if (N->getOpcode() == ISD::SIGN_EXTEND)
9812 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
9813 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
9814 else if (N->getOpcode() == ISD::ZERO_EXTEND)
9815 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
9816 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
9818 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
9819 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
9822 // Replace all operations (these are all the same, but have a different
9823 // (promoted) return type). DAG.getNode will validate that the types of
9824 // a binary operator match, so go through the list in reverse so that
9825 // we've likely promoted both operands first.
9826 while (!PromOps.empty()) {
9827 SDValue PromOp = PromOps.back();
9831 switch (PromOp.getOpcode()) {
9832 default: C = 0; break;
9833 case ISD::SELECT: C = 1; break;
9834 case ISD::SELECT_CC: C = 2; break;
9837 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
9838 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
9839 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
9840 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
9841 // The to-be-promoted operands of this node have not yet been
9842 // promoted (this should be rare because we're going through the
9843 // list backward, but if one of the operands has several users in
9844 // this cluster of to-be-promoted nodes, it is possible).
9845 PromOps.insert(PromOps.begin(), PromOp);
9849 // For SELECT and SELECT_CC nodes, we do a similar check for any
9850 // to-be-promoted comparison inputs.
9851 if (PromOp.getOpcode() == ISD::SELECT ||
9852 PromOp.getOpcode() == ISD::SELECT_CC) {
9853 if ((SelectTruncOp[0].count(PromOp.getNode()) &&
9854 PromOp.getOperand(0).getValueType() != N->getValueType(0)) ||
9855 (SelectTruncOp[1].count(PromOp.getNode()) &&
9856 PromOp.getOperand(1).getValueType() != N->getValueType(0))) {
9857 PromOps.insert(PromOps.begin(), PromOp);
9862 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
9863 PromOp.getNode()->op_end());
9865 // If this node has constant inputs, then they'll need to be promoted here.
9866 for (unsigned i = 0; i < 2; ++i) {
9867 if (!isa<ConstantSDNode>(Ops[C+i]))
9869 if (Ops[C+i].getValueType() == N->getValueType(0))
9872 if (N->getOpcode() == ISD::SIGN_EXTEND)
9873 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
9874 else if (N->getOpcode() == ISD::ZERO_EXTEND)
9875 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
9877 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
9880 // If we've promoted the comparison inputs of a SELECT or SELECT_CC,
9881 // truncate them again to the original value type.
9882 if (PromOp.getOpcode() == ISD::SELECT ||
9883 PromOp.getOpcode() == ISD::SELECT_CC) {
9884 auto SI0 = SelectTruncOp[0].find(PromOp.getNode());
9885 if (SI0 != SelectTruncOp[0].end())
9886 Ops[0] = DAG.getNode(ISD::TRUNCATE, dl, SI0->second, Ops[0]);
9887 auto SI1 = SelectTruncOp[1].find(PromOp.getNode());
9888 if (SI1 != SelectTruncOp[1].end())
9889 Ops[1] = DAG.getNode(ISD::TRUNCATE, dl, SI1->second, Ops[1]);
9892 DAG.ReplaceAllUsesOfValueWith(PromOp,
9893 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
9896 // Now we're left with the initial extension itself.
9897 if (!ReallyNeedsExt)
9898 return N->getOperand(0);
9900 // To zero extend, just mask off everything except for the first bit (in the
9902 if (N->getOpcode() == ISD::ZERO_EXTEND)
9903 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
9904 DAG.getConstant(APInt::getLowBitsSet(
9905 N->getValueSizeInBits(0), PromBits),
9906 dl, N->getValueType(0)));
9908 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
9909 "Invalid extension type");
9910 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0), DAG.getDataLayout());
9912 DAG.getConstant(N->getValueSizeInBits(0) - PromBits, dl, ShiftAmountTy);
9913 return DAG.getNode(ISD::SRA, dl, N->getValueType(0),
9914 DAG.getNode(ISD::SHL, dl, N->getValueType(0),
9915 N->getOperand(0), ShiftCst), ShiftCst);
9918 SDValue PPCTargetLowering::combineFPToIntToFP(SDNode *N,
9919 DAGCombinerInfo &DCI) const {
9920 assert((N->getOpcode() == ISD::SINT_TO_FP ||
9921 N->getOpcode() == ISD::UINT_TO_FP) &&
9922 "Need an int -> FP conversion node here");
9924 if (!Subtarget.has64BitSupport())
9927 SelectionDAG &DAG = DCI.DAG;
9931 // Don't handle ppc_fp128 here or i1 conversions.
9932 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
9934 if (Op.getOperand(0).getValueType() == MVT::i1)
9937 // For i32 intermediate values, unfortunately, the conversion functions
9938 // leave the upper 32 bits of the value are undefined. Within the set of
9939 // scalar instructions, we have no method for zero- or sign-extending the
9940 // value. Thus, we cannot handle i32 intermediate values here.
9941 if (Op.getOperand(0).getValueType() == MVT::i32)
9944 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
9945 "UINT_TO_FP is supported only with FPCVT");
9947 // If we have FCFIDS, then use it when converting to single-precision.
9948 // Otherwise, convert to double-precision and then round.
9949 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
9950 ? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
9952 : (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
9954 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
9958 // If we're converting from a float, to an int, and back to a float again,
9959 // then we don't need the store/load pair at all.
9960 if ((Op.getOperand(0).getOpcode() == ISD::FP_TO_UINT &&
9961 Subtarget.hasFPCVT()) ||
9962 (Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT)) {
9963 SDValue Src = Op.getOperand(0).getOperand(0);
9964 if (Src.getValueType() == MVT::f32) {
9965 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
9966 DCI.AddToWorklist(Src.getNode());
9970 Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
9973 SDValue Tmp = DAG.getNode(FCTOp, dl, MVT::f64, Src);
9974 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Tmp);
9976 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) {
9977 FP = DAG.getNode(ISD::FP_ROUND, dl,
9978 MVT::f32, FP, DAG.getIntPtrConstant(0, dl));
9979 DCI.AddToWorklist(FP.getNode());
9988 // expandVSXLoadForLE - Convert VSX loads (which may be intrinsics for
9989 // builtins) into loads with swaps.
9990 SDValue PPCTargetLowering::expandVSXLoadForLE(SDNode *N,
9991 DAGCombinerInfo &DCI) const {
9992 SelectionDAG &DAG = DCI.DAG;
9996 MachineMemOperand *MMO;
9998 switch (N->getOpcode()) {
10000 llvm_unreachable("Unexpected opcode for little endian VSX load");
10002 LoadSDNode *LD = cast<LoadSDNode>(N);
10003 Chain = LD->getChain();
10004 Base = LD->getBasePtr();
10005 MMO = LD->getMemOperand();
10006 // If the MMO suggests this isn't a load of a full vector, leave
10007 // things alone. For a built-in, we have to make the change for
10008 // correctness, so if there is a size problem that will be a bug.
10009 if (MMO->getSize() < 16)
10013 case ISD::INTRINSIC_W_CHAIN: {
10014 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
10015 Chain = Intrin->getChain();
10016 // Similarly to the store case below, Intrin->getBasePtr() doesn't get
10017 // us what we want. Get operand 2 instead.
10018 Base = Intrin->getOperand(2);
10019 MMO = Intrin->getMemOperand();
10024 MVT VecTy = N->getValueType(0).getSimpleVT();
10025 SDValue LoadOps[] = { Chain, Base };
10026 SDValue Load = DAG.getMemIntrinsicNode(PPCISD::LXVD2X, dl,
10027 DAG.getVTList(VecTy, MVT::Other),
10028 LoadOps, VecTy, MMO);
10029 DCI.AddToWorklist(Load.getNode());
10030 Chain = Load.getValue(1);
10031 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
10032 DAG.getVTList(VecTy, MVT::Other), Chain, Load);
10033 DCI.AddToWorklist(Swap.getNode());
10037 // expandVSXStoreForLE - Convert VSX stores (which may be intrinsics for
10038 // builtins) into stores with swaps.
10039 SDValue PPCTargetLowering::expandVSXStoreForLE(SDNode *N,
10040 DAGCombinerInfo &DCI) const {
10041 SelectionDAG &DAG = DCI.DAG;
10046 MachineMemOperand *MMO;
10048 switch (N->getOpcode()) {
10050 llvm_unreachable("Unexpected opcode for little endian VSX store");
10052 StoreSDNode *ST = cast<StoreSDNode>(N);
10053 Chain = ST->getChain();
10054 Base = ST->getBasePtr();
10055 MMO = ST->getMemOperand();
10057 // If the MMO suggests this isn't a store of a full vector, leave
10058 // things alone. For a built-in, we have to make the change for
10059 // correctness, so if there is a size problem that will be a bug.
10060 if (MMO->getSize() < 16)
10064 case ISD::INTRINSIC_VOID: {
10065 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
10066 Chain = Intrin->getChain();
10067 // Intrin->getBasePtr() oddly does not get what we want.
10068 Base = Intrin->getOperand(3);
10069 MMO = Intrin->getMemOperand();
10075 SDValue Src = N->getOperand(SrcOpnd);
10076 MVT VecTy = Src.getValueType().getSimpleVT();
10077 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
10078 DAG.getVTList(VecTy, MVT::Other), Chain, Src);
10079 DCI.AddToWorklist(Swap.getNode());
10080 Chain = Swap.getValue(1);
10081 SDValue StoreOps[] = { Chain, Swap, Base };
10082 SDValue Store = DAG.getMemIntrinsicNode(PPCISD::STXVD2X, dl,
10083 DAG.getVTList(MVT::Other),
10084 StoreOps, VecTy, MMO);
10085 DCI.AddToWorklist(Store.getNode());
10089 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
10090 DAGCombinerInfo &DCI) const {
10091 SelectionDAG &DAG = DCI.DAG;
10093 switch (N->getOpcode()) {
10096 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
10097 if (C->isNullValue()) // 0 << V -> 0.
10098 return N->getOperand(0);
10102 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
10103 if (C->isNullValue()) // 0 >>u V -> 0.
10104 return N->getOperand(0);
10108 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
10109 if (C->isNullValue() || // 0 >>s V -> 0.
10110 C->isAllOnesValue()) // -1 >>s V -> -1.
10111 return N->getOperand(0);
10114 case ISD::SIGN_EXTEND:
10115 case ISD::ZERO_EXTEND:
10116 case ISD::ANY_EXTEND:
10117 return DAGCombineExtBoolTrunc(N, DCI);
10118 case ISD::TRUNCATE:
10120 case ISD::SELECT_CC:
10121 return DAGCombineTruncBoolExt(N, DCI);
10122 case ISD::SINT_TO_FP:
10123 case ISD::UINT_TO_FP:
10124 return combineFPToIntToFP(N, DCI);
10126 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
10127 if (Subtarget.hasSTFIWX() && !cast<StoreSDNode>(N)->isTruncatingStore() &&
10128 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
10129 N->getOperand(1).getValueType() == MVT::i32 &&
10130 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
10131 SDValue Val = N->getOperand(1).getOperand(0);
10132 if (Val.getValueType() == MVT::f32) {
10133 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
10134 DCI.AddToWorklist(Val.getNode());
10136 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
10137 DCI.AddToWorklist(Val.getNode());
10140 N->getOperand(0), Val, N->getOperand(2),
10141 DAG.getValueType(N->getOperand(1).getValueType())
10144 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
10145 DAG.getVTList(MVT::Other), Ops,
10146 cast<StoreSDNode>(N)->getMemoryVT(),
10147 cast<StoreSDNode>(N)->getMemOperand());
10148 DCI.AddToWorklist(Val.getNode());
10152 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
10153 if (cast<StoreSDNode>(N)->isUnindexed() &&
10154 N->getOperand(1).getOpcode() == ISD::BSWAP &&
10155 N->getOperand(1).getNode()->hasOneUse() &&
10156 (N->getOperand(1).getValueType() == MVT::i32 ||
10157 N->getOperand(1).getValueType() == MVT::i16 ||
10158 (Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
10159 N->getOperand(1).getValueType() == MVT::i64))) {
10160 SDValue BSwapOp = N->getOperand(1).getOperand(0);
10161 // Do an any-extend to 32-bits if this is a half-word input.
10162 if (BSwapOp.getValueType() == MVT::i16)
10163 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
10166 N->getOperand(0), BSwapOp, N->getOperand(2),
10167 DAG.getValueType(N->getOperand(1).getValueType())
10170 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
10171 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
10172 cast<StoreSDNode>(N)->getMemOperand());
10175 // For little endian, VSX stores require generating xxswapd/lxvd2x.
10176 EVT VT = N->getOperand(1).getValueType();
10177 if (VT.isSimple()) {
10178 MVT StoreVT = VT.getSimpleVT();
10179 if (Subtarget.hasVSX() && Subtarget.isLittleEndian() &&
10180 (StoreVT == MVT::v2f64 || StoreVT == MVT::v2i64 ||
10181 StoreVT == MVT::v4f32 || StoreVT == MVT::v4i32))
10182 return expandVSXStoreForLE(N, DCI);
10187 LoadSDNode *LD = cast<LoadSDNode>(N);
10188 EVT VT = LD->getValueType(0);
10190 // For little endian, VSX loads require generating lxvd2x/xxswapd.
10191 if (VT.isSimple()) {
10192 MVT LoadVT = VT.getSimpleVT();
10193 if (Subtarget.hasVSX() && Subtarget.isLittleEndian() &&
10194 (LoadVT == MVT::v2f64 || LoadVT == MVT::v2i64 ||
10195 LoadVT == MVT::v4f32 || LoadVT == MVT::v4i32))
10196 return expandVSXLoadForLE(N, DCI);
10199 EVT MemVT = LD->getMemoryVT();
10200 Type *Ty = MemVT.getTypeForEVT(*DAG.getContext());
10201 unsigned ABIAlignment = DAG.getDataLayout().getABITypeAlignment(Ty);
10202 Type *STy = MemVT.getScalarType().getTypeForEVT(*DAG.getContext());
10203 unsigned ScalarABIAlignment = DAG.getDataLayout().getABITypeAlignment(STy);
10204 if (LD->isUnindexed() && VT.isVector() &&
10205 ((Subtarget.hasAltivec() && ISD::isNON_EXTLoad(N) &&
10206 // P8 and later hardware should just use LOAD.
10207 !Subtarget.hasP8Vector() && (VT == MVT::v16i8 || VT == MVT::v8i16 ||
10208 VT == MVT::v4i32 || VT == MVT::v4f32)) ||
10209 (Subtarget.hasQPX() && (VT == MVT::v4f64 || VT == MVT::v4f32) &&
10210 LD->getAlignment() >= ScalarABIAlignment)) &&
10211 LD->getAlignment() < ABIAlignment) {
10212 // This is a type-legal unaligned Altivec or QPX load.
10213 SDValue Chain = LD->getChain();
10214 SDValue Ptr = LD->getBasePtr();
10215 bool isLittleEndian = Subtarget.isLittleEndian();
10217 // This implements the loading of unaligned vectors as described in
10218 // the venerable Apple Velocity Engine overview. Specifically:
10219 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
10220 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
10222 // The general idea is to expand a sequence of one or more unaligned
10223 // loads into an alignment-based permutation-control instruction (lvsl
10224 // or lvsr), a series of regular vector loads (which always truncate
10225 // their input address to an aligned address), and a series of
10226 // permutations. The results of these permutations are the requested
10227 // loaded values. The trick is that the last "extra" load is not taken
10228 // from the address you might suspect (sizeof(vector) bytes after the
10229 // last requested load), but rather sizeof(vector) - 1 bytes after the
10230 // last requested vector. The point of this is to avoid a page fault if
10231 // the base address happened to be aligned. This works because if the
10232 // base address is aligned, then adding less than a full vector length
10233 // will cause the last vector in the sequence to be (re)loaded.
10234 // Otherwise, the next vector will be fetched as you might suspect was
10237 // We might be able to reuse the permutation generation from
10238 // a different base address offset from this one by an aligned amount.
10239 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
10240 // optimization later.
10241 Intrinsic::ID Intr, IntrLD, IntrPerm;
10242 MVT PermCntlTy, PermTy, LDTy;
10243 if (Subtarget.hasAltivec()) {
10244 Intr = isLittleEndian ? Intrinsic::ppc_altivec_lvsr :
10245 Intrinsic::ppc_altivec_lvsl;
10246 IntrLD = Intrinsic::ppc_altivec_lvx;
10247 IntrPerm = Intrinsic::ppc_altivec_vperm;
10248 PermCntlTy = MVT::v16i8;
10249 PermTy = MVT::v4i32;
10252 Intr = MemVT == MVT::v4f64 ? Intrinsic::ppc_qpx_qvlpcld :
10253 Intrinsic::ppc_qpx_qvlpcls;
10254 IntrLD = MemVT == MVT::v4f64 ? Intrinsic::ppc_qpx_qvlfd :
10255 Intrinsic::ppc_qpx_qvlfs;
10256 IntrPerm = Intrinsic::ppc_qpx_qvfperm;
10257 PermCntlTy = MVT::v4f64;
10258 PermTy = MVT::v4f64;
10259 LDTy = MemVT.getSimpleVT();
10262 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, PermCntlTy);
10264 // Create the new MMO for the new base load. It is like the original MMO,
10265 // but represents an area in memory almost twice the vector size centered
10266 // on the original address. If the address is unaligned, we might start
10267 // reading up to (sizeof(vector)-1) bytes below the address of the
10268 // original unaligned load.
10269 MachineFunction &MF = DAG.getMachineFunction();
10270 MachineMemOperand *BaseMMO =
10271 MF.getMachineMemOperand(LD->getMemOperand(), -MemVT.getStoreSize()+1,
10272 2*MemVT.getStoreSize()-1);
10274 // Create the new base load.
10276 DAG.getTargetConstant(IntrLD, dl, getPointerTy(MF.getDataLayout()));
10277 SDValue BaseLoadOps[] = { Chain, LDXIntID, Ptr };
10279 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
10280 DAG.getVTList(PermTy, MVT::Other),
10281 BaseLoadOps, LDTy, BaseMMO);
10283 // Note that the value of IncOffset (which is provided to the next
10284 // load's pointer info offset value, and thus used to calculate the
10285 // alignment), and the value of IncValue (which is actually used to
10286 // increment the pointer value) are different! This is because we
10287 // require the next load to appear to be aligned, even though it
10288 // is actually offset from the base pointer by a lesser amount.
10289 int IncOffset = VT.getSizeInBits() / 8;
10290 int IncValue = IncOffset;
10292 // Walk (both up and down) the chain looking for another load at the real
10293 // (aligned) offset (the alignment of the other load does not matter in
10294 // this case). If found, then do not use the offset reduction trick, as
10295 // that will prevent the loads from being later combined (as they would
10296 // otherwise be duplicates).
10297 if (!findConsecutiveLoad(LD, DAG))
10300 SDValue Increment =
10301 DAG.getConstant(IncValue, dl, getPointerTy(MF.getDataLayout()));
10302 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
10304 MachineMemOperand *ExtraMMO =
10305 MF.getMachineMemOperand(LD->getMemOperand(),
10306 1, 2*MemVT.getStoreSize()-1);
10307 SDValue ExtraLoadOps[] = { Chain, LDXIntID, Ptr };
10308 SDValue ExtraLoad =
10309 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
10310 DAG.getVTList(PermTy, MVT::Other),
10311 ExtraLoadOps, LDTy, ExtraMMO);
10313 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
10314 BaseLoad.getValue(1), ExtraLoad.getValue(1));
10316 // Because vperm has a big-endian bias, we must reverse the order
10317 // of the input vectors and complement the permute control vector
10318 // when generating little endian code. We have already handled the
10319 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
10320 // and ExtraLoad here.
10322 if (isLittleEndian)
10323 Perm = BuildIntrinsicOp(IntrPerm,
10324 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
10326 Perm = BuildIntrinsicOp(IntrPerm,
10327 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
10330 Perm = Subtarget.hasAltivec() ?
10331 DAG.getNode(ISD::BITCAST, dl, VT, Perm) :
10332 DAG.getNode(ISD::FP_ROUND, dl, VT, Perm, // QPX
10333 DAG.getTargetConstant(1, dl, MVT::i64));
10334 // second argument is 1 because this rounding
10335 // is always exact.
10337 // The output of the permutation is our loaded result, the TokenFactor is
10339 DCI.CombineTo(N, Perm, TF);
10340 return SDValue(N, 0);
10344 case ISD::INTRINSIC_WO_CHAIN: {
10345 bool isLittleEndian = Subtarget.isLittleEndian();
10346 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
10347 Intrinsic::ID Intr = (isLittleEndian ? Intrinsic::ppc_altivec_lvsr
10348 : Intrinsic::ppc_altivec_lvsl);
10349 if ((IID == Intr ||
10350 IID == Intrinsic::ppc_qpx_qvlpcld ||
10351 IID == Intrinsic::ppc_qpx_qvlpcls) &&
10352 N->getOperand(1)->getOpcode() == ISD::ADD) {
10353 SDValue Add = N->getOperand(1);
10355 int Bits = IID == Intrinsic::ppc_qpx_qvlpcld ?
10356 5 /* 32 byte alignment */ : 4 /* 16 byte alignment */;
10358 if (DAG.MaskedValueIsZero(
10359 Add->getOperand(1),
10360 APInt::getAllOnesValue(Bits /* alignment */)
10362 Add.getValueType().getScalarType().getSizeInBits()))) {
10363 SDNode *BasePtr = Add->getOperand(0).getNode();
10364 for (SDNode::use_iterator UI = BasePtr->use_begin(),
10365 UE = BasePtr->use_end();
10367 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
10368 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() == IID) {
10369 // We've found another LVSL/LVSR, and this address is an aligned
10370 // multiple of that one. The results will be the same, so use the
10371 // one we've just found instead.
10373 return SDValue(*UI, 0);
10378 if (isa<ConstantSDNode>(Add->getOperand(1))) {
10379 SDNode *BasePtr = Add->getOperand(0).getNode();
10380 for (SDNode::use_iterator UI = BasePtr->use_begin(),
10381 UE = BasePtr->use_end(); UI != UE; ++UI) {
10382 if (UI->getOpcode() == ISD::ADD &&
10383 isa<ConstantSDNode>(UI->getOperand(1)) &&
10384 (cast<ConstantSDNode>(Add->getOperand(1))->getZExtValue() -
10385 cast<ConstantSDNode>(UI->getOperand(1))->getZExtValue()) %
10386 (1ULL << Bits) == 0) {
10387 SDNode *OtherAdd = *UI;
10388 for (SDNode::use_iterator VI = OtherAdd->use_begin(),
10389 VE = OtherAdd->use_end(); VI != VE; ++VI) {
10390 if (VI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
10391 cast<ConstantSDNode>(VI->getOperand(0))->getZExtValue() == IID) {
10392 return SDValue(*VI, 0);
10402 case ISD::INTRINSIC_W_CHAIN: {
10403 // For little endian, VSX loads require generating lxvd2x/xxswapd.
10404 if (Subtarget.hasVSX() && Subtarget.isLittleEndian()) {
10405 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
10408 case Intrinsic::ppc_vsx_lxvw4x:
10409 case Intrinsic::ppc_vsx_lxvd2x:
10410 return expandVSXLoadForLE(N, DCI);
10415 case ISD::INTRINSIC_VOID: {
10416 // For little endian, VSX stores require generating xxswapd/stxvd2x.
10417 if (Subtarget.hasVSX() && Subtarget.isLittleEndian()) {
10418 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
10421 case Intrinsic::ppc_vsx_stxvw4x:
10422 case Intrinsic::ppc_vsx_stxvd2x:
10423 return expandVSXStoreForLE(N, DCI);
10429 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
10430 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
10431 N->getOperand(0).hasOneUse() &&
10432 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
10433 (Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
10434 N->getValueType(0) == MVT::i64))) {
10435 SDValue Load = N->getOperand(0);
10436 LoadSDNode *LD = cast<LoadSDNode>(Load);
10437 // Create the byte-swapping load.
10439 LD->getChain(), // Chain
10440 LD->getBasePtr(), // Ptr
10441 DAG.getValueType(N->getValueType(0)) // VT
10444 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
10445 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
10446 MVT::i64 : MVT::i32, MVT::Other),
10447 Ops, LD->getMemoryVT(), LD->getMemOperand());
10449 // If this is an i16 load, insert the truncate.
10450 SDValue ResVal = BSLoad;
10451 if (N->getValueType(0) == MVT::i16)
10452 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
10454 // First, combine the bswap away. This makes the value produced by the
10456 DCI.CombineTo(N, ResVal);
10458 // Next, combine the load away, we give it a bogus result value but a real
10459 // chain result. The result value is dead because the bswap is dead.
10460 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
10462 // Return N so it doesn't get rechecked!
10463 return SDValue(N, 0);
10467 case PPCISD::VCMP: {
10468 // If a VCMPo node already exists with exactly the same operands as this
10469 // node, use its result instead of this node (VCMPo computes both a CR6 and
10470 // a normal output).
10472 if (!N->getOperand(0).hasOneUse() &&
10473 !N->getOperand(1).hasOneUse() &&
10474 !N->getOperand(2).hasOneUse()) {
10476 // Scan all of the users of the LHS, looking for VCMPo's that match.
10477 SDNode *VCMPoNode = nullptr;
10479 SDNode *LHSN = N->getOperand(0).getNode();
10480 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
10482 if (UI->getOpcode() == PPCISD::VCMPo &&
10483 UI->getOperand(1) == N->getOperand(1) &&
10484 UI->getOperand(2) == N->getOperand(2) &&
10485 UI->getOperand(0) == N->getOperand(0)) {
10490 // If there is no VCMPo node, or if the flag value has a single use, don't
10492 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
10495 // Look at the (necessarily single) use of the flag value. If it has a
10496 // chain, this transformation is more complex. Note that multiple things
10497 // could use the value result, which we should ignore.
10498 SDNode *FlagUser = nullptr;
10499 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
10500 FlagUser == nullptr; ++UI) {
10501 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
10502 SDNode *User = *UI;
10503 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
10504 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
10511 // If the user is a MFOCRF instruction, we know this is safe.
10512 // Otherwise we give up for right now.
10513 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
10514 return SDValue(VCMPoNode, 0);
10518 case ISD::BRCOND: {
10519 SDValue Cond = N->getOperand(1);
10520 SDValue Target = N->getOperand(2);
10522 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
10523 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
10524 Intrinsic::ppc_is_decremented_ctr_nonzero) {
10526 // We now need to make the intrinsic dead (it cannot be instruction
10528 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
10529 assert(Cond.getNode()->hasOneUse() &&
10530 "Counter decrement has more than one use");
10532 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
10533 N->getOperand(0), Target);
10538 // If this is a branch on an altivec predicate comparison, lower this so
10539 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
10540 // lowering is done pre-legalize, because the legalizer lowers the predicate
10541 // compare down to code that is difficult to reassemble.
10542 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
10543 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
10545 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
10546 // value. If so, pass-through the AND to get to the intrinsic.
10547 if (LHS.getOpcode() == ISD::AND &&
10548 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
10549 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
10550 Intrinsic::ppc_is_decremented_ctr_nonzero &&
10551 isa<ConstantSDNode>(LHS.getOperand(1)) &&
10552 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
10554 LHS = LHS.getOperand(0);
10556 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
10557 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
10558 Intrinsic::ppc_is_decremented_ctr_nonzero &&
10559 isa<ConstantSDNode>(RHS)) {
10560 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
10561 "Counter decrement comparison is not EQ or NE");
10563 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
10564 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
10565 (CC == ISD::SETNE && !Val);
10567 // We now need to make the intrinsic dead (it cannot be instruction
10569 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
10570 assert(LHS.getNode()->hasOneUse() &&
10571 "Counter decrement has more than one use");
10573 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
10574 N->getOperand(0), N->getOperand(4));
10580 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
10581 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
10582 getAltivecCompareInfo(LHS, CompareOpc, isDot, Subtarget)) {
10583 assert(isDot && "Can't compare against a vector result!");
10585 // If this is a comparison against something other than 0/1, then we know
10586 // that the condition is never/always true.
10587 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
10588 if (Val != 0 && Val != 1) {
10589 if (CC == ISD::SETEQ) // Cond never true, remove branch.
10590 return N->getOperand(0);
10591 // Always !=, turn it into an unconditional branch.
10592 return DAG.getNode(ISD::BR, dl, MVT::Other,
10593 N->getOperand(0), N->getOperand(4));
10596 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
10598 // Create the PPCISD altivec 'dot' comparison node.
10600 LHS.getOperand(2), // LHS of compare
10601 LHS.getOperand(3), // RHS of compare
10602 DAG.getConstant(CompareOpc, dl, MVT::i32)
10604 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
10605 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
10607 // Unpack the result based on how the target uses it.
10608 PPC::Predicate CompOpc;
10609 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
10610 default: // Can't happen, don't crash on invalid number though.
10611 case 0: // Branch on the value of the EQ bit of CR6.
10612 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
10614 case 1: // Branch on the inverted value of the EQ bit of CR6.
10615 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
10617 case 2: // Branch on the value of the LT bit of CR6.
10618 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
10620 case 3: // Branch on the inverted value of the LT bit of CR6.
10621 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
10625 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
10626 DAG.getConstant(CompOpc, dl, MVT::i32),
10627 DAG.getRegister(PPC::CR6, MVT::i32),
10628 N->getOperand(4), CompNode.getValue(1));
10638 PPCTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
10640 std::vector<SDNode *> *Created) const {
10641 // fold (sdiv X, pow2)
10642 EVT VT = N->getValueType(0);
10643 if (VT == MVT::i64 && !Subtarget.isPPC64())
10645 if ((VT != MVT::i32 && VT != MVT::i64) ||
10646 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
10650 SDValue N0 = N->getOperand(0);
10652 bool IsNegPow2 = (-Divisor).isPowerOf2();
10653 unsigned Lg2 = (IsNegPow2 ? -Divisor : Divisor).countTrailingZeros();
10654 SDValue ShiftAmt = DAG.getConstant(Lg2, DL, VT);
10656 SDValue Op = DAG.getNode(PPCISD::SRA_ADDZE, DL, VT, N0, ShiftAmt);
10658 Created->push_back(Op.getNode());
10661 Op = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Op);
10663 Created->push_back(Op.getNode());
10669 //===----------------------------------------------------------------------===//
10670 // Inline Assembly Support
10671 //===----------------------------------------------------------------------===//
10673 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
10676 const SelectionDAG &DAG,
10677 unsigned Depth) const {
10678 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
10679 switch (Op.getOpcode()) {
10681 case PPCISD::LBRX: {
10682 // lhbrx is known to have the top bits cleared out.
10683 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
10684 KnownZero = 0xFFFF0000;
10687 case ISD::INTRINSIC_WO_CHAIN: {
10688 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
10690 case Intrinsic::ppc_altivec_vcmpbfp_p:
10691 case Intrinsic::ppc_altivec_vcmpeqfp_p:
10692 case Intrinsic::ppc_altivec_vcmpequb_p:
10693 case Intrinsic::ppc_altivec_vcmpequh_p:
10694 case Intrinsic::ppc_altivec_vcmpequw_p:
10695 case Intrinsic::ppc_altivec_vcmpequd_p:
10696 case Intrinsic::ppc_altivec_vcmpgefp_p:
10697 case Intrinsic::ppc_altivec_vcmpgtfp_p:
10698 case Intrinsic::ppc_altivec_vcmpgtsb_p:
10699 case Intrinsic::ppc_altivec_vcmpgtsh_p:
10700 case Intrinsic::ppc_altivec_vcmpgtsw_p:
10701 case Intrinsic::ppc_altivec_vcmpgtsd_p:
10702 case Intrinsic::ppc_altivec_vcmpgtub_p:
10703 case Intrinsic::ppc_altivec_vcmpgtuh_p:
10704 case Intrinsic::ppc_altivec_vcmpgtuw_p:
10705 case Intrinsic::ppc_altivec_vcmpgtud_p:
10706 KnownZero = ~1U; // All bits but the low one are known to be zero.
10713 unsigned PPCTargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
10714 switch (Subtarget.getDarwinDirective()) {
10717 case PPC::DIR_PWR4:
10718 case PPC::DIR_PWR5:
10719 case PPC::DIR_PWR5X:
10720 case PPC::DIR_PWR6:
10721 case PPC::DIR_PWR6X:
10722 case PPC::DIR_PWR7:
10723 case PPC::DIR_PWR8: {
10727 const PPCInstrInfo *TII = Subtarget.getInstrInfo();
10729 // For small loops (between 5 and 8 instructions), align to a 32-byte
10730 // boundary so that the entire loop fits in one instruction-cache line.
10731 uint64_t LoopSize = 0;
10732 for (auto I = ML->block_begin(), IE = ML->block_end(); I != IE; ++I)
10733 for (auto J = (*I)->begin(), JE = (*I)->end(); J != JE; ++J)
10734 LoopSize += TII->GetInstSizeInBytes(J);
10736 if (LoopSize > 16 && LoopSize <= 32)
10743 return TargetLowering::getPrefLoopAlignment(ML);
10746 /// getConstraintType - Given a constraint, return the type of
10747 /// constraint it is for this target.
10748 PPCTargetLowering::ConstraintType
10749 PPCTargetLowering::getConstraintType(StringRef Constraint) const {
10750 if (Constraint.size() == 1) {
10751 switch (Constraint[0]) {
10758 return C_RegisterClass;
10760 // FIXME: While Z does indicate a memory constraint, it specifically
10761 // indicates an r+r address (used in conjunction with the 'y' modifier
10762 // in the replacement string). Currently, we're forcing the base
10763 // register to be r0 in the asm printer (which is interpreted as zero)
10764 // and forming the complete address in the second register. This is
10768 } else if (Constraint == "wc") { // individual CR bits.
10769 return C_RegisterClass;
10770 } else if (Constraint == "wa" || Constraint == "wd" ||
10771 Constraint == "wf" || Constraint == "ws") {
10772 return C_RegisterClass; // VSX registers.
10774 return TargetLowering::getConstraintType(Constraint);
10777 /// Examine constraint type and operand type and determine a weight value.
10778 /// This object must already have been set up with the operand type
10779 /// and the current alternative constraint selected.
10780 TargetLowering::ConstraintWeight
10781 PPCTargetLowering::getSingleConstraintMatchWeight(
10782 AsmOperandInfo &info, const char *constraint) const {
10783 ConstraintWeight weight = CW_Invalid;
10784 Value *CallOperandVal = info.CallOperandVal;
10785 // If we don't have a value, we can't do a match,
10786 // but allow it at the lowest weight.
10787 if (!CallOperandVal)
10789 Type *type = CallOperandVal->getType();
10791 // Look at the constraint type.
10792 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
10793 return CW_Register; // an individual CR bit.
10794 else if ((StringRef(constraint) == "wa" ||
10795 StringRef(constraint) == "wd" ||
10796 StringRef(constraint) == "wf") &&
10797 type->isVectorTy())
10798 return CW_Register;
10799 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
10800 return CW_Register;
10802 switch (*constraint) {
10804 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
10807 if (type->isIntegerTy())
10808 weight = CW_Register;
10811 if (type->isFloatTy())
10812 weight = CW_Register;
10815 if (type->isDoubleTy())
10816 weight = CW_Register;
10819 if (type->isVectorTy())
10820 weight = CW_Register;
10823 weight = CW_Register;
10826 weight = CW_Memory;
10832 std::pair<unsigned, const TargetRegisterClass *>
10833 PPCTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
10834 StringRef Constraint,
10836 if (Constraint.size() == 1) {
10837 // GCC RS6000 Constraint Letters
10838 switch (Constraint[0]) {
10839 case 'b': // R1-R31
10840 if (VT == MVT::i64 && Subtarget.isPPC64())
10841 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
10842 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
10843 case 'r': // R0-R31
10844 if (VT == MVT::i64 && Subtarget.isPPC64())
10845 return std::make_pair(0U, &PPC::G8RCRegClass);
10846 return std::make_pair(0U, &PPC::GPRCRegClass);
10848 if (VT == MVT::f32 || VT == MVT::i32)
10849 return std::make_pair(0U, &PPC::F4RCRegClass);
10850 if (VT == MVT::f64 || VT == MVT::i64)
10851 return std::make_pair(0U, &PPC::F8RCRegClass);
10852 if (VT == MVT::v4f64 && Subtarget.hasQPX())
10853 return std::make_pair(0U, &PPC::QFRCRegClass);
10854 if (VT == MVT::v4f32 && Subtarget.hasQPX())
10855 return std::make_pair(0U, &PPC::QSRCRegClass);
10858 if (VT == MVT::v4f64 && Subtarget.hasQPX())
10859 return std::make_pair(0U, &PPC::QFRCRegClass);
10860 if (VT == MVT::v4f32 && Subtarget.hasQPX())
10861 return std::make_pair(0U, &PPC::QSRCRegClass);
10862 return std::make_pair(0U, &PPC::VRRCRegClass);
10864 return std::make_pair(0U, &PPC::CRRCRegClass);
10866 } else if (Constraint == "wc") { // an individual CR bit.
10867 return std::make_pair(0U, &PPC::CRBITRCRegClass);
10868 } else if (Constraint == "wa" || Constraint == "wd" ||
10869 Constraint == "wf") {
10870 return std::make_pair(0U, &PPC::VSRCRegClass);
10871 } else if (Constraint == "ws") {
10872 if (VT == MVT::f32)
10873 return std::make_pair(0U, &PPC::VSSRCRegClass);
10875 return std::make_pair(0U, &PPC::VSFRCRegClass);
10878 std::pair<unsigned, const TargetRegisterClass *> R =
10879 TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
10881 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
10882 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
10883 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
10885 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
10886 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
10887 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
10888 PPC::GPRCRegClass.contains(R.first))
10889 return std::make_pair(TRI->getMatchingSuperReg(R.first,
10890 PPC::sub_32, &PPC::G8RCRegClass),
10891 &PPC::G8RCRegClass);
10893 // GCC accepts 'cc' as an alias for 'cr0', and we need to do the same.
10894 if (!R.second && StringRef("{cc}").equals_lower(Constraint)) {
10895 R.first = PPC::CR0;
10896 R.second = &PPC::CRRCRegClass;
10903 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
10904 /// vector. If it is invalid, don't add anything to Ops.
10905 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
10906 std::string &Constraint,
10907 std::vector<SDValue>&Ops,
10908 SelectionDAG &DAG) const {
10911 // Only support length 1 constraints.
10912 if (Constraint.length() > 1) return;
10914 char Letter = Constraint[0];
10925 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
10926 if (!CST) return; // Must be an immediate to match.
10928 int64_t Value = CST->getSExtValue();
10929 EVT TCVT = MVT::i64; // All constants taken to be 64 bits so that negative
10930 // numbers are printed as such.
10932 default: llvm_unreachable("Unknown constraint letter!");
10933 case 'I': // "I" is a signed 16-bit constant.
10934 if (isInt<16>(Value))
10935 Result = DAG.getTargetConstant(Value, dl, TCVT);
10937 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
10938 if (isShiftedUInt<16, 16>(Value))
10939 Result = DAG.getTargetConstant(Value, dl, TCVT);
10941 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
10942 if (isShiftedInt<16, 16>(Value))
10943 Result = DAG.getTargetConstant(Value, dl, TCVT);
10945 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
10946 if (isUInt<16>(Value))
10947 Result = DAG.getTargetConstant(Value, dl, TCVT);
10949 case 'M': // "M" is a constant that is greater than 31.
10951 Result = DAG.getTargetConstant(Value, dl, TCVT);
10953 case 'N': // "N" is a positive constant that is an exact power of two.
10954 if (Value > 0 && isPowerOf2_64(Value))
10955 Result = DAG.getTargetConstant(Value, dl, TCVT);
10957 case 'O': // "O" is the constant zero.
10959 Result = DAG.getTargetConstant(Value, dl, TCVT);
10961 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
10962 if (isInt<16>(-Value))
10963 Result = DAG.getTargetConstant(Value, dl, TCVT);
10970 if (Result.getNode()) {
10971 Ops.push_back(Result);
10975 // Handle standard constraint letters.
10976 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
10979 // isLegalAddressingMode - Return true if the addressing mode represented
10980 // by AM is legal for this target, for a load/store of the specified type.
10981 bool PPCTargetLowering::isLegalAddressingMode(const DataLayout &DL,
10982 const AddrMode &AM, Type *Ty,
10983 unsigned AS) const {
10984 // PPC does not allow r+i addressing modes for vectors!
10985 if (Ty->isVectorTy() && AM.BaseOffs != 0)
10988 // PPC allows a sign-extended 16-bit immediate field.
10989 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
10992 // No global is ever allowed as a base.
10996 // PPC only support r+r,
10997 switch (AM.Scale) {
10998 case 0: // "r+i" or just "i", depending on HasBaseReg.
11001 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
11003 // Otherwise we have r+r or r+i.
11006 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
11008 // Allow 2*r as r+r.
11011 // No other scales are supported.
11018 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
11019 SelectionDAG &DAG) const {
11020 MachineFunction &MF = DAG.getMachineFunction();
11021 MachineFrameInfo *MFI = MF.getFrameInfo();
11022 MFI->setReturnAddressIsTaken(true);
11024 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
11028 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11030 // Make sure the function does not optimize away the store of the RA to
11032 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
11033 FuncInfo->setLRStoreRequired();
11034 bool isPPC64 = Subtarget.isPPC64();
11035 auto PtrVT = getPointerTy(MF.getDataLayout());
11038 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
11040 DAG.getConstant(Subtarget.getFrameLowering()->getReturnSaveOffset(), dl,
11041 isPPC64 ? MVT::i64 : MVT::i32);
11042 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
11043 DAG.getNode(ISD::ADD, dl, PtrVT, FrameAddr, Offset),
11044 MachinePointerInfo(), false, false, false, 0);
11047 // Just load the return address off the stack.
11048 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
11049 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), RetAddrFI,
11050 MachinePointerInfo(), false, false, false, 0);
11053 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
11054 SelectionDAG &DAG) const {
11056 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11058 MachineFunction &MF = DAG.getMachineFunction();
11059 MachineFrameInfo *MFI = MF.getFrameInfo();
11060 MFI->setFrameAddressIsTaken(true);
11062 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
11063 bool isPPC64 = PtrVT == MVT::i64;
11065 // Naked functions never have a frame pointer, and so we use r1. For all
11066 // other functions, this decision must be delayed until during PEI.
11068 if (MF.getFunction()->hasFnAttribute(Attribute::Naked))
11069 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
11071 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
11073 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
11076 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
11077 FrameAddr, MachinePointerInfo(), false, false,
11082 // FIXME? Maybe this could be a TableGen attribute on some registers and
11083 // this table could be generated automatically from RegInfo.
11084 unsigned PPCTargetLowering::getRegisterByName(const char* RegName, EVT VT,
11085 SelectionDAG &DAG) const {
11086 bool isPPC64 = Subtarget.isPPC64();
11087 bool isDarwinABI = Subtarget.isDarwinABI();
11089 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
11090 (!isPPC64 && VT != MVT::i32))
11091 report_fatal_error("Invalid register global variable type");
11093 bool is64Bit = isPPC64 && VT == MVT::i64;
11094 unsigned Reg = StringSwitch<unsigned>(RegName)
11095 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
11096 .Case("r2", (isDarwinABI || isPPC64) ? 0 : PPC::R2)
11097 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
11098 (is64Bit ? PPC::X13 : PPC::R13))
11103 report_fatal_error("Invalid register name global variable");
11107 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
11108 // The PowerPC target isn't yet aware of offsets.
11112 bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
11114 unsigned Intrinsic) const {
11116 switch (Intrinsic) {
11117 case Intrinsic::ppc_qpx_qvlfd:
11118 case Intrinsic::ppc_qpx_qvlfs:
11119 case Intrinsic::ppc_qpx_qvlfcd:
11120 case Intrinsic::ppc_qpx_qvlfcs:
11121 case Intrinsic::ppc_qpx_qvlfiwa:
11122 case Intrinsic::ppc_qpx_qvlfiwz:
11123 case Intrinsic::ppc_altivec_lvx:
11124 case Intrinsic::ppc_altivec_lvxl:
11125 case Intrinsic::ppc_altivec_lvebx:
11126 case Intrinsic::ppc_altivec_lvehx:
11127 case Intrinsic::ppc_altivec_lvewx:
11128 case Intrinsic::ppc_vsx_lxvd2x:
11129 case Intrinsic::ppc_vsx_lxvw4x: {
11131 switch (Intrinsic) {
11132 case Intrinsic::ppc_altivec_lvebx:
11135 case Intrinsic::ppc_altivec_lvehx:
11138 case Intrinsic::ppc_altivec_lvewx:
11141 case Intrinsic::ppc_vsx_lxvd2x:
11144 case Intrinsic::ppc_qpx_qvlfd:
11147 case Intrinsic::ppc_qpx_qvlfs:
11150 case Intrinsic::ppc_qpx_qvlfcd:
11153 case Intrinsic::ppc_qpx_qvlfcs:
11161 Info.opc = ISD::INTRINSIC_W_CHAIN;
11163 Info.ptrVal = I.getArgOperand(0);
11164 Info.offset = -VT.getStoreSize()+1;
11165 Info.size = 2*VT.getStoreSize()-1;
11168 Info.readMem = true;
11169 Info.writeMem = false;
11172 case Intrinsic::ppc_qpx_qvlfda:
11173 case Intrinsic::ppc_qpx_qvlfsa:
11174 case Intrinsic::ppc_qpx_qvlfcda:
11175 case Intrinsic::ppc_qpx_qvlfcsa:
11176 case Intrinsic::ppc_qpx_qvlfiwaa:
11177 case Intrinsic::ppc_qpx_qvlfiwza: {
11179 switch (Intrinsic) {
11180 case Intrinsic::ppc_qpx_qvlfda:
11183 case Intrinsic::ppc_qpx_qvlfsa:
11186 case Intrinsic::ppc_qpx_qvlfcda:
11189 case Intrinsic::ppc_qpx_qvlfcsa:
11197 Info.opc = ISD::INTRINSIC_W_CHAIN;
11199 Info.ptrVal = I.getArgOperand(0);
11201 Info.size = VT.getStoreSize();
11204 Info.readMem = true;
11205 Info.writeMem = false;
11208 case Intrinsic::ppc_qpx_qvstfd:
11209 case Intrinsic::ppc_qpx_qvstfs:
11210 case Intrinsic::ppc_qpx_qvstfcd:
11211 case Intrinsic::ppc_qpx_qvstfcs:
11212 case Intrinsic::ppc_qpx_qvstfiw:
11213 case Intrinsic::ppc_altivec_stvx:
11214 case Intrinsic::ppc_altivec_stvxl:
11215 case Intrinsic::ppc_altivec_stvebx:
11216 case Intrinsic::ppc_altivec_stvehx:
11217 case Intrinsic::ppc_altivec_stvewx:
11218 case Intrinsic::ppc_vsx_stxvd2x:
11219 case Intrinsic::ppc_vsx_stxvw4x: {
11221 switch (Intrinsic) {
11222 case Intrinsic::ppc_altivec_stvebx:
11225 case Intrinsic::ppc_altivec_stvehx:
11228 case Intrinsic::ppc_altivec_stvewx:
11231 case Intrinsic::ppc_vsx_stxvd2x:
11234 case Intrinsic::ppc_qpx_qvstfd:
11237 case Intrinsic::ppc_qpx_qvstfs:
11240 case Intrinsic::ppc_qpx_qvstfcd:
11243 case Intrinsic::ppc_qpx_qvstfcs:
11251 Info.opc = ISD::INTRINSIC_VOID;
11253 Info.ptrVal = I.getArgOperand(1);
11254 Info.offset = -VT.getStoreSize()+1;
11255 Info.size = 2*VT.getStoreSize()-1;
11258 Info.readMem = false;
11259 Info.writeMem = true;
11262 case Intrinsic::ppc_qpx_qvstfda:
11263 case Intrinsic::ppc_qpx_qvstfsa:
11264 case Intrinsic::ppc_qpx_qvstfcda:
11265 case Intrinsic::ppc_qpx_qvstfcsa:
11266 case Intrinsic::ppc_qpx_qvstfiwa: {
11268 switch (Intrinsic) {
11269 case Intrinsic::ppc_qpx_qvstfda:
11272 case Intrinsic::ppc_qpx_qvstfsa:
11275 case Intrinsic::ppc_qpx_qvstfcda:
11278 case Intrinsic::ppc_qpx_qvstfcsa:
11286 Info.opc = ISD::INTRINSIC_VOID;
11288 Info.ptrVal = I.getArgOperand(1);
11290 Info.size = VT.getStoreSize();
11293 Info.readMem = false;
11294 Info.writeMem = true;
11304 /// getOptimalMemOpType - Returns the target specific optimal type for load
11305 /// and store operations as a result of memset, memcpy, and memmove
11306 /// lowering. If DstAlign is zero that means it's safe to destination
11307 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
11308 /// means there isn't a need to check it against alignment requirement,
11309 /// probably because the source does not need to be loaded. If 'IsMemset' is
11310 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
11311 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
11312 /// source is constant so it does not need to be loaded.
11313 /// It returns EVT::Other if the type should be determined using generic
11314 /// target-independent logic.
11315 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
11316 unsigned DstAlign, unsigned SrcAlign,
11317 bool IsMemset, bool ZeroMemset,
11319 MachineFunction &MF) const {
11320 if (getTargetMachine().getOptLevel() != CodeGenOpt::None) {
11321 const Function *F = MF.getFunction();
11322 // When expanding a memset, require at least two QPX instructions to cover
11323 // the cost of loading the value to be stored from the constant pool.
11324 if (Subtarget.hasQPX() && Size >= 32 && (!IsMemset || Size >= 64) &&
11325 (!SrcAlign || SrcAlign >= 32) && (!DstAlign || DstAlign >= 32) &&
11326 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
11330 // We should use Altivec/VSX loads and stores when available. For unaligned
11331 // addresses, unaligned VSX loads are only fast starting with the P8.
11332 if (Subtarget.hasAltivec() && Size >= 16 &&
11333 (((!SrcAlign || SrcAlign >= 16) && (!DstAlign || DstAlign >= 16)) ||
11334 ((IsMemset && Subtarget.hasVSX()) || Subtarget.hasP8Vector())))
11338 if (Subtarget.isPPC64()) {
11345 /// \brief Returns true if it is beneficial to convert a load of a constant
11346 /// to just the constant itself.
11347 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
11349 assert(Ty->isIntegerTy());
11351 unsigned BitSize = Ty->getPrimitiveSizeInBits();
11352 if (BitSize == 0 || BitSize > 64)
11357 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11358 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11360 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11361 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11362 return NumBits1 == 64 && NumBits2 == 32;
11365 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11366 if (!VT1.isInteger() || !VT2.isInteger())
11368 unsigned NumBits1 = VT1.getSizeInBits();
11369 unsigned NumBits2 = VT2.getSizeInBits();
11370 return NumBits1 == 64 && NumBits2 == 32;
11373 bool PPCTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
11374 // Generally speaking, zexts are not free, but they are free when they can be
11375 // folded with other operations.
11376 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Val)) {
11377 EVT MemVT = LD->getMemoryVT();
11378 if ((MemVT == MVT::i1 || MemVT == MVT::i8 || MemVT == MVT::i16 ||
11379 (Subtarget.isPPC64() && MemVT == MVT::i32)) &&
11380 (LD->getExtensionType() == ISD::NON_EXTLOAD ||
11381 LD->getExtensionType() == ISD::ZEXTLOAD))
11385 // FIXME: Add other cases...
11386 // - 32-bit shifts with a zext to i64
11387 // - zext after ctlz, bswap, etc.
11388 // - zext after and by a constant mask
11390 return TargetLowering::isZExtFree(Val, VT2);
11393 bool PPCTargetLowering::isFPExtFree(EVT VT) const {
11394 assert(VT.isFloatingPoint());
11398 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
11399 return isInt<16>(Imm) || isUInt<16>(Imm);
11402 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
11403 return isInt<16>(Imm) || isUInt<16>(Imm);
11406 bool PPCTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
11409 bool *Fast) const {
11410 if (DisablePPCUnaligned)
11413 // PowerPC supports unaligned memory access for simple non-vector types.
11414 // Although accessing unaligned addresses is not as efficient as accessing
11415 // aligned addresses, it is generally more efficient than manual expansion,
11416 // and generally only traps for software emulation when crossing page
11419 if (!VT.isSimple())
11422 if (VT.getSimpleVT().isVector()) {
11423 if (Subtarget.hasVSX()) {
11424 if (VT != MVT::v2f64 && VT != MVT::v2i64 &&
11425 VT != MVT::v4f32 && VT != MVT::v4i32)
11432 if (VT == MVT::ppcf128)
11441 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
11442 VT = VT.getScalarType();
11444 if (!VT.isSimple())
11447 switch (VT.getSimpleVT().SimpleTy) {
11459 PPCTargetLowering::getScratchRegisters(CallingConv::ID) const {
11460 // LR is a callee-save register, but we must treat it as clobbered by any call
11461 // site. Hence we include LR in the scratch registers, which are in turn added
11462 // as implicit-defs for stackmaps and patchpoints. The same reasoning applies
11463 // to CTR, which is used by any indirect call.
11464 static const MCPhysReg ScratchRegs[] = {
11465 PPC::X12, PPC::LR8, PPC::CTR8, 0
11468 return ScratchRegs;
11472 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
11473 EVT VT , unsigned DefinedValues) const {
11474 if (VT == MVT::v2i64)
11477 if (Subtarget.hasQPX()) {
11478 if (VT == MVT::v4f32 || VT == MVT::v4f64 || VT == MVT::v4i1)
11482 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
11485 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
11486 if (DisableILPPref || Subtarget.enableMachineScheduler())
11487 return TargetLowering::getSchedulingPreference(N);
11492 // Create a fast isel object.
11494 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
11495 const TargetLibraryInfo *LibInfo) const {
11496 return PPC::createFastISel(FuncInfo, LibInfo);