1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPerfectShuffle.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCTargetObjectFile.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/StringSwitch.h"
22 #include "llvm/ADT/Triple.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
30 #include "llvm/IR/CallingConv.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/DerivedTypes.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/IR/Intrinsics.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/Target/TargetOptions.h"
42 // FIXME: Remove this once soft-float is supported.
43 static cl::opt<bool> DisablePPCFloatInVariadic("disable-ppc-float-in-variadic",
44 cl::desc("disable saving float registers for va_start on PPC"), cl::Hidden);
46 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
47 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
49 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
50 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
52 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
53 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
55 // FIXME: Remove this once the bug has been fixed!
56 extern cl::opt<bool> ANDIGlueBug;
58 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
59 // If it isn't a Mach-O file then it's going to be a linux ELF
62 return new TargetLoweringObjectFileMachO();
64 return new PPC64LinuxTargetObjectFile();
67 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
68 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))),
69 Subtarget(*TM.getSubtargetImpl()) {
72 // Use _setjmp/_longjmp instead of setjmp/longjmp.
73 setUseUnderscoreSetJmp(true);
74 setUseUnderscoreLongJmp(true);
76 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
77 // arguments are at least 4/8 bytes aligned.
78 bool isPPC64 = Subtarget.isPPC64();
79 setMinStackArgumentAlignment(isPPC64 ? 8:4);
81 // Set up the register classes.
82 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
83 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
84 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
86 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
87 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
88 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
90 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
92 // PowerPC has pre-inc load and store's.
93 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
94 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
95 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
96 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
97 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
99 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
100 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
101 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
102 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
104 if (Subtarget.useCRBits()) {
105 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
107 if (isPPC64 || Subtarget.hasFPCVT()) {
108 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
109 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
110 isPPC64 ? MVT::i64 : MVT::i32);
111 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
112 AddPromotedToType (ISD::UINT_TO_FP, MVT::i1,
113 isPPC64 ? MVT::i64 : MVT::i32);
115 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
116 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
119 // PowerPC does not support direct load / store of condition registers
120 setOperationAction(ISD::LOAD, MVT::i1, Custom);
121 setOperationAction(ISD::STORE, MVT::i1, Custom);
123 // FIXME: Remove this once the ANDI glue bug is fixed:
125 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
127 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
128 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
129 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
130 setTruncStoreAction(MVT::i32, MVT::i1, Expand);
131 setTruncStoreAction(MVT::i16, MVT::i1, Expand);
132 setTruncStoreAction(MVT::i8, MVT::i1, Expand);
134 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
137 // This is used in the ppcf128->int sequence. Note it has different semantics
138 // from FP_ROUND: that rounds to nearest, this rounds to zero.
139 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
141 // We do not currently implement these libm ops for PowerPC.
142 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
143 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
144 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
145 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
146 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
147 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
149 // PowerPC has no SREM/UREM instructions
150 setOperationAction(ISD::SREM, MVT::i32, Expand);
151 setOperationAction(ISD::UREM, MVT::i32, Expand);
152 setOperationAction(ISD::SREM, MVT::i64, Expand);
153 setOperationAction(ISD::UREM, MVT::i64, Expand);
155 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
156 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
157 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
158 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
159 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
160 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
161 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
162 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
163 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
165 // We don't support sin/cos/sqrt/fmod/pow
166 setOperationAction(ISD::FSIN , MVT::f64, Expand);
167 setOperationAction(ISD::FCOS , MVT::f64, Expand);
168 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
169 setOperationAction(ISD::FREM , MVT::f64, Expand);
170 setOperationAction(ISD::FPOW , MVT::f64, Expand);
171 setOperationAction(ISD::FMA , MVT::f64, Legal);
172 setOperationAction(ISD::FSIN , MVT::f32, Expand);
173 setOperationAction(ISD::FCOS , MVT::f32, Expand);
174 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
175 setOperationAction(ISD::FREM , MVT::f32, Expand);
176 setOperationAction(ISD::FPOW , MVT::f32, Expand);
177 setOperationAction(ISD::FMA , MVT::f32, Legal);
179 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
181 // If we're enabling GP optimizations, use hardware square root
182 if (!Subtarget.hasFSQRT() &&
183 !(TM.Options.UnsafeFPMath &&
184 Subtarget.hasFRSQRTE() && Subtarget.hasFRE()))
185 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
187 if (!Subtarget.hasFSQRT() &&
188 !(TM.Options.UnsafeFPMath &&
189 Subtarget.hasFRSQRTES() && Subtarget.hasFRES()))
190 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
192 if (Subtarget.hasFCPSGN()) {
193 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
194 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
196 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
197 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
200 if (Subtarget.hasFPRND()) {
201 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
202 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
203 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
204 setOperationAction(ISD::FROUND, MVT::f64, Legal);
206 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
207 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
208 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
209 setOperationAction(ISD::FROUND, MVT::f32, Legal);
212 // PowerPC does not have BSWAP, CTPOP or CTTZ
213 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
214 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
215 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
216 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
217 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
218 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
219 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
220 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
222 if (Subtarget.hasPOPCNTD()) {
223 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
224 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
226 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
227 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
230 // PowerPC does not have ROTR
231 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
232 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
234 if (!Subtarget.useCRBits()) {
235 // PowerPC does not have Select
236 setOperationAction(ISD::SELECT, MVT::i32, Expand);
237 setOperationAction(ISD::SELECT, MVT::i64, Expand);
238 setOperationAction(ISD::SELECT, MVT::f32, Expand);
239 setOperationAction(ISD::SELECT, MVT::f64, Expand);
242 // PowerPC wants to turn select_cc of FP into fsel when possible.
243 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
244 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
246 // PowerPC wants to optimize integer setcc a bit
247 if (!Subtarget.useCRBits())
248 setOperationAction(ISD::SETCC, MVT::i32, Custom);
250 // PowerPC does not have BRCOND which requires SetCC
251 if (!Subtarget.useCRBits())
252 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
254 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
256 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
257 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
259 // PowerPC does not have [U|S]INT_TO_FP
260 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
261 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
263 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
264 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
265 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
266 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
268 // We cannot sextinreg(i1). Expand to shifts.
269 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
271 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
272 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
273 // support continuation, user-level threading, and etc.. As a result, no
274 // other SjLj exception interfaces are implemented and please don't build
275 // your own exception handling based on them.
276 // LLVM/Clang supports zero-cost DWARF exception handling.
277 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
278 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
280 // We want to legalize GlobalAddress and ConstantPool nodes into the
281 // appropriate instructions to materialize the address.
282 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
283 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
284 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
285 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
286 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
287 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
288 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
289 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
290 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
291 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
294 setOperationAction(ISD::TRAP, MVT::Other, Legal);
296 // TRAMPOLINE is custom lowered.
297 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
298 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
300 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
301 setOperationAction(ISD::VASTART , MVT::Other, Custom);
303 if (Subtarget.isSVR4ABI()) {
305 // VAARG always uses double-word chunks, so promote anything smaller.
306 setOperationAction(ISD::VAARG, MVT::i1, Promote);
307 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
308 setOperationAction(ISD::VAARG, MVT::i8, Promote);
309 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
310 setOperationAction(ISD::VAARG, MVT::i16, Promote);
311 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
312 setOperationAction(ISD::VAARG, MVT::i32, Promote);
313 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
314 setOperationAction(ISD::VAARG, MVT::Other, Expand);
316 // VAARG is custom lowered with the 32-bit SVR4 ABI.
317 setOperationAction(ISD::VAARG, MVT::Other, Custom);
318 setOperationAction(ISD::VAARG, MVT::i64, Custom);
321 setOperationAction(ISD::VAARG, MVT::Other, Expand);
323 if (Subtarget.isSVR4ABI() && !isPPC64)
324 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
325 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
327 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
329 // Use the default implementation.
330 setOperationAction(ISD::VAEND , MVT::Other, Expand);
331 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
332 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
333 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
334 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
336 // We want to custom lower some of our intrinsics.
337 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
339 // To handle counter-based loop conditions.
340 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
342 // Comparisons that require checking two conditions.
343 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
344 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
345 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
346 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
347 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
348 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
349 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
350 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
351 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
352 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
353 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
354 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
356 if (Subtarget.has64BitSupport()) {
357 // They also have instructions for converting between i64 and fp.
358 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
359 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
360 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
361 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
362 // This is just the low 32 bits of a (signed) fp->i64 conversion.
363 // We cannot do this with Promote because i64 is not a legal type.
364 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
366 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
367 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
369 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
370 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
373 // With the instructions enabled under FPCVT, we can do everything.
374 if (Subtarget.hasFPCVT()) {
375 if (Subtarget.has64BitSupport()) {
376 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
377 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
378 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
379 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
382 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
383 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
384 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
385 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
388 if (Subtarget.use64BitRegs()) {
389 // 64-bit PowerPC implementations can support i64 types directly
390 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
391 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
392 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
393 // 64-bit PowerPC wants to expand i128 shifts itself.
394 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
395 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
396 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
398 // 32-bit PowerPC wants to expand i64 shifts itself.
399 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
400 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
401 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
404 if (Subtarget.hasAltivec()) {
405 // First set operation action for all vector types to expand. Then we
406 // will selectively turn on ones that can be effectively codegen'd.
407 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
408 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
409 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
411 // add/sub are legal for all supported vector VT's.
412 setOperationAction(ISD::ADD , VT, Legal);
413 setOperationAction(ISD::SUB , VT, Legal);
415 // We promote all shuffles to v16i8.
416 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
417 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
419 // We promote all non-typed operations to v4i32.
420 setOperationAction(ISD::AND , VT, Promote);
421 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
422 setOperationAction(ISD::OR , VT, Promote);
423 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
424 setOperationAction(ISD::XOR , VT, Promote);
425 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
426 setOperationAction(ISD::LOAD , VT, Promote);
427 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
428 setOperationAction(ISD::SELECT, VT, Promote);
429 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
430 setOperationAction(ISD::STORE, VT, Promote);
431 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
433 // No other operations are legal.
434 setOperationAction(ISD::MUL , VT, Expand);
435 setOperationAction(ISD::SDIV, VT, Expand);
436 setOperationAction(ISD::SREM, VT, Expand);
437 setOperationAction(ISD::UDIV, VT, Expand);
438 setOperationAction(ISD::UREM, VT, Expand);
439 setOperationAction(ISD::FDIV, VT, Expand);
440 setOperationAction(ISD::FREM, VT, Expand);
441 setOperationAction(ISD::FNEG, VT, Expand);
442 setOperationAction(ISD::FSQRT, VT, Expand);
443 setOperationAction(ISD::FLOG, VT, Expand);
444 setOperationAction(ISD::FLOG10, VT, Expand);
445 setOperationAction(ISD::FLOG2, VT, Expand);
446 setOperationAction(ISD::FEXP, VT, Expand);
447 setOperationAction(ISD::FEXP2, VT, Expand);
448 setOperationAction(ISD::FSIN, VT, Expand);
449 setOperationAction(ISD::FCOS, VT, Expand);
450 setOperationAction(ISD::FABS, VT, Expand);
451 setOperationAction(ISD::FPOWI, VT, Expand);
452 setOperationAction(ISD::FFLOOR, VT, Expand);
453 setOperationAction(ISD::FCEIL, VT, Expand);
454 setOperationAction(ISD::FTRUNC, VT, Expand);
455 setOperationAction(ISD::FRINT, VT, Expand);
456 setOperationAction(ISD::FNEARBYINT, VT, Expand);
457 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
458 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
459 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
460 setOperationAction(ISD::MULHU, VT, Expand);
461 setOperationAction(ISD::MULHS, VT, Expand);
462 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
463 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
464 setOperationAction(ISD::UDIVREM, VT, Expand);
465 setOperationAction(ISD::SDIVREM, VT, Expand);
466 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
467 setOperationAction(ISD::FPOW, VT, Expand);
468 setOperationAction(ISD::BSWAP, VT, Expand);
469 setOperationAction(ISD::CTPOP, VT, Expand);
470 setOperationAction(ISD::CTLZ, VT, Expand);
471 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
472 setOperationAction(ISD::CTTZ, VT, Expand);
473 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
474 setOperationAction(ISD::VSELECT, VT, Expand);
475 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
477 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
478 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
479 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
480 setTruncStoreAction(VT, InnerVT, Expand);
482 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
483 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
484 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
487 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
488 // with merges, splats, etc.
489 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
491 setOperationAction(ISD::AND , MVT::v4i32, Legal);
492 setOperationAction(ISD::OR , MVT::v4i32, Legal);
493 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
494 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
495 setOperationAction(ISD::SELECT, MVT::v4i32,
496 Subtarget.useCRBits() ? Legal : Expand);
497 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
498 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
499 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
500 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
501 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
502 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
503 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
504 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
505 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
507 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
508 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
509 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
510 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
512 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
513 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
515 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
516 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
517 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
520 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
521 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
522 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
524 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
525 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
527 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
528 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
529 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
530 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
532 // Altivec does not contain unordered floating-point compare instructions
533 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
534 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
535 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
536 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
538 if (Subtarget.hasVSX()) {
539 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
540 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
542 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
543 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
544 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
545 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
546 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
548 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
550 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
551 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
553 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
554 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
556 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
557 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
558 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
559 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
560 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
562 // Share the Altivec comparison restrictions.
563 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
564 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
565 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
566 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
568 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
569 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
571 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
573 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
575 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
576 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
578 // VSX v2i64 only supports non-arithmetic operations.
579 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
580 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
582 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
583 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
584 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
586 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
588 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
589 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
590 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
591 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
593 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
595 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
596 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
597 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
598 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
600 // Vector operation legalization checks the result type of
601 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
602 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
603 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
604 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
605 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
607 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
611 if (Subtarget.has64BitSupport()) {
612 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
613 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
616 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
617 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
618 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
619 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
621 setBooleanContents(ZeroOrOneBooleanContent);
622 // Altivec instructions set fields to all zeros or all ones.
623 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
626 // These libcalls are not available in 32-bit.
627 setLibcallName(RTLIB::SHL_I128, nullptr);
628 setLibcallName(RTLIB::SRL_I128, nullptr);
629 setLibcallName(RTLIB::SRA_I128, nullptr);
633 setStackPointerRegisterToSaveRestore(PPC::X1);
634 setExceptionPointerRegister(PPC::X3);
635 setExceptionSelectorRegister(PPC::X4);
637 setStackPointerRegisterToSaveRestore(PPC::R1);
638 setExceptionPointerRegister(PPC::R3);
639 setExceptionSelectorRegister(PPC::R4);
642 // We have target-specific dag combine patterns for the following nodes:
643 setTargetDAGCombine(ISD::SINT_TO_FP);
644 setTargetDAGCombine(ISD::LOAD);
645 setTargetDAGCombine(ISD::STORE);
646 setTargetDAGCombine(ISD::BR_CC);
647 if (Subtarget.useCRBits())
648 setTargetDAGCombine(ISD::BRCOND);
649 setTargetDAGCombine(ISD::BSWAP);
650 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
652 setTargetDAGCombine(ISD::SIGN_EXTEND);
653 setTargetDAGCombine(ISD::ZERO_EXTEND);
654 setTargetDAGCombine(ISD::ANY_EXTEND);
656 if (Subtarget.useCRBits()) {
657 setTargetDAGCombine(ISD::TRUNCATE);
658 setTargetDAGCombine(ISD::SETCC);
659 setTargetDAGCombine(ISD::SELECT_CC);
662 // Use reciprocal estimates.
663 if (TM.Options.UnsafeFPMath) {
664 setTargetDAGCombine(ISD::FDIV);
665 setTargetDAGCombine(ISD::FSQRT);
668 // Darwin long double math library functions have $LDBL128 appended.
669 if (Subtarget.isDarwin()) {
670 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
671 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
672 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
673 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
674 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
675 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
676 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
677 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
678 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
679 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
682 // With 32 condition bits, we don't need to sink (and duplicate) compares
683 // aggressively in CodeGenPrep.
684 if (Subtarget.useCRBits())
685 setHasMultipleConditionRegisters();
687 setMinFunctionAlignment(2);
688 if (Subtarget.isDarwin())
689 setPrefFunctionAlignment(4);
691 if (isPPC64 && Subtarget.isJITCodeModel())
692 // Temporary workaround for the inability of PPC64 JIT to handle jump
694 setSupportJumpTables(false);
696 setInsertFencesForAtomic(true);
698 if (Subtarget.enableMachineScheduler())
699 setSchedulingPreference(Sched::Source);
701 setSchedulingPreference(Sched::Hybrid);
703 computeRegisterProperties();
705 // The Freescale cores does better with aggressive inlining of memcpy and
706 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores).
707 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
708 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
709 MaxStoresPerMemset = 32;
710 MaxStoresPerMemsetOptSize = 16;
711 MaxStoresPerMemcpy = 32;
712 MaxStoresPerMemcpyOptSize = 8;
713 MaxStoresPerMemmove = 32;
714 MaxStoresPerMemmoveOptSize = 8;
716 setPrefFunctionAlignment(4);
720 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
721 /// the desired ByVal argument alignment.
722 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
723 unsigned MaxMaxAlign) {
724 if (MaxAlign == MaxMaxAlign)
726 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
727 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
729 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
731 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
732 unsigned EltAlign = 0;
733 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
734 if (EltAlign > MaxAlign)
736 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
737 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
738 unsigned EltAlign = 0;
739 getMaxByValAlign(STy->getElementType(i), EltAlign, MaxMaxAlign);
740 if (EltAlign > MaxAlign)
742 if (MaxAlign == MaxMaxAlign)
748 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
749 /// function arguments in the caller parameter area.
750 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
751 // Darwin passes everything on 4 byte boundary.
752 if (Subtarget.isDarwin())
755 // 16byte and wider vectors are passed on 16byte boundary.
756 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
757 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
758 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
759 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
763 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
765 default: return nullptr;
766 case PPCISD::FSEL: return "PPCISD::FSEL";
767 case PPCISD::FCFID: return "PPCISD::FCFID";
768 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
769 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
770 case PPCISD::FRE: return "PPCISD::FRE";
771 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
772 case PPCISD::STFIWX: return "PPCISD::STFIWX";
773 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
774 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
775 case PPCISD::VPERM: return "PPCISD::VPERM";
776 case PPCISD::Hi: return "PPCISD::Hi";
777 case PPCISD::Lo: return "PPCISD::Lo";
778 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
779 case PPCISD::LOAD: return "PPCISD::LOAD";
780 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
781 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
782 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
783 case PPCISD::SRL: return "PPCISD::SRL";
784 case PPCISD::SRA: return "PPCISD::SRA";
785 case PPCISD::SHL: return "PPCISD::SHL";
786 case PPCISD::CALL: return "PPCISD::CALL";
787 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
788 case PPCISD::MTCTR: return "PPCISD::MTCTR";
789 case PPCISD::BCTRL: return "PPCISD::BCTRL";
790 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
791 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
792 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
793 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
794 case PPCISD::VCMP: return "PPCISD::VCMP";
795 case PPCISD::VCMPo: return "PPCISD::VCMPo";
796 case PPCISD::LBRX: return "PPCISD::LBRX";
797 case PPCISD::STBRX: return "PPCISD::STBRX";
798 case PPCISD::LARX: return "PPCISD::LARX";
799 case PPCISD::STCX: return "PPCISD::STCX";
800 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
801 case PPCISD::BDNZ: return "PPCISD::BDNZ";
802 case PPCISD::BDZ: return "PPCISD::BDZ";
803 case PPCISD::MFFS: return "PPCISD::MFFS";
804 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
805 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
806 case PPCISD::CR6SET: return "PPCISD::CR6SET";
807 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
808 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
809 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
810 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
811 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
812 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
813 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
814 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
815 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
816 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
817 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
818 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
819 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
820 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
821 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
822 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
823 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
824 case PPCISD::SC: return "PPCISD::SC";
828 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
830 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
831 return VT.changeVectorElementTypeToInteger();
834 //===----------------------------------------------------------------------===//
835 // Node matching predicates, for use by the tblgen matching code.
836 //===----------------------------------------------------------------------===//
838 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
839 static bool isFloatingPointZero(SDValue Op) {
840 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
841 return CFP->getValueAPF().isZero();
842 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
843 // Maybe this has already been legalized into the constant pool?
844 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
845 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
846 return CFP->getValueAPF().isZero();
851 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
852 /// true if Op is undef or if it matches the specified value.
853 static bool isConstantOrUndef(int Op, int Val) {
854 return Op < 0 || Op == Val;
857 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
858 /// VPKUHUM instruction.
859 /// The ShuffleKind distinguishes between big-endian operations with
860 /// two different inputs (0), either-endian operations with two identical
861 /// inputs (1), and little-endian operantion with two different inputs (2).
862 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
863 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
865 bool IsLE = DAG.getSubtarget().getDataLayout()->isLittleEndian();
866 if (ShuffleKind == 0) {
869 for (unsigned i = 0; i != 16; ++i)
870 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
872 } else if (ShuffleKind == 2) {
875 for (unsigned i = 0; i != 16; ++i)
876 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
878 } else if (ShuffleKind == 1) {
879 unsigned j = IsLE ? 0 : 1;
880 for (unsigned i = 0; i != 8; ++i)
881 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
882 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
888 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
889 /// VPKUWUM instruction.
890 /// The ShuffleKind distinguishes between big-endian operations with
891 /// two different inputs (0), either-endian operations with two identical
892 /// inputs (1), and little-endian operantion with two different inputs (2).
893 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
894 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
896 bool IsLE = DAG.getSubtarget().getDataLayout()->isLittleEndian();
897 if (ShuffleKind == 0) {
900 for (unsigned i = 0; i != 16; i += 2)
901 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
902 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
904 } else if (ShuffleKind == 2) {
907 for (unsigned i = 0; i != 16; i += 2)
908 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
909 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
911 } else if (ShuffleKind == 1) {
912 unsigned j = IsLE ? 0 : 2;
913 for (unsigned i = 0; i != 8; i += 2)
914 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
915 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
916 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
917 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
923 /// isVMerge - Common function, used to match vmrg* shuffles.
925 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
926 unsigned LHSStart, unsigned RHSStart) {
927 if (N->getValueType(0) != MVT::v16i8)
929 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
930 "Unsupported merge size!");
932 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
933 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
934 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
935 LHSStart+j+i*UnitSize) ||
936 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
937 RHSStart+j+i*UnitSize))
943 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
944 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
945 /// The ShuffleKind distinguishes between big-endian merges with two
946 /// different inputs (0), either-endian merges with two identical inputs (1),
947 /// and little-endian merges with two different inputs (2). For the latter,
948 /// the input operands are swapped (see PPCInstrAltivec.td).
949 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
950 unsigned ShuffleKind, SelectionDAG &DAG) {
951 if (DAG.getSubtarget().getDataLayout()->isLittleEndian()) {
952 if (ShuffleKind == 1) // unary
953 return isVMerge(N, UnitSize, 0, 0);
954 else if (ShuffleKind == 2) // swapped
955 return isVMerge(N, UnitSize, 0, 16);
959 if (ShuffleKind == 1) // unary
960 return isVMerge(N, UnitSize, 8, 8);
961 else if (ShuffleKind == 0) // normal
962 return isVMerge(N, UnitSize, 8, 24);
968 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
969 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
970 /// The ShuffleKind distinguishes between big-endian merges with two
971 /// different inputs (0), either-endian merges with two identical inputs (1),
972 /// and little-endian merges with two different inputs (2). For the latter,
973 /// the input operands are swapped (see PPCInstrAltivec.td).
974 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
975 unsigned ShuffleKind, SelectionDAG &DAG) {
976 if (DAG.getSubtarget().getDataLayout()->isLittleEndian()) {
977 if (ShuffleKind == 1) // unary
978 return isVMerge(N, UnitSize, 8, 8);
979 else if (ShuffleKind == 2) // swapped
980 return isVMerge(N, UnitSize, 8, 24);
984 if (ShuffleKind == 1) // unary
985 return isVMerge(N, UnitSize, 0, 0);
986 else if (ShuffleKind == 0) // normal
987 return isVMerge(N, UnitSize, 0, 16);
994 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
995 /// amount, otherwise return -1.
996 /// The ShuffleKind distinguishes between big-endian operations with two
997 /// different inputs (0), either-endian operations with two identical inputs
998 /// (1), and little-endian operations with two different inputs (2). For the
999 /// latter, the input operands are swapped (see PPCInstrAltivec.td).
1000 int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
1001 SelectionDAG &DAG) {
1002 if (N->getValueType(0) != MVT::v16i8)
1005 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1007 // Find the first non-undef value in the shuffle mask.
1009 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
1012 if (i == 16) return -1; // all undef.
1014 // Otherwise, check to see if the rest of the elements are consecutively
1015 // numbered from this value.
1016 unsigned ShiftAmt = SVOp->getMaskElt(i);
1017 if (ShiftAmt < i) return -1;
1020 bool isLE = DAG.getTarget().getSubtargetImpl()->getDataLayout()->
1023 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
1024 // Check the rest of the elements to see if they are consecutive.
1025 for (++i; i != 16; ++i)
1026 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1028 } else if (ShuffleKind == 1) {
1029 // Check the rest of the elements to see if they are consecutive.
1030 for (++i; i != 16; ++i)
1031 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1036 if (ShuffleKind == 2 && isLE)
1037 ShiftAmt = 16 - ShiftAmt;
1042 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1043 /// specifies a splat of a single element that is suitable for input to
1044 /// VSPLTB/VSPLTH/VSPLTW.
1045 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1046 assert(N->getValueType(0) == MVT::v16i8 &&
1047 (EltSize == 1 || EltSize == 2 || EltSize == 4));
1049 // This is a splat operation if each element of the permute is the same, and
1050 // if the value doesn't reference the second vector.
1051 unsigned ElementBase = N->getMaskElt(0);
1053 // FIXME: Handle UNDEF elements too!
1054 if (ElementBase >= 16)
1057 // Check that the indices are consecutive, in the case of a multi-byte element
1058 // splatted with a v16i8 mask.
1059 for (unsigned i = 1; i != EltSize; ++i)
1060 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1063 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1064 if (N->getMaskElt(i) < 0) continue;
1065 for (unsigned j = 0; j != EltSize; ++j)
1066 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1072 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
1074 bool PPC::isAllNegativeZeroVector(SDNode *N) {
1075 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
1077 APInt APVal, APUndef;
1081 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
1082 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
1083 return CFP->getValueAPF().isNegZero();
1088 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1089 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1090 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1091 SelectionDAG &DAG) {
1092 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1093 assert(isSplatShuffleMask(SVOp, EltSize));
1094 if (DAG.getSubtarget().getDataLayout()->isLittleEndian())
1095 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1097 return SVOp->getMaskElt(0) / EltSize;
1100 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1101 /// by using a vspltis[bhw] instruction of the specified element size, return
1102 /// the constant being splatted. The ByteSize field indicates the number of
1103 /// bytes of each element [124] -> [bhw].
1104 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1105 SDValue OpVal(nullptr, 0);
1107 // If ByteSize of the splat is bigger than the element size of the
1108 // build_vector, then we have a case where we are checking for a splat where
1109 // multiple elements of the buildvector are folded together into a single
1110 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1111 unsigned EltSize = 16/N->getNumOperands();
1112 if (EltSize < ByteSize) {
1113 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1114 SDValue UniquedVals[4];
1115 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1117 // See if all of the elements in the buildvector agree across.
1118 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1119 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1120 // If the element isn't a constant, bail fully out.
1121 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1124 if (!UniquedVals[i&(Multiple-1)].getNode())
1125 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1126 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1127 return SDValue(); // no match.
1130 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1131 // either constant or undef values that are identical for each chunk. See
1132 // if these chunks can form into a larger vspltis*.
1134 // Check to see if all of the leading entries are either 0 or -1. If
1135 // neither, then this won't fit into the immediate field.
1136 bool LeadingZero = true;
1137 bool LeadingOnes = true;
1138 for (unsigned i = 0; i != Multiple-1; ++i) {
1139 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1141 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
1142 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
1144 // Finally, check the least significant entry.
1146 if (!UniquedVals[Multiple-1].getNode())
1147 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
1148 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1150 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
1153 if (!UniquedVals[Multiple-1].getNode())
1154 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
1155 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1156 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1157 return DAG.getTargetConstant(Val, MVT::i32);
1163 // Check to see if this buildvec has a single non-undef value in its elements.
1164 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1165 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1166 if (!OpVal.getNode())
1167 OpVal = N->getOperand(i);
1168 else if (OpVal != N->getOperand(i))
1172 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1174 unsigned ValSizeInBytes = EltSize;
1176 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1177 Value = CN->getZExtValue();
1178 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1179 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1180 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1183 // If the splat value is larger than the element value, then we can never do
1184 // this splat. The only case that we could fit the replicated bits into our
1185 // immediate field for would be zero, and we prefer to use vxor for it.
1186 if (ValSizeInBytes < ByteSize) return SDValue();
1188 // If the element value is larger than the splat value, cut it in half and
1189 // check to see if the two halves are equal. Continue doing this until we
1190 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
1191 while (ValSizeInBytes > ByteSize) {
1192 ValSizeInBytes >>= 1;
1194 // If the top half equals the bottom half, we're still ok.
1195 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
1196 (Value & ((1 << (8*ValSizeInBytes))-1)))
1200 // Properly sign extend the value.
1201 int MaskVal = SignExtend32(Value, ByteSize * 8);
1203 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1204 if (MaskVal == 0) return SDValue();
1206 // Finally, if this value fits in a 5 bit sext field, return it
1207 if (SignExtend32<5>(MaskVal) == MaskVal)
1208 return DAG.getTargetConstant(MaskVal, MVT::i32);
1212 //===----------------------------------------------------------------------===//
1213 // Addressing Mode Selection
1214 //===----------------------------------------------------------------------===//
1216 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1217 /// or 64-bit immediate, and if the value can be accurately represented as a
1218 /// sign extension from a 16-bit value. If so, this returns true and the
1220 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1221 if (!isa<ConstantSDNode>(N))
1224 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1225 if (N->getValueType(0) == MVT::i32)
1226 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1228 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1230 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1231 return isIntS16Immediate(Op.getNode(), Imm);
1235 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1236 /// can be represented as an indexed [r+r] operation. Returns false if it
1237 /// can be more efficiently represented with [r+imm].
1238 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1240 SelectionDAG &DAG) const {
1242 if (N.getOpcode() == ISD::ADD) {
1243 if (isIntS16Immediate(N.getOperand(1), imm))
1244 return false; // r+i
1245 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1246 return false; // r+i
1248 Base = N.getOperand(0);
1249 Index = N.getOperand(1);
1251 } else if (N.getOpcode() == ISD::OR) {
1252 if (isIntS16Immediate(N.getOperand(1), imm))
1253 return false; // r+i can fold it if we can.
1255 // If this is an or of disjoint bitfields, we can codegen this as an add
1256 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1258 APInt LHSKnownZero, LHSKnownOne;
1259 APInt RHSKnownZero, RHSKnownOne;
1260 DAG.computeKnownBits(N.getOperand(0),
1261 LHSKnownZero, LHSKnownOne);
1263 if (LHSKnownZero.getBoolValue()) {
1264 DAG.computeKnownBits(N.getOperand(1),
1265 RHSKnownZero, RHSKnownOne);
1266 // If all of the bits are known zero on the LHS or RHS, the add won't
1268 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1269 Base = N.getOperand(0);
1270 Index = N.getOperand(1);
1279 // If we happen to be doing an i64 load or store into a stack slot that has
1280 // less than a 4-byte alignment, then the frame-index elimination may need to
1281 // use an indexed load or store instruction (because the offset may not be a
1282 // multiple of 4). The extra register needed to hold the offset comes from the
1283 // register scavenger, and it is possible that the scavenger will need to use
1284 // an emergency spill slot. As a result, we need to make sure that a spill slot
1285 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1287 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1288 // FIXME: This does not handle the LWA case.
1292 // NOTE: We'll exclude negative FIs here, which come from argument
1293 // lowering, because there are no known test cases triggering this problem
1294 // using packed structures (or similar). We can remove this exclusion if
1295 // we find such a test case. The reason why this is so test-case driven is
1296 // because this entire 'fixup' is only to prevent crashes (from the
1297 // register scavenger) on not-really-valid inputs. For example, if we have:
1299 // %b = bitcast i1* %a to i64*
1300 // store i64* a, i64 b
1301 // then the store should really be marked as 'align 1', but is not. If it
1302 // were marked as 'align 1' then the indexed form would have been
1303 // instruction-selected initially, and the problem this 'fixup' is preventing
1304 // won't happen regardless.
1308 MachineFunction &MF = DAG.getMachineFunction();
1309 MachineFrameInfo *MFI = MF.getFrameInfo();
1311 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1315 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1316 FuncInfo->setHasNonRISpills();
1319 /// Returns true if the address N can be represented by a base register plus
1320 /// a signed 16-bit displacement [r+imm], and if it is not better
1321 /// represented as reg+reg. If Aligned is true, only accept displacements
1322 /// suitable for STD and friends, i.e. multiples of 4.
1323 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1326 bool Aligned) const {
1327 // FIXME dl should come from parent load or store, not from address
1329 // If this can be more profitably realized as r+r, fail.
1330 if (SelectAddressRegReg(N, Disp, Base, DAG))
1333 if (N.getOpcode() == ISD::ADD) {
1335 if (isIntS16Immediate(N.getOperand(1), imm) &&
1336 (!Aligned || (imm & 3) == 0)) {
1337 Disp = DAG.getTargetConstant(imm, N.getValueType());
1338 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1339 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1340 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1342 Base = N.getOperand(0);
1344 return true; // [r+i]
1345 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1346 // Match LOAD (ADD (X, Lo(G))).
1347 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1348 && "Cannot handle constant offsets yet!");
1349 Disp = N.getOperand(1).getOperand(0); // The global address.
1350 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1351 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1352 Disp.getOpcode() == ISD::TargetConstantPool ||
1353 Disp.getOpcode() == ISD::TargetJumpTable);
1354 Base = N.getOperand(0);
1355 return true; // [&g+r]
1357 } else if (N.getOpcode() == ISD::OR) {
1359 if (isIntS16Immediate(N.getOperand(1), imm) &&
1360 (!Aligned || (imm & 3) == 0)) {
1361 // If this is an or of disjoint bitfields, we can codegen this as an add
1362 // (for better address arithmetic) if the LHS and RHS of the OR are
1363 // provably disjoint.
1364 APInt LHSKnownZero, LHSKnownOne;
1365 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1367 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1368 // If all of the bits are known zero on the LHS or RHS, the add won't
1370 if (FrameIndexSDNode *FI =
1371 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1372 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1373 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1375 Base = N.getOperand(0);
1377 Disp = DAG.getTargetConstant(imm, N.getValueType());
1381 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1382 // Loading from a constant address.
1384 // If this address fits entirely in a 16-bit sext immediate field, codegen
1387 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1388 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1389 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1390 CN->getValueType(0));
1394 // Handle 32-bit sext immediates with LIS + addr mode.
1395 if ((CN->getValueType(0) == MVT::i32 ||
1396 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1397 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1398 int Addr = (int)CN->getZExtValue();
1400 // Otherwise, break this down into an LIS + disp.
1401 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1403 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1404 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1405 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1410 Disp = DAG.getTargetConstant(0, getPointerTy());
1411 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1412 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1413 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1416 return true; // [r+0]
1419 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1420 /// represented as an indexed [r+r] operation.
1421 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1423 SelectionDAG &DAG) const {
1424 // Check to see if we can easily represent this as an [r+r] address. This
1425 // will fail if it thinks that the address is more profitably represented as
1426 // reg+imm, e.g. where imm = 0.
1427 if (SelectAddressRegReg(N, Base, Index, DAG))
1430 // If the operand is an addition, always emit this as [r+r], since this is
1431 // better (for code size, and execution, as the memop does the add for free)
1432 // than emitting an explicit add.
1433 if (N.getOpcode() == ISD::ADD) {
1434 Base = N.getOperand(0);
1435 Index = N.getOperand(1);
1439 // Otherwise, do it the hard way, using R0 as the base register.
1440 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1446 /// getPreIndexedAddressParts - returns true by value, base pointer and
1447 /// offset pointer and addressing mode by reference if the node's address
1448 /// can be legally represented as pre-indexed load / store address.
1449 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1451 ISD::MemIndexedMode &AM,
1452 SelectionDAG &DAG) const {
1453 if (DisablePPCPreinc) return false;
1459 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1460 Ptr = LD->getBasePtr();
1461 VT = LD->getMemoryVT();
1462 Alignment = LD->getAlignment();
1463 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1464 Ptr = ST->getBasePtr();
1465 VT = ST->getMemoryVT();
1466 Alignment = ST->getAlignment();
1471 // PowerPC doesn't have preinc load/store instructions for vectors.
1475 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1477 // Common code will reject creating a pre-inc form if the base pointer
1478 // is a frame index, or if N is a store and the base pointer is either
1479 // the same as or a predecessor of the value being stored. Check for
1480 // those situations here, and try with swapped Base/Offset instead.
1483 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1486 SDValue Val = cast<StoreSDNode>(N)->getValue();
1487 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1492 std::swap(Base, Offset);
1498 // LDU/STU can only handle immediates that are a multiple of 4.
1499 if (VT != MVT::i64) {
1500 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1503 // LDU/STU need an address with at least 4-byte alignment.
1507 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1511 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1512 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1513 // sext i32 to i64 when addr mode is r+i.
1514 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1515 LD->getExtensionType() == ISD::SEXTLOAD &&
1516 isa<ConstantSDNode>(Offset))
1524 //===----------------------------------------------------------------------===//
1525 // LowerOperation implementation
1526 //===----------------------------------------------------------------------===//
1528 /// GetLabelAccessInfo - Return true if we should reference labels using a
1529 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1530 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1531 unsigned &LoOpFlags,
1532 const GlobalValue *GV = nullptr) {
1533 HiOpFlags = PPCII::MO_HA;
1534 LoOpFlags = PPCII::MO_LO;
1536 // Don't use the pic base if not in PIC relocation model.
1537 bool isPIC = TM.getRelocationModel() == Reloc::PIC_;
1540 HiOpFlags |= PPCII::MO_PIC_FLAG;
1541 LoOpFlags |= PPCII::MO_PIC_FLAG;
1544 // If this is a reference to a global value that requires a non-lazy-ptr, make
1545 // sure that instruction lowering adds it.
1546 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1547 HiOpFlags |= PPCII::MO_NLP_FLAG;
1548 LoOpFlags |= PPCII::MO_NLP_FLAG;
1550 if (GV->hasHiddenVisibility()) {
1551 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1552 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1559 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1560 SelectionDAG &DAG) {
1561 EVT PtrVT = HiPart.getValueType();
1562 SDValue Zero = DAG.getConstant(0, PtrVT);
1565 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1566 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1568 // With PIC, the first instruction is actually "GR+hi(&G)".
1570 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1571 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1573 // Generate non-pic code that has direct accesses to the constant pool.
1574 // The address of the global is just (hi(&g)+lo(&g)).
1575 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1578 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1579 SelectionDAG &DAG) const {
1580 EVT PtrVT = Op.getValueType();
1581 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1582 const Constant *C = CP->getConstVal();
1584 // 64-bit SVR4 ABI code is always position-independent.
1585 // The actual address of the GlobalValue is stored in the TOC.
1586 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1587 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1588 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1589 DAG.getRegister(PPC::X2, MVT::i64));
1592 unsigned MOHiFlag, MOLoFlag;
1593 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1595 if (isPIC && Subtarget.isSVR4ABI()) {
1596 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
1597 PPCII::MO_PIC_FLAG);
1599 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1600 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1604 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1606 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1607 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1610 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1611 EVT PtrVT = Op.getValueType();
1612 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1614 // 64-bit SVR4 ABI code is always position-independent.
1615 // The actual address of the GlobalValue is stored in the TOC.
1616 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1617 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1618 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1619 DAG.getRegister(PPC::X2, MVT::i64));
1622 unsigned MOHiFlag, MOLoFlag;
1623 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1625 if (isPIC && Subtarget.isSVR4ABI()) {
1626 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
1627 PPCII::MO_PIC_FLAG);
1629 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), PtrVT, GA,
1630 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1633 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1634 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1635 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1638 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1639 SelectionDAG &DAG) const {
1640 EVT PtrVT = Op.getValueType();
1642 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1644 unsigned MOHiFlag, MOLoFlag;
1645 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1646 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1647 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1648 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1651 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1652 SelectionDAG &DAG) const {
1654 // FIXME: TLS addresses currently use medium model code sequences,
1655 // which is the most useful form. Eventually support for small and
1656 // large models could be added if users need it, at the cost of
1657 // additional complexity.
1658 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1660 const GlobalValue *GV = GA->getGlobal();
1661 EVT PtrVT = getPointerTy();
1662 bool is64bit = Subtarget.isPPC64();
1664 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1666 if (Model == TLSModel::LocalExec) {
1667 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1668 PPCII::MO_TPREL_HA);
1669 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1670 PPCII::MO_TPREL_LO);
1671 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1672 is64bit ? MVT::i64 : MVT::i32);
1673 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1674 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1677 if (Model == TLSModel::InitialExec) {
1678 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1679 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1683 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1684 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1685 PtrVT, GOTReg, TGA);
1687 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
1688 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1689 PtrVT, TGA, GOTPtr);
1690 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
1693 if (Model == TLSModel::GeneralDynamic) {
1694 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1697 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1698 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1701 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
1703 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1706 // We need a chain node, and don't have one handy. The underlying
1707 // call has no side effects, so using the function entry node
1709 SDValue Chain = DAG.getEntryNode();
1710 Chain = DAG.getCopyToReg(Chain, dl,
1711 is64bit ? PPC::X3 : PPC::R3, GOTEntry);
1712 SDValue ParmReg = DAG.getRegister(is64bit ? PPC::X3 : PPC::R3,
1713 is64bit ? MVT::i64 : MVT::i32);
1714 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl,
1715 PtrVT, ParmReg, TGA);
1716 // The return value from GET_TLS_ADDR really is in X3 already, but
1717 // some hacks are needed here to tie everything together. The extra
1718 // copies dissolve during subsequent transforms.
1719 Chain = DAG.getCopyToReg(Chain, dl, is64bit ? PPC::X3 : PPC::R3, TLSAddr);
1720 return DAG.getCopyFromReg(Chain, dl, is64bit ? PPC::X3 : PPC::R3, PtrVT);
1723 if (Model == TLSModel::LocalDynamic) {
1724 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1727 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1728 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1731 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
1733 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1736 // We need a chain node, and don't have one handy. The underlying
1737 // call has no side effects, so using the function entry node
1739 SDValue Chain = DAG.getEntryNode();
1740 Chain = DAG.getCopyToReg(Chain, dl,
1741 is64bit ? PPC::X3 : PPC::R3, GOTEntry);
1742 SDValue ParmReg = DAG.getRegister(is64bit ? PPC::X3 : PPC::R3,
1743 is64bit ? MVT::i64 : MVT::i32);
1744 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl,
1745 PtrVT, ParmReg, TGA);
1746 // The return value from GET_TLSLD_ADDR really is in X3 already, but
1747 // some hacks are needed here to tie everything together. The extra
1748 // copies dissolve during subsequent transforms.
1749 Chain = DAG.getCopyToReg(Chain, dl, is64bit ? PPC::X3 : PPC::R3, TLSAddr);
1750 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1751 Chain, ParmReg, TGA);
1752 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1755 llvm_unreachable("Unknown TLS model!");
1758 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1759 SelectionDAG &DAG) const {
1760 EVT PtrVT = Op.getValueType();
1761 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1763 const GlobalValue *GV = GSDN->getGlobal();
1765 // 64-bit SVR4 ABI code is always position-independent.
1766 // The actual address of the GlobalValue is stored in the TOC.
1767 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1768 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1769 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1770 DAG.getRegister(PPC::X2, MVT::i64));
1773 unsigned MOHiFlag, MOLoFlag;
1774 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1776 if (isPIC && Subtarget.isSVR4ABI()) {
1777 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
1779 PPCII::MO_PIC_FLAG);
1780 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1781 DAG.getNode(PPCISD::GlobalBaseReg, DL, MVT::i32));
1785 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1787 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1789 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1791 // If the global reference is actually to a non-lazy-pointer, we have to do an
1792 // extra load to get the address of the global.
1793 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1794 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1795 false, false, false, 0);
1799 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1800 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1803 if (Op.getValueType() == MVT::v2i64) {
1804 // When the operands themselves are v2i64 values, we need to do something
1805 // special because VSX has no underlying comparison operations for these.
1806 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
1807 // Equality can be handled by casting to the legal type for Altivec
1808 // comparisons, everything else needs to be expanded.
1809 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1810 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
1811 DAG.getSetCC(dl, MVT::v4i32,
1812 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
1813 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
1820 // We handle most of these in the usual way.
1824 // If we're comparing for equality to zero, expose the fact that this is
1825 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1826 // fold the new nodes.
1827 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1828 if (C->isNullValue() && CC == ISD::SETEQ) {
1829 EVT VT = Op.getOperand(0).getValueType();
1830 SDValue Zext = Op.getOperand(0);
1831 if (VT.bitsLT(MVT::i32)) {
1833 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1835 unsigned Log2b = Log2_32(VT.getSizeInBits());
1836 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1837 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1838 DAG.getConstant(Log2b, MVT::i32));
1839 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1841 // Leave comparisons against 0 and -1 alone for now, since they're usually
1842 // optimized. FIXME: revisit this when we can custom lower all setcc
1844 if (C->isAllOnesValue() || C->isNullValue())
1848 // If we have an integer seteq/setne, turn it into a compare against zero
1849 // by xor'ing the rhs with the lhs, which is faster than setting a
1850 // condition register, reading it back out, and masking the correct bit. The
1851 // normal approach here uses sub to do this instead of xor. Using xor exposes
1852 // the result to other bit-twiddling opportunities.
1853 EVT LHSVT = Op.getOperand(0).getValueType();
1854 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1855 EVT VT = Op.getValueType();
1856 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1858 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1863 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1864 const PPCSubtarget &Subtarget) const {
1865 SDNode *Node = Op.getNode();
1866 EVT VT = Node->getValueType(0);
1867 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1868 SDValue InChain = Node->getOperand(0);
1869 SDValue VAListPtr = Node->getOperand(1);
1870 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1873 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1876 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1877 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1878 false, false, false, 0);
1879 InChain = GprIndex.getValue(1);
1881 if (VT == MVT::i64) {
1882 // Check if GprIndex is even
1883 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1884 DAG.getConstant(1, MVT::i32));
1885 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1886 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1887 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1888 DAG.getConstant(1, MVT::i32));
1889 // Align GprIndex to be even if it isn't
1890 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1894 // fpr index is 1 byte after gpr
1895 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1896 DAG.getConstant(1, MVT::i32));
1899 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1900 FprPtr, MachinePointerInfo(SV), MVT::i8,
1901 false, false, false, 0);
1902 InChain = FprIndex.getValue(1);
1904 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1905 DAG.getConstant(8, MVT::i32));
1907 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1908 DAG.getConstant(4, MVT::i32));
1911 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1912 MachinePointerInfo(), false, false,
1914 InChain = OverflowArea.getValue(1);
1916 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1917 MachinePointerInfo(), false, false,
1919 InChain = RegSaveArea.getValue(1);
1921 // select overflow_area if index > 8
1922 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1923 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1925 // adjustment constant gpr_index * 4/8
1926 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1927 VT.isInteger() ? GprIndex : FprIndex,
1928 DAG.getConstant(VT.isInteger() ? 4 : 8,
1931 // OurReg = RegSaveArea + RegConstant
1932 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1935 // Floating types are 32 bytes into RegSaveArea
1936 if (VT.isFloatingPoint())
1937 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1938 DAG.getConstant(32, MVT::i32));
1940 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1941 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1942 VT.isInteger() ? GprIndex : FprIndex,
1943 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1946 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1947 VT.isInteger() ? VAListPtr : FprPtr,
1948 MachinePointerInfo(SV),
1949 MVT::i8, false, false, 0);
1951 // determine if we should load from reg_save_area or overflow_area
1952 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1954 // increase overflow_area by 4/8 if gpr/fpr > 8
1955 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1956 DAG.getConstant(VT.isInteger() ? 4 : 8,
1959 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1962 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1964 MachinePointerInfo(),
1965 MVT::i32, false, false, 0);
1967 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1968 false, false, false, 0);
1971 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
1972 const PPCSubtarget &Subtarget) const {
1973 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
1975 // We have to copy the entire va_list struct:
1976 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
1977 return DAG.getMemcpy(Op.getOperand(0), Op,
1978 Op.getOperand(1), Op.getOperand(2),
1979 DAG.getConstant(12, MVT::i32), 8, false, true,
1980 MachinePointerInfo(), MachinePointerInfo());
1983 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
1984 SelectionDAG &DAG) const {
1985 return Op.getOperand(0);
1988 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
1989 SelectionDAG &DAG) const {
1990 SDValue Chain = Op.getOperand(0);
1991 SDValue Trmp = Op.getOperand(1); // trampoline
1992 SDValue FPtr = Op.getOperand(2); // nested function
1993 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1996 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1997 bool isPPC64 = (PtrVT == MVT::i64);
1999 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
2002 TargetLowering::ArgListTy Args;
2003 TargetLowering::ArgListEntry Entry;
2005 Entry.Ty = IntPtrTy;
2006 Entry.Node = Trmp; Args.push_back(Entry);
2008 // TrampSize == (isPPC64 ? 48 : 40);
2009 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
2010 isPPC64 ? MVT::i64 : MVT::i32);
2011 Args.push_back(Entry);
2013 Entry.Node = FPtr; Args.push_back(Entry);
2014 Entry.Node = Nest; Args.push_back(Entry);
2016 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
2017 TargetLowering::CallLoweringInfo CLI(DAG);
2018 CLI.setDebugLoc(dl).setChain(Chain)
2019 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
2020 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
2021 std::move(Args), 0);
2023 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2024 return CallResult.second;
2027 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
2028 const PPCSubtarget &Subtarget) const {
2029 MachineFunction &MF = DAG.getMachineFunction();
2030 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2034 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
2035 // vastart just stores the address of the VarArgsFrameIndex slot into the
2036 // memory location argument.
2037 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2038 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2039 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2040 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2041 MachinePointerInfo(SV),
2045 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
2046 // We suppose the given va_list is already allocated.
2049 // char gpr; /* index into the array of 8 GPRs
2050 // * stored in the register save area
2051 // * gpr=0 corresponds to r3,
2052 // * gpr=1 to r4, etc.
2054 // char fpr; /* index into the array of 8 FPRs
2055 // * stored in the register save area
2056 // * fpr=0 corresponds to f1,
2057 // * fpr=1 to f2, etc.
2059 // char *overflow_arg_area;
2060 // /* location on stack that holds
2061 // * the next overflow argument
2063 // char *reg_save_area;
2064 // /* where r3:r10 and f1:f8 (if saved)
2070 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
2071 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
2074 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2076 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
2078 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2081 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2082 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
2084 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2085 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
2087 uint64_t FPROffset = 1;
2088 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
2090 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2092 // Store first byte : number of int regs
2093 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
2095 MachinePointerInfo(SV),
2096 MVT::i8, false, false, 0);
2097 uint64_t nextOffset = FPROffset;
2098 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2101 // Store second byte : number of float regs
2102 SDValue secondStore =
2103 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2104 MachinePointerInfo(SV, nextOffset), MVT::i8,
2106 nextOffset += StackOffset;
2107 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2109 // Store second word : arguments given on stack
2110 SDValue thirdStore =
2111 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2112 MachinePointerInfo(SV, nextOffset),
2114 nextOffset += FrameOffset;
2115 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2117 // Store third word : arguments given in registers
2118 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2119 MachinePointerInfo(SV, nextOffset),
2124 #include "PPCGenCallingConv.inc"
2126 // Function whose sole purpose is to kill compiler warnings
2127 // stemming from unused functions included from PPCGenCallingConv.inc.
2128 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2129 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2132 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2133 CCValAssign::LocInfo &LocInfo,
2134 ISD::ArgFlagsTy &ArgFlags,
2139 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2141 CCValAssign::LocInfo &LocInfo,
2142 ISD::ArgFlagsTy &ArgFlags,
2144 static const MCPhysReg ArgRegs[] = {
2145 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2146 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2148 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2150 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2152 // Skip one register if the first unallocated register has an even register
2153 // number and there are still argument registers available which have not been
2154 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2155 // need to skip a register if RegNum is odd.
2156 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2157 State.AllocateReg(ArgRegs[RegNum]);
2160 // Always return false here, as this function only makes sure that the first
2161 // unallocated register has an odd register number and does not actually
2162 // allocate a register for the current argument.
2166 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2168 CCValAssign::LocInfo &LocInfo,
2169 ISD::ArgFlagsTy &ArgFlags,
2171 static const MCPhysReg ArgRegs[] = {
2172 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2176 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2178 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2180 // If there is only one Floating-point register left we need to put both f64
2181 // values of a split ppc_fp128 value on the stack.
2182 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2183 State.AllocateReg(ArgRegs[RegNum]);
2186 // Always return false here, as this function only makes sure that the two f64
2187 // values a ppc_fp128 value is split into are both passed in registers or both
2188 // passed on the stack and does not actually allocate a register for the
2189 // current argument.
2193 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
2195 static const MCPhysReg *GetFPR() {
2196 static const MCPhysReg FPR[] = {
2197 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2198 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
2204 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2206 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2207 unsigned PtrByteSize) {
2208 unsigned ArgSize = ArgVT.getStoreSize();
2209 if (Flags.isByVal())
2210 ArgSize = Flags.getByValSize();
2212 // Round up to multiples of the pointer size, except for array members,
2213 // which are always packed.
2214 if (!Flags.isInConsecutiveRegs())
2215 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2220 /// CalculateStackSlotAlignment - Calculates the alignment of this argument
2222 static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
2223 ISD::ArgFlagsTy Flags,
2224 unsigned PtrByteSize) {
2225 unsigned Align = PtrByteSize;
2227 // Altivec parameters are padded to a 16 byte boundary.
2228 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2229 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2230 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2233 // ByVal parameters are aligned as requested.
2234 if (Flags.isByVal()) {
2235 unsigned BVAlign = Flags.getByValAlign();
2236 if (BVAlign > PtrByteSize) {
2237 if (BVAlign % PtrByteSize != 0)
2239 "ByVal alignment is not a multiple of the pointer size");
2245 // Array members are always packed to their original alignment.
2246 if (Flags.isInConsecutiveRegs()) {
2247 // If the array member was split into multiple registers, the first
2248 // needs to be aligned to the size of the full type. (Except for
2249 // ppcf128, which is only aligned as its f64 components.)
2250 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
2251 Align = OrigVT.getStoreSize();
2253 Align = ArgVT.getStoreSize();
2259 /// CalculateStackSlotUsed - Return whether this argument will use its
2260 /// stack slot (instead of being passed in registers). ArgOffset,
2261 /// AvailableFPRs, and AvailableVRs must hold the current argument
2262 /// position, and will be updated to account for this argument.
2263 static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT,
2264 ISD::ArgFlagsTy Flags,
2265 unsigned PtrByteSize,
2266 unsigned LinkageSize,
2267 unsigned ParamAreaSize,
2268 unsigned &ArgOffset,
2269 unsigned &AvailableFPRs,
2270 unsigned &AvailableVRs) {
2271 bool UseMemory = false;
2273 // Respect alignment of argument on the stack.
2275 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
2276 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2277 // If there's no space left in the argument save area, we must
2278 // use memory (this check also catches zero-sized arguments).
2279 if (ArgOffset >= LinkageSize + ParamAreaSize)
2282 // Allocate argument on the stack.
2283 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2284 if (Flags.isInConsecutiveRegsLast())
2285 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2286 // If we overran the argument save area, we must use memory
2287 // (this check catches arguments passed partially in memory)
2288 if (ArgOffset > LinkageSize + ParamAreaSize)
2291 // However, if the argument is actually passed in an FPR or a VR,
2292 // we don't use memory after all.
2293 if (!Flags.isByVal()) {
2294 if (ArgVT == MVT::f32 || ArgVT == MVT::f64)
2295 if (AvailableFPRs > 0) {
2299 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2300 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2301 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2302 if (AvailableVRs > 0) {
2311 /// EnsureStackAlignment - Round stack frame size up from NumBytes to
2312 /// ensure minimum alignment required for target.
2313 static unsigned EnsureStackAlignment(const TargetMachine &Target,
2314 unsigned NumBytes) {
2315 unsigned TargetAlign =
2316 Target.getSubtargetImpl()->getFrameLowering()->getStackAlignment();
2317 unsigned AlignMask = TargetAlign - 1;
2318 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2323 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
2324 CallingConv::ID CallConv, bool isVarArg,
2325 const SmallVectorImpl<ISD::InputArg>
2327 SDLoc dl, SelectionDAG &DAG,
2328 SmallVectorImpl<SDValue> &InVals)
2330 if (Subtarget.isSVR4ABI()) {
2331 if (Subtarget.isPPC64())
2332 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2335 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2338 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2344 PPCTargetLowering::LowerFormalArguments_32SVR4(
2346 CallingConv::ID CallConv, bool isVarArg,
2347 const SmallVectorImpl<ISD::InputArg>
2349 SDLoc dl, SelectionDAG &DAG,
2350 SmallVectorImpl<SDValue> &InVals) const {
2352 // 32-bit SVR4 ABI Stack Frame Layout:
2353 // +-----------------------------------+
2354 // +--> | Back chain |
2355 // | +-----------------------------------+
2356 // | | Floating-point register save area |
2357 // | +-----------------------------------+
2358 // | | General register save area |
2359 // | +-----------------------------------+
2360 // | | CR save word |
2361 // | +-----------------------------------+
2362 // | | VRSAVE save word |
2363 // | +-----------------------------------+
2364 // | | Alignment padding |
2365 // | +-----------------------------------+
2366 // | | Vector register save area |
2367 // | +-----------------------------------+
2368 // | | Local variable space |
2369 // | +-----------------------------------+
2370 // | | Parameter list area |
2371 // | +-----------------------------------+
2372 // | | LR save word |
2373 // | +-----------------------------------+
2374 // SP--> +--- | Back chain |
2375 // +-----------------------------------+
2378 // System V Application Binary Interface PowerPC Processor Supplement
2379 // AltiVec Technology Programming Interface Manual
2381 MachineFunction &MF = DAG.getMachineFunction();
2382 MachineFrameInfo *MFI = MF.getFrameInfo();
2383 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2385 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2386 // Potential tail calls could cause overwriting of argument stack slots.
2387 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2388 (CallConv == CallingConv::Fast));
2389 unsigned PtrByteSize = 4;
2391 // Assign locations to all of the incoming arguments.
2392 SmallVector<CCValAssign, 16> ArgLocs;
2393 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2396 // Reserve space for the linkage area on the stack.
2397 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(false, false, false);
2398 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
2400 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2402 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2403 CCValAssign &VA = ArgLocs[i];
2405 // Arguments stored in registers.
2406 if (VA.isRegLoc()) {
2407 const TargetRegisterClass *RC;
2408 EVT ValVT = VA.getValVT();
2410 switch (ValVT.getSimpleVT().SimpleTy) {
2412 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2415 RC = &PPC::GPRCRegClass;
2418 RC = &PPC::F4RCRegClass;
2421 if (Subtarget.hasVSX())
2422 RC = &PPC::VSFRCRegClass;
2424 RC = &PPC::F8RCRegClass;
2430 RC = &PPC::VRRCRegClass;
2434 RC = &PPC::VSHRCRegClass;
2438 // Transform the arguments stored in physical registers into virtual ones.
2439 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2440 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2441 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2443 if (ValVT == MVT::i1)
2444 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2446 InVals.push_back(ArgValue);
2448 // Argument stored in memory.
2449 assert(VA.isMemLoc());
2451 unsigned ArgSize = VA.getLocVT().getStoreSize();
2452 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2455 // Create load nodes to retrieve arguments from the stack.
2456 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2457 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2458 MachinePointerInfo(),
2459 false, false, false, 0));
2463 // Assign locations to all of the incoming aggregate by value arguments.
2464 // Aggregates passed by value are stored in the local variable space of the
2465 // caller's stack frame, right above the parameter list area.
2466 SmallVector<CCValAssign, 16> ByValArgLocs;
2467 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2468 ByValArgLocs, *DAG.getContext());
2470 // Reserve stack space for the allocations in CCInfo.
2471 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2473 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2475 // Area that is at least reserved in the caller of this function.
2476 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2477 MinReservedArea = std::max(MinReservedArea, LinkageSize);
2479 // Set the size that is at least reserved in caller of this function. Tail
2480 // call optimized function's reserved stack space needs to be aligned so that
2481 // taking the difference between two stack areas will result in an aligned
2483 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2484 FuncInfo->setMinReservedArea(MinReservedArea);
2486 SmallVector<SDValue, 8> MemOps;
2488 // If the function takes variable number of arguments, make a frame index for
2489 // the start of the first vararg value... for expansion of llvm.va_start.
2491 static const MCPhysReg GPArgRegs[] = {
2492 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2493 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2495 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2497 static const MCPhysReg FPArgRegs[] = {
2498 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2501 unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2502 if (DisablePPCFloatInVariadic)
2505 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2507 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2510 // Make room for NumGPArgRegs and NumFPArgRegs.
2511 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2512 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
2514 FuncInfo->setVarArgsStackOffset(
2515 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2516 CCInfo.getNextStackOffset(), true));
2518 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2519 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2521 // The fixed integer arguments of a variadic function are stored to the
2522 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2523 // the result of va_next.
2524 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2525 // Get an existing live-in vreg, or add a new one.
2526 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2528 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2530 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2531 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2532 MachinePointerInfo(), false, false, 0);
2533 MemOps.push_back(Store);
2534 // Increment the address by four for the next argument to store
2535 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2536 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2539 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2541 // The double arguments are stored to the VarArgsFrameIndex
2543 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2544 // Get an existing live-in vreg, or add a new one.
2545 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2547 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2549 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2550 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2551 MachinePointerInfo(), false, false, 0);
2552 MemOps.push_back(Store);
2553 // Increment the address by eight for the next argument to store
2554 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
2556 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2560 if (!MemOps.empty())
2561 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2566 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2567 // value to MVT::i64 and then truncate to the correct register size.
2569 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2570 SelectionDAG &DAG, SDValue ArgVal,
2573 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2574 DAG.getValueType(ObjectVT));
2575 else if (Flags.isZExt())
2576 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2577 DAG.getValueType(ObjectVT));
2579 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
2583 PPCTargetLowering::LowerFormalArguments_64SVR4(
2585 CallingConv::ID CallConv, bool isVarArg,
2586 const SmallVectorImpl<ISD::InputArg>
2588 SDLoc dl, SelectionDAG &DAG,
2589 SmallVectorImpl<SDValue> &InVals) const {
2590 // TODO: add description of PPC stack frame format, or at least some docs.
2592 bool isELFv2ABI = Subtarget.isELFv2ABI();
2593 bool isLittleEndian = Subtarget.isLittleEndian();
2594 MachineFunction &MF = DAG.getMachineFunction();
2595 MachineFrameInfo *MFI = MF.getFrameInfo();
2596 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2598 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2599 // Potential tail calls could cause overwriting of argument stack slots.
2600 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2601 (CallConv == CallingConv::Fast));
2602 unsigned PtrByteSize = 8;
2604 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
2607 static const MCPhysReg GPR[] = {
2608 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2609 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2612 static const MCPhysReg *FPR = GetFPR();
2614 static const MCPhysReg VR[] = {
2615 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2616 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2618 static const MCPhysReg VSRH[] = {
2619 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
2620 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
2623 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2624 const unsigned Num_FPR_Regs = 13;
2625 const unsigned Num_VR_Regs = array_lengthof(VR);
2627 // Do a first pass over the arguments to determine whether the ABI
2628 // guarantees that our caller has allocated the parameter save area
2629 // on its stack frame. In the ELFv1 ABI, this is always the case;
2630 // in the ELFv2 ABI, it is true if this is a vararg function or if
2631 // any parameter is located in a stack slot.
2633 bool HasParameterArea = !isELFv2ABI || isVarArg;
2634 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
2635 unsigned NumBytes = LinkageSize;
2636 unsigned AvailableFPRs = Num_FPR_Regs;
2637 unsigned AvailableVRs = Num_VR_Regs;
2638 for (unsigned i = 0, e = Ins.size(); i != e; ++i)
2639 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
2640 PtrByteSize, LinkageSize, ParamAreaSize,
2641 NumBytes, AvailableFPRs, AvailableVRs))
2642 HasParameterArea = true;
2644 // Add DAG nodes to load the arguments or copy them out of registers. On
2645 // entry to a function on PPC, the arguments start after the linkage area,
2646 // although the first ones are often in registers.
2648 unsigned ArgOffset = LinkageSize;
2649 unsigned GPR_idx, FPR_idx = 0, VR_idx = 0;
2650 SmallVector<SDValue, 8> MemOps;
2651 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2652 unsigned CurArgIdx = 0;
2653 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2655 bool needsLoad = false;
2656 EVT ObjectVT = Ins[ArgNo].VT;
2657 EVT OrigVT = Ins[ArgNo].ArgVT;
2658 unsigned ObjSize = ObjectVT.getStoreSize();
2659 unsigned ArgSize = ObjSize;
2660 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2661 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2662 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2664 /* Respect alignment of argument on the stack. */
2666 CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
2667 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2668 unsigned CurArgOffset = ArgOffset;
2670 /* Compute GPR index associated with argument offset. */
2671 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2672 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
2674 // FIXME the codegen can be much improved in some cases.
2675 // We do not have to keep everything in memory.
2676 if (Flags.isByVal()) {
2677 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2678 ObjSize = Flags.getByValSize();
2679 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2680 // Empty aggregate parameters do not take up registers. Examples:
2684 // etc. However, we have to provide a place-holder in InVals, so
2685 // pretend we have an 8-byte item at the current address for that
2688 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2689 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2690 InVals.push_back(FIN);
2694 // Create a stack object covering all stack doublewords occupied
2695 // by the argument. If the argument is (fully or partially) on
2696 // the stack, or if the argument is fully in registers but the
2697 // caller has allocated the parameter save anyway, we can refer
2698 // directly to the caller's stack frame. Otherwise, create a
2699 // local copy in our own frame.
2701 if (HasParameterArea ||
2702 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
2703 FI = MFI->CreateFixedObject(ArgSize, ArgOffset, false, true);
2705 FI = MFI->CreateStackObject(ArgSize, Align, false);
2706 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2708 // Handle aggregates smaller than 8 bytes.
2709 if (ObjSize < PtrByteSize) {
2710 // The value of the object is its address, which differs from the
2711 // address of the enclosing doubleword on big-endian systems.
2713 if (!isLittleEndian) {
2714 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, PtrVT);
2715 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
2717 InVals.push_back(Arg);
2719 if (GPR_idx != Num_GPR_Regs) {
2720 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2721 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2724 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2725 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2726 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2727 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
2728 MachinePointerInfo(FuncArg),
2729 ObjType, false, false, 0);
2731 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2732 // store the whole register as-is to the parameter save area
2734 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2735 MachinePointerInfo(FuncArg),
2739 MemOps.push_back(Store);
2741 // Whether we copied from a register or not, advance the offset
2742 // into the parameter save area by a full doubleword.
2743 ArgOffset += PtrByteSize;
2747 // The value of the object is its address, which is the address of
2748 // its first stack doubleword.
2749 InVals.push_back(FIN);
2751 // Store whatever pieces of the object are in registers to memory.
2752 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2753 if (GPR_idx == Num_GPR_Regs)
2756 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2757 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2760 SDValue Off = DAG.getConstant(j, PtrVT);
2761 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
2763 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
2764 MachinePointerInfo(FuncArg, j),
2766 MemOps.push_back(Store);
2769 ArgOffset += ArgSize;
2773 switch (ObjectVT.getSimpleVT().SimpleTy) {
2774 default: llvm_unreachable("Unhandled argument type!");
2778 // These can be scalar arguments or elements of an integer array type
2779 // passed directly. Clang may use those instead of "byval" aggregate
2780 // types to avoid forcing arguments to memory unnecessarily.
2781 if (GPR_idx != Num_GPR_Regs) {
2782 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2783 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2785 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
2786 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2787 // value to MVT::i64 and then truncate to the correct register size.
2788 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2791 ArgSize = PtrByteSize;
2798 // These can be scalar arguments or elements of a float array type
2799 // passed directly. The latter are used to implement ELFv2 homogenous
2800 // float aggregates.
2801 if (FPR_idx != Num_FPR_Regs) {
2804 if (ObjectVT == MVT::f32)
2805 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2807 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX() ?
2808 &PPC::VSFRCRegClass :
2809 &PPC::F8RCRegClass);
2811 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2813 } else if (GPR_idx != Num_GPR_Regs) {
2814 // This can only ever happen in the presence of f32 array types,
2815 // since otherwise we never run out of FPRs before running out
2817 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2818 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2820 if (ObjectVT == MVT::f32) {
2821 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
2822 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
2823 DAG.getConstant(32, MVT::i32));
2824 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2827 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
2832 // When passing an array of floats, the array occupies consecutive
2833 // space in the argument area; only round up to the next doubleword
2834 // at the end of the array. Otherwise, each float takes 8 bytes.
2835 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
2836 ArgOffset += ArgSize;
2837 if (Flags.isInConsecutiveRegsLast())
2838 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2846 // These can be scalar arguments or elements of a vector array type
2847 // passed directly. The latter are used to implement ELFv2 homogenous
2848 // vector aggregates.
2849 if (VR_idx != Num_VR_Regs) {
2850 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
2851 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
2852 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2853 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2862 // We need to load the argument to a virtual register if we determined
2863 // above that we ran out of physical registers of the appropriate type.
2865 if (ObjSize < ArgSize && !isLittleEndian)
2866 CurArgOffset += ArgSize - ObjSize;
2867 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
2868 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2869 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2870 false, false, false, 0);
2873 InVals.push_back(ArgVal);
2876 // Area that is at least reserved in the caller of this function.
2877 unsigned MinReservedArea;
2878 if (HasParameterArea)
2879 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
2881 MinReservedArea = LinkageSize;
2883 // Set the size that is at least reserved in caller of this function. Tail
2884 // call optimized functions' reserved stack space needs to be aligned so that
2885 // taking the difference between two stack areas will result in an aligned
2887 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2888 FuncInfo->setMinReservedArea(MinReservedArea);
2890 // If the function takes variable number of arguments, make a frame index for
2891 // the start of the first vararg value... for expansion of llvm.va_start.
2893 int Depth = ArgOffset;
2895 FuncInfo->setVarArgsFrameIndex(
2896 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2897 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2899 // If this function is vararg, store any remaining integer argument regs
2900 // to their spots on the stack so that they may be loaded by deferencing the
2901 // result of va_next.
2902 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2903 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
2904 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2905 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2906 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2907 MachinePointerInfo(), false, false, 0);
2908 MemOps.push_back(Store);
2909 // Increment the address by four for the next argument to store
2910 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2911 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2915 if (!MemOps.empty())
2916 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2922 PPCTargetLowering::LowerFormalArguments_Darwin(
2924 CallingConv::ID CallConv, bool isVarArg,
2925 const SmallVectorImpl<ISD::InputArg>
2927 SDLoc dl, SelectionDAG &DAG,
2928 SmallVectorImpl<SDValue> &InVals) const {
2929 // TODO: add description of PPC stack frame format, or at least some docs.
2931 MachineFunction &MF = DAG.getMachineFunction();
2932 MachineFrameInfo *MFI = MF.getFrameInfo();
2933 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2935 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2936 bool isPPC64 = PtrVT == MVT::i64;
2937 // Potential tail calls could cause overwriting of argument stack slots.
2938 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2939 (CallConv == CallingConv::Fast));
2940 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2942 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true,
2944 unsigned ArgOffset = LinkageSize;
2945 // Area that is at least reserved in caller of this function.
2946 unsigned MinReservedArea = ArgOffset;
2948 static const MCPhysReg GPR_32[] = { // 32-bit registers.
2949 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2950 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2952 static const MCPhysReg GPR_64[] = { // 64-bit registers.
2953 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2954 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2957 static const MCPhysReg *FPR = GetFPR();
2959 static const MCPhysReg VR[] = {
2960 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2961 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2964 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2965 const unsigned Num_FPR_Regs = 13;
2966 const unsigned Num_VR_Regs = array_lengthof( VR);
2968 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2970 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
2972 // In 32-bit non-varargs functions, the stack space for vectors is after the
2973 // stack space for non-vectors. We do not use this space unless we have
2974 // too many vectors to fit in registers, something that only occurs in
2975 // constructed examples:), but we have to walk the arglist to figure
2976 // that out...for the pathological case, compute VecArgOffset as the
2977 // start of the vector parameter area. Computing VecArgOffset is the
2978 // entire point of the following loop.
2979 unsigned VecArgOffset = ArgOffset;
2980 if (!isVarArg && !isPPC64) {
2981 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
2983 EVT ObjectVT = Ins[ArgNo].VT;
2984 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2986 if (Flags.isByVal()) {
2987 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
2988 unsigned ObjSize = Flags.getByValSize();
2990 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2991 VecArgOffset += ArgSize;
2995 switch(ObjectVT.getSimpleVT().SimpleTy) {
2996 default: llvm_unreachable("Unhandled argument type!");
3002 case MVT::i64: // PPC64
3004 // FIXME: We are guaranteed to be !isPPC64 at this point.
3005 // Does MVT::i64 apply?
3012 // Nothing to do, we're only looking at Nonvector args here.
3017 // We've found where the vector parameter area in memory is. Skip the
3018 // first 12 parameters; these don't use that memory.
3019 VecArgOffset = ((VecArgOffset+15)/16)*16;
3020 VecArgOffset += 12*16;
3022 // Add DAG nodes to load the arguments or copy them out of registers. On
3023 // entry to a function on PPC, the arguments start after the linkage area,
3024 // although the first ones are often in registers.
3026 SmallVector<SDValue, 8> MemOps;
3027 unsigned nAltivecParamsAtEnd = 0;
3028 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3029 unsigned CurArgIdx = 0;
3030 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3032 bool needsLoad = false;
3033 EVT ObjectVT = Ins[ArgNo].VT;
3034 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
3035 unsigned ArgSize = ObjSize;
3036 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3037 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
3038 CurArgIdx = Ins[ArgNo].OrigArgIndex;
3040 unsigned CurArgOffset = ArgOffset;
3042 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
3043 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
3044 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
3045 if (isVarArg || isPPC64) {
3046 MinReservedArea = ((MinReservedArea+15)/16)*16;
3047 MinReservedArea += CalculateStackSlotSize(ObjectVT,
3050 } else nAltivecParamsAtEnd++;
3052 // Calculate min reserved area.
3053 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
3057 // FIXME the codegen can be much improved in some cases.
3058 // We do not have to keep everything in memory.
3059 if (Flags.isByVal()) {
3060 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3061 ObjSize = Flags.getByValSize();
3062 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3063 // Objects of size 1 and 2 are right justified, everything else is
3064 // left justified. This means the memory address is adjusted forwards.
3065 if (ObjSize==1 || ObjSize==2) {
3066 CurArgOffset = CurArgOffset + (4 - ObjSize);
3068 // The value of the object is its address.
3069 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, false, true);
3070 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3071 InVals.push_back(FIN);
3072 if (ObjSize==1 || ObjSize==2) {
3073 if (GPR_idx != Num_GPR_Regs) {
3076 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3078 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3079 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3080 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
3081 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
3082 MachinePointerInfo(FuncArg),
3083 ObjType, false, false, 0);
3084 MemOps.push_back(Store);
3088 ArgOffset += PtrByteSize;
3092 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3093 // Store whatever pieces of the object are in registers
3094 // to memory. ArgOffset will be the address of the beginning
3096 if (GPR_idx != Num_GPR_Regs) {
3099 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3101 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3102 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3103 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3104 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3105 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3106 MachinePointerInfo(FuncArg, j),
3108 MemOps.push_back(Store);
3110 ArgOffset += PtrByteSize;
3112 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
3119 switch (ObjectVT.getSimpleVT().SimpleTy) {
3120 default: llvm_unreachable("Unhandled argument type!");
3124 if (GPR_idx != Num_GPR_Regs) {
3125 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3126 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3128 if (ObjectVT == MVT::i1)
3129 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
3134 ArgSize = PtrByteSize;
3136 // All int arguments reserve stack space in the Darwin ABI.
3137 ArgOffset += PtrByteSize;
3141 case MVT::i64: // PPC64
3142 if (GPR_idx != Num_GPR_Regs) {
3143 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3144 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3146 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3147 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3148 // value to MVT::i64 and then truncate to the correct register size.
3149 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3154 ArgSize = PtrByteSize;
3156 // All int arguments reserve stack space in the Darwin ABI.
3162 // Every 4 bytes of argument space consumes one of the GPRs available for
3163 // argument passing.
3164 if (GPR_idx != Num_GPR_Regs) {
3166 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
3169 if (FPR_idx != Num_FPR_Regs) {
3172 if (ObjectVT == MVT::f32)
3173 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
3175 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
3177 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3183 // All FP arguments reserve stack space in the Darwin ABI.
3184 ArgOffset += isPPC64 ? 8 : ObjSize;
3190 // Note that vector arguments in registers don't reserve stack space,
3191 // except in varargs functions.
3192 if (VR_idx != Num_VR_Regs) {
3193 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3194 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3196 while ((ArgOffset % 16) != 0) {
3197 ArgOffset += PtrByteSize;
3198 if (GPR_idx != Num_GPR_Regs)
3202 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
3206 if (!isVarArg && !isPPC64) {
3207 // Vectors go after all the nonvectors.
3208 CurArgOffset = VecArgOffset;
3211 // Vectors are aligned.
3212 ArgOffset = ((ArgOffset+15)/16)*16;
3213 CurArgOffset = ArgOffset;
3221 // We need to load the argument to a virtual register if we determined above
3222 // that we ran out of physical registers of the appropriate type.
3224 int FI = MFI->CreateFixedObject(ObjSize,
3225 CurArgOffset + (ArgSize - ObjSize),
3227 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3228 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3229 false, false, false, 0);
3232 InVals.push_back(ArgVal);
3235 // Allow for Altivec parameters at the end, if needed.
3236 if (nAltivecParamsAtEnd) {
3237 MinReservedArea = ((MinReservedArea+15)/16)*16;
3238 MinReservedArea += 16*nAltivecParamsAtEnd;
3241 // Area that is at least reserved in the caller of this function.
3242 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
3244 // Set the size that is at least reserved in caller of this function. Tail
3245 // call optimized functions' reserved stack space needs to be aligned so that
3246 // taking the difference between two stack areas will result in an aligned
3248 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
3249 FuncInfo->setMinReservedArea(MinReservedArea);
3251 // If the function takes variable number of arguments, make a frame index for
3252 // the start of the first vararg value... for expansion of llvm.va_start.
3254 int Depth = ArgOffset;
3256 FuncInfo->setVarArgsFrameIndex(
3257 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3259 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3261 // If this function is vararg, store any remaining integer argument regs
3262 // to their spots on the stack so that they may be loaded by deferencing the
3263 // result of va_next.
3264 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3268 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3270 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3272 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3273 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3274 MachinePointerInfo(), false, false, 0);
3275 MemOps.push_back(Store);
3276 // Increment the address by four for the next argument to store
3277 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
3278 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3282 if (!MemOps.empty())
3283 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3288 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3289 /// adjusted to accommodate the arguments for the tailcall.
3290 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3291 unsigned ParamSize) {
3293 if (!isTailCall) return 0;
3295 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3296 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3297 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3298 // Remember only if the new adjustement is bigger.
3299 if (SPDiff < FI->getTailCallSPDelta())
3300 FI->setTailCallSPDelta(SPDiff);
3305 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3306 /// for tail call optimization. Targets which want to do tail call
3307 /// optimization should implement this function.
3309 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3310 CallingConv::ID CalleeCC,
3312 const SmallVectorImpl<ISD::InputArg> &Ins,
3313 SelectionDAG& DAG) const {
3314 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3317 // Variable argument functions are not supported.
3321 MachineFunction &MF = DAG.getMachineFunction();
3322 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3323 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3324 // Functions containing by val parameters are not supported.
3325 for (unsigned i = 0; i != Ins.size(); i++) {
3326 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3327 if (Flags.isByVal()) return false;
3330 // Non-PIC/GOT tail calls are supported.
3331 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3334 // At the moment we can only do local tail calls (in same module, hidden
3335 // or protected) if we are generating PIC.
3336 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3337 return G->getGlobal()->hasHiddenVisibility()
3338 || G->getGlobal()->hasProtectedVisibility();
3344 /// isCallCompatibleAddress - Return the immediate to use if the specified
3345 /// 32-bit value is representable in the immediate field of a BxA instruction.
3346 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3347 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3348 if (!C) return nullptr;
3350 int Addr = C->getZExtValue();
3351 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3352 SignExtend32<26>(Addr) != Addr)
3353 return nullptr; // Top 6 bits have to be sext of immediate.
3355 return DAG.getConstant((int)C->getZExtValue() >> 2,
3356 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
3361 struct TailCallArgumentInfo {
3366 TailCallArgumentInfo() : FrameIdx(0) {}
3371 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3373 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3375 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3376 SmallVectorImpl<SDValue> &MemOpChains,
3378 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3379 SDValue Arg = TailCallArgs[i].Arg;
3380 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3381 int FI = TailCallArgs[i].FrameIdx;
3382 // Store relative to framepointer.
3383 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
3384 MachinePointerInfo::getFixedStack(FI),
3389 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3390 /// the appropriate stack slot for the tail call optimized function call.
3391 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3392 MachineFunction &MF,
3401 // Calculate the new stack slot for the return address.
3402 int SlotSize = isPPC64 ? 8 : 4;
3403 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
3405 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3406 NewRetAddrLoc, true);
3407 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3408 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3409 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3410 MachinePointerInfo::getFixedStack(NewRetAddr),
3413 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3414 // slot as the FP is never overwritten.
3417 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
3418 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3420 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3421 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3422 MachinePointerInfo::getFixedStack(NewFPIdx),
3429 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3430 /// the position of the argument.
3432 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3433 SDValue Arg, int SPDiff, unsigned ArgOffset,
3434 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3435 int Offset = ArgOffset + SPDiff;
3436 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3437 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3438 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3439 SDValue FIN = DAG.getFrameIndex(FI, VT);
3440 TailCallArgumentInfo Info;
3442 Info.FrameIdxOp = FIN;
3444 TailCallArguments.push_back(Info);
3447 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3448 /// stack slot. Returns the chain as result and the loaded frame pointers in
3449 /// LROpOut/FPOpout. Used when tail calling.
3450 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3458 // Load the LR and FP stack slot for later adjusting.
3459 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
3460 LROpOut = getReturnAddrFrameIndex(DAG);
3461 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3462 false, false, false, 0);
3463 Chain = SDValue(LROpOut.getNode(), 1);
3465 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3466 // slot as the FP is never overwritten.
3468 FPOpOut = getFramePointerFrameIndex(DAG);
3469 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3470 false, false, false, 0);
3471 Chain = SDValue(FPOpOut.getNode(), 1);
3477 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3478 /// by "Src" to address "Dst" of size "Size". Alignment information is
3479 /// specified by the specific parameter attribute. The copy will be passed as
3480 /// a byval function parameter.
3481 /// Sometimes what we are copying is the end of a larger object, the part that
3482 /// does not fit in registers.
3484 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3485 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3487 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3488 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3489 false, false, MachinePointerInfo(),
3490 MachinePointerInfo());
3493 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3496 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3497 SDValue Arg, SDValue PtrOff, int SPDiff,
3498 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3499 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
3500 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
3502 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3507 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3509 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3510 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3511 DAG.getConstant(ArgOffset, PtrVT));
3513 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3514 MachinePointerInfo(), false, false, 0));
3515 // Calculate and remember argument location.
3516 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3521 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3522 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3523 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3524 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
3525 MachineFunction &MF = DAG.getMachineFunction();
3527 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3528 // might overwrite each other in case of tail call optimization.
3529 SmallVector<SDValue, 8> MemOpChains2;
3530 // Do not flag preceding copytoreg stuff together with the following stuff.
3532 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3534 if (!MemOpChains2.empty())
3535 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3537 // Store the return address to the appropriate stack slot.
3538 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3539 isPPC64, isDarwinABI, dl);
3541 // Emit callseq_end just before tailcall node.
3542 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3543 DAG.getIntPtrConstant(0, true), InFlag, dl);
3544 InFlag = Chain.getValue(1);
3548 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3549 SDValue &Chain, SDLoc dl, int SPDiff, bool isTailCall,
3550 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
3551 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
3552 const PPCSubtarget &Subtarget) {
3554 bool isPPC64 = Subtarget.isPPC64();
3555 bool isSVR4ABI = Subtarget.isSVR4ABI();
3556 bool isELFv2ABI = Subtarget.isELFv2ABI();
3558 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3559 NodeTys.push_back(MVT::Other); // Returns a chain
3560 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3562 unsigned CallOpc = PPCISD::CALL;
3564 bool needIndirectCall = true;
3565 if (!isSVR4ABI || !isPPC64)
3566 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3567 // If this is an absolute destination address, use the munged value.
3568 Callee = SDValue(Dest, 0);
3569 needIndirectCall = false;
3572 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3573 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201
3574 // Use indirect calls for ALL functions calls in JIT mode, since the
3575 // far-call stubs may be outside relocation limits for a BL instruction.
3576 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
3577 unsigned OpFlags = 0;
3578 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3579 (Subtarget.getTargetTriple().isMacOSX() &&
3580 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3581 (G->getGlobal()->isDeclaration() ||
3582 G->getGlobal()->isWeakForLinker())) ||
3583 (Subtarget.isTargetELF() && !isPPC64 &&
3584 !G->getGlobal()->hasLocalLinkage() &&
3585 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3586 // PC-relative references to external symbols should go through $stub,
3587 // unless we're building with the leopard linker or later, which
3588 // automatically synthesizes these stubs.
3589 OpFlags = PPCII::MO_PLT_OR_STUB;
3592 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3593 // every direct call is) turn it into a TargetGlobalAddress /
3594 // TargetExternalSymbol node so that legalize doesn't hack it.
3595 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3596 Callee.getValueType(),
3598 needIndirectCall = false;
3602 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3603 unsigned char OpFlags = 0;
3605 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3606 (Subtarget.getTargetTriple().isMacOSX() &&
3607 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) ||
3608 (Subtarget.isTargetELF() && !isPPC64 &&
3609 DAG.getTarget().getRelocationModel() == Reloc::PIC_) ) {
3610 // PC-relative references to external symbols should go through $stub,
3611 // unless we're building with the leopard linker or later, which
3612 // automatically synthesizes these stubs.
3613 OpFlags = PPCII::MO_PLT_OR_STUB;
3616 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3618 needIndirectCall = false;
3621 if (needIndirectCall) {
3622 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3623 // to do the call, we can't use PPCISD::CALL.
3624 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3626 if (isSVR4ABI && isPPC64 && !isELFv2ABI) {
3627 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3628 // entry point, but to the function descriptor (the function entry point
3629 // address is part of the function descriptor though).
3630 // The function descriptor is a three doubleword structure with the
3631 // following fields: function entry point, TOC base address and
3632 // environment pointer.
3633 // Thus for a call through a function pointer, the following actions need
3635 // 1. Save the TOC of the caller in the TOC save area of its stack
3636 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3637 // 2. Load the address of the function entry point from the function
3639 // 3. Load the TOC of the callee from the function descriptor into r2.
3640 // 4. Load the environment pointer from the function descriptor into
3642 // 5. Branch to the function entry point address.
3643 // 6. On return of the callee, the TOC of the caller needs to be
3644 // restored (this is done in FinishCall()).
3646 // All those operations are flagged together to ensure that no other
3647 // operations can be scheduled in between. E.g. without flagging the
3648 // operations together, a TOC access in the caller could be scheduled
3649 // between the load of the callee TOC and the branch to the callee, which
3650 // results in the TOC access going through the TOC of the callee instead
3651 // of going through the TOC of the caller, which leads to incorrect code.
3653 // Load the address of the function entry point from the function
3655 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3656 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs,
3657 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3658 Chain = LoadFuncPtr.getValue(1);
3659 InFlag = LoadFuncPtr.getValue(2);
3661 // Load environment pointer into r11.
3662 // Offset of the environment pointer within the function descriptor.
3663 SDValue PtrOff = DAG.getIntPtrConstant(16);
3665 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3666 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
3668 Chain = LoadEnvPtr.getValue(1);
3669 InFlag = LoadEnvPtr.getValue(2);
3671 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3673 Chain = EnvVal.getValue(0);
3674 InFlag = EnvVal.getValue(1);
3676 // Load TOC of the callee into r2. We are using a target-specific load
3677 // with r2 hard coded, because the result of a target-independent load
3678 // would never go directly into r2, since r2 is a reserved register (which
3679 // prevents the register allocator from allocating it), resulting in an
3680 // additional register being allocated and an unnecessary move instruction
3682 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3683 SDValue TOCOff = DAG.getIntPtrConstant(8);
3684 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
3685 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
3687 Chain = LoadTOCPtr.getValue(0);
3688 InFlag = LoadTOCPtr.getValue(1);
3690 MTCTROps[0] = Chain;
3691 MTCTROps[1] = LoadFuncPtr;
3692 MTCTROps[2] = InFlag;
3695 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
3696 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3697 InFlag = Chain.getValue(1);
3700 NodeTys.push_back(MVT::Other);
3701 NodeTys.push_back(MVT::Glue);
3702 Ops.push_back(Chain);
3703 CallOpc = PPCISD::BCTRL;
3704 Callee.setNode(nullptr);
3705 // Add use of X11 (holding environment pointer)
3706 if (isSVR4ABI && isPPC64 && !isELFv2ABI)
3707 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3708 // Add CTR register as callee so a bctr can be emitted later.
3710 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3713 // If this is a direct call, pass the chain and the callee.
3714 if (Callee.getNode()) {
3715 Ops.push_back(Chain);
3716 Ops.push_back(Callee);
3718 // If this is a tail call add stack pointer delta.
3720 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3722 // Add argument registers to the end of the list so that they are known live
3724 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3725 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3726 RegsToPass[i].second.getValueType()));
3728 // Direct calls in the ELFv2 ABI need the TOC register live into the call.
3729 if (Callee.getNode() && isELFv2ABI)
3730 Ops.push_back(DAG.getRegister(PPC::X2, PtrVT));
3736 bool isLocalCall(const SDValue &Callee)
3738 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3739 return !G->getGlobal()->isDeclaration() &&
3740 !G->getGlobal()->isWeakForLinker();
3745 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3746 CallingConv::ID CallConv, bool isVarArg,
3747 const SmallVectorImpl<ISD::InputArg> &Ins,
3748 SDLoc dl, SelectionDAG &DAG,
3749 SmallVectorImpl<SDValue> &InVals) const {
3751 SmallVector<CCValAssign, 16> RVLocs;
3752 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
3754 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3756 // Copy all of the result registers out of their specified physreg.
3757 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3758 CCValAssign &VA = RVLocs[i];
3759 assert(VA.isRegLoc() && "Can only return in registers!");
3761 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3762 VA.getLocReg(), VA.getLocVT(), InFlag);
3763 Chain = Val.getValue(1);
3764 InFlag = Val.getValue(2);
3766 switch (VA.getLocInfo()) {
3767 default: llvm_unreachable("Unknown loc info!");
3768 case CCValAssign::Full: break;
3769 case CCValAssign::AExt:
3770 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3772 case CCValAssign::ZExt:
3773 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3774 DAG.getValueType(VA.getValVT()));
3775 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3777 case CCValAssign::SExt:
3778 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3779 DAG.getValueType(VA.getValVT()));
3780 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3784 InVals.push_back(Val);
3791 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
3792 bool isTailCall, bool isVarArg,
3794 SmallVector<std::pair<unsigned, SDValue>, 8>
3796 SDValue InFlag, SDValue Chain,
3798 int SPDiff, unsigned NumBytes,
3799 const SmallVectorImpl<ISD::InputArg> &Ins,
3800 SmallVectorImpl<SDValue> &InVals) const {
3802 bool isELFv2ABI = Subtarget.isELFv2ABI();
3803 std::vector<EVT> NodeTys;
3804 SmallVector<SDValue, 8> Ops;
3805 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
3806 isTailCall, RegsToPass, Ops, NodeTys,
3809 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3810 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
3811 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3813 // When performing tail call optimization the callee pops its arguments off
3814 // the stack. Account for this here so these bytes can be pushed back on in
3815 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3816 int BytesCalleePops =
3817 (CallConv == CallingConv::Fast &&
3818 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3820 // Add a register mask operand representing the call-preserved registers.
3821 const TargetRegisterInfo *TRI =
3822 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
3823 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3824 assert(Mask && "Missing call preserved mask for calling convention");
3825 Ops.push_back(DAG.getRegisterMask(Mask));
3827 if (InFlag.getNode())
3828 Ops.push_back(InFlag);
3832 assert(((Callee.getOpcode() == ISD::Register &&
3833 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3834 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3835 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3836 isa<ConstantSDNode>(Callee)) &&
3837 "Expecting an global address, external symbol, absolute value or register");
3839 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
3842 // Add a NOP immediately after the branch instruction when using the 64-bit
3843 // SVR4 ABI. At link time, if caller and callee are in a different module and
3844 // thus have a different TOC, the call will be replaced with a call to a stub
3845 // function which saves the current TOC, loads the TOC of the callee and
3846 // branches to the callee. The NOP will be replaced with a load instruction
3847 // which restores the TOC of the caller from the TOC save slot of the current
3848 // stack frame. If caller and callee belong to the same module (and have the
3849 // same TOC), the NOP will remain unchanged.
3851 bool needsTOCRestore = false;
3852 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64()) {
3853 if (CallOpc == PPCISD::BCTRL) {
3854 // This is a call through a function pointer.
3855 // Restore the caller TOC from the save area into R2.
3856 // See PrepareCall() for more information about calls through function
3857 // pointers in the 64-bit SVR4 ABI.
3858 // We are using a target-specific load with r2 hard coded, because the
3859 // result of a target-independent load would never go directly into r2,
3860 // since r2 is a reserved register (which prevents the register allocator
3861 // from allocating it), resulting in an additional register being
3862 // allocated and an unnecessary move instruction being generated.
3863 needsTOCRestore = true;
3864 } else if ((CallOpc == PPCISD::CALL) &&
3865 (!isLocalCall(Callee) ||
3866 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3867 // Otherwise insert NOP for non-local calls.
3868 CallOpc = PPCISD::CALL_NOP;
3872 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
3873 InFlag = Chain.getValue(1);
3875 if (needsTOCRestore) {
3876 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3877 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3878 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
3879 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset(isELFv2ABI);
3880 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset);
3881 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
3882 Chain = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain, AddTOC, InFlag);
3883 InFlag = Chain.getValue(1);
3886 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3887 DAG.getIntPtrConstant(BytesCalleePops, true),
3890 InFlag = Chain.getValue(1);
3892 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3893 Ins, dl, DAG, InVals);
3897 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3898 SmallVectorImpl<SDValue> &InVals) const {
3899 SelectionDAG &DAG = CLI.DAG;
3901 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3902 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3903 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3904 SDValue Chain = CLI.Chain;
3905 SDValue Callee = CLI.Callee;
3906 bool &isTailCall = CLI.IsTailCall;
3907 CallingConv::ID CallConv = CLI.CallConv;
3908 bool isVarArg = CLI.IsVarArg;
3911 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3914 if (!isTailCall && CLI.CS && CLI.CS->isMustTailCall())
3915 report_fatal_error("failed to perform tail call elimination on a call "
3916 "site marked musttail");
3918 if (Subtarget.isSVR4ABI()) {
3919 if (Subtarget.isPPC64())
3920 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3921 isTailCall, Outs, OutVals, Ins,
3924 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3925 isTailCall, Outs, OutVals, Ins,
3929 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
3930 isTailCall, Outs, OutVals, Ins,
3935 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
3936 CallingConv::ID CallConv, bool isVarArg,
3938 const SmallVectorImpl<ISD::OutputArg> &Outs,
3939 const SmallVectorImpl<SDValue> &OutVals,
3940 const SmallVectorImpl<ISD::InputArg> &Ins,
3941 SDLoc dl, SelectionDAG &DAG,
3942 SmallVectorImpl<SDValue> &InVals) const {
3943 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
3944 // of the 32-bit SVR4 ABI stack frame layout.
3946 assert((CallConv == CallingConv::C ||
3947 CallConv == CallingConv::Fast) && "Unknown calling convention!");
3949 unsigned PtrByteSize = 4;
3951 MachineFunction &MF = DAG.getMachineFunction();
3953 // Mark this function as potentially containing a function that contains a
3954 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3955 // and restoring the callers stack pointer in this functions epilog. This is
3956 // done because by tail calling the called function might overwrite the value
3957 // in this function's (MF) stack pointer stack slot 0(SP).
3958 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3959 CallConv == CallingConv::Fast)
3960 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3962 // Count how many bytes are to be pushed on the stack, including the linkage
3963 // area, parameter list area and the part of the local variable space which
3964 // contains copies of aggregates which are passed by value.
3966 // Assign locations to all of the outgoing arguments.
3967 SmallVector<CCValAssign, 16> ArgLocs;
3968 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
3971 // Reserve space for the linkage area on the stack.
3972 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false, false),
3976 // Handle fixed and variable vector arguments differently.
3977 // Fixed vector arguments go into registers as long as registers are
3978 // available. Variable vector arguments always go into memory.
3979 unsigned NumArgs = Outs.size();
3981 for (unsigned i = 0; i != NumArgs; ++i) {
3982 MVT ArgVT = Outs[i].VT;
3983 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3986 if (Outs[i].IsFixed) {
3987 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
3990 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
3996 errs() << "Call operand #" << i << " has unhandled type "
3997 << EVT(ArgVT).getEVTString() << "\n";
3999 llvm_unreachable(nullptr);
4003 // All arguments are treated the same.
4004 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
4007 // Assign locations to all of the outgoing aggregate by value arguments.
4008 SmallVector<CCValAssign, 16> ByValArgLocs;
4009 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4010 ByValArgLocs, *DAG.getContext());
4012 // Reserve stack space for the allocations in CCInfo.
4013 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
4015 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
4017 // Size of the linkage area, parameter list area and the part of the local
4018 // space variable where copies of aggregates which are passed by value are
4020 unsigned NumBytes = CCByValInfo.getNextStackOffset();
4022 // Calculate by how many bytes the stack has to be adjusted in case of tail
4023 // call optimization.
4024 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4026 // Adjust the stack pointer for the new arguments...
4027 // These operations are automatically eliminated by the prolog/epilog pass
4028 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4030 SDValue CallSeqStart = Chain;
4032 // Load the return address and frame pointer so it can be moved somewhere else
4035 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
4038 // Set up a copy of the stack pointer for use loading and storing any
4039 // arguments that may not fit in the registers available for argument
4041 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4043 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4044 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4045 SmallVector<SDValue, 8> MemOpChains;
4047 bool seenFloatArg = false;
4048 // Walk the register/memloc assignments, inserting copies/loads.
4049 for (unsigned i = 0, j = 0, e = ArgLocs.size();
4052 CCValAssign &VA = ArgLocs[i];
4053 SDValue Arg = OutVals[i];
4054 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4056 if (Flags.isByVal()) {
4057 // Argument is an aggregate which is passed by value, thus we need to
4058 // create a copy of it in the local variable space of the current stack
4059 // frame (which is the stack frame of the caller) and pass the address of
4060 // this copy to the callee.
4061 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
4062 CCValAssign &ByValVA = ByValArgLocs[j++];
4063 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
4065 // Memory reserved in the local variable space of the callers stack frame.
4066 unsigned LocMemOffset = ByValVA.getLocMemOffset();
4068 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4069 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4071 // Create a copy of the argument in the local area of the current
4073 SDValue MemcpyCall =
4074 CreateCopyOfByValArgument(Arg, PtrOff,
4075 CallSeqStart.getNode()->getOperand(0),
4078 // This must go outside the CALLSEQ_START..END.
4079 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4080 CallSeqStart.getNode()->getOperand(1),
4082 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4083 NewCallSeqStart.getNode());
4084 Chain = CallSeqStart = NewCallSeqStart;
4086 // Pass the address of the aggregate copy on the stack either in a
4087 // physical register or in the parameter list area of the current stack
4088 // frame to the callee.
4092 if (VA.isRegLoc()) {
4093 if (Arg.getValueType() == MVT::i1)
4094 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
4096 seenFloatArg |= VA.getLocVT().isFloatingPoint();
4097 // Put argument in a physical register.
4098 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
4100 // Put argument in the parameter list area of the current stack frame.
4101 assert(VA.isMemLoc());
4102 unsigned LocMemOffset = VA.getLocMemOffset();
4105 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4106 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4108 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4109 MachinePointerInfo(),
4112 // Calculate and remember argument location.
4113 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
4119 if (!MemOpChains.empty())
4120 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4122 // Build a sequence of copy-to-reg nodes chained together with token chain
4123 // and flag operands which copy the outgoing args into the appropriate regs.
4125 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4126 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4127 RegsToPass[i].second, InFlag);
4128 InFlag = Chain.getValue(1);
4131 // Set CR bit 6 to true if this is a vararg call with floating args passed in
4134 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
4135 SDValue Ops[] = { Chain, InFlag };
4137 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
4138 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
4140 InFlag = Chain.getValue(1);
4144 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
4145 false, TailCallArguments);
4147 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4148 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4152 // Copy an argument into memory, being careful to do this outside the
4153 // call sequence for the call to which the argument belongs.
4155 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
4156 SDValue CallSeqStart,
4157 ISD::ArgFlagsTy Flags,
4160 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
4161 CallSeqStart.getNode()->getOperand(0),
4163 // The MEMCPY must go outside the CALLSEQ_START..END.
4164 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4165 CallSeqStart.getNode()->getOperand(1),
4167 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4168 NewCallSeqStart.getNode());
4169 return NewCallSeqStart;
4173 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
4174 CallingConv::ID CallConv, bool isVarArg,
4176 const SmallVectorImpl<ISD::OutputArg> &Outs,
4177 const SmallVectorImpl<SDValue> &OutVals,
4178 const SmallVectorImpl<ISD::InputArg> &Ins,
4179 SDLoc dl, SelectionDAG &DAG,
4180 SmallVectorImpl<SDValue> &InVals) const {
4182 bool isELFv2ABI = Subtarget.isELFv2ABI();
4183 bool isLittleEndian = Subtarget.isLittleEndian();
4184 unsigned NumOps = Outs.size();
4186 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4187 unsigned PtrByteSize = 8;
4189 MachineFunction &MF = DAG.getMachineFunction();
4191 // Mark this function as potentially containing a function that contains a
4192 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4193 // and restoring the callers stack pointer in this functions epilog. This is
4194 // done because by tail calling the called function might overwrite the value
4195 // in this function's (MF) stack pointer stack slot 0(SP).
4196 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4197 CallConv == CallingConv::Fast)
4198 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4200 // Count how many bytes are to be pushed on the stack, including the linkage
4201 // area, and parameter passing area. On ELFv1, the linkage area is 48 bytes
4202 // reserved space for [SP][CR][LR][2 x unused][TOC]; on ELFv2, the linkage
4203 // area is 32 bytes reserved space for [SP][CR][LR][TOC].
4204 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
4206 unsigned NumBytes = LinkageSize;
4208 // Add up all the space actually used.
4209 for (unsigned i = 0; i != NumOps; ++i) {
4210 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4211 EVT ArgVT = Outs[i].VT;
4212 EVT OrigVT = Outs[i].ArgVT;
4214 /* Respect alignment of argument on the stack. */
4216 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4217 NumBytes = ((NumBytes + Align - 1) / Align) * Align;
4219 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4220 if (Flags.isInConsecutiveRegsLast())
4221 NumBytes = ((NumBytes + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4224 unsigned NumBytesActuallyUsed = NumBytes;
4226 // The prolog code of the callee may store up to 8 GPR argument registers to
4227 // the stack, allowing va_start to index over them in memory if its varargs.
4228 // Because we cannot tell if this is needed on the caller side, we have to
4229 // conservatively assume that it is needed. As such, make sure we have at
4230 // least enough stack space for the caller to store the 8 GPRs.
4231 // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
4232 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4234 // Tail call needs the stack to be aligned.
4235 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4236 CallConv == CallingConv::Fast)
4237 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
4239 // Calculate by how many bytes the stack has to be adjusted in case of tail
4240 // call optimization.
4241 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4243 // To protect arguments on the stack from being clobbered in a tail call,
4244 // force all the loads to happen before doing any other lowering.
4246 Chain = DAG.getStackArgumentTokenFactor(Chain);
4248 // Adjust the stack pointer for the new arguments...
4249 // These operations are automatically eliminated by the prolog/epilog pass
4250 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4252 SDValue CallSeqStart = Chain;
4254 // Load the return address and frame pointer so it can be move somewhere else
4257 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4260 // Set up a copy of the stack pointer for use loading and storing any
4261 // arguments that may not fit in the registers available for argument
4263 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4265 // Figure out which arguments are going to go in registers, and which in
4266 // memory. Also, if this is a vararg function, floating point operations
4267 // must be stored to our stack, and loaded into integer regs as well, if
4268 // any integer regs are available for argument passing.
4269 unsigned ArgOffset = LinkageSize;
4270 unsigned GPR_idx, FPR_idx = 0, VR_idx = 0;
4272 static const MCPhysReg GPR[] = {
4273 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4274 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4276 static const MCPhysReg *FPR = GetFPR();
4278 static const MCPhysReg VR[] = {
4279 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4280 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4282 static const MCPhysReg VSRH[] = {
4283 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4284 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4287 const unsigned NumGPRs = array_lengthof(GPR);
4288 const unsigned NumFPRs = 13;
4289 const unsigned NumVRs = array_lengthof(VR);
4291 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4292 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4294 SmallVector<SDValue, 8> MemOpChains;
4295 for (unsigned i = 0; i != NumOps; ++i) {
4296 SDValue Arg = OutVals[i];
4297 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4298 EVT ArgVT = Outs[i].VT;
4299 EVT OrigVT = Outs[i].ArgVT;
4301 /* Respect alignment of argument on the stack. */
4303 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4304 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
4306 /* Compute GPR index associated with argument offset. */
4307 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4308 GPR_idx = std::min(GPR_idx, NumGPRs);
4310 // PtrOff will be used to store the current argument to the stack if a
4311 // register cannot be found for it.
4314 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4316 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4318 // Promote integers to 64-bit values.
4319 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4320 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4321 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4322 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4325 // FIXME memcpy is used way more than necessary. Correctness first.
4326 // Note: "by value" is code for passing a structure by value, not
4328 if (Flags.isByVal()) {
4329 // Note: Size includes alignment padding, so
4330 // struct x { short a; char b; }
4331 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4332 // These are the proper values we need for right-justifying the
4333 // aggregate in a parameter register.
4334 unsigned Size = Flags.getByValSize();
4336 // An empty aggregate parameter takes up no storage and no
4341 // All aggregates smaller than 8 bytes must be passed right-justified.
4342 if (Size==1 || Size==2 || Size==4) {
4343 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4344 if (GPR_idx != NumGPRs) {
4345 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4346 MachinePointerInfo(), VT,
4347 false, false, false, 0);
4348 MemOpChains.push_back(Load.getValue(1));
4349 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Load));
4351 ArgOffset += PtrByteSize;
4356 if (GPR_idx == NumGPRs && Size < 8) {
4357 SDValue AddPtr = PtrOff;
4358 if (!isLittleEndian) {
4359 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4360 PtrOff.getValueType());
4361 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4363 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4366 ArgOffset += PtrByteSize;
4369 // Copy entire object into memory. There are cases where gcc-generated
4370 // code assumes it is there, even if it could be put entirely into
4371 // registers. (This is not what the doc says.)
4373 // FIXME: The above statement is likely due to a misunderstanding of the
4374 // documents. All arguments must be copied into the parameter area BY
4375 // THE CALLEE in the event that the callee takes the address of any
4376 // formal argument. That has not yet been implemented. However, it is
4377 // reasonable to use the stack area as a staging area for the register
4380 // Skip this for small aggregates, as we will use the same slot for a
4381 // right-justified copy, below.
4383 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4387 // When a register is available, pass a small aggregate right-justified.
4388 if (Size < 8 && GPR_idx != NumGPRs) {
4389 // The easiest way to get this right-justified in a register
4390 // is to copy the structure into the rightmost portion of a
4391 // local variable slot, then load the whole slot into the
4393 // FIXME: The memcpy seems to produce pretty awful code for
4394 // small aggregates, particularly for packed ones.
4395 // FIXME: It would be preferable to use the slot in the
4396 // parameter save area instead of a new local variable.
4397 SDValue AddPtr = PtrOff;
4398 if (!isLittleEndian) {
4399 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
4400 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4402 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4406 // Load the slot into the register.
4407 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
4408 MachinePointerInfo(),
4409 false, false, false, 0);
4410 MemOpChains.push_back(Load.getValue(1));
4411 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Load));
4413 // Done with this argument.
4414 ArgOffset += PtrByteSize;
4418 // For aggregates larger than PtrByteSize, copy the pieces of the
4419 // object that fit into registers from the parameter save area.
4420 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4421 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4422 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4423 if (GPR_idx != NumGPRs) {
4424 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4425 MachinePointerInfo(),
4426 false, false, false, 0);
4427 MemOpChains.push_back(Load.getValue(1));
4428 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4429 ArgOffset += PtrByteSize;
4431 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4438 switch (Arg.getSimpleValueType().SimpleTy) {
4439 default: llvm_unreachable("Unexpected ValueType for argument!");
4443 // These can be scalar arguments or elements of an integer array type
4444 // passed directly. Clang may use those instead of "byval" aggregate
4445 // types to avoid forcing arguments to memory unnecessarily.
4446 if (GPR_idx != NumGPRs) {
4447 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Arg));
4449 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4450 true, isTailCall, false, MemOpChains,
4451 TailCallArguments, dl);
4453 ArgOffset += PtrByteSize;
4457 // These can be scalar arguments or elements of a float array type
4458 // passed directly. The latter are used to implement ELFv2 homogenous
4459 // float aggregates.
4461 // Named arguments go into FPRs first, and once they overflow, the
4462 // remaining arguments go into GPRs and then the parameter save area.
4463 // Unnamed arguments for vararg functions always go to GPRs and
4464 // then the parameter save area. For now, put all arguments to vararg
4465 // routines always in both locations (FPR *and* GPR or stack slot).
4466 bool NeedGPROrStack = isVarArg || FPR_idx == NumFPRs;
4468 // First load the argument into the next available FPR.
4469 if (FPR_idx != NumFPRs)
4470 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4472 // Next, load the argument into GPR or stack slot if needed.
4473 if (!NeedGPROrStack)
4475 else if (GPR_idx != NumGPRs) {
4476 // In the non-vararg case, this can only ever happen in the
4477 // presence of f32 array types, since otherwise we never run
4478 // out of FPRs before running out of GPRs.
4481 // Double values are always passed in a single GPR.
4482 if (Arg.getValueType() != MVT::f32) {
4483 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
4485 // Non-array float values are extended and passed in a GPR.
4486 } else if (!Flags.isInConsecutiveRegs()) {
4487 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4488 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4490 // If we have an array of floats, we collect every odd element
4491 // together with its predecessor into one GPR.
4492 } else if (ArgOffset % PtrByteSize != 0) {
4494 Lo = DAG.getNode(ISD::BITCAST, dl, MVT::i32, OutVals[i - 1]);
4495 Hi = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4496 if (!isLittleEndian)
4498 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
4500 // The final element, if even, goes into the first half of a GPR.
4501 } else if (Flags.isInConsecutiveRegsLast()) {
4502 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4503 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4504 if (!isLittleEndian)
4505 ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal,
4506 DAG.getConstant(32, MVT::i32));
4508 // Non-final even elements are skipped; they will be handled
4509 // together the with subsequent argument on the next go-around.
4513 if (ArgVal.getNode())
4514 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], ArgVal));
4516 // Single-precision floating-point values are mapped to the
4517 // second (rightmost) word of the stack doubleword.
4518 if (Arg.getValueType() == MVT::f32 &&
4519 !isLittleEndian && !Flags.isInConsecutiveRegs()) {
4520 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4521 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4524 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4525 true, isTailCall, false, MemOpChains,
4526 TailCallArguments, dl);
4528 // When passing an array of floats, the array occupies consecutive
4529 // space in the argument area; only round up to the next doubleword
4530 // at the end of the array. Otherwise, each float takes 8 bytes.
4531 ArgOffset += (Arg.getValueType() == MVT::f32 &&
4532 Flags.isInConsecutiveRegs()) ? 4 : 8;
4533 if (Flags.isInConsecutiveRegsLast())
4534 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4543 // These can be scalar arguments or elements of a vector array type
4544 // passed directly. The latter are used to implement ELFv2 homogenous
4545 // vector aggregates.
4547 // For a varargs call, named arguments go into VRs or on the stack as
4548 // usual; unnamed arguments always go to the stack or the corresponding
4549 // GPRs when within range. For now, we always put the value in both
4550 // locations (or even all three).
4552 // We could elide this store in the case where the object fits
4553 // entirely in R registers. Maybe later.
4554 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4555 MachinePointerInfo(), false, false, 0);
4556 MemOpChains.push_back(Store);
4557 if (VR_idx != NumVRs) {
4558 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4559 MachinePointerInfo(),
4560 false, false, false, 0);
4561 MemOpChains.push_back(Load.getValue(1));
4563 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4564 Arg.getSimpleValueType() == MVT::v2i64) ?
4565 VSRH[VR_idx] : VR[VR_idx];
4568 RegsToPass.push_back(std::make_pair(VReg, Load));
4571 for (unsigned i=0; i<16; i+=PtrByteSize) {
4572 if (GPR_idx == NumGPRs)
4574 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4575 DAG.getConstant(i, PtrVT));
4576 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4577 false, false, false, 0);
4578 MemOpChains.push_back(Load.getValue(1));
4579 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4584 // Non-varargs Altivec params go into VRs or on the stack.
4585 if (VR_idx != NumVRs) {
4586 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4587 Arg.getSimpleValueType() == MVT::v2i64) ?
4588 VSRH[VR_idx] : VR[VR_idx];
4591 RegsToPass.push_back(std::make_pair(VReg, Arg));
4593 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4594 true, isTailCall, true, MemOpChains,
4595 TailCallArguments, dl);
4602 assert(NumBytesActuallyUsed == ArgOffset);
4603 (void)NumBytesActuallyUsed;
4605 if (!MemOpChains.empty())
4606 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4608 // Check if this is an indirect call (MTCTR/BCTRL).
4609 // See PrepareCall() for more information about calls through function
4610 // pointers in the 64-bit SVR4 ABI.
4612 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4613 !dyn_cast<ExternalSymbolSDNode>(Callee)) {
4614 // Load r2 into a virtual register and store it to the TOC save area.
4615 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4616 // TOC save area offset.
4617 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset(isELFv2ABI);
4618 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset);
4619 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4620 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
4622 // In the ELFv2 ABI, R12 must contain the address of an indirect callee.
4623 // This does not mean the MTCTR instruction must use R12; it's easier
4624 // to model this as an extra parameter, so do that.
4626 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
4629 // Build a sequence of copy-to-reg nodes chained together with token chain
4630 // and flag operands which copy the outgoing args into the appropriate regs.
4632 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4633 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4634 RegsToPass[i].second, InFlag);
4635 InFlag = Chain.getValue(1);
4639 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4640 FPOp, true, TailCallArguments);
4642 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4643 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4648 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4649 CallingConv::ID CallConv, bool isVarArg,
4651 const SmallVectorImpl<ISD::OutputArg> &Outs,
4652 const SmallVectorImpl<SDValue> &OutVals,
4653 const SmallVectorImpl<ISD::InputArg> &Ins,
4654 SDLoc dl, SelectionDAG &DAG,
4655 SmallVectorImpl<SDValue> &InVals) const {
4657 unsigned NumOps = Outs.size();
4659 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4660 bool isPPC64 = PtrVT == MVT::i64;
4661 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4663 MachineFunction &MF = DAG.getMachineFunction();
4665 // Mark this function as potentially containing a function that contains a
4666 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4667 // and restoring the callers stack pointer in this functions epilog. This is
4668 // done because by tail calling the called function might overwrite the value
4669 // in this function's (MF) stack pointer stack slot 0(SP).
4670 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4671 CallConv == CallingConv::Fast)
4672 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4674 // Count how many bytes are to be pushed on the stack, including the linkage
4675 // area, and parameter passing area. We start with 24/48 bytes, which is
4676 // prereserved space for [SP][CR][LR][3 x unused].
4677 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true,
4679 unsigned NumBytes = LinkageSize;
4681 // Add up all the space actually used.
4682 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
4683 // they all go in registers, but we must reserve stack space for them for
4684 // possible use by the caller. In varargs or 64-bit calls, parameters are
4685 // assigned stack space in order, with padding so Altivec parameters are
4687 unsigned nAltivecParamsAtEnd = 0;
4688 for (unsigned i = 0; i != NumOps; ++i) {
4689 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4690 EVT ArgVT = Outs[i].VT;
4691 // Varargs Altivec parameters are padded to a 16 byte boundary.
4692 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
4693 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
4694 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) {
4695 if (!isVarArg && !isPPC64) {
4696 // Non-varargs Altivec parameters go after all the non-Altivec
4697 // parameters; handle those later so we know how much padding we need.
4698 nAltivecParamsAtEnd++;
4701 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
4702 NumBytes = ((NumBytes+15)/16)*16;
4704 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4707 // Allow for Altivec parameters at the end, if needed.
4708 if (nAltivecParamsAtEnd) {
4709 NumBytes = ((NumBytes+15)/16)*16;
4710 NumBytes += 16*nAltivecParamsAtEnd;
4713 // The prolog code of the callee may store up to 8 GPR argument registers to
4714 // the stack, allowing va_start to index over them in memory if its varargs.
4715 // Because we cannot tell if this is needed on the caller side, we have to
4716 // conservatively assume that it is needed. As such, make sure we have at
4717 // least enough stack space for the caller to store the 8 GPRs.
4718 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4720 // Tail call needs the stack to be aligned.
4721 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4722 CallConv == CallingConv::Fast)
4723 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
4725 // Calculate by how many bytes the stack has to be adjusted in case of tail
4726 // call optimization.
4727 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4729 // To protect arguments on the stack from being clobbered in a tail call,
4730 // force all the loads to happen before doing any other lowering.
4732 Chain = DAG.getStackArgumentTokenFactor(Chain);
4734 // Adjust the stack pointer for the new arguments...
4735 // These operations are automatically eliminated by the prolog/epilog pass
4736 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4738 SDValue CallSeqStart = Chain;
4740 // Load the return address and frame pointer so it can be move somewhere else
4743 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4746 // Set up a copy of the stack pointer for use loading and storing any
4747 // arguments that may not fit in the registers available for argument
4751 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4753 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4755 // Figure out which arguments are going to go in registers, and which in
4756 // memory. Also, if this is a vararg function, floating point operations
4757 // must be stored to our stack, and loaded into integer regs as well, if
4758 // any integer regs are available for argument passing.
4759 unsigned ArgOffset = LinkageSize;
4760 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4762 static const MCPhysReg GPR_32[] = { // 32-bit registers.
4763 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4764 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4766 static const MCPhysReg GPR_64[] = { // 64-bit registers.
4767 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4768 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4770 static const MCPhysReg *FPR = GetFPR();
4772 static const MCPhysReg VR[] = {
4773 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4774 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4776 const unsigned NumGPRs = array_lengthof(GPR_32);
4777 const unsigned NumFPRs = 13;
4778 const unsigned NumVRs = array_lengthof(VR);
4780 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
4782 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4783 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4785 SmallVector<SDValue, 8> MemOpChains;
4786 for (unsigned i = 0; i != NumOps; ++i) {
4787 SDValue Arg = OutVals[i];
4788 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4790 // PtrOff will be used to store the current argument to the stack if a
4791 // register cannot be found for it.
4794 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4796 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4798 // On PPC64, promote integers to 64-bit values.
4799 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4800 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4801 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4802 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4805 // FIXME memcpy is used way more than necessary. Correctness first.
4806 // Note: "by value" is code for passing a structure by value, not
4808 if (Flags.isByVal()) {
4809 unsigned Size = Flags.getByValSize();
4810 // Very small objects are passed right-justified. Everything else is
4811 // passed left-justified.
4812 if (Size==1 || Size==2) {
4813 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4814 if (GPR_idx != NumGPRs) {
4815 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4816 MachinePointerInfo(), VT,
4817 false, false, false, 0);
4818 MemOpChains.push_back(Load.getValue(1));
4819 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4821 ArgOffset += PtrByteSize;
4823 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4824 PtrOff.getValueType());
4825 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4826 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4829 ArgOffset += PtrByteSize;
4833 // Copy entire object into memory. There are cases where gcc-generated
4834 // code assumes it is there, even if it could be put entirely into
4835 // registers. (This is not what the doc says.)
4836 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4840 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4841 // copy the pieces of the object that fit into registers from the
4842 // parameter save area.
4843 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4844 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4845 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4846 if (GPR_idx != NumGPRs) {
4847 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4848 MachinePointerInfo(),
4849 false, false, false, 0);
4850 MemOpChains.push_back(Load.getValue(1));
4851 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4852 ArgOffset += PtrByteSize;
4854 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4861 switch (Arg.getSimpleValueType().SimpleTy) {
4862 default: llvm_unreachable("Unexpected ValueType for argument!");
4866 if (GPR_idx != NumGPRs) {
4867 if (Arg.getValueType() == MVT::i1)
4868 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
4870 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4872 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4873 isPPC64, isTailCall, false, MemOpChains,
4874 TailCallArguments, dl);
4876 ArgOffset += PtrByteSize;
4880 if (FPR_idx != NumFPRs) {
4881 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4884 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4885 MachinePointerInfo(), false, false, 0);
4886 MemOpChains.push_back(Store);
4888 // Float varargs are always shadowed in available integer registers
4889 if (GPR_idx != NumGPRs) {
4890 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4891 MachinePointerInfo(), false, false,
4893 MemOpChains.push_back(Load.getValue(1));
4894 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4896 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4897 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4898 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4899 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4900 MachinePointerInfo(),
4901 false, false, false, 0);
4902 MemOpChains.push_back(Load.getValue(1));
4903 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4906 // If we have any FPRs remaining, we may also have GPRs remaining.
4907 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4909 if (GPR_idx != NumGPRs)
4911 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4912 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4916 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4917 isPPC64, isTailCall, false, MemOpChains,
4918 TailCallArguments, dl);
4922 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4929 // These go aligned on the stack, or in the corresponding R registers
4930 // when within range. The Darwin PPC ABI doc claims they also go in
4931 // V registers; in fact gcc does this only for arguments that are
4932 // prototyped, not for those that match the ... We do it for all
4933 // arguments, seems to work.
4934 while (ArgOffset % 16 !=0) {
4935 ArgOffset += PtrByteSize;
4936 if (GPR_idx != NumGPRs)
4939 // We could elide this store in the case where the object fits
4940 // entirely in R registers. Maybe later.
4941 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4942 DAG.getConstant(ArgOffset, PtrVT));
4943 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4944 MachinePointerInfo(), false, false, 0);
4945 MemOpChains.push_back(Store);
4946 if (VR_idx != NumVRs) {
4947 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4948 MachinePointerInfo(),
4949 false, false, false, 0);
4950 MemOpChains.push_back(Load.getValue(1));
4951 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4954 for (unsigned i=0; i<16; i+=PtrByteSize) {
4955 if (GPR_idx == NumGPRs)
4957 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4958 DAG.getConstant(i, PtrVT));
4959 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4960 false, false, false, 0);
4961 MemOpChains.push_back(Load.getValue(1));
4962 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4967 // Non-varargs Altivec params generally go in registers, but have
4968 // stack space allocated at the end.
4969 if (VR_idx != NumVRs) {
4970 // Doesn't have GPR space allocated.
4971 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4972 } else if (nAltivecParamsAtEnd==0) {
4973 // We are emitting Altivec params in order.
4974 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4975 isPPC64, isTailCall, true, MemOpChains,
4976 TailCallArguments, dl);
4982 // If all Altivec parameters fit in registers, as they usually do,
4983 // they get stack space following the non-Altivec parameters. We
4984 // don't track this here because nobody below needs it.
4985 // If there are more Altivec parameters than fit in registers emit
4987 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
4989 // Offset is aligned; skip 1st 12 params which go in V registers.
4990 ArgOffset = ((ArgOffset+15)/16)*16;
4992 for (unsigned i = 0; i != NumOps; ++i) {
4993 SDValue Arg = OutVals[i];
4994 EVT ArgType = Outs[i].VT;
4995 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
4996 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
4999 // We are emitting Altivec params in order.
5000 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5001 isPPC64, isTailCall, true, MemOpChains,
5002 TailCallArguments, dl);
5009 if (!MemOpChains.empty())
5010 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5012 // On Darwin, R12 must contain the address of an indirect callee. This does
5013 // not mean the MTCTR instruction must use R12; it's easier to model this as
5014 // an extra parameter, so do that.
5016 !dyn_cast<GlobalAddressSDNode>(Callee) &&
5017 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
5018 !isBLACompatibleAddress(Callee, DAG))
5019 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
5020 PPC::R12), Callee));
5022 // Build a sequence of copy-to-reg nodes chained together with token chain
5023 // and flag operands which copy the outgoing args into the appropriate regs.
5025 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5026 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5027 RegsToPass[i].second, InFlag);
5028 InFlag = Chain.getValue(1);
5032 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
5033 FPOp, true, TailCallArguments);
5035 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
5036 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
5041 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
5042 MachineFunction &MF, bool isVarArg,
5043 const SmallVectorImpl<ISD::OutputArg> &Outs,
5044 LLVMContext &Context) const {
5045 SmallVector<CCValAssign, 16> RVLocs;
5046 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
5047 return CCInfo.CheckReturn(Outs, RetCC_PPC);
5051 PPCTargetLowering::LowerReturn(SDValue Chain,
5052 CallingConv::ID CallConv, bool isVarArg,
5053 const SmallVectorImpl<ISD::OutputArg> &Outs,
5054 const SmallVectorImpl<SDValue> &OutVals,
5055 SDLoc dl, SelectionDAG &DAG) const {
5057 SmallVector<CCValAssign, 16> RVLocs;
5058 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
5060 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
5063 SmallVector<SDValue, 4> RetOps(1, Chain);
5065 // Copy the result values into the output registers.
5066 for (unsigned i = 0; i != RVLocs.size(); ++i) {
5067 CCValAssign &VA = RVLocs[i];
5068 assert(VA.isRegLoc() && "Can only return in registers!");
5070 SDValue Arg = OutVals[i];
5072 switch (VA.getLocInfo()) {
5073 default: llvm_unreachable("Unknown loc info!");
5074 case CCValAssign::Full: break;
5075 case CCValAssign::AExt:
5076 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
5078 case CCValAssign::ZExt:
5079 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
5081 case CCValAssign::SExt:
5082 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
5086 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
5087 Flag = Chain.getValue(1);
5088 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
5091 RetOps[0] = Chain; // Update chain.
5093 // Add the flag if we have it.
5095 RetOps.push_back(Flag);
5097 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
5100 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
5101 const PPCSubtarget &Subtarget) const {
5102 // When we pop the dynamic allocation we need to restore the SP link.
5105 // Get the corect type for pointers.
5106 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5108 // Construct the stack pointer operand.
5109 bool isPPC64 = Subtarget.isPPC64();
5110 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
5111 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
5113 // Get the operands for the STACKRESTORE.
5114 SDValue Chain = Op.getOperand(0);
5115 SDValue SaveSP = Op.getOperand(1);
5117 // Load the old link SP.
5118 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
5119 MachinePointerInfo(),
5120 false, false, false, 0);
5122 // Restore the stack pointer.
5123 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
5125 // Store the old link SP.
5126 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
5133 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
5134 MachineFunction &MF = DAG.getMachineFunction();
5135 bool isPPC64 = Subtarget.isPPC64();
5136 bool isDarwinABI = Subtarget.isDarwinABI();
5137 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5139 // Get current frame pointer save index. The users of this index will be
5140 // primarily DYNALLOC instructions.
5141 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5142 int RASI = FI->getReturnAddrSaveIndex();
5144 // If the frame pointer save index hasn't been defined yet.
5146 // Find out what the fix offset of the frame pointer save area.
5147 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
5148 // Allocate the frame index for frame pointer save area.
5149 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
5151 FI->setReturnAddrSaveIndex(RASI);
5153 return DAG.getFrameIndex(RASI, PtrVT);
5157 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
5158 MachineFunction &MF = DAG.getMachineFunction();
5159 bool isPPC64 = Subtarget.isPPC64();
5160 bool isDarwinABI = Subtarget.isDarwinABI();
5161 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5163 // Get current frame pointer save index. The users of this index will be
5164 // primarily DYNALLOC instructions.
5165 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5166 int FPSI = FI->getFramePointerSaveIndex();
5168 // If the frame pointer save index hasn't been defined yet.
5170 // Find out what the fix offset of the frame pointer save area.
5171 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
5174 // Allocate the frame index for frame pointer save area.
5175 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
5177 FI->setFramePointerSaveIndex(FPSI);
5179 return DAG.getFrameIndex(FPSI, PtrVT);
5182 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5184 const PPCSubtarget &Subtarget) const {
5186 SDValue Chain = Op.getOperand(0);
5187 SDValue Size = Op.getOperand(1);
5190 // Get the corect type for pointers.
5191 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5193 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
5194 DAG.getConstant(0, PtrVT), Size);
5195 // Construct a node for the frame pointer save index.
5196 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
5197 // Build a DYNALLOC node.
5198 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
5199 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
5200 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
5203 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
5204 SelectionDAG &DAG) const {
5206 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
5207 DAG.getVTList(MVT::i32, MVT::Other),
5208 Op.getOperand(0), Op.getOperand(1));
5211 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
5212 SelectionDAG &DAG) const {
5214 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
5215 Op.getOperand(0), Op.getOperand(1));
5218 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
5219 assert(Op.getValueType() == MVT::i1 &&
5220 "Custom lowering only for i1 loads");
5222 // First, load 8 bits into 32 bits, then truncate to 1 bit.
5225 LoadSDNode *LD = cast<LoadSDNode>(Op);
5227 SDValue Chain = LD->getChain();
5228 SDValue BasePtr = LD->getBasePtr();
5229 MachineMemOperand *MMO = LD->getMemOperand();
5231 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(), Chain,
5232 BasePtr, MVT::i8, MMO);
5233 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
5235 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
5236 return DAG.getMergeValues(Ops, dl);
5239 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
5240 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
5241 "Custom lowering only for i1 stores");
5243 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
5246 StoreSDNode *ST = cast<StoreSDNode>(Op);
5248 SDValue Chain = ST->getChain();
5249 SDValue BasePtr = ST->getBasePtr();
5250 SDValue Value = ST->getValue();
5251 MachineMemOperand *MMO = ST->getMemOperand();
5253 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(), Value);
5254 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
5257 // FIXME: Remove this once the ANDI glue bug is fixed:
5258 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
5259 assert(Op.getValueType() == MVT::i1 &&
5260 "Custom lowering only for i1 results");
5263 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
5267 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
5269 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5270 // Not FP? Not a fsel.
5271 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
5272 !Op.getOperand(2).getValueType().isFloatingPoint())
5275 // We might be able to do better than this under some circumstances, but in
5276 // general, fsel-based lowering of select is a finite-math-only optimization.
5277 // For more information, see section F.3 of the 2.06 ISA specification.
5278 if (!DAG.getTarget().Options.NoInfsFPMath ||
5279 !DAG.getTarget().Options.NoNaNsFPMath)
5282 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5284 EVT ResVT = Op.getValueType();
5285 EVT CmpVT = Op.getOperand(0).getValueType();
5286 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5287 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
5290 // If the RHS of the comparison is a 0.0, we don't need to do the
5291 // subtraction at all.
5293 if (isFloatingPointZero(RHS))
5295 default: break; // SETUO etc aren't handled by fsel.
5299 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5300 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5301 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5302 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5303 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5304 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5305 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
5308 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5311 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5312 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5313 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5316 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5319 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5320 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5321 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5322 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
5327 default: break; // SETUO etc aren't handled by fsel.
5331 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5332 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5333 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5334 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5335 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5336 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5337 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5338 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
5341 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5342 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5343 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5344 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5347 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5348 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5349 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5350 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5353 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5354 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5355 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5356 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5359 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5360 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5361 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5362 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5367 // FIXME: Split this code up when LegalizeDAGTypes lands.
5368 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
5370 assert(Op.getOperand(0).getValueType().isFloatingPoint());
5371 SDValue Src = Op.getOperand(0);
5372 if (Src.getValueType() == MVT::f32)
5373 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
5376 switch (Op.getSimpleValueType().SimpleTy) {
5377 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
5379 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
5380 (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ :
5385 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
5386 "i64 FP_TO_UINT is supported only with FPCVT");
5387 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
5393 // Convert the FP value to an int value through memory.
5394 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
5395 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
5396 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
5397 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
5398 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
5400 // Emit a store to the stack slot.
5403 MachineFunction &MF = DAG.getMachineFunction();
5404 MachineMemOperand *MMO =
5405 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
5406 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
5407 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
5408 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
5410 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
5411 MPI, false, false, 0);
5413 // Result is a load from the stack slot. If loading 4 bytes, make sure to
5415 if (Op.getValueType() == MVT::i32 && !i32Stack) {
5416 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
5417 DAG.getConstant(4, FIPtr.getValueType()));
5418 MPI = MachinePointerInfo();
5421 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MPI,
5422 false, false, false, 0);
5425 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
5426 SelectionDAG &DAG) const {
5428 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
5429 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
5432 if (Op.getOperand(0).getValueType() == MVT::i1)
5433 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
5434 DAG.getConstantFP(1.0, Op.getValueType()),
5435 DAG.getConstantFP(0.0, Op.getValueType()));
5437 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
5438 "UINT_TO_FP is supported only with FPCVT");
5440 // If we have FCFIDS, then use it when converting to single-precision.
5441 // Otherwise, convert to double-precision and then round.
5442 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5443 (Op.getOpcode() == ISD::UINT_TO_FP ?
5444 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
5445 (Op.getOpcode() == ISD::UINT_TO_FP ?
5446 PPCISD::FCFIDU : PPCISD::FCFID);
5447 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5448 MVT::f32 : MVT::f64;
5450 if (Op.getOperand(0).getValueType() == MVT::i64) {
5451 SDValue SINT = Op.getOperand(0);
5452 // When converting to single-precision, we actually need to convert
5453 // to double-precision first and then round to single-precision.
5454 // To avoid double-rounding effects during that operation, we have
5455 // to prepare the input operand. Bits that might be truncated when
5456 // converting to double-precision are replaced by a bit that won't
5457 // be lost at this stage, but is below the single-precision rounding
5460 // However, if -enable-unsafe-fp-math is in effect, accept double
5461 // rounding to avoid the extra overhead.
5462 if (Op.getValueType() == MVT::f32 &&
5463 !Subtarget.hasFPCVT() &&
5464 !DAG.getTarget().Options.UnsafeFPMath) {
5466 // Twiddle input to make sure the low 11 bits are zero. (If this
5467 // is the case, we are guaranteed the value will fit into the 53 bit
5468 // mantissa of an IEEE double-precision value without rounding.)
5469 // If any of those low 11 bits were not zero originally, make sure
5470 // bit 12 (value 2048) is set instead, so that the final rounding
5471 // to single-precision gets the correct result.
5472 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5473 SINT, DAG.getConstant(2047, MVT::i64));
5474 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
5475 Round, DAG.getConstant(2047, MVT::i64));
5476 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
5477 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5478 Round, DAG.getConstant(-2048, MVT::i64));
5480 // However, we cannot use that value unconditionally: if the magnitude
5481 // of the input value is small, the bit-twiddling we did above might
5482 // end up visibly changing the output. Fortunately, in that case, we
5483 // don't need to twiddle bits since the original input will convert
5484 // exactly to double-precision floating-point already. Therefore,
5485 // construct a conditional to use the original value if the top 11
5486 // bits are all sign-bit copies, and use the rounded value computed
5488 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
5489 SINT, DAG.getConstant(53, MVT::i32));
5490 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
5491 Cond, DAG.getConstant(1, MVT::i64));
5492 Cond = DAG.getSetCC(dl, MVT::i32,
5493 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
5495 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
5498 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
5499 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
5501 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5502 FP = DAG.getNode(ISD::FP_ROUND, dl,
5503 MVT::f32, FP, DAG.getIntPtrConstant(0));
5507 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
5508 "Unhandled INT_TO_FP type in custom expander!");
5509 // Since we only generate this in 64-bit mode, we can take advantage of
5510 // 64-bit registers. In particular, sign extend the input value into the
5511 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
5512 // then lfd it and fcfid it.
5513 MachineFunction &MF = DAG.getMachineFunction();
5514 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
5515 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5518 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
5519 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
5520 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5522 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
5523 MachinePointerInfo::getFixedStack(FrameIdx),
5526 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
5527 "Expected an i32 store");
5528 MachineMemOperand *MMO =
5529 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
5530 MachineMemOperand::MOLoad, 4, 4);
5531 SDValue Ops[] = { Store, FIdx };
5532 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
5533 PPCISD::LFIWZX : PPCISD::LFIWAX,
5534 dl, DAG.getVTList(MVT::f64, MVT::Other),
5535 Ops, MVT::i32, MMO);
5537 assert(Subtarget.isPPC64() &&
5538 "i32->FP without LFIWAX supported only on PPC64");
5540 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
5541 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5543 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
5546 // STD the extended value into the stack slot.
5547 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
5548 MachinePointerInfo::getFixedStack(FrameIdx),
5551 // Load the value as a double.
5552 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
5553 MachinePointerInfo::getFixedStack(FrameIdx),
5554 false, false, false, 0);
5557 // FCFID it and return it.
5558 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
5559 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5560 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
5564 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
5565 SelectionDAG &DAG) const {
5568 The rounding mode is in bits 30:31 of FPSR, and has the following
5575 FLT_ROUNDS, on the other hand, expects the following:
5582 To perform the conversion, we do:
5583 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
5586 MachineFunction &MF = DAG.getMachineFunction();
5587 EVT VT = Op.getValueType();
5588 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5590 // Save FP Control Word to register
5592 MVT::f64, // return register
5593 MVT::Glue // unused in this context
5595 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
5597 // Save FP register to stack slot
5598 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5599 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
5600 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
5601 StackSlot, MachinePointerInfo(), false, false,0);
5603 // Load FP Control Word from low 32 bits of stack slot.
5604 SDValue Four = DAG.getConstant(4, PtrVT);
5605 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
5606 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
5607 false, false, false, 0);
5609 // Transform as necessary
5611 DAG.getNode(ISD::AND, dl, MVT::i32,
5612 CWD, DAG.getConstant(3, MVT::i32));
5614 DAG.getNode(ISD::SRL, dl, MVT::i32,
5615 DAG.getNode(ISD::AND, dl, MVT::i32,
5616 DAG.getNode(ISD::XOR, dl, MVT::i32,
5617 CWD, DAG.getConstant(3, MVT::i32)),
5618 DAG.getConstant(3, MVT::i32)),
5619 DAG.getConstant(1, MVT::i32));
5622 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
5624 return DAG.getNode((VT.getSizeInBits() < 16 ?
5625 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
5628 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5629 EVT VT = Op.getValueType();
5630 unsigned BitWidth = VT.getSizeInBits();
5632 assert(Op.getNumOperands() == 3 &&
5633 VT == Op.getOperand(1).getValueType() &&
5636 // Expand into a bunch of logical ops. Note that these ops
5637 // depend on the PPC behavior for oversized shift amounts.
5638 SDValue Lo = Op.getOperand(0);
5639 SDValue Hi = Op.getOperand(1);
5640 SDValue Amt = Op.getOperand(2);
5641 EVT AmtVT = Amt.getValueType();
5643 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5644 DAG.getConstant(BitWidth, AmtVT), Amt);
5645 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
5646 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5647 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5648 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5649 DAG.getConstant(-BitWidth, AmtVT));
5650 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5651 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5652 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
5653 SDValue OutOps[] = { OutLo, OutHi };
5654 return DAG.getMergeValues(OutOps, dl);
5657 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5658 EVT VT = Op.getValueType();
5660 unsigned BitWidth = VT.getSizeInBits();
5661 assert(Op.getNumOperands() == 3 &&
5662 VT == Op.getOperand(1).getValueType() &&
5665 // Expand into a bunch of logical ops. Note that these ops
5666 // depend on the PPC behavior for oversized shift amounts.
5667 SDValue Lo = Op.getOperand(0);
5668 SDValue Hi = Op.getOperand(1);
5669 SDValue Amt = Op.getOperand(2);
5670 EVT AmtVT = Amt.getValueType();
5672 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5673 DAG.getConstant(BitWidth, AmtVT), Amt);
5674 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5675 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5676 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5677 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5678 DAG.getConstant(-BitWidth, AmtVT));
5679 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
5680 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5681 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
5682 SDValue OutOps[] = { OutLo, OutHi };
5683 return DAG.getMergeValues(OutOps, dl);
5686 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
5688 EVT VT = Op.getValueType();
5689 unsigned BitWidth = VT.getSizeInBits();
5690 assert(Op.getNumOperands() == 3 &&
5691 VT == Op.getOperand(1).getValueType() &&
5694 // Expand into a bunch of logical ops, followed by a select_cc.
5695 SDValue Lo = Op.getOperand(0);
5696 SDValue Hi = Op.getOperand(1);
5697 SDValue Amt = Op.getOperand(2);
5698 EVT AmtVT = Amt.getValueType();
5700 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5701 DAG.getConstant(BitWidth, AmtVT), Amt);
5702 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5703 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5704 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5705 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5706 DAG.getConstant(-BitWidth, AmtVT));
5707 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
5708 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
5709 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
5710 Tmp4, Tmp6, ISD::SETLE);
5711 SDValue OutOps[] = { OutLo, OutHi };
5712 return DAG.getMergeValues(OutOps, dl);
5715 //===----------------------------------------------------------------------===//
5716 // Vector related lowering.
5719 /// BuildSplatI - Build a canonical splati of Val with an element size of
5720 /// SplatSize. Cast the result to VT.
5721 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
5722 SelectionDAG &DAG, SDLoc dl) {
5723 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
5725 static const EVT VTys[] = { // canonical VT to use for each size.
5726 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
5729 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
5731 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
5735 EVT CanonicalVT = VTys[SplatSize-1];
5737 // Build a canonical splat for this value.
5738 SDValue Elt = DAG.getConstant(Val, MVT::i32);
5739 SmallVector<SDValue, 8> Ops;
5740 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
5741 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
5742 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
5745 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
5746 /// specified intrinsic ID.
5747 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
5748 SelectionDAG &DAG, SDLoc dl,
5749 EVT DestVT = MVT::Other) {
5750 if (DestVT == MVT::Other) DestVT = Op.getValueType();
5751 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5752 DAG.getConstant(IID, MVT::i32), Op);
5755 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
5756 /// specified intrinsic ID.
5757 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
5758 SelectionDAG &DAG, SDLoc dl,
5759 EVT DestVT = MVT::Other) {
5760 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
5761 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5762 DAG.getConstant(IID, MVT::i32), LHS, RHS);
5765 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
5766 /// specified intrinsic ID.
5767 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
5768 SDValue Op2, SelectionDAG &DAG,
5769 SDLoc dl, EVT DestVT = MVT::Other) {
5770 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
5771 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5772 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
5776 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
5777 /// amount. The result has the specified value type.
5778 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
5779 EVT VT, SelectionDAG &DAG, SDLoc dl) {
5780 // Force LHS/RHS to be the right type.
5781 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
5782 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
5785 for (unsigned i = 0; i != 16; ++i)
5787 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
5788 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5791 // If this is a case we can't handle, return null and let the default
5792 // expansion code take care of it. If we CAN select this case, and if it
5793 // selects to a single instruction, return Op. Otherwise, if we can codegen
5794 // this case more efficiently than a constant pool load, lower it to the
5795 // sequence of ops that should be used.
5796 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
5797 SelectionDAG &DAG) const {
5799 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5800 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
5802 // Check if this is a splat of a constant value.
5803 APInt APSplatBits, APSplatUndef;
5804 unsigned SplatBitSize;
5806 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
5807 HasAnyUndefs, 0, true) || SplatBitSize > 32)
5810 unsigned SplatBits = APSplatBits.getZExtValue();
5811 unsigned SplatUndef = APSplatUndef.getZExtValue();
5812 unsigned SplatSize = SplatBitSize / 8;
5814 // First, handle single instruction cases.
5817 if (SplatBits == 0) {
5818 // Canonicalize all zero vectors to be v4i32.
5819 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5820 SDValue Z = DAG.getConstant(0, MVT::i32);
5821 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5822 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
5827 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
5828 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
5830 if (SextVal >= -16 && SextVal <= 15)
5831 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
5834 // Two instruction sequences.
5836 // If this value is in the range [-32,30] and is even, use:
5837 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
5838 // If this value is in the range [17,31] and is odd, use:
5839 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
5840 // If this value is in the range [-31,-17] and is odd, use:
5841 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
5842 // Note the last two are three-instruction sequences.
5843 if (SextVal >= -32 && SextVal <= 31) {
5844 // To avoid having these optimizations undone by constant folding,
5845 // we convert to a pseudo that will be expanded later into one of
5847 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
5848 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
5849 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
5850 SDValue EltSize = DAG.getConstant(SplatSize, MVT::i32);
5851 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
5852 if (VT == Op.getValueType())
5855 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
5858 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
5859 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
5861 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
5862 // Make -1 and vspltisw -1:
5863 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
5865 // Make the VSLW intrinsic, computing 0x8000_0000.
5866 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
5869 // xor by OnesV to invert it.
5870 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5871 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5874 // The remaining cases assume either big endian element order or
5875 // a splat-size that equates to the element size of the vector
5876 // to be built. An example that doesn't work for little endian is
5877 // {0, -1, 0, -1, 0, -1, 0, -1} which has a splat size of 32 bits
5878 // and a vector element size of 16 bits. The code below will
5879 // produce the vector in big endian element order, which for little
5880 // endian is {-1, 0, -1, 0, -1, 0, -1, 0}.
5882 // For now, just avoid these optimizations in that case.
5883 // FIXME: Develop correct optimizations for LE with mismatched
5884 // splat and element sizes.
5886 if (Subtarget.isLittleEndian() &&
5887 SplatSize != Op.getValueType().getVectorElementType().getSizeInBits())
5890 // Check to see if this is a wide variety of vsplti*, binop self cases.
5891 static const signed char SplatCsts[] = {
5892 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
5893 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
5896 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
5897 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
5898 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
5899 int i = SplatCsts[idx];
5901 // Figure out what shift amount will be used by altivec if shifted by i in
5903 unsigned TypeShiftAmt = i & (SplatBitSize-1);
5905 // vsplti + shl self.
5906 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
5907 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5908 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5909 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
5910 Intrinsic::ppc_altivec_vslw
5912 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5913 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5916 // vsplti + srl self.
5917 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5918 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5919 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5920 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
5921 Intrinsic::ppc_altivec_vsrw
5923 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5924 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5927 // vsplti + sra self.
5928 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5929 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5930 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5931 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
5932 Intrinsic::ppc_altivec_vsraw
5934 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5935 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5938 // vsplti + rol self.
5939 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
5940 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
5941 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5942 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5943 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
5944 Intrinsic::ppc_altivec_vrlw
5946 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5947 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5950 // t = vsplti c, result = vsldoi t, t, 1
5951 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
5952 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5953 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
5955 // t = vsplti c, result = vsldoi t, t, 2
5956 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
5957 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5958 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
5960 // t = vsplti c, result = vsldoi t, t, 3
5961 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
5962 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5963 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
5970 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5971 /// the specified operations to build the shuffle.
5972 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5973 SDValue RHS, SelectionDAG &DAG,
5975 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5976 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5977 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5980 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5992 if (OpNum == OP_COPY) {
5993 if (LHSID == (1*9+2)*9+3) return LHS;
5994 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5998 SDValue OpLHS, OpRHS;
5999 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
6000 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
6004 default: llvm_unreachable("Unknown i32 permute!");
6006 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
6007 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
6008 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
6009 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
6012 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
6013 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
6014 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
6015 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
6018 for (unsigned i = 0; i != 16; ++i)
6019 ShufIdxs[i] = (i&3)+0;
6022 for (unsigned i = 0; i != 16; ++i)
6023 ShufIdxs[i] = (i&3)+4;
6026 for (unsigned i = 0; i != 16; ++i)
6027 ShufIdxs[i] = (i&3)+8;
6030 for (unsigned i = 0; i != 16; ++i)
6031 ShufIdxs[i] = (i&3)+12;
6034 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
6036 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
6038 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
6040 EVT VT = OpLHS.getValueType();
6041 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
6042 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
6043 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
6044 return DAG.getNode(ISD::BITCAST, dl, VT, T);
6047 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
6048 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
6049 /// return the code it can be lowered into. Worst case, it can always be
6050 /// lowered into a vperm.
6051 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
6052 SelectionDAG &DAG) const {
6054 SDValue V1 = Op.getOperand(0);
6055 SDValue V2 = Op.getOperand(1);
6056 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6057 EVT VT = Op.getValueType();
6058 bool isLittleEndian = Subtarget.isLittleEndian();
6060 // Cases that are handled by instructions that take permute immediates
6061 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
6062 // selected by the instruction selector.
6063 if (V2.getOpcode() == ISD::UNDEF) {
6064 if (PPC::isSplatShuffleMask(SVOp, 1) ||
6065 PPC::isSplatShuffleMask(SVOp, 2) ||
6066 PPC::isSplatShuffleMask(SVOp, 4) ||
6067 PPC::isVPKUWUMShuffleMask(SVOp, 1, DAG) ||
6068 PPC::isVPKUHUMShuffleMask(SVOp, 1, DAG) ||
6069 PPC::isVSLDOIShuffleMask(SVOp, 1, DAG) != -1 ||
6070 PPC::isVMRGLShuffleMask(SVOp, 1, 1, DAG) ||
6071 PPC::isVMRGLShuffleMask(SVOp, 2, 1, DAG) ||
6072 PPC::isVMRGLShuffleMask(SVOp, 4, 1, DAG) ||
6073 PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) ||
6074 PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) ||
6075 PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG)) {
6080 // Altivec has a variety of "shuffle immediates" that take two vector inputs
6081 // and produce a fixed permutation. If any of these match, do not lower to
6083 unsigned int ShuffleKind = isLittleEndian ? 2 : 0;
6084 if (PPC::isVPKUWUMShuffleMask(SVOp, ShuffleKind, DAG) ||
6085 PPC::isVPKUHUMShuffleMask(SVOp, ShuffleKind, DAG) ||
6086 PPC::isVSLDOIShuffleMask(SVOp, ShuffleKind, DAG) != -1 ||
6087 PPC::isVMRGLShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6088 PPC::isVMRGLShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6089 PPC::isVMRGLShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
6090 PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6091 PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6092 PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG))
6095 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
6096 // perfect shuffle table to emit an optimal matching sequence.
6097 ArrayRef<int> PermMask = SVOp->getMask();
6099 unsigned PFIndexes[4];
6100 bool isFourElementShuffle = true;
6101 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
6102 unsigned EltNo = 8; // Start out undef.
6103 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
6104 if (PermMask[i*4+j] < 0)
6105 continue; // Undef, ignore it.
6107 unsigned ByteSource = PermMask[i*4+j];
6108 if ((ByteSource & 3) != j) {
6109 isFourElementShuffle = false;
6114 EltNo = ByteSource/4;
6115 } else if (EltNo != ByteSource/4) {
6116 isFourElementShuffle = false;
6120 PFIndexes[i] = EltNo;
6123 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
6124 // perfect shuffle vector to determine if it is cost effective to do this as
6125 // discrete instructions, or whether we should use a vperm.
6126 // For now, we skip this for little endian until such time as we have a
6127 // little-endian perfect shuffle table.
6128 if (isFourElementShuffle && !isLittleEndian) {
6129 // Compute the index in the perfect shuffle table.
6130 unsigned PFTableIndex =
6131 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
6133 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6134 unsigned Cost = (PFEntry >> 30);
6136 // Determining when to avoid vperm is tricky. Many things affect the cost
6137 // of vperm, particularly how many times the perm mask needs to be computed.
6138 // For example, if the perm mask can be hoisted out of a loop or is already
6139 // used (perhaps because there are multiple permutes with the same shuffle
6140 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
6141 // the loop requires an extra register.
6143 // As a compromise, we only emit discrete instructions if the shuffle can be
6144 // generated in 3 or fewer operations. When we have loop information
6145 // available, if this block is within a loop, we should avoid using vperm
6146 // for 3-operation perms and use a constant pool load instead.
6148 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
6151 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
6152 // vector that will get spilled to the constant pool.
6153 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
6155 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
6156 // that it is in input element units, not in bytes. Convert now.
6158 // For little endian, the order of the input vectors is reversed, and
6159 // the permutation mask is complemented with respect to 31. This is
6160 // necessary to produce proper semantics with the big-endian-biased vperm
6162 EVT EltVT = V1.getValueType().getVectorElementType();
6163 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
6165 SmallVector<SDValue, 16> ResultMask;
6166 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
6167 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
6169 for (unsigned j = 0; j != BytesPerElement; ++j)
6171 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement+j),
6174 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
6178 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
6181 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
6184 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
6188 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
6189 /// altivec comparison. If it is, return true and fill in Opc/isDot with
6190 /// information about the intrinsic.
6191 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
6193 unsigned IntrinsicID =
6194 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
6197 switch (IntrinsicID) {
6198 default: return false;
6199 // Comparison predicates.
6200 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
6201 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
6202 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
6203 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
6204 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
6205 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
6206 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
6207 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
6208 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
6209 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
6210 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
6211 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
6212 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
6214 // Normal Comparisons.
6215 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
6216 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
6217 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
6218 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
6219 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
6220 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
6221 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
6222 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
6223 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
6224 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
6225 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
6226 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
6227 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
6232 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
6233 /// lower, do it, otherwise return null.
6234 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
6235 SelectionDAG &DAG) const {
6236 // If this is a lowered altivec predicate compare, CompareOpc is set to the
6237 // opcode number of the comparison.
6241 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
6242 return SDValue(); // Don't custom lower most intrinsics.
6244 // If this is a non-dot comparison, make the VCMP node and we are done.
6246 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
6247 Op.getOperand(1), Op.getOperand(2),
6248 DAG.getConstant(CompareOpc, MVT::i32));
6249 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
6252 // Create the PPCISD altivec 'dot' comparison node.
6254 Op.getOperand(2), // LHS
6255 Op.getOperand(3), // RHS
6256 DAG.getConstant(CompareOpc, MVT::i32)
6258 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
6259 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
6261 // Now that we have the comparison, emit a copy from the CR to a GPR.
6262 // This is flagged to the above dot comparison.
6263 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
6264 DAG.getRegister(PPC::CR6, MVT::i32),
6265 CompNode.getValue(1));
6267 // Unpack the result based on how the target uses it.
6268 unsigned BitNo; // Bit # of CR6.
6269 bool InvertBit; // Invert result?
6270 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
6271 default: // Can't happen, don't crash on invalid number though.
6272 case 0: // Return the value of the EQ bit of CR6.
6273 BitNo = 0; InvertBit = false;
6275 case 1: // Return the inverted value of the EQ bit of CR6.
6276 BitNo = 0; InvertBit = true;
6278 case 2: // Return the value of the LT bit of CR6.
6279 BitNo = 2; InvertBit = false;
6281 case 3: // Return the inverted value of the LT bit of CR6.
6282 BitNo = 2; InvertBit = true;
6286 // Shift the bit into the low position.
6287 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
6288 DAG.getConstant(8-(3-BitNo), MVT::i32));
6290 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
6291 DAG.getConstant(1, MVT::i32));
6293 // If we are supposed to, toggle the bit.
6295 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
6296 DAG.getConstant(1, MVT::i32));
6300 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
6301 SelectionDAG &DAG) const {
6303 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
6304 // instructions), but for smaller types, we need to first extend up to v2i32
6305 // before doing going farther.
6306 if (Op.getValueType() == MVT::v2i64) {
6307 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
6308 if (ExtVT != MVT::v2i32) {
6309 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
6310 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
6311 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
6312 ExtVT.getVectorElementType(), 4)));
6313 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
6314 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
6315 DAG.getValueType(MVT::v2i32));
6324 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
6325 SelectionDAG &DAG) const {
6327 // Create a stack slot that is 16-byte aligned.
6328 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6329 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
6330 EVT PtrVT = getPointerTy();
6331 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6333 // Store the input value into Value#0 of the stack slot.
6334 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
6335 Op.getOperand(0), FIdx, MachinePointerInfo(),
6338 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
6339 false, false, false, 0);
6342 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
6344 if (Op.getValueType() == MVT::v4i32) {
6345 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6347 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
6348 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
6350 SDValue RHSSwap = // = vrlw RHS, 16
6351 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
6353 // Shrinkify inputs to v8i16.
6354 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
6355 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
6356 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
6358 // Low parts multiplied together, generating 32-bit results (we ignore the
6360 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
6361 LHS, RHS, DAG, dl, MVT::v4i32);
6363 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
6364 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
6365 // Shift the high parts up 16 bits.
6366 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
6368 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
6369 } else if (Op.getValueType() == MVT::v8i16) {
6370 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6372 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
6374 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
6375 LHS, RHS, Zero, DAG, dl);
6376 } else if (Op.getValueType() == MVT::v16i8) {
6377 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6378 bool isLittleEndian = Subtarget.isLittleEndian();
6380 // Multiply the even 8-bit parts, producing 16-bit sums.
6381 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
6382 LHS, RHS, DAG, dl, MVT::v8i16);
6383 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
6385 // Multiply the odd 8-bit parts, producing 16-bit sums.
6386 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
6387 LHS, RHS, DAG, dl, MVT::v8i16);
6388 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
6390 // Merge the results together. Because vmuleub and vmuloub are
6391 // instructions with a big-endian bias, we must reverse the
6392 // element numbering and reverse the meaning of "odd" and "even"
6393 // when generating little endian code.
6395 for (unsigned i = 0; i != 8; ++i) {
6396 if (isLittleEndian) {
6398 Ops[i*2+1] = 2*i+16;
6401 Ops[i*2+1] = 2*i+1+16;
6405 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
6407 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
6409 llvm_unreachable("Unknown mul to lower!");
6413 /// LowerOperation - Provide custom lowering hooks for some operations.
6415 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6416 switch (Op.getOpcode()) {
6417 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
6418 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6419 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
6420 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6421 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6422 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6423 case ISD::SETCC: return LowerSETCC(Op, DAG);
6424 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
6425 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
6427 return LowerVASTART(Op, DAG, Subtarget);
6430 return LowerVAARG(Op, DAG, Subtarget);
6433 return LowerVACOPY(Op, DAG, Subtarget);
6435 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget);
6436 case ISD::DYNAMIC_STACKALLOC:
6437 return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget);
6439 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
6440 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
6442 case ISD::LOAD: return LowerLOAD(Op, DAG);
6443 case ISD::STORE: return LowerSTORE(Op, DAG);
6444 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
6445 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6446 case ISD::FP_TO_UINT:
6447 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
6449 case ISD::UINT_TO_FP:
6450 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6451 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6453 // Lower 64-bit shifts.
6454 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
6455 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
6456 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
6458 // Vector-related lowering.
6459 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6460 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6461 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6462 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6463 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
6464 case ISD::MUL: return LowerMUL(Op, DAG);
6466 // For counter-based loop handling.
6467 case ISD::INTRINSIC_W_CHAIN: return SDValue();
6469 // Frame & Return address.
6470 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6471 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6475 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
6476 SmallVectorImpl<SDValue>&Results,
6477 SelectionDAG &DAG) const {
6478 const TargetMachine &TM = getTargetMachine();
6480 switch (N->getOpcode()) {
6482 llvm_unreachable("Do not know how to custom type legalize this operation!");
6483 case ISD::INTRINSIC_W_CHAIN: {
6484 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
6485 Intrinsic::ppc_is_decremented_ctr_nonzero)
6488 assert(N->getValueType(0) == MVT::i1 &&
6489 "Unexpected result type for CTR decrement intrinsic");
6490 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
6491 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
6492 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
6495 Results.push_back(NewInt);
6496 Results.push_back(NewInt.getValue(1));
6500 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
6501 || TM.getSubtarget<PPCSubtarget>().isPPC64())
6504 EVT VT = N->getValueType(0);
6506 if (VT == MVT::i64) {
6507 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget);
6509 Results.push_back(NewNode);
6510 Results.push_back(NewNode.getValue(1));
6514 case ISD::FP_ROUND_INREG: {
6515 assert(N->getValueType(0) == MVT::ppcf128);
6516 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
6517 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6518 MVT::f64, N->getOperand(0),
6519 DAG.getIntPtrConstant(0));
6520 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6521 MVT::f64, N->getOperand(0),
6522 DAG.getIntPtrConstant(1));
6524 // Add the two halves of the long double in round-to-zero mode.
6525 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
6527 // We know the low half is about to be thrown away, so just use something
6529 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
6533 case ISD::FP_TO_SINT:
6534 // LowerFP_TO_INT() can only handle f32 and f64.
6535 if (N->getOperand(0).getValueType() == MVT::ppcf128)
6537 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
6543 //===----------------------------------------------------------------------===//
6544 // Other Lowering Code
6545 //===----------------------------------------------------------------------===//
6548 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
6549 bool is64bit, unsigned BinOpcode) const {
6550 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6551 const TargetInstrInfo *TII =
6552 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6554 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6555 MachineFunction *F = BB->getParent();
6556 MachineFunction::iterator It = BB;
6559 unsigned dest = MI->getOperand(0).getReg();
6560 unsigned ptrA = MI->getOperand(1).getReg();
6561 unsigned ptrB = MI->getOperand(2).getReg();
6562 unsigned incr = MI->getOperand(3).getReg();
6563 DebugLoc dl = MI->getDebugLoc();
6565 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6566 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6567 F->insert(It, loopMBB);
6568 F->insert(It, exitMBB);
6569 exitMBB->splice(exitMBB->begin(), BB,
6570 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6571 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6573 MachineRegisterInfo &RegInfo = F->getRegInfo();
6574 unsigned TmpReg = (!BinOpcode) ? incr :
6575 RegInfo.createVirtualRegister(
6576 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6577 (const TargetRegisterClass *) &PPC::GPRCRegClass);
6581 // fallthrough --> loopMBB
6582 BB->addSuccessor(loopMBB);
6585 // l[wd]arx dest, ptr
6586 // add r0, dest, incr
6587 // st[wd]cx. r0, ptr
6589 // fallthrough --> exitMBB
6591 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6592 .addReg(ptrA).addReg(ptrB);
6594 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
6595 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6596 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
6597 BuildMI(BB, dl, TII->get(PPC::BCC))
6598 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6599 BB->addSuccessor(loopMBB);
6600 BB->addSuccessor(exitMBB);
6609 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
6610 MachineBasicBlock *BB,
6611 bool is8bit, // operation
6612 unsigned BinOpcode) const {
6613 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6614 const TargetInstrInfo *TII =
6615 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6616 // In 64 bit mode we have to use 64 bits for addresses, even though the
6617 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
6618 // registers without caring whether they're 32 or 64, but here we're
6619 // doing actual arithmetic on the addresses.
6620 bool is64bit = Subtarget.isPPC64();
6621 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6623 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6624 MachineFunction *F = BB->getParent();
6625 MachineFunction::iterator It = BB;
6628 unsigned dest = MI->getOperand(0).getReg();
6629 unsigned ptrA = MI->getOperand(1).getReg();
6630 unsigned ptrB = MI->getOperand(2).getReg();
6631 unsigned incr = MI->getOperand(3).getReg();
6632 DebugLoc dl = MI->getDebugLoc();
6634 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6635 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6636 F->insert(It, loopMBB);
6637 F->insert(It, exitMBB);
6638 exitMBB->splice(exitMBB->begin(), BB,
6639 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6640 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6642 MachineRegisterInfo &RegInfo = F->getRegInfo();
6643 const TargetRegisterClass *RC =
6644 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6645 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6646 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6647 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6648 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6649 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
6650 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6651 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6652 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6653 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6654 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
6655 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6656 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6658 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
6662 // fallthrough --> loopMBB
6663 BB->addSuccessor(loopMBB);
6665 // The 4-byte load must be aligned, while a char or short may be
6666 // anywhere in the word. Hence all this nasty bookkeeping code.
6667 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6668 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6669 // xori shift, shift1, 24 [16]
6670 // rlwinm ptr, ptr1, 0, 0, 29
6671 // slw incr2, incr, shift
6672 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6673 // slw mask, mask2, shift
6675 // lwarx tmpDest, ptr
6676 // add tmp, tmpDest, incr2
6677 // andc tmp2, tmpDest, mask
6678 // and tmp3, tmp, mask
6679 // or tmp4, tmp3, tmp2
6682 // fallthrough --> exitMBB
6683 // srw dest, tmpDest, shift
6684 if (ptrA != ZeroReg) {
6685 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6686 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6687 .addReg(ptrA).addReg(ptrB);
6691 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6692 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6693 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6694 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6696 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6697 .addReg(Ptr1Reg).addImm(0).addImm(61);
6699 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6700 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6701 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
6702 .addReg(incr).addReg(ShiftReg);
6704 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6706 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6707 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
6709 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6710 .addReg(Mask2Reg).addReg(ShiftReg);
6713 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6714 .addReg(ZeroReg).addReg(PtrReg);
6716 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
6717 .addReg(Incr2Reg).addReg(TmpDestReg);
6718 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
6719 .addReg(TmpDestReg).addReg(MaskReg);
6720 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
6721 .addReg(TmpReg).addReg(MaskReg);
6722 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
6723 .addReg(Tmp3Reg).addReg(Tmp2Reg);
6724 BuildMI(BB, dl, TII->get(PPC::STWCX))
6725 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
6726 BuildMI(BB, dl, TII->get(PPC::BCC))
6727 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6728 BB->addSuccessor(loopMBB);
6729 BB->addSuccessor(exitMBB);
6734 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
6739 llvm::MachineBasicBlock*
6740 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
6741 MachineBasicBlock *MBB) const {
6742 DebugLoc DL = MI->getDebugLoc();
6743 const TargetInstrInfo *TII =
6744 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6746 MachineFunction *MF = MBB->getParent();
6747 MachineRegisterInfo &MRI = MF->getRegInfo();
6749 const BasicBlock *BB = MBB->getBasicBlock();
6750 MachineFunction::iterator I = MBB;
6754 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6755 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6757 unsigned DstReg = MI->getOperand(0).getReg();
6758 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
6759 assert(RC->hasType(MVT::i32) && "Invalid destination!");
6760 unsigned mainDstReg = MRI.createVirtualRegister(RC);
6761 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
6763 MVT PVT = getPointerTy();
6764 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6765 "Invalid Pointer Size!");
6766 // For v = setjmp(buf), we generate
6769 // SjLjSetup mainMBB
6775 // buf[LabelOffset] = LR
6779 // v = phi(main, restore)
6782 MachineBasicBlock *thisMBB = MBB;
6783 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
6784 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
6785 MF->insert(I, mainMBB);
6786 MF->insert(I, sinkMBB);
6788 MachineInstrBuilder MIB;
6790 // Transfer the remainder of BB and its successor edges to sinkMBB.
6791 sinkMBB->splice(sinkMBB->begin(), MBB,
6792 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
6793 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
6795 // Note that the structure of the jmp_buf used here is not compatible
6796 // with that used by libc, and is not designed to be. Specifically, it
6797 // stores only those 'reserved' registers that LLVM does not otherwise
6798 // understand how to spill. Also, by convention, by the time this
6799 // intrinsic is called, Clang has already stored the frame address in the
6800 // first slot of the buffer and stack address in the third. Following the
6801 // X86 target code, we'll store the jump address in the second slot. We also
6802 // need to save the TOC pointer (R2) to handle jumps between shared
6803 // libraries, and that will be stored in the fourth slot. The thread
6804 // identifier (R13) is not affected.
6807 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6808 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6809 const int64_t BPOffset = 4 * PVT.getStoreSize();
6811 // Prepare IP either in reg.
6812 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
6813 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
6814 unsigned BufReg = MI->getOperand(1).getReg();
6816 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
6817 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
6821 MIB.setMemRefs(MMOBegin, MMOEnd);
6824 // Naked functions never have a base pointer, and so we use r1. For all
6825 // other functions, this decision must be delayed until during PEI.
6827 if (MF->getFunction()->getAttributes().hasAttribute(
6828 AttributeSet::FunctionIndex, Attribute::Naked))
6829 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
6831 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
6833 MIB = BuildMI(*thisMBB, MI, DL,
6834 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
6838 MIB.setMemRefs(MMOBegin, MMOEnd);
6841 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
6842 const PPCRegisterInfo *TRI =
6843 getTargetMachine().getSubtarget<PPCSubtarget>().getRegisterInfo();
6844 MIB.addRegMask(TRI->getNoPreservedMask());
6846 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
6848 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
6850 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
6852 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
6853 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
6857 MIB = BuildMI(mainMBB, DL,
6858 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
6861 if (Subtarget.isPPC64()) {
6862 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
6864 .addImm(LabelOffset)
6867 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
6869 .addImm(LabelOffset)
6873 MIB.setMemRefs(MMOBegin, MMOEnd);
6875 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
6876 mainMBB->addSuccessor(sinkMBB);
6879 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
6880 TII->get(PPC::PHI), DstReg)
6881 .addReg(mainDstReg).addMBB(mainMBB)
6882 .addReg(restoreDstReg).addMBB(thisMBB);
6884 MI->eraseFromParent();
6889 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
6890 MachineBasicBlock *MBB) const {
6891 DebugLoc DL = MI->getDebugLoc();
6892 const TargetInstrInfo *TII =
6893 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6895 MachineFunction *MF = MBB->getParent();
6896 MachineRegisterInfo &MRI = MF->getRegInfo();
6899 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6900 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6902 MVT PVT = getPointerTy();
6903 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6904 "Invalid Pointer Size!");
6906 const TargetRegisterClass *RC =
6907 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6908 unsigned Tmp = MRI.createVirtualRegister(RC);
6909 // Since FP is only updated here but NOT referenced, it's treated as GPR.
6910 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6911 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6912 unsigned BP = (PVT == MVT::i64) ? PPC::X30 :
6913 (Subtarget.isSVR4ABI() &&
6914 MF->getTarget().getRelocationModel() == Reloc::PIC_ ?
6915 PPC::R29 : PPC::R30);
6917 MachineInstrBuilder MIB;
6919 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6920 const int64_t SPOffset = 2 * PVT.getStoreSize();
6921 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6922 const int64_t BPOffset = 4 * PVT.getStoreSize();
6924 unsigned BufReg = MI->getOperand(0).getReg();
6926 // Reload FP (the jumped-to function may not have had a
6927 // frame pointer, and if so, then its r31 will be restored
6929 if (PVT == MVT::i64) {
6930 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
6934 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
6938 MIB.setMemRefs(MMOBegin, MMOEnd);
6941 if (PVT == MVT::i64) {
6942 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
6943 .addImm(LabelOffset)
6946 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
6947 .addImm(LabelOffset)
6950 MIB.setMemRefs(MMOBegin, MMOEnd);
6953 if (PVT == MVT::i64) {
6954 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
6958 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
6962 MIB.setMemRefs(MMOBegin, MMOEnd);
6965 if (PVT == MVT::i64) {
6966 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
6970 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
6974 MIB.setMemRefs(MMOBegin, MMOEnd);
6977 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
6978 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
6982 MIB.setMemRefs(MMOBegin, MMOEnd);
6986 BuildMI(*MBB, MI, DL,
6987 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
6988 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
6990 MI->eraseFromParent();
6995 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6996 MachineBasicBlock *BB) const {
6997 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
6998 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
6999 return emitEHSjLjSetJmp(MI, BB);
7000 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
7001 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
7002 return emitEHSjLjLongJmp(MI, BB);
7005 const TargetInstrInfo *TII =
7006 getTargetMachine().getSubtargetImpl()->getInstrInfo();
7008 // To "insert" these instructions we actually have to insert their
7009 // control-flow patterns.
7010 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7011 MachineFunction::iterator It = BB;
7014 MachineFunction *F = BB->getParent();
7016 if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7017 MI->getOpcode() == PPC::SELECT_CC_I8 ||
7018 MI->getOpcode() == PPC::SELECT_I4 ||
7019 MI->getOpcode() == PPC::SELECT_I8)) {
7020 SmallVector<MachineOperand, 2> Cond;
7021 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7022 MI->getOpcode() == PPC::SELECT_CC_I8)
7023 Cond.push_back(MI->getOperand(4));
7025 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
7026 Cond.push_back(MI->getOperand(1));
7028 DebugLoc dl = MI->getDebugLoc();
7029 const TargetInstrInfo *TII =
7030 getTargetMachine().getSubtargetImpl()->getInstrInfo();
7031 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
7032 Cond, MI->getOperand(2).getReg(),
7033 MI->getOperand(3).getReg());
7034 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7035 MI->getOpcode() == PPC::SELECT_CC_I8 ||
7036 MI->getOpcode() == PPC::SELECT_CC_F4 ||
7037 MI->getOpcode() == PPC::SELECT_CC_F8 ||
7038 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
7039 MI->getOpcode() == PPC::SELECT_I4 ||
7040 MI->getOpcode() == PPC::SELECT_I8 ||
7041 MI->getOpcode() == PPC::SELECT_F4 ||
7042 MI->getOpcode() == PPC::SELECT_F8 ||
7043 MI->getOpcode() == PPC::SELECT_VRRC) {
7044 // The incoming instruction knows the destination vreg to set, the
7045 // condition code register to branch on, the true/false values to
7046 // select between, and a branch opcode to use.
7051 // cmpTY ccX, r1, r2
7053 // fallthrough --> copy0MBB
7054 MachineBasicBlock *thisMBB = BB;
7055 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7056 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7057 DebugLoc dl = MI->getDebugLoc();
7058 F->insert(It, copy0MBB);
7059 F->insert(It, sinkMBB);
7061 // Transfer the remainder of BB and its successor edges to sinkMBB.
7062 sinkMBB->splice(sinkMBB->begin(), BB,
7063 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7064 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7066 // Next, add the true and fallthrough blocks as its successors.
7067 BB->addSuccessor(copy0MBB);
7068 BB->addSuccessor(sinkMBB);
7070 if (MI->getOpcode() == PPC::SELECT_I4 ||
7071 MI->getOpcode() == PPC::SELECT_I8 ||
7072 MI->getOpcode() == PPC::SELECT_F4 ||
7073 MI->getOpcode() == PPC::SELECT_F8 ||
7074 MI->getOpcode() == PPC::SELECT_VRRC) {
7075 BuildMI(BB, dl, TII->get(PPC::BC))
7076 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
7078 unsigned SelectPred = MI->getOperand(4).getImm();
7079 BuildMI(BB, dl, TII->get(PPC::BCC))
7080 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
7084 // %FalseValue = ...
7085 // # fallthrough to sinkMBB
7088 // Update machine-CFG edges
7089 BB->addSuccessor(sinkMBB);
7092 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7095 BuildMI(*BB, BB->begin(), dl,
7096 TII->get(PPC::PHI), MI->getOperand(0).getReg())
7097 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
7098 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7100 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
7101 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
7102 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
7103 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
7104 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
7105 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
7106 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
7107 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
7109 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
7110 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
7111 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
7112 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
7113 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
7114 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
7115 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
7116 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
7118 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
7119 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
7120 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
7121 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
7122 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
7123 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
7124 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
7125 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
7127 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
7128 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
7129 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
7130 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
7131 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
7132 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
7133 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
7134 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
7136 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
7137 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND);
7138 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
7139 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND);
7140 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
7141 BB = EmitAtomicBinary(MI, BB, false, PPC::NAND);
7142 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
7143 BB = EmitAtomicBinary(MI, BB, true, PPC::NAND8);
7145 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
7146 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
7147 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
7148 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
7149 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
7150 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
7151 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
7152 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
7154 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
7155 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
7156 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
7157 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
7158 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
7159 BB = EmitAtomicBinary(MI, BB, false, 0);
7160 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
7161 BB = EmitAtomicBinary(MI, BB, true, 0);
7163 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
7164 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
7165 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
7167 unsigned dest = MI->getOperand(0).getReg();
7168 unsigned ptrA = MI->getOperand(1).getReg();
7169 unsigned ptrB = MI->getOperand(2).getReg();
7170 unsigned oldval = MI->getOperand(3).getReg();
7171 unsigned newval = MI->getOperand(4).getReg();
7172 DebugLoc dl = MI->getDebugLoc();
7174 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
7175 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
7176 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
7177 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7178 F->insert(It, loop1MBB);
7179 F->insert(It, loop2MBB);
7180 F->insert(It, midMBB);
7181 F->insert(It, exitMBB);
7182 exitMBB->splice(exitMBB->begin(), BB,
7183 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7184 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7188 // fallthrough --> loopMBB
7189 BB->addSuccessor(loop1MBB);
7192 // l[wd]arx dest, ptr
7193 // cmp[wd] dest, oldval
7196 // st[wd]cx. newval, ptr
7200 // st[wd]cx. dest, ptr
7203 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
7204 .addReg(ptrA).addReg(ptrB);
7205 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
7206 .addReg(oldval).addReg(dest);
7207 BuildMI(BB, dl, TII->get(PPC::BCC))
7208 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7209 BB->addSuccessor(loop2MBB);
7210 BB->addSuccessor(midMBB);
7213 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7214 .addReg(newval).addReg(ptrA).addReg(ptrB);
7215 BuildMI(BB, dl, TII->get(PPC::BCC))
7216 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7217 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7218 BB->addSuccessor(loop1MBB);
7219 BB->addSuccessor(exitMBB);
7222 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7223 .addReg(dest).addReg(ptrA).addReg(ptrB);
7224 BB->addSuccessor(exitMBB);
7229 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
7230 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
7231 // We must use 64-bit registers for addresses when targeting 64-bit,
7232 // since we're actually doing arithmetic on them. Other registers
7234 bool is64bit = Subtarget.isPPC64();
7235 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
7237 unsigned dest = MI->getOperand(0).getReg();
7238 unsigned ptrA = MI->getOperand(1).getReg();
7239 unsigned ptrB = MI->getOperand(2).getReg();
7240 unsigned oldval = MI->getOperand(3).getReg();
7241 unsigned newval = MI->getOperand(4).getReg();
7242 DebugLoc dl = MI->getDebugLoc();
7244 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
7245 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
7246 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
7247 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7248 F->insert(It, loop1MBB);
7249 F->insert(It, loop2MBB);
7250 F->insert(It, midMBB);
7251 F->insert(It, exitMBB);
7252 exitMBB->splice(exitMBB->begin(), BB,
7253 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7254 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7256 MachineRegisterInfo &RegInfo = F->getRegInfo();
7257 const TargetRegisterClass *RC =
7258 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
7259 (const TargetRegisterClass *) &PPC::GPRCRegClass;
7260 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
7261 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
7262 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
7263 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
7264 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
7265 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
7266 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
7267 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
7268 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
7269 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
7270 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
7271 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
7272 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
7274 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
7275 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
7278 // fallthrough --> loopMBB
7279 BB->addSuccessor(loop1MBB);
7281 // The 4-byte load must be aligned, while a char or short may be
7282 // anywhere in the word. Hence all this nasty bookkeeping code.
7283 // add ptr1, ptrA, ptrB [copy if ptrA==0]
7284 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
7285 // xori shift, shift1, 24 [16]
7286 // rlwinm ptr, ptr1, 0, 0, 29
7287 // slw newval2, newval, shift
7288 // slw oldval2, oldval,shift
7289 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
7290 // slw mask, mask2, shift
7291 // and newval3, newval2, mask
7292 // and oldval3, oldval2, mask
7294 // lwarx tmpDest, ptr
7295 // and tmp, tmpDest, mask
7296 // cmpw tmp, oldval3
7299 // andc tmp2, tmpDest, mask
7300 // or tmp4, tmp2, newval3
7305 // stwcx. tmpDest, ptr
7307 // srw dest, tmpDest, shift
7308 if (ptrA != ZeroReg) {
7309 Ptr1Reg = RegInfo.createVirtualRegister(RC);
7310 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
7311 .addReg(ptrA).addReg(ptrB);
7315 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
7316 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
7317 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
7318 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
7320 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
7321 .addReg(Ptr1Reg).addImm(0).addImm(61);
7323 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
7324 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
7325 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
7326 .addReg(newval).addReg(ShiftReg);
7327 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
7328 .addReg(oldval).addReg(ShiftReg);
7330 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
7332 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
7333 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
7334 .addReg(Mask3Reg).addImm(65535);
7336 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
7337 .addReg(Mask2Reg).addReg(ShiftReg);
7338 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
7339 .addReg(NewVal2Reg).addReg(MaskReg);
7340 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
7341 .addReg(OldVal2Reg).addReg(MaskReg);
7344 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
7345 .addReg(ZeroReg).addReg(PtrReg);
7346 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
7347 .addReg(TmpDestReg).addReg(MaskReg);
7348 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
7349 .addReg(TmpReg).addReg(OldVal3Reg);
7350 BuildMI(BB, dl, TII->get(PPC::BCC))
7351 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7352 BB->addSuccessor(loop2MBB);
7353 BB->addSuccessor(midMBB);
7356 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
7357 .addReg(TmpDestReg).addReg(MaskReg);
7358 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
7359 .addReg(Tmp2Reg).addReg(NewVal3Reg);
7360 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
7361 .addReg(ZeroReg).addReg(PtrReg);
7362 BuildMI(BB, dl, TII->get(PPC::BCC))
7363 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7364 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7365 BB->addSuccessor(loop1MBB);
7366 BB->addSuccessor(exitMBB);
7369 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
7370 .addReg(ZeroReg).addReg(PtrReg);
7371 BB->addSuccessor(exitMBB);
7376 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
7378 } else if (MI->getOpcode() == PPC::FADDrtz) {
7379 // This pseudo performs an FADD with rounding mode temporarily forced
7380 // to round-to-zero. We emit this via custom inserter since the FPSCR
7381 // is not modeled at the SelectionDAG level.
7382 unsigned Dest = MI->getOperand(0).getReg();
7383 unsigned Src1 = MI->getOperand(1).getReg();
7384 unsigned Src2 = MI->getOperand(2).getReg();
7385 DebugLoc dl = MI->getDebugLoc();
7387 MachineRegisterInfo &RegInfo = F->getRegInfo();
7388 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
7390 // Save FPSCR value.
7391 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
7393 // Set rounding mode to round-to-zero.
7394 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
7395 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
7397 // Perform addition.
7398 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
7400 // Restore FPSCR value.
7401 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg);
7402 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7403 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
7404 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7405 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
7406 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7407 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
7408 PPC::ANDIo8 : PPC::ANDIo;
7409 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7410 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
7412 MachineRegisterInfo &RegInfo = F->getRegInfo();
7413 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
7414 &PPC::GPRCRegClass :
7415 &PPC::G8RCRegClass);
7417 DebugLoc dl = MI->getDebugLoc();
7418 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
7419 .addReg(MI->getOperand(1).getReg()).addImm(1);
7420 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
7421 MI->getOperand(0).getReg())
7422 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
7424 llvm_unreachable("Unexpected instr type to insert");
7427 MI->eraseFromParent(); // The pseudo instruction is gone now.
7431 //===----------------------------------------------------------------------===//
7432 // Target Optimization Hooks
7433 //===----------------------------------------------------------------------===//
7435 SDValue PPCTargetLowering::DAGCombineFastRecip(SDValue Op,
7436 DAGCombinerInfo &DCI) const {
7437 if (DCI.isAfterLegalizeVectorOps())
7440 EVT VT = Op.getValueType();
7442 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
7443 (VT == MVT::f64 && Subtarget.hasFRE()) ||
7444 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7445 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7447 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
7448 // For the reciprocal, we need to find the zero of the function:
7449 // F(X) = A X - 1 [which has a zero at X = 1/A]
7451 // X_{i+1} = X_i (2 - A X_i) = X_i + X_i (1 - A X_i) [this second form
7452 // does not require additional intermediate precision]
7454 // Convergence is quadratic, so we essentially double the number of digits
7455 // correct after every iteration. The minimum architected relative
7456 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
7457 // 23 digits and double has 52 digits.
7458 int Iterations = Subtarget.hasRecipPrec() ? 1 : 3;
7459 if (VT.getScalarType() == MVT::f64)
7462 SelectionDAG &DAG = DCI.DAG;
7466 DAG.getConstantFP(1.0, VT.getScalarType());
7467 if (VT.isVector()) {
7468 assert(VT.getVectorNumElements() == 4 &&
7469 "Unknown vector type");
7470 FPOne = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
7471 FPOne, FPOne, FPOne, FPOne);
7474 SDValue Est = DAG.getNode(PPCISD::FRE, dl, VT, Op);
7475 DCI.AddToWorklist(Est.getNode());
7477 // Newton iterations: Est = Est + Est (1 - Arg * Est)
7478 for (int i = 0; i < Iterations; ++i) {
7479 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Op, Est);
7480 DCI.AddToWorklist(NewEst.getNode());
7482 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPOne, NewEst);
7483 DCI.AddToWorklist(NewEst.getNode());
7485 NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
7486 DCI.AddToWorklist(NewEst.getNode());
7488 Est = DAG.getNode(ISD::FADD, dl, VT, Est, NewEst);
7489 DCI.AddToWorklist(Est.getNode());
7498 SDValue PPCTargetLowering::DAGCombineFastRecipFSQRT(SDValue Op,
7499 DAGCombinerInfo &DCI) const {
7500 if (DCI.isAfterLegalizeVectorOps())
7503 EVT VT = Op.getValueType();
7505 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
7506 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
7507 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7508 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7510 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
7511 // For the reciprocal sqrt, we need to find the zero of the function:
7512 // F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
7514 // X_{i+1} = X_i (1.5 - A X_i^2 / 2)
7515 // As a result, we precompute A/2 prior to the iteration loop.
7517 // Convergence is quadratic, so we essentially double the number of digits
7518 // correct after every iteration. The minimum architected relative
7519 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
7520 // 23 digits and double has 52 digits.
7521 int Iterations = Subtarget.hasRecipPrec() ? 1 : 3;
7522 if (VT.getScalarType() == MVT::f64)
7525 SelectionDAG &DAG = DCI.DAG;
7528 SDValue FPThreeHalves =
7529 DAG.getConstantFP(1.5, VT.getScalarType());
7530 if (VT.isVector()) {
7531 assert(VT.getVectorNumElements() == 4 &&
7532 "Unknown vector type");
7533 FPThreeHalves = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
7534 FPThreeHalves, FPThreeHalves,
7535 FPThreeHalves, FPThreeHalves);
7538 SDValue Est = DAG.getNode(PPCISD::FRSQRTE, dl, VT, Op);
7539 DCI.AddToWorklist(Est.getNode());
7541 // We now need 0.5*Arg which we can write as (1.5*Arg - Arg) so that
7542 // this entire sequence requires only one FP constant.
7543 SDValue HalfArg = DAG.getNode(ISD::FMUL, dl, VT, FPThreeHalves, Op);
7544 DCI.AddToWorklist(HalfArg.getNode());
7546 HalfArg = DAG.getNode(ISD::FSUB, dl, VT, HalfArg, Op);
7547 DCI.AddToWorklist(HalfArg.getNode());
7549 // Newton iterations: Est = Est * (1.5 - HalfArg * Est * Est)
7550 for (int i = 0; i < Iterations; ++i) {
7551 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, Est);
7552 DCI.AddToWorklist(NewEst.getNode());
7554 NewEst = DAG.getNode(ISD::FMUL, dl, VT, HalfArg, NewEst);
7555 DCI.AddToWorklist(NewEst.getNode());
7557 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPThreeHalves, NewEst);
7558 DCI.AddToWorklist(NewEst.getNode());
7560 Est = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
7561 DCI.AddToWorklist(Est.getNode());
7570 static bool isConsecutiveLSLoc(SDValue Loc, EVT VT, LSBaseSDNode *Base,
7571 unsigned Bytes, int Dist,
7572 SelectionDAG &DAG) {
7573 if (VT.getSizeInBits() / 8 != Bytes)
7576 SDValue BaseLoc = Base->getBasePtr();
7577 if (Loc.getOpcode() == ISD::FrameIndex) {
7578 if (BaseLoc.getOpcode() != ISD::FrameIndex)
7580 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7581 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
7582 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
7583 int FS = MFI->getObjectSize(FI);
7584 int BFS = MFI->getObjectSize(BFI);
7585 if (FS != BFS || FS != (int)Bytes) return false;
7586 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
7590 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
7591 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
7594 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7595 const GlobalValue *GV1 = nullptr;
7596 const GlobalValue *GV2 = nullptr;
7597 int64_t Offset1 = 0;
7598 int64_t Offset2 = 0;
7599 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
7600 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
7601 if (isGA1 && isGA2 && GV1 == GV2)
7602 return Offset1 == (Offset2 + Dist*Bytes);
7606 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
7607 // not enforce equality of the chain operands.
7608 static bool isConsecutiveLS(SDNode *N, LSBaseSDNode *Base,
7609 unsigned Bytes, int Dist,
7610 SelectionDAG &DAG) {
7611 if (LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(N)) {
7612 EVT VT = LS->getMemoryVT();
7613 SDValue Loc = LS->getBasePtr();
7614 return isConsecutiveLSLoc(Loc, VT, Base, Bytes, Dist, DAG);
7617 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
7619 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
7620 default: return false;
7621 case Intrinsic::ppc_altivec_lvx:
7622 case Intrinsic::ppc_altivec_lvxl:
7625 case Intrinsic::ppc_altivec_lvebx:
7628 case Intrinsic::ppc_altivec_lvehx:
7631 case Intrinsic::ppc_altivec_lvewx:
7636 return isConsecutiveLSLoc(N->getOperand(2), VT, Base, Bytes, Dist, DAG);
7639 if (N->getOpcode() == ISD::INTRINSIC_VOID) {
7641 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
7642 default: return false;
7643 case Intrinsic::ppc_altivec_stvx:
7644 case Intrinsic::ppc_altivec_stvxl:
7647 case Intrinsic::ppc_altivec_stvebx:
7650 case Intrinsic::ppc_altivec_stvehx:
7653 case Intrinsic::ppc_altivec_stvewx:
7658 return isConsecutiveLSLoc(N->getOperand(3), VT, Base, Bytes, Dist, DAG);
7664 // Return true is there is a nearyby consecutive load to the one provided
7665 // (regardless of alignment). We search up and down the chain, looking though
7666 // token factors and other loads (but nothing else). As a result, a true result
7667 // indicates that it is safe to create a new consecutive load adjacent to the
7669 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
7670 SDValue Chain = LD->getChain();
7671 EVT VT = LD->getMemoryVT();
7673 SmallSet<SDNode *, 16> LoadRoots;
7674 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
7675 SmallSet<SDNode *, 16> Visited;
7677 // First, search up the chain, branching to follow all token-factor operands.
7678 // If we find a consecutive load, then we're done, otherwise, record all
7679 // nodes just above the top-level loads and token factors.
7680 while (!Queue.empty()) {
7681 SDNode *ChainNext = Queue.pop_back_val();
7682 if (!Visited.insert(ChainNext))
7685 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(ChainNext)) {
7686 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7689 if (!Visited.count(ChainLD->getChain().getNode()))
7690 Queue.push_back(ChainLD->getChain().getNode());
7691 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
7692 for (const SDUse &O : ChainNext->ops())
7693 if (!Visited.count(O.getNode()))
7694 Queue.push_back(O.getNode());
7696 LoadRoots.insert(ChainNext);
7699 // Second, search down the chain, starting from the top-level nodes recorded
7700 // in the first phase. These top-level nodes are the nodes just above all
7701 // loads and token factors. Starting with their uses, recursively look though
7702 // all loads (just the chain uses) and token factors to find a consecutive
7707 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
7708 IE = LoadRoots.end(); I != IE; ++I) {
7709 Queue.push_back(*I);
7711 while (!Queue.empty()) {
7712 SDNode *LoadRoot = Queue.pop_back_val();
7713 if (!Visited.insert(LoadRoot))
7716 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(LoadRoot))
7717 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7720 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
7721 UE = LoadRoot->use_end(); UI != UE; ++UI)
7722 if (((isa<MemSDNode>(*UI) &&
7723 cast<MemSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
7724 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
7725 Queue.push_back(*UI);
7732 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
7733 DAGCombinerInfo &DCI) const {
7734 SelectionDAG &DAG = DCI.DAG;
7737 assert(Subtarget.useCRBits() &&
7738 "Expecting to be tracking CR bits");
7739 // If we're tracking CR bits, we need to be careful that we don't have:
7740 // trunc(binary-ops(zext(x), zext(y)))
7742 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
7743 // such that we're unnecessarily moving things into GPRs when it would be
7744 // better to keep them in CR bits.
7746 // Note that trunc here can be an actual i1 trunc, or can be the effective
7747 // truncation that comes from a setcc or select_cc.
7748 if (N->getOpcode() == ISD::TRUNCATE &&
7749 N->getValueType(0) != MVT::i1)
7752 if (N->getOperand(0).getValueType() != MVT::i32 &&
7753 N->getOperand(0).getValueType() != MVT::i64)
7756 if (N->getOpcode() == ISD::SETCC ||
7757 N->getOpcode() == ISD::SELECT_CC) {
7758 // If we're looking at a comparison, then we need to make sure that the
7759 // high bits (all except for the first) don't matter the result.
7761 cast<CondCodeSDNode>(N->getOperand(
7762 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
7763 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
7765 if (ISD::isSignedIntSetCC(CC)) {
7766 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
7767 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
7769 } else if (ISD::isUnsignedIntSetCC(CC)) {
7770 if (!DAG.MaskedValueIsZero(N->getOperand(0),
7771 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
7772 !DAG.MaskedValueIsZero(N->getOperand(1),
7773 APInt::getHighBitsSet(OpBits, OpBits-1)))
7776 // This is neither a signed nor an unsigned comparison, just make sure
7777 // that the high bits are equal.
7778 APInt Op1Zero, Op1One;
7779 APInt Op2Zero, Op2One;
7780 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
7781 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
7783 // We don't really care about what is known about the first bit (if
7784 // anything), so clear it in all masks prior to comparing them.
7785 Op1Zero.clearBit(0); Op1One.clearBit(0);
7786 Op2Zero.clearBit(0); Op2One.clearBit(0);
7788 if (Op1Zero != Op2Zero || Op1One != Op2One)
7793 // We now know that the higher-order bits are irrelevant, we just need to
7794 // make sure that all of the intermediate operations are bit operations, and
7795 // all inputs are extensions.
7796 if (N->getOperand(0).getOpcode() != ISD::AND &&
7797 N->getOperand(0).getOpcode() != ISD::OR &&
7798 N->getOperand(0).getOpcode() != ISD::XOR &&
7799 N->getOperand(0).getOpcode() != ISD::SELECT &&
7800 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
7801 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
7802 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
7803 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
7804 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
7807 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
7808 N->getOperand(1).getOpcode() != ISD::AND &&
7809 N->getOperand(1).getOpcode() != ISD::OR &&
7810 N->getOperand(1).getOpcode() != ISD::XOR &&
7811 N->getOperand(1).getOpcode() != ISD::SELECT &&
7812 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
7813 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
7814 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
7815 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
7816 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
7819 SmallVector<SDValue, 4> Inputs;
7820 SmallVector<SDValue, 8> BinOps, PromOps;
7821 SmallPtrSet<SDNode *, 16> Visited;
7823 for (unsigned i = 0; i < 2; ++i) {
7824 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7825 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7826 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7827 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7828 isa<ConstantSDNode>(N->getOperand(i)))
7829 Inputs.push_back(N->getOperand(i));
7831 BinOps.push_back(N->getOperand(i));
7833 if (N->getOpcode() == ISD::TRUNCATE)
7837 // Visit all inputs, collect all binary operations (and, or, xor and
7838 // select) that are all fed by extensions.
7839 while (!BinOps.empty()) {
7840 SDValue BinOp = BinOps.back();
7843 if (!Visited.insert(BinOp.getNode()))
7846 PromOps.push_back(BinOp);
7848 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
7849 // The condition of the select is not promoted.
7850 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
7852 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
7855 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7856 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7857 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7858 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7859 isa<ConstantSDNode>(BinOp.getOperand(i))) {
7860 Inputs.push_back(BinOp.getOperand(i));
7861 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
7862 BinOp.getOperand(i).getOpcode() == ISD::OR ||
7863 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
7864 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
7865 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
7866 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
7867 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7868 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7869 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
7870 BinOps.push_back(BinOp.getOperand(i));
7872 // We have an input that is not an extension or another binary
7873 // operation; we'll abort this transformation.
7879 // Make sure that this is a self-contained cluster of operations (which
7880 // is not quite the same thing as saying that everything has only one
7882 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7883 if (isa<ConstantSDNode>(Inputs[i]))
7886 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
7887 UE = Inputs[i].getNode()->use_end();
7890 if (User != N && !Visited.count(User))
7893 // Make sure that we're not going to promote the non-output-value
7894 // operand(s) or SELECT or SELECT_CC.
7895 // FIXME: Although we could sometimes handle this, and it does occur in
7896 // practice that one of the condition inputs to the select is also one of
7897 // the outputs, we currently can't deal with this.
7898 if (User->getOpcode() == ISD::SELECT) {
7899 if (User->getOperand(0) == Inputs[i])
7901 } else if (User->getOpcode() == ISD::SELECT_CC) {
7902 if (User->getOperand(0) == Inputs[i] ||
7903 User->getOperand(1) == Inputs[i])
7909 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
7910 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
7911 UE = PromOps[i].getNode()->use_end();
7914 if (User != N && !Visited.count(User))
7917 // Make sure that we're not going to promote the non-output-value
7918 // operand(s) or SELECT or SELECT_CC.
7919 // FIXME: Although we could sometimes handle this, and it does occur in
7920 // practice that one of the condition inputs to the select is also one of
7921 // the outputs, we currently can't deal with this.
7922 if (User->getOpcode() == ISD::SELECT) {
7923 if (User->getOperand(0) == PromOps[i])
7925 } else if (User->getOpcode() == ISD::SELECT_CC) {
7926 if (User->getOperand(0) == PromOps[i] ||
7927 User->getOperand(1) == PromOps[i])
7933 // Replace all inputs with the extension operand.
7934 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7935 // Constants may have users outside the cluster of to-be-promoted nodes,
7936 // and so we need to replace those as we do the promotions.
7937 if (isa<ConstantSDNode>(Inputs[i]))
7940 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
7943 // Replace all operations (these are all the same, but have a different
7944 // (i1) return type). DAG.getNode will validate that the types of
7945 // a binary operator match, so go through the list in reverse so that
7946 // we've likely promoted both operands first. Any intermediate truncations or
7947 // extensions disappear.
7948 while (!PromOps.empty()) {
7949 SDValue PromOp = PromOps.back();
7952 if (PromOp.getOpcode() == ISD::TRUNCATE ||
7953 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
7954 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
7955 PromOp.getOpcode() == ISD::ANY_EXTEND) {
7956 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
7957 PromOp.getOperand(0).getValueType() != MVT::i1) {
7958 // The operand is not yet ready (see comment below).
7959 PromOps.insert(PromOps.begin(), PromOp);
7963 SDValue RepValue = PromOp.getOperand(0);
7964 if (isa<ConstantSDNode>(RepValue))
7965 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
7967 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
7972 switch (PromOp.getOpcode()) {
7973 default: C = 0; break;
7974 case ISD::SELECT: C = 1; break;
7975 case ISD::SELECT_CC: C = 2; break;
7978 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
7979 PromOp.getOperand(C).getValueType() != MVT::i1) ||
7980 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
7981 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
7982 // The to-be-promoted operands of this node have not yet been
7983 // promoted (this should be rare because we're going through the
7984 // list backward, but if one of the operands has several users in
7985 // this cluster of to-be-promoted nodes, it is possible).
7986 PromOps.insert(PromOps.begin(), PromOp);
7990 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
7991 PromOp.getNode()->op_end());
7993 // If there are any constant inputs, make sure they're replaced now.
7994 for (unsigned i = 0; i < 2; ++i)
7995 if (isa<ConstantSDNode>(Ops[C+i]))
7996 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
7998 DAG.ReplaceAllUsesOfValueWith(PromOp,
7999 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
8002 // Now we're left with the initial truncation itself.
8003 if (N->getOpcode() == ISD::TRUNCATE)
8004 return N->getOperand(0);
8006 // Otherwise, this is a comparison. The operands to be compared have just
8007 // changed type (to i1), but everything else is the same.
8008 return SDValue(N, 0);
8011 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
8012 DAGCombinerInfo &DCI) const {
8013 SelectionDAG &DAG = DCI.DAG;
8016 // If we're tracking CR bits, we need to be careful that we don't have:
8017 // zext(binary-ops(trunc(x), trunc(y)))
8019 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
8020 // such that we're unnecessarily moving things into CR bits that can more
8021 // efficiently stay in GPRs. Note that if we're not certain that the high
8022 // bits are set as required by the final extension, we still may need to do
8023 // some masking to get the proper behavior.
8025 // This same functionality is important on PPC64 when dealing with
8026 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
8027 // the return values of functions. Because it is so similar, it is handled
8030 if (N->getValueType(0) != MVT::i32 &&
8031 N->getValueType(0) != MVT::i64)
8034 if (!((N->getOperand(0).getValueType() == MVT::i1 &&
8035 Subtarget.useCRBits()) ||
8036 (N->getOperand(0).getValueType() == MVT::i32 &&
8037 Subtarget.isPPC64())))
8040 if (N->getOperand(0).getOpcode() != ISD::AND &&
8041 N->getOperand(0).getOpcode() != ISD::OR &&
8042 N->getOperand(0).getOpcode() != ISD::XOR &&
8043 N->getOperand(0).getOpcode() != ISD::SELECT &&
8044 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
8047 SmallVector<SDValue, 4> Inputs;
8048 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
8049 SmallPtrSet<SDNode *, 16> Visited;
8051 // Visit all inputs, collect all binary operations (and, or, xor and
8052 // select) that are all fed by truncations.
8053 while (!BinOps.empty()) {
8054 SDValue BinOp = BinOps.back();
8057 if (!Visited.insert(BinOp.getNode()))
8060 PromOps.push_back(BinOp);
8062 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
8063 // The condition of the select is not promoted.
8064 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
8066 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
8069 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
8070 isa<ConstantSDNode>(BinOp.getOperand(i))) {
8071 Inputs.push_back(BinOp.getOperand(i));
8072 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
8073 BinOp.getOperand(i).getOpcode() == ISD::OR ||
8074 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
8075 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
8076 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
8077 BinOps.push_back(BinOp.getOperand(i));
8079 // We have an input that is not a truncation or another binary
8080 // operation; we'll abort this transformation.
8086 // Make sure that this is a self-contained cluster of operations (which
8087 // is not quite the same thing as saying that everything has only one
8089 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8090 if (isa<ConstantSDNode>(Inputs[i]))
8093 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
8094 UE = Inputs[i].getNode()->use_end();
8097 if (User != N && !Visited.count(User))
8100 // Make sure that we're not going to promote the non-output-value
8101 // operand(s) or SELECT or SELECT_CC.
8102 // FIXME: Although we could sometimes handle this, and it does occur in
8103 // practice that one of the condition inputs to the select is also one of
8104 // the outputs, we currently can't deal with this.
8105 if (User->getOpcode() == ISD::SELECT) {
8106 if (User->getOperand(0) == Inputs[i])
8108 } else if (User->getOpcode() == ISD::SELECT_CC) {
8109 if (User->getOperand(0) == Inputs[i] ||
8110 User->getOperand(1) == Inputs[i])
8116 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
8117 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
8118 UE = PromOps[i].getNode()->use_end();
8121 if (User != N && !Visited.count(User))
8124 // Make sure that we're not going to promote the non-output-value
8125 // operand(s) or SELECT or SELECT_CC.
8126 // FIXME: Although we could sometimes handle this, and it does occur in
8127 // practice that one of the condition inputs to the select is also one of
8128 // the outputs, we currently can't deal with this.
8129 if (User->getOpcode() == ISD::SELECT) {
8130 if (User->getOperand(0) == PromOps[i])
8132 } else if (User->getOpcode() == ISD::SELECT_CC) {
8133 if (User->getOperand(0) == PromOps[i] ||
8134 User->getOperand(1) == PromOps[i])
8140 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
8141 bool ReallyNeedsExt = false;
8142 if (N->getOpcode() != ISD::ANY_EXTEND) {
8143 // If all of the inputs are not already sign/zero extended, then
8144 // we'll still need to do that at the end.
8145 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8146 if (isa<ConstantSDNode>(Inputs[i]))
8150 Inputs[i].getOperand(0).getValueSizeInBits();
8151 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
8153 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
8154 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
8155 APInt::getHighBitsSet(OpBits,
8156 OpBits-PromBits))) ||
8157 (N->getOpcode() == ISD::SIGN_EXTEND &&
8158 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
8159 (OpBits-(PromBits-1)))) {
8160 ReallyNeedsExt = true;
8166 // Replace all inputs, either with the truncation operand, or a
8167 // truncation or extension to the final output type.
8168 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8169 // Constant inputs need to be replaced with the to-be-promoted nodes that
8170 // use them because they might have users outside of the cluster of
8172 if (isa<ConstantSDNode>(Inputs[i]))
8175 SDValue InSrc = Inputs[i].getOperand(0);
8176 if (Inputs[i].getValueType() == N->getValueType(0))
8177 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
8178 else if (N->getOpcode() == ISD::SIGN_EXTEND)
8179 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8180 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
8181 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8182 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8183 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
8185 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8186 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
8189 // Replace all operations (these are all the same, but have a different
8190 // (promoted) return type). DAG.getNode will validate that the types of
8191 // a binary operator match, so go through the list in reverse so that
8192 // we've likely promoted both operands first.
8193 while (!PromOps.empty()) {
8194 SDValue PromOp = PromOps.back();
8198 switch (PromOp.getOpcode()) {
8199 default: C = 0; break;
8200 case ISD::SELECT: C = 1; break;
8201 case ISD::SELECT_CC: C = 2; break;
8204 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
8205 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
8206 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
8207 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
8208 // The to-be-promoted operands of this node have not yet been
8209 // promoted (this should be rare because we're going through the
8210 // list backward, but if one of the operands has several users in
8211 // this cluster of to-be-promoted nodes, it is possible).
8212 PromOps.insert(PromOps.begin(), PromOp);
8216 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
8217 PromOp.getNode()->op_end());
8219 // If this node has constant inputs, then they'll need to be promoted here.
8220 for (unsigned i = 0; i < 2; ++i) {
8221 if (!isa<ConstantSDNode>(Ops[C+i]))
8223 if (Ops[C+i].getValueType() == N->getValueType(0))
8226 if (N->getOpcode() == ISD::SIGN_EXTEND)
8227 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8228 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8229 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8231 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8234 DAG.ReplaceAllUsesOfValueWith(PromOp,
8235 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
8238 // Now we're left with the initial extension itself.
8239 if (!ReallyNeedsExt)
8240 return N->getOperand(0);
8242 // To zero extend, just mask off everything except for the first bit (in the
8244 if (N->getOpcode() == ISD::ZERO_EXTEND)
8245 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
8246 DAG.getConstant(APInt::getLowBitsSet(
8247 N->getValueSizeInBits(0), PromBits),
8248 N->getValueType(0)));
8250 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
8251 "Invalid extension type");
8252 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0));
8254 DAG.getConstant(N->getValueSizeInBits(0)-PromBits, ShiftAmountTy);
8255 return DAG.getNode(ISD::SRA, dl, N->getValueType(0),
8256 DAG.getNode(ISD::SHL, dl, N->getValueType(0),
8257 N->getOperand(0), ShiftCst), ShiftCst);
8260 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
8261 DAGCombinerInfo &DCI) const {
8262 const TargetMachine &TM = getTargetMachine();
8263 SelectionDAG &DAG = DCI.DAG;
8265 switch (N->getOpcode()) {
8268 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8269 if (C->isNullValue()) // 0 << V -> 0.
8270 return N->getOperand(0);
8274 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8275 if (C->isNullValue()) // 0 >>u V -> 0.
8276 return N->getOperand(0);
8280 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8281 if (C->isNullValue() || // 0 >>s V -> 0.
8282 C->isAllOnesValue()) // -1 >>s V -> -1.
8283 return N->getOperand(0);
8286 case ISD::SIGN_EXTEND:
8287 case ISD::ZERO_EXTEND:
8288 case ISD::ANY_EXTEND:
8289 return DAGCombineExtBoolTrunc(N, DCI);
8292 case ISD::SELECT_CC:
8293 return DAGCombineTruncBoolExt(N, DCI);
8295 assert(TM.Options.UnsafeFPMath &&
8296 "Reciprocal estimates require UnsafeFPMath");
8298 if (N->getOperand(1).getOpcode() == ISD::FSQRT) {
8300 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0), DCI);
8302 DCI.AddToWorklist(RV.getNode());
8303 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
8304 N->getOperand(0), RV);
8306 } else if (N->getOperand(1).getOpcode() == ISD::FP_EXTEND &&
8307 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
8309 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
8312 DCI.AddToWorklist(RV.getNode());
8313 RV = DAG.getNode(ISD::FP_EXTEND, SDLoc(N->getOperand(1)),
8314 N->getValueType(0), RV);
8315 DCI.AddToWorklist(RV.getNode());
8316 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
8317 N->getOperand(0), RV);
8319 } else if (N->getOperand(1).getOpcode() == ISD::FP_ROUND &&
8320 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
8322 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
8325 DCI.AddToWorklist(RV.getNode());
8326 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N->getOperand(1)),
8327 N->getValueType(0), RV,
8328 N->getOperand(1).getOperand(1));
8329 DCI.AddToWorklist(RV.getNode());
8330 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
8331 N->getOperand(0), RV);
8335 SDValue RV = DAGCombineFastRecip(N->getOperand(1), DCI);
8337 DCI.AddToWorklist(RV.getNode());
8338 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
8339 N->getOperand(0), RV);
8345 assert(TM.Options.UnsafeFPMath &&
8346 "Reciprocal estimates require UnsafeFPMath");
8348 // Compute this as 1/(1/sqrt(X)), which is the reciprocal of the
8350 SDValue RV = DAGCombineFastRecipFSQRT(N->getOperand(0), DCI);
8352 DCI.AddToWorklist(RV.getNode());
8353 RV = DAGCombineFastRecip(RV, DCI);
8355 // Unfortunately, RV is now NaN if the input was exactly 0. Select out
8356 // this case and force the answer to 0.
8358 EVT VT = RV.getValueType();
8360 SDValue Zero = DAG.getConstantFP(0.0, VT.getScalarType());
8361 if (VT.isVector()) {
8362 assert(VT.getVectorNumElements() == 4 && "Unknown vector type");
8363 Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Zero, Zero, Zero, Zero);
8367 DAG.getSetCC(dl, getSetCCResultType(*DAG.getContext(), VT),
8368 N->getOperand(0), Zero, ISD::SETEQ);
8369 DCI.AddToWorklist(ZeroCmp.getNode());
8370 DCI.AddToWorklist(RV.getNode());
8372 RV = DAG.getNode(VT.isVector() ? ISD::VSELECT : ISD::SELECT, dl, VT,
8380 case ISD::SINT_TO_FP:
8381 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
8382 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
8383 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
8384 // We allow the src/dst to be either f32/f64, but the intermediate
8385 // type must be i64.
8386 if (N->getOperand(0).getValueType() == MVT::i64 &&
8387 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
8388 SDValue Val = N->getOperand(0).getOperand(0);
8389 if (Val.getValueType() == MVT::f32) {
8390 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8391 DCI.AddToWorklist(Val.getNode());
8394 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
8395 DCI.AddToWorklist(Val.getNode());
8396 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
8397 DCI.AddToWorklist(Val.getNode());
8398 if (N->getValueType(0) == MVT::f32) {
8399 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
8400 DAG.getIntPtrConstant(0));
8401 DCI.AddToWorklist(Val.getNode());
8404 } else if (N->getOperand(0).getValueType() == MVT::i32) {
8405 // If the intermediate type is i32, we can avoid the load/store here
8412 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
8413 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
8414 !cast<StoreSDNode>(N)->isTruncatingStore() &&
8415 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
8416 N->getOperand(1).getValueType() == MVT::i32 &&
8417 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
8418 SDValue Val = N->getOperand(1).getOperand(0);
8419 if (Val.getValueType() == MVT::f32) {
8420 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8421 DCI.AddToWorklist(Val.getNode());
8423 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
8424 DCI.AddToWorklist(Val.getNode());
8427 N->getOperand(0), Val, N->getOperand(2),
8428 DAG.getValueType(N->getOperand(1).getValueType())
8431 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
8432 DAG.getVTList(MVT::Other), Ops,
8433 cast<StoreSDNode>(N)->getMemoryVT(),
8434 cast<StoreSDNode>(N)->getMemOperand());
8435 DCI.AddToWorklist(Val.getNode());
8439 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
8440 if (cast<StoreSDNode>(N)->isUnindexed() &&
8441 N->getOperand(1).getOpcode() == ISD::BSWAP &&
8442 N->getOperand(1).getNode()->hasOneUse() &&
8443 (N->getOperand(1).getValueType() == MVT::i32 ||
8444 N->getOperand(1).getValueType() == MVT::i16 ||
8445 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8446 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8447 N->getOperand(1).getValueType() == MVT::i64))) {
8448 SDValue BSwapOp = N->getOperand(1).getOperand(0);
8449 // Do an any-extend to 32-bits if this is a half-word input.
8450 if (BSwapOp.getValueType() == MVT::i16)
8451 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
8454 N->getOperand(0), BSwapOp, N->getOperand(2),
8455 DAG.getValueType(N->getOperand(1).getValueType())
8458 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
8459 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
8460 cast<StoreSDNode>(N)->getMemOperand());
8464 LoadSDNode *LD = cast<LoadSDNode>(N);
8465 EVT VT = LD->getValueType(0);
8466 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
8467 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
8468 if (ISD::isNON_EXTLoad(N) && VT.isVector() &&
8469 TM.getSubtarget<PPCSubtarget>().hasAltivec() &&
8470 (VT == MVT::v16i8 || VT == MVT::v8i16 ||
8471 VT == MVT::v4i32 || VT == MVT::v4f32) &&
8472 LD->getAlignment() < ABIAlignment) {
8473 // This is a type-legal unaligned Altivec load.
8474 SDValue Chain = LD->getChain();
8475 SDValue Ptr = LD->getBasePtr();
8476 bool isLittleEndian = Subtarget.isLittleEndian();
8478 // This implements the loading of unaligned vectors as described in
8479 // the venerable Apple Velocity Engine overview. Specifically:
8480 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
8481 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
8483 // The general idea is to expand a sequence of one or more unaligned
8484 // loads into an alignment-based permutation-control instruction (lvsl
8485 // or lvsr), a series of regular vector loads (which always truncate
8486 // their input address to an aligned address), and a series of
8487 // permutations. The results of these permutations are the requested
8488 // loaded values. The trick is that the last "extra" load is not taken
8489 // from the address you might suspect (sizeof(vector) bytes after the
8490 // last requested load), but rather sizeof(vector) - 1 bytes after the
8491 // last requested vector. The point of this is to avoid a page fault if
8492 // the base address happened to be aligned. This works because if the
8493 // base address is aligned, then adding less than a full vector length
8494 // will cause the last vector in the sequence to be (re)loaded.
8495 // Otherwise, the next vector will be fetched as you might suspect was
8498 // We might be able to reuse the permutation generation from
8499 // a different base address offset from this one by an aligned amount.
8500 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
8501 // optimization later.
8502 Intrinsic::ID Intr = (isLittleEndian ?
8503 Intrinsic::ppc_altivec_lvsr :
8504 Intrinsic::ppc_altivec_lvsl);
8505 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, MVT::v16i8);
8507 // Create the new MMO for the new base load. It is like the original MMO,
8508 // but represents an area in memory almost twice the vector size centered
8509 // on the original address. If the address is unaligned, we might start
8510 // reading up to (sizeof(vector)-1) bytes below the address of the
8511 // original unaligned load.
8512 MachineFunction &MF = DAG.getMachineFunction();
8513 MachineMemOperand *BaseMMO =
8514 MF.getMachineMemOperand(LD->getMemOperand(),
8515 -LD->getMemoryVT().getStoreSize()+1,
8516 2*LD->getMemoryVT().getStoreSize()-1);
8518 // Create the new base load.
8519 SDValue LDXIntID = DAG.getTargetConstant(Intrinsic::ppc_altivec_lvx,
8521 SDValue BaseLoadOps[] = { Chain, LDXIntID, Ptr };
8523 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
8524 DAG.getVTList(MVT::v4i32, MVT::Other),
8525 BaseLoadOps, MVT::v4i32, BaseMMO);
8527 // Note that the value of IncOffset (which is provided to the next
8528 // load's pointer info offset value, and thus used to calculate the
8529 // alignment), and the value of IncValue (which is actually used to
8530 // increment the pointer value) are different! This is because we
8531 // require the next load to appear to be aligned, even though it
8532 // is actually offset from the base pointer by a lesser amount.
8533 int IncOffset = VT.getSizeInBits() / 8;
8534 int IncValue = IncOffset;
8536 // Walk (both up and down) the chain looking for another load at the real
8537 // (aligned) offset (the alignment of the other load does not matter in
8538 // this case). If found, then do not use the offset reduction trick, as
8539 // that will prevent the loads from being later combined (as they would
8540 // otherwise be duplicates).
8541 if (!findConsecutiveLoad(LD, DAG))
8544 SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
8545 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
8547 MachineMemOperand *ExtraMMO =
8548 MF.getMachineMemOperand(LD->getMemOperand(),
8549 1, 2*LD->getMemoryVT().getStoreSize()-1);
8550 SDValue ExtraLoadOps[] = { Chain, LDXIntID, Ptr };
8552 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
8553 DAG.getVTList(MVT::v4i32, MVT::Other),
8554 ExtraLoadOps, MVT::v4i32, ExtraMMO);
8556 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
8557 BaseLoad.getValue(1), ExtraLoad.getValue(1));
8559 // Because vperm has a big-endian bias, we must reverse the order
8560 // of the input vectors and complement the permute control vector
8561 // when generating little endian code. We have already handled the
8562 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
8563 // and ExtraLoad here.
8566 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8567 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
8569 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8570 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
8572 if (VT != MVT::v4i32)
8573 Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm);
8575 // The output of the permutation is our loaded result, the TokenFactor is
8577 DCI.CombineTo(N, Perm, TF);
8578 return SDValue(N, 0);
8582 case ISD::INTRINSIC_WO_CHAIN: {
8583 bool isLittleEndian = Subtarget.isLittleEndian();
8584 Intrinsic::ID Intr = (isLittleEndian ?
8585 Intrinsic::ppc_altivec_lvsr :
8586 Intrinsic::ppc_altivec_lvsl);
8587 if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() == Intr &&
8588 N->getOperand(1)->getOpcode() == ISD::ADD) {
8589 SDValue Add = N->getOperand(1);
8591 if (DAG.MaskedValueIsZero(Add->getOperand(1),
8592 APInt::getAllOnesValue(4 /* 16 byte alignment */).zext(
8593 Add.getValueType().getScalarType().getSizeInBits()))) {
8594 SDNode *BasePtr = Add->getOperand(0).getNode();
8595 for (SDNode::use_iterator UI = BasePtr->use_begin(),
8596 UE = BasePtr->use_end(); UI != UE; ++UI) {
8597 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8598 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() ==
8600 // We've found another LVSL/LVSR, and this address is an aligned
8601 // multiple of that one. The results will be the same, so use the
8602 // one we've just found instead.
8604 return SDValue(*UI, 0);
8613 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
8614 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
8615 N->getOperand(0).hasOneUse() &&
8616 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
8617 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8618 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8619 N->getValueType(0) == MVT::i64))) {
8620 SDValue Load = N->getOperand(0);
8621 LoadSDNode *LD = cast<LoadSDNode>(Load);
8622 // Create the byte-swapping load.
8624 LD->getChain(), // Chain
8625 LD->getBasePtr(), // Ptr
8626 DAG.getValueType(N->getValueType(0)) // VT
8629 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
8630 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
8631 MVT::i64 : MVT::i32, MVT::Other),
8632 Ops, LD->getMemoryVT(), LD->getMemOperand());
8634 // If this is an i16 load, insert the truncate.
8635 SDValue ResVal = BSLoad;
8636 if (N->getValueType(0) == MVT::i16)
8637 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
8639 // First, combine the bswap away. This makes the value produced by the
8641 DCI.CombineTo(N, ResVal);
8643 // Next, combine the load away, we give it a bogus result value but a real
8644 // chain result. The result value is dead because the bswap is dead.
8645 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
8647 // Return N so it doesn't get rechecked!
8648 return SDValue(N, 0);
8652 case PPCISD::VCMP: {
8653 // If a VCMPo node already exists with exactly the same operands as this
8654 // node, use its result instead of this node (VCMPo computes both a CR6 and
8655 // a normal output).
8657 if (!N->getOperand(0).hasOneUse() &&
8658 !N->getOperand(1).hasOneUse() &&
8659 !N->getOperand(2).hasOneUse()) {
8661 // Scan all of the users of the LHS, looking for VCMPo's that match.
8662 SDNode *VCMPoNode = nullptr;
8664 SDNode *LHSN = N->getOperand(0).getNode();
8665 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
8667 if (UI->getOpcode() == PPCISD::VCMPo &&
8668 UI->getOperand(1) == N->getOperand(1) &&
8669 UI->getOperand(2) == N->getOperand(2) &&
8670 UI->getOperand(0) == N->getOperand(0)) {
8675 // If there is no VCMPo node, or if the flag value has a single use, don't
8677 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
8680 // Look at the (necessarily single) use of the flag value. If it has a
8681 // chain, this transformation is more complex. Note that multiple things
8682 // could use the value result, which we should ignore.
8683 SDNode *FlagUser = nullptr;
8684 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
8685 FlagUser == nullptr; ++UI) {
8686 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
8688 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
8689 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
8696 // If the user is a MFOCRF instruction, we know this is safe.
8697 // Otherwise we give up for right now.
8698 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
8699 return SDValue(VCMPoNode, 0);
8704 SDValue Cond = N->getOperand(1);
8705 SDValue Target = N->getOperand(2);
8707 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8708 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
8709 Intrinsic::ppc_is_decremented_ctr_nonzero) {
8711 // We now need to make the intrinsic dead (it cannot be instruction
8713 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
8714 assert(Cond.getNode()->hasOneUse() &&
8715 "Counter decrement has more than one use");
8717 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
8718 N->getOperand(0), Target);
8723 // If this is a branch on an altivec predicate comparison, lower this so
8724 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
8725 // lowering is done pre-legalize, because the legalizer lowers the predicate
8726 // compare down to code that is difficult to reassemble.
8727 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
8728 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
8730 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
8731 // value. If so, pass-through the AND to get to the intrinsic.
8732 if (LHS.getOpcode() == ISD::AND &&
8733 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8734 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
8735 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8736 isa<ConstantSDNode>(LHS.getOperand(1)) &&
8737 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
8739 LHS = LHS.getOperand(0);
8741 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8742 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
8743 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8744 isa<ConstantSDNode>(RHS)) {
8745 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
8746 "Counter decrement comparison is not EQ or NE");
8748 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8749 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
8750 (CC == ISD::SETNE && !Val);
8752 // We now need to make the intrinsic dead (it cannot be instruction
8754 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
8755 assert(LHS.getNode()->hasOneUse() &&
8756 "Counter decrement has more than one use");
8758 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
8759 N->getOperand(0), N->getOperand(4));
8765 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8766 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
8767 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
8768 assert(isDot && "Can't compare against a vector result!");
8770 // If this is a comparison against something other than 0/1, then we know
8771 // that the condition is never/always true.
8772 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8773 if (Val != 0 && Val != 1) {
8774 if (CC == ISD::SETEQ) // Cond never true, remove branch.
8775 return N->getOperand(0);
8776 // Always !=, turn it into an unconditional branch.
8777 return DAG.getNode(ISD::BR, dl, MVT::Other,
8778 N->getOperand(0), N->getOperand(4));
8781 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
8783 // Create the PPCISD altivec 'dot' comparison node.
8785 LHS.getOperand(2), // LHS of compare
8786 LHS.getOperand(3), // RHS of compare
8787 DAG.getConstant(CompareOpc, MVT::i32)
8789 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
8790 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
8792 // Unpack the result based on how the target uses it.
8793 PPC::Predicate CompOpc;
8794 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
8795 default: // Can't happen, don't crash on invalid number though.
8796 case 0: // Branch on the value of the EQ bit of CR6.
8797 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
8799 case 1: // Branch on the inverted value of the EQ bit of CR6.
8800 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
8802 case 2: // Branch on the value of the LT bit of CR6.
8803 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
8805 case 3: // Branch on the inverted value of the LT bit of CR6.
8806 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
8810 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
8811 DAG.getConstant(CompOpc, MVT::i32),
8812 DAG.getRegister(PPC::CR6, MVT::i32),
8813 N->getOperand(4), CompNode.getValue(1));
8822 //===----------------------------------------------------------------------===//
8823 // Inline Assembly Support
8824 //===----------------------------------------------------------------------===//
8826 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
8829 const SelectionDAG &DAG,
8830 unsigned Depth) const {
8831 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
8832 switch (Op.getOpcode()) {
8834 case PPCISD::LBRX: {
8835 // lhbrx is known to have the top bits cleared out.
8836 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
8837 KnownZero = 0xFFFF0000;
8840 case ISD::INTRINSIC_WO_CHAIN: {
8841 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
8843 case Intrinsic::ppc_altivec_vcmpbfp_p:
8844 case Intrinsic::ppc_altivec_vcmpeqfp_p:
8845 case Intrinsic::ppc_altivec_vcmpequb_p:
8846 case Intrinsic::ppc_altivec_vcmpequh_p:
8847 case Intrinsic::ppc_altivec_vcmpequw_p:
8848 case Intrinsic::ppc_altivec_vcmpgefp_p:
8849 case Intrinsic::ppc_altivec_vcmpgtfp_p:
8850 case Intrinsic::ppc_altivec_vcmpgtsb_p:
8851 case Intrinsic::ppc_altivec_vcmpgtsh_p:
8852 case Intrinsic::ppc_altivec_vcmpgtsw_p:
8853 case Intrinsic::ppc_altivec_vcmpgtub_p:
8854 case Intrinsic::ppc_altivec_vcmpgtuh_p:
8855 case Intrinsic::ppc_altivec_vcmpgtuw_p:
8856 KnownZero = ~1U; // All bits but the low one are known to be zero.
8864 /// getConstraintType - Given a constraint, return the type of
8865 /// constraint it is for this target.
8866 PPCTargetLowering::ConstraintType
8867 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
8868 if (Constraint.size() == 1) {
8869 switch (Constraint[0]) {
8876 return C_RegisterClass;
8878 // FIXME: While Z does indicate a memory constraint, it specifically
8879 // indicates an r+r address (used in conjunction with the 'y' modifier
8880 // in the replacement string). Currently, we're forcing the base
8881 // register to be r0 in the asm printer (which is interpreted as zero)
8882 // and forming the complete address in the second register. This is
8886 } else if (Constraint == "wc") { // individual CR bits.
8887 return C_RegisterClass;
8888 } else if (Constraint == "wa" || Constraint == "wd" ||
8889 Constraint == "wf" || Constraint == "ws") {
8890 return C_RegisterClass; // VSX registers.
8892 return TargetLowering::getConstraintType(Constraint);
8895 /// Examine constraint type and operand type and determine a weight value.
8896 /// This object must already have been set up with the operand type
8897 /// and the current alternative constraint selected.
8898 TargetLowering::ConstraintWeight
8899 PPCTargetLowering::getSingleConstraintMatchWeight(
8900 AsmOperandInfo &info, const char *constraint) const {
8901 ConstraintWeight weight = CW_Invalid;
8902 Value *CallOperandVal = info.CallOperandVal;
8903 // If we don't have a value, we can't do a match,
8904 // but allow it at the lowest weight.
8905 if (!CallOperandVal)
8907 Type *type = CallOperandVal->getType();
8909 // Look at the constraint type.
8910 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
8911 return CW_Register; // an individual CR bit.
8912 else if ((StringRef(constraint) == "wa" ||
8913 StringRef(constraint) == "wd" ||
8914 StringRef(constraint) == "wf") &&
8917 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
8920 switch (*constraint) {
8922 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
8925 if (type->isIntegerTy())
8926 weight = CW_Register;
8929 if (type->isFloatTy())
8930 weight = CW_Register;
8933 if (type->isDoubleTy())
8934 weight = CW_Register;
8937 if (type->isVectorTy())
8938 weight = CW_Register;
8941 weight = CW_Register;
8950 std::pair<unsigned, const TargetRegisterClass*>
8951 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
8953 if (Constraint.size() == 1) {
8954 // GCC RS6000 Constraint Letters
8955 switch (Constraint[0]) {
8957 if (VT == MVT::i64 && Subtarget.isPPC64())
8958 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
8959 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
8961 if (VT == MVT::i64 && Subtarget.isPPC64())
8962 return std::make_pair(0U, &PPC::G8RCRegClass);
8963 return std::make_pair(0U, &PPC::GPRCRegClass);
8965 if (VT == MVT::f32 || VT == MVT::i32)
8966 return std::make_pair(0U, &PPC::F4RCRegClass);
8967 if (VT == MVT::f64 || VT == MVT::i64)
8968 return std::make_pair(0U, &PPC::F8RCRegClass);
8971 return std::make_pair(0U, &PPC::VRRCRegClass);
8973 return std::make_pair(0U, &PPC::CRRCRegClass);
8975 } else if (Constraint == "wc") { // an individual CR bit.
8976 return std::make_pair(0U, &PPC::CRBITRCRegClass);
8977 } else if (Constraint == "wa" || Constraint == "wd" ||
8978 Constraint == "wf") {
8979 return std::make_pair(0U, &PPC::VSRCRegClass);
8980 } else if (Constraint == "ws") {
8981 return std::make_pair(0U, &PPC::VSFRCRegClass);
8984 std::pair<unsigned, const TargetRegisterClass*> R =
8985 TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
8987 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
8988 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
8989 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
8991 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
8992 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
8993 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
8994 PPC::GPRCRegClass.contains(R.first)) {
8995 const TargetRegisterInfo *TRI =
8996 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
8997 return std::make_pair(TRI->getMatchingSuperReg(R.first,
8998 PPC::sub_32, &PPC::G8RCRegClass),
8999 &PPC::G8RCRegClass);
9006 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
9007 /// vector. If it is invalid, don't add anything to Ops.
9008 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
9009 std::string &Constraint,
9010 std::vector<SDValue>&Ops,
9011 SelectionDAG &DAG) const {
9014 // Only support length 1 constraints.
9015 if (Constraint.length() > 1) return;
9017 char Letter = Constraint[0];
9028 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
9029 if (!CST) return; // Must be an immediate to match.
9030 unsigned Value = CST->getZExtValue();
9032 default: llvm_unreachable("Unknown constraint letter!");
9033 case 'I': // "I" is a signed 16-bit constant.
9034 if ((short)Value == (int)Value)
9035 Result = DAG.getTargetConstant(Value, Op.getValueType());
9037 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
9038 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
9039 if ((short)Value == 0)
9040 Result = DAG.getTargetConstant(Value, Op.getValueType());
9042 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
9043 if ((Value >> 16) == 0)
9044 Result = DAG.getTargetConstant(Value, Op.getValueType());
9046 case 'M': // "M" is a constant that is greater than 31.
9048 Result = DAG.getTargetConstant(Value, Op.getValueType());
9050 case 'N': // "N" is a positive constant that is an exact power of two.
9051 if ((int)Value > 0 && isPowerOf2_32(Value))
9052 Result = DAG.getTargetConstant(Value, Op.getValueType());
9054 case 'O': // "O" is the constant zero.
9056 Result = DAG.getTargetConstant(Value, Op.getValueType());
9058 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
9059 if ((short)-Value == (int)-Value)
9060 Result = DAG.getTargetConstant(Value, Op.getValueType());
9067 if (Result.getNode()) {
9068 Ops.push_back(Result);
9072 // Handle standard constraint letters.
9073 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
9076 // isLegalAddressingMode - Return true if the addressing mode represented
9077 // by AM is legal for this target, for a load/store of the specified type.
9078 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
9080 // FIXME: PPC does not allow r+i addressing modes for vectors!
9082 // PPC allows a sign-extended 16-bit immediate field.
9083 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
9086 // No global is ever allowed as a base.
9090 // PPC only support r+r,
9092 case 0: // "r+i" or just "i", depending on HasBaseReg.
9095 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
9097 // Otherwise we have r+r or r+i.
9100 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
9102 // Allow 2*r as r+r.
9105 // No other scales are supported.
9112 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
9113 SelectionDAG &DAG) const {
9114 MachineFunction &MF = DAG.getMachineFunction();
9115 MachineFrameInfo *MFI = MF.getFrameInfo();
9116 MFI->setReturnAddressIsTaken(true);
9118 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
9122 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9124 // Make sure the function does not optimize away the store of the RA to
9126 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
9127 FuncInfo->setLRStoreRequired();
9128 bool isPPC64 = Subtarget.isPPC64();
9129 bool isDarwinABI = Subtarget.isDarwinABI();
9132 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9135 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
9136 isPPC64? MVT::i64 : MVT::i32);
9137 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9138 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9140 MachinePointerInfo(), false, false, false, 0);
9143 // Just load the return address off the stack.
9144 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
9145 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9146 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9149 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
9150 SelectionDAG &DAG) const {
9152 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9154 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
9155 bool isPPC64 = PtrVT == MVT::i64;
9157 MachineFunction &MF = DAG.getMachineFunction();
9158 MachineFrameInfo *MFI = MF.getFrameInfo();
9159 MFI->setFrameAddressIsTaken(true);
9161 // Naked functions never have a frame pointer, and so we use r1. For all
9162 // other functions, this decision must be delayed until during PEI.
9164 if (MF.getFunction()->getAttributes().hasAttribute(
9165 AttributeSet::FunctionIndex, Attribute::Naked))
9166 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
9168 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
9170 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
9173 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
9174 FrameAddr, MachinePointerInfo(), false, false,
9179 // FIXME? Maybe this could be a TableGen attribute on some registers and
9180 // this table could be generated automatically from RegInfo.
9181 unsigned PPCTargetLowering::getRegisterByName(const char* RegName,
9183 bool isPPC64 = Subtarget.isPPC64();
9184 bool isDarwinABI = Subtarget.isDarwinABI();
9186 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
9187 (!isPPC64 && VT != MVT::i32))
9188 report_fatal_error("Invalid register global variable type");
9190 bool is64Bit = isPPC64 && VT == MVT::i64;
9191 unsigned Reg = StringSwitch<unsigned>(RegName)
9192 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
9193 .Case("r2", isDarwinABI ? 0 : (is64Bit ? PPC::X2 : PPC::R2))
9194 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
9195 (is64Bit ? PPC::X13 : PPC::R13))
9200 report_fatal_error("Invalid register name global variable");
9204 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
9205 // The PowerPC target isn't yet aware of offsets.
9209 bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
9211 unsigned Intrinsic) const {
9213 switch (Intrinsic) {
9214 case Intrinsic::ppc_altivec_lvx:
9215 case Intrinsic::ppc_altivec_lvxl:
9216 case Intrinsic::ppc_altivec_lvebx:
9217 case Intrinsic::ppc_altivec_lvehx:
9218 case Intrinsic::ppc_altivec_lvewx: {
9220 switch (Intrinsic) {
9221 case Intrinsic::ppc_altivec_lvebx:
9224 case Intrinsic::ppc_altivec_lvehx:
9227 case Intrinsic::ppc_altivec_lvewx:
9235 Info.opc = ISD::INTRINSIC_W_CHAIN;
9237 Info.ptrVal = I.getArgOperand(0);
9238 Info.offset = -VT.getStoreSize()+1;
9239 Info.size = 2*VT.getStoreSize()-1;
9242 Info.readMem = true;
9243 Info.writeMem = false;
9246 case Intrinsic::ppc_altivec_stvx:
9247 case Intrinsic::ppc_altivec_stvxl:
9248 case Intrinsic::ppc_altivec_stvebx:
9249 case Intrinsic::ppc_altivec_stvehx:
9250 case Intrinsic::ppc_altivec_stvewx: {
9252 switch (Intrinsic) {
9253 case Intrinsic::ppc_altivec_stvebx:
9256 case Intrinsic::ppc_altivec_stvehx:
9259 case Intrinsic::ppc_altivec_stvewx:
9267 Info.opc = ISD::INTRINSIC_VOID;
9269 Info.ptrVal = I.getArgOperand(1);
9270 Info.offset = -VT.getStoreSize()+1;
9271 Info.size = 2*VT.getStoreSize()-1;
9274 Info.readMem = false;
9275 Info.writeMem = true;
9285 /// getOptimalMemOpType - Returns the target specific optimal type for load
9286 /// and store operations as a result of memset, memcpy, and memmove
9287 /// lowering. If DstAlign is zero that means it's safe to destination
9288 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
9289 /// means there isn't a need to check it against alignment requirement,
9290 /// probably because the source does not need to be loaded. If 'IsMemset' is
9291 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
9292 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
9293 /// source is constant so it does not need to be loaded.
9294 /// It returns EVT::Other if the type should be determined using generic
9295 /// target-independent logic.
9296 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
9297 unsigned DstAlign, unsigned SrcAlign,
9298 bool IsMemset, bool ZeroMemset,
9300 MachineFunction &MF) const {
9301 if (Subtarget.isPPC64()) {
9308 /// \brief Returns true if it is beneficial to convert a load of a constant
9309 /// to just the constant itself.
9310 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
9312 assert(Ty->isIntegerTy());
9314 unsigned BitSize = Ty->getPrimitiveSizeInBits();
9315 if (BitSize == 0 || BitSize > 64)
9320 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
9321 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
9323 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
9324 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
9325 return NumBits1 == 64 && NumBits2 == 32;
9328 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
9329 if (!VT1.isInteger() || !VT2.isInteger())
9331 unsigned NumBits1 = VT1.getSizeInBits();
9332 unsigned NumBits2 = VT2.getSizeInBits();
9333 return NumBits1 == 64 && NumBits2 == 32;
9336 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
9337 return isInt<16>(Imm) || isUInt<16>(Imm);
9340 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
9341 return isInt<16>(Imm) || isUInt<16>(Imm);
9344 bool PPCTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
9348 if (DisablePPCUnaligned)
9351 // PowerPC supports unaligned memory access for simple non-vector types.
9352 // Although accessing unaligned addresses is not as efficient as accessing
9353 // aligned addresses, it is generally more efficient than manual expansion,
9354 // and generally only traps for software emulation when crossing page
9360 if (VT.getSimpleVT().isVector()) {
9361 if (Subtarget.hasVSX()) {
9362 if (VT != MVT::v2f64 && VT != MVT::v2i64)
9369 if (VT == MVT::ppcf128)
9378 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
9379 VT = VT.getScalarType();
9384 switch (VT.getSimpleVT().SimpleTy) {
9396 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
9397 EVT VT , unsigned DefinedValues) const {
9398 if (VT == MVT::v2i64)
9401 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
9404 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
9405 if (DisableILPPref || Subtarget.enableMachineScheduler())
9406 return TargetLowering::getSchedulingPreference(N);
9411 // Create a fast isel object.
9413 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
9414 const TargetLibraryInfo *LibInfo) const {
9415 return PPC::createFastISel(FuncInfo, LibInfo);