1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPerfectShuffle.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCTargetObjectFile.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28 #include "llvm/IR/CallingConv.h"
29 #include "llvm/IR/Constants.h"
30 #include "llvm/IR/DerivedTypes.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/Intrinsics.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/Target/TargetOptions.h"
40 static bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
41 CCValAssign::LocInfo &LocInfo,
42 ISD::ArgFlagsTy &ArgFlags,
44 static bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
46 CCValAssign::LocInfo &LocInfo,
47 ISD::ArgFlagsTy &ArgFlags,
49 static bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
51 CCValAssign::LocInfo &LocInfo,
52 ISD::ArgFlagsTy &ArgFlags,
55 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
56 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
58 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
59 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
61 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
62 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
64 static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) {
65 if (TM.getSubtargetImpl()->isDarwin())
66 return new TargetLoweringObjectFileMachO();
68 if (TM.getSubtargetImpl()->isSVR4ABI())
69 return new PPC64LinuxTargetObjectFile();
71 return new TargetLoweringObjectFileELF();
74 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
75 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) {
76 const PPCSubtarget *Subtarget = &TM.getSubtarget<PPCSubtarget>();
77 PPCRegInfo = TM.getRegisterInfo();
78 PPCII = TM.getInstrInfo();
82 // Use _setjmp/_longjmp instead of setjmp/longjmp.
83 setUseUnderscoreSetJmp(true);
84 setUseUnderscoreLongJmp(true);
86 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
87 // arguments are at least 4/8 bytes aligned.
88 bool isPPC64 = Subtarget->isPPC64();
89 setMinStackArgumentAlignment(isPPC64 ? 8:4);
91 // Set up the register classes.
92 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
93 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
94 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
96 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
97 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
98 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
100 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
102 // PowerPC has pre-inc load and store's.
103 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
104 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
105 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
106 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
107 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
108 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
109 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
110 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
111 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
112 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
114 // This is used in the ppcf128->int sequence. Note it has different semantics
115 // from FP_ROUND: that rounds to nearest, this rounds to zero.
116 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
118 // We do not currently implement these libm ops for PowerPC.
119 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
120 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
121 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
122 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
123 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
124 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
126 // PowerPC has no SREM/UREM instructions
127 setOperationAction(ISD::SREM, MVT::i32, Expand);
128 setOperationAction(ISD::UREM, MVT::i32, Expand);
129 setOperationAction(ISD::SREM, MVT::i64, Expand);
130 setOperationAction(ISD::UREM, MVT::i64, Expand);
132 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
133 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
134 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
135 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
136 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
137 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
138 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
139 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
140 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
142 // We don't support sin/cos/sqrt/fmod/pow
143 setOperationAction(ISD::FSIN , MVT::f64, Expand);
144 setOperationAction(ISD::FCOS , MVT::f64, Expand);
145 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
146 setOperationAction(ISD::FREM , MVT::f64, Expand);
147 setOperationAction(ISD::FPOW , MVT::f64, Expand);
148 setOperationAction(ISD::FMA , MVT::f64, Legal);
149 setOperationAction(ISD::FSIN , MVT::f32, Expand);
150 setOperationAction(ISD::FCOS , MVT::f32, Expand);
151 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
152 setOperationAction(ISD::FREM , MVT::f32, Expand);
153 setOperationAction(ISD::FPOW , MVT::f32, Expand);
154 setOperationAction(ISD::FMA , MVT::f32, Legal);
156 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
158 // If we're enabling GP optimizations, use hardware square root
159 if (!Subtarget->hasFSQRT() &&
160 !(TM.Options.UnsafeFPMath &&
161 Subtarget->hasFRSQRTE() && Subtarget->hasFRE()))
162 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
164 if (!Subtarget->hasFSQRT() &&
165 !(TM.Options.UnsafeFPMath &&
166 Subtarget->hasFRSQRTES() && Subtarget->hasFRES()))
167 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
169 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
170 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
172 if (Subtarget->hasFPRND()) {
173 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
174 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
175 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
177 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
178 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
179 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
181 // frin does not implement "ties to even." Thus, this is safe only in
183 if (TM.Options.UnsafeFPMath) {
184 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
185 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
187 // These need to set FE_INEXACT, and use a custom inserter.
188 setOperationAction(ISD::FRINT, MVT::f64, Legal);
189 setOperationAction(ISD::FRINT, MVT::f32, Legal);
193 // PowerPC does not have BSWAP, CTPOP or CTTZ
194 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
195 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
196 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
197 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
198 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
199 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
200 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
201 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
203 if (Subtarget->hasPOPCNTD()) {
204 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
205 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
207 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
208 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
211 // PowerPC does not have ROTR
212 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
213 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
215 // PowerPC does not have Select
216 setOperationAction(ISD::SELECT, MVT::i32, Expand);
217 setOperationAction(ISD::SELECT, MVT::i64, Expand);
218 setOperationAction(ISD::SELECT, MVT::f32, Expand);
219 setOperationAction(ISD::SELECT, MVT::f64, Expand);
221 // PowerPC wants to turn select_cc of FP into fsel when possible.
222 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
223 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
225 // PowerPC wants to optimize integer setcc a bit
226 setOperationAction(ISD::SETCC, MVT::i32, Custom);
228 // PowerPC does not have BRCOND which requires SetCC
229 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
231 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
233 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
234 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
236 // PowerPC does not have [U|S]INT_TO_FP
237 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
238 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
240 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
241 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
242 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
243 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
245 // We cannot sextinreg(i1). Expand to shifts.
246 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
248 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
249 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
250 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
251 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
253 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
254 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
255 // support continuation, user-level threading, and etc.. As a result, no
256 // other SjLj exception interfaces are implemented and please don't build
257 // your own exception handling based on them.
258 // LLVM/Clang supports zero-cost DWARF exception handling.
259 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
260 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
262 // We want to legalize GlobalAddress and ConstantPool nodes into the
263 // appropriate instructions to materialize the address.
264 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
265 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
266 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
267 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
268 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
269 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
270 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
271 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
272 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
273 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
276 setOperationAction(ISD::TRAP, MVT::Other, Legal);
278 // TRAMPOLINE is custom lowered.
279 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
280 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
282 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
283 setOperationAction(ISD::VASTART , MVT::Other, Custom);
285 if (Subtarget->isSVR4ABI()) {
287 // VAARG always uses double-word chunks, so promote anything smaller.
288 setOperationAction(ISD::VAARG, MVT::i1, Promote);
289 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
290 setOperationAction(ISD::VAARG, MVT::i8, Promote);
291 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
292 setOperationAction(ISD::VAARG, MVT::i16, Promote);
293 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
294 setOperationAction(ISD::VAARG, MVT::i32, Promote);
295 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
296 setOperationAction(ISD::VAARG, MVT::Other, Expand);
298 // VAARG is custom lowered with the 32-bit SVR4 ABI.
299 setOperationAction(ISD::VAARG, MVT::Other, Custom);
300 setOperationAction(ISD::VAARG, MVT::i64, Custom);
303 setOperationAction(ISD::VAARG, MVT::Other, Expand);
305 // Use the default implementation.
306 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
307 setOperationAction(ISD::VAEND , MVT::Other, Expand);
308 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
309 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
310 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
311 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
313 // We want to custom lower some of our intrinsics.
314 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
316 // Comparisons that require checking two conditions.
317 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
318 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
319 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
320 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
321 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
322 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
323 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
324 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
325 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
326 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
327 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
328 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
330 if (Subtarget->has64BitSupport()) {
331 // They also have instructions for converting between i64 and fp.
332 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
333 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
334 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
335 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
336 // This is just the low 32 bits of a (signed) fp->i64 conversion.
337 // We cannot do this with Promote because i64 is not a legal type.
338 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
340 if (PPCSubTarget.hasLFIWAX() || Subtarget->isPPC64())
341 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
343 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
344 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
347 // With the instructions enabled under FPCVT, we can do everything.
348 if (PPCSubTarget.hasFPCVT()) {
349 if (Subtarget->has64BitSupport()) {
350 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
351 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
352 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
353 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
356 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
357 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
358 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
359 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
362 if (Subtarget->use64BitRegs()) {
363 // 64-bit PowerPC implementations can support i64 types directly
364 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
365 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
366 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
367 // 64-bit PowerPC wants to expand i128 shifts itself.
368 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
369 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
370 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
372 // 32-bit PowerPC wants to expand i64 shifts itself.
373 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
374 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
375 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
378 if (Subtarget->hasAltivec()) {
379 // First set operation action for all vector types to expand. Then we
380 // will selectively turn on ones that can be effectively codegen'd.
381 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
382 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
383 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
385 // add/sub are legal for all supported vector VT's.
386 setOperationAction(ISD::ADD , VT, Legal);
387 setOperationAction(ISD::SUB , VT, Legal);
389 // We promote all shuffles to v16i8.
390 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
391 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
393 // We promote all non-typed operations to v4i32.
394 setOperationAction(ISD::AND , VT, Promote);
395 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
396 setOperationAction(ISD::OR , VT, Promote);
397 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
398 setOperationAction(ISD::XOR , VT, Promote);
399 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
400 setOperationAction(ISD::LOAD , VT, Promote);
401 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
402 setOperationAction(ISD::SELECT, VT, Promote);
403 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
404 setOperationAction(ISD::STORE, VT, Promote);
405 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
407 // No other operations are legal.
408 setOperationAction(ISD::MUL , VT, Expand);
409 setOperationAction(ISD::SDIV, VT, Expand);
410 setOperationAction(ISD::SREM, VT, Expand);
411 setOperationAction(ISD::UDIV, VT, Expand);
412 setOperationAction(ISD::UREM, VT, Expand);
413 setOperationAction(ISD::FDIV, VT, Expand);
414 setOperationAction(ISD::FNEG, VT, Expand);
415 setOperationAction(ISD::FSQRT, VT, Expand);
416 setOperationAction(ISD::FLOG, VT, Expand);
417 setOperationAction(ISD::FLOG10, VT, Expand);
418 setOperationAction(ISD::FLOG2, VT, Expand);
419 setOperationAction(ISD::FEXP, VT, Expand);
420 setOperationAction(ISD::FEXP2, VT, Expand);
421 setOperationAction(ISD::FSIN, VT, Expand);
422 setOperationAction(ISD::FCOS, VT, Expand);
423 setOperationAction(ISD::FABS, VT, Expand);
424 setOperationAction(ISD::FPOWI, VT, Expand);
425 setOperationAction(ISD::FFLOOR, VT, Expand);
426 setOperationAction(ISD::FCEIL, VT, Expand);
427 setOperationAction(ISD::FTRUNC, VT, Expand);
428 setOperationAction(ISD::FRINT, VT, Expand);
429 setOperationAction(ISD::FNEARBYINT, VT, Expand);
430 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
431 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
432 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
433 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
434 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
435 setOperationAction(ISD::UDIVREM, VT, Expand);
436 setOperationAction(ISD::SDIVREM, VT, Expand);
437 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
438 setOperationAction(ISD::FPOW, VT, Expand);
439 setOperationAction(ISD::CTPOP, VT, Expand);
440 setOperationAction(ISD::CTLZ, VT, Expand);
441 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
442 setOperationAction(ISD::CTTZ, VT, Expand);
443 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
444 setOperationAction(ISD::VSELECT, VT, Expand);
445 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
447 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
448 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
449 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
450 setTruncStoreAction(VT, InnerVT, Expand);
452 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
453 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
454 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
457 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
458 // with merges, splats, etc.
459 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
461 setOperationAction(ISD::AND , MVT::v4i32, Legal);
462 setOperationAction(ISD::OR , MVT::v4i32, Legal);
463 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
464 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
465 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
466 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
467 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
468 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
469 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
470 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
471 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
472 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
473 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
474 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
476 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
477 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
478 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
479 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
481 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
482 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
484 if (TM.Options.UnsafeFPMath) {
485 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
486 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
489 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
490 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
491 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
493 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
494 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
496 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
497 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
498 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
499 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
501 // Altivec does not contain unordered floating-point compare instructions
502 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
503 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
504 setCondCodeAction(ISD::SETUGT, MVT::v4f32, Expand);
505 setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand);
506 setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand);
507 setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand);
510 if (Subtarget->has64BitSupport()) {
511 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
512 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
515 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
516 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
517 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
518 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
520 setBooleanContents(ZeroOrOneBooleanContent);
521 // Altivec instructions set fields to all zeros or all ones.
522 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
525 setStackPointerRegisterToSaveRestore(PPC::X1);
526 setExceptionPointerRegister(PPC::X3);
527 setExceptionSelectorRegister(PPC::X4);
529 setStackPointerRegisterToSaveRestore(PPC::R1);
530 setExceptionPointerRegister(PPC::R3);
531 setExceptionSelectorRegister(PPC::R4);
534 // We have target-specific dag combine patterns for the following nodes:
535 setTargetDAGCombine(ISD::SINT_TO_FP);
536 setTargetDAGCombine(ISD::STORE);
537 setTargetDAGCombine(ISD::BR_CC);
538 setTargetDAGCombine(ISD::BSWAP);
540 // Use reciprocal estimates.
541 if (TM.Options.UnsafeFPMath) {
542 setTargetDAGCombine(ISD::FDIV);
543 setTargetDAGCombine(ISD::FSQRT);
546 // Darwin long double math library functions have $LDBL128 appended.
547 if (Subtarget->isDarwin()) {
548 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
549 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
550 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
551 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
552 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
553 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
554 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
555 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
556 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
557 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
560 setMinFunctionAlignment(2);
561 if (PPCSubTarget.isDarwin())
562 setPrefFunctionAlignment(4);
564 if (isPPC64 && Subtarget->isJITCodeModel())
565 // Temporary workaround for the inability of PPC64 JIT to handle jump
567 setSupportJumpTables(false);
569 setInsertFencesForAtomic(true);
571 setSchedulingPreference(Sched::Hybrid);
573 computeRegisterProperties();
575 // The Freescale cores does better with aggressive inlining of memcpy and
576 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores).
577 if (Subtarget->getDarwinDirective() == PPC::DIR_E500mc ||
578 Subtarget->getDarwinDirective() == PPC::DIR_E5500) {
579 MaxStoresPerMemset = 32;
580 MaxStoresPerMemsetOptSize = 16;
581 MaxStoresPerMemcpy = 32;
582 MaxStoresPerMemcpyOptSize = 8;
583 MaxStoresPerMemmove = 32;
584 MaxStoresPerMemmoveOptSize = 8;
586 setPrefFunctionAlignment(4);
590 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
591 /// function arguments in the caller parameter area.
592 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
593 const TargetMachine &TM = getTargetMachine();
594 // Darwin passes everything on 4 byte boundary.
595 if (TM.getSubtarget<PPCSubtarget>().isDarwin())
598 // 16byte and wider vectors are passed on 16byte boundary.
599 if (VectorType *VTy = dyn_cast<VectorType>(Ty))
600 if (VTy->getBitWidth() >= 128)
603 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
604 if (PPCSubTarget.isPPC64())
610 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
613 case PPCISD::FSEL: return "PPCISD::FSEL";
614 case PPCISD::FCFID: return "PPCISD::FCFID";
615 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
616 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
617 case PPCISD::FRE: return "PPCISD::FRE";
618 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
619 case PPCISD::STFIWX: return "PPCISD::STFIWX";
620 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
621 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
622 case PPCISD::VPERM: return "PPCISD::VPERM";
623 case PPCISD::Hi: return "PPCISD::Hi";
624 case PPCISD::Lo: return "PPCISD::Lo";
625 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
626 case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE";
627 case PPCISD::LOAD: return "PPCISD::LOAD";
628 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
629 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
630 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
631 case PPCISD::SRL: return "PPCISD::SRL";
632 case PPCISD::SRA: return "PPCISD::SRA";
633 case PPCISD::SHL: return "PPCISD::SHL";
634 case PPCISD::CALL: return "PPCISD::CALL";
635 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
636 case PPCISD::MTCTR: return "PPCISD::MTCTR";
637 case PPCISD::BCTRL: return "PPCISD::BCTRL";
638 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
639 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
640 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
641 case PPCISD::MFCR: return "PPCISD::MFCR";
642 case PPCISD::VCMP: return "PPCISD::VCMP";
643 case PPCISD::VCMPo: return "PPCISD::VCMPo";
644 case PPCISD::LBRX: return "PPCISD::LBRX";
645 case PPCISD::STBRX: return "PPCISD::STBRX";
646 case PPCISD::LARX: return "PPCISD::LARX";
647 case PPCISD::STCX: return "PPCISD::STCX";
648 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
649 case PPCISD::MFFS: return "PPCISD::MFFS";
650 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
651 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
652 case PPCISD::CR6SET: return "PPCISD::CR6SET";
653 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
654 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
655 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
656 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
657 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
658 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
659 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
660 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
661 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
662 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
663 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
664 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
665 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
666 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
667 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
668 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
669 case PPCISD::SC: return "PPCISD::SC";
673 EVT PPCTargetLowering::getSetCCResultType(EVT VT) const {
676 return VT.changeVectorElementTypeToInteger();
679 //===----------------------------------------------------------------------===//
680 // Node matching predicates, for use by the tblgen matching code.
681 //===----------------------------------------------------------------------===//
683 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
684 static bool isFloatingPointZero(SDValue Op) {
685 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
686 return CFP->getValueAPF().isZero();
687 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
688 // Maybe this has already been legalized into the constant pool?
689 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
690 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
691 return CFP->getValueAPF().isZero();
696 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
697 /// true if Op is undef or if it matches the specified value.
698 static bool isConstantOrUndef(int Op, int Val) {
699 return Op < 0 || Op == Val;
702 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
703 /// VPKUHUM instruction.
704 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
706 for (unsigned i = 0; i != 16; ++i)
707 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
710 for (unsigned i = 0; i != 8; ++i)
711 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) ||
712 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1))
718 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
719 /// VPKUWUM instruction.
720 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
722 for (unsigned i = 0; i != 16; i += 2)
723 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
724 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
727 for (unsigned i = 0; i != 8; i += 2)
728 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
729 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) ||
730 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) ||
731 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3))
737 /// isVMerge - Common function, used to match vmrg* shuffles.
739 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
740 unsigned LHSStart, unsigned RHSStart) {
741 assert(N->getValueType(0) == MVT::v16i8 &&
742 "PPC only supports shuffles by bytes!");
743 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
744 "Unsupported merge size!");
746 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
747 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
748 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
749 LHSStart+j+i*UnitSize) ||
750 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
751 RHSStart+j+i*UnitSize))
757 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
758 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
759 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
762 return isVMerge(N, UnitSize, 8, 24);
763 return isVMerge(N, UnitSize, 8, 8);
766 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
767 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
768 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
771 return isVMerge(N, UnitSize, 0, 16);
772 return isVMerge(N, UnitSize, 0, 0);
776 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
777 /// amount, otherwise return -1.
778 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
779 assert(N->getValueType(0) == MVT::v16i8 &&
780 "PPC only supports shuffles by bytes!");
782 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
784 // Find the first non-undef value in the shuffle mask.
786 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
789 if (i == 16) return -1; // all undef.
791 // Otherwise, check to see if the rest of the elements are consecutively
792 // numbered from this value.
793 unsigned ShiftAmt = SVOp->getMaskElt(i);
794 if (ShiftAmt < i) return -1;
798 // Check the rest of the elements to see if they are consecutive.
799 for (++i; i != 16; ++i)
800 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
803 // Check the rest of the elements to see if they are consecutive.
804 for (++i; i != 16; ++i)
805 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
811 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
812 /// specifies a splat of a single element that is suitable for input to
813 /// VSPLTB/VSPLTH/VSPLTW.
814 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
815 assert(N->getValueType(0) == MVT::v16i8 &&
816 (EltSize == 1 || EltSize == 2 || EltSize == 4));
818 // This is a splat operation if each element of the permute is the same, and
819 // if the value doesn't reference the second vector.
820 unsigned ElementBase = N->getMaskElt(0);
822 // FIXME: Handle UNDEF elements too!
823 if (ElementBase >= 16)
826 // Check that the indices are consecutive, in the case of a multi-byte element
827 // splatted with a v16i8 mask.
828 for (unsigned i = 1; i != EltSize; ++i)
829 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
832 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
833 if (N->getMaskElt(i) < 0) continue;
834 for (unsigned j = 0; j != EltSize; ++j)
835 if (N->getMaskElt(i+j) != N->getMaskElt(j))
841 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
843 bool PPC::isAllNegativeZeroVector(SDNode *N) {
844 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
846 APInt APVal, APUndef;
850 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
851 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
852 return CFP->getValueAPF().isNegZero();
857 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
858 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
859 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
860 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
861 assert(isSplatShuffleMask(SVOp, EltSize));
862 return SVOp->getMaskElt(0) / EltSize;
865 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
866 /// by using a vspltis[bhw] instruction of the specified element size, return
867 /// the constant being splatted. The ByteSize field indicates the number of
868 /// bytes of each element [124] -> [bhw].
869 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
872 // If ByteSize of the splat is bigger than the element size of the
873 // build_vector, then we have a case where we are checking for a splat where
874 // multiple elements of the buildvector are folded together into a single
875 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
876 unsigned EltSize = 16/N->getNumOperands();
877 if (EltSize < ByteSize) {
878 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
879 SDValue UniquedVals[4];
880 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
882 // See if all of the elements in the buildvector agree across.
883 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
884 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
885 // If the element isn't a constant, bail fully out.
886 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
889 if (UniquedVals[i&(Multiple-1)].getNode() == 0)
890 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
891 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
892 return SDValue(); // no match.
895 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
896 // either constant or undef values that are identical for each chunk. See
897 // if these chunks can form into a larger vspltis*.
899 // Check to see if all of the leading entries are either 0 or -1. If
900 // neither, then this won't fit into the immediate field.
901 bool LeadingZero = true;
902 bool LeadingOnes = true;
903 for (unsigned i = 0; i != Multiple-1; ++i) {
904 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs.
906 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
907 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
909 // Finally, check the least significant entry.
911 if (UniquedVals[Multiple-1].getNode() == 0)
912 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
913 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
915 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
918 if (UniquedVals[Multiple-1].getNode() == 0)
919 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
920 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
921 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
922 return DAG.getTargetConstant(Val, MVT::i32);
928 // Check to see if this buildvec has a single non-undef value in its elements.
929 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
930 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
931 if (OpVal.getNode() == 0)
932 OpVal = N->getOperand(i);
933 else if (OpVal != N->getOperand(i))
937 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def.
939 unsigned ValSizeInBytes = EltSize;
941 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
942 Value = CN->getZExtValue();
943 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
944 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
945 Value = FloatToBits(CN->getValueAPF().convertToFloat());
948 // If the splat value is larger than the element value, then we can never do
949 // this splat. The only case that we could fit the replicated bits into our
950 // immediate field for would be zero, and we prefer to use vxor for it.
951 if (ValSizeInBytes < ByteSize) return SDValue();
953 // If the element value is larger than the splat value, cut it in half and
954 // check to see if the two halves are equal. Continue doing this until we
955 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
956 while (ValSizeInBytes > ByteSize) {
957 ValSizeInBytes >>= 1;
959 // If the top half equals the bottom half, we're still ok.
960 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
961 (Value & ((1 << (8*ValSizeInBytes))-1)))
965 // Properly sign extend the value.
966 int MaskVal = SignExtend32(Value, ByteSize * 8);
968 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
969 if (MaskVal == 0) return SDValue();
971 // Finally, if this value fits in a 5 bit sext field, return it
972 if (SignExtend32<5>(MaskVal) == MaskVal)
973 return DAG.getTargetConstant(MaskVal, MVT::i32);
977 //===----------------------------------------------------------------------===//
978 // Addressing Mode Selection
979 //===----------------------------------------------------------------------===//
981 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
982 /// or 64-bit immediate, and if the value can be accurately represented as a
983 /// sign extension from a 16-bit value. If so, this returns true and the
985 static bool isIntS16Immediate(SDNode *N, short &Imm) {
986 if (N->getOpcode() != ISD::Constant)
989 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
990 if (N->getValueType(0) == MVT::i32)
991 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
993 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
995 static bool isIntS16Immediate(SDValue Op, short &Imm) {
996 return isIntS16Immediate(Op.getNode(), Imm);
1000 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1001 /// can be represented as an indexed [r+r] operation. Returns false if it
1002 /// can be more efficiently represented with [r+imm].
1003 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1005 SelectionDAG &DAG) const {
1007 if (N.getOpcode() == ISD::ADD) {
1008 if (isIntS16Immediate(N.getOperand(1), imm))
1009 return false; // r+i
1010 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1011 return false; // r+i
1013 Base = N.getOperand(0);
1014 Index = N.getOperand(1);
1016 } else if (N.getOpcode() == ISD::OR) {
1017 if (isIntS16Immediate(N.getOperand(1), imm))
1018 return false; // r+i can fold it if we can.
1020 // If this is an or of disjoint bitfields, we can codegen this as an add
1021 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1023 APInt LHSKnownZero, LHSKnownOne;
1024 APInt RHSKnownZero, RHSKnownOne;
1025 DAG.ComputeMaskedBits(N.getOperand(0),
1026 LHSKnownZero, LHSKnownOne);
1028 if (LHSKnownZero.getBoolValue()) {
1029 DAG.ComputeMaskedBits(N.getOperand(1),
1030 RHSKnownZero, RHSKnownOne);
1031 // If all of the bits are known zero on the LHS or RHS, the add won't
1033 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1034 Base = N.getOperand(0);
1035 Index = N.getOperand(1);
1044 /// Returns true if the address N can be represented by a base register plus
1045 /// a signed 16-bit displacement [r+imm], and if it is not better
1046 /// represented as reg+reg.
1047 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1049 SelectionDAG &DAG) const {
1050 // FIXME dl should come from parent load or store, not from address
1051 DebugLoc dl = N.getDebugLoc();
1052 // If this can be more profitably realized as r+r, fail.
1053 if (SelectAddressRegReg(N, Disp, Base, DAG))
1056 if (N.getOpcode() == ISD::ADD) {
1058 if (isIntS16Immediate(N.getOperand(1), imm)) {
1059 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
1060 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1061 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1063 Base = N.getOperand(0);
1065 return true; // [r+i]
1066 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1067 // Match LOAD (ADD (X, Lo(G))).
1068 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1069 && "Cannot handle constant offsets yet!");
1070 Disp = N.getOperand(1).getOperand(0); // The global address.
1071 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1072 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1073 Disp.getOpcode() == ISD::TargetConstantPool ||
1074 Disp.getOpcode() == ISD::TargetJumpTable);
1075 Base = N.getOperand(0);
1076 return true; // [&g+r]
1078 } else if (N.getOpcode() == ISD::OR) {
1080 if (isIntS16Immediate(N.getOperand(1), imm)) {
1081 // If this is an or of disjoint bitfields, we can codegen this as an add
1082 // (for better address arithmetic) if the LHS and RHS of the OR are
1083 // provably disjoint.
1084 APInt LHSKnownZero, LHSKnownOne;
1085 DAG.ComputeMaskedBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1087 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1088 // If all of the bits are known zero on the LHS or RHS, the add won't
1090 Base = N.getOperand(0);
1091 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
1095 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1096 // Loading from a constant address.
1098 // If this address fits entirely in a 16-bit sext immediate field, codegen
1101 if (isIntS16Immediate(CN, Imm)) {
1102 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1103 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1104 CN->getValueType(0));
1108 // Handle 32-bit sext immediates with LIS + addr mode.
1109 if (CN->getValueType(0) == MVT::i32 ||
1110 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
1111 int Addr = (int)CN->getZExtValue();
1113 // Otherwise, break this down into an LIS + disp.
1114 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1116 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1117 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1118 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1123 Disp = DAG.getTargetConstant(0, getPointerTy());
1124 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
1125 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1128 return true; // [r+0]
1131 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1132 /// represented as an indexed [r+r] operation.
1133 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1135 SelectionDAG &DAG) const {
1136 // Check to see if we can easily represent this as an [r+r] address. This
1137 // will fail if it thinks that the address is more profitably represented as
1138 // reg+imm, e.g. where imm = 0.
1139 if (SelectAddressRegReg(N, Base, Index, DAG))
1142 // If the operand is an addition, always emit this as [r+r], since this is
1143 // better (for code size, and execution, as the memop does the add for free)
1144 // than emitting an explicit add.
1145 if (N.getOpcode() == ISD::ADD) {
1146 Base = N.getOperand(0);
1147 Index = N.getOperand(1);
1151 // Otherwise, do it the hard way, using R0 as the base register.
1152 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1158 /// SelectAddressRegImmShift - Returns true if the address N can be
1159 /// represented by a base register plus a signed 14-bit displacement
1160 /// [r+imm*4]. Suitable for use by STD and friends.
1161 bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp,
1163 SelectionDAG &DAG) const {
1164 // FIXME dl should come from the parent load or store, not the address
1165 DebugLoc dl = N.getDebugLoc();
1166 // If this can be more profitably realized as r+r, fail.
1167 if (SelectAddressRegReg(N, Disp, Base, DAG))
1170 if (N.getOpcode() == ISD::ADD) {
1172 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
1173 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
1174 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1175 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1177 Base = N.getOperand(0);
1179 return true; // [r+i]
1180 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1181 // Match LOAD (ADD (X, Lo(G))).
1182 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1183 && "Cannot handle constant offsets yet!");
1184 Disp = N.getOperand(1).getOperand(0); // The global address.
1185 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1186 Disp.getOpcode() == ISD::TargetConstantPool ||
1187 Disp.getOpcode() == ISD::TargetJumpTable);
1188 Base = N.getOperand(0);
1189 return true; // [&g+r]
1191 } else if (N.getOpcode() == ISD::OR) {
1193 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
1194 // If this is an or of disjoint bitfields, we can codegen this as an add
1195 // (for better address arithmetic) if the LHS and RHS of the OR are
1196 // provably disjoint.
1197 APInt LHSKnownZero, LHSKnownOne;
1198 DAG.ComputeMaskedBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1199 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1200 // If all of the bits are known zero on the LHS or RHS, the add won't
1202 Base = N.getOperand(0);
1203 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
1207 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1208 // Loading from a constant address. Verify low two bits are clear.
1209 if ((CN->getZExtValue() & 3) == 0) {
1210 // If this address fits entirely in a 14-bit sext immediate field, codegen
1213 if (isIntS16Immediate(CN, Imm)) {
1214 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
1215 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1216 CN->getValueType(0));
1220 // Fold the low-part of 32-bit absolute addresses into addr mode.
1221 if (CN->getValueType(0) == MVT::i32 ||
1222 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
1223 int Addr = (int)CN->getZExtValue();
1225 // Otherwise, break this down into an LIS + disp.
1226 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
1227 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
1228 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1229 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base),0);
1235 Disp = DAG.getTargetConstant(0, getPointerTy());
1236 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
1237 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1240 return true; // [r+0]
1244 /// getPreIndexedAddressParts - returns true by value, base pointer and
1245 /// offset pointer and addressing mode by reference if the node's address
1246 /// can be legally represented as pre-indexed load / store address.
1247 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1249 ISD::MemIndexedMode &AM,
1250 SelectionDAG &DAG) const {
1251 if (DisablePPCPreinc) return false;
1257 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1258 Ptr = LD->getBasePtr();
1259 VT = LD->getMemoryVT();
1260 Alignment = LD->getAlignment();
1261 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1262 Ptr = ST->getBasePtr();
1263 VT = ST->getMemoryVT();
1264 Alignment = ST->getAlignment();
1269 // PowerPC doesn't have preinc load/store instructions for vectors.
1273 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1275 // Common code will reject creating a pre-inc form if the base pointer
1276 // is a frame index, or if N is a store and the base pointer is either
1277 // the same as or a predecessor of the value being stored. Check for
1278 // those situations here, and try with swapped Base/Offset instead.
1281 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1284 SDValue Val = cast<StoreSDNode>(N)->getValue();
1285 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1290 std::swap(Base, Offset);
1296 // LDU/STU use reg+imm*4, others use reg+imm.
1297 if (VT != MVT::i64) {
1299 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
1302 // LDU/STU need an address with at least 4-byte alignment.
1307 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
1311 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1312 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1313 // sext i32 to i64 when addr mode is r+i.
1314 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1315 LD->getExtensionType() == ISD::SEXTLOAD &&
1316 isa<ConstantSDNode>(Offset))
1324 //===----------------------------------------------------------------------===//
1325 // LowerOperation implementation
1326 //===----------------------------------------------------------------------===//
1328 /// GetLabelAccessInfo - Return true if we should reference labels using a
1329 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1330 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1331 unsigned &LoOpFlags, const GlobalValue *GV = 0) {
1332 HiOpFlags = PPCII::MO_HA16;
1333 LoOpFlags = PPCII::MO_LO16;
1335 // Don't use the pic base if not in PIC relocation model. Or if we are on a
1336 // non-darwin platform. We don't support PIC on other platforms yet.
1337 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ &&
1338 TM.getSubtarget<PPCSubtarget>().isDarwin();
1340 HiOpFlags |= PPCII::MO_PIC_FLAG;
1341 LoOpFlags |= PPCII::MO_PIC_FLAG;
1344 // If this is a reference to a global value that requires a non-lazy-ptr, make
1345 // sure that instruction lowering adds it.
1346 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1347 HiOpFlags |= PPCII::MO_NLP_FLAG;
1348 LoOpFlags |= PPCII::MO_NLP_FLAG;
1350 if (GV->hasHiddenVisibility()) {
1351 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1352 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1359 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1360 SelectionDAG &DAG) {
1361 EVT PtrVT = HiPart.getValueType();
1362 SDValue Zero = DAG.getConstant(0, PtrVT);
1363 DebugLoc DL = HiPart.getDebugLoc();
1365 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1366 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1368 // With PIC, the first instruction is actually "GR+hi(&G)".
1370 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1371 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1373 // Generate non-pic code that has direct accesses to the constant pool.
1374 // The address of the global is just (hi(&g)+lo(&g)).
1375 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1378 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1379 SelectionDAG &DAG) const {
1380 EVT PtrVT = Op.getValueType();
1381 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1382 const Constant *C = CP->getConstVal();
1384 // 64-bit SVR4 ABI code is always position-independent.
1385 // The actual address of the GlobalValue is stored in the TOC.
1386 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1387 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1388 return DAG.getNode(PPCISD::TOC_ENTRY, CP->getDebugLoc(), MVT::i64, GA,
1389 DAG.getRegister(PPC::X2, MVT::i64));
1392 unsigned MOHiFlag, MOLoFlag;
1393 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1395 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1397 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1398 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1401 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1402 EVT PtrVT = Op.getValueType();
1403 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1405 // 64-bit SVR4 ABI code is always position-independent.
1406 // The actual address of the GlobalValue is stored in the TOC.
1407 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1408 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1409 return DAG.getNode(PPCISD::TOC_ENTRY, JT->getDebugLoc(), MVT::i64, GA,
1410 DAG.getRegister(PPC::X2, MVT::i64));
1413 unsigned MOHiFlag, MOLoFlag;
1414 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1415 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1416 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1417 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1420 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1421 SelectionDAG &DAG) const {
1422 EVT PtrVT = Op.getValueType();
1424 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1426 unsigned MOHiFlag, MOLoFlag;
1427 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1428 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1429 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1430 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1433 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1434 SelectionDAG &DAG) const {
1436 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1437 DebugLoc dl = GA->getDebugLoc();
1438 const GlobalValue *GV = GA->getGlobal();
1439 EVT PtrVT = getPointerTy();
1440 bool is64bit = PPCSubTarget.isPPC64();
1442 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1444 if (Model == TLSModel::LocalExec) {
1445 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1446 PPCII::MO_TPREL16_HA);
1447 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1448 PPCII::MO_TPREL16_LO);
1449 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1450 is64bit ? MVT::i64 : MVT::i32);
1451 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1452 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1456 llvm_unreachable("only local-exec is currently supported for ppc32");
1458 if (Model == TLSModel::InitialExec) {
1459 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1460 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1461 SDValue TPOffsetHi = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1462 PtrVT, GOTReg, TGA);
1463 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1464 PtrVT, TGA, TPOffsetHi);
1465 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGA);
1468 if (Model == TLSModel::GeneralDynamic) {
1469 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1470 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1471 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1473 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1476 // We need a chain node, and don't have one handy. The underlying
1477 // call has no side effects, so using the function entry node
1479 SDValue Chain = DAG.getEntryNode();
1480 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1481 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1482 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl,
1483 PtrVT, ParmReg, TGA);
1484 // The return value from GET_TLS_ADDR really is in X3 already, but
1485 // some hacks are needed here to tie everything together. The extra
1486 // copies dissolve during subsequent transforms.
1487 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1488 return DAG.getCopyFromReg(Chain, dl, PPC::X3, PtrVT);
1491 if (Model == TLSModel::LocalDynamic) {
1492 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1493 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1494 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1496 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1499 // We need a chain node, and don't have one handy. The underlying
1500 // call has no side effects, so using the function entry node
1502 SDValue Chain = DAG.getEntryNode();
1503 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1504 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1505 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl,
1506 PtrVT, ParmReg, TGA);
1507 // The return value from GET_TLSLD_ADDR really is in X3 already, but
1508 // some hacks are needed here to tie everything together. The extra
1509 // copies dissolve during subsequent transforms.
1510 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1511 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1512 Chain, ParmReg, TGA);
1513 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1516 llvm_unreachable("Unknown TLS model!");
1519 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1520 SelectionDAG &DAG) const {
1521 EVT PtrVT = Op.getValueType();
1522 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1523 DebugLoc DL = GSDN->getDebugLoc();
1524 const GlobalValue *GV = GSDN->getGlobal();
1526 // 64-bit SVR4 ABI code is always position-independent.
1527 // The actual address of the GlobalValue is stored in the TOC.
1528 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1529 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1530 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1531 DAG.getRegister(PPC::X2, MVT::i64));
1534 unsigned MOHiFlag, MOLoFlag;
1535 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1538 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1540 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1542 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1544 // If the global reference is actually to a non-lazy-pointer, we have to do an
1545 // extra load to get the address of the global.
1546 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1547 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1548 false, false, false, 0);
1552 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1553 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1554 DebugLoc dl = Op.getDebugLoc();
1556 // If we're comparing for equality to zero, expose the fact that this is
1557 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1558 // fold the new nodes.
1559 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1560 if (C->isNullValue() && CC == ISD::SETEQ) {
1561 EVT VT = Op.getOperand(0).getValueType();
1562 SDValue Zext = Op.getOperand(0);
1563 if (VT.bitsLT(MVT::i32)) {
1565 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1567 unsigned Log2b = Log2_32(VT.getSizeInBits());
1568 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1569 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1570 DAG.getConstant(Log2b, MVT::i32));
1571 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1573 // Leave comparisons against 0 and -1 alone for now, since they're usually
1574 // optimized. FIXME: revisit this when we can custom lower all setcc
1576 if (C->isAllOnesValue() || C->isNullValue())
1580 // If we have an integer seteq/setne, turn it into a compare against zero
1581 // by xor'ing the rhs with the lhs, which is faster than setting a
1582 // condition register, reading it back out, and masking the correct bit. The
1583 // normal approach here uses sub to do this instead of xor. Using xor exposes
1584 // the result to other bit-twiddling opportunities.
1585 EVT LHSVT = Op.getOperand(0).getValueType();
1586 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1587 EVT VT = Op.getValueType();
1588 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1590 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1595 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1596 const PPCSubtarget &Subtarget) const {
1597 SDNode *Node = Op.getNode();
1598 EVT VT = Node->getValueType(0);
1599 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1600 SDValue InChain = Node->getOperand(0);
1601 SDValue VAListPtr = Node->getOperand(1);
1602 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1603 DebugLoc dl = Node->getDebugLoc();
1605 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1608 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1609 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1611 InChain = GprIndex.getValue(1);
1613 if (VT == MVT::i64) {
1614 // Check if GprIndex is even
1615 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1616 DAG.getConstant(1, MVT::i32));
1617 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1618 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1619 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1620 DAG.getConstant(1, MVT::i32));
1621 // Align GprIndex to be even if it isn't
1622 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1626 // fpr index is 1 byte after gpr
1627 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1628 DAG.getConstant(1, MVT::i32));
1631 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1632 FprPtr, MachinePointerInfo(SV), MVT::i8,
1634 InChain = FprIndex.getValue(1);
1636 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1637 DAG.getConstant(8, MVT::i32));
1639 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1640 DAG.getConstant(4, MVT::i32));
1643 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1644 MachinePointerInfo(), false, false,
1646 InChain = OverflowArea.getValue(1);
1648 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1649 MachinePointerInfo(), false, false,
1651 InChain = RegSaveArea.getValue(1);
1653 // select overflow_area if index > 8
1654 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1655 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1657 // adjustment constant gpr_index * 4/8
1658 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1659 VT.isInteger() ? GprIndex : FprIndex,
1660 DAG.getConstant(VT.isInteger() ? 4 : 8,
1663 // OurReg = RegSaveArea + RegConstant
1664 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1667 // Floating types are 32 bytes into RegSaveArea
1668 if (VT.isFloatingPoint())
1669 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1670 DAG.getConstant(32, MVT::i32));
1672 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1673 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1674 VT.isInteger() ? GprIndex : FprIndex,
1675 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1678 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1679 VT.isInteger() ? VAListPtr : FprPtr,
1680 MachinePointerInfo(SV),
1681 MVT::i8, false, false, 0);
1683 // determine if we should load from reg_save_area or overflow_area
1684 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1686 // increase overflow_area by 4/8 if gpr/fpr > 8
1687 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1688 DAG.getConstant(VT.isInteger() ? 4 : 8,
1691 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1694 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1696 MachinePointerInfo(),
1697 MVT::i32, false, false, 0);
1699 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1700 false, false, false, 0);
1703 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
1704 SelectionDAG &DAG) const {
1705 return Op.getOperand(0);
1708 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
1709 SelectionDAG &DAG) const {
1710 SDValue Chain = Op.getOperand(0);
1711 SDValue Trmp = Op.getOperand(1); // trampoline
1712 SDValue FPtr = Op.getOperand(2); // nested function
1713 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1714 DebugLoc dl = Op.getDebugLoc();
1716 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1717 bool isPPC64 = (PtrVT == MVT::i64);
1719 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
1722 TargetLowering::ArgListTy Args;
1723 TargetLowering::ArgListEntry Entry;
1725 Entry.Ty = IntPtrTy;
1726 Entry.Node = Trmp; Args.push_back(Entry);
1728 // TrampSize == (isPPC64 ? 48 : 40);
1729 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1730 isPPC64 ? MVT::i64 : MVT::i32);
1731 Args.push_back(Entry);
1733 Entry.Node = FPtr; Args.push_back(Entry);
1734 Entry.Node = Nest; Args.push_back(Entry);
1736 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1737 TargetLowering::CallLoweringInfo CLI(Chain,
1738 Type::getVoidTy(*DAG.getContext()),
1739 false, false, false, false, 0,
1741 /*isTailCall=*/false,
1742 /*doesNotRet=*/false,
1743 /*isReturnValueUsed=*/true,
1744 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1746 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1748 return CallResult.second;
1751 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1752 const PPCSubtarget &Subtarget) const {
1753 MachineFunction &MF = DAG.getMachineFunction();
1754 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1756 DebugLoc dl = Op.getDebugLoc();
1758 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
1759 // vastart just stores the address of the VarArgsFrameIndex slot into the
1760 // memory location argument.
1761 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1762 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1763 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1764 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
1765 MachinePointerInfo(SV),
1769 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
1770 // We suppose the given va_list is already allocated.
1773 // char gpr; /* index into the array of 8 GPRs
1774 // * stored in the register save area
1775 // * gpr=0 corresponds to r3,
1776 // * gpr=1 to r4, etc.
1778 // char fpr; /* index into the array of 8 FPRs
1779 // * stored in the register save area
1780 // * fpr=0 corresponds to f1,
1781 // * fpr=1 to f2, etc.
1783 // char *overflow_arg_area;
1784 // /* location on stack that holds
1785 // * the next overflow argument
1787 // char *reg_save_area;
1788 // /* where r3:r10 and f1:f8 (if saved)
1794 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
1795 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
1798 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1800 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
1802 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1805 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
1806 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1808 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
1809 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1811 uint64_t FPROffset = 1;
1812 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1814 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1816 // Store first byte : number of int regs
1817 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
1819 MachinePointerInfo(SV),
1820 MVT::i8, false, false, 0);
1821 uint64_t nextOffset = FPROffset;
1822 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
1825 // Store second byte : number of float regs
1826 SDValue secondStore =
1827 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
1828 MachinePointerInfo(SV, nextOffset), MVT::i8,
1830 nextOffset += StackOffset;
1831 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
1833 // Store second word : arguments given on stack
1834 SDValue thirdStore =
1835 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
1836 MachinePointerInfo(SV, nextOffset),
1838 nextOffset += FrameOffset;
1839 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
1841 // Store third word : arguments given in registers
1842 return DAG.getStore(thirdStore, dl, FR, nextPtr,
1843 MachinePointerInfo(SV, nextOffset),
1848 #include "PPCGenCallingConv.inc"
1850 static bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
1851 CCValAssign::LocInfo &LocInfo,
1852 ISD::ArgFlagsTy &ArgFlags,
1857 static bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
1859 CCValAssign::LocInfo &LocInfo,
1860 ISD::ArgFlagsTy &ArgFlags,
1862 static const uint16_t ArgRegs[] = {
1863 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1864 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1866 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1868 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1870 // Skip one register if the first unallocated register has an even register
1871 // number and there are still argument registers available which have not been
1872 // allocated yet. RegNum is actually an index into ArgRegs, which means we
1873 // need to skip a register if RegNum is odd.
1874 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
1875 State.AllocateReg(ArgRegs[RegNum]);
1878 // Always return false here, as this function only makes sure that the first
1879 // unallocated register has an odd register number and does not actually
1880 // allocate a register for the current argument.
1884 static bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
1886 CCValAssign::LocInfo &LocInfo,
1887 ISD::ArgFlagsTy &ArgFlags,
1889 static const uint16_t ArgRegs[] = {
1890 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1894 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1896 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1898 // If there is only one Floating-point register left we need to put both f64
1899 // values of a split ppc_fp128 value on the stack.
1900 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
1901 State.AllocateReg(ArgRegs[RegNum]);
1904 // Always return false here, as this function only makes sure that the two f64
1905 // values a ppc_fp128 value is split into are both passed in registers or both
1906 // passed on the stack and does not actually allocate a register for the
1907 // current argument.
1911 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1913 static const uint16_t *GetFPR() {
1914 static const uint16_t FPR[] = {
1915 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1916 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1922 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
1924 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
1925 unsigned PtrByteSize) {
1926 unsigned ArgSize = ArgVT.getSizeInBits()/8;
1927 if (Flags.isByVal())
1928 ArgSize = Flags.getByValSize();
1929 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1935 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
1936 CallingConv::ID CallConv, bool isVarArg,
1937 const SmallVectorImpl<ISD::InputArg>
1939 DebugLoc dl, SelectionDAG &DAG,
1940 SmallVectorImpl<SDValue> &InVals)
1942 if (PPCSubTarget.isSVR4ABI()) {
1943 if (PPCSubTarget.isPPC64())
1944 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
1947 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
1950 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
1956 PPCTargetLowering::LowerFormalArguments_32SVR4(
1958 CallingConv::ID CallConv, bool isVarArg,
1959 const SmallVectorImpl<ISD::InputArg>
1961 DebugLoc dl, SelectionDAG &DAG,
1962 SmallVectorImpl<SDValue> &InVals) const {
1964 // 32-bit SVR4 ABI Stack Frame Layout:
1965 // +-----------------------------------+
1966 // +--> | Back chain |
1967 // | +-----------------------------------+
1968 // | | Floating-point register save area |
1969 // | +-----------------------------------+
1970 // | | General register save area |
1971 // | +-----------------------------------+
1972 // | | CR save word |
1973 // | +-----------------------------------+
1974 // | | VRSAVE save word |
1975 // | +-----------------------------------+
1976 // | | Alignment padding |
1977 // | +-----------------------------------+
1978 // | | Vector register save area |
1979 // | +-----------------------------------+
1980 // | | Local variable space |
1981 // | +-----------------------------------+
1982 // | | Parameter list area |
1983 // | +-----------------------------------+
1984 // | | LR save word |
1985 // | +-----------------------------------+
1986 // SP--> +--- | Back chain |
1987 // +-----------------------------------+
1990 // System V Application Binary Interface PowerPC Processor Supplement
1991 // AltiVec Technology Programming Interface Manual
1993 MachineFunction &MF = DAG.getMachineFunction();
1994 MachineFrameInfo *MFI = MF.getFrameInfo();
1995 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1997 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1998 // Potential tail calls could cause overwriting of argument stack slots.
1999 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2000 (CallConv == CallingConv::Fast));
2001 unsigned PtrByteSize = 4;
2003 // Assign locations to all of the incoming arguments.
2004 SmallVector<CCValAssign, 16> ArgLocs;
2005 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2006 getTargetMachine(), ArgLocs, *DAG.getContext());
2008 // Reserve space for the linkage area on the stack.
2009 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
2011 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2013 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2014 CCValAssign &VA = ArgLocs[i];
2016 // Arguments stored in registers.
2017 if (VA.isRegLoc()) {
2018 const TargetRegisterClass *RC;
2019 EVT ValVT = VA.getValVT();
2021 switch (ValVT.getSimpleVT().SimpleTy) {
2023 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2025 RC = &PPC::GPRCRegClass;
2028 RC = &PPC::F4RCRegClass;
2031 RC = &PPC::F8RCRegClass;
2037 RC = &PPC::VRRCRegClass;
2041 // Transform the arguments stored in physical registers into virtual ones.
2042 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2043 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT);
2045 InVals.push_back(ArgValue);
2047 // Argument stored in memory.
2048 assert(VA.isMemLoc());
2050 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
2051 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2054 // Create load nodes to retrieve arguments from the stack.
2055 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2056 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2057 MachinePointerInfo(),
2058 false, false, false, 0));
2062 // Assign locations to all of the incoming aggregate by value arguments.
2063 // Aggregates passed by value are stored in the local variable space of the
2064 // caller's stack frame, right above the parameter list area.
2065 SmallVector<CCValAssign, 16> ByValArgLocs;
2066 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2067 getTargetMachine(), ByValArgLocs, *DAG.getContext());
2069 // Reserve stack space for the allocations in CCInfo.
2070 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2072 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2074 // Area that is at least reserved in the caller of this function.
2075 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2077 // Set the size that is at least reserved in caller of this function. Tail
2078 // call optimized function's reserved stack space needs to be aligned so that
2079 // taking the difference between two stack areas will result in an aligned
2081 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2084 std::max(MinReservedArea,
2085 PPCFrameLowering::getMinCallFrameSize(false, false));
2087 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
2088 getStackAlignment();
2089 unsigned AlignMask = TargetAlign-1;
2090 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2092 FI->setMinReservedArea(MinReservedArea);
2094 SmallVector<SDValue, 8> MemOps;
2096 // If the function takes variable number of arguments, make a frame index for
2097 // the start of the first vararg value... for expansion of llvm.va_start.
2099 static const uint16_t GPArgRegs[] = {
2100 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2101 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2103 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2105 static const uint16_t FPArgRegs[] = {
2106 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2109 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2111 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2113 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2116 // Make room for NumGPArgRegs and NumFPArgRegs.
2117 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2118 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
2120 FuncInfo->setVarArgsStackOffset(
2121 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2122 CCInfo.getNextStackOffset(), true));
2124 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2125 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2127 // The fixed integer arguments of a variadic function are stored to the
2128 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2129 // the result of va_next.
2130 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2131 // Get an existing live-in vreg, or add a new one.
2132 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2134 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2136 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2137 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2138 MachinePointerInfo(), false, false, 0);
2139 MemOps.push_back(Store);
2140 // Increment the address by four for the next argument to store
2141 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2142 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2145 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2147 // The double arguments are stored to the VarArgsFrameIndex
2149 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2150 // Get an existing live-in vreg, or add a new one.
2151 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2153 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2155 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2156 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2157 MachinePointerInfo(), false, false, 0);
2158 MemOps.push_back(Store);
2159 // Increment the address by eight for the next argument to store
2160 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
2162 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2166 if (!MemOps.empty())
2167 Chain = DAG.getNode(ISD::TokenFactor, dl,
2168 MVT::Other, &MemOps[0], MemOps.size());
2173 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2174 // value to MVT::i64 and then truncate to the correct register size.
2176 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2177 SelectionDAG &DAG, SDValue ArgVal,
2178 DebugLoc dl) const {
2180 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2181 DAG.getValueType(ObjectVT));
2182 else if (Flags.isZExt())
2183 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2184 DAG.getValueType(ObjectVT));
2186 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2189 // Set the size that is at least reserved in caller of this function. Tail
2190 // call optimized functions' reserved stack space needs to be aligned so that
2191 // taking the difference between two stack areas will result in an aligned
2194 PPCTargetLowering::setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG,
2195 unsigned nAltivecParamsAtEnd,
2196 unsigned MinReservedArea,
2197 bool isPPC64) const {
2198 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2199 // Add the Altivec parameters at the end, if needed.
2200 if (nAltivecParamsAtEnd) {
2201 MinReservedArea = ((MinReservedArea+15)/16)*16;
2202 MinReservedArea += 16*nAltivecParamsAtEnd;
2205 std::max(MinReservedArea,
2206 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2207 unsigned TargetAlign
2208 = DAG.getMachineFunction().getTarget().getFrameLowering()->
2209 getStackAlignment();
2210 unsigned AlignMask = TargetAlign-1;
2211 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2212 FI->setMinReservedArea(MinReservedArea);
2216 PPCTargetLowering::LowerFormalArguments_64SVR4(
2218 CallingConv::ID CallConv, bool isVarArg,
2219 const SmallVectorImpl<ISD::InputArg>
2221 DebugLoc dl, SelectionDAG &DAG,
2222 SmallVectorImpl<SDValue> &InVals) const {
2223 // TODO: add description of PPC stack frame format, or at least some docs.
2225 MachineFunction &MF = DAG.getMachineFunction();
2226 MachineFrameInfo *MFI = MF.getFrameInfo();
2227 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2229 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2230 // Potential tail calls could cause overwriting of argument stack slots.
2231 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2232 (CallConv == CallingConv::Fast));
2233 unsigned PtrByteSize = 8;
2235 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
2236 // Area that is at least reserved in caller of this function.
2237 unsigned MinReservedArea = ArgOffset;
2239 static const uint16_t GPR[] = {
2240 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2241 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2244 static const uint16_t *FPR = GetFPR();
2246 static const uint16_t VR[] = {
2247 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2248 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2251 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2252 const unsigned Num_FPR_Regs = 13;
2253 const unsigned Num_VR_Regs = array_lengthof(VR);
2255 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2257 // Add DAG nodes to load the arguments or copy them out of registers. On
2258 // entry to a function on PPC, the arguments start after the linkage area,
2259 // although the first ones are often in registers.
2261 SmallVector<SDValue, 8> MemOps;
2262 unsigned nAltivecParamsAtEnd = 0;
2263 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2264 unsigned CurArgIdx = 0;
2265 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2267 bool needsLoad = false;
2268 EVT ObjectVT = Ins[ArgNo].VT;
2269 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2270 unsigned ArgSize = ObjSize;
2271 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2272 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2273 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2275 unsigned CurArgOffset = ArgOffset;
2277 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2278 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2279 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2281 MinReservedArea = ((MinReservedArea+15)/16)*16;
2282 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2286 nAltivecParamsAtEnd++;
2288 // Calculate min reserved area.
2289 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2293 // FIXME the codegen can be much improved in some cases.
2294 // We do not have to keep everything in memory.
2295 if (Flags.isByVal()) {
2296 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2297 ObjSize = Flags.getByValSize();
2298 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2299 // Empty aggregate parameters do not take up registers. Examples:
2303 // etc. However, we have to provide a place-holder in InVals, so
2304 // pretend we have an 8-byte item at the current address for that
2307 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2308 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2309 InVals.push_back(FIN);
2312 // All aggregates smaller than 8 bytes must be passed right-justified.
2313 if (ObjSize < PtrByteSize)
2314 CurArgOffset = CurArgOffset + (PtrByteSize - ObjSize);
2315 // The value of the object is its address.
2316 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2317 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2318 InVals.push_back(FIN);
2321 if (GPR_idx != Num_GPR_Regs) {
2322 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2323 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2326 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2327 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2328 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2329 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2330 MachinePointerInfo(FuncArg, CurArgOffset),
2331 ObjType, false, false, 0);
2333 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2334 // store the whole register as-is to the parameter save area
2335 // slot. The address of the parameter was already calculated
2336 // above (InVals.push_back(FIN)) to be the right-justified
2337 // offset within the slot. For this store, we need a new
2338 // frame index that points at the beginning of the slot.
2339 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2340 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2341 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2342 MachinePointerInfo(FuncArg, ArgOffset),
2346 MemOps.push_back(Store);
2349 // Whether we copied from a register or not, advance the offset
2350 // into the parameter save area by a full doubleword.
2351 ArgOffset += PtrByteSize;
2355 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2356 // Store whatever pieces of the object are in registers
2357 // to memory. ArgOffset will be the address of the beginning
2359 if (GPR_idx != Num_GPR_Regs) {
2361 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2362 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2363 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2364 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2365 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2366 MachinePointerInfo(FuncArg, ArgOffset),
2368 MemOps.push_back(Store);
2370 ArgOffset += PtrByteSize;
2372 ArgOffset += ArgSize - j;
2379 switch (ObjectVT.getSimpleVT().SimpleTy) {
2380 default: llvm_unreachable("Unhandled argument type!");
2383 if (GPR_idx != Num_GPR_Regs) {
2384 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2385 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2387 if (ObjectVT == MVT::i32)
2388 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2389 // value to MVT::i64 and then truncate to the correct register size.
2390 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2395 ArgSize = PtrByteSize;
2402 // Every 8 bytes of argument space consumes one of the GPRs available for
2403 // argument passing.
2404 if (GPR_idx != Num_GPR_Regs) {
2407 if (FPR_idx != Num_FPR_Regs) {
2410 if (ObjectVT == MVT::f32)
2411 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2413 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2415 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2419 ArgSize = PtrByteSize;
2428 // Note that vector arguments in registers don't reserve stack space,
2429 // except in varargs functions.
2430 if (VR_idx != Num_VR_Regs) {
2431 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2432 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2434 while ((ArgOffset % 16) != 0) {
2435 ArgOffset += PtrByteSize;
2436 if (GPR_idx != Num_GPR_Regs)
2440 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2444 // Vectors are aligned.
2445 ArgOffset = ((ArgOffset+15)/16)*16;
2446 CurArgOffset = ArgOffset;
2453 // We need to load the argument to a virtual register if we determined
2454 // above that we ran out of physical registers of the appropriate type.
2456 int FI = MFI->CreateFixedObject(ObjSize,
2457 CurArgOffset + (ArgSize - ObjSize),
2459 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2460 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2461 false, false, false, 0);
2464 InVals.push_back(ArgVal);
2467 // Set the size that is at least reserved in caller of this function. Tail
2468 // call optimized functions' reserved stack space needs to be aligned so that
2469 // taking the difference between two stack areas will result in an aligned
2471 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, true);
2473 // If the function takes variable number of arguments, make a frame index for
2474 // the start of the first vararg value... for expansion of llvm.va_start.
2476 int Depth = ArgOffset;
2478 FuncInfo->setVarArgsFrameIndex(
2479 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2480 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2482 // If this function is vararg, store any remaining integer argument regs
2483 // to their spots on the stack so that they may be loaded by deferencing the
2484 // result of va_next.
2485 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2486 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2487 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2488 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2489 MachinePointerInfo(), false, false, 0);
2490 MemOps.push_back(Store);
2491 // Increment the address by four for the next argument to store
2492 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2493 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2497 if (!MemOps.empty())
2498 Chain = DAG.getNode(ISD::TokenFactor, dl,
2499 MVT::Other, &MemOps[0], MemOps.size());
2505 PPCTargetLowering::LowerFormalArguments_Darwin(
2507 CallingConv::ID CallConv, bool isVarArg,
2508 const SmallVectorImpl<ISD::InputArg>
2510 DebugLoc dl, SelectionDAG &DAG,
2511 SmallVectorImpl<SDValue> &InVals) const {
2512 // TODO: add description of PPC stack frame format, or at least some docs.
2514 MachineFunction &MF = DAG.getMachineFunction();
2515 MachineFrameInfo *MFI = MF.getFrameInfo();
2516 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2518 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2519 bool isPPC64 = PtrVT == MVT::i64;
2520 // Potential tail calls could cause overwriting of argument stack slots.
2521 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2522 (CallConv == CallingConv::Fast));
2523 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2525 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
2526 // Area that is at least reserved in caller of this function.
2527 unsigned MinReservedArea = ArgOffset;
2529 static const uint16_t GPR_32[] = { // 32-bit registers.
2530 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2531 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2533 static const uint16_t GPR_64[] = { // 64-bit registers.
2534 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2535 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2538 static const uint16_t *FPR = GetFPR();
2540 static const uint16_t VR[] = {
2541 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2542 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2545 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2546 const unsigned Num_FPR_Regs = 13;
2547 const unsigned Num_VR_Regs = array_lengthof( VR);
2549 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2551 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
2553 // In 32-bit non-varargs functions, the stack space for vectors is after the
2554 // stack space for non-vectors. We do not use this space unless we have
2555 // too many vectors to fit in registers, something that only occurs in
2556 // constructed examples:), but we have to walk the arglist to figure
2557 // that out...for the pathological case, compute VecArgOffset as the
2558 // start of the vector parameter area. Computing VecArgOffset is the
2559 // entire point of the following loop.
2560 unsigned VecArgOffset = ArgOffset;
2561 if (!isVarArg && !isPPC64) {
2562 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
2564 EVT ObjectVT = Ins[ArgNo].VT;
2565 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2567 if (Flags.isByVal()) {
2568 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
2569 unsigned ObjSize = Flags.getByValSize();
2571 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2572 VecArgOffset += ArgSize;
2576 switch(ObjectVT.getSimpleVT().SimpleTy) {
2577 default: llvm_unreachable("Unhandled argument type!");
2582 case MVT::i64: // PPC64
2584 // FIXME: We are guaranteed to be !isPPC64 at this point.
2585 // Does MVT::i64 apply?
2592 // Nothing to do, we're only looking at Nonvector args here.
2597 // We've found where the vector parameter area in memory is. Skip the
2598 // first 12 parameters; these don't use that memory.
2599 VecArgOffset = ((VecArgOffset+15)/16)*16;
2600 VecArgOffset += 12*16;
2602 // Add DAG nodes to load the arguments or copy them out of registers. On
2603 // entry to a function on PPC, the arguments start after the linkage area,
2604 // although the first ones are often in registers.
2606 SmallVector<SDValue, 8> MemOps;
2607 unsigned nAltivecParamsAtEnd = 0;
2608 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2609 unsigned CurArgIdx = 0;
2610 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2612 bool needsLoad = false;
2613 EVT ObjectVT = Ins[ArgNo].VT;
2614 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2615 unsigned ArgSize = ObjSize;
2616 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2617 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2618 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2620 unsigned CurArgOffset = ArgOffset;
2622 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2623 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2624 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2625 if (isVarArg || isPPC64) {
2626 MinReservedArea = ((MinReservedArea+15)/16)*16;
2627 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2630 } else nAltivecParamsAtEnd++;
2632 // Calculate min reserved area.
2633 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2637 // FIXME the codegen can be much improved in some cases.
2638 // We do not have to keep everything in memory.
2639 if (Flags.isByVal()) {
2640 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2641 ObjSize = Flags.getByValSize();
2642 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2643 // Objects of size 1 and 2 are right justified, everything else is
2644 // left justified. This means the memory address is adjusted forwards.
2645 if (ObjSize==1 || ObjSize==2) {
2646 CurArgOffset = CurArgOffset + (4 - ObjSize);
2648 // The value of the object is its address.
2649 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2650 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2651 InVals.push_back(FIN);
2652 if (ObjSize==1 || ObjSize==2) {
2653 if (GPR_idx != Num_GPR_Regs) {
2656 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2658 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2659 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2660 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
2661 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2662 MachinePointerInfo(FuncArg,
2664 ObjType, false, false, 0);
2665 MemOps.push_back(Store);
2669 ArgOffset += PtrByteSize;
2673 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2674 // Store whatever pieces of the object are in registers
2675 // to memory. ArgOffset will be the address of the beginning
2677 if (GPR_idx != Num_GPR_Regs) {
2680 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2682 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2683 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2684 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2685 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2686 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2687 MachinePointerInfo(FuncArg, ArgOffset),
2689 MemOps.push_back(Store);
2691 ArgOffset += PtrByteSize;
2693 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
2700 switch (ObjectVT.getSimpleVT().SimpleTy) {
2701 default: llvm_unreachable("Unhandled argument type!");
2704 if (GPR_idx != Num_GPR_Regs) {
2705 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2706 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2710 ArgSize = PtrByteSize;
2712 // All int arguments reserve stack space in the Darwin ABI.
2713 ArgOffset += PtrByteSize;
2717 case MVT::i64: // PPC64
2718 if (GPR_idx != Num_GPR_Regs) {
2719 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2720 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2722 if (ObjectVT == MVT::i32)
2723 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2724 // value to MVT::i64 and then truncate to the correct register size.
2725 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2730 ArgSize = PtrByteSize;
2732 // All int arguments reserve stack space in the Darwin ABI.
2738 // Every 4 bytes of argument space consumes one of the GPRs available for
2739 // argument passing.
2740 if (GPR_idx != Num_GPR_Regs) {
2742 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
2745 if (FPR_idx != Num_FPR_Regs) {
2748 if (ObjectVT == MVT::f32)
2749 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2751 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2753 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2759 // All FP arguments reserve stack space in the Darwin ABI.
2760 ArgOffset += isPPC64 ? 8 : ObjSize;
2766 // Note that vector arguments in registers don't reserve stack space,
2767 // except in varargs functions.
2768 if (VR_idx != Num_VR_Regs) {
2769 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2770 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2772 while ((ArgOffset % 16) != 0) {
2773 ArgOffset += PtrByteSize;
2774 if (GPR_idx != Num_GPR_Regs)
2778 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2782 if (!isVarArg && !isPPC64) {
2783 // Vectors go after all the nonvectors.
2784 CurArgOffset = VecArgOffset;
2787 // Vectors are aligned.
2788 ArgOffset = ((ArgOffset+15)/16)*16;
2789 CurArgOffset = ArgOffset;
2797 // We need to load the argument to a virtual register if we determined above
2798 // that we ran out of physical registers of the appropriate type.
2800 int FI = MFI->CreateFixedObject(ObjSize,
2801 CurArgOffset + (ArgSize - ObjSize),
2803 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2804 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2805 false, false, false, 0);
2808 InVals.push_back(ArgVal);
2811 // Set the size that is at least reserved in caller of this function. Tail
2812 // call optimized functions' reserved stack space needs to be aligned so that
2813 // taking the difference between two stack areas will result in an aligned
2815 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, isPPC64);
2817 // If the function takes variable number of arguments, make a frame index for
2818 // the start of the first vararg value... for expansion of llvm.va_start.
2820 int Depth = ArgOffset;
2822 FuncInfo->setVarArgsFrameIndex(
2823 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2825 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2827 // If this function is vararg, store any remaining integer argument regs
2828 // to their spots on the stack so that they may be loaded by deferencing the
2829 // result of va_next.
2830 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2834 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2836 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2838 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2839 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2840 MachinePointerInfo(), false, false, 0);
2841 MemOps.push_back(Store);
2842 // Increment the address by four for the next argument to store
2843 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2844 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2848 if (!MemOps.empty())
2849 Chain = DAG.getNode(ISD::TokenFactor, dl,
2850 MVT::Other, &MemOps[0], MemOps.size());
2855 /// CalculateParameterAndLinkageAreaSize - Get the size of the parameter plus
2856 /// linkage area for the Darwin ABI, or the 64-bit SVR4 ABI.
2858 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
2862 const SmallVectorImpl<ISD::OutputArg>
2864 const SmallVectorImpl<SDValue> &OutVals,
2865 unsigned &nAltivecParamsAtEnd) {
2866 // Count how many bytes are to be pushed on the stack, including the linkage
2867 // area, and parameter passing area. We start with 24/48 bytes, which is
2868 // prereserved space for [SP][CR][LR][3 x unused].
2869 unsigned NumBytes = PPCFrameLowering::getLinkageSize(isPPC64, true);
2870 unsigned NumOps = Outs.size();
2871 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2873 // Add up all the space actually used.
2874 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
2875 // they all go in registers, but we must reserve stack space for them for
2876 // possible use by the caller. In varargs or 64-bit calls, parameters are
2877 // assigned stack space in order, with padding so Altivec parameters are
2879 nAltivecParamsAtEnd = 0;
2880 for (unsigned i = 0; i != NumOps; ++i) {
2881 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2882 EVT ArgVT = Outs[i].VT;
2883 // Varargs Altivec parameters are padded to a 16 byte boundary.
2884 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
2885 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
2886 if (!isVarArg && !isPPC64) {
2887 // Non-varargs Altivec parameters go after all the non-Altivec
2888 // parameters; handle those later so we know how much padding we need.
2889 nAltivecParamsAtEnd++;
2892 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
2893 NumBytes = ((NumBytes+15)/16)*16;
2895 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2898 // Allow for Altivec parameters at the end, if needed.
2899 if (nAltivecParamsAtEnd) {
2900 NumBytes = ((NumBytes+15)/16)*16;
2901 NumBytes += 16*nAltivecParamsAtEnd;
2904 // The prolog code of the callee may store up to 8 GPR argument registers to
2905 // the stack, allowing va_start to index over them in memory if its varargs.
2906 // Because we cannot tell if this is needed on the caller side, we have to
2907 // conservatively assume that it is needed. As such, make sure we have at
2908 // least enough stack space for the caller to store the 8 GPRs.
2909 NumBytes = std::max(NumBytes,
2910 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2912 // Tail call needs the stack to be aligned.
2913 if (CC == CallingConv::Fast && DAG.getTarget().Options.GuaranteedTailCallOpt){
2914 unsigned TargetAlign = DAG.getMachineFunction().getTarget().
2915 getFrameLowering()->getStackAlignment();
2916 unsigned AlignMask = TargetAlign-1;
2917 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2923 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
2924 /// adjusted to accommodate the arguments for the tailcall.
2925 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
2926 unsigned ParamSize) {
2928 if (!isTailCall) return 0;
2930 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
2931 unsigned CallerMinReservedArea = FI->getMinReservedArea();
2932 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
2933 // Remember only if the new adjustement is bigger.
2934 if (SPDiff < FI->getTailCallSPDelta())
2935 FI->setTailCallSPDelta(SPDiff);
2940 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2941 /// for tail call optimization. Targets which want to do tail call
2942 /// optimization should implement this function.
2944 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2945 CallingConv::ID CalleeCC,
2947 const SmallVectorImpl<ISD::InputArg> &Ins,
2948 SelectionDAG& DAG) const {
2949 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
2952 // Variable argument functions are not supported.
2956 MachineFunction &MF = DAG.getMachineFunction();
2957 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
2958 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
2959 // Functions containing by val parameters are not supported.
2960 for (unsigned i = 0; i != Ins.size(); i++) {
2961 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2962 if (Flags.isByVal()) return false;
2965 // Non PIC/GOT tail calls are supported.
2966 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
2969 // At the moment we can only do local tail calls (in same module, hidden
2970 // or protected) if we are generating PIC.
2971 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2972 return G->getGlobal()->hasHiddenVisibility()
2973 || G->getGlobal()->hasProtectedVisibility();
2979 /// isCallCompatibleAddress - Return the immediate to use if the specified
2980 /// 32-bit value is representable in the immediate field of a BxA instruction.
2981 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
2982 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2985 int Addr = C->getZExtValue();
2986 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
2987 SignExtend32<26>(Addr) != Addr)
2988 return 0; // Top 6 bits have to be sext of immediate.
2990 return DAG.getConstant((int)C->getZExtValue() >> 2,
2991 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
2996 struct TailCallArgumentInfo {
3001 TailCallArgumentInfo() : FrameIdx(0) {}
3006 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3008 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3010 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs,
3011 SmallVector<SDValue, 8> &MemOpChains,
3013 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3014 SDValue Arg = TailCallArgs[i].Arg;
3015 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3016 int FI = TailCallArgs[i].FrameIdx;
3017 // Store relative to framepointer.
3018 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
3019 MachinePointerInfo::getFixedStack(FI),
3024 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3025 /// the appropriate stack slot for the tail call optimized function call.
3026 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3027 MachineFunction &MF,
3036 // Calculate the new stack slot for the return address.
3037 int SlotSize = isPPC64 ? 8 : 4;
3038 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
3040 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3041 NewRetAddrLoc, true);
3042 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3043 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3044 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3045 MachinePointerInfo::getFixedStack(NewRetAddr),
3048 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3049 // slot as the FP is never overwritten.
3052 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
3053 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3055 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3056 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3057 MachinePointerInfo::getFixedStack(NewFPIdx),
3064 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3065 /// the position of the argument.
3067 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3068 SDValue Arg, int SPDiff, unsigned ArgOffset,
3069 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
3070 int Offset = ArgOffset + SPDiff;
3071 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3072 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3073 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3074 SDValue FIN = DAG.getFrameIndex(FI, VT);
3075 TailCallArgumentInfo Info;
3077 Info.FrameIdxOp = FIN;
3079 TailCallArguments.push_back(Info);
3082 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3083 /// stack slot. Returns the chain as result and the loaded frame pointers in
3084 /// LROpOut/FPOpout. Used when tail calling.
3085 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3091 DebugLoc dl) const {
3093 // Load the LR and FP stack slot for later adjusting.
3094 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
3095 LROpOut = getReturnAddrFrameIndex(DAG);
3096 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3097 false, false, false, 0);
3098 Chain = SDValue(LROpOut.getNode(), 1);
3100 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3101 // slot as the FP is never overwritten.
3103 FPOpOut = getFramePointerFrameIndex(DAG);
3104 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3105 false, false, false, 0);
3106 Chain = SDValue(FPOpOut.getNode(), 1);
3112 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3113 /// by "Src" to address "Dst" of size "Size". Alignment information is
3114 /// specified by the specific parameter attribute. The copy will be passed as
3115 /// a byval function parameter.
3116 /// Sometimes what we are copying is the end of a larger object, the part that
3117 /// does not fit in registers.
3119 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3120 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3122 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3123 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3124 false, false, MachinePointerInfo(0),
3125 MachinePointerInfo(0));
3128 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3131 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3132 SDValue Arg, SDValue PtrOff, int SPDiff,
3133 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3134 bool isVector, SmallVector<SDValue, 8> &MemOpChains,
3135 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments,
3137 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3142 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3144 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3145 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3146 DAG.getConstant(ArgOffset, PtrVT));
3148 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3149 MachinePointerInfo(), false, false, 0));
3150 // Calculate and remember argument location.
3151 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3156 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3157 DebugLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3158 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3159 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments) {
3160 MachineFunction &MF = DAG.getMachineFunction();
3162 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3163 // might overwrite each other in case of tail call optimization.
3164 SmallVector<SDValue, 8> MemOpChains2;
3165 // Do not flag preceding copytoreg stuff together with the following stuff.
3167 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3169 if (!MemOpChains2.empty())
3170 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3171 &MemOpChains2[0], MemOpChains2.size());
3173 // Store the return address to the appropriate stack slot.
3174 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3175 isPPC64, isDarwinABI, dl);
3177 // Emit callseq_end just before tailcall node.
3178 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3179 DAG.getIntPtrConstant(0, true), InFlag);
3180 InFlag = Chain.getValue(1);
3184 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3185 SDValue &Chain, DebugLoc dl, int SPDiff, bool isTailCall,
3186 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
3187 SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys,
3188 const PPCSubtarget &PPCSubTarget) {
3190 bool isPPC64 = PPCSubTarget.isPPC64();
3191 bool isSVR4ABI = PPCSubTarget.isSVR4ABI();
3193 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3194 NodeTys.push_back(MVT::Other); // Returns a chain
3195 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3197 unsigned CallOpc = PPCISD::CALL;
3199 bool needIndirectCall = true;
3200 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3201 // If this is an absolute destination address, use the munged value.
3202 Callee = SDValue(Dest, 0);
3203 needIndirectCall = false;
3206 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3207 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201
3208 // Use indirect calls for ALL functions calls in JIT mode, since the
3209 // far-call stubs may be outside relocation limits for a BL instruction.
3210 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
3211 unsigned OpFlags = 0;
3212 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3213 (PPCSubTarget.getTargetTriple().isMacOSX() &&
3214 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3215 (G->getGlobal()->isDeclaration() ||
3216 G->getGlobal()->isWeakForLinker())) {
3217 // PC-relative references to external symbols should go through $stub,
3218 // unless we're building with the leopard linker or later, which
3219 // automatically synthesizes these stubs.
3220 OpFlags = PPCII::MO_DARWIN_STUB;
3223 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3224 // every direct call is) turn it into a TargetGlobalAddress /
3225 // TargetExternalSymbol node so that legalize doesn't hack it.
3226 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3227 Callee.getValueType(),
3229 needIndirectCall = false;
3233 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3234 unsigned char OpFlags = 0;
3236 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3237 (PPCSubTarget.getTargetTriple().isMacOSX() &&
3238 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5))) {
3239 // PC-relative references to external symbols should go through $stub,
3240 // unless we're building with the leopard linker or later, which
3241 // automatically synthesizes these stubs.
3242 OpFlags = PPCII::MO_DARWIN_STUB;
3245 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3247 needIndirectCall = false;
3250 if (needIndirectCall) {
3251 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3252 // to do the call, we can't use PPCISD::CALL.
3253 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3255 if (isSVR4ABI && isPPC64) {
3256 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3257 // entry point, but to the function descriptor (the function entry point
3258 // address is part of the function descriptor though).
3259 // The function descriptor is a three doubleword structure with the
3260 // following fields: function entry point, TOC base address and
3261 // environment pointer.
3262 // Thus for a call through a function pointer, the following actions need
3264 // 1. Save the TOC of the caller in the TOC save area of its stack
3265 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3266 // 2. Load the address of the function entry point from the function
3268 // 3. Load the TOC of the callee from the function descriptor into r2.
3269 // 4. Load the environment pointer from the function descriptor into
3271 // 5. Branch to the function entry point address.
3272 // 6. On return of the callee, the TOC of the caller needs to be
3273 // restored (this is done in FinishCall()).
3275 // All those operations are flagged together to ensure that no other
3276 // operations can be scheduled in between. E.g. without flagging the
3277 // operations together, a TOC access in the caller could be scheduled
3278 // between the load of the callee TOC and the branch to the callee, which
3279 // results in the TOC access going through the TOC of the callee instead
3280 // of going through the TOC of the caller, which leads to incorrect code.
3282 // Load the address of the function entry point from the function
3284 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3285 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps,
3286 InFlag.getNode() ? 3 : 2);
3287 Chain = LoadFuncPtr.getValue(1);
3288 InFlag = LoadFuncPtr.getValue(2);
3290 // Load environment pointer into r11.
3291 // Offset of the environment pointer within the function descriptor.
3292 SDValue PtrOff = DAG.getIntPtrConstant(16);
3294 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3295 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
3297 Chain = LoadEnvPtr.getValue(1);
3298 InFlag = LoadEnvPtr.getValue(2);
3300 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3302 Chain = EnvVal.getValue(0);
3303 InFlag = EnvVal.getValue(1);
3305 // Load TOC of the callee into r2. We are using a target-specific load
3306 // with r2 hard coded, because the result of a target-independent load
3307 // would never go directly into r2, since r2 is a reserved register (which
3308 // prevents the register allocator from allocating it), resulting in an
3309 // additional register being allocated and an unnecessary move instruction
3311 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3312 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
3314 Chain = LoadTOCPtr.getValue(0);
3315 InFlag = LoadTOCPtr.getValue(1);
3317 MTCTROps[0] = Chain;
3318 MTCTROps[1] = LoadFuncPtr;
3319 MTCTROps[2] = InFlag;
3322 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps,
3323 2 + (InFlag.getNode() != 0));
3324 InFlag = Chain.getValue(1);
3327 NodeTys.push_back(MVT::Other);
3328 NodeTys.push_back(MVT::Glue);
3329 Ops.push_back(Chain);
3330 CallOpc = PPCISD::BCTRL;
3332 // Add use of X11 (holding environment pointer)
3333 if (isSVR4ABI && isPPC64)
3334 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3335 // Add CTR register as callee so a bctr can be emitted later.
3337 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3340 // If this is a direct call, pass the chain and the callee.
3341 if (Callee.getNode()) {
3342 Ops.push_back(Chain);
3343 Ops.push_back(Callee);
3345 // If this is a tail call add stack pointer delta.
3347 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3349 // Add argument registers to the end of the list so that they are known live
3351 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3352 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3353 RegsToPass[i].second.getValueType()));
3359 bool isLocalCall(const SDValue &Callee)
3361 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3362 return !G->getGlobal()->isDeclaration() &&
3363 !G->getGlobal()->isWeakForLinker();
3368 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3369 CallingConv::ID CallConv, bool isVarArg,
3370 const SmallVectorImpl<ISD::InputArg> &Ins,
3371 DebugLoc dl, SelectionDAG &DAG,
3372 SmallVectorImpl<SDValue> &InVals) const {
3374 SmallVector<CCValAssign, 16> RVLocs;
3375 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3376 getTargetMachine(), RVLocs, *DAG.getContext());
3377 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3379 // Copy all of the result registers out of their specified physreg.
3380 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3381 CCValAssign &VA = RVLocs[i];
3382 assert(VA.isRegLoc() && "Can only return in registers!");
3384 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3385 VA.getLocReg(), VA.getLocVT(), InFlag);
3386 Chain = Val.getValue(1);
3387 InFlag = Val.getValue(2);
3389 switch (VA.getLocInfo()) {
3390 default: llvm_unreachable("Unknown loc info!");
3391 case CCValAssign::Full: break;
3392 case CCValAssign::AExt:
3393 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3395 case CCValAssign::ZExt:
3396 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3397 DAG.getValueType(VA.getValVT()));
3398 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3400 case CCValAssign::SExt:
3401 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3402 DAG.getValueType(VA.getValVT()));
3403 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3407 InVals.push_back(Val);
3414 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, DebugLoc dl,
3415 bool isTailCall, bool isVarArg,
3417 SmallVector<std::pair<unsigned, SDValue>, 8>
3419 SDValue InFlag, SDValue Chain,
3421 int SPDiff, unsigned NumBytes,
3422 const SmallVectorImpl<ISD::InputArg> &Ins,
3423 SmallVectorImpl<SDValue> &InVals) const {
3424 std::vector<EVT> NodeTys;
3425 SmallVector<SDValue, 8> Ops;
3426 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
3427 isTailCall, RegsToPass, Ops, NodeTys,
3430 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3431 if (isVarArg && PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64())
3432 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3434 // When performing tail call optimization the callee pops its arguments off
3435 // the stack. Account for this here so these bytes can be pushed back on in
3436 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3437 int BytesCalleePops =
3438 (CallConv == CallingConv::Fast &&
3439 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3441 // Add a register mask operand representing the call-preserved registers.
3442 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
3443 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3444 assert(Mask && "Missing call preserved mask for calling convention");
3445 Ops.push_back(DAG.getRegisterMask(Mask));
3447 if (InFlag.getNode())
3448 Ops.push_back(InFlag);
3452 assert(((Callee.getOpcode() == ISD::Register &&
3453 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3454 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3455 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3456 isa<ConstantSDNode>(Callee)) &&
3457 "Expecting an global address, external symbol, absolute value or register");
3459 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size());
3462 // Add a NOP immediately after the branch instruction when using the 64-bit
3463 // SVR4 ABI. At link time, if caller and callee are in a different module and
3464 // thus have a different TOC, the call will be replaced with a call to a stub
3465 // function which saves the current TOC, loads the TOC of the callee and
3466 // branches to the callee. The NOP will be replaced with a load instruction
3467 // which restores the TOC of the caller from the TOC save slot of the current
3468 // stack frame. If caller and callee belong to the same module (and have the
3469 // same TOC), the NOP will remain unchanged.
3471 bool needsTOCRestore = false;
3472 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) {
3473 if (CallOpc == PPCISD::BCTRL) {
3474 // This is a call through a function pointer.
3475 // Restore the caller TOC from the save area into R2.
3476 // See PrepareCall() for more information about calls through function
3477 // pointers in the 64-bit SVR4 ABI.
3478 // We are using a target-specific load with r2 hard coded, because the
3479 // result of a target-independent load would never go directly into r2,
3480 // since r2 is a reserved register (which prevents the register allocator
3481 // from allocating it), resulting in an additional register being
3482 // allocated and an unnecessary move instruction being generated.
3483 needsTOCRestore = true;
3484 } else if ((CallOpc == PPCISD::CALL) && !isLocalCall(Callee)) {
3485 // Otherwise insert NOP for non-local calls.
3486 CallOpc = PPCISD::CALL_NOP;
3490 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
3491 InFlag = Chain.getValue(1);
3493 if (needsTOCRestore) {
3494 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3495 Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag);
3496 InFlag = Chain.getValue(1);
3499 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3500 DAG.getIntPtrConstant(BytesCalleePops, true),
3503 InFlag = Chain.getValue(1);
3505 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3506 Ins, dl, DAG, InVals);
3510 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3511 SmallVectorImpl<SDValue> &InVals) const {
3512 SelectionDAG &DAG = CLI.DAG;
3513 DebugLoc &dl = CLI.DL;
3514 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
3515 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
3516 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
3517 SDValue Chain = CLI.Chain;
3518 SDValue Callee = CLI.Callee;
3519 bool &isTailCall = CLI.IsTailCall;
3520 CallingConv::ID CallConv = CLI.CallConv;
3521 bool isVarArg = CLI.IsVarArg;
3524 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3527 if (PPCSubTarget.isSVR4ABI()) {
3528 if (PPCSubTarget.isPPC64())
3529 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3530 isTailCall, Outs, OutVals, Ins,
3533 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3534 isTailCall, Outs, OutVals, Ins,
3538 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
3539 isTailCall, Outs, OutVals, Ins,
3544 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
3545 CallingConv::ID CallConv, bool isVarArg,
3547 const SmallVectorImpl<ISD::OutputArg> &Outs,
3548 const SmallVectorImpl<SDValue> &OutVals,
3549 const SmallVectorImpl<ISD::InputArg> &Ins,
3550 DebugLoc dl, SelectionDAG &DAG,
3551 SmallVectorImpl<SDValue> &InVals) const {
3552 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
3553 // of the 32-bit SVR4 ABI stack frame layout.
3555 assert((CallConv == CallingConv::C ||
3556 CallConv == CallingConv::Fast) && "Unknown calling convention!");
3558 unsigned PtrByteSize = 4;
3560 MachineFunction &MF = DAG.getMachineFunction();
3562 // Mark this function as potentially containing a function that contains a
3563 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3564 // and restoring the callers stack pointer in this functions epilog. This is
3565 // done because by tail calling the called function might overwrite the value
3566 // in this function's (MF) stack pointer stack slot 0(SP).
3567 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3568 CallConv == CallingConv::Fast)
3569 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3571 // Count how many bytes are to be pushed on the stack, including the linkage
3572 // area, parameter list area and the part of the local variable space which
3573 // contains copies of aggregates which are passed by value.
3575 // Assign locations to all of the outgoing arguments.
3576 SmallVector<CCValAssign, 16> ArgLocs;
3577 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3578 getTargetMachine(), ArgLocs, *DAG.getContext());
3580 // Reserve space for the linkage area on the stack.
3581 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
3584 // Handle fixed and variable vector arguments differently.
3585 // Fixed vector arguments go into registers as long as registers are
3586 // available. Variable vector arguments always go into memory.
3587 unsigned NumArgs = Outs.size();
3589 for (unsigned i = 0; i != NumArgs; ++i) {
3590 MVT ArgVT = Outs[i].VT;
3591 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3594 if (Outs[i].IsFixed) {
3595 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
3598 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
3604 errs() << "Call operand #" << i << " has unhandled type "
3605 << EVT(ArgVT).getEVTString() << "\n";
3607 llvm_unreachable(0);
3611 // All arguments are treated the same.
3612 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
3615 // Assign locations to all of the outgoing aggregate by value arguments.
3616 SmallVector<CCValAssign, 16> ByValArgLocs;
3617 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3618 getTargetMachine(), ByValArgLocs, *DAG.getContext());
3620 // Reserve stack space for the allocations in CCInfo.
3621 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
3623 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
3625 // Size of the linkage area, parameter list area and the part of the local
3626 // space variable where copies of aggregates which are passed by value are
3628 unsigned NumBytes = CCByValInfo.getNextStackOffset();
3630 // Calculate by how many bytes the stack has to be adjusted in case of tail
3631 // call optimization.
3632 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3634 // Adjust the stack pointer for the new arguments...
3635 // These operations are automatically eliminated by the prolog/epilog pass
3636 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
3637 SDValue CallSeqStart = Chain;
3639 // Load the return address and frame pointer so it can be moved somewhere else
3642 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
3645 // Set up a copy of the stack pointer for use loading and storing any
3646 // arguments that may not fit in the registers available for argument
3648 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3650 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3651 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3652 SmallVector<SDValue, 8> MemOpChains;
3654 bool seenFloatArg = false;
3655 // Walk the register/memloc assignments, inserting copies/loads.
3656 for (unsigned i = 0, j = 0, e = ArgLocs.size();
3659 CCValAssign &VA = ArgLocs[i];
3660 SDValue Arg = OutVals[i];
3661 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3663 if (Flags.isByVal()) {
3664 // Argument is an aggregate which is passed by value, thus we need to
3665 // create a copy of it in the local variable space of the current stack
3666 // frame (which is the stack frame of the caller) and pass the address of
3667 // this copy to the callee.
3668 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
3669 CCValAssign &ByValVA = ByValArgLocs[j++];
3670 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
3672 // Memory reserved in the local variable space of the callers stack frame.
3673 unsigned LocMemOffset = ByValVA.getLocMemOffset();
3675 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3676 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3678 // Create a copy of the argument in the local area of the current
3680 SDValue MemcpyCall =
3681 CreateCopyOfByValArgument(Arg, PtrOff,
3682 CallSeqStart.getNode()->getOperand(0),
3685 // This must go outside the CALLSEQ_START..END.
3686 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3687 CallSeqStart.getNode()->getOperand(1));
3688 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3689 NewCallSeqStart.getNode());
3690 Chain = CallSeqStart = NewCallSeqStart;
3692 // Pass the address of the aggregate copy on the stack either in a
3693 // physical register or in the parameter list area of the current stack
3694 // frame to the callee.
3698 if (VA.isRegLoc()) {
3699 seenFloatArg |= VA.getLocVT().isFloatingPoint();
3700 // Put argument in a physical register.
3701 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3703 // Put argument in the parameter list area of the current stack frame.
3704 assert(VA.isMemLoc());
3705 unsigned LocMemOffset = VA.getLocMemOffset();
3708 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3709 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3711 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3712 MachinePointerInfo(),
3715 // Calculate and remember argument location.
3716 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
3722 if (!MemOpChains.empty())
3723 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3724 &MemOpChains[0], MemOpChains.size());
3726 // Build a sequence of copy-to-reg nodes chained together with token chain
3727 // and flag operands which copy the outgoing args into the appropriate regs.
3729 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3730 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3731 RegsToPass[i].second, InFlag);
3732 InFlag = Chain.getValue(1);
3735 // Set CR bit 6 to true if this is a vararg call with floating args passed in
3738 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3739 SDValue Ops[] = { Chain, InFlag };
3741 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
3742 dl, VTs, Ops, InFlag.getNode() ? 2 : 1);
3744 InFlag = Chain.getValue(1);
3748 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
3749 false, TailCallArguments);
3751 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3752 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3756 // Copy an argument into memory, being careful to do this outside the
3757 // call sequence for the call to which the argument belongs.
3759 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
3760 SDValue CallSeqStart,
3761 ISD::ArgFlagsTy Flags,
3763 DebugLoc dl) const {
3764 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
3765 CallSeqStart.getNode()->getOperand(0),
3767 // The MEMCPY must go outside the CALLSEQ_START..END.
3768 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3769 CallSeqStart.getNode()->getOperand(1));
3770 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3771 NewCallSeqStart.getNode());
3772 return NewCallSeqStart;
3776 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
3777 CallingConv::ID CallConv, bool isVarArg,
3779 const SmallVectorImpl<ISD::OutputArg> &Outs,
3780 const SmallVectorImpl<SDValue> &OutVals,
3781 const SmallVectorImpl<ISD::InputArg> &Ins,
3782 DebugLoc dl, SelectionDAG &DAG,
3783 SmallVectorImpl<SDValue> &InVals) const {
3785 unsigned NumOps = Outs.size();
3787 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3788 unsigned PtrByteSize = 8;
3790 MachineFunction &MF = DAG.getMachineFunction();
3792 // Mark this function as potentially containing a function that contains a
3793 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3794 // and restoring the callers stack pointer in this functions epilog. This is
3795 // done because by tail calling the called function might overwrite the value
3796 // in this function's (MF) stack pointer stack slot 0(SP).
3797 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3798 CallConv == CallingConv::Fast)
3799 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3801 unsigned nAltivecParamsAtEnd = 0;
3803 // Count how many bytes are to be pushed on the stack, including the linkage
3804 // area, and parameter passing area. We start with at least 48 bytes, which
3805 // is reserved space for [SP][CR][LR][3 x unused].
3806 // NOTE: For PPC64, nAltivecParamsAtEnd always remains zero as a result
3809 CalculateParameterAndLinkageAreaSize(DAG, true, isVarArg, CallConv,
3810 Outs, OutVals, nAltivecParamsAtEnd);
3812 // Calculate by how many bytes the stack has to be adjusted in case of tail
3813 // call optimization.
3814 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3816 // To protect arguments on the stack from being clobbered in a tail call,
3817 // force all the loads to happen before doing any other lowering.
3819 Chain = DAG.getStackArgumentTokenFactor(Chain);
3821 // Adjust the stack pointer for the new arguments...
3822 // These operations are automatically eliminated by the prolog/epilog pass
3823 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
3824 SDValue CallSeqStart = Chain;
3826 // Load the return address and frame pointer so it can be move somewhere else
3829 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
3832 // Set up a copy of the stack pointer for use loading and storing any
3833 // arguments that may not fit in the registers available for argument
3835 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3837 // Figure out which arguments are going to go in registers, and which in
3838 // memory. Also, if this is a vararg function, floating point operations
3839 // must be stored to our stack, and loaded into integer regs as well, if
3840 // any integer regs are available for argument passing.
3841 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
3842 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3844 static const uint16_t GPR[] = {
3845 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3846 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3848 static const uint16_t *FPR = GetFPR();
3850 static const uint16_t VR[] = {
3851 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3852 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3854 const unsigned NumGPRs = array_lengthof(GPR);
3855 const unsigned NumFPRs = 13;
3856 const unsigned NumVRs = array_lengthof(VR);
3858 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3859 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3861 SmallVector<SDValue, 8> MemOpChains;
3862 for (unsigned i = 0; i != NumOps; ++i) {
3863 SDValue Arg = OutVals[i];
3864 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3866 // PtrOff will be used to store the current argument to the stack if a
3867 // register cannot be found for it.
3870 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
3872 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
3874 // Promote integers to 64-bit values.
3875 if (Arg.getValueType() == MVT::i32) {
3876 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
3877 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3878 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
3881 // FIXME memcpy is used way more than necessary. Correctness first.
3882 // Note: "by value" is code for passing a structure by value, not
3884 if (Flags.isByVal()) {
3885 // Note: Size includes alignment padding, so
3886 // struct x { short a; char b; }
3887 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
3888 // These are the proper values we need for right-justifying the
3889 // aggregate in a parameter register.
3890 unsigned Size = Flags.getByValSize();
3892 // An empty aggregate parameter takes up no storage and no
3897 // All aggregates smaller than 8 bytes must be passed right-justified.
3898 if (Size==1 || Size==2 || Size==4) {
3899 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
3900 if (GPR_idx != NumGPRs) {
3901 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
3902 MachinePointerInfo(), VT,
3904 MemOpChains.push_back(Load.getValue(1));
3905 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3907 ArgOffset += PtrByteSize;
3912 if (GPR_idx == NumGPRs && Size < 8) {
3913 SDValue Const = DAG.getConstant(PtrByteSize - Size,
3914 PtrOff.getValueType());
3915 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3916 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
3919 ArgOffset += PtrByteSize;
3922 // Copy entire object into memory. There are cases where gcc-generated
3923 // code assumes it is there, even if it could be put entirely into
3924 // registers. (This is not what the doc says.)
3926 // FIXME: The above statement is likely due to a misunderstanding of the
3927 // documents. All arguments must be copied into the parameter area BY
3928 // THE CALLEE in the event that the callee takes the address of any
3929 // formal argument. That has not yet been implemented. However, it is
3930 // reasonable to use the stack area as a staging area for the register
3933 // Skip this for small aggregates, as we will use the same slot for a
3934 // right-justified copy, below.
3936 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
3940 // When a register is available, pass a small aggregate right-justified.
3941 if (Size < 8 && GPR_idx != NumGPRs) {
3942 // The easiest way to get this right-justified in a register
3943 // is to copy the structure into the rightmost portion of a
3944 // local variable slot, then load the whole slot into the
3946 // FIXME: The memcpy seems to produce pretty awful code for
3947 // small aggregates, particularly for packed ones.
3948 // FIXME: It would be preferable to use the slot in the
3949 // parameter save area instead of a new local variable.
3950 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
3951 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3952 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
3956 // Load the slot into the register.
3957 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
3958 MachinePointerInfo(),
3959 false, false, false, 0);
3960 MemOpChains.push_back(Load.getValue(1));
3961 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3963 // Done with this argument.
3964 ArgOffset += PtrByteSize;
3968 // For aggregates larger than PtrByteSize, copy the pieces of the
3969 // object that fit into registers from the parameter save area.
3970 for (unsigned j=0; j<Size; j+=PtrByteSize) {
3971 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
3972 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
3973 if (GPR_idx != NumGPRs) {
3974 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
3975 MachinePointerInfo(),
3976 false, false, false, 0);
3977 MemOpChains.push_back(Load.getValue(1));
3978 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3979 ArgOffset += PtrByteSize;
3981 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
3988 switch (Arg.getValueType().getSimpleVT().SimpleTy) {
3989 default: llvm_unreachable("Unexpected ValueType for argument!");
3992 if (GPR_idx != NumGPRs) {
3993 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
3995 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3996 true, isTailCall, false, MemOpChains,
3997 TailCallArguments, dl);
3999 ArgOffset += PtrByteSize;
4003 if (FPR_idx != NumFPRs) {
4004 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4007 // A single float or an aggregate containing only a single float
4008 // must be passed right-justified in the stack doubleword, and
4009 // in the GPR, if one is available.
4011 if (Arg.getValueType().getSimpleVT().SimpleTy == MVT::f32) {
4012 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4013 StoreOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4017 SDValue Store = DAG.getStore(Chain, dl, Arg, StoreOff,
4018 MachinePointerInfo(), false, false, 0);
4019 MemOpChains.push_back(Store);
4021 // Float varargs are always shadowed in available integer registers
4022 if (GPR_idx != NumGPRs) {
4023 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4024 MachinePointerInfo(), false, false,
4026 MemOpChains.push_back(Load.getValue(1));
4027 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4029 } else if (GPR_idx != NumGPRs)
4030 // If we have any FPRs remaining, we may also have GPRs remaining.
4033 // Single-precision floating-point values are mapped to the
4034 // second (rightmost) word of the stack doubleword.
4035 if (Arg.getValueType() == MVT::f32) {
4036 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4037 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4040 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4041 true, isTailCall, false, MemOpChains,
4042 TailCallArguments, dl);
4051 // These go aligned on the stack, or in the corresponding R registers
4052 // when within range. The Darwin PPC ABI doc claims they also go in
4053 // V registers; in fact gcc does this only for arguments that are
4054 // prototyped, not for those that match the ... We do it for all
4055 // arguments, seems to work.
4056 while (ArgOffset % 16 !=0) {
4057 ArgOffset += PtrByteSize;
4058 if (GPR_idx != NumGPRs)
4061 // We could elide this store in the case where the object fits
4062 // entirely in R registers. Maybe later.
4063 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4064 DAG.getConstant(ArgOffset, PtrVT));
4065 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4066 MachinePointerInfo(), false, false, 0);
4067 MemOpChains.push_back(Store);
4068 if (VR_idx != NumVRs) {
4069 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4070 MachinePointerInfo(),
4071 false, false, false, 0);
4072 MemOpChains.push_back(Load.getValue(1));
4073 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4076 for (unsigned i=0; i<16; i+=PtrByteSize) {
4077 if (GPR_idx == NumGPRs)
4079 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4080 DAG.getConstant(i, PtrVT));
4081 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4082 false, false, false, 0);
4083 MemOpChains.push_back(Load.getValue(1));
4084 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4089 // Non-varargs Altivec params generally go in registers, but have
4090 // stack space allocated at the end.
4091 if (VR_idx != NumVRs) {
4092 // Doesn't have GPR space allocated.
4093 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4095 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4096 true, isTailCall, true, MemOpChains,
4097 TailCallArguments, dl);
4104 if (!MemOpChains.empty())
4105 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4106 &MemOpChains[0], MemOpChains.size());
4108 // Check if this is an indirect call (MTCTR/BCTRL).
4109 // See PrepareCall() for more information about calls through function
4110 // pointers in the 64-bit SVR4 ABI.
4112 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4113 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4114 !isBLACompatibleAddress(Callee, DAG)) {
4115 // Load r2 into a virtual register and store it to the TOC save area.
4116 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4117 // TOC save area offset.
4118 SDValue PtrOff = DAG.getIntPtrConstant(40);
4119 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4120 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
4122 // R12 must contain the address of an indirect callee. This does not
4123 // mean the MTCTR instruction must use R12; it's easier to model this
4124 // as an extra parameter, so do that.
4125 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
4128 // Build a sequence of copy-to-reg nodes chained together with token chain
4129 // and flag operands which copy the outgoing args into the appropriate regs.
4131 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4132 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4133 RegsToPass[i].second, InFlag);
4134 InFlag = Chain.getValue(1);
4138 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4139 FPOp, true, TailCallArguments);
4141 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4142 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4147 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4148 CallingConv::ID CallConv, bool isVarArg,
4150 const SmallVectorImpl<ISD::OutputArg> &Outs,
4151 const SmallVectorImpl<SDValue> &OutVals,
4152 const SmallVectorImpl<ISD::InputArg> &Ins,
4153 DebugLoc dl, SelectionDAG &DAG,
4154 SmallVectorImpl<SDValue> &InVals) const {
4156 unsigned NumOps = Outs.size();
4158 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4159 bool isPPC64 = PtrVT == MVT::i64;
4160 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4162 MachineFunction &MF = DAG.getMachineFunction();
4164 // Mark this function as potentially containing a function that contains a
4165 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4166 // and restoring the callers stack pointer in this functions epilog. This is
4167 // done because by tail calling the called function might overwrite the value
4168 // in this function's (MF) stack pointer stack slot 0(SP).
4169 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4170 CallConv == CallingConv::Fast)
4171 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4173 unsigned nAltivecParamsAtEnd = 0;
4175 // Count how many bytes are to be pushed on the stack, including the linkage
4176 // area, and parameter passing area. We start with 24/48 bytes, which is
4177 // prereserved space for [SP][CR][LR][3 x unused].
4179 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv,
4181 nAltivecParamsAtEnd);
4183 // Calculate by how many bytes the stack has to be adjusted in case of tail
4184 // call optimization.
4185 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4187 // To protect arguments on the stack from being clobbered in a tail call,
4188 // force all the loads to happen before doing any other lowering.
4190 Chain = DAG.getStackArgumentTokenFactor(Chain);
4192 // Adjust the stack pointer for the new arguments...
4193 // These operations are automatically eliminated by the prolog/epilog pass
4194 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
4195 SDValue CallSeqStart = Chain;
4197 // Load the return address and frame pointer so it can be move somewhere else
4200 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4203 // Set up a copy of the stack pointer for use loading and storing any
4204 // arguments that may not fit in the registers available for argument
4208 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4210 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4212 // Figure out which arguments are going to go in registers, and which in
4213 // memory. Also, if this is a vararg function, floating point operations
4214 // must be stored to our stack, and loaded into integer regs as well, if
4215 // any integer regs are available for argument passing.
4216 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
4217 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4219 static const uint16_t GPR_32[] = { // 32-bit registers.
4220 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4221 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4223 static const uint16_t GPR_64[] = { // 64-bit registers.
4224 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4225 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4227 static const uint16_t *FPR = GetFPR();
4229 static const uint16_t VR[] = {
4230 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4231 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4233 const unsigned NumGPRs = array_lengthof(GPR_32);
4234 const unsigned NumFPRs = 13;
4235 const unsigned NumVRs = array_lengthof(VR);
4237 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
4239 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4240 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4242 SmallVector<SDValue, 8> MemOpChains;
4243 for (unsigned i = 0; i != NumOps; ++i) {
4244 SDValue Arg = OutVals[i];
4245 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4247 // PtrOff will be used to store the current argument to the stack if a
4248 // register cannot be found for it.
4251 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4253 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4255 // On PPC64, promote integers to 64-bit values.
4256 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4257 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4258 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4259 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4262 // FIXME memcpy is used way more than necessary. Correctness first.
4263 // Note: "by value" is code for passing a structure by value, not
4265 if (Flags.isByVal()) {
4266 unsigned Size = Flags.getByValSize();
4267 // Very small objects are passed right-justified. Everything else is
4268 // passed left-justified.
4269 if (Size==1 || Size==2) {
4270 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4271 if (GPR_idx != NumGPRs) {
4272 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4273 MachinePointerInfo(), VT,
4275 MemOpChains.push_back(Load.getValue(1));
4276 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4278 ArgOffset += PtrByteSize;
4280 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4281 PtrOff.getValueType());
4282 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4283 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4286 ArgOffset += PtrByteSize;
4290 // Copy entire object into memory. There are cases where gcc-generated
4291 // code assumes it is there, even if it could be put entirely into
4292 // registers. (This is not what the doc says.)
4293 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4297 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4298 // copy the pieces of the object that fit into registers from the
4299 // parameter save area.
4300 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4301 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4302 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4303 if (GPR_idx != NumGPRs) {
4304 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4305 MachinePointerInfo(),
4306 false, false, false, 0);
4307 MemOpChains.push_back(Load.getValue(1));
4308 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4309 ArgOffset += PtrByteSize;
4311 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4318 switch (Arg.getValueType().getSimpleVT().SimpleTy) {
4319 default: llvm_unreachable("Unexpected ValueType for argument!");
4322 if (GPR_idx != NumGPRs) {
4323 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4325 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4326 isPPC64, isTailCall, false, MemOpChains,
4327 TailCallArguments, dl);
4329 ArgOffset += PtrByteSize;
4333 if (FPR_idx != NumFPRs) {
4334 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4337 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4338 MachinePointerInfo(), false, false, 0);
4339 MemOpChains.push_back(Store);
4341 // Float varargs are always shadowed in available integer registers
4342 if (GPR_idx != NumGPRs) {
4343 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4344 MachinePointerInfo(), false, false,
4346 MemOpChains.push_back(Load.getValue(1));
4347 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4349 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4350 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4351 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4352 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4353 MachinePointerInfo(),
4354 false, false, false, 0);
4355 MemOpChains.push_back(Load.getValue(1));
4356 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4359 // If we have any FPRs remaining, we may also have GPRs remaining.
4360 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4362 if (GPR_idx != NumGPRs)
4364 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4365 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4369 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4370 isPPC64, isTailCall, false, MemOpChains,
4371 TailCallArguments, dl);
4375 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4382 // These go aligned on the stack, or in the corresponding R registers
4383 // when within range. The Darwin PPC ABI doc claims they also go in
4384 // V registers; in fact gcc does this only for arguments that are
4385 // prototyped, not for those that match the ... We do it for all
4386 // arguments, seems to work.
4387 while (ArgOffset % 16 !=0) {
4388 ArgOffset += PtrByteSize;
4389 if (GPR_idx != NumGPRs)
4392 // We could elide this store in the case where the object fits
4393 // entirely in R registers. Maybe later.
4394 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4395 DAG.getConstant(ArgOffset, PtrVT));
4396 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4397 MachinePointerInfo(), false, false, 0);
4398 MemOpChains.push_back(Store);
4399 if (VR_idx != NumVRs) {
4400 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4401 MachinePointerInfo(),
4402 false, false, false, 0);
4403 MemOpChains.push_back(Load.getValue(1));
4404 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4407 for (unsigned i=0; i<16; i+=PtrByteSize) {
4408 if (GPR_idx == NumGPRs)
4410 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4411 DAG.getConstant(i, PtrVT));
4412 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4413 false, false, false, 0);
4414 MemOpChains.push_back(Load.getValue(1));
4415 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4420 // Non-varargs Altivec params generally go in registers, but have
4421 // stack space allocated at the end.
4422 if (VR_idx != NumVRs) {
4423 // Doesn't have GPR space allocated.
4424 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4425 } else if (nAltivecParamsAtEnd==0) {
4426 // We are emitting Altivec params in order.
4427 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4428 isPPC64, isTailCall, true, MemOpChains,
4429 TailCallArguments, dl);
4435 // If all Altivec parameters fit in registers, as they usually do,
4436 // they get stack space following the non-Altivec parameters. We
4437 // don't track this here because nobody below needs it.
4438 // If there are more Altivec parameters than fit in registers emit
4440 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
4442 // Offset is aligned; skip 1st 12 params which go in V registers.
4443 ArgOffset = ((ArgOffset+15)/16)*16;
4445 for (unsigned i = 0; i != NumOps; ++i) {
4446 SDValue Arg = OutVals[i];
4447 EVT ArgType = Outs[i].VT;
4448 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
4449 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
4452 // We are emitting Altivec params in order.
4453 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4454 isPPC64, isTailCall, true, MemOpChains,
4455 TailCallArguments, dl);
4462 if (!MemOpChains.empty())
4463 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4464 &MemOpChains[0], MemOpChains.size());
4466 // On Darwin, R12 must contain the address of an indirect callee. This does
4467 // not mean the MTCTR instruction must use R12; it's easier to model this as
4468 // an extra parameter, so do that.
4470 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4471 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4472 !isBLACompatibleAddress(Callee, DAG))
4473 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
4474 PPC::R12), Callee));
4476 // Build a sequence of copy-to-reg nodes chained together with token chain
4477 // and flag operands which copy the outgoing args into the appropriate regs.
4479 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4480 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4481 RegsToPass[i].second, InFlag);
4482 InFlag = Chain.getValue(1);
4486 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
4487 FPOp, true, TailCallArguments);
4489 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4490 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4495 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
4496 MachineFunction &MF, bool isVarArg,
4497 const SmallVectorImpl<ISD::OutputArg> &Outs,
4498 LLVMContext &Context) const {
4499 SmallVector<CCValAssign, 16> RVLocs;
4500 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
4502 return CCInfo.CheckReturn(Outs, RetCC_PPC);
4506 PPCTargetLowering::LowerReturn(SDValue Chain,
4507 CallingConv::ID CallConv, bool isVarArg,
4508 const SmallVectorImpl<ISD::OutputArg> &Outs,
4509 const SmallVectorImpl<SDValue> &OutVals,
4510 DebugLoc dl, SelectionDAG &DAG) const {
4512 SmallVector<CCValAssign, 16> RVLocs;
4513 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4514 getTargetMachine(), RVLocs, *DAG.getContext());
4515 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
4518 SmallVector<SDValue, 4> RetOps(1, Chain);
4520 // Copy the result values into the output registers.
4521 for (unsigned i = 0; i != RVLocs.size(); ++i) {
4522 CCValAssign &VA = RVLocs[i];
4523 assert(VA.isRegLoc() && "Can only return in registers!");
4525 SDValue Arg = OutVals[i];
4527 switch (VA.getLocInfo()) {
4528 default: llvm_unreachable("Unknown loc info!");
4529 case CCValAssign::Full: break;
4530 case CCValAssign::AExt:
4531 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
4533 case CCValAssign::ZExt:
4534 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
4536 case CCValAssign::SExt:
4537 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
4541 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
4542 Flag = Chain.getValue(1);
4543 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
4546 RetOps[0] = Chain; // Update chain.
4548 // Add the flag if we have it.
4550 RetOps.push_back(Flag);
4552 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other,
4553 &RetOps[0], RetOps.size());
4556 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
4557 const PPCSubtarget &Subtarget) const {
4558 // When we pop the dynamic allocation we need to restore the SP link.
4559 DebugLoc dl = Op.getDebugLoc();
4561 // Get the corect type for pointers.
4562 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4564 // Construct the stack pointer operand.
4565 bool isPPC64 = Subtarget.isPPC64();
4566 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
4567 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
4569 // Get the operands for the STACKRESTORE.
4570 SDValue Chain = Op.getOperand(0);
4571 SDValue SaveSP = Op.getOperand(1);
4573 // Load the old link SP.
4574 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
4575 MachinePointerInfo(),
4576 false, false, false, 0);
4578 // Restore the stack pointer.
4579 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
4581 // Store the old link SP.
4582 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
4589 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
4590 MachineFunction &MF = DAG.getMachineFunction();
4591 bool isPPC64 = PPCSubTarget.isPPC64();
4592 bool isDarwinABI = PPCSubTarget.isDarwinABI();
4593 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4595 // Get current frame pointer save index. The users of this index will be
4596 // primarily DYNALLOC instructions.
4597 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4598 int RASI = FI->getReturnAddrSaveIndex();
4600 // If the frame pointer save index hasn't been defined yet.
4602 // Find out what the fix offset of the frame pointer save area.
4603 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
4604 // Allocate the frame index for frame pointer save area.
4605 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
4607 FI->setReturnAddrSaveIndex(RASI);
4609 return DAG.getFrameIndex(RASI, PtrVT);
4613 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
4614 MachineFunction &MF = DAG.getMachineFunction();
4615 bool isPPC64 = PPCSubTarget.isPPC64();
4616 bool isDarwinABI = PPCSubTarget.isDarwinABI();
4617 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4619 // Get current frame pointer save index. The users of this index will be
4620 // primarily DYNALLOC instructions.
4621 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4622 int FPSI = FI->getFramePointerSaveIndex();
4624 // If the frame pointer save index hasn't been defined yet.
4626 // Find out what the fix offset of the frame pointer save area.
4627 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
4630 // Allocate the frame index for frame pointer save area.
4631 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
4633 FI->setFramePointerSaveIndex(FPSI);
4635 return DAG.getFrameIndex(FPSI, PtrVT);
4638 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
4640 const PPCSubtarget &Subtarget) const {
4642 SDValue Chain = Op.getOperand(0);
4643 SDValue Size = Op.getOperand(1);
4644 DebugLoc dl = Op.getDebugLoc();
4646 // Get the corect type for pointers.
4647 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4649 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
4650 DAG.getConstant(0, PtrVT), Size);
4651 // Construct a node for the frame pointer save index.
4652 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
4653 // Build a DYNALLOC node.
4654 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
4655 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
4656 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3);
4659 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
4660 SelectionDAG &DAG) const {
4661 DebugLoc DL = Op.getDebugLoc();
4662 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
4663 DAG.getVTList(MVT::i32, MVT::Other),
4664 Op.getOperand(0), Op.getOperand(1));
4667 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
4668 SelectionDAG &DAG) const {
4669 DebugLoc DL = Op.getDebugLoc();
4670 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
4671 Op.getOperand(0), Op.getOperand(1));
4674 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
4676 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
4677 // Not FP? Not a fsel.
4678 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
4679 !Op.getOperand(2).getValueType().isFloatingPoint())
4682 // We might be able to do better than this under some circumstances, but in
4683 // general, fsel-based lowering of select is a finite-math-only optimization.
4684 // For more information, see section F.3 of the 2.06 ISA specification.
4685 if (!DAG.getTarget().Options.NoInfsFPMath ||
4686 !DAG.getTarget().Options.NoNaNsFPMath)
4689 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4691 EVT ResVT = Op.getValueType();
4692 EVT CmpVT = Op.getOperand(0).getValueType();
4693 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4694 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
4695 DebugLoc dl = Op.getDebugLoc();
4697 // If the RHS of the comparison is a 0.0, we don't need to do the
4698 // subtraction at all.
4700 if (isFloatingPointZero(RHS))
4702 default: break; // SETUO etc aren't handled by fsel.
4706 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4707 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4708 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
4709 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
4710 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
4711 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4712 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
4715 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
4718 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4719 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4720 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
4723 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
4726 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4727 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4728 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4729 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
4734 default: break; // SETUO etc aren't handled by fsel.
4738 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4739 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4740 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4741 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4742 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
4743 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
4744 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4745 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
4748 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4749 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4750 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4751 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
4754 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4755 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4756 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4757 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4760 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
4761 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4762 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4763 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
4766 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
4767 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4768 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4769 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4774 // FIXME: Split this code up when LegalizeDAGTypes lands.
4775 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
4776 DebugLoc dl) const {
4777 assert(Op.getOperand(0).getValueType().isFloatingPoint());
4778 SDValue Src = Op.getOperand(0);
4779 if (Src.getValueType() == MVT::f32)
4780 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
4783 switch (Op.getValueType().getSimpleVT().SimpleTy) {
4784 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
4786 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
4787 (PPCSubTarget.hasFPCVT() ? PPCISD::FCTIWUZ :
4792 assert((Op.getOpcode() == ISD::FP_TO_SINT || PPCSubTarget.hasFPCVT()) &&
4793 "i64 FP_TO_UINT is supported only with FPCVT");
4794 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
4800 // Convert the FP value to an int value through memory.
4801 bool i32Stack = Op.getValueType() == MVT::i32 && PPCSubTarget.hasSTFIWX() &&
4802 (Op.getOpcode() == ISD::FP_TO_SINT || PPCSubTarget.hasFPCVT());
4803 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
4804 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
4805 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
4807 // Emit a store to the stack slot.
4810 MachineFunction &MF = DAG.getMachineFunction();
4811 MachineMemOperand *MMO =
4812 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
4813 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
4814 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
4815 DAG.getVTList(MVT::Other), Ops, array_lengthof(Ops),
4818 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
4819 MPI, false, false, 0);
4821 // Result is a load from the stack slot. If loading 4 bytes, make sure to
4823 if (Op.getValueType() == MVT::i32 && !i32Stack) {
4824 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
4825 DAG.getConstant(4, FIPtr.getValueType()));
4826 MPI = MachinePointerInfo();
4829 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MPI,
4830 false, false, false, 0);
4833 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
4834 SelectionDAG &DAG) const {
4835 DebugLoc dl = Op.getDebugLoc();
4836 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
4837 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
4840 assert((Op.getOpcode() == ISD::SINT_TO_FP || PPCSubTarget.hasFPCVT()) &&
4841 "UINT_TO_FP is supported only with FPCVT");
4843 // If we have FCFIDS, then use it when converting to single-precision.
4844 // Otherwise, convert to double-precision and then round.
4845 unsigned FCFOp = (PPCSubTarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
4846 (Op.getOpcode() == ISD::UINT_TO_FP ?
4847 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
4848 (Op.getOpcode() == ISD::UINT_TO_FP ?
4849 PPCISD::FCFIDU : PPCISD::FCFID);
4850 MVT FCFTy = (PPCSubTarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
4851 MVT::f32 : MVT::f64;
4853 if (Op.getOperand(0).getValueType() == MVT::i64) {
4854 SDValue SINT = Op.getOperand(0);
4855 // When converting to single-precision, we actually need to convert
4856 // to double-precision first and then round to single-precision.
4857 // To avoid double-rounding effects during that operation, we have
4858 // to prepare the input operand. Bits that might be truncated when
4859 // converting to double-precision are replaced by a bit that won't
4860 // be lost at this stage, but is below the single-precision rounding
4863 // However, if -enable-unsafe-fp-math is in effect, accept double
4864 // rounding to avoid the extra overhead.
4865 if (Op.getValueType() == MVT::f32 &&
4866 !PPCSubTarget.hasFPCVT() &&
4867 !DAG.getTarget().Options.UnsafeFPMath) {
4869 // Twiddle input to make sure the low 11 bits are zero. (If this
4870 // is the case, we are guaranteed the value will fit into the 53 bit
4871 // mantissa of an IEEE double-precision value without rounding.)
4872 // If any of those low 11 bits were not zero originally, make sure
4873 // bit 12 (value 2048) is set instead, so that the final rounding
4874 // to single-precision gets the correct result.
4875 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
4876 SINT, DAG.getConstant(2047, MVT::i64));
4877 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
4878 Round, DAG.getConstant(2047, MVT::i64));
4879 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
4880 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
4881 Round, DAG.getConstant(-2048, MVT::i64));
4883 // However, we cannot use that value unconditionally: if the magnitude
4884 // of the input value is small, the bit-twiddling we did above might
4885 // end up visibly changing the output. Fortunately, in that case, we
4886 // don't need to twiddle bits since the original input will convert
4887 // exactly to double-precision floating-point already. Therefore,
4888 // construct a conditional to use the original value if the top 11
4889 // bits are all sign-bit copies, and use the rounded value computed
4891 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
4892 SINT, DAG.getConstant(53, MVT::i32));
4893 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
4894 Cond, DAG.getConstant(1, MVT::i64));
4895 Cond = DAG.getSetCC(dl, MVT::i32,
4896 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
4898 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
4901 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
4902 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
4904 if (Op.getValueType() == MVT::f32 && !PPCSubTarget.hasFPCVT())
4905 FP = DAG.getNode(ISD::FP_ROUND, dl,
4906 MVT::f32, FP, DAG.getIntPtrConstant(0));
4910 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
4911 "Unhandled INT_TO_FP type in custom expander!");
4912 // Since we only generate this in 64-bit mode, we can take advantage of
4913 // 64-bit registers. In particular, sign extend the input value into the
4914 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
4915 // then lfd it and fcfid it.
4916 MachineFunction &MF = DAG.getMachineFunction();
4917 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
4918 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4921 if (PPCSubTarget.hasLFIWAX() || PPCSubTarget.hasFPCVT()) {
4922 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
4923 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4925 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
4926 MachinePointerInfo::getFixedStack(FrameIdx),
4929 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
4930 "Expected an i32 store");
4931 MachineMemOperand *MMO =
4932 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
4933 MachineMemOperand::MOLoad, 4, 4);
4934 SDValue Ops[] = { Store, FIdx };
4935 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
4936 PPCISD::LFIWZX : PPCISD::LFIWAX,
4937 dl, DAG.getVTList(MVT::f64, MVT::Other),
4938 Ops, 2, MVT::i32, MMO);
4940 assert(PPCSubTarget.isPPC64() &&
4941 "i32->FP without LFIWAX supported only on PPC64");
4943 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
4944 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4946 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
4949 // STD the extended value into the stack slot.
4950 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
4951 MachinePointerInfo::getFixedStack(FrameIdx),
4954 // Load the value as a double.
4955 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
4956 MachinePointerInfo::getFixedStack(FrameIdx),
4957 false, false, false, 0);
4960 // FCFID it and return it.
4961 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
4962 if (Op.getValueType() == MVT::f32 && !PPCSubTarget.hasFPCVT())
4963 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
4967 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
4968 SelectionDAG &DAG) const {
4969 DebugLoc dl = Op.getDebugLoc();
4971 The rounding mode is in bits 30:31 of FPSR, and has the following
4978 FLT_ROUNDS, on the other hand, expects the following:
4985 To perform the conversion, we do:
4986 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
4989 MachineFunction &MF = DAG.getMachineFunction();
4990 EVT VT = Op.getValueType();
4991 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4992 SDValue MFFSreg, InFlag;
4994 // Save FP Control Word to register
4996 MVT::f64, // return register
4997 MVT::Glue // unused in this context
4999 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
5001 // Save FP register to stack slot
5002 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5003 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
5004 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
5005 StackSlot, MachinePointerInfo(), false, false,0);
5007 // Load FP Control Word from low 32 bits of stack slot.
5008 SDValue Four = DAG.getConstant(4, PtrVT);
5009 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
5010 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
5011 false, false, false, 0);
5013 // Transform as necessary
5015 DAG.getNode(ISD::AND, dl, MVT::i32,
5016 CWD, DAG.getConstant(3, MVT::i32));
5018 DAG.getNode(ISD::SRL, dl, MVT::i32,
5019 DAG.getNode(ISD::AND, dl, MVT::i32,
5020 DAG.getNode(ISD::XOR, dl, MVT::i32,
5021 CWD, DAG.getConstant(3, MVT::i32)),
5022 DAG.getConstant(3, MVT::i32)),
5023 DAG.getConstant(1, MVT::i32));
5026 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
5028 return DAG.getNode((VT.getSizeInBits() < 16 ?
5029 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
5032 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5033 EVT VT = Op.getValueType();
5034 unsigned BitWidth = VT.getSizeInBits();
5035 DebugLoc dl = Op.getDebugLoc();
5036 assert(Op.getNumOperands() == 3 &&
5037 VT == Op.getOperand(1).getValueType() &&
5040 // Expand into a bunch of logical ops. Note that these ops
5041 // depend on the PPC behavior for oversized shift amounts.
5042 SDValue Lo = Op.getOperand(0);
5043 SDValue Hi = Op.getOperand(1);
5044 SDValue Amt = Op.getOperand(2);
5045 EVT AmtVT = Amt.getValueType();
5047 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5048 DAG.getConstant(BitWidth, AmtVT), Amt);
5049 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
5050 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5051 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5052 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5053 DAG.getConstant(-BitWidth, AmtVT));
5054 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5055 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5056 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
5057 SDValue OutOps[] = { OutLo, OutHi };
5058 return DAG.getMergeValues(OutOps, 2, dl);
5061 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5062 EVT VT = Op.getValueType();
5063 DebugLoc dl = Op.getDebugLoc();
5064 unsigned BitWidth = VT.getSizeInBits();
5065 assert(Op.getNumOperands() == 3 &&
5066 VT == Op.getOperand(1).getValueType() &&
5069 // Expand into a bunch of logical ops. Note that these ops
5070 // depend on the PPC behavior for oversized shift amounts.
5071 SDValue Lo = Op.getOperand(0);
5072 SDValue Hi = Op.getOperand(1);
5073 SDValue Amt = Op.getOperand(2);
5074 EVT AmtVT = Amt.getValueType();
5076 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5077 DAG.getConstant(BitWidth, AmtVT), Amt);
5078 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5079 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5080 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5081 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5082 DAG.getConstant(-BitWidth, AmtVT));
5083 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
5084 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5085 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
5086 SDValue OutOps[] = { OutLo, OutHi };
5087 return DAG.getMergeValues(OutOps, 2, dl);
5090 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
5091 DebugLoc dl = Op.getDebugLoc();
5092 EVT VT = Op.getValueType();
5093 unsigned BitWidth = VT.getSizeInBits();
5094 assert(Op.getNumOperands() == 3 &&
5095 VT == Op.getOperand(1).getValueType() &&
5098 // Expand into a bunch of logical ops, followed by a select_cc.
5099 SDValue Lo = Op.getOperand(0);
5100 SDValue Hi = Op.getOperand(1);
5101 SDValue Amt = Op.getOperand(2);
5102 EVT AmtVT = Amt.getValueType();
5104 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5105 DAG.getConstant(BitWidth, AmtVT), Amt);
5106 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5107 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5108 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5109 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5110 DAG.getConstant(-BitWidth, AmtVT));
5111 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
5112 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
5113 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
5114 Tmp4, Tmp6, ISD::SETLE);
5115 SDValue OutOps[] = { OutLo, OutHi };
5116 return DAG.getMergeValues(OutOps, 2, dl);
5119 //===----------------------------------------------------------------------===//
5120 // Vector related lowering.
5123 /// BuildSplatI - Build a canonical splati of Val with an element size of
5124 /// SplatSize. Cast the result to VT.
5125 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
5126 SelectionDAG &DAG, DebugLoc dl) {
5127 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
5129 static const EVT VTys[] = { // canonical VT to use for each size.
5130 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
5133 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
5135 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
5139 EVT CanonicalVT = VTys[SplatSize-1];
5141 // Build a canonical splat for this value.
5142 SDValue Elt = DAG.getConstant(Val, MVT::i32);
5143 SmallVector<SDValue, 8> Ops;
5144 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
5145 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
5146 &Ops[0], Ops.size());
5147 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
5150 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
5151 /// specified intrinsic ID.
5152 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
5153 SelectionDAG &DAG, DebugLoc dl,
5154 EVT DestVT = MVT::Other) {
5155 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
5156 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5157 DAG.getConstant(IID, MVT::i32), LHS, RHS);
5160 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
5161 /// specified intrinsic ID.
5162 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
5163 SDValue Op2, SelectionDAG &DAG,
5164 DebugLoc dl, EVT DestVT = MVT::Other) {
5165 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
5166 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5167 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
5171 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
5172 /// amount. The result has the specified value type.
5173 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
5174 EVT VT, SelectionDAG &DAG, DebugLoc dl) {
5175 // Force LHS/RHS to be the right type.
5176 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
5177 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
5180 for (unsigned i = 0; i != 16; ++i)
5182 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
5183 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5186 // If this is a case we can't handle, return null and let the default
5187 // expansion code take care of it. If we CAN select this case, and if it
5188 // selects to a single instruction, return Op. Otherwise, if we can codegen
5189 // this case more efficiently than a constant pool load, lower it to the
5190 // sequence of ops that should be used.
5191 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
5192 SelectionDAG &DAG) const {
5193 DebugLoc dl = Op.getDebugLoc();
5194 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5195 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
5197 // Check if this is a splat of a constant value.
5198 APInt APSplatBits, APSplatUndef;
5199 unsigned SplatBitSize;
5201 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
5202 HasAnyUndefs, 0, true) || SplatBitSize > 32)
5205 unsigned SplatBits = APSplatBits.getZExtValue();
5206 unsigned SplatUndef = APSplatUndef.getZExtValue();
5207 unsigned SplatSize = SplatBitSize / 8;
5209 // First, handle single instruction cases.
5212 if (SplatBits == 0) {
5213 // Canonicalize all zero vectors to be v4i32.
5214 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5215 SDValue Z = DAG.getConstant(0, MVT::i32);
5216 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5217 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
5222 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
5223 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
5225 if (SextVal >= -16 && SextVal <= 15)
5226 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
5229 // Two instruction sequences.
5231 // If this value is in the range [-32,30] and is even, use:
5232 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
5233 // If this value is in the range [17,31] and is odd, use:
5234 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
5235 // If this value is in the range [-31,-17] and is odd, use:
5236 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
5237 // Note the last two are three-instruction sequences.
5238 if (SextVal >= -32 && SextVal <= 31) {
5239 // To avoid having these optimizations undone by constant folding,
5240 // we convert to a pseudo that will be expanded later into one of
5242 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
5243 EVT VT = Op.getValueType();
5244 int Size = VT == MVT::v16i8 ? 1 : (VT == MVT::v8i16 ? 2 : 4);
5245 SDValue EltSize = DAG.getConstant(Size, MVT::i32);
5246 return DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
5249 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
5250 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
5252 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
5253 // Make -1 and vspltisw -1:
5254 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
5256 // Make the VSLW intrinsic, computing 0x8000_0000.
5257 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
5260 // xor by OnesV to invert it.
5261 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5262 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5265 // Check to see if this is a wide variety of vsplti*, binop self cases.
5266 static const signed char SplatCsts[] = {
5267 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
5268 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
5271 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
5272 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
5273 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
5274 int i = SplatCsts[idx];
5276 // Figure out what shift amount will be used by altivec if shifted by i in
5278 unsigned TypeShiftAmt = i & (SplatBitSize-1);
5280 // vsplti + shl self.
5281 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
5282 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5283 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5284 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
5285 Intrinsic::ppc_altivec_vslw
5287 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5288 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5291 // vsplti + srl self.
5292 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5293 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5294 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5295 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
5296 Intrinsic::ppc_altivec_vsrw
5298 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5299 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5302 // vsplti + sra self.
5303 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5304 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5305 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5306 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
5307 Intrinsic::ppc_altivec_vsraw
5309 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5310 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5313 // vsplti + rol self.
5314 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
5315 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
5316 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5317 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5318 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
5319 Intrinsic::ppc_altivec_vrlw
5321 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5322 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5325 // t = vsplti c, result = vsldoi t, t, 1
5326 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
5327 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5328 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
5330 // t = vsplti c, result = vsldoi t, t, 2
5331 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
5332 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5333 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
5335 // t = vsplti c, result = vsldoi t, t, 3
5336 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
5337 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5338 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
5345 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5346 /// the specified operations to build the shuffle.
5347 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5348 SDValue RHS, SelectionDAG &DAG,
5350 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5351 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5352 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5355 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5367 if (OpNum == OP_COPY) {
5368 if (LHSID == (1*9+2)*9+3) return LHS;
5369 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5373 SDValue OpLHS, OpRHS;
5374 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5375 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5379 default: llvm_unreachable("Unknown i32 permute!");
5381 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
5382 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
5383 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
5384 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
5387 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
5388 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
5389 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
5390 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
5393 for (unsigned i = 0; i != 16; ++i)
5394 ShufIdxs[i] = (i&3)+0;
5397 for (unsigned i = 0; i != 16; ++i)
5398 ShufIdxs[i] = (i&3)+4;
5401 for (unsigned i = 0; i != 16; ++i)
5402 ShufIdxs[i] = (i&3)+8;
5405 for (unsigned i = 0; i != 16; ++i)
5406 ShufIdxs[i] = (i&3)+12;
5409 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
5411 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
5413 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
5415 EVT VT = OpLHS.getValueType();
5416 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
5417 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
5418 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
5419 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5422 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
5423 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
5424 /// return the code it can be lowered into. Worst case, it can always be
5425 /// lowered into a vperm.
5426 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5427 SelectionDAG &DAG) const {
5428 DebugLoc dl = Op.getDebugLoc();
5429 SDValue V1 = Op.getOperand(0);
5430 SDValue V2 = Op.getOperand(1);
5431 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5432 EVT VT = Op.getValueType();
5434 // Cases that are handled by instructions that take permute immediates
5435 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
5436 // selected by the instruction selector.
5437 if (V2.getOpcode() == ISD::UNDEF) {
5438 if (PPC::isSplatShuffleMask(SVOp, 1) ||
5439 PPC::isSplatShuffleMask(SVOp, 2) ||
5440 PPC::isSplatShuffleMask(SVOp, 4) ||
5441 PPC::isVPKUWUMShuffleMask(SVOp, true) ||
5442 PPC::isVPKUHUMShuffleMask(SVOp, true) ||
5443 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 ||
5444 PPC::isVMRGLShuffleMask(SVOp, 1, true) ||
5445 PPC::isVMRGLShuffleMask(SVOp, 2, true) ||
5446 PPC::isVMRGLShuffleMask(SVOp, 4, true) ||
5447 PPC::isVMRGHShuffleMask(SVOp, 1, true) ||
5448 PPC::isVMRGHShuffleMask(SVOp, 2, true) ||
5449 PPC::isVMRGHShuffleMask(SVOp, 4, true)) {
5454 // Altivec has a variety of "shuffle immediates" that take two vector inputs
5455 // and produce a fixed permutation. If any of these match, do not lower to
5457 if (PPC::isVPKUWUMShuffleMask(SVOp, false) ||
5458 PPC::isVPKUHUMShuffleMask(SVOp, false) ||
5459 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 ||
5460 PPC::isVMRGLShuffleMask(SVOp, 1, false) ||
5461 PPC::isVMRGLShuffleMask(SVOp, 2, false) ||
5462 PPC::isVMRGLShuffleMask(SVOp, 4, false) ||
5463 PPC::isVMRGHShuffleMask(SVOp, 1, false) ||
5464 PPC::isVMRGHShuffleMask(SVOp, 2, false) ||
5465 PPC::isVMRGHShuffleMask(SVOp, 4, false))
5468 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
5469 // perfect shuffle table to emit an optimal matching sequence.
5470 ArrayRef<int> PermMask = SVOp->getMask();
5472 unsigned PFIndexes[4];
5473 bool isFourElementShuffle = true;
5474 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
5475 unsigned EltNo = 8; // Start out undef.
5476 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
5477 if (PermMask[i*4+j] < 0)
5478 continue; // Undef, ignore it.
5480 unsigned ByteSource = PermMask[i*4+j];
5481 if ((ByteSource & 3) != j) {
5482 isFourElementShuffle = false;
5487 EltNo = ByteSource/4;
5488 } else if (EltNo != ByteSource/4) {
5489 isFourElementShuffle = false;
5493 PFIndexes[i] = EltNo;
5496 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
5497 // perfect shuffle vector to determine if it is cost effective to do this as
5498 // discrete instructions, or whether we should use a vperm.
5499 if (isFourElementShuffle) {
5500 // Compute the index in the perfect shuffle table.
5501 unsigned PFTableIndex =
5502 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5504 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5505 unsigned Cost = (PFEntry >> 30);
5507 // Determining when to avoid vperm is tricky. Many things affect the cost
5508 // of vperm, particularly how many times the perm mask needs to be computed.
5509 // For example, if the perm mask can be hoisted out of a loop or is already
5510 // used (perhaps because there are multiple permutes with the same shuffle
5511 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
5512 // the loop requires an extra register.
5514 // As a compromise, we only emit discrete instructions if the shuffle can be
5515 // generated in 3 or fewer operations. When we have loop information
5516 // available, if this block is within a loop, we should avoid using vperm
5517 // for 3-operation perms and use a constant pool load instead.
5519 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5522 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
5523 // vector that will get spilled to the constant pool.
5524 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
5526 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
5527 // that it is in input element units, not in bytes. Convert now.
5528 EVT EltVT = V1.getValueType().getVectorElementType();
5529 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
5531 SmallVector<SDValue, 16> ResultMask;
5532 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
5533 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
5535 for (unsigned j = 0; j != BytesPerElement; ++j)
5536 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
5540 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
5541 &ResultMask[0], ResultMask.size());
5542 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
5545 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
5546 /// altivec comparison. If it is, return true and fill in Opc/isDot with
5547 /// information about the intrinsic.
5548 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
5550 unsigned IntrinsicID =
5551 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
5554 switch (IntrinsicID) {
5555 default: return false;
5556 // Comparison predicates.
5557 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
5558 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
5559 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
5560 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
5561 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
5562 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
5563 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
5564 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
5565 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
5566 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
5567 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
5568 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
5569 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
5571 // Normal Comparisons.
5572 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
5573 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
5574 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
5575 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
5576 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
5577 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
5578 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
5579 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
5580 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
5581 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
5582 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
5583 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
5584 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
5589 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
5590 /// lower, do it, otherwise return null.
5591 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
5592 SelectionDAG &DAG) const {
5593 // If this is a lowered altivec predicate compare, CompareOpc is set to the
5594 // opcode number of the comparison.
5595 DebugLoc dl = Op.getDebugLoc();
5598 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
5599 return SDValue(); // Don't custom lower most intrinsics.
5601 // If this is a non-dot comparison, make the VCMP node and we are done.
5603 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
5604 Op.getOperand(1), Op.getOperand(2),
5605 DAG.getConstant(CompareOpc, MVT::i32));
5606 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
5609 // Create the PPCISD altivec 'dot' comparison node.
5611 Op.getOperand(2), // LHS
5612 Op.getOperand(3), // RHS
5613 DAG.getConstant(CompareOpc, MVT::i32)
5615 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
5616 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
5618 // Now that we have the comparison, emit a copy from the CR to a GPR.
5619 // This is flagged to the above dot comparison.
5620 SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32,
5621 DAG.getRegister(PPC::CR6, MVT::i32),
5622 CompNode.getValue(1));
5624 // Unpack the result based on how the target uses it.
5625 unsigned BitNo; // Bit # of CR6.
5626 bool InvertBit; // Invert result?
5627 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
5628 default: // Can't happen, don't crash on invalid number though.
5629 case 0: // Return the value of the EQ bit of CR6.
5630 BitNo = 0; InvertBit = false;
5632 case 1: // Return the inverted value of the EQ bit of CR6.
5633 BitNo = 0; InvertBit = true;
5635 case 2: // Return the value of the LT bit of CR6.
5636 BitNo = 2; InvertBit = false;
5638 case 3: // Return the inverted value of the LT bit of CR6.
5639 BitNo = 2; InvertBit = true;
5643 // Shift the bit into the low position.
5644 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
5645 DAG.getConstant(8-(3-BitNo), MVT::i32));
5647 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
5648 DAG.getConstant(1, MVT::i32));
5650 // If we are supposed to, toggle the bit.
5652 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
5653 DAG.getConstant(1, MVT::i32));
5657 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
5658 SelectionDAG &DAG) const {
5659 DebugLoc dl = Op.getDebugLoc();
5660 // Create a stack slot that is 16-byte aligned.
5661 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
5662 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
5663 EVT PtrVT = getPointerTy();
5664 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5666 // Store the input value into Value#0 of the stack slot.
5667 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
5668 Op.getOperand(0), FIdx, MachinePointerInfo(),
5671 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
5672 false, false, false, 0);
5675 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
5676 DebugLoc dl = Op.getDebugLoc();
5677 if (Op.getValueType() == MVT::v4i32) {
5678 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5680 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
5681 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
5683 SDValue RHSSwap = // = vrlw RHS, 16
5684 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
5686 // Shrinkify inputs to v8i16.
5687 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
5688 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
5689 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
5691 // Low parts multiplied together, generating 32-bit results (we ignore the
5693 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
5694 LHS, RHS, DAG, dl, MVT::v4i32);
5696 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
5697 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
5698 // Shift the high parts up 16 bits.
5699 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
5701 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
5702 } else if (Op.getValueType() == MVT::v8i16) {
5703 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5705 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
5707 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
5708 LHS, RHS, Zero, DAG, dl);
5709 } else if (Op.getValueType() == MVT::v16i8) {
5710 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5712 // Multiply the even 8-bit parts, producing 16-bit sums.
5713 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
5714 LHS, RHS, DAG, dl, MVT::v8i16);
5715 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
5717 // Multiply the odd 8-bit parts, producing 16-bit sums.
5718 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
5719 LHS, RHS, DAG, dl, MVT::v8i16);
5720 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
5722 // Merge the results together.
5724 for (unsigned i = 0; i != 8; ++i) {
5726 Ops[i*2+1] = 2*i+1+16;
5728 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
5730 llvm_unreachable("Unknown mul to lower!");
5734 /// LowerOperation - Provide custom lowering hooks for some operations.
5736 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
5737 switch (Op.getOpcode()) {
5738 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
5739 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
5740 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
5741 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
5742 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
5743 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
5744 case ISD::SETCC: return LowerSETCC(Op, DAG);
5745 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
5746 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
5748 return LowerVASTART(Op, DAG, PPCSubTarget);
5751 return LowerVAARG(Op, DAG, PPCSubTarget);
5753 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
5754 case ISD::DYNAMIC_STACKALLOC:
5755 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
5757 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
5758 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
5760 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
5761 case ISD::FP_TO_UINT:
5762 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
5764 case ISD::UINT_TO_FP:
5765 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
5766 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
5768 // Lower 64-bit shifts.
5769 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
5770 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
5771 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
5773 // Vector-related lowering.
5774 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
5775 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
5776 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
5777 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
5778 case ISD::MUL: return LowerMUL(Op, DAG);
5780 // Frame & Return address.
5781 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
5782 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
5786 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
5787 SmallVectorImpl<SDValue>&Results,
5788 SelectionDAG &DAG) const {
5789 const TargetMachine &TM = getTargetMachine();
5790 DebugLoc dl = N->getDebugLoc();
5791 switch (N->getOpcode()) {
5793 llvm_unreachable("Do not know how to custom type legalize this operation!");
5795 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
5796 || TM.getSubtarget<PPCSubtarget>().isPPC64())
5799 EVT VT = N->getValueType(0);
5801 if (VT == MVT::i64) {
5802 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, PPCSubTarget);
5804 Results.push_back(NewNode);
5805 Results.push_back(NewNode.getValue(1));
5809 case ISD::FP_ROUND_INREG: {
5810 assert(N->getValueType(0) == MVT::ppcf128);
5811 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
5812 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
5813 MVT::f64, N->getOperand(0),
5814 DAG.getIntPtrConstant(0));
5815 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
5816 MVT::f64, N->getOperand(0),
5817 DAG.getIntPtrConstant(1));
5819 // Add the two halves of the long double in round-to-zero mode.
5820 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
5822 // We know the low half is about to be thrown away, so just use something
5824 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
5828 case ISD::FP_TO_SINT:
5829 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
5835 //===----------------------------------------------------------------------===//
5836 // Other Lowering Code
5837 //===----------------------------------------------------------------------===//
5840 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
5841 bool is64bit, unsigned BinOpcode) const {
5842 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
5843 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5845 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5846 MachineFunction *F = BB->getParent();
5847 MachineFunction::iterator It = BB;
5850 unsigned dest = MI->getOperand(0).getReg();
5851 unsigned ptrA = MI->getOperand(1).getReg();
5852 unsigned ptrB = MI->getOperand(2).getReg();
5853 unsigned incr = MI->getOperand(3).getReg();
5854 DebugLoc dl = MI->getDebugLoc();
5856 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
5857 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
5858 F->insert(It, loopMBB);
5859 F->insert(It, exitMBB);
5860 exitMBB->splice(exitMBB->begin(), BB,
5861 llvm::next(MachineBasicBlock::iterator(MI)),
5863 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5865 MachineRegisterInfo &RegInfo = F->getRegInfo();
5866 unsigned TmpReg = (!BinOpcode) ? incr :
5867 RegInfo.createVirtualRegister(
5868 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
5869 (const TargetRegisterClass *) &PPC::GPRCRegClass);
5873 // fallthrough --> loopMBB
5874 BB->addSuccessor(loopMBB);
5877 // l[wd]arx dest, ptr
5878 // add r0, dest, incr
5879 // st[wd]cx. r0, ptr
5881 // fallthrough --> exitMBB
5883 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
5884 .addReg(ptrA).addReg(ptrB);
5886 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
5887 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
5888 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
5889 BuildMI(BB, dl, TII->get(PPC::BCC))
5890 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
5891 BB->addSuccessor(loopMBB);
5892 BB->addSuccessor(exitMBB);
5901 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
5902 MachineBasicBlock *BB,
5903 bool is8bit, // operation
5904 unsigned BinOpcode) const {
5905 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
5906 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5907 // In 64 bit mode we have to use 64 bits for addresses, even though the
5908 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
5909 // registers without caring whether they're 32 or 64, but here we're
5910 // doing actual arithmetic on the addresses.
5911 bool is64bit = PPCSubTarget.isPPC64();
5912 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
5914 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5915 MachineFunction *F = BB->getParent();
5916 MachineFunction::iterator It = BB;
5919 unsigned dest = MI->getOperand(0).getReg();
5920 unsigned ptrA = MI->getOperand(1).getReg();
5921 unsigned ptrB = MI->getOperand(2).getReg();
5922 unsigned incr = MI->getOperand(3).getReg();
5923 DebugLoc dl = MI->getDebugLoc();
5925 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
5926 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
5927 F->insert(It, loopMBB);
5928 F->insert(It, exitMBB);
5929 exitMBB->splice(exitMBB->begin(), BB,
5930 llvm::next(MachineBasicBlock::iterator(MI)),
5932 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5934 MachineRegisterInfo &RegInfo = F->getRegInfo();
5935 const TargetRegisterClass *RC =
5936 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
5937 (const TargetRegisterClass *) &PPC::GPRCRegClass;
5938 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
5939 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
5940 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
5941 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
5942 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
5943 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
5944 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
5945 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
5946 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
5947 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
5948 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
5950 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
5954 // fallthrough --> loopMBB
5955 BB->addSuccessor(loopMBB);
5957 // The 4-byte load must be aligned, while a char or short may be
5958 // anywhere in the word. Hence all this nasty bookkeeping code.
5959 // add ptr1, ptrA, ptrB [copy if ptrA==0]
5960 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
5961 // xori shift, shift1, 24 [16]
5962 // rlwinm ptr, ptr1, 0, 0, 29
5963 // slw incr2, incr, shift
5964 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
5965 // slw mask, mask2, shift
5967 // lwarx tmpDest, ptr
5968 // add tmp, tmpDest, incr2
5969 // andc tmp2, tmpDest, mask
5970 // and tmp3, tmp, mask
5971 // or tmp4, tmp3, tmp2
5974 // fallthrough --> exitMBB
5975 // srw dest, tmpDest, shift
5976 if (ptrA != ZeroReg) {
5977 Ptr1Reg = RegInfo.createVirtualRegister(RC);
5978 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
5979 .addReg(ptrA).addReg(ptrB);
5983 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
5984 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
5985 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
5986 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
5988 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
5989 .addReg(Ptr1Reg).addImm(0).addImm(61);
5991 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
5992 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
5993 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
5994 .addReg(incr).addReg(ShiftReg);
5996 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
5998 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
5999 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
6001 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6002 .addReg(Mask2Reg).addReg(ShiftReg);
6005 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6006 .addReg(ZeroReg).addReg(PtrReg);
6008 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
6009 .addReg(Incr2Reg).addReg(TmpDestReg);
6010 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
6011 .addReg(TmpDestReg).addReg(MaskReg);
6012 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
6013 .addReg(TmpReg).addReg(MaskReg);
6014 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
6015 .addReg(Tmp3Reg).addReg(Tmp2Reg);
6016 BuildMI(BB, dl, TII->get(PPC::STWCX))
6017 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
6018 BuildMI(BB, dl, TII->get(PPC::BCC))
6019 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6020 BB->addSuccessor(loopMBB);
6021 BB->addSuccessor(exitMBB);
6026 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
6031 llvm::MachineBasicBlock*
6032 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
6033 MachineBasicBlock *MBB) const {
6034 DebugLoc DL = MI->getDebugLoc();
6035 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6037 MachineFunction *MF = MBB->getParent();
6038 MachineRegisterInfo &MRI = MF->getRegInfo();
6040 const BasicBlock *BB = MBB->getBasicBlock();
6041 MachineFunction::iterator I = MBB;
6045 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6046 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6048 unsigned DstReg = MI->getOperand(0).getReg();
6049 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
6050 assert(RC->hasType(MVT::i32) && "Invalid destination!");
6051 unsigned mainDstReg = MRI.createVirtualRegister(RC);
6052 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
6054 MVT PVT = getPointerTy();
6055 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6056 "Invalid Pointer Size!");
6057 // For v = setjmp(buf), we generate
6060 // SjLjSetup mainMBB
6066 // buf[LabelOffset] = LR
6070 // v = phi(main, restore)
6073 MachineBasicBlock *thisMBB = MBB;
6074 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
6075 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
6076 MF->insert(I, mainMBB);
6077 MF->insert(I, sinkMBB);
6079 MachineInstrBuilder MIB;
6081 // Transfer the remainder of BB and its successor edges to sinkMBB.
6082 sinkMBB->splice(sinkMBB->begin(), MBB,
6083 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
6084 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
6086 // Note that the structure of the jmp_buf used here is not compatible
6087 // with that used by libc, and is not designed to be. Specifically, it
6088 // stores only those 'reserved' registers that LLVM does not otherwise
6089 // understand how to spill. Also, by convention, by the time this
6090 // intrinsic is called, Clang has already stored the frame address in the
6091 // first slot of the buffer and stack address in the third. Following the
6092 // X86 target code, we'll store the jump address in the second slot. We also
6093 // need to save the TOC pointer (R2) to handle jumps between shared
6094 // libraries, and that will be stored in the fourth slot. The thread
6095 // identifier (R13) is not affected.
6098 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6099 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6101 // Prepare IP either in reg.
6102 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
6103 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
6104 unsigned BufReg = MI->getOperand(1).getReg();
6106 if (PPCSubTarget.isPPC64() && PPCSubTarget.isSVR4ABI()) {
6107 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
6109 .addImm(TOCOffset / 4)
6112 MIB.setMemRefs(MMOBegin, MMOEnd);
6116 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
6117 MIB.addRegMask(PPCRegInfo->getNoPreservedMask());
6119 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
6121 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
6123 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
6125 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
6126 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
6130 MIB = BuildMI(mainMBB, DL,
6131 TII->get(PPCSubTarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
6134 if (PPCSubTarget.isPPC64()) {
6135 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
6137 .addImm(LabelOffset / 4)
6140 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
6142 .addImm(LabelOffset)
6146 MIB.setMemRefs(MMOBegin, MMOEnd);
6148 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
6149 mainMBB->addSuccessor(sinkMBB);
6152 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
6153 TII->get(PPC::PHI), DstReg)
6154 .addReg(mainDstReg).addMBB(mainMBB)
6155 .addReg(restoreDstReg).addMBB(thisMBB);
6157 MI->eraseFromParent();
6162 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
6163 MachineBasicBlock *MBB) const {
6164 DebugLoc DL = MI->getDebugLoc();
6165 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6167 MachineFunction *MF = MBB->getParent();
6168 MachineRegisterInfo &MRI = MF->getRegInfo();
6171 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6172 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6174 MVT PVT = getPointerTy();
6175 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6176 "Invalid Pointer Size!");
6178 const TargetRegisterClass *RC =
6179 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6180 unsigned Tmp = MRI.createVirtualRegister(RC);
6181 // Since FP is only updated here but NOT referenced, it's treated as GPR.
6182 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6183 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6185 MachineInstrBuilder MIB;
6187 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6188 const int64_t SPOffset = 2 * PVT.getStoreSize();
6189 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6191 unsigned BufReg = MI->getOperand(0).getReg();
6193 // Reload FP (the jumped-to function may not have had a
6194 // frame pointer, and if so, then its r31 will be restored
6196 if (PVT == MVT::i64) {
6197 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
6201 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
6205 MIB.setMemRefs(MMOBegin, MMOEnd);
6208 if (PVT == MVT::i64) {
6209 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
6210 .addImm(LabelOffset / 4)
6213 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
6214 .addImm(LabelOffset)
6217 MIB.setMemRefs(MMOBegin, MMOEnd);
6220 if (PVT == MVT::i64) {
6221 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
6222 .addImm(SPOffset / 4)
6225 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
6229 MIB.setMemRefs(MMOBegin, MMOEnd);
6231 // FIXME: When we also support base pointers, that register must also be
6235 if (PVT == MVT::i64 && PPCSubTarget.isSVR4ABI()) {
6236 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
6237 .addImm(TOCOffset / 4)
6240 MIB.setMemRefs(MMOBegin, MMOEnd);
6244 BuildMI(*MBB, MI, DL,
6245 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
6246 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
6248 MI->eraseFromParent();
6253 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6254 MachineBasicBlock *BB) const {
6255 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
6256 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
6257 return emitEHSjLjSetJmp(MI, BB);
6258 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
6259 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
6260 return emitEHSjLjLongJmp(MI, BB);
6263 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6265 // To "insert" these instructions we actually have to insert their
6266 // control-flow patterns.
6267 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6268 MachineFunction::iterator It = BB;
6271 MachineFunction *F = BB->getParent();
6273 if (PPCSubTarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6274 MI->getOpcode() == PPC::SELECT_CC_I8)) {
6275 SmallVector<MachineOperand, 2> Cond;
6276 Cond.push_back(MI->getOperand(4));
6277 Cond.push_back(MI->getOperand(1));
6279 DebugLoc dl = MI->getDebugLoc();
6280 PPCII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(), Cond,
6281 MI->getOperand(2).getReg(), MI->getOperand(3).getReg());
6282 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6283 MI->getOpcode() == PPC::SELECT_CC_I8 ||
6284 MI->getOpcode() == PPC::SELECT_CC_F4 ||
6285 MI->getOpcode() == PPC::SELECT_CC_F8 ||
6286 MI->getOpcode() == PPC::SELECT_CC_VRRC) {
6289 // The incoming instruction knows the destination vreg to set, the
6290 // condition code register to branch on, the true/false values to
6291 // select between, and a branch opcode to use.
6296 // cmpTY ccX, r1, r2
6298 // fallthrough --> copy0MBB
6299 MachineBasicBlock *thisMBB = BB;
6300 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
6301 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
6302 unsigned SelectPred = MI->getOperand(4).getImm();
6303 DebugLoc dl = MI->getDebugLoc();
6304 F->insert(It, copy0MBB);
6305 F->insert(It, sinkMBB);
6307 // Transfer the remainder of BB and its successor edges to sinkMBB.
6308 sinkMBB->splice(sinkMBB->begin(), BB,
6309 llvm::next(MachineBasicBlock::iterator(MI)),
6311 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
6313 // Next, add the true and fallthrough blocks as its successors.
6314 BB->addSuccessor(copy0MBB);
6315 BB->addSuccessor(sinkMBB);
6317 BuildMI(BB, dl, TII->get(PPC::BCC))
6318 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
6321 // %FalseValue = ...
6322 // # fallthrough to sinkMBB
6325 // Update machine-CFG edges
6326 BB->addSuccessor(sinkMBB);
6329 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
6332 BuildMI(*BB, BB->begin(), dl,
6333 TII->get(PPC::PHI), MI->getOperand(0).getReg())
6334 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
6335 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
6337 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
6338 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
6339 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
6340 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
6341 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
6342 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
6343 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
6344 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
6346 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
6347 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
6348 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
6349 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
6350 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
6351 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
6352 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
6353 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
6355 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
6356 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
6357 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
6358 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
6359 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
6360 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
6361 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
6362 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
6364 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
6365 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
6366 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
6367 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
6368 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
6369 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
6370 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
6371 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
6373 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
6374 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
6375 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
6376 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
6377 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
6378 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
6379 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
6380 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
6382 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
6383 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
6384 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
6385 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
6386 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
6387 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
6388 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
6389 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
6391 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
6392 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
6393 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
6394 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
6395 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
6396 BB = EmitAtomicBinary(MI, BB, false, 0);
6397 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
6398 BB = EmitAtomicBinary(MI, BB, true, 0);
6400 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
6401 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
6402 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
6404 unsigned dest = MI->getOperand(0).getReg();
6405 unsigned ptrA = MI->getOperand(1).getReg();
6406 unsigned ptrB = MI->getOperand(2).getReg();
6407 unsigned oldval = MI->getOperand(3).getReg();
6408 unsigned newval = MI->getOperand(4).getReg();
6409 DebugLoc dl = MI->getDebugLoc();
6411 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6412 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6413 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6414 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6415 F->insert(It, loop1MBB);
6416 F->insert(It, loop2MBB);
6417 F->insert(It, midMBB);
6418 F->insert(It, exitMBB);
6419 exitMBB->splice(exitMBB->begin(), BB,
6420 llvm::next(MachineBasicBlock::iterator(MI)),
6422 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6426 // fallthrough --> loopMBB
6427 BB->addSuccessor(loop1MBB);
6430 // l[wd]arx dest, ptr
6431 // cmp[wd] dest, oldval
6434 // st[wd]cx. newval, ptr
6438 // st[wd]cx. dest, ptr
6441 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6442 .addReg(ptrA).addReg(ptrB);
6443 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
6444 .addReg(oldval).addReg(dest);
6445 BuildMI(BB, dl, TII->get(PPC::BCC))
6446 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6447 BB->addSuccessor(loop2MBB);
6448 BB->addSuccessor(midMBB);
6451 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6452 .addReg(newval).addReg(ptrA).addReg(ptrB);
6453 BuildMI(BB, dl, TII->get(PPC::BCC))
6454 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6455 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6456 BB->addSuccessor(loop1MBB);
6457 BB->addSuccessor(exitMBB);
6460 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6461 .addReg(dest).addReg(ptrA).addReg(ptrB);
6462 BB->addSuccessor(exitMBB);
6467 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
6468 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
6469 // We must use 64-bit registers for addresses when targeting 64-bit,
6470 // since we're actually doing arithmetic on them. Other registers
6472 bool is64bit = PPCSubTarget.isPPC64();
6473 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
6475 unsigned dest = MI->getOperand(0).getReg();
6476 unsigned ptrA = MI->getOperand(1).getReg();
6477 unsigned ptrB = MI->getOperand(2).getReg();
6478 unsigned oldval = MI->getOperand(3).getReg();
6479 unsigned newval = MI->getOperand(4).getReg();
6480 DebugLoc dl = MI->getDebugLoc();
6482 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6483 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6484 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6485 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6486 F->insert(It, loop1MBB);
6487 F->insert(It, loop2MBB);
6488 F->insert(It, midMBB);
6489 F->insert(It, exitMBB);
6490 exitMBB->splice(exitMBB->begin(), BB,
6491 llvm::next(MachineBasicBlock::iterator(MI)),
6493 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6495 MachineRegisterInfo &RegInfo = F->getRegInfo();
6496 const TargetRegisterClass *RC =
6497 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6498 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6499 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6500 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6501 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6502 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
6503 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
6504 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
6505 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
6506 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6507 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6508 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6509 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6510 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6511 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6513 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
6514 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6517 // fallthrough --> loopMBB
6518 BB->addSuccessor(loop1MBB);
6520 // The 4-byte load must be aligned, while a char or short may be
6521 // anywhere in the word. Hence all this nasty bookkeeping code.
6522 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6523 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6524 // xori shift, shift1, 24 [16]
6525 // rlwinm ptr, ptr1, 0, 0, 29
6526 // slw newval2, newval, shift
6527 // slw oldval2, oldval,shift
6528 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6529 // slw mask, mask2, shift
6530 // and newval3, newval2, mask
6531 // and oldval3, oldval2, mask
6533 // lwarx tmpDest, ptr
6534 // and tmp, tmpDest, mask
6535 // cmpw tmp, oldval3
6538 // andc tmp2, tmpDest, mask
6539 // or tmp4, tmp2, newval3
6544 // stwcx. tmpDest, ptr
6546 // srw dest, tmpDest, shift
6547 if (ptrA != ZeroReg) {
6548 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6549 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6550 .addReg(ptrA).addReg(ptrB);
6554 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6555 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6556 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6557 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6559 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6560 .addReg(Ptr1Reg).addImm(0).addImm(61);
6562 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6563 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6564 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
6565 .addReg(newval).addReg(ShiftReg);
6566 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
6567 .addReg(oldval).addReg(ShiftReg);
6569 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6571 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6572 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
6573 .addReg(Mask3Reg).addImm(65535);
6575 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6576 .addReg(Mask2Reg).addReg(ShiftReg);
6577 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
6578 .addReg(NewVal2Reg).addReg(MaskReg);
6579 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
6580 .addReg(OldVal2Reg).addReg(MaskReg);
6583 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6584 .addReg(ZeroReg).addReg(PtrReg);
6585 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
6586 .addReg(TmpDestReg).addReg(MaskReg);
6587 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
6588 .addReg(TmpReg).addReg(OldVal3Reg);
6589 BuildMI(BB, dl, TII->get(PPC::BCC))
6590 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6591 BB->addSuccessor(loop2MBB);
6592 BB->addSuccessor(midMBB);
6595 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
6596 .addReg(TmpDestReg).addReg(MaskReg);
6597 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
6598 .addReg(Tmp2Reg).addReg(NewVal3Reg);
6599 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
6600 .addReg(ZeroReg).addReg(PtrReg);
6601 BuildMI(BB, dl, TII->get(PPC::BCC))
6602 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6603 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6604 BB->addSuccessor(loop1MBB);
6605 BB->addSuccessor(exitMBB);
6608 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
6609 .addReg(ZeroReg).addReg(PtrReg);
6610 BB->addSuccessor(exitMBB);
6615 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
6617 } else if (MI->getOpcode() == PPC::FADDrtz) {
6618 // This pseudo performs an FADD with rounding mode temporarily forced
6619 // to round-to-zero. We emit this via custom inserter since the FPSCR
6620 // is not modeled at the SelectionDAG level.
6621 unsigned Dest = MI->getOperand(0).getReg();
6622 unsigned Src1 = MI->getOperand(1).getReg();
6623 unsigned Src2 = MI->getOperand(2).getReg();
6624 DebugLoc dl = MI->getDebugLoc();
6626 MachineRegisterInfo &RegInfo = F->getRegInfo();
6627 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
6629 // Save FPSCR value.
6630 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
6632 // Set rounding mode to round-to-zero.
6633 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
6634 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
6636 // Perform addition.
6637 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
6639 // Restore FPSCR value.
6640 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg);
6641 } else if (MI->getOpcode() == PPC::FRINDrint ||
6642 MI->getOpcode() == PPC::FRINSrint) {
6643 bool isf32 = MI->getOpcode() == PPC::FRINSrint;
6644 unsigned Dest = MI->getOperand(0).getReg();
6645 unsigned Src = MI->getOperand(1).getReg();
6646 DebugLoc dl = MI->getDebugLoc();
6648 MachineRegisterInfo &RegInfo = F->getRegInfo();
6649 unsigned CRReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
6651 // Perform the rounding.
6652 BuildMI(*BB, MI, dl, TII->get(isf32 ? PPC::FRINS : PPC::FRIND), Dest)
6655 // Compare the results.
6656 BuildMI(*BB, MI, dl, TII->get(isf32 ? PPC::FCMPUS : PPC::FCMPUD), CRReg)
6657 .addReg(Dest).addReg(Src);
6659 // If the results were not equal, then set the FPSCR XX bit.
6660 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6661 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6662 F->insert(It, midMBB);
6663 F->insert(It, exitMBB);
6664 exitMBB->splice(exitMBB->begin(), BB,
6665 llvm::next(MachineBasicBlock::iterator(MI)),
6667 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6669 BuildMI(*BB, MI, dl, TII->get(PPC::BCC))
6670 .addImm(PPC::PRED_EQ).addReg(CRReg).addMBB(exitMBB);
6672 BB->addSuccessor(midMBB);
6673 BB->addSuccessor(exitMBB);
6677 // Set the FPSCR XX bit (FE_INEXACT). Note that we cannot just set
6678 // the FI bit here because that will not automatically set XX also,
6679 // and XX is what libm interprets as the FE_INEXACT flag.
6680 BuildMI(BB, dl, TII->get(PPC::MTFSB1)).addImm(/* 38 - 32 = */ 6);
6681 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6683 BB->addSuccessor(exitMBB);
6687 llvm_unreachable("Unexpected instr type to insert");
6690 MI->eraseFromParent(); // The pseudo instruction is gone now.
6694 //===----------------------------------------------------------------------===//
6695 // Target Optimization Hooks
6696 //===----------------------------------------------------------------------===//
6698 SDValue PPCTargetLowering::DAGCombineFastRecip(SDValue Op,
6699 DAGCombinerInfo &DCI) const {
6700 if (DCI.isAfterLegalizeVectorOps())
6703 EVT VT = Op.getValueType();
6705 if ((VT == MVT::f32 && PPCSubTarget.hasFRES()) ||
6706 (VT == MVT::f64 && PPCSubTarget.hasFRE()) ||
6707 (VT == MVT::v4f32 && PPCSubTarget.hasAltivec())) {
6709 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
6710 // For the reciprocal, we need to find the zero of the function:
6711 // F(X) = A X - 1 [which has a zero at X = 1/A]
6713 // X_{i+1} = X_i (2 - A X_i) = X_i + X_i (1 - A X_i) [this second form
6714 // does not require additional intermediate precision]
6716 // Convergence is quadratic, so we essentially double the number of digits
6717 // correct after every iteration. The minimum architected relative
6718 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
6719 // 23 digits and double has 52 digits.
6720 int Iterations = PPCSubTarget.hasRecipPrec() ? 1 : 3;
6721 if (VT.getScalarType() == MVT::f64)
6724 SelectionDAG &DAG = DCI.DAG;
6725 DebugLoc dl = Op.getDebugLoc();
6728 DAG.getConstantFP(1.0, VT.getScalarType());
6729 if (VT.isVector()) {
6730 assert(VT.getVectorNumElements() == 4 &&
6731 "Unknown vector type");
6732 FPOne = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
6733 FPOne, FPOne, FPOne, FPOne);
6736 SDValue Est = DAG.getNode(PPCISD::FRE, dl, VT, Op);
6737 DCI.AddToWorklist(Est.getNode());
6739 // Newton iterations: Est = Est + Est (1 - Arg * Est)
6740 for (int i = 0; i < Iterations; ++i) {
6741 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Op, Est);
6742 DCI.AddToWorklist(NewEst.getNode());
6744 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPOne, NewEst);
6745 DCI.AddToWorklist(NewEst.getNode());
6747 NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
6748 DCI.AddToWorklist(NewEst.getNode());
6750 Est = DAG.getNode(ISD::FADD, dl, VT, Est, NewEst);
6751 DCI.AddToWorklist(Est.getNode());
6760 SDValue PPCTargetLowering::DAGCombineFastRecipFSQRT(SDValue Op,
6761 DAGCombinerInfo &DCI) const {
6762 if (DCI.isAfterLegalizeVectorOps())
6765 EVT VT = Op.getValueType();
6767 if ((VT == MVT::f32 && PPCSubTarget.hasFRSQRTES()) ||
6768 (VT == MVT::f64 && PPCSubTarget.hasFRSQRTE()) ||
6769 (VT == MVT::v4f32 && PPCSubTarget.hasAltivec())) {
6771 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
6772 // For the reciprocal sqrt, we need to find the zero of the function:
6773 // F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
6775 // X_{i+1} = X_i (1.5 - A X_i^2 / 2)
6776 // As a result, we precompute A/2 prior to the iteration loop.
6778 // Convergence is quadratic, so we essentially double the number of digits
6779 // correct after every iteration. The minimum architected relative
6780 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
6781 // 23 digits and double has 52 digits.
6782 int Iterations = PPCSubTarget.hasRecipPrec() ? 1 : 3;
6783 if (VT.getScalarType() == MVT::f64)
6786 SelectionDAG &DAG = DCI.DAG;
6787 DebugLoc dl = Op.getDebugLoc();
6789 SDValue FPThreeHalves =
6790 DAG.getConstantFP(1.5, VT.getScalarType());
6791 if (VT.isVector()) {
6792 assert(VT.getVectorNumElements() == 4 &&
6793 "Unknown vector type");
6794 FPThreeHalves = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
6795 FPThreeHalves, FPThreeHalves,
6796 FPThreeHalves, FPThreeHalves);
6799 SDValue Est = DAG.getNode(PPCISD::FRSQRTE, dl, VT, Op);
6800 DCI.AddToWorklist(Est.getNode());
6802 // We now need 0.5*Arg which we can write as (1.5*Arg - Arg) so that
6803 // this entire sequence requires only one FP constant.
6804 SDValue HalfArg = DAG.getNode(ISD::FMUL, dl, VT, FPThreeHalves, Op);
6805 DCI.AddToWorklist(HalfArg.getNode());
6807 HalfArg = DAG.getNode(ISD::FSUB, dl, VT, HalfArg, Op);
6808 DCI.AddToWorklist(HalfArg.getNode());
6810 // Newton iterations: Est = Est * (1.5 - HalfArg * Est * Est)
6811 for (int i = 0; i < Iterations; ++i) {
6812 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, Est);
6813 DCI.AddToWorklist(NewEst.getNode());
6815 NewEst = DAG.getNode(ISD::FMUL, dl, VT, HalfArg, NewEst);
6816 DCI.AddToWorklist(NewEst.getNode());
6818 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPThreeHalves, NewEst);
6819 DCI.AddToWorklist(NewEst.getNode());
6821 Est = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
6822 DCI.AddToWorklist(Est.getNode());
6831 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
6832 DAGCombinerInfo &DCI) const {
6833 const TargetMachine &TM = getTargetMachine();
6834 SelectionDAG &DAG = DCI.DAG;
6835 DebugLoc dl = N->getDebugLoc();
6836 switch (N->getOpcode()) {
6839 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6840 if (C->isNullValue()) // 0 << V -> 0.
6841 return N->getOperand(0);
6845 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6846 if (C->isNullValue()) // 0 >>u V -> 0.
6847 return N->getOperand(0);
6851 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6852 if (C->isNullValue() || // 0 >>s V -> 0.
6853 C->isAllOnesValue()) // -1 >>s V -> -1.
6854 return N->getOperand(0);
6858 assert(TM.Options.UnsafeFPMath &&
6859 "Reciprocal estimates require UnsafeFPMath");
6861 if (N->getOperand(1).getOpcode() == ISD::FSQRT) {
6863 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0), DCI);
6864 if (RV.getNode() != 0) {
6865 DCI.AddToWorklist(RV.getNode());
6866 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
6867 N->getOperand(0), RV);
6869 } else if (N->getOperand(1).getOpcode() == ISD::FP_EXTEND &&
6870 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
6872 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
6874 if (RV.getNode() != 0) {
6875 DCI.AddToWorklist(RV.getNode());
6876 RV = DAG.getNode(ISD::FP_EXTEND, N->getOperand(1).getDebugLoc(),
6877 N->getValueType(0), RV);
6878 DCI.AddToWorklist(RV.getNode());
6879 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
6880 N->getOperand(0), RV);
6882 } else if (N->getOperand(1).getOpcode() == ISD::FP_ROUND &&
6883 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
6885 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
6887 if (RV.getNode() != 0) {
6888 DCI.AddToWorklist(RV.getNode());
6889 RV = DAG.getNode(ISD::FP_ROUND, N->getOperand(1).getDebugLoc(),
6890 N->getValueType(0), RV,
6891 N->getOperand(1).getOperand(1));
6892 DCI.AddToWorklist(RV.getNode());
6893 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
6894 N->getOperand(0), RV);
6898 SDValue RV = DAGCombineFastRecip(N->getOperand(1), DCI);
6899 if (RV.getNode() != 0) {
6900 DCI.AddToWorklist(RV.getNode());
6901 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
6902 N->getOperand(0), RV);
6908 assert(TM.Options.UnsafeFPMath &&
6909 "Reciprocal estimates require UnsafeFPMath");
6911 // Compute this as 1/(1/sqrt(X)), which is the reciprocal of the
6913 SDValue RV = DAGCombineFastRecipFSQRT(N->getOperand(0), DCI);
6914 if (RV.getNode() != 0) {
6915 DCI.AddToWorklist(RV.getNode());
6916 RV = DAGCombineFastRecip(RV, DCI);
6917 if (RV.getNode() != 0)
6923 case ISD::SINT_TO_FP:
6924 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
6925 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
6926 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
6927 // We allow the src/dst to be either f32/f64, but the intermediate
6928 // type must be i64.
6929 if (N->getOperand(0).getValueType() == MVT::i64 &&
6930 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
6931 SDValue Val = N->getOperand(0).getOperand(0);
6932 if (Val.getValueType() == MVT::f32) {
6933 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
6934 DCI.AddToWorklist(Val.getNode());
6937 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
6938 DCI.AddToWorklist(Val.getNode());
6939 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
6940 DCI.AddToWorklist(Val.getNode());
6941 if (N->getValueType(0) == MVT::f32) {
6942 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
6943 DAG.getIntPtrConstant(0));
6944 DCI.AddToWorklist(Val.getNode());
6947 } else if (N->getOperand(0).getValueType() == MVT::i32) {
6948 // If the intermediate type is i32, we can avoid the load/store here
6955 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
6956 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
6957 !cast<StoreSDNode>(N)->isTruncatingStore() &&
6958 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
6959 N->getOperand(1).getValueType() == MVT::i32 &&
6960 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
6961 SDValue Val = N->getOperand(1).getOperand(0);
6962 if (Val.getValueType() == MVT::f32) {
6963 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
6964 DCI.AddToWorklist(Val.getNode());
6966 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
6967 DCI.AddToWorklist(Val.getNode());
6970 N->getOperand(0), Val, N->getOperand(2),
6971 DAG.getValueType(N->getOperand(1).getValueType())
6974 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
6975 DAG.getVTList(MVT::Other), Ops, array_lengthof(Ops),
6976 cast<StoreSDNode>(N)->getMemoryVT(),
6977 cast<StoreSDNode>(N)->getMemOperand());
6978 DCI.AddToWorklist(Val.getNode());
6982 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
6983 if (cast<StoreSDNode>(N)->isUnindexed() &&
6984 N->getOperand(1).getOpcode() == ISD::BSWAP &&
6985 N->getOperand(1).getNode()->hasOneUse() &&
6986 (N->getOperand(1).getValueType() == MVT::i32 ||
6987 N->getOperand(1).getValueType() == MVT::i16 ||
6988 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
6989 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
6990 N->getOperand(1).getValueType() == MVT::i64))) {
6991 SDValue BSwapOp = N->getOperand(1).getOperand(0);
6992 // Do an any-extend to 32-bits if this is a half-word input.
6993 if (BSwapOp.getValueType() == MVT::i16)
6994 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
6997 N->getOperand(0), BSwapOp, N->getOperand(2),
6998 DAG.getValueType(N->getOperand(1).getValueType())
7001 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
7002 Ops, array_lengthof(Ops),
7003 cast<StoreSDNode>(N)->getMemoryVT(),
7004 cast<StoreSDNode>(N)->getMemOperand());
7008 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
7009 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
7010 N->getOperand(0).hasOneUse() &&
7011 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
7012 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
7013 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
7014 N->getValueType(0) == MVT::i64))) {
7015 SDValue Load = N->getOperand(0);
7016 LoadSDNode *LD = cast<LoadSDNode>(Load);
7017 // Create the byte-swapping load.
7019 LD->getChain(), // Chain
7020 LD->getBasePtr(), // Ptr
7021 DAG.getValueType(N->getValueType(0)) // VT
7024 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
7025 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
7026 MVT::i64 : MVT::i32, MVT::Other),
7027 Ops, 3, LD->getMemoryVT(), LD->getMemOperand());
7029 // If this is an i16 load, insert the truncate.
7030 SDValue ResVal = BSLoad;
7031 if (N->getValueType(0) == MVT::i16)
7032 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
7034 // First, combine the bswap away. This makes the value produced by the
7036 DCI.CombineTo(N, ResVal);
7038 // Next, combine the load away, we give it a bogus result value but a real
7039 // chain result. The result value is dead because the bswap is dead.
7040 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
7042 // Return N so it doesn't get rechecked!
7043 return SDValue(N, 0);
7047 case PPCISD::VCMP: {
7048 // If a VCMPo node already exists with exactly the same operands as this
7049 // node, use its result instead of this node (VCMPo computes both a CR6 and
7050 // a normal output).
7052 if (!N->getOperand(0).hasOneUse() &&
7053 !N->getOperand(1).hasOneUse() &&
7054 !N->getOperand(2).hasOneUse()) {
7056 // Scan all of the users of the LHS, looking for VCMPo's that match.
7057 SDNode *VCMPoNode = 0;
7059 SDNode *LHSN = N->getOperand(0).getNode();
7060 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
7062 if (UI->getOpcode() == PPCISD::VCMPo &&
7063 UI->getOperand(1) == N->getOperand(1) &&
7064 UI->getOperand(2) == N->getOperand(2) &&
7065 UI->getOperand(0) == N->getOperand(0)) {
7070 // If there is no VCMPo node, or if the flag value has a single use, don't
7072 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
7075 // Look at the (necessarily single) use of the flag value. If it has a
7076 // chain, this transformation is more complex. Note that multiple things
7077 // could use the value result, which we should ignore.
7078 SDNode *FlagUser = 0;
7079 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
7080 FlagUser == 0; ++UI) {
7081 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
7083 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
7084 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
7091 // If the user is a MFCR instruction, we know this is safe. Otherwise we
7092 // give up for right now.
7093 if (FlagUser->getOpcode() == PPCISD::MFCR)
7094 return SDValue(VCMPoNode, 0);
7099 // If this is a branch on an altivec predicate comparison, lower this so
7100 // that we don't have to do a MFCR: instead, branch directly on CR6. This
7101 // lowering is done pre-legalize, because the legalizer lowers the predicate
7102 // compare down to code that is difficult to reassemble.
7103 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
7104 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
7108 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
7109 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
7110 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
7111 assert(isDot && "Can't compare against a vector result!");
7113 // If this is a comparison against something other than 0/1, then we know
7114 // that the condition is never/always true.
7115 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
7116 if (Val != 0 && Val != 1) {
7117 if (CC == ISD::SETEQ) // Cond never true, remove branch.
7118 return N->getOperand(0);
7119 // Always !=, turn it into an unconditional branch.
7120 return DAG.getNode(ISD::BR, dl, MVT::Other,
7121 N->getOperand(0), N->getOperand(4));
7124 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
7126 // Create the PPCISD altivec 'dot' comparison node.
7128 LHS.getOperand(2), // LHS of compare
7129 LHS.getOperand(3), // RHS of compare
7130 DAG.getConstant(CompareOpc, MVT::i32)
7132 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
7133 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
7135 // Unpack the result based on how the target uses it.
7136 PPC::Predicate CompOpc;
7137 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
7138 default: // Can't happen, don't crash on invalid number though.
7139 case 0: // Branch on the value of the EQ bit of CR6.
7140 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
7142 case 1: // Branch on the inverted value of the EQ bit of CR6.
7143 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
7145 case 2: // Branch on the value of the LT bit of CR6.
7146 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
7148 case 3: // Branch on the inverted value of the LT bit of CR6.
7149 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
7153 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
7154 DAG.getConstant(CompOpc, MVT::i32),
7155 DAG.getRegister(PPC::CR6, MVT::i32),
7156 N->getOperand(4), CompNode.getValue(1));
7165 //===----------------------------------------------------------------------===//
7166 // Inline Assembly Support
7167 //===----------------------------------------------------------------------===//
7169 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
7172 const SelectionDAG &DAG,
7173 unsigned Depth) const {
7174 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
7175 switch (Op.getOpcode()) {
7177 case PPCISD::LBRX: {
7178 // lhbrx is known to have the top bits cleared out.
7179 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
7180 KnownZero = 0xFFFF0000;
7183 case ISD::INTRINSIC_WO_CHAIN: {
7184 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
7186 case Intrinsic::ppc_altivec_vcmpbfp_p:
7187 case Intrinsic::ppc_altivec_vcmpeqfp_p:
7188 case Intrinsic::ppc_altivec_vcmpequb_p:
7189 case Intrinsic::ppc_altivec_vcmpequh_p:
7190 case Intrinsic::ppc_altivec_vcmpequw_p:
7191 case Intrinsic::ppc_altivec_vcmpgefp_p:
7192 case Intrinsic::ppc_altivec_vcmpgtfp_p:
7193 case Intrinsic::ppc_altivec_vcmpgtsb_p:
7194 case Intrinsic::ppc_altivec_vcmpgtsh_p:
7195 case Intrinsic::ppc_altivec_vcmpgtsw_p:
7196 case Intrinsic::ppc_altivec_vcmpgtub_p:
7197 case Intrinsic::ppc_altivec_vcmpgtuh_p:
7198 case Intrinsic::ppc_altivec_vcmpgtuw_p:
7199 KnownZero = ~1U; // All bits but the low one are known to be zero.
7207 /// getConstraintType - Given a constraint, return the type of
7208 /// constraint it is for this target.
7209 PPCTargetLowering::ConstraintType
7210 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
7211 if (Constraint.size() == 1) {
7212 switch (Constraint[0]) {
7219 return C_RegisterClass;
7221 // FIXME: While Z does indicate a memory constraint, it specifically
7222 // indicates an r+r address (used in conjunction with the 'y' modifier
7223 // in the replacement string). Currently, we're forcing the base
7224 // register to be r0 in the asm printer (which is interpreted as zero)
7225 // and forming the complete address in the second register. This is
7230 return TargetLowering::getConstraintType(Constraint);
7233 /// Examine constraint type and operand type and determine a weight value.
7234 /// This object must already have been set up with the operand type
7235 /// and the current alternative constraint selected.
7236 TargetLowering::ConstraintWeight
7237 PPCTargetLowering::getSingleConstraintMatchWeight(
7238 AsmOperandInfo &info, const char *constraint) const {
7239 ConstraintWeight weight = CW_Invalid;
7240 Value *CallOperandVal = info.CallOperandVal;
7241 // If we don't have a value, we can't do a match,
7242 // but allow it at the lowest weight.
7243 if (CallOperandVal == NULL)
7245 Type *type = CallOperandVal->getType();
7246 // Look at the constraint type.
7247 switch (*constraint) {
7249 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
7252 if (type->isIntegerTy())
7253 weight = CW_Register;
7256 if (type->isFloatTy())
7257 weight = CW_Register;
7260 if (type->isDoubleTy())
7261 weight = CW_Register;
7264 if (type->isVectorTy())
7265 weight = CW_Register;
7268 weight = CW_Register;
7277 std::pair<unsigned, const TargetRegisterClass*>
7278 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
7280 if (Constraint.size() == 1) {
7281 // GCC RS6000 Constraint Letters
7282 switch (Constraint[0]) {
7284 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
7285 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
7286 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
7288 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
7289 return std::make_pair(0U, &PPC::G8RCRegClass);
7290 return std::make_pair(0U, &PPC::GPRCRegClass);
7292 if (VT == MVT::f32 || VT == MVT::i32)
7293 return std::make_pair(0U, &PPC::F4RCRegClass);
7294 if (VT == MVT::f64 || VT == MVT::i64)
7295 return std::make_pair(0U, &PPC::F8RCRegClass);
7298 return std::make_pair(0U, &PPC::VRRCRegClass);
7300 return std::make_pair(0U, &PPC::CRRCRegClass);
7304 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
7308 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
7309 /// vector. If it is invalid, don't add anything to Ops.
7310 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
7311 std::string &Constraint,
7312 std::vector<SDValue>&Ops,
7313 SelectionDAG &DAG) const {
7314 SDValue Result(0,0);
7316 // Only support length 1 constraints.
7317 if (Constraint.length() > 1) return;
7319 char Letter = Constraint[0];
7330 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
7331 if (!CST) return; // Must be an immediate to match.
7332 unsigned Value = CST->getZExtValue();
7334 default: llvm_unreachable("Unknown constraint letter!");
7335 case 'I': // "I" is a signed 16-bit constant.
7336 if ((short)Value == (int)Value)
7337 Result = DAG.getTargetConstant(Value, Op.getValueType());
7339 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
7340 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
7341 if ((short)Value == 0)
7342 Result = DAG.getTargetConstant(Value, Op.getValueType());
7344 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
7345 if ((Value >> 16) == 0)
7346 Result = DAG.getTargetConstant(Value, Op.getValueType());
7348 case 'M': // "M" is a constant that is greater than 31.
7350 Result = DAG.getTargetConstant(Value, Op.getValueType());
7352 case 'N': // "N" is a positive constant that is an exact power of two.
7353 if ((int)Value > 0 && isPowerOf2_32(Value))
7354 Result = DAG.getTargetConstant(Value, Op.getValueType());
7356 case 'O': // "O" is the constant zero.
7358 Result = DAG.getTargetConstant(Value, Op.getValueType());
7360 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
7361 if ((short)-Value == (int)-Value)
7362 Result = DAG.getTargetConstant(Value, Op.getValueType());
7369 if (Result.getNode()) {
7370 Ops.push_back(Result);
7374 // Handle standard constraint letters.
7375 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
7378 // isLegalAddressingMode - Return true if the addressing mode represented
7379 // by AM is legal for this target, for a load/store of the specified type.
7380 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
7382 // FIXME: PPC does not allow r+i addressing modes for vectors!
7384 // PPC allows a sign-extended 16-bit immediate field.
7385 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
7388 // No global is ever allowed as a base.
7392 // PPC only support r+r,
7394 case 0: // "r+i" or just "i", depending on HasBaseReg.
7397 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
7399 // Otherwise we have r+r or r+i.
7402 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
7404 // Allow 2*r as r+r.
7407 // No other scales are supported.
7414 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
7415 SelectionDAG &DAG) const {
7416 MachineFunction &MF = DAG.getMachineFunction();
7417 MachineFrameInfo *MFI = MF.getFrameInfo();
7418 MFI->setReturnAddressIsTaken(true);
7420 DebugLoc dl = Op.getDebugLoc();
7421 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7423 // Make sure the function does not optimize away the store of the RA to
7425 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
7426 FuncInfo->setLRStoreRequired();
7427 bool isPPC64 = PPCSubTarget.isPPC64();
7428 bool isDarwinABI = PPCSubTarget.isDarwinABI();
7431 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
7434 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
7435 isPPC64? MVT::i64 : MVT::i32);
7436 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7437 DAG.getNode(ISD::ADD, dl, getPointerTy(),
7439 MachinePointerInfo(), false, false, false, 0);
7442 // Just load the return address off the stack.
7443 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
7444 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7445 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
7448 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
7449 SelectionDAG &DAG) const {
7450 DebugLoc dl = Op.getDebugLoc();
7451 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7453 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
7454 bool isPPC64 = PtrVT == MVT::i64;
7456 MachineFunction &MF = DAG.getMachineFunction();
7457 MachineFrameInfo *MFI = MF.getFrameInfo();
7458 MFI->setFrameAddressIsTaken(true);
7460 // Naked functions never have a frame pointer, and so we use r1. For all
7461 // other functions, this decision must be delayed until during PEI.
7463 if (MF.getFunction()->getAttributes().hasAttribute(
7464 AttributeSet::FunctionIndex, Attribute::Naked))
7465 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
7467 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
7469 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
7472 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
7473 FrameAddr, MachinePointerInfo(), false, false,
7479 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
7480 // The PowerPC target isn't yet aware of offsets.
7484 /// getOptimalMemOpType - Returns the target specific optimal type for load
7485 /// and store operations as a result of memset, memcpy, and memmove
7486 /// lowering. If DstAlign is zero that means it's safe to destination
7487 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
7488 /// means there isn't a need to check it against alignment requirement,
7489 /// probably because the source does not need to be loaded. If 'IsMemset' is
7490 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
7491 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
7492 /// source is constant so it does not need to be loaded.
7493 /// It returns EVT::Other if the type should be determined using generic
7494 /// target-independent logic.
7495 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
7496 unsigned DstAlign, unsigned SrcAlign,
7497 bool IsMemset, bool ZeroMemset,
7499 MachineFunction &MF) const {
7500 if (this->PPCSubTarget.isPPC64()) {
7507 bool PPCTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
7509 if (DisablePPCUnaligned)
7512 // PowerPC supports unaligned memory access for simple non-vector types.
7513 // Although accessing unaligned addresses is not as efficient as accessing
7514 // aligned addresses, it is generally more efficient than manual expansion,
7515 // and generally only traps for software emulation when crossing page
7521 if (VT.getSimpleVT().isVector())
7524 if (VT == MVT::ppcf128)
7533 /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than
7534 /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to
7535 /// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd
7536 /// is expanded to mul + add.
7537 bool PPCTargetLowering::isFMAFasterThanMulAndAdd(EVT VT) const {
7541 switch (VT.getSimpleVT().SimpleTy) {
7553 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
7555 return TargetLowering::getSchedulingPreference(N);