1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCMachineFunctionInfo.h"
16 #include "PPCPredicates.h"
17 #include "PPCTargetMachine.h"
18 #include "PPCPerfectShuffle.h"
19 #include "llvm/ADT/VectorExtras.h"
20 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/SSARegMap.h"
26 #include "llvm/Constants.h"
27 #include "llvm/Function.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/Support/MathExtras.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Support/CommandLine.h"
34 static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc");
36 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
37 : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) {
39 // Fold away setcc operations if possible.
40 setSetCCIsExpensive();
43 // Use _setjmp/_longjmp instead of setjmp/longjmp.
44 setUseUnderscoreSetJmpLongJmp(true);
46 // Set up the register classes.
47 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
48 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
49 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
51 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
52 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand);
53 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand);
55 // PowerPC does not have truncstore for i1.
56 setStoreXAction(MVT::i1, Promote);
58 // PowerPC has pre-inc load and store's.
59 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
60 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
61 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
62 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
63 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
64 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
65 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
66 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
67 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
68 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
70 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
71 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
73 // PowerPC has no intrinsics for these particular operations
74 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
75 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
76 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
78 // PowerPC has no SREM/UREM instructions
79 setOperationAction(ISD::SREM, MVT::i32, Expand);
80 setOperationAction(ISD::UREM, MVT::i32, Expand);
81 setOperationAction(ISD::SREM, MVT::i64, Expand);
82 setOperationAction(ISD::UREM, MVT::i64, Expand);
84 // We don't support sin/cos/sqrt/fmod
85 setOperationAction(ISD::FSIN , MVT::f64, Expand);
86 setOperationAction(ISD::FCOS , MVT::f64, Expand);
87 setOperationAction(ISD::FREM , MVT::f64, Expand);
88 setOperationAction(ISD::FSIN , MVT::f32, Expand);
89 setOperationAction(ISD::FCOS , MVT::f32, Expand);
90 setOperationAction(ISD::FREM , MVT::f32, Expand);
92 // If we're enabling GP optimizations, use hardware square root
93 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
94 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
95 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
98 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
99 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
101 // PowerPC does not have BSWAP, CTPOP or CTTZ
102 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
103 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
104 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
105 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
106 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
107 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
109 // PowerPC does not have ROTR
110 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
112 // PowerPC does not have Select
113 setOperationAction(ISD::SELECT, MVT::i32, Expand);
114 setOperationAction(ISD::SELECT, MVT::i64, Expand);
115 setOperationAction(ISD::SELECT, MVT::f32, Expand);
116 setOperationAction(ISD::SELECT, MVT::f64, Expand);
118 // PowerPC wants to turn select_cc of FP into fsel when possible.
119 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
120 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
122 // PowerPC wants to optimize integer setcc a bit
123 setOperationAction(ISD::SETCC, MVT::i32, Custom);
125 // PowerPC does not have BRCOND which requires SetCC
126 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
128 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
130 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
131 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
133 // PowerPC does not have [U|S]INT_TO_FP
134 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
135 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
137 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
138 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
139 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
140 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
142 // We cannot sextinreg(i1). Expand to shifts.
143 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
146 // Support label based line numbers.
147 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
148 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
149 // FIXME - use subtarget debug flags
150 if (!TM.getSubtarget<PPCSubtarget>().isDarwin())
151 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
153 // We want to legalize GlobalAddress and ConstantPool nodes into the
154 // appropriate instructions to materialize the address.
155 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
156 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
157 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
158 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
159 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
160 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
162 // RET must be custom lowered, to meet ABI requirements
163 setOperationAction(ISD::RET , MVT::Other, Custom);
165 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
166 setOperationAction(ISD::VASTART , MVT::Other, Custom);
168 // Use the default implementation.
169 setOperationAction(ISD::VAARG , MVT::Other, Expand);
170 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
171 setOperationAction(ISD::VAEND , MVT::Other, Expand);
172 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
173 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
174 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
175 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
177 // We want to custom lower some of our intrinsics.
178 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
180 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
181 // They also have instructions for converting between i64 and fp.
182 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
183 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
185 // FIXME: disable this lowered code. This generates 64-bit register values,
186 // and we don't model the fact that the top part is clobbered by calls. We
187 // need to flag these together so that the value isn't live across a call.
188 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
190 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
191 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
193 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
194 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
197 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
198 // 64 bit PowerPC implementations can support i64 types directly
199 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
200 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
201 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
203 // 32 bit PowerPC wants to expand i64 shifts itself.
204 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
205 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
206 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
209 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
210 // First set operation action for all vector types to expand. Then we
211 // will selectively turn on ones that can be effectively codegen'd.
212 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
213 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
214 // add/sub are legal for all supported vector VT's.
215 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal);
216 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal);
218 // We promote all shuffles to v16i8.
219 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote);
220 AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8);
222 // We promote all non-typed operations to v4i32.
223 setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote);
224 AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32);
225 setOperationAction(ISD::OR , (MVT::ValueType)VT, Promote);
226 AddPromotedToType (ISD::OR , (MVT::ValueType)VT, MVT::v4i32);
227 setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote);
228 AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32);
229 setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote);
230 AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32);
231 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
232 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32);
233 setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote);
234 AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32);
236 // No other operations are legal.
237 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
238 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
239 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
240 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
241 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
242 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
243 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
244 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
245 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
247 setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand);
250 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
251 // with merges, splats, etc.
252 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
254 setOperationAction(ISD::AND , MVT::v4i32, Legal);
255 setOperationAction(ISD::OR , MVT::v4i32, Legal);
256 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
257 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
258 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
259 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
261 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
262 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
263 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
264 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
266 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
267 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
268 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
269 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
271 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
272 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
274 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
275 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
276 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
277 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
280 setSetCCResultType(MVT::i32);
281 setShiftAmountType(MVT::i32);
282 setSetCCResultContents(ZeroOrOneSetCCResult);
284 if (TM.getSubtarget<PPCSubtarget>().isPPC64())
285 setStackPointerRegisterToSaveRestore(PPC::X1);
287 setStackPointerRegisterToSaveRestore(PPC::R1);
289 // We have target-specific dag combine patterns for the following nodes:
290 setTargetDAGCombine(ISD::SINT_TO_FP);
291 setTargetDAGCombine(ISD::STORE);
292 setTargetDAGCombine(ISD::BR_CC);
293 setTargetDAGCombine(ISD::BSWAP);
295 computeRegisterProperties();
298 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
301 case PPCISD::FSEL: return "PPCISD::FSEL";
302 case PPCISD::FCFID: return "PPCISD::FCFID";
303 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
304 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
305 case PPCISD::STFIWX: return "PPCISD::STFIWX";
306 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
307 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
308 case PPCISD::VPERM: return "PPCISD::VPERM";
309 case PPCISD::Hi: return "PPCISD::Hi";
310 case PPCISD::Lo: return "PPCISD::Lo";
311 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
312 case PPCISD::SRL: return "PPCISD::SRL";
313 case PPCISD::SRA: return "PPCISD::SRA";
314 case PPCISD::SHL: return "PPCISD::SHL";
315 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
316 case PPCISD::STD_32: return "PPCISD::STD_32";
317 case PPCISD::CALL: return "PPCISD::CALL";
318 case PPCISD::MTCTR: return "PPCISD::MTCTR";
319 case PPCISD::BCTRL: return "PPCISD::BCTRL";
320 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
321 case PPCISD::MFCR: return "PPCISD::MFCR";
322 case PPCISD::VCMP: return "PPCISD::VCMP";
323 case PPCISD::VCMPo: return "PPCISD::VCMPo";
324 case PPCISD::LBRX: return "PPCISD::LBRX";
325 case PPCISD::STBRX: return "PPCISD::STBRX";
326 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
330 //===----------------------------------------------------------------------===//
331 // Node matching predicates, for use by the tblgen matching code.
332 //===----------------------------------------------------------------------===//
334 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
335 static bool isFloatingPointZero(SDOperand Op) {
336 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
337 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
338 else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
339 // Maybe this has already been legalized into the constant pool?
340 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
341 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
342 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
347 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
348 /// true if Op is undef or if it matches the specified value.
349 static bool isConstantOrUndef(SDOperand Op, unsigned Val) {
350 return Op.getOpcode() == ISD::UNDEF ||
351 cast<ConstantSDNode>(Op)->getValue() == Val;
354 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
355 /// VPKUHUM instruction.
356 bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) {
358 for (unsigned i = 0; i != 16; ++i)
359 if (!isConstantOrUndef(N->getOperand(i), i*2+1))
362 for (unsigned i = 0; i != 8; ++i)
363 if (!isConstantOrUndef(N->getOperand(i), i*2+1) ||
364 !isConstantOrUndef(N->getOperand(i+8), i*2+1))
370 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
371 /// VPKUWUM instruction.
372 bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) {
374 for (unsigned i = 0; i != 16; i += 2)
375 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
376 !isConstantOrUndef(N->getOperand(i+1), i*2+3))
379 for (unsigned i = 0; i != 8; i += 2)
380 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
381 !isConstantOrUndef(N->getOperand(i+1), i*2+3) ||
382 !isConstantOrUndef(N->getOperand(i+8), i*2+2) ||
383 !isConstantOrUndef(N->getOperand(i+9), i*2+3))
389 /// isVMerge - Common function, used to match vmrg* shuffles.
391 static bool isVMerge(SDNode *N, unsigned UnitSize,
392 unsigned LHSStart, unsigned RHSStart) {
393 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
394 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
395 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
396 "Unsupported merge size!");
398 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
399 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
400 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j),
401 LHSStart+j+i*UnitSize) ||
402 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j),
403 RHSStart+j+i*UnitSize))
409 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
410 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
411 bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
413 return isVMerge(N, UnitSize, 8, 24);
414 return isVMerge(N, UnitSize, 8, 8);
417 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
418 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
419 bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
421 return isVMerge(N, UnitSize, 0, 16);
422 return isVMerge(N, UnitSize, 0, 0);
426 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
427 /// amount, otherwise return -1.
428 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
429 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
430 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
431 // Find the first non-undef value in the shuffle mask.
433 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i)
436 if (i == 16) return -1; // all undef.
438 // Otherwise, check to see if the rest of the elements are consequtively
439 // numbered from this value.
440 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue();
441 if (ShiftAmt < i) return -1;
445 // Check the rest of the elements to see if they are consequtive.
446 for (++i; i != 16; ++i)
447 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i))
450 // Check the rest of the elements to see if they are consequtive.
451 for (++i; i != 16; ++i)
452 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15))
459 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
460 /// specifies a splat of a single element that is suitable for input to
461 /// VSPLTB/VSPLTH/VSPLTW.
462 bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) {
463 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
464 N->getNumOperands() == 16 &&
465 (EltSize == 1 || EltSize == 2 || EltSize == 4));
467 // This is a splat operation if each element of the permute is the same, and
468 // if the value doesn't reference the second vector.
469 unsigned ElementBase = 0;
470 SDOperand Elt = N->getOperand(0);
471 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt))
472 ElementBase = EltV->getValue();
474 return false; // FIXME: Handle UNDEF elements too!
476 if (cast<ConstantSDNode>(Elt)->getValue() >= 16)
479 // Check that they are consequtive.
480 for (unsigned i = 1; i != EltSize; ++i) {
481 if (!isa<ConstantSDNode>(N->getOperand(i)) ||
482 cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase)
486 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
487 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
488 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
489 assert(isa<ConstantSDNode>(N->getOperand(i)) &&
490 "Invalid VECTOR_SHUFFLE mask!");
491 for (unsigned j = 0; j != EltSize; ++j)
492 if (N->getOperand(i+j) != N->getOperand(j))
499 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
500 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
501 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
502 assert(isSplatShuffleMask(N, EltSize));
503 return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize;
506 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
507 /// by using a vspltis[bhw] instruction of the specified element size, return
508 /// the constant being splatted. The ByteSize field indicates the number of
509 /// bytes of each element [124] -> [bhw].
510 SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
511 SDOperand OpVal(0, 0);
513 // If ByteSize of the splat is bigger than the element size of the
514 // build_vector, then we have a case where we are checking for a splat where
515 // multiple elements of the buildvector are folded together into a single
516 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
517 unsigned EltSize = 16/N->getNumOperands();
518 if (EltSize < ByteSize) {
519 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
520 SDOperand UniquedVals[4];
521 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
523 // See if all of the elements in the buildvector agree across.
524 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
525 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
526 // If the element isn't a constant, bail fully out.
527 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand();
530 if (UniquedVals[i&(Multiple-1)].Val == 0)
531 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
532 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
533 return SDOperand(); // no match.
536 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
537 // either constant or undef values that are identical for each chunk. See
538 // if these chunks can form into a larger vspltis*.
540 // Check to see if all of the leading entries are either 0 or -1. If
541 // neither, then this won't fit into the immediate field.
542 bool LeadingZero = true;
543 bool LeadingOnes = true;
544 for (unsigned i = 0; i != Multiple-1; ++i) {
545 if (UniquedVals[i].Val == 0) continue; // Must have been undefs.
547 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
548 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
550 // Finally, check the least significant entry.
552 if (UniquedVals[Multiple-1].Val == 0)
553 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
554 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue();
556 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
559 if (UniquedVals[Multiple-1].Val == 0)
560 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
561 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended();
562 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
563 return DAG.getTargetConstant(Val, MVT::i32);
569 // Check to see if this buildvec has a single non-undef value in its elements.
570 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
571 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
573 OpVal = N->getOperand(i);
574 else if (OpVal != N->getOperand(i))
578 if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def.
580 unsigned ValSizeInBytes = 0;
582 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
583 Value = CN->getValue();
584 ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8;
585 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
586 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
587 Value = FloatToBits(CN->getValue());
591 // If the splat value is larger than the element value, then we can never do
592 // this splat. The only case that we could fit the replicated bits into our
593 // immediate field for would be zero, and we prefer to use vxor for it.
594 if (ValSizeInBytes < ByteSize) return SDOperand();
596 // If the element value is larger than the splat value, cut it in half and
597 // check to see if the two halves are equal. Continue doing this until we
598 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
599 while (ValSizeInBytes > ByteSize) {
600 ValSizeInBytes >>= 1;
602 // If the top half equals the bottom half, we're still ok.
603 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
604 (Value & ((1 << (8*ValSizeInBytes))-1)))
608 // Properly sign extend the value.
609 int ShAmt = (4-ByteSize)*8;
610 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
612 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
613 if (MaskVal == 0) return SDOperand();
615 // Finally, if this value fits in a 5 bit sext field, return it
616 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
617 return DAG.getTargetConstant(MaskVal, MVT::i32);
621 //===----------------------------------------------------------------------===//
622 // Addressing Mode Selection
623 //===----------------------------------------------------------------------===//
625 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
626 /// or 64-bit immediate, and if the value can be accurately represented as a
627 /// sign extension from a 16-bit value. If so, this returns true and the
629 static bool isIntS16Immediate(SDNode *N, short &Imm) {
630 if (N->getOpcode() != ISD::Constant)
633 Imm = (short)cast<ConstantSDNode>(N)->getValue();
634 if (N->getValueType(0) == MVT::i32)
635 return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue();
637 return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue();
639 static bool isIntS16Immediate(SDOperand Op, short &Imm) {
640 return isIntS16Immediate(Op.Val, Imm);
644 /// SelectAddressRegReg - Given the specified addressed, check to see if it
645 /// can be represented as an indexed [r+r] operation. Returns false if it
646 /// can be more efficiently represented with [r+imm].
647 bool PPCTargetLowering::SelectAddressRegReg(SDOperand N, SDOperand &Base,
651 if (N.getOpcode() == ISD::ADD) {
652 if (isIntS16Immediate(N.getOperand(1), imm))
654 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
657 Base = N.getOperand(0);
658 Index = N.getOperand(1);
660 } else if (N.getOpcode() == ISD::OR) {
661 if (isIntS16Immediate(N.getOperand(1), imm))
662 return false; // r+i can fold it if we can.
664 // If this is an or of disjoint bitfields, we can codegen this as an add
665 // (for better address arithmetic) if the LHS and RHS of the OR are provably
667 uint64_t LHSKnownZero, LHSKnownOne;
668 uint64_t RHSKnownZero, RHSKnownOne;
669 ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne);
672 ComputeMaskedBits(N.getOperand(1), ~0U, RHSKnownZero, RHSKnownOne);
673 // If all of the bits are known zero on the LHS or RHS, the add won't
675 if ((LHSKnownZero | RHSKnownZero) == ~0U) {
676 Base = N.getOperand(0);
677 Index = N.getOperand(1);
686 /// Returns true if the address N can be represented by a base register plus
687 /// a signed 16-bit displacement [r+imm], and if it is not better
688 /// represented as reg+reg.
689 bool PPCTargetLowering::SelectAddressRegImm(SDOperand N, SDOperand &Disp,
690 SDOperand &Base, SelectionDAG &DAG){
691 // If this can be more profitably realized as r+r, fail.
692 if (SelectAddressRegReg(N, Disp, Base, DAG))
695 if (N.getOpcode() == ISD::ADD) {
697 if (isIntS16Immediate(N.getOperand(1), imm)) {
698 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
699 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
700 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
702 Base = N.getOperand(0);
704 return true; // [r+i]
705 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
706 // Match LOAD (ADD (X, Lo(G))).
707 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
708 && "Cannot handle constant offsets yet!");
709 Disp = N.getOperand(1).getOperand(0); // The global address.
710 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
711 Disp.getOpcode() == ISD::TargetConstantPool ||
712 Disp.getOpcode() == ISD::TargetJumpTable);
713 Base = N.getOperand(0);
714 return true; // [&g+r]
716 } else if (N.getOpcode() == ISD::OR) {
718 if (isIntS16Immediate(N.getOperand(1), imm)) {
719 // If this is an or of disjoint bitfields, we can codegen this as an add
720 // (for better address arithmetic) if the LHS and RHS of the OR are
721 // provably disjoint.
722 uint64_t LHSKnownZero, LHSKnownOne;
723 ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne);
724 if ((LHSKnownZero|~(unsigned)imm) == ~0U) {
725 // If all of the bits are known zero on the LHS or RHS, the add won't
727 Base = N.getOperand(0);
728 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
732 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
733 // Loading from a constant address.
735 // If this address fits entirely in a 16-bit sext immediate field, codegen
738 if (isIntS16Immediate(CN, Imm)) {
739 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
740 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
744 // FIXME: Handle small sext constant offsets in PPC64 mode also!
745 if (CN->getValueType(0) == MVT::i32) {
746 int Addr = (int)CN->getValue();
748 // Otherwise, break this down into an LIS + disp.
749 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
750 Base = DAG.getConstant(Addr - (signed short)Addr, MVT::i32);
755 Disp = DAG.getTargetConstant(0, getPointerTy());
756 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
757 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
760 return true; // [r+0]
763 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
764 /// represented as an indexed [r+r] operation.
765 bool PPCTargetLowering::SelectAddressRegRegOnly(SDOperand N, SDOperand &Base,
768 // Check to see if we can easily represent this as an [r+r] address. This
769 // will fail if it thinks that the address is more profitably represented as
770 // reg+imm, e.g. where imm = 0.
771 if (SelectAddressRegReg(N, Base, Index, DAG))
774 // If the operand is an addition, always emit this as [r+r], since this is
775 // better (for code size, and execution, as the memop does the add for free)
776 // than emitting an explicit add.
777 if (N.getOpcode() == ISD::ADD) {
778 Base = N.getOperand(0);
779 Index = N.getOperand(1);
783 // Otherwise, do it the hard way, using R0 as the base register.
784 Base = DAG.getRegister(PPC::R0, N.getValueType());
789 /// SelectAddressRegImmShift - Returns true if the address N can be
790 /// represented by a base register plus a signed 14-bit displacement
791 /// [r+imm*4]. Suitable for use by STD and friends.
792 bool PPCTargetLowering::SelectAddressRegImmShift(SDOperand N, SDOperand &Disp,
795 // If this can be more profitably realized as r+r, fail.
796 if (SelectAddressRegReg(N, Disp, Base, DAG))
799 if (N.getOpcode() == ISD::ADD) {
801 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
802 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
803 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
804 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
806 Base = N.getOperand(0);
808 return true; // [r+i]
809 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
810 // Match LOAD (ADD (X, Lo(G))).
811 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
812 && "Cannot handle constant offsets yet!");
813 Disp = N.getOperand(1).getOperand(0); // The global address.
814 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
815 Disp.getOpcode() == ISD::TargetConstantPool ||
816 Disp.getOpcode() == ISD::TargetJumpTable);
817 Base = N.getOperand(0);
818 return true; // [&g+r]
820 } else if (N.getOpcode() == ISD::OR) {
822 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
823 // If this is an or of disjoint bitfields, we can codegen this as an add
824 // (for better address arithmetic) if the LHS and RHS of the OR are
825 // provably disjoint.
826 uint64_t LHSKnownZero, LHSKnownOne;
827 ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne);
828 if ((LHSKnownZero|~(unsigned)imm) == ~0U) {
829 // If all of the bits are known zero on the LHS or RHS, the add won't
831 Base = N.getOperand(0);
832 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
836 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
837 // Loading from a constant address.
839 // If this address fits entirely in a 14-bit sext immediate field, codegen
842 if (isIntS16Immediate(CN, Imm)) {
843 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
844 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
848 // FIXME: Handle small sext constant offsets in PPC64 mode also!
849 if (CN->getValueType(0) == MVT::i32) {
850 int Addr = (int)CN->getValue();
852 // Otherwise, break this down into an LIS + disp.
853 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
854 Base = DAG.getConstant(Addr - (signed short)Addr, MVT::i32);
859 Disp = DAG.getTargetConstant(0, getPointerTy());
860 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
861 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
864 return true; // [r+0]
868 /// getPreIndexedAddressParts - returns true by value, base pointer and
869 /// offset pointer and addressing mode by reference if the node's address
870 /// can be legally represented as pre-indexed load / store address.
871 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
873 ISD::MemIndexedMode &AM,
875 // Disabled by default for now.
876 if (!EnablePPCPreinc) return false;
880 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
881 Ptr = LD->getBasePtr();
882 VT = LD->getLoadedVT();
884 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
886 Ptr = ST->getBasePtr();
887 VT = ST->getStoredVT();
891 // PowerPC doesn't have preinc load/store instructions for vectors.
892 if (MVT::isVector(VT))
895 // TODO: Check reg+reg first.
897 // LDU/STU use reg+imm*4, others use reg+imm.
898 if (VT != MVT::i64) {
900 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
904 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
908 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
909 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
910 // sext i32 to i64 when addr mode is r+i.
911 if (LD->getValueType(0) == MVT::i64 && LD->getLoadedVT() == MVT::i32 &&
912 LD->getExtensionType() == ISD::SEXTLOAD &&
913 isa<ConstantSDNode>(Offset))
921 //===----------------------------------------------------------------------===//
922 // LowerOperation implementation
923 //===----------------------------------------------------------------------===//
925 static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
926 MVT::ValueType PtrVT = Op.getValueType();
927 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
928 Constant *C = CP->getConstVal();
929 SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
930 SDOperand Zero = DAG.getConstant(0, PtrVT);
932 const TargetMachine &TM = DAG.getTarget();
934 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero);
935 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero);
937 // If this is a non-darwin platform, we don't support non-static relo models
939 if (TM.getRelocationModel() == Reloc::Static ||
940 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
941 // Generate non-pic code that has direct accesses to the constant pool.
942 // The address of the global is just (hi(&g)+lo(&g)).
943 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
946 if (TM.getRelocationModel() == Reloc::PIC_) {
947 // With PIC, the first instruction is actually "GR+hi(&G)".
948 Hi = DAG.getNode(ISD::ADD, PtrVT,
949 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
952 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
956 static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
957 MVT::ValueType PtrVT = Op.getValueType();
958 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
959 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
960 SDOperand Zero = DAG.getConstant(0, PtrVT);
962 const TargetMachine &TM = DAG.getTarget();
964 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero);
965 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero);
967 // If this is a non-darwin platform, we don't support non-static relo models
969 if (TM.getRelocationModel() == Reloc::Static ||
970 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
971 // Generate non-pic code that has direct accesses to the constant pool.
972 // The address of the global is just (hi(&g)+lo(&g)).
973 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
976 if (TM.getRelocationModel() == Reloc::PIC_) {
977 // With PIC, the first instruction is actually "GR+hi(&G)".
978 Hi = DAG.getNode(ISD::ADD, PtrVT,
979 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
982 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
986 static SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
987 MVT::ValueType PtrVT = Op.getValueType();
988 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
989 GlobalValue *GV = GSDN->getGlobal();
990 SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
991 SDOperand Zero = DAG.getConstant(0, PtrVT);
993 const TargetMachine &TM = DAG.getTarget();
995 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero);
996 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero);
998 // If this is a non-darwin platform, we don't support non-static relo models
1000 if (TM.getRelocationModel() == Reloc::Static ||
1001 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1002 // Generate non-pic code that has direct accesses to globals.
1003 // The address of the global is just (hi(&g)+lo(&g)).
1004 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1007 if (TM.getRelocationModel() == Reloc::PIC_) {
1008 // With PIC, the first instruction is actually "GR+hi(&G)".
1009 Hi = DAG.getNode(ISD::ADD, PtrVT,
1010 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1013 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1015 if (!GV->hasWeakLinkage() && !GV->hasLinkOnceLinkage() &&
1016 (!GV->isExternal() || GV->hasNotBeenReadFromBytecode()))
1019 // If the global is weak or external, we have to go through the lazy
1021 return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0);
1024 static SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
1025 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1027 // If we're comparing for equality to zero, expose the fact that this is
1028 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1029 // fold the new nodes.
1030 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1031 if (C->isNullValue() && CC == ISD::SETEQ) {
1032 MVT::ValueType VT = Op.getOperand(0).getValueType();
1033 SDOperand Zext = Op.getOperand(0);
1034 if (VT < MVT::i32) {
1036 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0));
1038 unsigned Log2b = Log2_32(MVT::getSizeInBits(VT));
1039 SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext);
1040 SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz,
1041 DAG.getConstant(Log2b, MVT::i32));
1042 return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc);
1044 // Leave comparisons against 0 and -1 alone for now, since they're usually
1045 // optimized. FIXME: revisit this when we can custom lower all setcc
1047 if (C->isAllOnesValue() || C->isNullValue())
1051 // If we have an integer seteq/setne, turn it into a compare against zero
1052 // by xor'ing the rhs with the lhs, which is faster than setting a
1053 // condition register, reading it back out, and masking the correct bit. The
1054 // normal approach here uses sub to do this instead of xor. Using xor exposes
1055 // the result to other bit-twiddling opportunities.
1056 MVT::ValueType LHSVT = Op.getOperand(0).getValueType();
1057 if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1058 MVT::ValueType VT = Op.getValueType();
1059 SDOperand Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0),
1061 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC);
1066 static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
1067 unsigned VarArgsFrameIndex) {
1068 // vastart just stores the address of the VarArgsFrameIndex slot into the
1069 // memory location argument.
1070 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1071 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1072 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
1073 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(),
1077 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
1078 int &VarArgsFrameIndex) {
1079 // TODO: add description of PPC stack frame format, or at least some docs.
1081 MachineFunction &MF = DAG.getMachineFunction();
1082 MachineFrameInfo *MFI = MF.getFrameInfo();
1083 SSARegMap *RegMap = MF.getSSARegMap();
1084 SmallVector<SDOperand, 8> ArgValues;
1085 SDOperand Root = Op.getOperand(0);
1087 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1088 bool isPPC64 = PtrVT == MVT::i64;
1090 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64);
1092 static const unsigned GPR_32[] = { // 32-bit registers.
1093 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1094 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1096 static const unsigned GPR_64[] = { // 64-bit registers.
1097 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1098 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1100 static const unsigned FPR[] = {
1101 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1102 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1104 static const unsigned VR[] = {
1105 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1106 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1109 const unsigned Num_GPR_Regs = sizeof(GPR_32)/sizeof(GPR_32[0]);
1110 const unsigned Num_FPR_Regs = sizeof(FPR)/sizeof(FPR[0]);
1111 const unsigned Num_VR_Regs = sizeof( VR)/sizeof( VR[0]);
1113 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1115 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1117 // Add DAG nodes to load the arguments or copy them out of registers. On
1118 // entry to a function on PPC, the arguments start after the linkage area,
1119 // although the first ones are often in registers.
1120 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
1122 bool needsLoad = false;
1123 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
1124 unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8;
1126 unsigned CurArgOffset = ArgOffset;
1128 default: assert(0 && "Unhandled argument type!");
1130 // All int arguments reserve stack space.
1131 ArgOffset += isPPC64 ? 8 : 4;
1133 if (GPR_idx != Num_GPR_Regs) {
1134 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
1135 MF.addLiveIn(GPR[GPR_idx], VReg);
1136 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32);
1142 case MVT::i64: // PPC64
1143 // All int arguments reserve stack space.
1146 if (GPR_idx != Num_GPR_Regs) {
1147 unsigned VReg = RegMap->createVirtualRegister(&PPC::G8RCRegClass);
1148 MF.addLiveIn(GPR[GPR_idx], VReg);
1149 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1157 // All FP arguments reserve stack space.
1158 ArgOffset += isPPC64 ? 8 : ObjSize;
1160 // Every 4 bytes of argument space consumes one of the GPRs available for
1161 // argument passing.
1162 if (GPR_idx != Num_GPR_Regs) {
1164 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
1167 if (FPR_idx != Num_FPR_Regs) {
1169 if (ObjectVT == MVT::f32)
1170 VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass);
1172 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass);
1173 MF.addLiveIn(FPR[FPR_idx], VReg);
1174 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
1184 // Note that vector arguments in registers don't reserve stack space.
1185 if (VR_idx != Num_VR_Regs) {
1186 unsigned VReg = RegMap->createVirtualRegister(&PPC::VRRCRegClass);
1187 MF.addLiveIn(VR[VR_idx], VReg);
1188 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
1191 // This should be simple, but requires getting 16-byte aligned stack
1193 assert(0 && "Loading VR argument not implemented yet!");
1199 // We need to load the argument to a virtual register if we determined above
1200 // that we ran out of physical registers of the appropriate type
1202 // If the argument is actually used, emit a load from the right stack
1204 if (!Op.Val->hasNUsesOfValue(0, ArgNo)) {
1205 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset);
1206 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
1207 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
1209 // Don't emit a dead load.
1210 ArgVal = DAG.getNode(ISD::UNDEF, ObjectVT);
1214 ArgValues.push_back(ArgVal);
1217 // If the function takes variable number of arguments, make a frame index for
1218 // the start of the first vararg value... for expansion of llvm.va_start.
1219 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1221 VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8,
1223 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1224 // If this function is vararg, store any remaining integer argument regs
1225 // to their spots on the stack so that they may be loaded by deferencing the
1226 // result of va_next.
1227 SmallVector<SDOperand, 8> MemOps;
1228 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
1231 VReg = RegMap->createVirtualRegister(&PPC::G8RCRegClass);
1233 VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
1235 MF.addLiveIn(GPR[GPR_idx], VReg);
1236 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
1237 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1238 MemOps.push_back(Store);
1239 // Increment the address by four for the next argument to store
1240 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT);
1241 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1243 if (!MemOps.empty())
1244 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size());
1247 ArgValues.push_back(Root);
1249 // Return the new list of results.
1250 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
1251 Op.Val->value_end());
1252 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
1255 /// isCallCompatibleAddress - Return the immediate to use if the specified
1256 /// 32-bit value is representable in the immediate field of a BxA instruction.
1257 static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) {
1258 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
1261 int Addr = C->getValue();
1262 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
1263 (Addr << 6 >> 6) != Addr)
1264 return 0; // Top 6 bits have to be sext of immediate.
1266 return DAG.getConstant((int)C->getValue() >> 2, MVT::i32).Val;
1270 static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
1271 SDOperand Chain = Op.getOperand(0);
1272 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1273 SDOperand Callee = Op.getOperand(4);
1274 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
1276 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1277 bool isPPC64 = PtrVT == MVT::i64;
1278 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1280 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in
1281 // SelectExpr to use to put the arguments in the appropriate registers.
1282 std::vector<SDOperand> args_to_use;
1284 // Count how many bytes are to be pushed on the stack, including the linkage
1285 // area, and parameter passing area. We start with 24/48 bytes, which is
1286 // prereserved space for [SP][CR][LR][3 x unused].
1287 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64);
1289 // Add up all the space actually used.
1290 for (unsigned i = 0; i != NumOps; ++i)
1291 NumBytes += MVT::getSizeInBits(Op.getOperand(5+2*i).getValueType())/8;
1293 // The prolog code of the callee may store up to 8 GPR argument registers to
1294 // the stack, allowing va_start to index over them in memory if its varargs.
1295 // Because we cannot tell if this is needed on the caller side, we have to
1296 // conservatively assume that it is needed. As such, make sure we have at
1297 // least enough stack space for the caller to store the 8 GPRs.
1298 NumBytes = std::max(NumBytes, PPCFrameInfo::getMinCallFrameSize(isPPC64));
1300 // Adjust the stack pointer for the new arguments...
1301 // These operations are automatically eliminated by the prolog/epilog pass
1302 Chain = DAG.getCALLSEQ_START(Chain,
1303 DAG.getConstant(NumBytes, PtrVT));
1305 // Set up a copy of the stack pointer for use loading and storing any
1306 // arguments that may not fit in the registers available for argument
1310 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
1312 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
1314 // Figure out which arguments are going to go in registers, and which in
1315 // memory. Also, if this is a vararg function, floating point operations
1316 // must be stored to our stack, and loaded into integer regs as well, if
1317 // any integer regs are available for argument passing.
1318 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64);
1319 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1321 static const unsigned GPR_32[] = { // 32-bit registers.
1322 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1323 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1325 static const unsigned GPR_64[] = { // 64-bit registers.
1326 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1327 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1329 static const unsigned FPR[] = {
1330 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1331 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1333 static const unsigned VR[] = {
1334 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1335 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1337 const unsigned NumGPRs = sizeof(GPR_32)/sizeof(GPR_32[0]);
1338 const unsigned NumFPRs = sizeof(FPR)/sizeof(FPR[0]);
1339 const unsigned NumVRs = sizeof( VR)/sizeof( VR[0]);
1341 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1343 std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
1344 SmallVector<SDOperand, 8> MemOpChains;
1345 for (unsigned i = 0; i != NumOps; ++i) {
1346 SDOperand Arg = Op.getOperand(5+2*i);
1348 // PtrOff will be used to store the current argument to the stack if a
1349 // register cannot be found for it.
1350 SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
1351 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff);
1353 // On PPC64, promote integers to 64-bit values.
1354 if (isPPC64 && Arg.getValueType() == MVT::i32) {
1355 unsigned ExtOp = ISD::ZERO_EXTEND;
1356 if (cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue())
1357 ExtOp = ISD::SIGN_EXTEND;
1358 Arg = DAG.getNode(ExtOp, MVT::i64, Arg);
1361 switch (Arg.getValueType()) {
1362 default: assert(0 && "Unexpected ValueType for argument!");
1365 if (GPR_idx != NumGPRs) {
1366 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
1368 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1370 ArgOffset += PtrByteSize;
1374 if (FPR_idx != NumFPRs) {
1375 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
1378 SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
1379 MemOpChains.push_back(Store);
1381 // Float varargs are always shadowed in available integer registers
1382 if (GPR_idx != NumGPRs) {
1383 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
1384 MemOpChains.push_back(Load.getValue(1));
1385 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
1387 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64) {
1388 SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType());
1389 PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour);
1390 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
1391 MemOpChains.push_back(Load.getValue(1));
1392 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
1395 // If we have any FPRs remaining, we may also have GPRs remaining.
1396 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
1398 if (GPR_idx != NumGPRs)
1400 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64)
1404 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1409 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
1415 assert(!isVarArg && "Don't support passing vectors to varargs yet!");
1416 assert(VR_idx != NumVRs &&
1417 "Don't support passing more than 12 vector args yet!");
1418 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
1422 if (!MemOpChains.empty())
1423 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1424 &MemOpChains[0], MemOpChains.size());
1426 // Build a sequence of copy-to-reg nodes chained together with token chain
1427 // and flag operands which copy the outgoing args into the appropriate regs.
1429 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1430 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1432 InFlag = Chain.getValue(1);
1435 std::vector<MVT::ValueType> NodeTys;
1436 NodeTys.push_back(MVT::Other); // Returns a chain
1437 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
1439 SmallVector<SDOperand, 8> Ops;
1440 unsigned CallOpc = PPCISD::CALL;
1442 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1443 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1444 // node so that legalize doesn't hack it.
1445 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1446 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
1447 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1448 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType());
1449 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
1450 // If this is an absolute destination address, use the munged value.
1451 Callee = SDOperand(Dest, 0);
1453 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
1454 // to do the call, we can't use PPCISD::CALL.
1455 SDOperand MTCTROps[] = {Chain, Callee, InFlag};
1456 Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+(InFlag.Val!=0));
1457 InFlag = Chain.getValue(1);
1459 // Copy the callee address into R12 on darwin.
1460 Chain = DAG.getCopyToReg(Chain, PPC::R12, Callee, InFlag);
1461 InFlag = Chain.getValue(1);
1464 NodeTys.push_back(MVT::Other);
1465 NodeTys.push_back(MVT::Flag);
1466 Ops.push_back(Chain);
1467 CallOpc = PPCISD::BCTRL;
1471 // If this is a direct call, pass the chain and the callee.
1473 Ops.push_back(Chain);
1474 Ops.push_back(Callee);
1477 // Add argument registers to the end of the list so that they are known live
1479 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1480 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1481 RegsToPass[i].second.getValueType()));
1484 Ops.push_back(InFlag);
1485 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
1486 InFlag = Chain.getValue(1);
1488 SDOperand ResultVals[3];
1489 unsigned NumResults = 0;
1492 // If the call has results, copy the values out of the ret val registers.
1493 switch (Op.Val->getValueType(0)) {
1494 default: assert(0 && "Unexpected ret value!");
1495 case MVT::Other: break;
1497 if (Op.Val->getValueType(1) == MVT::i32) {
1498 Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32, InFlag).getValue(1);
1499 ResultVals[0] = Chain.getValue(0);
1500 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32,
1501 Chain.getValue(2)).getValue(1);
1502 ResultVals[1] = Chain.getValue(0);
1504 NodeTys.push_back(MVT::i32);
1506 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1);
1507 ResultVals[0] = Chain.getValue(0);
1510 NodeTys.push_back(MVT::i32);
1513 Chain = DAG.getCopyFromReg(Chain, PPC::X3, MVT::i64, InFlag).getValue(1);
1514 ResultVals[0] = Chain.getValue(0);
1516 NodeTys.push_back(MVT::i64);
1520 Chain = DAG.getCopyFromReg(Chain, PPC::F1, Op.Val->getValueType(0),
1521 InFlag).getValue(1);
1522 ResultVals[0] = Chain.getValue(0);
1524 NodeTys.push_back(Op.Val->getValueType(0));
1530 Chain = DAG.getCopyFromReg(Chain, PPC::V2, Op.Val->getValueType(0),
1531 InFlag).getValue(1);
1532 ResultVals[0] = Chain.getValue(0);
1534 NodeTys.push_back(Op.Val->getValueType(0));
1538 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
1539 DAG.getConstant(NumBytes, PtrVT));
1540 NodeTys.push_back(MVT::Other);
1542 // If the function returns void, just return the chain.
1543 if (NumResults == 0)
1546 // Otherwise, merge everything together with a MERGE_VALUES node.
1547 ResultVals[NumResults++] = Chain;
1548 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys,
1549 ResultVals, NumResults);
1550 return Res.getValue(Op.ResNo);
1553 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
1555 switch(Op.getNumOperands()) {
1557 assert(0 && "Do not know how to return this many arguments!");
1560 return SDOperand(); // ret void is legal
1562 MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
1564 if (ArgVT == MVT::i32) {
1566 } else if (ArgVT == MVT::i64) {
1568 } else if (MVT::isVector(ArgVT)) {
1571 assert(MVT::isFloatingPoint(ArgVT));
1575 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
1578 // If we haven't noted the R3/F1 are live out, do so now.
1579 if (DAG.getMachineFunction().liveout_empty())
1580 DAG.getMachineFunction().addLiveOut(ArgReg);
1584 Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(3),
1586 Copy = DAG.getCopyToReg(Copy, PPC::R4, Op.getOperand(1),Copy.getValue(1));
1587 // If we haven't noted the R3+R4 are live out, do so now.
1588 if (DAG.getMachineFunction().liveout_empty()) {
1589 DAG.getMachineFunction().addLiveOut(PPC::R3);
1590 DAG.getMachineFunction().addLiveOut(PPC::R4);
1594 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
1597 static SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG,
1598 const PPCSubtarget &Subtarget) {
1599 MachineFunction &MF = DAG.getMachineFunction();
1600 bool IsPPC64 = Subtarget.isPPC64();
1602 // Get current frame pointer save index. The users of this index will be
1603 // primarily DYNALLOC instructions.
1604 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1605 int FPSI = FI->getFramePointerSaveIndex();
1607 // If the frame pointer save index hasn't been defined yet.
1609 // Find out what the fix offset of the frame pointer save area.
1610 int Offset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64);
1611 // Allocate the frame index for frame pointer save area.
1612 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, Offset);
1614 FI->setFramePointerSaveIndex(FPSI);
1618 SDOperand Chain = Op.getOperand(0);
1619 SDOperand Size = Op.getOperand(1);
1621 // Get the corect type for pointers.
1622 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1624 SDOperand NegSize = DAG.getNode(ISD::SUB, PtrVT,
1625 DAG.getConstant(0, PtrVT), Size);
1626 // Construct a node for the frame pointer save index.
1627 SDOperand FPSIdx = DAG.getFrameIndex(FPSI, PtrVT);
1628 // Build a DYNALLOC node.
1629 SDOperand Ops[3] = { Chain, NegSize, FPSIdx };
1630 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
1631 return DAG.getNode(PPCISD::DYNALLOC, VTs, Ops, 3);
1635 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
1637 static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
1638 // Not FP? Not a fsel.
1639 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) ||
1640 !MVT::isFloatingPoint(Op.getOperand(2).getValueType()))
1643 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1645 // Cannot handle SETEQ/SETNE.
1646 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand();
1648 MVT::ValueType ResVT = Op.getValueType();
1649 MVT::ValueType CmpVT = Op.getOperand(0).getValueType();
1650 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
1651 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3);
1653 // If the RHS of the comparison is a 0.0, we don't need to do the
1654 // subtraction at all.
1655 if (isFloatingPointZero(RHS))
1657 default: break; // SETUO etc aren't handled by fsel.
1661 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
1665 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
1666 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
1667 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
1671 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
1675 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
1676 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
1677 return DAG.getNode(PPCISD::FSEL, ResVT,
1678 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV);
1683 default: break; // SETUO etc aren't handled by fsel.
1687 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
1688 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1689 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1690 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
1694 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
1695 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1696 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1697 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
1701 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
1702 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1703 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1704 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
1708 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
1709 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1710 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1711 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
1716 static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
1717 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType()));
1718 SDOperand Src = Op.getOperand(0);
1719 if (Src.getValueType() == MVT::f32)
1720 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src);
1723 switch (Op.getValueType()) {
1724 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
1726 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src);
1729 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src);
1733 // Convert the FP value to an int value through memory.
1734 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Tmp);
1735 if (Op.getValueType() == MVT::i32)
1736 Bits = DAG.getNode(ISD::TRUNCATE, MVT::i32, Bits);
1740 static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
1741 if (Op.getOperand(0).getValueType() == MVT::i64) {
1742 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
1743 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
1744 if (Op.getValueType() == MVT::f32)
1745 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
1749 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
1750 "Unhandled SINT_TO_FP type in custom expander!");
1751 // Since we only generate this in 64-bit mode, we can take advantage of
1752 // 64-bit registers. In particular, sign extend the input value into the
1753 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
1754 // then lfd it and fcfid it.
1755 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
1756 int FrameIdx = FrameInfo->CreateStackObject(8, 8);
1757 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1758 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
1760 SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32,
1763 // STD the extended value into the stack slot.
1764 SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other,
1765 DAG.getEntryNode(), Ext64, FIdx,
1766 DAG.getSrcValue(NULL));
1767 // Load the value as a double.
1768 SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0);
1770 // FCFID it and return it.
1771 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld);
1772 if (Op.getValueType() == MVT::f32)
1773 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
1777 static SDOperand LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) {
1778 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
1779 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
1781 // Expand into a bunch of logical ops. Note that these ops
1782 // depend on the PPC behavior for oversized shift amounts.
1783 SDOperand Lo = Op.getOperand(0);
1784 SDOperand Hi = Op.getOperand(1);
1785 SDOperand Amt = Op.getOperand(2);
1787 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
1788 DAG.getConstant(32, MVT::i32), Amt);
1789 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt);
1790 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1);
1791 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
1792 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
1793 DAG.getConstant(-32U, MVT::i32));
1794 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5);
1795 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
1796 SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt);
1797 SDOperand OutOps[] = { OutLo, OutHi };
1798 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
1802 static SDOperand LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) {
1803 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
1804 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRL!");
1806 // Otherwise, expand into a bunch of logical ops. Note that these ops
1807 // depend on the PPC behavior for oversized shift amounts.
1808 SDOperand Lo = Op.getOperand(0);
1809 SDOperand Hi = Op.getOperand(1);
1810 SDOperand Amt = Op.getOperand(2);
1812 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
1813 DAG.getConstant(32, MVT::i32), Amt);
1814 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
1815 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
1816 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
1817 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
1818 DAG.getConstant(-32U, MVT::i32));
1819 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5);
1820 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
1821 SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt);
1822 SDOperand OutOps[] = { OutLo, OutHi };
1823 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
1827 static SDOperand LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) {
1828 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
1829 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!");
1831 // Otherwise, expand into a bunch of logical ops, followed by a select_cc.
1832 SDOperand Lo = Op.getOperand(0);
1833 SDOperand Hi = Op.getOperand(1);
1834 SDOperand Amt = Op.getOperand(2);
1836 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
1837 DAG.getConstant(32, MVT::i32), Amt);
1838 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
1839 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
1840 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
1841 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
1842 DAG.getConstant(-32U, MVT::i32));
1843 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5);
1844 SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt);
1845 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32),
1846 Tmp4, Tmp6, ISD::SETLE);
1847 SDOperand OutOps[] = { OutLo, OutHi };
1848 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
1852 //===----------------------------------------------------------------------===//
1853 // Vector related lowering.
1856 // If this is a vector of constants or undefs, get the bits. A bit in
1857 // UndefBits is set if the corresponding element of the vector is an
1858 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
1859 // zero. Return true if this is not an array of constants, false if it is.
1861 static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
1862 uint64_t UndefBits[2]) {
1863 // Start with zero'd results.
1864 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0;
1866 unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType());
1867 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
1868 SDOperand OpVal = BV->getOperand(i);
1870 unsigned PartNo = i >= e/2; // In the upper 128 bits?
1871 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t.
1873 uint64_t EltBits = 0;
1874 if (OpVal.getOpcode() == ISD::UNDEF) {
1875 uint64_t EltUndefBits = ~0U >> (32-EltBitSize);
1876 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize);
1878 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1879 EltBits = CN->getValue() & (~0U >> (32-EltBitSize));
1880 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1881 assert(CN->getValueType(0) == MVT::f32 &&
1882 "Only one legal FP vector type!");
1883 EltBits = FloatToBits(CN->getValue());
1885 // Nonconstant element.
1889 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize);
1892 //printf("%llx %llx %llx %llx\n",
1893 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]);
1897 // If this is a splat (repetition) of a value across the whole vector, return
1898 // the smallest size that splats it. For example, "0x01010101010101..." is a
1899 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
1900 // SplatSize = 1 byte.
1901 static bool isConstantSplat(const uint64_t Bits128[2],
1902 const uint64_t Undef128[2],
1903 unsigned &SplatBits, unsigned &SplatUndef,
1904 unsigned &SplatSize) {
1906 // Don't let undefs prevent splats from matching. See if the top 64-bits are
1907 // the same as the lower 64-bits, ignoring undefs.
1908 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0]))
1909 return false; // Can't be a splat if two pieces don't match.
1911 uint64_t Bits64 = Bits128[0] | Bits128[1];
1912 uint64_t Undef64 = Undef128[0] & Undef128[1];
1914 // Check that the top 32-bits are the same as the lower 32-bits, ignoring
1916 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64))
1917 return false; // Can't be a splat if two pieces don't match.
1919 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32);
1920 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32);
1922 // If the top 16-bits are different than the lower 16-bits, ignoring
1923 // undefs, we have an i32 splat.
1924 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) {
1926 SplatUndef = Undef32;
1931 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16);
1932 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16);
1934 // If the top 8-bits are different than the lower 8-bits, ignoring
1935 // undefs, we have an i16 splat.
1936 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) {
1938 SplatUndef = Undef16;
1943 // Otherwise, we have an 8-bit splat.
1944 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8);
1945 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8);
1950 /// BuildSplatI - Build a canonical splati of Val with an element size of
1951 /// SplatSize. Cast the result to VT.
1952 static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT,
1953 SelectionDAG &DAG) {
1954 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
1956 // Force vspltis[hw] -1 to vspltisb -1.
1957 if (Val == -1) SplatSize = 1;
1959 static const MVT::ValueType VTys[] = { // canonical VT to use for each size.
1960 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
1962 MVT::ValueType CanonicalVT = VTys[SplatSize-1];
1964 // Build a canonical splat for this value.
1965 SDOperand Elt = DAG.getConstant(Val, MVT::getVectorBaseType(CanonicalVT));
1966 SmallVector<SDOperand, 8> Ops;
1967 Ops.assign(MVT::getVectorNumElements(CanonicalVT), Elt);
1968 SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT,
1969 &Ops[0], Ops.size());
1970 return DAG.getNode(ISD::BIT_CONVERT, VT, Res);
1973 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
1974 /// specified intrinsic ID.
1975 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS,
1977 MVT::ValueType DestVT = MVT::Other) {
1978 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
1979 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
1980 DAG.getConstant(IID, MVT::i32), LHS, RHS);
1983 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
1984 /// specified intrinsic ID.
1985 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1,
1986 SDOperand Op2, SelectionDAG &DAG,
1987 MVT::ValueType DestVT = MVT::Other) {
1988 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
1989 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
1990 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
1994 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
1995 /// amount. The result has the specified value type.
1996 static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt,
1997 MVT::ValueType VT, SelectionDAG &DAG) {
1998 // Force LHS/RHS to be the right type.
1999 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS);
2000 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS);
2003 for (unsigned i = 0; i != 16; ++i)
2004 Ops[i] = DAG.getConstant(i+Amt, MVT::i32);
2005 SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS,
2006 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16));
2007 return DAG.getNode(ISD::BIT_CONVERT, VT, T);
2010 // If this is a case we can't handle, return null and let the default
2011 // expansion code take care of it. If we CAN select this case, and if it
2012 // selects to a single instruction, return Op. Otherwise, if we can codegen
2013 // this case more efficiently than a constant pool load, lower it to the
2014 // sequence of ops that should be used.
2015 static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2016 // If this is a vector of constants or undefs, get the bits. A bit in
2017 // UndefBits is set if the corresponding element of the vector is an
2018 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
2020 uint64_t VectorBits[2];
2021 uint64_t UndefBits[2];
2022 if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits))
2023 return SDOperand(); // Not a constant vector.
2025 // If this is a splat (repetition) of a value across the whole vector, return
2026 // the smallest size that splats it. For example, "0x01010101010101..." is a
2027 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
2028 // SplatSize = 1 byte.
2029 unsigned SplatBits, SplatUndef, SplatSize;
2030 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){
2031 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0;
2033 // First, handle single instruction cases.
2036 if (SplatBits == 0) {
2037 // Canonicalize all zero vectors to be v4i32.
2038 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
2039 SDOperand Z = DAG.getConstant(0, MVT::i32);
2040 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z);
2041 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z);
2046 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
2047 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize);
2048 if (SextVal >= -16 && SextVal <= 15)
2049 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG);
2052 // Two instruction sequences.
2054 // If this value is in the range [-32,30] and is even, use:
2055 // tmp = VSPLTI[bhw], result = add tmp, tmp
2056 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
2057 Op = BuildSplatI(SextVal >> 1, SplatSize, Op.getValueType(), DAG);
2058 return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op);
2061 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
2062 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
2064 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
2065 // Make -1 and vspltisw -1:
2066 SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG);
2068 // Make the VSLW intrinsic, computing 0x8000_0000.
2069 SDOperand Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
2072 // xor by OnesV to invert it.
2073 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV);
2074 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2077 // Check to see if this is a wide variety of vsplti*, binop self cases.
2078 unsigned SplatBitSize = SplatSize*8;
2079 static const char SplatCsts[] = {
2080 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
2081 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
2083 for (unsigned idx = 0; idx < sizeof(SplatCsts)/sizeof(SplatCsts[0]); ++idx){
2084 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
2085 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
2086 int i = SplatCsts[idx];
2088 // Figure out what shift amount will be used by altivec if shifted by i in
2090 unsigned TypeShiftAmt = i & (SplatBitSize-1);
2092 // vsplti + shl self.
2093 if (SextVal == (i << (int)TypeShiftAmt)) {
2094 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
2095 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2096 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
2097 Intrinsic::ppc_altivec_vslw
2099 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
2102 // vsplti + srl self.
2103 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
2104 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
2105 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2106 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
2107 Intrinsic::ppc_altivec_vsrw
2109 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
2112 // vsplti + sra self.
2113 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
2114 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
2115 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2116 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
2117 Intrinsic::ppc_altivec_vsraw
2119 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
2122 // vsplti + rol self.
2123 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
2124 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
2125 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
2126 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2127 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
2128 Intrinsic::ppc_altivec_vrlw
2130 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
2133 // t = vsplti c, result = vsldoi t, t, 1
2134 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
2135 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2136 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG);
2138 // t = vsplti c, result = vsldoi t, t, 2
2139 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
2140 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2141 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG);
2143 // t = vsplti c, result = vsldoi t, t, 3
2144 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
2145 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2146 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG);
2150 // Three instruction sequences.
2152 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
2153 if (SextVal >= 0 && SextVal <= 31) {
2154 SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, Op.getValueType(),DAG);
2155 SDOperand RHS = BuildSplatI(-16, SplatSize, Op.getValueType(), DAG);
2156 return DAG.getNode(ISD::SUB, Op.getValueType(), LHS, RHS);
2158 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
2159 if (SextVal >= -31 && SextVal <= 0) {
2160 SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, Op.getValueType(),DAG);
2161 SDOperand RHS = BuildSplatI(-16, SplatSize, Op.getValueType(), DAG);
2162 return DAG.getNode(ISD::ADD, Op.getValueType(), LHS, RHS);
2169 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
2170 /// the specified operations to build the shuffle.
2171 static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS,
2172 SDOperand RHS, SelectionDAG &DAG) {
2173 unsigned OpNum = (PFEntry >> 26) & 0x0F;
2174 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
2175 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
2178 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
2190 if (OpNum == OP_COPY) {
2191 if (LHSID == (1*9+2)*9+3) return LHS;
2192 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
2196 SDOperand OpLHS, OpRHS;
2197 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG);
2198 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG);
2200 unsigned ShufIdxs[16];
2202 default: assert(0 && "Unknown i32 permute!");
2204 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
2205 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
2206 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
2207 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
2210 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
2211 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
2212 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
2213 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
2216 for (unsigned i = 0; i != 16; ++i)
2217 ShufIdxs[i] = (i&3)+0;
2220 for (unsigned i = 0; i != 16; ++i)
2221 ShufIdxs[i] = (i&3)+4;
2224 for (unsigned i = 0; i != 16; ++i)
2225 ShufIdxs[i] = (i&3)+8;
2228 for (unsigned i = 0; i != 16; ++i)
2229 ShufIdxs[i] = (i&3)+12;
2232 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG);
2234 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG);
2236 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG);
2239 for (unsigned i = 0; i != 16; ++i)
2240 Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i32);
2242 return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS,
2243 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
2246 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
2247 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
2248 /// return the code it can be lowered into. Worst case, it can always be
2249 /// lowered into a vperm.
2250 static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
2251 SDOperand V1 = Op.getOperand(0);
2252 SDOperand V2 = Op.getOperand(1);
2253 SDOperand PermMask = Op.getOperand(2);
2255 // Cases that are handled by instructions that take permute immediates
2256 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
2257 // selected by the instruction selector.
2258 if (V2.getOpcode() == ISD::UNDEF) {
2259 if (PPC::isSplatShuffleMask(PermMask.Val, 1) ||
2260 PPC::isSplatShuffleMask(PermMask.Val, 2) ||
2261 PPC::isSplatShuffleMask(PermMask.Val, 4) ||
2262 PPC::isVPKUWUMShuffleMask(PermMask.Val, true) ||
2263 PPC::isVPKUHUMShuffleMask(PermMask.Val, true) ||
2264 PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 ||
2265 PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) ||
2266 PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) ||
2267 PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) ||
2268 PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) ||
2269 PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) ||
2270 PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) {
2275 // Altivec has a variety of "shuffle immediates" that take two vector inputs
2276 // and produce a fixed permutation. If any of these match, do not lower to
2278 if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) ||
2279 PPC::isVPKUHUMShuffleMask(PermMask.Val, false) ||
2280 PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 ||
2281 PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) ||
2282 PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) ||
2283 PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) ||
2284 PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) ||
2285 PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) ||
2286 PPC::isVMRGHShuffleMask(PermMask.Val, 4, false))
2289 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
2290 // perfect shuffle table to emit an optimal matching sequence.
2291 unsigned PFIndexes[4];
2292 bool isFourElementShuffle = true;
2293 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
2294 unsigned EltNo = 8; // Start out undef.
2295 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
2296 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF)
2297 continue; // Undef, ignore it.
2299 unsigned ByteSource =
2300 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue();
2301 if ((ByteSource & 3) != j) {
2302 isFourElementShuffle = false;
2307 EltNo = ByteSource/4;
2308 } else if (EltNo != ByteSource/4) {
2309 isFourElementShuffle = false;
2313 PFIndexes[i] = EltNo;
2316 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
2317 // perfect shuffle vector to determine if it is cost effective to do this as
2318 // discrete instructions, or whether we should use a vperm.
2319 if (isFourElementShuffle) {
2320 // Compute the index in the perfect shuffle table.
2321 unsigned PFTableIndex =
2322 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
2324 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
2325 unsigned Cost = (PFEntry >> 30);
2327 // Determining when to avoid vperm is tricky. Many things affect the cost
2328 // of vperm, particularly how many times the perm mask needs to be computed.
2329 // For example, if the perm mask can be hoisted out of a loop or is already
2330 // used (perhaps because there are multiple permutes with the same shuffle
2331 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
2332 // the loop requires an extra register.
2334 // As a compromise, we only emit discrete instructions if the shuffle can be
2335 // generated in 3 or fewer operations. When we have loop information
2336 // available, if this block is within a loop, we should avoid using vperm
2337 // for 3-operation perms and use a constant pool load instead.
2339 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG);
2342 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
2343 // vector that will get spilled to the constant pool.
2344 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
2346 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
2347 // that it is in input element units, not in bytes. Convert now.
2348 MVT::ValueType EltVT = MVT::getVectorBaseType(V1.getValueType());
2349 unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8;
2351 SmallVector<SDOperand, 16> ResultMask;
2352 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
2354 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
2357 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue();
2359 for (unsigned j = 0; j != BytesPerElement; ++j)
2360 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
2364 SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8,
2365 &ResultMask[0], ResultMask.size());
2366 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
2369 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
2370 /// altivec comparison. If it is, return true and fill in Opc/isDot with
2371 /// information about the intrinsic.
2372 static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc,
2374 unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue();
2377 switch (IntrinsicID) {
2378 default: return false;
2379 // Comparison predicates.
2380 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
2381 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
2382 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
2383 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
2384 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
2385 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
2386 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
2387 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
2388 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
2389 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
2390 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
2391 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
2392 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
2394 // Normal Comparisons.
2395 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
2396 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
2397 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
2398 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
2399 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
2400 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
2401 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
2402 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
2403 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
2404 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
2405 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
2406 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
2407 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
2412 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
2413 /// lower, do it, otherwise return null.
2414 static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
2415 // If this is a lowered altivec predicate compare, CompareOpc is set to the
2416 // opcode number of the comparison.
2419 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
2420 return SDOperand(); // Don't custom lower most intrinsics.
2422 // If this is a non-dot comparison, make the VCMP node and we are done.
2424 SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(),
2425 Op.getOperand(1), Op.getOperand(2),
2426 DAG.getConstant(CompareOpc, MVT::i32));
2427 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp);
2430 // Create the PPCISD altivec 'dot' comparison node.
2432 Op.getOperand(2), // LHS
2433 Op.getOperand(3), // RHS
2434 DAG.getConstant(CompareOpc, MVT::i32)
2436 std::vector<MVT::ValueType> VTs;
2437 VTs.push_back(Op.getOperand(2).getValueType());
2438 VTs.push_back(MVT::Flag);
2439 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
2441 // Now that we have the comparison, emit a copy from the CR to a GPR.
2442 // This is flagged to the above dot comparison.
2443 SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32,
2444 DAG.getRegister(PPC::CR6, MVT::i32),
2445 CompNode.getValue(1));
2447 // Unpack the result based on how the target uses it.
2448 unsigned BitNo; // Bit # of CR6.
2449 bool InvertBit; // Invert result?
2450 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
2451 default: // Can't happen, don't crash on invalid number though.
2452 case 0: // Return the value of the EQ bit of CR6.
2453 BitNo = 0; InvertBit = false;
2455 case 1: // Return the inverted value of the EQ bit of CR6.
2456 BitNo = 0; InvertBit = true;
2458 case 2: // Return the value of the LT bit of CR6.
2459 BitNo = 2; InvertBit = false;
2461 case 3: // Return the inverted value of the LT bit of CR6.
2462 BitNo = 2; InvertBit = true;
2466 // Shift the bit into the low position.
2467 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags,
2468 DAG.getConstant(8-(3-BitNo), MVT::i32));
2470 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags,
2471 DAG.getConstant(1, MVT::i32));
2473 // If we are supposed to, toggle the bit.
2475 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags,
2476 DAG.getConstant(1, MVT::i32));
2480 static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2481 // Create a stack slot that is 16-byte aligned.
2482 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
2483 int FrameIdx = FrameInfo->CreateStackObject(16, 16);
2484 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2485 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
2487 // Store the input value into Value#0 of the stack slot.
2488 SDOperand Store = DAG.getStore(DAG.getEntryNode(),
2489 Op.getOperand(0), FIdx, NULL, 0);
2491 return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0);
2494 static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) {
2495 if (Op.getValueType() == MVT::v4i32) {
2496 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2498 SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG);
2499 SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt.
2501 SDOperand RHSSwap = // = vrlw RHS, 16
2502 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG);
2504 // Shrinkify inputs to v8i16.
2505 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS);
2506 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS);
2507 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap);
2509 // Low parts multiplied together, generating 32-bit results (we ignore the
2511 SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
2512 LHS, RHS, DAG, MVT::v4i32);
2514 SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
2515 LHS, RHSSwap, Zero, DAG, MVT::v4i32);
2516 // Shift the high parts up 16 bits.
2517 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG);
2518 return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd);
2519 } else if (Op.getValueType() == MVT::v8i16) {
2520 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2522 SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG);
2524 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
2525 LHS, RHS, Zero, DAG);
2526 } else if (Op.getValueType() == MVT::v16i8) {
2527 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2529 // Multiply the even 8-bit parts, producing 16-bit sums.
2530 SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
2531 LHS, RHS, DAG, MVT::v8i16);
2532 EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts);
2534 // Multiply the odd 8-bit parts, producing 16-bit sums.
2535 SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
2536 LHS, RHS, DAG, MVT::v8i16);
2537 OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts);
2539 // Merge the results together.
2541 for (unsigned i = 0; i != 8; ++i) {
2542 Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8);
2543 Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8);
2545 return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts,
2546 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
2548 assert(0 && "Unknown mul to lower!");
2553 /// LowerOperation - Provide custom lowering hooks for some operations.
2555 SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
2556 switch (Op.getOpcode()) {
2557 default: assert(0 && "Wasn't expecting to be able to lower this!");
2558 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2559 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
2560 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
2561 case ISD::SETCC: return LowerSETCC(Op, DAG);
2562 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
2563 case ISD::FORMAL_ARGUMENTS:
2564 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex);
2565 case ISD::CALL: return LowerCALL(Op, DAG);
2566 case ISD::RET: return LowerRET(Op, DAG);
2567 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG,
2570 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
2571 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
2572 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
2574 // Lower 64-bit shifts.
2575 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
2576 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
2577 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
2579 // Vector-related lowering.
2580 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
2581 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2582 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2583 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
2584 case ISD::MUL: return LowerMUL(Op, DAG);
2589 //===----------------------------------------------------------------------===//
2590 // Other Lowering Code
2591 //===----------------------------------------------------------------------===//
2594 PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
2595 MachineBasicBlock *BB) {
2596 assert((MI->getOpcode() == PPC::SELECT_CC_I4 ||
2597 MI->getOpcode() == PPC::SELECT_CC_I8 ||
2598 MI->getOpcode() == PPC::SELECT_CC_F4 ||
2599 MI->getOpcode() == PPC::SELECT_CC_F8 ||
2600 MI->getOpcode() == PPC::SELECT_CC_VRRC) &&
2601 "Unexpected instr type to insert");
2603 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
2604 // control-flow pattern. The incoming instruction knows the destination vreg
2605 // to set, the condition code register to branch on, the true/false values to
2606 // select between, and a branch opcode to use.
2607 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2608 ilist<MachineBasicBlock>::iterator It = BB;
2614 // cmpTY ccX, r1, r2
2616 // fallthrough --> copy0MBB
2617 MachineBasicBlock *thisMBB = BB;
2618 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
2619 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
2620 unsigned SelectPred = MI->getOperand(4).getImm();
2621 BuildMI(BB, PPC::BCC, 3)
2622 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
2623 MachineFunction *F = BB->getParent();
2624 F->getBasicBlockList().insert(It, copy0MBB);
2625 F->getBasicBlockList().insert(It, sinkMBB);
2626 // Update machine-CFG edges by first adding all successors of the current
2627 // block to the new block which will contain the Phi node for the select.
2628 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
2629 e = BB->succ_end(); i != e; ++i)
2630 sinkMBB->addSuccessor(*i);
2631 // Next, remove all successors of the current block, and add the true
2632 // and fallthrough blocks as its successors.
2633 while(!BB->succ_empty())
2634 BB->removeSuccessor(BB->succ_begin());
2635 BB->addSuccessor(copy0MBB);
2636 BB->addSuccessor(sinkMBB);
2639 // %FalseValue = ...
2640 // # fallthrough to sinkMBB
2643 // Update machine-CFG edges
2644 BB->addSuccessor(sinkMBB);
2647 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
2650 BuildMI(BB, PPC::PHI, 4, MI->getOperand(0).getReg())
2651 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
2652 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
2654 delete MI; // The pseudo instruction is gone now.
2658 //===----------------------------------------------------------------------===//
2659 // Target Optimization Hooks
2660 //===----------------------------------------------------------------------===//
2662 SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
2663 DAGCombinerInfo &DCI) const {
2664 TargetMachine &TM = getTargetMachine();
2665 SelectionDAG &DAG = DCI.DAG;
2666 switch (N->getOpcode()) {
2669 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
2670 if (C->getValue() == 0) // 0 << V -> 0.
2671 return N->getOperand(0);
2675 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
2676 if (C->getValue() == 0) // 0 >>u V -> 0.
2677 return N->getOperand(0);
2681 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
2682 if (C->getValue() == 0 || // 0 >>s V -> 0.
2683 C->isAllOnesValue()) // -1 >>s V -> -1.
2684 return N->getOperand(0);
2688 case ISD::SINT_TO_FP:
2689 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
2690 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
2691 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
2692 // We allow the src/dst to be either f32/f64, but the intermediate
2693 // type must be i64.
2694 if (N->getOperand(0).getValueType() == MVT::i64) {
2695 SDOperand Val = N->getOperand(0).getOperand(0);
2696 if (Val.getValueType() == MVT::f32) {
2697 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
2698 DCI.AddToWorklist(Val.Val);
2701 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val);
2702 DCI.AddToWorklist(Val.Val);
2703 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val);
2704 DCI.AddToWorklist(Val.Val);
2705 if (N->getValueType(0) == MVT::f32) {
2706 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val);
2707 DCI.AddToWorklist(Val.Val);
2710 } else if (N->getOperand(0).getValueType() == MVT::i32) {
2711 // If the intermediate type is i32, we can avoid the load/store here
2718 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
2719 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
2720 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
2721 N->getOperand(1).getValueType() == MVT::i32) {
2722 SDOperand Val = N->getOperand(1).getOperand(0);
2723 if (Val.getValueType() == MVT::f32) {
2724 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
2725 DCI.AddToWorklist(Val.Val);
2727 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val);
2728 DCI.AddToWorklist(Val.Val);
2730 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val,
2731 N->getOperand(2), N->getOperand(3));
2732 DCI.AddToWorklist(Val.Val);
2736 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
2737 if (N->getOperand(1).getOpcode() == ISD::BSWAP &&
2738 N->getOperand(1).Val->hasOneUse() &&
2739 (N->getOperand(1).getValueType() == MVT::i32 ||
2740 N->getOperand(1).getValueType() == MVT::i16)) {
2741 SDOperand BSwapOp = N->getOperand(1).getOperand(0);
2742 // Do an any-extend to 32-bits if this is a half-word input.
2743 if (BSwapOp.getValueType() == MVT::i16)
2744 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp);
2746 return DAG.getNode(PPCISD::STBRX, MVT::Other, N->getOperand(0), BSwapOp,
2747 N->getOperand(2), N->getOperand(3),
2748 DAG.getValueType(N->getOperand(1).getValueType()));
2752 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
2753 if (ISD::isNON_EXTLoad(N->getOperand(0).Val) &&
2754 N->getOperand(0).hasOneUse() &&
2755 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
2756 SDOperand Load = N->getOperand(0);
2757 LoadSDNode *LD = cast<LoadSDNode>(Load);
2758 // Create the byte-swapping load.
2759 std::vector<MVT::ValueType> VTs;
2760 VTs.push_back(MVT::i32);
2761 VTs.push_back(MVT::Other);
2762 SDOperand SV = DAG.getSrcValue(LD->getSrcValue(), LD->getSrcValueOffset());
2764 LD->getChain(), // Chain
2765 LD->getBasePtr(), // Ptr
2767 DAG.getValueType(N->getValueType(0)) // VT
2769 SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4);
2771 // If this is an i16 load, insert the truncate.
2772 SDOperand ResVal = BSLoad;
2773 if (N->getValueType(0) == MVT::i16)
2774 ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad);
2776 // First, combine the bswap away. This makes the value produced by the
2778 DCI.CombineTo(N, ResVal);
2780 // Next, combine the load away, we give it a bogus result value but a real
2781 // chain result. The result value is dead because the bswap is dead.
2782 DCI.CombineTo(Load.Val, ResVal, BSLoad.getValue(1));
2784 // Return N so it doesn't get rechecked!
2785 return SDOperand(N, 0);
2789 case PPCISD::VCMP: {
2790 // If a VCMPo node already exists with exactly the same operands as this
2791 // node, use its result instead of this node (VCMPo computes both a CR6 and
2792 // a normal output).
2794 if (!N->getOperand(0).hasOneUse() &&
2795 !N->getOperand(1).hasOneUse() &&
2796 !N->getOperand(2).hasOneUse()) {
2798 // Scan all of the users of the LHS, looking for VCMPo's that match.
2799 SDNode *VCMPoNode = 0;
2801 SDNode *LHSN = N->getOperand(0).Val;
2802 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
2804 if ((*UI)->getOpcode() == PPCISD::VCMPo &&
2805 (*UI)->getOperand(1) == N->getOperand(1) &&
2806 (*UI)->getOperand(2) == N->getOperand(2) &&
2807 (*UI)->getOperand(0) == N->getOperand(0)) {
2812 // If there is no VCMPo node, or if the flag value has a single use, don't
2814 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
2817 // Look at the (necessarily single) use of the flag value. If it has a
2818 // chain, this transformation is more complex. Note that multiple things
2819 // could use the value result, which we should ignore.
2820 SDNode *FlagUser = 0;
2821 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
2822 FlagUser == 0; ++UI) {
2823 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
2825 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
2826 if (User->getOperand(i) == SDOperand(VCMPoNode, 1)) {
2833 // If the user is a MFCR instruction, we know this is safe. Otherwise we
2834 // give up for right now.
2835 if (FlagUser->getOpcode() == PPCISD::MFCR)
2836 return SDOperand(VCMPoNode, 0);
2841 // If this is a branch on an altivec predicate comparison, lower this so
2842 // that we don't have to do a MFCR: instead, branch directly on CR6. This
2843 // lowering is done pre-legalize, because the legalizer lowers the predicate
2844 // compare down to code that is difficult to reassemble.
2845 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
2846 SDOperand LHS = N->getOperand(2), RHS = N->getOperand(3);
2850 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
2851 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
2852 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
2853 assert(isDot && "Can't compare against a vector result!");
2855 // If this is a comparison against something other than 0/1, then we know
2856 // that the condition is never/always true.
2857 unsigned Val = cast<ConstantSDNode>(RHS)->getValue();
2858 if (Val != 0 && Val != 1) {
2859 if (CC == ISD::SETEQ) // Cond never true, remove branch.
2860 return N->getOperand(0);
2861 // Always !=, turn it into an unconditional branch.
2862 return DAG.getNode(ISD::BR, MVT::Other,
2863 N->getOperand(0), N->getOperand(4));
2866 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
2868 // Create the PPCISD altivec 'dot' comparison node.
2869 std::vector<MVT::ValueType> VTs;
2871 LHS.getOperand(2), // LHS of compare
2872 LHS.getOperand(3), // RHS of compare
2873 DAG.getConstant(CompareOpc, MVT::i32)
2875 VTs.push_back(LHS.getOperand(2).getValueType());
2876 VTs.push_back(MVT::Flag);
2877 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
2879 // Unpack the result based on how the target uses it.
2880 PPC::Predicate CompOpc;
2881 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) {
2882 default: // Can't happen, don't crash on invalid number though.
2883 case 0: // Branch on the value of the EQ bit of CR6.
2884 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
2886 case 1: // Branch on the inverted value of the EQ bit of CR6.
2887 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
2889 case 2: // Branch on the value of the LT bit of CR6.
2890 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
2892 case 3: // Branch on the inverted value of the LT bit of CR6.
2893 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
2897 return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0),
2898 DAG.getConstant(CompOpc, MVT::i32),
2899 DAG.getRegister(PPC::CR6, MVT::i32),
2900 N->getOperand(4), CompNode.getValue(1));
2909 //===----------------------------------------------------------------------===//
2910 // Inline Assembly Support
2911 //===----------------------------------------------------------------------===//
2913 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
2915 uint64_t &KnownZero,
2917 unsigned Depth) const {
2920 switch (Op.getOpcode()) {
2922 case PPCISD::LBRX: {
2923 // lhbrx is known to have the top bits cleared out.
2924 if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16)
2925 KnownZero = 0xFFFF0000;
2928 case ISD::INTRINSIC_WO_CHAIN: {
2929 switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) {
2931 case Intrinsic::ppc_altivec_vcmpbfp_p:
2932 case Intrinsic::ppc_altivec_vcmpeqfp_p:
2933 case Intrinsic::ppc_altivec_vcmpequb_p:
2934 case Intrinsic::ppc_altivec_vcmpequh_p:
2935 case Intrinsic::ppc_altivec_vcmpequw_p:
2936 case Intrinsic::ppc_altivec_vcmpgefp_p:
2937 case Intrinsic::ppc_altivec_vcmpgtfp_p:
2938 case Intrinsic::ppc_altivec_vcmpgtsb_p:
2939 case Intrinsic::ppc_altivec_vcmpgtsh_p:
2940 case Intrinsic::ppc_altivec_vcmpgtsw_p:
2941 case Intrinsic::ppc_altivec_vcmpgtub_p:
2942 case Intrinsic::ppc_altivec_vcmpgtuh_p:
2943 case Intrinsic::ppc_altivec_vcmpgtuw_p:
2944 KnownZero = ~1U; // All bits but the low one are known to be zero.
2952 /// getConstraintType - Given a constraint letter, return the type of
2953 /// constraint it is for this target.
2954 PPCTargetLowering::ConstraintType
2955 PPCTargetLowering::getConstraintType(char ConstraintLetter) const {
2956 switch (ConstraintLetter) {
2963 return C_RegisterClass;
2965 return TargetLowering::getConstraintType(ConstraintLetter);
2968 std::pair<unsigned, const TargetRegisterClass*>
2969 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
2970 MVT::ValueType VT) const {
2971 if (Constraint.size() == 1) {
2972 // GCC RS6000 Constraint Letters
2973 switch (Constraint[0]) {
2976 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
2977 return std::make_pair(0U, PPC::G8RCRegisterClass);
2978 return std::make_pair(0U, PPC::GPRCRegisterClass);
2981 return std::make_pair(0U, PPC::F4RCRegisterClass);
2982 else if (VT == MVT::f64)
2983 return std::make_pair(0U, PPC::F8RCRegisterClass);
2986 return std::make_pair(0U, PPC::VRRCRegisterClass);
2988 return std::make_pair(0U, PPC::CRRCRegisterClass);
2992 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
2996 // isOperandValidForConstraint
2997 SDOperand PPCTargetLowering::
2998 isOperandValidForConstraint(SDOperand Op, char Letter, SelectionDAG &DAG) {
3009 if (!isa<ConstantSDNode>(Op)) return SDOperand(0,0);// Must be an immediate.
3010 unsigned Value = cast<ConstantSDNode>(Op)->getValue();
3012 default: assert(0 && "Unknown constraint letter!");
3013 case 'I': // "I" is a signed 16-bit constant.
3014 if ((short)Value == (int)Value) return Op;
3016 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
3017 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
3018 if ((short)Value == 0) return Op;
3020 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
3021 if ((Value >> 16) == 0) return Op;
3023 case 'M': // "M" is a constant that is greater than 31.
3024 if (Value > 31) return Op;
3026 case 'N': // "N" is a positive constant that is an exact power of two.
3027 if ((int)Value > 0 && isPowerOf2_32(Value)) return Op;
3029 case 'O': // "O" is the constant zero.
3030 if (Value == 0) return Op;
3032 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
3033 if ((short)-Value == (int)-Value) return Op;
3040 // Handle standard constraint letters.
3041 return TargetLowering::isOperandValidForConstraint(Op, Letter, DAG);
3044 /// isLegalAddressImmediate - Return true if the integer value can be used
3045 /// as the offset of the target addressing mode.
3046 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V) const {
3047 // PPC allows a sign-extended 16-bit immediate field.
3048 return (V > -(1 << 16) && V < (1 << 16)-1);
3051 bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
3052 return TargetLowering::isLegalAddressImmediate(GV);