1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCTargetMachine.h"
16 #include "PPCPerfectShuffle.h"
17 #include "llvm/ADT/VectorExtras.h"
18 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SSARegMap.h"
24 #include "llvm/Constants.h"
25 #include "llvm/Function.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/Target/TargetOptions.h"
31 PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
32 : TargetLowering(TM) {
34 // Fold away setcc operations if possible.
35 setSetCCIsExpensive();
38 // Use _setjmp/_longjmp instead of setjmp/longjmp.
39 setUseUnderscoreSetJmpLongJmp(true);
41 // Set up the register classes.
42 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
43 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
44 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
46 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
47 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
49 // PowerPC has no intrinsics for these particular operations
50 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
51 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
52 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
54 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
55 setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
56 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
58 // PowerPC has no SREM/UREM instructions
59 setOperationAction(ISD::SREM, MVT::i32, Expand);
60 setOperationAction(ISD::UREM, MVT::i32, Expand);
62 // We don't support sin/cos/sqrt/fmod
63 setOperationAction(ISD::FSIN , MVT::f64, Expand);
64 setOperationAction(ISD::FCOS , MVT::f64, Expand);
65 setOperationAction(ISD::FREM , MVT::f64, Expand);
66 setOperationAction(ISD::FSIN , MVT::f32, Expand);
67 setOperationAction(ISD::FCOS , MVT::f32, Expand);
68 setOperationAction(ISD::FREM , MVT::f32, Expand);
70 // If we're enabling GP optimizations, use hardware square root
71 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
72 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
73 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
76 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
77 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
79 // PowerPC does not have BSWAP, CTPOP or CTTZ
80 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
81 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
82 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
84 // PowerPC does not have ROTR
85 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
87 // PowerPC does not have Select
88 setOperationAction(ISD::SELECT, MVT::i32, Expand);
89 setOperationAction(ISD::SELECT, MVT::f32, Expand);
90 setOperationAction(ISD::SELECT, MVT::f64, Expand);
92 // PowerPC wants to turn select_cc of FP into fsel when possible.
93 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
94 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
96 // PowerPC wants to optimize integer setcc a bit
97 setOperationAction(ISD::SETCC, MVT::i32, Custom);
99 // PowerPC does not have BRCOND which requires SetCC
100 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
102 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
103 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
105 // PowerPC does not have [U|S]INT_TO_FP
106 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
107 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
109 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
110 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
112 // PowerPC does not have truncstore for i1.
113 setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
115 // We cannot sextinreg(i1). Expand to shifts.
116 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
119 // Support label based line numbers.
120 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
121 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
122 // FIXME - use subtarget debug flags
123 if (!TM.getSubtarget<PPCSubtarget>().isDarwin())
124 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
126 // We want to legalize GlobalAddress and ConstantPool nodes into the
127 // appropriate instructions to materialize the address.
128 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
129 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
130 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
131 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
132 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
133 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
135 // RET must be custom lowered, to meet ABI requirements
136 setOperationAction(ISD::RET , MVT::Other, Custom);
138 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
139 setOperationAction(ISD::VASTART , MVT::Other, Custom);
141 // Use the default implementation.
142 setOperationAction(ISD::VAARG , MVT::Other, Expand);
143 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
144 setOperationAction(ISD::VAEND , MVT::Other, Expand);
145 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
146 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
147 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
149 // We want to custom lower some of our intrinsics.
150 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
152 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
153 // They also have instructions for converting between i64 and fp.
154 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
155 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
157 // FIXME: disable this lowered code. This generates 64-bit register values,
158 // and we don't model the fact that the top part is clobbered by calls. We
159 // need to flag these together so that the value isn't live across a call.
160 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
162 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
163 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
165 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
166 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
169 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
170 // 64 bit PowerPC implementations can support i64 types directly
171 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
172 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
173 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
175 // 32 bit PowerPC wants to expand i64 shifts itself.
176 setOperationAction(ISD::SHL, MVT::i64, Custom);
177 setOperationAction(ISD::SRL, MVT::i64, Custom);
178 setOperationAction(ISD::SRA, MVT::i64, Custom);
181 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
182 // First set operation action for all vector types to expand. Then we
183 // will selectively turn on ones that can be effectively codegen'd.
184 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
185 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
186 // add/sub are legal for all supported vector VT's.
187 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal);
188 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal);
190 // We promote all shuffles to v16i8.
191 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote);
192 AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8);
194 // We promote all non-typed operations to v4i32.
195 setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote);
196 AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32);
197 setOperationAction(ISD::OR , (MVT::ValueType)VT, Promote);
198 AddPromotedToType (ISD::OR , (MVT::ValueType)VT, MVT::v4i32);
199 setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote);
200 AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32);
201 setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote);
202 AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32);
203 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
204 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32);
205 setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote);
206 AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32);
208 // No other operations are legal.
209 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
210 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
211 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
212 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
213 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
214 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
215 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
216 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
217 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
219 setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand);
222 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
223 // with merges, splats, etc.
224 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
226 setOperationAction(ISD::AND , MVT::v4i32, Legal);
227 setOperationAction(ISD::OR , MVT::v4i32, Legal);
228 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
229 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
230 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
231 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
233 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
234 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
235 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
236 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
238 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
239 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
240 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
241 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
243 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
244 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
246 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
247 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
248 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
249 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
252 setSetCCResultContents(ZeroOrOneSetCCResult);
253 setStackPointerRegisterToSaveRestore(PPC::R1);
255 // We have target-specific dag combine patterns for the following nodes:
256 setTargetDAGCombine(ISD::SINT_TO_FP);
257 setTargetDAGCombine(ISD::STORE);
258 setTargetDAGCombine(ISD::BR_CC);
260 computeRegisterProperties();
263 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
266 case PPCISD::FSEL: return "PPCISD::FSEL";
267 case PPCISD::FCFID: return "PPCISD::FCFID";
268 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
269 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
270 case PPCISD::STFIWX: return "PPCISD::STFIWX";
271 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
272 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
273 case PPCISD::VPERM: return "PPCISD::VPERM";
274 case PPCISD::Hi: return "PPCISD::Hi";
275 case PPCISD::Lo: return "PPCISD::Lo";
276 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
277 case PPCISD::SRL: return "PPCISD::SRL";
278 case PPCISD::SRA: return "PPCISD::SRA";
279 case PPCISD::SHL: return "PPCISD::SHL";
280 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
281 case PPCISD::STD_32: return "PPCISD::STD_32";
282 case PPCISD::CALL: return "PPCISD::CALL";
283 case PPCISD::MTCTR: return "PPCISD::MTCTR";
284 case PPCISD::BCTRL: return "PPCISD::BCTRL";
285 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
286 case PPCISD::MFCR: return "PPCISD::MFCR";
287 case PPCISD::VCMP: return "PPCISD::VCMP";
288 case PPCISD::VCMPo: return "PPCISD::VCMPo";
289 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
293 //===----------------------------------------------------------------------===//
294 // Node matching predicates, for use by the tblgen matching code.
295 //===----------------------------------------------------------------------===//
297 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
298 static bool isFloatingPointZero(SDOperand Op) {
299 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
300 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
301 else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) {
302 // Maybe this has already been legalized into the constant pool?
303 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
304 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->get()))
305 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
310 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
311 /// true if Op is undef or if it matches the specified value.
312 static bool isConstantOrUndef(SDOperand Op, unsigned Val) {
313 return Op.getOpcode() == ISD::UNDEF ||
314 cast<ConstantSDNode>(Op)->getValue() == Val;
317 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
318 /// VPKUHUM instruction.
319 bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) {
321 for (unsigned i = 0; i != 16; ++i)
322 if (!isConstantOrUndef(N->getOperand(i), i*2+1))
325 for (unsigned i = 0; i != 8; ++i)
326 if (!isConstantOrUndef(N->getOperand(i), i*2+1) ||
327 !isConstantOrUndef(N->getOperand(i+8), i*2+1))
333 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
334 /// VPKUWUM instruction.
335 bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) {
337 for (unsigned i = 0; i != 16; i += 2)
338 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
339 !isConstantOrUndef(N->getOperand(i+1), i*2+3))
342 for (unsigned i = 0; i != 8; i += 2)
343 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
344 !isConstantOrUndef(N->getOperand(i+1), i*2+3) ||
345 !isConstantOrUndef(N->getOperand(i+8), i*2+2) ||
346 !isConstantOrUndef(N->getOperand(i+9), i*2+3))
352 /// isVMerge - Common function, used to match vmrg* shuffles.
354 static bool isVMerge(SDNode *N, unsigned UnitSize,
355 unsigned LHSStart, unsigned RHSStart) {
356 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
357 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
358 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
359 "Unsupported merge size!");
361 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
362 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
363 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j),
364 LHSStart+j+i*UnitSize) ||
365 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j),
366 RHSStart+j+i*UnitSize))
372 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
373 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
374 bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
376 return isVMerge(N, UnitSize, 8, 24);
377 return isVMerge(N, UnitSize, 8, 8);
380 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
381 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
382 bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
384 return isVMerge(N, UnitSize, 0, 16);
385 return isVMerge(N, UnitSize, 0, 0);
389 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
390 /// amount, otherwise return -1.
391 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
392 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
393 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
394 // Find the first non-undef value in the shuffle mask.
396 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i)
399 if (i == 16) return -1; // all undef.
401 // Otherwise, check to see if the rest of the elements are consequtively
402 // numbered from this value.
403 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue();
404 if (ShiftAmt < i) return -1;
408 // Check the rest of the elements to see if they are consequtive.
409 for (++i; i != 16; ++i)
410 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i))
413 // Check the rest of the elements to see if they are consequtive.
414 for (++i; i != 16; ++i)
415 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15))
422 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
423 /// specifies a splat of a single element that is suitable for input to
424 /// VSPLTB/VSPLTH/VSPLTW.
425 bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) {
426 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
427 N->getNumOperands() == 16 &&
428 (EltSize == 1 || EltSize == 2 || EltSize == 4));
430 // This is a splat operation if each element of the permute is the same, and
431 // if the value doesn't reference the second vector.
432 unsigned ElementBase = 0;
433 SDOperand Elt = N->getOperand(0);
434 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt))
435 ElementBase = EltV->getValue();
437 return false; // FIXME: Handle UNDEF elements too!
439 if (cast<ConstantSDNode>(Elt)->getValue() >= 16)
442 // Check that they are consequtive.
443 for (unsigned i = 1; i != EltSize; ++i) {
444 if (!isa<ConstantSDNode>(N->getOperand(i)) ||
445 cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase)
449 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
450 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
451 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
452 assert(isa<ConstantSDNode>(N->getOperand(i)) &&
453 "Invalid VECTOR_SHUFFLE mask!");
454 for (unsigned j = 0; j != EltSize; ++j)
455 if (N->getOperand(i+j) != N->getOperand(j))
462 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
463 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
464 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
465 assert(isSplatShuffleMask(N, EltSize));
466 return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize;
469 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
470 /// by using a vspltis[bhw] instruction of the specified element size, return
471 /// the constant being splatted. The ByteSize field indicates the number of
472 /// bytes of each element [124] -> [bhw].
473 SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
474 SDOperand OpVal(0, 0);
476 // If ByteSize of the splat is bigger than the element size of the
477 // build_vector, then we have a case where we are checking for a splat where
478 // multiple elements of the buildvector are folded together into a single
479 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
480 unsigned EltSize = 16/N->getNumOperands();
481 if (EltSize < ByteSize) {
482 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
483 SDOperand UniquedVals[4];
484 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
486 // See if all of the elements in the buildvector agree across.
487 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
488 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
489 // If the element isn't a constant, bail fully out.
490 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand();
493 if (UniquedVals[i&(Multiple-1)].Val == 0)
494 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
495 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
496 return SDOperand(); // no match.
499 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
500 // either constant or undef values that are identical for each chunk. See
501 // if these chunks can form into a larger vspltis*.
503 // Check to see if all of the leading entries are either 0 or -1. If
504 // neither, then this won't fit into the immediate field.
505 bool LeadingZero = true;
506 bool LeadingOnes = true;
507 for (unsigned i = 0; i != Multiple-1; ++i) {
508 if (UniquedVals[i].Val == 0) continue; // Must have been undefs.
510 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
511 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
513 // Finally, check the least significant entry.
515 if (UniquedVals[Multiple-1].Val == 0)
516 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
517 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue();
519 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
522 if (UniquedVals[Multiple-1].Val == 0)
523 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
524 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended();
525 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
526 return DAG.getTargetConstant(Val, MVT::i32);
532 // Check to see if this buildvec has a single non-undef value in its elements.
533 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
534 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
536 OpVal = N->getOperand(i);
537 else if (OpVal != N->getOperand(i))
541 if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def.
543 unsigned ValSizeInBytes = 0;
545 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
546 Value = CN->getValue();
547 ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8;
548 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
549 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
550 Value = FloatToBits(CN->getValue());
554 // If the splat value is larger than the element value, then we can never do
555 // this splat. The only case that we could fit the replicated bits into our
556 // immediate field for would be zero, and we prefer to use vxor for it.
557 if (ValSizeInBytes < ByteSize) return SDOperand();
559 // If the element value is larger than the splat value, cut it in half and
560 // check to see if the two halves are equal. Continue doing this until we
561 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
562 while (ValSizeInBytes > ByteSize) {
563 ValSizeInBytes >>= 1;
565 // If the top half equals the bottom half, we're still ok.
566 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
567 (Value & ((1 << (8*ValSizeInBytes))-1)))
571 // Properly sign extend the value.
572 int ShAmt = (4-ByteSize)*8;
573 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
575 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
576 if (MaskVal == 0) return SDOperand();
578 // Finally, if this value fits in a 5 bit sext field, return it
579 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
580 return DAG.getTargetConstant(MaskVal, MVT::i32);
584 //===----------------------------------------------------------------------===//
585 // LowerOperation implementation
586 //===----------------------------------------------------------------------===//
588 static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
589 MVT::ValueType PtrVT = Op.getValueType();
590 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
591 Constant *C = CP->get();
592 SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
593 SDOperand Zero = DAG.getConstant(0, PtrVT);
595 const TargetMachine &TM = DAG.getTarget();
597 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero);
598 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero);
600 // If this is a non-darwin platform, we don't support non-static relo models
602 if (TM.getRelocationModel() == Reloc::Static ||
603 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
604 // Generate non-pic code that has direct accesses to the constant pool.
605 // The address of the global is just (hi(&g)+lo(&g)).
606 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
609 if (TM.getRelocationModel() == Reloc::PIC) {
610 // With PIC, the first instruction is actually "GR+hi(&G)".
611 Hi = DAG.getNode(ISD::ADD, PtrVT,
612 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
615 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
619 static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
620 MVT::ValueType PtrVT = Op.getValueType();
621 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
622 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
623 SDOperand Zero = DAG.getConstant(0, PtrVT);
625 const TargetMachine &TM = DAG.getTarget();
627 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero);
628 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero);
630 // If this is a non-darwin platform, we don't support non-static relo models
632 if (TM.getRelocationModel() == Reloc::Static ||
633 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
634 // Generate non-pic code that has direct accesses to the constant pool.
635 // The address of the global is just (hi(&g)+lo(&g)).
636 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
639 if (TM.getRelocationModel() == Reloc::PIC) {
640 // With PIC, the first instruction is actually "GR+hi(&G)".
641 Hi = DAG.getNode(ISD::ADD, PtrVT,
642 DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi);
645 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
649 static SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
650 MVT::ValueType PtrVT = Op.getValueType();
651 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
652 GlobalValue *GV = GSDN->getGlobal();
653 SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
654 SDOperand Zero = DAG.getConstant(0, PtrVT);
656 const TargetMachine &TM = DAG.getTarget();
658 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero);
659 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero);
661 // If this is a non-darwin platform, we don't support non-static relo models
663 if (TM.getRelocationModel() == Reloc::Static ||
664 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
665 // Generate non-pic code that has direct accesses to globals.
666 // The address of the global is just (hi(&g)+lo(&g)).
667 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
670 if (TM.getRelocationModel() == Reloc::PIC) {
671 // With PIC, the first instruction is actually "GR+hi(&G)".
672 Hi = DAG.getNode(ISD::ADD, PtrVT,
673 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
676 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
678 if (!GV->hasWeakLinkage() && !GV->hasLinkOnceLinkage() &&
679 (!GV->isExternal() || GV->hasNotBeenReadFromBytecode()))
682 // If the global is weak or external, we have to go through the lazy
684 return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, DAG.getSrcValue(0));
687 static SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
688 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
690 // If we're comparing for equality to zero, expose the fact that this is
691 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
692 // fold the new nodes.
693 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
694 if (C->isNullValue() && CC == ISD::SETEQ) {
695 MVT::ValueType VT = Op.getOperand(0).getValueType();
696 SDOperand Zext = Op.getOperand(0);
699 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0));
701 unsigned Log2b = Log2_32(MVT::getSizeInBits(VT));
702 SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext);
703 SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz,
704 DAG.getConstant(Log2b, MVT::i32));
705 return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc);
707 // Leave comparisons against 0 and -1 alone for now, since they're usually
708 // optimized. FIXME: revisit this when we can custom lower all setcc
710 if (C->isAllOnesValue() || C->isNullValue())
714 // If we have an integer seteq/setne, turn it into a compare against zero
715 // by subtracting the rhs from the lhs, which is faster than setting a
716 // condition register, reading it back out, and masking the correct bit.
717 MVT::ValueType LHSVT = Op.getOperand(0).getValueType();
718 if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
719 MVT::ValueType VT = Op.getValueType();
720 SDOperand Sub = DAG.getNode(ISD::SUB, LHSVT, Op.getOperand(0),
722 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC);
727 static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
728 unsigned VarArgsFrameIndex) {
729 // vastart just stores the address of the VarArgsFrameIndex slot into the
730 // memory location argument.
731 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
732 return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), FR,
733 Op.getOperand(1), Op.getOperand(2));
736 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
737 int &VarArgsFrameIndex) {
738 // TODO: add description of PPC stack frame format, or at least some docs.
740 MachineFunction &MF = DAG.getMachineFunction();
741 MachineFrameInfo *MFI = MF.getFrameInfo();
742 SSARegMap *RegMap = MF.getSSARegMap();
743 std::vector<SDOperand> ArgValues;
744 SDOperand Root = Op.getOperand(0);
746 unsigned ArgOffset = 24;
747 const unsigned Num_GPR_Regs = 8;
748 const unsigned Num_FPR_Regs = 13;
749 const unsigned Num_VR_Regs = 12;
750 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
751 static const unsigned GPR[] = {
752 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
753 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
755 static const unsigned FPR[] = {
756 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
757 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
759 static const unsigned VR[] = {
760 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
761 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
764 // Add DAG nodes to load the arguments or copy them out of registers. On
765 // entry to a function on PPC, the arguments start at offset 24, although the
766 // first ones are often in registers.
767 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
769 bool needsLoad = false;
770 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
771 unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8;
773 unsigned CurArgOffset = ArgOffset;
776 default: assert(0 && "Unhandled argument type!");
778 // All int arguments reserve stack space.
781 if (GPR_idx != Num_GPR_Regs) {
782 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
783 MF.addLiveIn(GPR[GPR_idx], VReg);
784 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32);
792 // All FP arguments reserve stack space.
793 ArgOffset += ObjSize;
795 // Every 4 bytes of argument space consumes one of the GPRs available for
797 if (GPR_idx != Num_GPR_Regs) {
799 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs)
802 if (FPR_idx != Num_FPR_Regs) {
804 if (ObjectVT == MVT::f32)
805 VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass);
807 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass);
808 MF.addLiveIn(FPR[FPR_idx], VReg);
809 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
819 // Note that vector arguments in registers don't reserve stack space.
820 if (VR_idx != Num_VR_Regs) {
821 unsigned VReg = RegMap->createVirtualRegister(&PPC::VRRCRegClass);
822 MF.addLiveIn(VR[VR_idx], VReg);
823 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
826 // This should be simple, but requires getting 16-byte aligned stack
828 assert(0 && "Loading VR argument not implemented yet!");
834 // We need to load the argument to a virtual register if we determined above
835 // that we ran out of physical registers of the appropriate type
837 // If the argument is actually used, emit a load from the right stack
839 if (!Op.Val->hasNUsesOfValue(0, ArgNo)) {
840 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset);
841 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
842 ArgVal = DAG.getLoad(ObjectVT, Root, FIN,
843 DAG.getSrcValue(NULL));
845 // Don't emit a dead load.
846 ArgVal = DAG.getNode(ISD::UNDEF, ObjectVT);
850 ArgValues.push_back(ArgVal);
853 // If the function takes variable number of arguments, make a frame index for
854 // the start of the first vararg value... for expansion of llvm.va_start.
855 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
857 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
858 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
859 // If this function is vararg, store any remaining integer argument regs
860 // to their spots on the stack so that they may be loaded by deferencing the
861 // result of va_next.
862 std::vector<SDOperand> MemOps;
863 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
864 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
865 MF.addLiveIn(GPR[GPR_idx], VReg);
866 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i32);
867 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
868 Val, FIN, DAG.getSrcValue(NULL));
869 MemOps.push_back(Store);
870 // Increment the address by four for the next argument to store
871 SDOperand PtrOff = DAG.getConstant(4, MVT::i32);
872 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, PtrOff);
875 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps);
878 ArgValues.push_back(Root);
880 // Return the new list of results.
881 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
882 Op.Val->value_end());
883 return DAG.getNode(ISD::MERGE_VALUES, RetVT, ArgValues);
886 /// isCallCompatibleAddress - Return the immediate to use if the specified
887 /// 32-bit value is representable in the immediate field of a BxA instruction.
888 static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) {
889 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
892 int Addr = C->getValue();
893 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
894 (Addr << 6 >> 6) != Addr)
895 return 0; // Top 6 bits have to be sext of immediate.
897 return DAG.getConstant((int)C->getValue() >> 2, MVT::i32).Val;
901 static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
902 SDOperand Chain = Op.getOperand(0);
903 unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue();
904 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
905 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
906 SDOperand Callee = Op.getOperand(4);
907 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
909 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in
910 // SelectExpr to use to put the arguments in the appropriate registers.
911 std::vector<SDOperand> args_to_use;
913 // Count how many bytes are to be pushed on the stack, including the linkage
914 // area, and parameter passing area. We start with 24 bytes, which is
915 // prereserved space for [SP][CR][LR][3 x unused].
916 unsigned NumBytes = 24;
918 // Add up all the space actually used.
919 for (unsigned i = 0; i != NumOps; ++i)
920 NumBytes += MVT::getSizeInBits(Op.getOperand(5+2*i).getValueType())/8;
922 // The prolog code of the callee may store up to 8 GPR argument registers to
923 // the stack, allowing va_start to index over them in memory if its varargs.
924 // Because we cannot tell if this is needed on the caller side, we have to
925 // conservatively assume that it is needed. As such, make sure we have at
926 // least enough stack space for the caller to store the 8 GPRs.
927 if (NumBytes < 24+8*4)
930 // Adjust the stack pointer for the new arguments...
931 // These operations are automatically eliminated by the prolog/epilog pass
932 Chain = DAG.getCALLSEQ_START(Chain,
933 DAG.getConstant(NumBytes, MVT::i32));
935 // Set up a copy of the stack pointer for use loading and storing any
936 // arguments that may not fit in the registers available for argument
938 SDOperand StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
940 // Figure out which arguments are going to go in registers, and which in
941 // memory. Also, if this is a vararg function, floating point operations
942 // must be stored to our stack, and loaded into integer regs as well, if
943 // any integer regs are available for argument passing.
944 unsigned ArgOffset = 24;
945 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
946 static const unsigned GPR[] = {
947 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
948 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
950 static const unsigned FPR[] = {
951 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
952 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
954 static const unsigned VR[] = {
955 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
956 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
958 const unsigned NumGPRs = sizeof(GPR)/sizeof(GPR[0]);
959 const unsigned NumFPRs = sizeof(FPR)/sizeof(FPR[0]);
960 const unsigned NumVRs = sizeof( VR)/sizeof( VR[0]);
962 std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
963 std::vector<SDOperand> MemOpChains;
964 for (unsigned i = 0; i != NumOps; ++i) {
965 SDOperand Arg = Op.getOperand(5+2*i);
967 // PtrOff will be used to store the current argument to the stack if a
968 // register cannot be found for it.
969 SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
970 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
971 switch (Arg.getValueType()) {
972 default: assert(0 && "Unexpected ValueType for argument!");
974 if (GPR_idx != NumGPRs) {
975 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
977 MemOpChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
978 Arg, PtrOff, DAG.getSrcValue(NULL)));
984 if (FPR_idx != NumFPRs) {
985 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
988 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
990 DAG.getSrcValue(NULL));
991 MemOpChains.push_back(Store);
993 // Float varargs are always shadowed in available integer registers
994 if (GPR_idx != NumGPRs) {
995 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
996 DAG.getSrcValue(NULL));
997 MemOpChains.push_back(Load.getValue(1));
998 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
1000 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64) {
1001 SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType());
1002 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
1003 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
1004 DAG.getSrcValue(NULL));
1005 MemOpChains.push_back(Load.getValue(1));
1006 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
1009 // If we have any FPRs remaining, we may also have GPRs remaining.
1010 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
1012 if (GPR_idx != NumGPRs)
1014 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64)
1018 MemOpChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
1019 Arg, PtrOff, DAG.getSrcValue(NULL)));
1021 ArgOffset += (Arg.getValueType() == MVT::f32) ? 4 : 8;
1027 assert(!isVarArg && "Don't support passing vectors to varargs yet!");
1028 assert(VR_idx != NumVRs &&
1029 "Don't support passing more than 12 vector args yet!");
1030 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
1034 if (!MemOpChains.empty())
1035 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOpChains);
1037 // Build a sequence of copy-to-reg nodes chained together with token chain
1038 // and flag operands which copy the outgoing args into the appropriate regs.
1040 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1041 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1043 InFlag = Chain.getValue(1);
1046 std::vector<MVT::ValueType> NodeTys;
1047 NodeTys.push_back(MVT::Other); // Returns a chain
1048 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
1050 std::vector<SDOperand> Ops;
1051 unsigned CallOpc = PPCISD::CALL;
1053 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1054 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1055 // node so that legalize doesn't hack it.
1056 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1057 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
1058 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1059 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType());
1060 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
1061 // If this is an absolute destination address, use the munged value.
1062 Callee = SDOperand(Dest, 0);
1064 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
1065 // to do the call, we can't use PPCISD::CALL.
1066 Ops.push_back(Chain);
1067 Ops.push_back(Callee);
1070 Ops.push_back(InFlag);
1071 Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, Ops);
1072 InFlag = Chain.getValue(1);
1074 // Copy the callee address into R12 on darwin.
1075 Chain = DAG.getCopyToReg(Chain, PPC::R12, Callee, InFlag);
1076 InFlag = Chain.getValue(1);
1079 NodeTys.push_back(MVT::Other);
1080 NodeTys.push_back(MVT::Flag);
1082 Ops.push_back(Chain);
1083 CallOpc = PPCISD::BCTRL;
1087 // If this is a direct call, pass the chain and the callee.
1089 Ops.push_back(Chain);
1090 Ops.push_back(Callee);
1093 // Add argument registers to the end of the list so that they are known live
1095 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1096 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1097 RegsToPass[i].second.getValueType()));
1100 Ops.push_back(InFlag);
1101 Chain = DAG.getNode(CallOpc, NodeTys, Ops);
1102 InFlag = Chain.getValue(1);
1104 std::vector<SDOperand> ResultVals;
1107 // If the call has results, copy the values out of the ret val registers.
1108 switch (Op.Val->getValueType(0)) {
1109 default: assert(0 && "Unexpected ret value!");
1110 case MVT::Other: break;
1112 if (Op.Val->getValueType(1) == MVT::i32) {
1113 Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32, InFlag).getValue(1);
1114 ResultVals.push_back(Chain.getValue(0));
1115 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32,
1116 Chain.getValue(2)).getValue(1);
1117 ResultVals.push_back(Chain.getValue(0));
1118 NodeTys.push_back(MVT::i32);
1120 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1);
1121 ResultVals.push_back(Chain.getValue(0));
1123 NodeTys.push_back(MVT::i32);
1127 Chain = DAG.getCopyFromReg(Chain, PPC::F1, Op.Val->getValueType(0),
1128 InFlag).getValue(1);
1129 ResultVals.push_back(Chain.getValue(0));
1130 NodeTys.push_back(Op.Val->getValueType(0));
1136 Chain = DAG.getCopyFromReg(Chain, PPC::V2, Op.Val->getValueType(0),
1137 InFlag).getValue(1);
1138 ResultVals.push_back(Chain.getValue(0));
1139 NodeTys.push_back(Op.Val->getValueType(0));
1143 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
1144 DAG.getConstant(NumBytes, MVT::i32));
1145 NodeTys.push_back(MVT::Other);
1147 // If the function returns void, just return the chain.
1148 if (ResultVals.empty())
1151 // Otherwise, merge everything together with a MERGE_VALUES node.
1152 ResultVals.push_back(Chain);
1153 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, ResultVals);
1154 return Res.getValue(Op.ResNo);
1157 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
1159 switch(Op.getNumOperands()) {
1161 assert(0 && "Do not know how to return this many arguments!");
1164 return SDOperand(); // ret void is legal
1166 MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
1168 if (MVT::isVector(ArgVT))
1170 else if (MVT::isInteger(ArgVT))
1173 assert(MVT::isFloatingPoint(ArgVT));
1177 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
1180 // If we haven't noted the R3/F1 are live out, do so now.
1181 if (DAG.getMachineFunction().liveout_empty())
1182 DAG.getMachineFunction().addLiveOut(ArgReg);
1186 Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(3),
1188 Copy = DAG.getCopyToReg(Copy, PPC::R4, Op.getOperand(1),Copy.getValue(1));
1189 // If we haven't noted the R3+R4 are live out, do so now.
1190 if (DAG.getMachineFunction().liveout_empty()) {
1191 DAG.getMachineFunction().addLiveOut(PPC::R3);
1192 DAG.getMachineFunction().addLiveOut(PPC::R4);
1196 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
1199 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
1201 static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
1202 // Not FP? Not a fsel.
1203 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) ||
1204 !MVT::isFloatingPoint(Op.getOperand(2).getValueType()))
1207 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1209 // Cannot handle SETEQ/SETNE.
1210 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand();
1212 MVT::ValueType ResVT = Op.getValueType();
1213 MVT::ValueType CmpVT = Op.getOperand(0).getValueType();
1214 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
1215 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3);
1217 // If the RHS of the comparison is a 0.0, we don't need to do the
1218 // subtraction at all.
1219 if (isFloatingPointZero(RHS))
1221 default: break; // SETUO etc aren't handled by fsel.
1225 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
1229 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
1230 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
1231 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
1235 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
1239 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
1240 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
1241 return DAG.getNode(PPCISD::FSEL, ResVT,
1242 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV);
1247 default: break; // SETUO etc aren't handled by fsel.
1251 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
1252 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1253 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1254 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
1258 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
1259 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1260 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1261 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
1265 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
1266 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1267 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1268 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
1272 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
1273 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1274 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1275 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
1280 static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
1281 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType()));
1282 SDOperand Src = Op.getOperand(0);
1283 if (Src.getValueType() == MVT::f32)
1284 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src);
1287 switch (Op.getValueType()) {
1288 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
1290 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src);
1293 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src);
1297 // Convert the FP value to an int value through memory.
1298 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Tmp);
1299 if (Op.getValueType() == MVT::i32)
1300 Bits = DAG.getNode(ISD::TRUNCATE, MVT::i32, Bits);
1304 static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
1305 if (Op.getOperand(0).getValueType() == MVT::i64) {
1306 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
1307 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
1308 if (Op.getValueType() == MVT::f32)
1309 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
1313 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
1314 "Unhandled SINT_TO_FP type in custom expander!");
1315 // Since we only generate this in 64-bit mode, we can take advantage of
1316 // 64-bit registers. In particular, sign extend the input value into the
1317 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
1318 // then lfd it and fcfid it.
1319 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
1320 int FrameIdx = FrameInfo->CreateStackObject(8, 8);
1321 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, MVT::i32);
1323 SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32,
1326 // STD the extended value into the stack slot.
1327 SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other,
1328 DAG.getEntryNode(), Ext64, FIdx,
1329 DAG.getSrcValue(NULL));
1330 // Load the value as a double.
1331 SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, DAG.getSrcValue(NULL));
1333 // FCFID it and return it.
1334 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld);
1335 if (Op.getValueType() == MVT::f32)
1336 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
1340 static SDOperand LowerSHL(SDOperand Op, SelectionDAG &DAG,
1341 MVT::ValueType PtrVT) {
1342 assert(Op.getValueType() == MVT::i64 &&
1343 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
1344 // The generic code does a fine job expanding shift by a constant.
1345 if (isa<ConstantSDNode>(Op.getOperand(1))) return SDOperand();
1347 // Otherwise, expand into a bunch of logical ops. Note that these ops
1348 // depend on the PPC behavior for oversized shift amounts.
1349 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1350 DAG.getConstant(0, PtrVT));
1351 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1352 DAG.getConstant(1, PtrVT));
1353 SDOperand Amt = Op.getOperand(1);
1355 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
1356 DAG.getConstant(32, MVT::i32), Amt);
1357 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt);
1358 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1);
1359 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
1360 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
1361 DAG.getConstant(-32U, MVT::i32));
1362 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5);
1363 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
1364 SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt);
1365 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
1368 static SDOperand LowerSRL(SDOperand Op, SelectionDAG &DAG,
1369 MVT::ValueType PtrVT) {
1370 assert(Op.getValueType() == MVT::i64 &&
1371 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
1372 // The generic code does a fine job expanding shift by a constant.
1373 if (isa<ConstantSDNode>(Op.getOperand(1))) return SDOperand();
1375 // Otherwise, expand into a bunch of logical ops. Note that these ops
1376 // depend on the PPC behavior for oversized shift amounts.
1377 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1378 DAG.getConstant(0, PtrVT));
1379 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1380 DAG.getConstant(1, PtrVT));
1381 SDOperand Amt = Op.getOperand(1);
1383 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
1384 DAG.getConstant(32, MVT::i32), Amt);
1385 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
1386 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
1387 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
1388 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
1389 DAG.getConstant(-32U, MVT::i32));
1390 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5);
1391 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
1392 SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt);
1393 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
1396 static SDOperand LowerSRA(SDOperand Op, SelectionDAG &DAG,
1397 MVT::ValueType PtrVT) {
1398 assert(Op.getValueType() == MVT::i64 &&
1399 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!");
1400 // The generic code does a fine job expanding shift by a constant.
1401 if (isa<ConstantSDNode>(Op.getOperand(1))) return SDOperand();
1403 // Otherwise, expand into a bunch of logical ops, followed by a select_cc.
1404 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1405 DAG.getConstant(0, PtrVT));
1406 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1407 DAG.getConstant(1, PtrVT));
1408 SDOperand Amt = Op.getOperand(1);
1410 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
1411 DAG.getConstant(32, MVT::i32), Amt);
1412 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
1413 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
1414 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
1415 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
1416 DAG.getConstant(-32U, MVT::i32));
1417 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5);
1418 SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt);
1419 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32),
1420 Tmp4, Tmp6, ISD::SETLE);
1421 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
1424 //===----------------------------------------------------------------------===//
1425 // Vector related lowering.
1428 // If this is a vector of constants or undefs, get the bits. A bit in
1429 // UndefBits is set if the corresponding element of the vector is an
1430 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
1431 // zero. Return true if this is not an array of constants, false if it is.
1433 static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
1434 uint64_t UndefBits[2]) {
1435 // Start with zero'd results.
1436 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0;
1438 unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType());
1439 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
1440 SDOperand OpVal = BV->getOperand(i);
1442 unsigned PartNo = i >= e/2; // In the upper 128 bits?
1443 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t.
1445 uint64_t EltBits = 0;
1446 if (OpVal.getOpcode() == ISD::UNDEF) {
1447 uint64_t EltUndefBits = ~0U >> (32-EltBitSize);
1448 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize);
1450 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1451 EltBits = CN->getValue() & (~0U >> (32-EltBitSize));
1452 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1453 assert(CN->getValueType(0) == MVT::f32 &&
1454 "Only one legal FP vector type!");
1455 EltBits = FloatToBits(CN->getValue());
1457 // Nonconstant element.
1461 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize);
1464 //printf("%llx %llx %llx %llx\n",
1465 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]);
1469 // If this is a splat (repetition) of a value across the whole vector, return
1470 // the smallest size that splats it. For example, "0x01010101010101..." is a
1471 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
1472 // SplatSize = 1 byte.
1473 static bool isConstantSplat(const uint64_t Bits128[2],
1474 const uint64_t Undef128[2],
1475 unsigned &SplatBits, unsigned &SplatUndef,
1476 unsigned &SplatSize) {
1478 // Don't let undefs prevent splats from matching. See if the top 64-bits are
1479 // the same as the lower 64-bits, ignoring undefs.
1480 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0]))
1481 return false; // Can't be a splat if two pieces don't match.
1483 uint64_t Bits64 = Bits128[0] | Bits128[1];
1484 uint64_t Undef64 = Undef128[0] & Undef128[1];
1486 // Check that the top 32-bits are the same as the lower 32-bits, ignoring
1488 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64))
1489 return false; // Can't be a splat if two pieces don't match.
1491 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32);
1492 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32);
1494 // If the top 16-bits are different than the lower 16-bits, ignoring
1495 // undefs, we have an i32 splat.
1496 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) {
1498 SplatUndef = Undef32;
1503 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16);
1504 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16);
1506 // If the top 8-bits are different than the lower 8-bits, ignoring
1507 // undefs, we have an i16 splat.
1508 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) {
1510 SplatUndef = Undef16;
1515 // Otherwise, we have an 8-bit splat.
1516 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8);
1517 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8);
1522 /// BuildSplatI - Build a canonical splati of Val with an element size of
1523 /// SplatSize. Cast the result to VT.
1524 static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT,
1525 SelectionDAG &DAG) {
1526 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
1528 // Force vspltis[hw] -1 to vspltisb -1.
1529 if (Val == -1) SplatSize = 1;
1531 static const MVT::ValueType VTys[] = { // canonical VT to use for each size.
1532 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
1534 MVT::ValueType CanonicalVT = VTys[SplatSize-1];
1536 // Build a canonical splat for this value.
1537 SDOperand Elt = DAG.getConstant(Val, MVT::getVectorBaseType(CanonicalVT));
1538 std::vector<SDOperand> Ops(MVT::getVectorNumElements(CanonicalVT), Elt);
1539 SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT, Ops);
1540 return DAG.getNode(ISD::BIT_CONVERT, VT, Res);
1543 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
1544 /// specified intrinsic ID.
1545 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS,
1547 MVT::ValueType DestVT = MVT::Other) {
1548 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
1549 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
1550 DAG.getConstant(IID, MVT::i32), LHS, RHS);
1553 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
1554 /// specified intrinsic ID.
1555 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1,
1556 SDOperand Op2, SelectionDAG &DAG,
1557 MVT::ValueType DestVT = MVT::Other) {
1558 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
1559 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
1560 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
1564 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
1565 /// amount. The result has the specified value type.
1566 static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt,
1567 MVT::ValueType VT, SelectionDAG &DAG) {
1568 // Force LHS/RHS to be the right type.
1569 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS);
1570 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS);
1572 std::vector<SDOperand> Ops;
1573 for (unsigned i = 0; i != 16; ++i)
1574 Ops.push_back(DAG.getConstant(i+Amt, MVT::i32));
1575 SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS,
1576 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops));
1577 return DAG.getNode(ISD::BIT_CONVERT, VT, T);
1580 // If this is a case we can't handle, return null and let the default
1581 // expansion code take care of it. If we CAN select this case, and if it
1582 // selects to a single instruction, return Op. Otherwise, if we can codegen
1583 // this case more efficiently than a constant pool load, lower it to the
1584 // sequence of ops that should be used.
1585 static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
1586 // If this is a vector of constants or undefs, get the bits. A bit in
1587 // UndefBits is set if the corresponding element of the vector is an
1588 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
1590 uint64_t VectorBits[2];
1591 uint64_t UndefBits[2];
1592 if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits))
1593 return SDOperand(); // Not a constant vector.
1595 // If this is a splat (repetition) of a value across the whole vector, return
1596 // the smallest size that splats it. For example, "0x01010101010101..." is a
1597 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
1598 // SplatSize = 1 byte.
1599 unsigned SplatBits, SplatUndef, SplatSize;
1600 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){
1601 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0;
1603 // First, handle single instruction cases.
1606 if (SplatBits == 0) {
1607 // Canonicalize all zero vectors to be v4i32.
1608 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
1609 SDOperand Z = DAG.getConstant(0, MVT::i32);
1610 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z);
1611 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z);
1616 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
1617 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize);
1618 if (SextVal >= -16 && SextVal <= 15)
1619 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG);
1622 // Two instruction sequences.
1624 // If this value is in the range [-32,30] and is even, use:
1625 // tmp = VSPLTI[bhw], result = add tmp, tmp
1626 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
1627 Op = BuildSplatI(SextVal >> 1, SplatSize, Op.getValueType(), DAG);
1628 return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op);
1631 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
1632 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
1634 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
1635 // Make -1 and vspltisw -1:
1636 SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG);
1638 // Make the VSLW intrinsic, computing 0x8000_0000.
1639 SDOperand Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
1642 // xor by OnesV to invert it.
1643 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV);
1644 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
1647 // Check to see if this is a wide variety of vsplti*, binop self cases.
1648 unsigned SplatBitSize = SplatSize*8;
1649 static const char SplatCsts[] = {
1650 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
1651 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
1653 for (unsigned idx = 0; idx < sizeof(SplatCsts)/sizeof(SplatCsts[0]); ++idx){
1654 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
1655 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
1656 int i = SplatCsts[idx];
1658 // Figure out what shift amount will be used by altivec if shifted by i in
1660 unsigned TypeShiftAmt = i & (SplatBitSize-1);
1662 // vsplti + shl self.
1663 if (SextVal == (i << (int)TypeShiftAmt)) {
1664 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
1665 static const unsigned IIDs[] = { // Intrinsic to use for each size.
1666 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
1667 Intrinsic::ppc_altivec_vslw
1669 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
1672 // vsplti + srl self.
1673 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
1674 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
1675 static const unsigned IIDs[] = { // Intrinsic to use for each size.
1676 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
1677 Intrinsic::ppc_altivec_vsrw
1679 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
1682 // vsplti + sra self.
1683 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
1684 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
1685 static const unsigned IIDs[] = { // Intrinsic to use for each size.
1686 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
1687 Intrinsic::ppc_altivec_vsraw
1689 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
1692 // vsplti + rol self.
1693 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
1694 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
1695 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
1696 static const unsigned IIDs[] = { // Intrinsic to use for each size.
1697 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
1698 Intrinsic::ppc_altivec_vrlw
1700 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
1703 // t = vsplti c, result = vsldoi t, t, 1
1704 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
1705 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
1706 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG);
1708 // t = vsplti c, result = vsldoi t, t, 2
1709 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
1710 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
1711 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG);
1713 // t = vsplti c, result = vsldoi t, t, 3
1714 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
1715 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
1716 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG);
1720 // Three instruction sequences.
1722 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
1723 if (SextVal >= 0 && SextVal <= 31) {
1724 SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, Op.getValueType(),DAG);
1725 SDOperand RHS = BuildSplatI(-16, SplatSize, Op.getValueType(), DAG);
1726 return DAG.getNode(ISD::SUB, Op.getValueType(), LHS, RHS);
1728 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
1729 if (SextVal >= -31 && SextVal <= 0) {
1730 SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, Op.getValueType(),DAG);
1731 SDOperand RHS = BuildSplatI(-16, SplatSize, Op.getValueType(), DAG);
1732 return DAG.getNode(ISD::ADD, Op.getValueType(), LHS, RHS);
1739 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
1740 /// the specified operations to build the shuffle.
1741 static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS,
1742 SDOperand RHS, SelectionDAG &DAG) {
1743 unsigned OpNum = (PFEntry >> 26) & 0x0F;
1744 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
1745 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
1748 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
1760 if (OpNum == OP_COPY) {
1761 if (LHSID == (1*9+2)*9+3) return LHS;
1762 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
1766 SDOperand OpLHS, OpRHS;
1767 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG);
1768 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG);
1770 unsigned ShufIdxs[16];
1772 default: assert(0 && "Unknown i32 permute!");
1774 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
1775 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
1776 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
1777 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
1780 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
1781 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
1782 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
1783 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
1786 for (unsigned i = 0; i != 16; ++i)
1787 ShufIdxs[i] = (i&3)+0;
1790 for (unsigned i = 0; i != 16; ++i)
1791 ShufIdxs[i] = (i&3)+4;
1794 for (unsigned i = 0; i != 16; ++i)
1795 ShufIdxs[i] = (i&3)+8;
1798 for (unsigned i = 0; i != 16; ++i)
1799 ShufIdxs[i] = (i&3)+12;
1802 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG);
1804 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG);
1806 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG);
1808 std::vector<SDOperand> Ops;
1809 for (unsigned i = 0; i != 16; ++i)
1810 Ops.push_back(DAG.getConstant(ShufIdxs[i], MVT::i32));
1812 return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS,
1813 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops));
1816 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
1817 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
1818 /// return the code it can be lowered into. Worst case, it can always be
1819 /// lowered into a vperm.
1820 static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
1821 SDOperand V1 = Op.getOperand(0);
1822 SDOperand V2 = Op.getOperand(1);
1823 SDOperand PermMask = Op.getOperand(2);
1825 // Cases that are handled by instructions that take permute immediates
1826 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
1827 // selected by the instruction selector.
1828 if (V2.getOpcode() == ISD::UNDEF) {
1829 if (PPC::isSplatShuffleMask(PermMask.Val, 1) ||
1830 PPC::isSplatShuffleMask(PermMask.Val, 2) ||
1831 PPC::isSplatShuffleMask(PermMask.Val, 4) ||
1832 PPC::isVPKUWUMShuffleMask(PermMask.Val, true) ||
1833 PPC::isVPKUHUMShuffleMask(PermMask.Val, true) ||
1834 PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 ||
1835 PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) ||
1836 PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) ||
1837 PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) ||
1838 PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) ||
1839 PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) ||
1840 PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) {
1845 // Altivec has a variety of "shuffle immediates" that take two vector inputs
1846 // and produce a fixed permutation. If any of these match, do not lower to
1848 if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) ||
1849 PPC::isVPKUHUMShuffleMask(PermMask.Val, false) ||
1850 PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 ||
1851 PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) ||
1852 PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) ||
1853 PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) ||
1854 PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) ||
1855 PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) ||
1856 PPC::isVMRGHShuffleMask(PermMask.Val, 4, false))
1859 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
1860 // perfect shuffle table to emit an optimal matching sequence.
1861 unsigned PFIndexes[4];
1862 bool isFourElementShuffle = true;
1863 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
1864 unsigned EltNo = 8; // Start out undef.
1865 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
1866 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF)
1867 continue; // Undef, ignore it.
1869 unsigned ByteSource =
1870 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue();
1871 if ((ByteSource & 3) != j) {
1872 isFourElementShuffle = false;
1877 EltNo = ByteSource/4;
1878 } else if (EltNo != ByteSource/4) {
1879 isFourElementShuffle = false;
1883 PFIndexes[i] = EltNo;
1886 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
1887 // perfect shuffle vector to determine if it is cost effective to do this as
1888 // discrete instructions, or whether we should use a vperm.
1889 if (isFourElementShuffle) {
1890 // Compute the index in the perfect shuffle table.
1891 unsigned PFTableIndex =
1892 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
1894 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
1895 unsigned Cost = (PFEntry >> 30);
1897 // Determining when to avoid vperm is tricky. Many things affect the cost
1898 // of vperm, particularly how many times the perm mask needs to be computed.
1899 // For example, if the perm mask can be hoisted out of a loop or is already
1900 // used (perhaps because there are multiple permutes with the same shuffle
1901 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
1902 // the loop requires an extra register.
1904 // As a compromise, we only emit discrete instructions if the shuffle can be
1905 // generated in 3 or fewer operations. When we have loop information
1906 // available, if this block is within a loop, we should avoid using vperm
1907 // for 3-operation perms and use a constant pool load instead.
1909 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG);
1912 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
1913 // vector that will get spilled to the constant pool.
1914 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
1916 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
1917 // that it is in input element units, not in bytes. Convert now.
1918 MVT::ValueType EltVT = MVT::getVectorBaseType(V1.getValueType());
1919 unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8;
1921 std::vector<SDOperand> ResultMask;
1922 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
1924 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
1927 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue();
1929 for (unsigned j = 0; j != BytesPerElement; ++j)
1930 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
1934 SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, ResultMask);
1935 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
1938 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
1939 /// altivec comparison. If it is, return true and fill in Opc/isDot with
1940 /// information about the intrinsic.
1941 static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc,
1943 unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue();
1946 switch (IntrinsicID) {
1947 default: return false;
1948 // Comparison predicates.
1949 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
1950 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
1951 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
1952 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
1953 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
1954 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
1955 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
1956 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
1957 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
1958 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
1959 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
1960 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
1961 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
1963 // Normal Comparisons.
1964 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
1965 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
1966 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
1967 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
1968 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
1969 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
1970 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
1971 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
1972 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
1973 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
1974 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
1975 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
1976 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
1981 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
1982 /// lower, do it, otherwise return null.
1983 static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
1984 // If this is a lowered altivec predicate compare, CompareOpc is set to the
1985 // opcode number of the comparison.
1988 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
1989 return SDOperand(); // Don't custom lower most intrinsics.
1991 // If this is a non-dot comparison, make the VCMP node and we are done.
1993 SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(),
1994 Op.getOperand(1), Op.getOperand(2),
1995 DAG.getConstant(CompareOpc, MVT::i32));
1996 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp);
1999 // Create the PPCISD altivec 'dot' comparison node.
2000 std::vector<SDOperand> Ops;
2001 std::vector<MVT::ValueType> VTs;
2002 Ops.push_back(Op.getOperand(2)); // LHS
2003 Ops.push_back(Op.getOperand(3)); // RHS
2004 Ops.push_back(DAG.getConstant(CompareOpc, MVT::i32));
2005 VTs.push_back(Op.getOperand(2).getValueType());
2006 VTs.push_back(MVT::Flag);
2007 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops);
2009 // Now that we have the comparison, emit a copy from the CR to a GPR.
2010 // This is flagged to the above dot comparison.
2011 SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32,
2012 DAG.getRegister(PPC::CR6, MVT::i32),
2013 CompNode.getValue(1));
2015 // Unpack the result based on how the target uses it.
2016 unsigned BitNo; // Bit # of CR6.
2017 bool InvertBit; // Invert result?
2018 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
2019 default: // Can't happen, don't crash on invalid number though.
2020 case 0: // Return the value of the EQ bit of CR6.
2021 BitNo = 0; InvertBit = false;
2023 case 1: // Return the inverted value of the EQ bit of CR6.
2024 BitNo = 0; InvertBit = true;
2026 case 2: // Return the value of the LT bit of CR6.
2027 BitNo = 2; InvertBit = false;
2029 case 3: // Return the inverted value of the LT bit of CR6.
2030 BitNo = 2; InvertBit = true;
2034 // Shift the bit into the low position.
2035 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags,
2036 DAG.getConstant(8-(3-BitNo), MVT::i32));
2038 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags,
2039 DAG.getConstant(1, MVT::i32));
2041 // If we are supposed to, toggle the bit.
2043 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags,
2044 DAG.getConstant(1, MVT::i32));
2048 static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2049 // Create a stack slot that is 16-byte aligned.
2050 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
2051 int FrameIdx = FrameInfo->CreateStackObject(16, 16);
2052 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, MVT::i32);
2054 // Store the input value into Value#0 of the stack slot.
2055 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
2056 Op.getOperand(0), FIdx,DAG.getSrcValue(NULL));
2058 return DAG.getLoad(Op.getValueType(), Store, FIdx, DAG.getSrcValue(NULL));
2061 static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) {
2062 if (Op.getValueType() == MVT::v4i32) {
2063 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2065 SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG);
2066 SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt.
2068 SDOperand RHSSwap = // = vrlw RHS, 16
2069 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG);
2071 // Shrinkify inputs to v8i16.
2072 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS);
2073 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS);
2074 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap);
2076 // Low parts multiplied together, generating 32-bit results (we ignore the
2078 SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
2079 LHS, RHS, DAG, MVT::v4i32);
2081 SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
2082 LHS, RHSSwap, Zero, DAG, MVT::v4i32);
2083 // Shift the high parts up 16 bits.
2084 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG);
2085 return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd);
2086 } else if (Op.getValueType() == MVT::v8i16) {
2087 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2089 SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG);
2091 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
2092 LHS, RHS, Zero, DAG);
2093 } else if (Op.getValueType() == MVT::v16i8) {
2094 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2096 // Multiply the even 8-bit parts, producing 16-bit sums.
2097 SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
2098 LHS, RHS, DAG, MVT::v8i16);
2099 EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts);
2101 // Multiply the odd 8-bit parts, producing 16-bit sums.
2102 SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
2103 LHS, RHS, DAG, MVT::v8i16);
2104 OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts);
2106 // Merge the results together.
2107 std::vector<SDOperand> Ops;
2108 for (unsigned i = 0; i != 8; ++i) {
2109 Ops.push_back(DAG.getConstant(2*i+1, MVT::i8));
2110 Ops.push_back(DAG.getConstant(2*i+1+16, MVT::i8));
2113 return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts,
2114 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops));
2116 assert(0 && "Unknown mul to lower!");
2121 /// LowerOperation - Provide custom lowering hooks for some operations.
2123 SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
2124 switch (Op.getOpcode()) {
2125 default: assert(0 && "Wasn't expecting to be able to lower this!");
2126 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2127 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
2128 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
2129 case ISD::SETCC: return LowerSETCC(Op, DAG);
2130 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
2131 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG,
2133 case ISD::CALL: return LowerCALL(Op, DAG);
2134 case ISD::RET: return LowerRET(Op, DAG);
2136 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
2137 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
2138 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
2140 // Lower 64-bit shifts.
2141 case ISD::SHL: return LowerSHL(Op, DAG, getPointerTy());
2142 case ISD::SRL: return LowerSRL(Op, DAG, getPointerTy());
2143 case ISD::SRA: return LowerSRA(Op, DAG, getPointerTy());
2145 // Vector-related lowering.
2146 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
2147 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2148 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2149 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
2150 case ISD::MUL: return LowerMUL(Op, DAG);
2155 //===----------------------------------------------------------------------===//
2156 // Other Lowering Code
2157 //===----------------------------------------------------------------------===//
2160 PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
2161 MachineBasicBlock *BB) {
2162 assert((MI->getOpcode() == PPC::SELECT_CC_Int ||
2163 MI->getOpcode() == PPC::SELECT_CC_F4 ||
2164 MI->getOpcode() == PPC::SELECT_CC_F8 ||
2165 MI->getOpcode() == PPC::SELECT_CC_VRRC) &&
2166 "Unexpected instr type to insert");
2168 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
2169 // control-flow pattern. The incoming instruction knows the destination vreg
2170 // to set, the condition code register to branch on, the true/false values to
2171 // select between, and a branch opcode to use.
2172 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2173 ilist<MachineBasicBlock>::iterator It = BB;
2179 // cmpTY ccX, r1, r2
2181 // fallthrough --> copy0MBB
2182 MachineBasicBlock *thisMBB = BB;
2183 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
2184 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
2185 BuildMI(BB, MI->getOperand(4).getImmedValue(), 2)
2186 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
2187 MachineFunction *F = BB->getParent();
2188 F->getBasicBlockList().insert(It, copy0MBB);
2189 F->getBasicBlockList().insert(It, sinkMBB);
2190 // Update machine-CFG edges by first adding all successors of the current
2191 // block to the new block which will contain the Phi node for the select.
2192 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
2193 e = BB->succ_end(); i != e; ++i)
2194 sinkMBB->addSuccessor(*i);
2195 // Next, remove all successors of the current block, and add the true
2196 // and fallthrough blocks as its successors.
2197 while(!BB->succ_empty())
2198 BB->removeSuccessor(BB->succ_begin());
2199 BB->addSuccessor(copy0MBB);
2200 BB->addSuccessor(sinkMBB);
2203 // %FalseValue = ...
2204 // # fallthrough to sinkMBB
2207 // Update machine-CFG edges
2208 BB->addSuccessor(sinkMBB);
2211 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
2214 BuildMI(BB, PPC::PHI, 4, MI->getOperand(0).getReg())
2215 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
2216 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
2218 delete MI; // The pseudo instruction is gone now.
2222 //===----------------------------------------------------------------------===//
2223 // Target Optimization Hooks
2224 //===----------------------------------------------------------------------===//
2226 SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
2227 DAGCombinerInfo &DCI) const {
2228 TargetMachine &TM = getTargetMachine();
2229 SelectionDAG &DAG = DCI.DAG;
2230 switch (N->getOpcode()) {
2232 case ISD::SINT_TO_FP:
2233 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
2234 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
2235 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
2236 // We allow the src/dst to be either f32/f64, but the intermediate
2237 // type must be i64.
2238 if (N->getOperand(0).getValueType() == MVT::i64) {
2239 SDOperand Val = N->getOperand(0).getOperand(0);
2240 if (Val.getValueType() == MVT::f32) {
2241 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
2242 DCI.AddToWorklist(Val.Val);
2245 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val);
2246 DCI.AddToWorklist(Val.Val);
2247 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val);
2248 DCI.AddToWorklist(Val.Val);
2249 if (N->getValueType(0) == MVT::f32) {
2250 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val);
2251 DCI.AddToWorklist(Val.Val);
2254 } else if (N->getOperand(0).getValueType() == MVT::i32) {
2255 // If the intermediate type is i32, we can avoid the load/store here
2262 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
2263 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
2264 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
2265 N->getOperand(1).getValueType() == MVT::i32) {
2266 SDOperand Val = N->getOperand(1).getOperand(0);
2267 if (Val.getValueType() == MVT::f32) {
2268 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
2269 DCI.AddToWorklist(Val.Val);
2271 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val);
2272 DCI.AddToWorklist(Val.Val);
2274 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val,
2275 N->getOperand(2), N->getOperand(3));
2276 DCI.AddToWorklist(Val.Val);
2280 case PPCISD::VCMP: {
2281 // If a VCMPo node already exists with exactly the same operands as this
2282 // node, use its result instead of this node (VCMPo computes both a CR6 and
2283 // a normal output).
2285 if (!N->getOperand(0).hasOneUse() &&
2286 !N->getOperand(1).hasOneUse() &&
2287 !N->getOperand(2).hasOneUse()) {
2289 // Scan all of the users of the LHS, looking for VCMPo's that match.
2290 SDNode *VCMPoNode = 0;
2292 SDNode *LHSN = N->getOperand(0).Val;
2293 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
2295 if ((*UI)->getOpcode() == PPCISD::VCMPo &&
2296 (*UI)->getOperand(1) == N->getOperand(1) &&
2297 (*UI)->getOperand(2) == N->getOperand(2) &&
2298 (*UI)->getOperand(0) == N->getOperand(0)) {
2303 // If there is no VCMPo node, or if the flag value has a single use, don't
2305 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
2308 // Look at the (necessarily single) use of the flag value. If it has a
2309 // chain, this transformation is more complex. Note that multiple things
2310 // could use the value result, which we should ignore.
2311 SDNode *FlagUser = 0;
2312 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
2313 FlagUser == 0; ++UI) {
2314 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
2316 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
2317 if (User->getOperand(i) == SDOperand(VCMPoNode, 1)) {
2324 // If the user is a MFCR instruction, we know this is safe. Otherwise we
2325 // give up for right now.
2326 if (FlagUser->getOpcode() == PPCISD::MFCR)
2327 return SDOperand(VCMPoNode, 0);
2332 // If this is a branch on an altivec predicate comparison, lower this so
2333 // that we don't have to do a MFCR: instead, branch directly on CR6. This
2334 // lowering is done pre-legalize, because the legalizer lowers the predicate
2335 // compare down to code that is difficult to reassemble.
2336 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
2337 SDOperand LHS = N->getOperand(2), RHS = N->getOperand(3);
2341 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
2342 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
2343 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
2344 assert(isDot && "Can't compare against a vector result!");
2346 // If this is a comparison against something other than 0/1, then we know
2347 // that the condition is never/always true.
2348 unsigned Val = cast<ConstantSDNode>(RHS)->getValue();
2349 if (Val != 0 && Val != 1) {
2350 if (CC == ISD::SETEQ) // Cond never true, remove branch.
2351 return N->getOperand(0);
2352 // Always !=, turn it into an unconditional branch.
2353 return DAG.getNode(ISD::BR, MVT::Other,
2354 N->getOperand(0), N->getOperand(4));
2357 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
2359 // Create the PPCISD altivec 'dot' comparison node.
2360 std::vector<SDOperand> Ops;
2361 std::vector<MVT::ValueType> VTs;
2362 Ops.push_back(LHS.getOperand(2)); // LHS of compare
2363 Ops.push_back(LHS.getOperand(3)); // RHS of compare
2364 Ops.push_back(DAG.getConstant(CompareOpc, MVT::i32));
2365 VTs.push_back(LHS.getOperand(2).getValueType());
2366 VTs.push_back(MVT::Flag);
2367 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops);
2369 // Unpack the result based on how the target uses it.
2371 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) {
2372 default: // Can't happen, don't crash on invalid number though.
2373 case 0: // Branch on the value of the EQ bit of CR6.
2374 CompOpc = BranchOnWhenPredTrue ? PPC::BEQ : PPC::BNE;
2376 case 1: // Branch on the inverted value of the EQ bit of CR6.
2377 CompOpc = BranchOnWhenPredTrue ? PPC::BNE : PPC::BEQ;
2379 case 2: // Branch on the value of the LT bit of CR6.
2380 CompOpc = BranchOnWhenPredTrue ? PPC::BLT : PPC::BGE;
2382 case 3: // Branch on the inverted value of the LT bit of CR6.
2383 CompOpc = BranchOnWhenPredTrue ? PPC::BGE : PPC::BLT;
2387 return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0),
2388 DAG.getRegister(PPC::CR6, MVT::i32),
2389 DAG.getConstant(CompOpc, MVT::i32),
2390 N->getOperand(4), CompNode.getValue(1));
2399 //===----------------------------------------------------------------------===//
2400 // Inline Assembly Support
2401 //===----------------------------------------------------------------------===//
2403 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
2405 uint64_t &KnownZero,
2407 unsigned Depth) const {
2410 switch (Op.getOpcode()) {
2412 case ISD::INTRINSIC_WO_CHAIN: {
2413 switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) {
2415 case Intrinsic::ppc_altivec_vcmpbfp_p:
2416 case Intrinsic::ppc_altivec_vcmpeqfp_p:
2417 case Intrinsic::ppc_altivec_vcmpequb_p:
2418 case Intrinsic::ppc_altivec_vcmpequh_p:
2419 case Intrinsic::ppc_altivec_vcmpequw_p:
2420 case Intrinsic::ppc_altivec_vcmpgefp_p:
2421 case Intrinsic::ppc_altivec_vcmpgtfp_p:
2422 case Intrinsic::ppc_altivec_vcmpgtsb_p:
2423 case Intrinsic::ppc_altivec_vcmpgtsh_p:
2424 case Intrinsic::ppc_altivec_vcmpgtsw_p:
2425 case Intrinsic::ppc_altivec_vcmpgtub_p:
2426 case Intrinsic::ppc_altivec_vcmpgtuh_p:
2427 case Intrinsic::ppc_altivec_vcmpgtuw_p:
2428 KnownZero = ~1U; // All bits but the low one are known to be zero.
2436 /// getConstraintType - Given a constraint letter, return the type of
2437 /// constraint it is for this target.
2438 PPCTargetLowering::ConstraintType
2439 PPCTargetLowering::getConstraintType(char ConstraintLetter) const {
2440 switch (ConstraintLetter) {
2447 return C_RegisterClass;
2449 return TargetLowering::getConstraintType(ConstraintLetter);
2453 std::vector<unsigned> PPCTargetLowering::
2454 getRegClassForInlineAsmConstraint(const std::string &Constraint,
2455 MVT::ValueType VT) const {
2456 if (Constraint.size() == 1) {
2457 switch (Constraint[0]) { // GCC RS6000 Constraint Letters
2458 default: break; // Unknown constriant letter
2460 return make_vector<unsigned>(/*no R0*/ PPC::R1 , PPC::R2 , PPC::R3 ,
2461 PPC::R4 , PPC::R5 , PPC::R6 , PPC::R7 ,
2462 PPC::R8 , PPC::R9 , PPC::R10, PPC::R11,
2463 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
2464 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
2465 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
2466 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
2467 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
2470 return make_vector<unsigned>(PPC::R0 , PPC::R1 , PPC::R2 , PPC::R3 ,
2471 PPC::R4 , PPC::R5 , PPC::R6 , PPC::R7 ,
2472 PPC::R8 , PPC::R9 , PPC::R10, PPC::R11,
2473 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
2474 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
2475 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
2476 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
2477 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
2480 return make_vector<unsigned>(PPC::F0 , PPC::F1 , PPC::F2 , PPC::F3 ,
2481 PPC::F4 , PPC::F5 , PPC::F6 , PPC::F7 ,
2482 PPC::F8 , PPC::F9 , PPC::F10, PPC::F11,
2483 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
2484 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
2485 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
2486 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
2487 PPC::F28, PPC::F29, PPC::F30, PPC::F31,
2490 return make_vector<unsigned>(PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 ,
2491 PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
2492 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11,
2493 PPC::V12, PPC::V13, PPC::V14, PPC::V15,
2494 PPC::V16, PPC::V17, PPC::V18, PPC::V19,
2495 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
2496 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
2497 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
2500 return make_vector<unsigned>(PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
2501 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7,
2506 return std::vector<unsigned>();
2509 // isOperandValidForConstraint
2510 bool PPCTargetLowering::
2511 isOperandValidForConstraint(SDOperand Op, char Letter) {
2522 if (!isa<ConstantSDNode>(Op)) return false; // Must be an immediate.
2523 unsigned Value = cast<ConstantSDNode>(Op)->getValue();
2525 default: assert(0 && "Unknown constraint letter!");
2526 case 'I': // "I" is a signed 16-bit constant.
2527 return (short)Value == (int)Value;
2528 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
2529 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
2530 return (short)Value == 0;
2531 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
2532 return (Value >> 16) == 0;
2533 case 'M': // "M" is a constant that is greater than 31.
2535 case 'N': // "N" is a positive constant that is an exact power of two.
2536 return (int)Value > 0 && isPowerOf2_32(Value);
2537 case 'O': // "O" is the constant zero.
2539 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
2540 return (short)-Value == (int)-Value;
2546 // Handle standard constraint letters.
2547 return TargetLowering::isOperandValidForConstraint(Op, Letter);
2550 /// isLegalAddressImmediate - Return true if the integer value can be used
2551 /// as the offset of the target addressing mode.
2552 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V) const {
2553 // PPC allows a sign-extended 16-bit immediate field.
2554 return (V > -(1 << 16) && V < (1 << 16)-1);