1 //===-- PPC32ISelLowering.cpp - PPC32 DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPC32ISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPC32ISelLowering.h"
15 #include "PPC32TargetMachine.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/SelectionDAG.h"
19 #include "llvm/Constants.h"
20 #include "llvm/Function.h"
23 PPC32TargetLowering::PPC32TargetLowering(TargetMachine &TM)
24 : TargetLowering(TM) {
26 // Fold away setcc operations if possible.
27 setSetCCIsExpensive();
29 // Set up the register classes.
30 addRegisterClass(MVT::i32, PPC32::GPRCRegisterClass);
31 addRegisterClass(MVT::f32, PPC32::FPRCRegisterClass);
32 addRegisterClass(MVT::f64, PPC32::FPRCRegisterClass);
34 // PowerPC has no intrinsics for these particular operations
35 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
36 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
37 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
39 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
40 setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
41 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
43 // PowerPC has no SREM/UREM instructions
44 setOperationAction(ISD::SREM, MVT::i32, Expand);
45 setOperationAction(ISD::UREM, MVT::i32, Expand);
47 // We don't support sin/cos/sqrt/fmod
48 setOperationAction(ISD::FSIN , MVT::f64, Expand);
49 setOperationAction(ISD::FCOS , MVT::f64, Expand);
50 setOperationAction(ISD::SREM , MVT::f64, Expand);
51 setOperationAction(ISD::FSIN , MVT::f32, Expand);
52 setOperationAction(ISD::FCOS , MVT::f32, Expand);
53 setOperationAction(ISD::SREM , MVT::f32, Expand);
55 // If we're enabling GP optimizations, use hardware square root
56 if (!TM.getSubtarget<PPCSubtarget>().isGigaProcessor()) {
57 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
58 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
61 // PowerPC does not have CTPOP or CTTZ
62 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
63 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
65 // PowerPC does not have Select
66 setOperationAction(ISD::SELECT, MVT::i32, Expand);
67 setOperationAction(ISD::SELECT, MVT::f32, Expand);
68 setOperationAction(ISD::SELECT, MVT::f64, Expand);
70 // PowerPC wants to turn select_cc of FP into fsel when possible.
71 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
72 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
74 // PowerPC does not have BRCOND* which requires SetCC
75 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
76 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
78 // PowerPC does not have FP_TO_UINT
79 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
81 // PowerPC does not have [U|S]INT_TO_FP
82 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
83 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
85 setSetCCResultContents(ZeroOrOneSetCCResult);
87 computeRegisterProperties();
90 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
91 static bool isFloatingPointZero(SDOperand Op) {
92 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
93 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
94 else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) {
95 // Maybe this has already been legalized into the constant pool?
96 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
97 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->get()))
98 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
103 /// LowerOperation - Provide custom lowering hooks for some operations.
105 SDOperand PPC32TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
106 switch (Op.getOpcode()) {
107 default: assert(0 && "Wasn't expecting to be able to lower this!");
109 // Turn FP only select_cc's into fsel instructions.
110 if (MVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
111 MVT::isFloatingPoint(Op.getOperand(2).getValueType())) {
112 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
113 MVT::ValueType ResVT = Op.getValueType();
114 MVT::ValueType CmpVT = Op.getOperand(0).getValueType();
115 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
116 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3);
118 // If the RHS of the comparison is a 0.0, we don't need to do the
119 // subtraction at all.
120 if (isFloatingPointZero(RHS))
122 default: assert(0 && "Invalid FSEL condition"); abort();
125 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
128 return DAG.getTargetNode(PPC::FSEL, ResVT, LHS, TV, FV);
131 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
134 return DAG.getTargetNode(PPC::FSEL, ResVT,
135 DAG.getNode(ISD::FNEG, ResVT, LHS), TV, FV);
139 default: assert(0 && "Invalid FSEL condition"); abort();
142 return DAG.getTargetNode(PPC::FSEL, ResVT,
143 DAG.getNode(ISD::SUB, CmpVT, LHS, RHS), FV,TV);
146 return DAG.getTargetNode(PPC::FSEL, ResVT,
147 DAG.getNode(ISD::SUB, CmpVT, LHS, RHS), TV,FV);
150 return DAG.getTargetNode(PPC::FSEL, ResVT,
151 DAG.getNode(ISD::SUB, CmpVT, RHS, LHS), FV,TV);
154 return DAG.getTargetNode(PPC::FSEL, ResVT,
155 DAG.getNode(ISD::SUB, CmpVT, RHS, LHS), TV,FV);
163 std::vector<SDOperand>
164 PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
166 // add beautiful description of PPC stack frame format, or at least some docs
168 MachineFunction &MF = DAG.getMachineFunction();
169 MachineFrameInfo *MFI = MF.getFrameInfo();
170 MachineBasicBlock& BB = MF.front();
171 std::vector<SDOperand> ArgValues;
173 // Due to the rather complicated nature of the PowerPC ABI, rather than a
174 // fixed size array of physical args, for the sake of simplicity let the STL
175 // handle tracking them for us.
176 std::vector<unsigned> argVR, argPR, argOp;
177 unsigned ArgOffset = 24;
178 unsigned GPR_remaining = 8;
179 unsigned FPR_remaining = 13;
180 unsigned GPR_idx = 0, FPR_idx = 0;
181 static const unsigned GPR[] = {
182 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
183 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
185 static const unsigned FPR[] = {
186 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
187 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
190 // Add DAG nodes to load the arguments... On entry to a function on PPC,
191 // the arguments start at offset 24, although they are likely to be passed
193 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
194 SDOperand newroot, argt;
196 bool needsLoad = false;
197 bool ArgLive = !I->use_empty();
198 MVT::ValueType ObjectVT = getValueType(I->getType());
201 default: assert(0 && "Unhandled argument type!");
208 if (GPR_remaining > 0) {
209 MF.addLiveIn(GPR[GPR_idx]);
210 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(),
211 GPR[GPR_idx], MVT::i32);
212 if (ObjectVT != MVT::i32)
213 argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, newroot);
218 case MVT::i64: ObjSize = 8;
220 if (GPR_remaining > 0) {
221 SDOperand argHi, argLo;
222 MF.addLiveIn(GPR[GPR_idx]);
223 argHi = DAG.getCopyFromReg(DAG.getRoot(), GPR[GPR_idx], MVT::i32);
224 // If we have two or more remaining argument registers, then both halves
225 // of the i64 can be sourced from there. Otherwise, the lower half will
226 // have to come off the stack. This can happen when an i64 is preceded
227 // by 28 bytes of arguments.
228 if (GPR_remaining > 1) {
229 MF.addLiveIn(GPR[GPR_idx+1]);
230 argLo = DAG.getCopyFromReg(argHi, GPR[GPR_idx+1], MVT::i32);
232 int FI = MFI->CreateFixedObject(4, ArgOffset+4);
233 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
234 argLo = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
235 DAG.getSrcValue(NULL));
237 // Build the outgoing arg thingy
238 argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi);
246 ObjSize = (ObjectVT == MVT::f64) ? 8 : 4;
248 if (FPR_remaining > 0) {
249 MF.addLiveIn(FPR[FPR_idx]);
250 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(),
251 FPR[FPR_idx], ObjectVT);
260 // We need to load the argument to a virtual register if we determined above
261 // that we ran out of physical registers of the appropriate type
263 unsigned SubregOffset = 0;
264 if (ObjectVT == MVT::i8 || ObjectVT == MVT::i1) SubregOffset = 3;
265 if (ObjectVT == MVT::i16) SubregOffset = 2;
266 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
267 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
268 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN,
269 DAG.getConstant(SubregOffset, MVT::i32));
270 argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
271 DAG.getSrcValue(NULL));
274 // Every 4 bytes of argument space consumes one of the GPRs available for
276 if (GPR_remaining > 0) {
277 unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1;
278 GPR_remaining -= delta;
281 ArgOffset += ObjSize;
283 DAG.setRoot(newroot.getValue(1));
285 ArgValues.push_back(argt);
288 // If the function takes variable number of arguments, make a frame index for
289 // the start of the first vararg value... for expansion of llvm.va_start.
291 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
292 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
293 // If this function is vararg, store any remaining integer argument regs
294 // to their spots on the stack so that they may be loaded by deferencing the
295 // result of va_next.
296 std::vector<SDOperand> MemOps;
297 for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) {
298 MF.addLiveIn(GPR[GPR_idx]);
299 SDOperand Val = DAG.getCopyFromReg(DAG.getRoot(), GPR[GPR_idx], MVT::i32);
300 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
301 Val, FIN, DAG.getSrcValue(NULL));
302 MemOps.push_back(Store);
303 // Increment the address by four for the next argument to store
304 SDOperand PtrOff = DAG.getConstant(4, getPointerTy());
305 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, PtrOff);
307 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps));
310 // Finally, inform the code generator which regs we return values in.
311 switch (getValueType(F.getReturnType())) {
312 default: assert(0 && "Unknown type!");
313 case MVT::isVoid: break;
318 MF.addLiveOut(PPC::R3);
321 MF.addLiveOut(PPC::R3);
322 MF.addLiveOut(PPC::R4);
326 MF.addLiveOut(PPC::F1);
333 std::pair<SDOperand, SDOperand>
334 PPC32TargetLowering::LowerCallTo(SDOperand Chain,
335 const Type *RetTy, bool isVarArg,
336 unsigned CallingConv, bool isTailCall,
337 SDOperand Callee, ArgListTy &Args,
339 // args_to_use will accumulate outgoing args for the ISD::CALL case in
340 // SelectExpr to use to put the arguments in the appropriate registers.
341 std::vector<SDOperand> args_to_use;
343 // Count how many bytes are to be pushed on the stack, including the linkage
344 // area, and parameter passing area.
345 unsigned NumBytes = 24;
348 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
349 DAG.getConstant(NumBytes, getPointerTy()));
351 for (unsigned i = 0, e = Args.size(); i != e; ++i)
352 switch (getValueType(Args[i].second)) {
353 default: assert(0 && "Unknown value type!");
367 // Just to be safe, we'll always reserve the full 24 bytes of linkage area
368 // plus 32 bytes of argument space in case any called code gets funky on us.
369 // (Required by ABI to support var arg)
370 if (NumBytes < 56) NumBytes = 56;
372 // Adjust the stack pointer for the new arguments...
373 // These operations are automatically eliminated by the prolog/epilog pass
374 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
375 DAG.getConstant(NumBytes, getPointerTy()));
377 // Set up a copy of the stack pointer for use loading and storing any
378 // arguments that may not fit in the registers available for argument
380 SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
383 // Figure out which arguments are going to go in registers, and which in
384 // memory. Also, if this is a vararg function, floating point operations
385 // must be stored to our stack, and loaded into integer regs as well, if
386 // any integer regs are available for argument passing.
387 unsigned ArgOffset = 24;
388 unsigned GPR_remaining = 8;
389 unsigned FPR_remaining = 13;
391 std::vector<SDOperand> MemOps;
392 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
393 // PtrOff will be used to store the current argument to the stack if a
394 // register cannot be found for it.
395 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
396 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
397 MVT::ValueType ArgVT = getValueType(Args[i].second);
400 default: assert(0 && "Unexpected ValueType for argument!");
404 // Promote the integer to 32 bits. If the input type is signed use a
405 // sign extend, otherwise use a zero extend.
406 if (Args[i].second->isSigned())
407 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
409 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
412 if (GPR_remaining > 0) {
413 args_to_use.push_back(Args[i].first);
416 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
417 Args[i].first, PtrOff,
418 DAG.getSrcValue(NULL)));
423 // If we have one free GPR left, we can place the upper half of the i64
424 // in it, and store the other half to the stack. If we have two or more
425 // free GPRs, then we can pass both halves of the i64 in registers.
426 if (GPR_remaining > 0) {
427 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
428 Args[i].first, DAG.getConstant(1, MVT::i32));
429 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
430 Args[i].first, DAG.getConstant(0, MVT::i32));
431 args_to_use.push_back(Hi);
433 if (GPR_remaining > 0) {
434 args_to_use.push_back(Lo);
437 SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
438 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
439 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
440 Lo, PtrOff, DAG.getSrcValue(NULL)));
443 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
444 Args[i].first, PtrOff,
445 DAG.getSrcValue(NULL)));
451 if (FPR_remaining > 0) {
452 args_to_use.push_back(Args[i].first);
455 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
456 Args[i].first, PtrOff,
457 DAG.getSrcValue(NULL));
458 MemOps.push_back(Store);
459 // Float varargs are always shadowed in available integer registers
460 if (GPR_remaining > 0) {
461 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
462 DAG.getSrcValue(NULL));
463 MemOps.push_back(Load);
464 args_to_use.push_back(Load);
467 if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
468 SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
469 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
470 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
471 DAG.getSrcValue(NULL));
472 MemOps.push_back(Load);
473 args_to_use.push_back(Load);
477 // If we have any FPRs remaining, we may also have GPRs remaining.
478 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
480 if (GPR_remaining > 0) {
481 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
484 if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
485 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
490 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
491 Args[i].first, PtrOff,
492 DAG.getSrcValue(NULL)));
494 ArgOffset += (ArgVT == MVT::f32) ? 4 : 8;
499 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps);
502 std::vector<MVT::ValueType> RetVals;
503 MVT::ValueType RetTyVT = getValueType(RetTy);
504 if (RetTyVT != MVT::isVoid)
505 RetVals.push_back(RetTyVT);
506 RetVals.push_back(MVT::Other);
508 SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
509 Chain, Callee, args_to_use), 0);
510 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
511 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
512 DAG.getConstant(NumBytes, getPointerTy()));
513 return std::make_pair(TheCall, Chain);
516 SDOperand PPC32TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
517 Value *VAListV, SelectionDAG &DAG) {
518 // vastart just stores the address of the VarArgsFrameIndex slot into the
519 // memory location argument.
520 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
521 return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
522 DAG.getSrcValue(VAListV));
525 std::pair<SDOperand,SDOperand>
526 PPC32TargetLowering::LowerVAArg(SDOperand Chain,
527 SDOperand VAListP, Value *VAListV,
528 const Type *ArgTy, SelectionDAG &DAG) {
529 MVT::ValueType ArgVT = getValueType(ArgTy);
532 DAG.getLoad(MVT::i32, Chain, VAListP, DAG.getSrcValue(VAListV));
533 SDOperand Result = DAG.getLoad(ArgVT, Chain, VAList, DAG.getSrcValue(NULL));
535 if (ArgVT == MVT::i32 || ArgVT == MVT::f32)
538 assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
539 "Other types should have been promoted for varargs!");
542 VAList = DAG.getNode(ISD::ADD, VAList.getValueType(), VAList,
543 DAG.getConstant(Amt, VAList.getValueType()));
544 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
545 VAList, VAListP, DAG.getSrcValue(VAListV));
546 return std::make_pair(Result, Chain);
550 std::pair<SDOperand, SDOperand> PPC32TargetLowering::
551 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
553 assert(0 && "LowerFrameReturnAddress unimplemented");