1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCTargetMachine.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/CodeGen/SSARegMap.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
25 PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
26 : TargetLowering(TM) {
28 // Fold away setcc operations if possible.
29 setSetCCIsExpensive();
32 // Use _setjmp/_longjmp instead of setjmp/longjmp.
33 setUseUnderscoreSetJmpLongJmp(true);
35 // Set up the register classes.
36 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
37 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
38 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
40 // PowerPC has no intrinsics for these particular operations
41 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
42 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
43 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
45 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
46 setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
47 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
49 // PowerPC has no SREM/UREM instructions
50 setOperationAction(ISD::SREM, MVT::i32, Expand);
51 setOperationAction(ISD::UREM, MVT::i32, Expand);
53 // We don't support sin/cos/sqrt/fmod
54 setOperationAction(ISD::FSIN , MVT::f64, Expand);
55 setOperationAction(ISD::FCOS , MVT::f64, Expand);
56 setOperationAction(ISD::FREM , MVT::f64, Expand);
57 setOperationAction(ISD::FSIN , MVT::f32, Expand);
58 setOperationAction(ISD::FCOS , MVT::f32, Expand);
59 setOperationAction(ISD::FREM , MVT::f32, Expand);
61 // If we're enabling GP optimizations, use hardware square root
62 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
63 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
64 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
67 // PowerPC does not have CTPOP or CTTZ
68 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
69 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
71 // PowerPC does not have Select
72 setOperationAction(ISD::SELECT, MVT::i32, Expand);
73 setOperationAction(ISD::SELECT, MVT::f32, Expand);
74 setOperationAction(ISD::SELECT, MVT::f64, Expand);
76 // PowerPC wants to turn select_cc of FP into fsel when possible.
77 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
78 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
80 // PowerPC does not have BRCOND* which requires SetCC
81 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
82 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
84 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
85 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
87 // PowerPC does not have [U|S]INT_TO_FP
88 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
89 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
91 // PowerPC does not have truncstore for i1.
92 setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
94 // We want to legalize GlobalAddress into the appropriate instructions to
95 // materialize the address.
96 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
98 if (TM.getSubtarget<PPCSubtarget>().is64Bit()) {
99 // They also have instructions for converting between i64 and fp.
100 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
101 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
102 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
103 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
105 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
106 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
109 if (TM.getSubtarget<PPCSubtarget>().has64BitRegs()) {
110 // 64 bit PowerPC implementations can support i64 types directly
111 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
112 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
113 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
115 // 32 bit PowerPC wants to expand i64 shifts itself.
116 setOperationAction(ISD::SHL, MVT::i64, Custom);
117 setOperationAction(ISD::SRL, MVT::i64, Custom);
118 setOperationAction(ISD::SRA, MVT::i64, Custom);
121 setSetCCResultContents(ZeroOrOneSetCCResult);
123 computeRegisterProperties();
126 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
127 static bool isFloatingPointZero(SDOperand Op) {
128 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
129 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
130 else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) {
131 // Maybe this has already been legalized into the constant pool?
132 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
133 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->get()))
134 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
139 /// LowerOperation - Provide custom lowering hooks for some operations.
141 SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
142 switch (Op.getOpcode()) {
143 default: assert(0 && "Wasn't expecting to be able to lower this!");
144 case ISD::FP_TO_SINT: {
145 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType()));
146 SDOperand Src = Op.getOperand(0);
147 if (Src.getValueType() == MVT::f32)
148 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src);
150 switch (Op.getValueType()) {
151 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
153 Op = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src);
156 Op = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src);
161 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
162 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i32);
163 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
164 Op, FI, DAG.getSrcValue(0));
165 if (Op.getOpcode() == PPCISD::FCTIDZ) {
166 Op = DAG.getLoad(MVT::i64, ST, FI, DAG.getSrcValue(0));
168 FI = DAG.getNode(ISD::ADD, MVT::i32, FI, DAG.getConstant(4, MVT::i32));
169 Op = DAG.getLoad(MVT::i32, ST, FI, DAG.getSrcValue(0));
173 case ISD::SINT_TO_FP: {
174 assert(MVT::i64 == Op.getOperand(0).getValueType() &&
175 "Unhandled SINT_TO_FP type in custom expander!");
177 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
178 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i32);
179 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
180 Op.getOperand(0), FI, DAG.getSrcValue(0));
181 SDOperand LD = DAG.getLoad(MVT::f64, ST, FI, DAG.getSrcValue(0));
182 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, LD);
183 if (MVT::f32 == Op.getValueType())
184 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
187 case ISD::SELECT_CC: {
188 // Turn FP only select_cc's into fsel instructions.
189 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) ||
190 !MVT::isFloatingPoint(Op.getOperand(2).getValueType()))
193 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
195 // Cannot handle SETEQ/SETNE.
196 if (CC == ISD::SETEQ || CC == ISD::SETNE) break;
198 MVT::ValueType ResVT = Op.getValueType();
199 MVT::ValueType CmpVT = Op.getOperand(0).getValueType();
200 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
201 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3);
203 // If the RHS of the comparison is a 0.0, we don't need to do the
204 // subtraction at all.
205 if (isFloatingPointZero(RHS))
207 default: assert(0 && "Invalid FSEL condition"); abort();
210 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
213 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
214 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
215 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
218 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
221 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
222 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
223 return DAG.getNode(PPCISD::FSEL, ResVT,
224 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV);
229 default: assert(0 && "Invalid FSEL condition"); abort();
232 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
233 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
234 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
235 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
238 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
239 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
240 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
241 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
244 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
245 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
246 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
247 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
250 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
251 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
252 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
253 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
258 assert(Op.getValueType() == MVT::i64 &&
259 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
260 // The generic code does a fine job expanding shift by a constant.
261 if (isa<ConstantSDNode>(Op.getOperand(1))) break;
263 // Otherwise, expand into a bunch of logical ops. Note that these ops
264 // depend on the PPC behavior for oversized shift amounts.
265 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
266 DAG.getConstant(0, MVT::i32));
267 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
268 DAG.getConstant(1, MVT::i32));
269 SDOperand Amt = Op.getOperand(1);
271 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
272 DAG.getConstant(32, MVT::i32), Amt);
273 SDOperand Tmp2 = DAG.getNode(ISD::SHL, MVT::i32, Hi, Amt);
274 SDOperand Tmp3 = DAG.getNode(ISD::SRL, MVT::i32, Lo, Tmp1);
275 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
276 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
277 DAG.getConstant(-32U, MVT::i32));
278 SDOperand Tmp6 = DAG.getNode(ISD::SHL, MVT::i32, Lo, Tmp5);
279 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
280 SDOperand OutLo = DAG.getNode(ISD::SHL, MVT::i32, Lo, Amt);
281 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
284 assert(Op.getValueType() == MVT::i64 &&
285 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
286 // The generic code does a fine job expanding shift by a constant.
287 if (isa<ConstantSDNode>(Op.getOperand(1))) break;
289 // Otherwise, expand into a bunch of logical ops. Note that these ops
290 // depend on the PPC behavior for oversized shift amounts.
291 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
292 DAG.getConstant(0, MVT::i32));
293 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
294 DAG.getConstant(1, MVT::i32));
295 SDOperand Amt = Op.getOperand(1);
297 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
298 DAG.getConstant(32, MVT::i32), Amt);
299 SDOperand Tmp2 = DAG.getNode(ISD::SRL, MVT::i32, Lo, Amt);
300 SDOperand Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, Hi, Tmp1);
301 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
302 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
303 DAG.getConstant(-32U, MVT::i32));
304 SDOperand Tmp6 = DAG.getNode(ISD::SRL, MVT::i32, Hi, Tmp5);
305 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
306 SDOperand OutHi = DAG.getNode(ISD::SRL, MVT::i32, Hi, Amt);
307 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
310 assert(Op.getValueType() == MVT::i64 &&
311 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!");
312 // The generic code does a fine job expanding shift by a constant.
313 if (isa<ConstantSDNode>(Op.getOperand(1))) break;
315 // Otherwise, expand into a bunch of logical ops, followed by a select_cc.
316 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
317 DAG.getConstant(0, MVT::i32));
318 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
319 DAG.getConstant(1, MVT::i32));
320 SDOperand Amt = Op.getOperand(1);
322 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
323 DAG.getConstant(32, MVT::i32), Amt);
324 SDOperand Tmp2 = DAG.getNode(ISD::SRL, MVT::i32, Lo, Amt);
325 SDOperand Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, Hi, Tmp1);
326 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
327 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
328 DAG.getConstant(-32U, MVT::i32));
329 SDOperand Tmp6 = DAG.getNode(ISD::SRA, MVT::i32, Hi, Tmp5);
330 SDOperand OutHi = DAG.getNode(ISD::SRA, MVT::i32, Hi, Amt);
331 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32),
332 Tmp4, Tmp6, ISD::SETLE);
333 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
335 case ISD::GlobalAddress: {
336 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
337 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
338 SDOperand Zero = DAG.getConstant(0, MVT::i32);
340 if (PPCGenerateStaticCode) {
341 // Generate non-pic code that has direct accesses to globals. To do this
342 // the address of the global is just (hi(&g)+lo(&g)).
343 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero);
344 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero);
345 return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
348 // Only lower GlobalAddress on Darwin.
349 if (!getTargetMachine().getSubtarget<PPCSubtarget>().isDarwin()) break;
350 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero);
352 // With PIC, the first instruction is actually "GR+hi(&G)".
353 Hi = DAG.getNode(ISD::ADD, MVT::i32,
354 DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi);
357 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero);
358 Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
360 if (!GV->hasWeakLinkage() && !GV->isExternal())
363 // If the global is weak or external, we have to go through the lazy
365 return DAG.getLoad(MVT::i32, DAG.getEntryNode(), Lo, DAG.getSrcValue(0));
371 std::vector<SDOperand>
372 PPCTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
374 // add beautiful description of PPC stack frame format, or at least some docs
376 MachineFunction &MF = DAG.getMachineFunction();
377 MachineFrameInfo *MFI = MF.getFrameInfo();
378 MachineBasicBlock& BB = MF.front();
379 SSARegMap *RegMap = MF.getSSARegMap();
380 std::vector<SDOperand> ArgValues;
382 unsigned ArgOffset = 24;
383 unsigned GPR_remaining = 8;
384 unsigned FPR_remaining = 13;
385 unsigned GPR_idx = 0, FPR_idx = 0;
386 static const unsigned GPR[] = {
387 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
388 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
390 static const unsigned FPR[] = {
391 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
392 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
395 // Add DAG nodes to load the arguments... On entry to a function on PPC,
396 // the arguments start at offset 24, although they are likely to be passed
398 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
399 SDOperand newroot, argt;
401 bool needsLoad = false;
402 bool ArgLive = !I->use_empty();
403 MVT::ValueType ObjectVT = getValueType(I->getType());
406 default: assert(0 && "Unhandled argument type!");
413 if (GPR_remaining > 0) {
414 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
415 MF.addLiveIn(GPR[GPR_idx], VReg);
416 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
417 if (ObjectVT != MVT::i32) {
418 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
420 argt = DAG.getNode(AssertOp, MVT::i32, argt,
421 DAG.getValueType(ObjectVT));
422 argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, argt);
428 case MVT::i64: ObjSize = 8;
430 if (GPR_remaining > 0) {
431 SDOperand argHi, argLo;
432 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
433 MF.addLiveIn(GPR[GPR_idx], VReg);
434 argHi = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
435 // If we have two or more remaining argument registers, then both halves
436 // of the i64 can be sourced from there. Otherwise, the lower half will
437 // have to come off the stack. This can happen when an i64 is preceded
438 // by 28 bytes of arguments.
439 if (GPR_remaining > 1) {
440 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
441 MF.addLiveIn(GPR[GPR_idx+1], VReg);
442 argLo = DAG.getCopyFromReg(argHi, VReg, MVT::i32);
444 int FI = MFI->CreateFixedObject(4, ArgOffset+4);
445 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
446 argLo = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
447 DAG.getSrcValue(NULL));
449 // Build the outgoing arg thingy
450 argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi);
458 ObjSize = (ObjectVT == MVT::f64) ? 8 : 4;
460 if (FPR_remaining > 0) {
462 if (ObjectVT == MVT::f32)
463 VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass);
465 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass);
466 MF.addLiveIn(FPR[FPR_idx], VReg);
467 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, ObjectVT);
476 // We need to load the argument to a virtual register if we determined above
477 // that we ran out of physical registers of the appropriate type
479 unsigned SubregOffset = 0;
480 if (ObjectVT == MVT::i8 || ObjectVT == MVT::i1) SubregOffset = 3;
481 if (ObjectVT == MVT::i16) SubregOffset = 2;
482 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
483 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
484 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN,
485 DAG.getConstant(SubregOffset, MVT::i32));
486 argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
487 DAG.getSrcValue(NULL));
490 // Every 4 bytes of argument space consumes one of the GPRs available for
492 if (GPR_remaining > 0) {
493 unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1;
494 GPR_remaining -= delta;
497 ArgOffset += ObjSize;
499 DAG.setRoot(newroot.getValue(1));
501 ArgValues.push_back(argt);
504 // If the function takes variable number of arguments, make a frame index for
505 // the start of the first vararg value... for expansion of llvm.va_start.
507 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
508 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
509 // If this function is vararg, store any remaining integer argument regs
510 // to their spots on the stack so that they may be loaded by deferencing the
511 // result of va_next.
512 std::vector<SDOperand> MemOps;
513 for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) {
514 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
515 MF.addLiveIn(GPR[GPR_idx], VReg);
516 SDOperand Val = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
517 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
518 Val, FIN, DAG.getSrcValue(NULL));
519 MemOps.push_back(Store);
520 // Increment the address by four for the next argument to store
521 SDOperand PtrOff = DAG.getConstant(4, getPointerTy());
522 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, PtrOff);
524 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps));
527 // Finally, inform the code generator which regs we return values in.
528 switch (getValueType(F.getReturnType())) {
529 default: assert(0 && "Unknown type!");
530 case MVT::isVoid: break;
535 MF.addLiveOut(PPC::R3);
538 MF.addLiveOut(PPC::R3);
539 MF.addLiveOut(PPC::R4);
543 MF.addLiveOut(PPC::F1);
550 std::pair<SDOperand, SDOperand>
551 PPCTargetLowering::LowerCallTo(SDOperand Chain,
552 const Type *RetTy, bool isVarArg,
553 unsigned CallingConv, bool isTailCall,
554 SDOperand Callee, ArgListTy &Args,
556 // args_to_use will accumulate outgoing args for the ISD::CALL case in
557 // SelectExpr to use to put the arguments in the appropriate registers.
558 std::vector<SDOperand> args_to_use;
560 // Count how many bytes are to be pushed on the stack, including the linkage
561 // area, and parameter passing area.
562 unsigned NumBytes = 24;
565 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
566 DAG.getConstant(NumBytes, getPointerTy()));
568 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
569 switch (getValueType(Args[i].second)) {
570 default: assert(0 && "Unknown value type!");
585 // Just to be safe, we'll always reserve the full 24 bytes of linkage area
586 // plus 32 bytes of argument space in case any called code gets funky on us.
587 // (Required by ABI to support var arg)
588 if (NumBytes < 56) NumBytes = 56;
590 // Adjust the stack pointer for the new arguments...
591 // These operations are automatically eliminated by the prolog/epilog pass
592 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
593 DAG.getConstant(NumBytes, getPointerTy()));
595 // Set up a copy of the stack pointer for use loading and storing any
596 // arguments that may not fit in the registers available for argument
598 SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
601 // Figure out which arguments are going to go in registers, and which in
602 // memory. Also, if this is a vararg function, floating point operations
603 // must be stored to our stack, and loaded into integer regs as well, if
604 // any integer regs are available for argument passing.
605 unsigned ArgOffset = 24;
606 unsigned GPR_remaining = 8;
607 unsigned FPR_remaining = 13;
609 std::vector<SDOperand> MemOps;
610 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
611 // PtrOff will be used to store the current argument to the stack if a
612 // register cannot be found for it.
613 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
614 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
615 MVT::ValueType ArgVT = getValueType(Args[i].second);
618 default: assert(0 && "Unexpected ValueType for argument!");
622 // Promote the integer to 32 bits. If the input type is signed use a
623 // sign extend, otherwise use a zero extend.
624 if (Args[i].second->isSigned())
625 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
627 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
630 if (GPR_remaining > 0) {
631 args_to_use.push_back(Args[i].first);
634 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
635 Args[i].first, PtrOff,
636 DAG.getSrcValue(NULL)));
641 // If we have one free GPR left, we can place the upper half of the i64
642 // in it, and store the other half to the stack. If we have two or more
643 // free GPRs, then we can pass both halves of the i64 in registers.
644 if (GPR_remaining > 0) {
645 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
646 Args[i].first, DAG.getConstant(1, MVT::i32));
647 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
648 Args[i].first, DAG.getConstant(0, MVT::i32));
649 args_to_use.push_back(Hi);
651 if (GPR_remaining > 0) {
652 args_to_use.push_back(Lo);
655 SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
656 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
657 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
658 Lo, PtrOff, DAG.getSrcValue(NULL)));
661 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
662 Args[i].first, PtrOff,
663 DAG.getSrcValue(NULL)));
669 if (FPR_remaining > 0) {
670 args_to_use.push_back(Args[i].first);
673 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
674 Args[i].first, PtrOff,
675 DAG.getSrcValue(NULL));
676 MemOps.push_back(Store);
677 // Float varargs are always shadowed in available integer registers
678 if (GPR_remaining > 0) {
679 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
680 DAG.getSrcValue(NULL));
681 MemOps.push_back(Load.getValue(1));
682 args_to_use.push_back(Load);
685 if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
686 SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
687 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
688 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
689 DAG.getSrcValue(NULL));
690 MemOps.push_back(Load.getValue(1));
691 args_to_use.push_back(Load);
695 // If we have any FPRs remaining, we may also have GPRs remaining.
696 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
698 if (GPR_remaining > 0) {
699 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
702 if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
703 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
708 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
709 Args[i].first, PtrOff,
710 DAG.getSrcValue(NULL)));
712 ArgOffset += (ArgVT == MVT::f32) ? 4 : 8;
717 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps);
720 std::vector<MVT::ValueType> RetVals;
721 MVT::ValueType RetTyVT = getValueType(RetTy);
722 MVT::ValueType ActualRetTyVT = RetTyVT;
723 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i16)
724 ActualRetTyVT = MVT::i32; // Promote result to i32.
726 if (RetTyVT != MVT::isVoid)
727 RetVals.push_back(ActualRetTyVT);
728 RetVals.push_back(MVT::Other);
730 // If the callee is a GlobalAddress node (quite common, every direct call is)
731 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
732 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
733 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
735 SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
736 Chain, Callee, args_to_use), 0);
737 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
738 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
739 DAG.getConstant(NumBytes, getPointerTy()));
740 SDOperand RetVal = TheCall;
742 // If the result is a small value, add a note so that we keep track of the
743 // information about whether it is sign or zero extended.
744 if (RetTyVT != ActualRetTyVT) {
745 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext,
746 MVT::i32, RetVal, DAG.getValueType(RetTyVT));
747 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
750 return std::make_pair(RetVal, Chain);
753 SDOperand PPCTargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op,
755 if (Op.getValueType() == MVT::i64) {
756 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
757 DAG.getConstant(1, MVT::i32));
758 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
759 DAG.getConstant(0, MVT::i32));
760 return DAG.getNode(ISD::RET, MVT::Other, Chain, Lo, Hi);
762 return DAG.getNode(ISD::RET, MVT::Other, Chain, Op);
766 SDOperand PPCTargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
767 Value *VAListV, SelectionDAG &DAG) {
768 // vastart just stores the address of the VarArgsFrameIndex slot into the
769 // memory location argument.
770 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
771 return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
772 DAG.getSrcValue(VAListV));
775 std::pair<SDOperand,SDOperand>
776 PPCTargetLowering::LowerVAArg(SDOperand Chain,
777 SDOperand VAListP, Value *VAListV,
778 const Type *ArgTy, SelectionDAG &DAG) {
779 MVT::ValueType ArgVT = getValueType(ArgTy);
782 DAG.getLoad(MVT::i32, Chain, VAListP, DAG.getSrcValue(VAListV));
783 SDOperand Result = DAG.getLoad(ArgVT, Chain, VAList, DAG.getSrcValue(NULL));
785 if (ArgVT == MVT::i32 || ArgVT == MVT::f32)
788 assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
789 "Other types should have been promoted for varargs!");
792 VAList = DAG.getNode(ISD::ADD, VAList.getValueType(), VAList,
793 DAG.getConstant(Amt, VAList.getValueType()));
794 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
795 VAList, VAListP, DAG.getSrcValue(VAListV));
796 return std::make_pair(Result, Chain);
800 std::pair<SDOperand, SDOperand> PPCTargetLowering::
801 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
803 assert(0 && "LowerFrameReturnAddress unimplemented");
808 PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
809 MachineBasicBlock *BB) {
810 assert((MI->getOpcode() == PPC::SELECT_CC_Int ||
811 MI->getOpcode() == PPC::SELECT_CC_F4 ||
812 MI->getOpcode() == PPC::SELECT_CC_F8) &&
813 "Unexpected instr type to insert");
815 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
816 // control-flow pattern. The incoming instruction knows the destination vreg
817 // to set, the condition code register to branch on, the true/false values to
818 // select between, and a branch opcode to use.
819 const BasicBlock *LLVM_BB = BB->getBasicBlock();
820 ilist<MachineBasicBlock>::iterator It = BB;
828 // fallthrough --> copy0MBB
829 MachineBasicBlock *thisMBB = BB;
830 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
831 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
832 BuildMI(BB, MI->getOperand(4).getImmedValue(), 2)
833 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
834 MachineFunction *F = BB->getParent();
835 F->getBasicBlockList().insert(It, copy0MBB);
836 F->getBasicBlockList().insert(It, sinkMBB);
837 // Update machine-CFG edges
838 BB->addSuccessor(copy0MBB);
839 BB->addSuccessor(sinkMBB);
843 // # fallthrough to sinkMBB
846 // Update machine-CFG edges
847 BB->addSuccessor(sinkMBB);
850 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
853 BuildMI(BB, PPC::PHI, 4, MI->getOperand(0).getReg())
854 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
855 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
857 delete MI; // The pseudo instruction is gone now.