1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPerfectShuffle.h"
18 #include "PPCTargetMachine.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
27 #include "llvm/IR/CallingConv.h"
28 #include "llvm/IR/Constants.h"
29 #include "llvm/IR/DerivedTypes.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/IR/Intrinsics.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetOptions.h"
39 static bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
40 CCValAssign::LocInfo &LocInfo,
41 ISD::ArgFlagsTy &ArgFlags,
43 static bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
45 CCValAssign::LocInfo &LocInfo,
46 ISD::ArgFlagsTy &ArgFlags,
48 static bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
50 CCValAssign::LocInfo &LocInfo,
51 ISD::ArgFlagsTy &ArgFlags,
54 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
55 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
57 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
58 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
60 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
61 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
63 static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) {
64 if (TM.getSubtargetImpl()->isDarwin())
65 return new TargetLoweringObjectFileMachO();
67 return new TargetLoweringObjectFileELF();
70 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
71 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) {
72 const PPCSubtarget *Subtarget = &TM.getSubtarget<PPCSubtarget>();
73 PPCRegInfo = TM.getRegisterInfo();
77 // Use _setjmp/_longjmp instead of setjmp/longjmp.
78 setUseUnderscoreSetJmp(true);
79 setUseUnderscoreLongJmp(true);
81 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
82 // arguments are at least 4/8 bytes aligned.
83 bool isPPC64 = Subtarget->isPPC64();
84 setMinStackArgumentAlignment(isPPC64 ? 8:4);
86 // Set up the register classes.
87 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
88 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
89 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
91 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
92 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
93 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
95 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
97 // PowerPC has pre-inc load and store's.
98 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
99 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
100 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
101 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
102 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
103 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
104 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
105 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
106 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
107 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
109 // This is used in the ppcf128->int sequence. Note it has different semantics
110 // from FP_ROUND: that rounds to nearest, this rounds to zero.
111 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
113 // We do not currently implement these libm ops for PowerPC.
114 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
115 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
116 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
117 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
118 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
120 // PowerPC has no SREM/UREM instructions
121 setOperationAction(ISD::SREM, MVT::i32, Expand);
122 setOperationAction(ISD::UREM, MVT::i32, Expand);
123 setOperationAction(ISD::SREM, MVT::i64, Expand);
124 setOperationAction(ISD::UREM, MVT::i64, Expand);
126 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
127 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
128 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
129 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
130 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
131 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
132 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
133 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
134 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
136 // We don't support sin/cos/sqrt/fmod/pow
137 setOperationAction(ISD::FSIN , MVT::f64, Expand);
138 setOperationAction(ISD::FCOS , MVT::f64, Expand);
139 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
140 setOperationAction(ISD::FREM , MVT::f64, Expand);
141 setOperationAction(ISD::FPOW , MVT::f64, Expand);
142 setOperationAction(ISD::FMA , MVT::f64, Legal);
143 setOperationAction(ISD::FSIN , MVT::f32, Expand);
144 setOperationAction(ISD::FCOS , MVT::f32, Expand);
145 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
146 setOperationAction(ISD::FREM , MVT::f32, Expand);
147 setOperationAction(ISD::FPOW , MVT::f32, Expand);
148 setOperationAction(ISD::FMA , MVT::f32, Legal);
150 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
152 // If we're enabling GP optimizations, use hardware square root
153 if (!Subtarget->hasFSQRT()) {
154 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
155 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
158 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
159 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
161 if (Subtarget->hasFPRND()) {
162 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
163 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
164 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
166 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
167 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
168 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
170 // frin does not implement "ties to even." Thus, this is safe only in
172 if (TM.Options.UnsafeFPMath) {
173 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
174 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
176 // These need to set FE_INEXACT, and use a custom inserter.
177 setOperationAction(ISD::FRINT, MVT::f64, Legal);
178 setOperationAction(ISD::FRINT, MVT::f32, Legal);
182 // PowerPC does not have BSWAP, CTPOP or CTTZ
183 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
184 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
185 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
186 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
187 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
188 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
189 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
190 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
192 if (Subtarget->hasPOPCNTD()) {
193 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
194 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
196 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
197 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
200 // PowerPC does not have ROTR
201 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
202 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
204 // PowerPC does not have Select
205 setOperationAction(ISD::SELECT, MVT::i32, Expand);
206 setOperationAction(ISD::SELECT, MVT::i64, Expand);
207 setOperationAction(ISD::SELECT, MVT::f32, Expand);
208 setOperationAction(ISD::SELECT, MVT::f64, Expand);
210 // PowerPC wants to turn select_cc of FP into fsel when possible.
211 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
212 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
214 // PowerPC wants to optimize integer setcc a bit
215 setOperationAction(ISD::SETCC, MVT::i32, Custom);
217 // PowerPC does not have BRCOND which requires SetCC
218 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
220 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
222 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
223 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
225 // PowerPC does not have [U|S]INT_TO_FP
226 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
227 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
229 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
230 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
231 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
232 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
234 // We cannot sextinreg(i1). Expand to shifts.
235 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
237 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
238 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
239 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
240 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
242 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
243 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
244 // support continuation, user-level threading, and etc.. As a result, no
245 // other SjLj exception interfaces are implemented and please don't build
246 // your own exception handling based on them.
247 // LLVM/Clang supports zero-cost DWARF exception handling.
248 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
249 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
251 // We want to legalize GlobalAddress and ConstantPool nodes into the
252 // appropriate instructions to materialize the address.
253 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
254 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
255 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
256 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
257 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
258 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
259 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
260 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
261 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
262 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
265 setOperationAction(ISD::TRAP, MVT::Other, Legal);
267 // TRAMPOLINE is custom lowered.
268 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
269 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
271 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
272 setOperationAction(ISD::VASTART , MVT::Other, Custom);
274 if (Subtarget->isSVR4ABI()) {
276 // VAARG always uses double-word chunks, so promote anything smaller.
277 setOperationAction(ISD::VAARG, MVT::i1, Promote);
278 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
279 setOperationAction(ISD::VAARG, MVT::i8, Promote);
280 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
281 setOperationAction(ISD::VAARG, MVT::i16, Promote);
282 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
283 setOperationAction(ISD::VAARG, MVT::i32, Promote);
284 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
285 setOperationAction(ISD::VAARG, MVT::Other, Expand);
287 // VAARG is custom lowered with the 32-bit SVR4 ABI.
288 setOperationAction(ISD::VAARG, MVT::Other, Custom);
289 setOperationAction(ISD::VAARG, MVT::i64, Custom);
292 setOperationAction(ISD::VAARG, MVT::Other, Expand);
294 // Use the default implementation.
295 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
296 setOperationAction(ISD::VAEND , MVT::Other, Expand);
297 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
298 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
299 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
300 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
302 // We want to custom lower some of our intrinsics.
303 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
305 // Comparisons that require checking two conditions.
306 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
307 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
308 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
309 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
310 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
311 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
312 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
313 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
314 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
315 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
316 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
317 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
319 if (Subtarget->has64BitSupport()) {
320 // They also have instructions for converting between i64 and fp.
321 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
322 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
323 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
324 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
325 // This is just the low 32 bits of a (signed) fp->i64 conversion.
326 // We cannot do this with Promote because i64 is not a legal type.
327 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
329 if (Subtarget->isPPC64())
330 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
332 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
333 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
336 if (Subtarget->use64BitRegs()) {
337 // 64-bit PowerPC implementations can support i64 types directly
338 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
339 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
340 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
341 // 64-bit PowerPC wants to expand i128 shifts itself.
342 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
343 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
344 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
346 // 32-bit PowerPC wants to expand i64 shifts itself.
347 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
348 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
349 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
352 if (Subtarget->hasAltivec()) {
353 // First set operation action for all vector types to expand. Then we
354 // will selectively turn on ones that can be effectively codegen'd.
355 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
356 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
357 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
359 // add/sub are legal for all supported vector VT's.
360 setOperationAction(ISD::ADD , VT, Legal);
361 setOperationAction(ISD::SUB , VT, Legal);
363 // We promote all shuffles to v16i8.
364 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
365 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
367 // We promote all non-typed operations to v4i32.
368 setOperationAction(ISD::AND , VT, Promote);
369 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
370 setOperationAction(ISD::OR , VT, Promote);
371 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
372 setOperationAction(ISD::XOR , VT, Promote);
373 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
374 setOperationAction(ISD::LOAD , VT, Promote);
375 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
376 setOperationAction(ISD::SELECT, VT, Promote);
377 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
378 setOperationAction(ISD::STORE, VT, Promote);
379 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
381 // No other operations are legal.
382 setOperationAction(ISD::MUL , VT, Expand);
383 setOperationAction(ISD::SDIV, VT, Expand);
384 setOperationAction(ISD::SREM, VT, Expand);
385 setOperationAction(ISD::UDIV, VT, Expand);
386 setOperationAction(ISD::UREM, VT, Expand);
387 setOperationAction(ISD::FDIV, VT, Expand);
388 setOperationAction(ISD::FNEG, VT, Expand);
389 setOperationAction(ISD::FSQRT, VT, Expand);
390 setOperationAction(ISD::FLOG, VT, Expand);
391 setOperationAction(ISD::FLOG10, VT, Expand);
392 setOperationAction(ISD::FLOG2, VT, Expand);
393 setOperationAction(ISD::FEXP, VT, Expand);
394 setOperationAction(ISD::FEXP2, VT, Expand);
395 setOperationAction(ISD::FSIN, VT, Expand);
396 setOperationAction(ISD::FCOS, VT, Expand);
397 setOperationAction(ISD::FABS, VT, Expand);
398 setOperationAction(ISD::FPOWI, VT, Expand);
399 setOperationAction(ISD::FFLOOR, VT, Expand);
400 setOperationAction(ISD::FCEIL, VT, Expand);
401 setOperationAction(ISD::FTRUNC, VT, Expand);
402 setOperationAction(ISD::FRINT, VT, Expand);
403 setOperationAction(ISD::FNEARBYINT, VT, Expand);
404 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
405 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
406 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
407 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
408 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
409 setOperationAction(ISD::UDIVREM, VT, Expand);
410 setOperationAction(ISD::SDIVREM, VT, Expand);
411 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
412 setOperationAction(ISD::FPOW, VT, Expand);
413 setOperationAction(ISD::CTPOP, VT, Expand);
414 setOperationAction(ISD::CTLZ, VT, Expand);
415 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
416 setOperationAction(ISD::CTTZ, VT, Expand);
417 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
418 setOperationAction(ISD::VSELECT, VT, Expand);
419 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
421 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
422 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
423 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
424 setTruncStoreAction(VT, InnerVT, Expand);
426 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
427 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
428 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
431 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
432 // with merges, splats, etc.
433 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
435 setOperationAction(ISD::AND , MVT::v4i32, Legal);
436 setOperationAction(ISD::OR , MVT::v4i32, Legal);
437 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
438 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
439 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
440 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
441 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
442 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
443 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
444 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
445 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
446 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
447 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
448 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
450 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
451 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
452 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
453 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
455 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
456 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
457 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
458 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
459 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
461 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
462 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
464 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
465 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
466 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
467 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
469 // Altivec does not contain unordered floating-point compare instructions
470 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
471 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
472 setCondCodeAction(ISD::SETUGT, MVT::v4f32, Expand);
473 setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand);
474 setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand);
475 setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand);
478 if (Subtarget->has64BitSupport()) {
479 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
480 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
483 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
484 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
485 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
486 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
488 setBooleanContents(ZeroOrOneBooleanContent);
489 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
492 setStackPointerRegisterToSaveRestore(PPC::X1);
493 setExceptionPointerRegister(PPC::X3);
494 setExceptionSelectorRegister(PPC::X4);
496 setStackPointerRegisterToSaveRestore(PPC::R1);
497 setExceptionPointerRegister(PPC::R3);
498 setExceptionSelectorRegister(PPC::R4);
501 // We have target-specific dag combine patterns for the following nodes:
502 setTargetDAGCombine(ISD::SINT_TO_FP);
503 setTargetDAGCombine(ISD::STORE);
504 setTargetDAGCombine(ISD::BR_CC);
505 setTargetDAGCombine(ISD::BSWAP);
507 // Darwin long double math library functions have $LDBL128 appended.
508 if (Subtarget->isDarwin()) {
509 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
510 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
511 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
512 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
513 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
514 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
515 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
516 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
517 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
518 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
521 setMinFunctionAlignment(2);
522 if (PPCSubTarget.isDarwin())
523 setPrefFunctionAlignment(4);
525 if (isPPC64 && Subtarget->isJITCodeModel())
526 // Temporary workaround for the inability of PPC64 JIT to handle jump
528 setSupportJumpTables(false);
530 setInsertFencesForAtomic(true);
532 setSchedulingPreference(Sched::Hybrid);
534 computeRegisterProperties();
536 // The Freescale cores does better with aggressive inlining of memcpy and
537 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores).
538 if (Subtarget->getDarwinDirective() == PPC::DIR_E500mc ||
539 Subtarget->getDarwinDirective() == PPC::DIR_E5500) {
540 MaxStoresPerMemset = 32;
541 MaxStoresPerMemsetOptSize = 16;
542 MaxStoresPerMemcpy = 32;
543 MaxStoresPerMemcpyOptSize = 8;
544 MaxStoresPerMemmove = 32;
545 MaxStoresPerMemmoveOptSize = 8;
547 setPrefFunctionAlignment(4);
551 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
552 /// function arguments in the caller parameter area.
553 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
554 const TargetMachine &TM = getTargetMachine();
555 // Darwin passes everything on 4 byte boundary.
556 if (TM.getSubtarget<PPCSubtarget>().isDarwin())
559 // 16byte and wider vectors are passed on 16byte boundary.
560 if (VectorType *VTy = dyn_cast<VectorType>(Ty))
561 if (VTy->getBitWidth() >= 128)
564 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
565 if (PPCSubTarget.isPPC64())
571 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
574 case PPCISD::FSEL: return "PPCISD::FSEL";
575 case PPCISD::FCFID: return "PPCISD::FCFID";
576 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
577 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
578 case PPCISD::STFIWX: return "PPCISD::STFIWX";
579 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
580 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
581 case PPCISD::VPERM: return "PPCISD::VPERM";
582 case PPCISD::Hi: return "PPCISD::Hi";
583 case PPCISD::Lo: return "PPCISD::Lo";
584 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
585 case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE";
586 case PPCISD::LOAD: return "PPCISD::LOAD";
587 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
588 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
589 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
590 case PPCISD::SRL: return "PPCISD::SRL";
591 case PPCISD::SRA: return "PPCISD::SRA";
592 case PPCISD::SHL: return "PPCISD::SHL";
593 case PPCISD::CALL: return "PPCISD::CALL";
594 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
595 case PPCISD::MTCTR: return "PPCISD::MTCTR";
596 case PPCISD::BCTRL: return "PPCISD::BCTRL";
597 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
598 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
599 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
600 case PPCISD::MFCR: return "PPCISD::MFCR";
601 case PPCISD::VCMP: return "PPCISD::VCMP";
602 case PPCISD::VCMPo: return "PPCISD::VCMPo";
603 case PPCISD::LBRX: return "PPCISD::LBRX";
604 case PPCISD::STBRX: return "PPCISD::STBRX";
605 case PPCISD::LARX: return "PPCISD::LARX";
606 case PPCISD::STCX: return "PPCISD::STCX";
607 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
608 case PPCISD::MFFS: return "PPCISD::MFFS";
609 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
610 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
611 case PPCISD::CR6SET: return "PPCISD::CR6SET";
612 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
613 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
614 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
615 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
616 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
617 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
618 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
619 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
620 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
621 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
622 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
623 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
624 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
625 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
626 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
627 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
631 EVT PPCTargetLowering::getSetCCResultType(EVT VT) const {
634 return VT.changeVectorElementTypeToInteger();
637 //===----------------------------------------------------------------------===//
638 // Node matching predicates, for use by the tblgen matching code.
639 //===----------------------------------------------------------------------===//
641 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
642 static bool isFloatingPointZero(SDValue Op) {
643 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
644 return CFP->getValueAPF().isZero();
645 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
646 // Maybe this has already been legalized into the constant pool?
647 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
648 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
649 return CFP->getValueAPF().isZero();
654 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
655 /// true if Op is undef or if it matches the specified value.
656 static bool isConstantOrUndef(int Op, int Val) {
657 return Op < 0 || Op == Val;
660 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
661 /// VPKUHUM instruction.
662 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
664 for (unsigned i = 0; i != 16; ++i)
665 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
668 for (unsigned i = 0; i != 8; ++i)
669 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) ||
670 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1))
676 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
677 /// VPKUWUM instruction.
678 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
680 for (unsigned i = 0; i != 16; i += 2)
681 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
682 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
685 for (unsigned i = 0; i != 8; i += 2)
686 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
687 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) ||
688 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) ||
689 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3))
695 /// isVMerge - Common function, used to match vmrg* shuffles.
697 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
698 unsigned LHSStart, unsigned RHSStart) {
699 assert(N->getValueType(0) == MVT::v16i8 &&
700 "PPC only supports shuffles by bytes!");
701 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
702 "Unsupported merge size!");
704 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
705 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
706 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
707 LHSStart+j+i*UnitSize) ||
708 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
709 RHSStart+j+i*UnitSize))
715 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
716 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
717 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
720 return isVMerge(N, UnitSize, 8, 24);
721 return isVMerge(N, UnitSize, 8, 8);
724 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
725 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
726 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
729 return isVMerge(N, UnitSize, 0, 16);
730 return isVMerge(N, UnitSize, 0, 0);
734 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
735 /// amount, otherwise return -1.
736 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
737 assert(N->getValueType(0) == MVT::v16i8 &&
738 "PPC only supports shuffles by bytes!");
740 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
742 // Find the first non-undef value in the shuffle mask.
744 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
747 if (i == 16) return -1; // all undef.
749 // Otherwise, check to see if the rest of the elements are consecutively
750 // numbered from this value.
751 unsigned ShiftAmt = SVOp->getMaskElt(i);
752 if (ShiftAmt < i) return -1;
756 // Check the rest of the elements to see if they are consecutive.
757 for (++i; i != 16; ++i)
758 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
761 // Check the rest of the elements to see if they are consecutive.
762 for (++i; i != 16; ++i)
763 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
769 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
770 /// specifies a splat of a single element that is suitable for input to
771 /// VSPLTB/VSPLTH/VSPLTW.
772 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
773 assert(N->getValueType(0) == MVT::v16i8 &&
774 (EltSize == 1 || EltSize == 2 || EltSize == 4));
776 // This is a splat operation if each element of the permute is the same, and
777 // if the value doesn't reference the second vector.
778 unsigned ElementBase = N->getMaskElt(0);
780 // FIXME: Handle UNDEF elements too!
781 if (ElementBase >= 16)
784 // Check that the indices are consecutive, in the case of a multi-byte element
785 // splatted with a v16i8 mask.
786 for (unsigned i = 1; i != EltSize; ++i)
787 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
790 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
791 if (N->getMaskElt(i) < 0) continue;
792 for (unsigned j = 0; j != EltSize; ++j)
793 if (N->getMaskElt(i+j) != N->getMaskElt(j))
799 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
801 bool PPC::isAllNegativeZeroVector(SDNode *N) {
802 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
804 APInt APVal, APUndef;
808 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
809 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
810 return CFP->getValueAPF().isNegZero();
815 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
816 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
817 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
818 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
819 assert(isSplatShuffleMask(SVOp, EltSize));
820 return SVOp->getMaskElt(0) / EltSize;
823 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
824 /// by using a vspltis[bhw] instruction of the specified element size, return
825 /// the constant being splatted. The ByteSize field indicates the number of
826 /// bytes of each element [124] -> [bhw].
827 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
830 // If ByteSize of the splat is bigger than the element size of the
831 // build_vector, then we have a case where we are checking for a splat where
832 // multiple elements of the buildvector are folded together into a single
833 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
834 unsigned EltSize = 16/N->getNumOperands();
835 if (EltSize < ByteSize) {
836 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
837 SDValue UniquedVals[4];
838 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
840 // See if all of the elements in the buildvector agree across.
841 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
842 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
843 // If the element isn't a constant, bail fully out.
844 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
847 if (UniquedVals[i&(Multiple-1)].getNode() == 0)
848 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
849 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
850 return SDValue(); // no match.
853 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
854 // either constant or undef values that are identical for each chunk. See
855 // if these chunks can form into a larger vspltis*.
857 // Check to see if all of the leading entries are either 0 or -1. If
858 // neither, then this won't fit into the immediate field.
859 bool LeadingZero = true;
860 bool LeadingOnes = true;
861 for (unsigned i = 0; i != Multiple-1; ++i) {
862 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs.
864 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
865 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
867 // Finally, check the least significant entry.
869 if (UniquedVals[Multiple-1].getNode() == 0)
870 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
871 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
873 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
876 if (UniquedVals[Multiple-1].getNode() == 0)
877 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
878 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
879 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
880 return DAG.getTargetConstant(Val, MVT::i32);
886 // Check to see if this buildvec has a single non-undef value in its elements.
887 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
888 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
889 if (OpVal.getNode() == 0)
890 OpVal = N->getOperand(i);
891 else if (OpVal != N->getOperand(i))
895 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def.
897 unsigned ValSizeInBytes = EltSize;
899 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
900 Value = CN->getZExtValue();
901 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
902 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
903 Value = FloatToBits(CN->getValueAPF().convertToFloat());
906 // If the splat value is larger than the element value, then we can never do
907 // this splat. The only case that we could fit the replicated bits into our
908 // immediate field for would be zero, and we prefer to use vxor for it.
909 if (ValSizeInBytes < ByteSize) return SDValue();
911 // If the element value is larger than the splat value, cut it in half and
912 // check to see if the two halves are equal. Continue doing this until we
913 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
914 while (ValSizeInBytes > ByteSize) {
915 ValSizeInBytes >>= 1;
917 // If the top half equals the bottom half, we're still ok.
918 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
919 (Value & ((1 << (8*ValSizeInBytes))-1)))
923 // Properly sign extend the value.
924 int MaskVal = SignExtend32(Value, ByteSize * 8);
926 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
927 if (MaskVal == 0) return SDValue();
929 // Finally, if this value fits in a 5 bit sext field, return it
930 if (SignExtend32<5>(MaskVal) == MaskVal)
931 return DAG.getTargetConstant(MaskVal, MVT::i32);
935 //===----------------------------------------------------------------------===//
936 // Addressing Mode Selection
937 //===----------------------------------------------------------------------===//
939 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
940 /// or 64-bit immediate, and if the value can be accurately represented as a
941 /// sign extension from a 16-bit value. If so, this returns true and the
943 static bool isIntS16Immediate(SDNode *N, short &Imm) {
944 if (N->getOpcode() != ISD::Constant)
947 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
948 if (N->getValueType(0) == MVT::i32)
949 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
951 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
953 static bool isIntS16Immediate(SDValue Op, short &Imm) {
954 return isIntS16Immediate(Op.getNode(), Imm);
958 /// SelectAddressRegReg - Given the specified addressed, check to see if it
959 /// can be represented as an indexed [r+r] operation. Returns false if it
960 /// can be more efficiently represented with [r+imm].
961 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
963 SelectionDAG &DAG) const {
965 if (N.getOpcode() == ISD::ADD) {
966 if (isIntS16Immediate(N.getOperand(1), imm))
968 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
971 Base = N.getOperand(0);
972 Index = N.getOperand(1);
974 } else if (N.getOpcode() == ISD::OR) {
975 if (isIntS16Immediate(N.getOperand(1), imm))
976 return false; // r+i can fold it if we can.
978 // If this is an or of disjoint bitfields, we can codegen this as an add
979 // (for better address arithmetic) if the LHS and RHS of the OR are provably
981 APInt LHSKnownZero, LHSKnownOne;
982 APInt RHSKnownZero, RHSKnownOne;
983 DAG.ComputeMaskedBits(N.getOperand(0),
984 LHSKnownZero, LHSKnownOne);
986 if (LHSKnownZero.getBoolValue()) {
987 DAG.ComputeMaskedBits(N.getOperand(1),
988 RHSKnownZero, RHSKnownOne);
989 // If all of the bits are known zero on the LHS or RHS, the add won't
991 if (~(LHSKnownZero | RHSKnownZero) == 0) {
992 Base = N.getOperand(0);
993 Index = N.getOperand(1);
1002 /// Returns true if the address N can be represented by a base register plus
1003 /// a signed 16-bit displacement [r+imm], and if it is not better
1004 /// represented as reg+reg.
1005 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1007 SelectionDAG &DAG) const {
1008 // FIXME dl should come from parent load or store, not from address
1009 DebugLoc dl = N.getDebugLoc();
1010 // If this can be more profitably realized as r+r, fail.
1011 if (SelectAddressRegReg(N, Disp, Base, DAG))
1014 if (N.getOpcode() == ISD::ADD) {
1016 if (isIntS16Immediate(N.getOperand(1), imm)) {
1017 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
1018 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1019 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1021 Base = N.getOperand(0);
1023 return true; // [r+i]
1024 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1025 // Match LOAD (ADD (X, Lo(G))).
1026 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1027 && "Cannot handle constant offsets yet!");
1028 Disp = N.getOperand(1).getOperand(0); // The global address.
1029 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1030 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1031 Disp.getOpcode() == ISD::TargetConstantPool ||
1032 Disp.getOpcode() == ISD::TargetJumpTable);
1033 Base = N.getOperand(0);
1034 return true; // [&g+r]
1036 } else if (N.getOpcode() == ISD::OR) {
1038 if (isIntS16Immediate(N.getOperand(1), imm)) {
1039 // If this is an or of disjoint bitfields, we can codegen this as an add
1040 // (for better address arithmetic) if the LHS and RHS of the OR are
1041 // provably disjoint.
1042 APInt LHSKnownZero, LHSKnownOne;
1043 DAG.ComputeMaskedBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1045 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1046 // If all of the bits are known zero on the LHS or RHS, the add won't
1048 Base = N.getOperand(0);
1049 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
1053 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1054 // Loading from a constant address.
1056 // If this address fits entirely in a 16-bit sext immediate field, codegen
1059 if (isIntS16Immediate(CN, Imm)) {
1060 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1061 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1062 CN->getValueType(0));
1066 // Handle 32-bit sext immediates with LIS + addr mode.
1067 if (CN->getValueType(0) == MVT::i32 ||
1068 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
1069 int Addr = (int)CN->getZExtValue();
1071 // Otherwise, break this down into an LIS + disp.
1072 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1074 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1075 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1076 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1081 Disp = DAG.getTargetConstant(0, getPointerTy());
1082 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
1083 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1086 return true; // [r+0]
1089 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1090 /// represented as an indexed [r+r] operation.
1091 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1093 SelectionDAG &DAG) const {
1094 // Check to see if we can easily represent this as an [r+r] address. This
1095 // will fail if it thinks that the address is more profitably represented as
1096 // reg+imm, e.g. where imm = 0.
1097 if (SelectAddressRegReg(N, Base, Index, DAG))
1100 // If the operand is an addition, always emit this as [r+r], since this is
1101 // better (for code size, and execution, as the memop does the add for free)
1102 // than emitting an explicit add.
1103 if (N.getOpcode() == ISD::ADD) {
1104 Base = N.getOperand(0);
1105 Index = N.getOperand(1);
1109 // Otherwise, do it the hard way, using R0 as the base register.
1110 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1116 /// SelectAddressRegImmShift - Returns true if the address N can be
1117 /// represented by a base register plus a signed 14-bit displacement
1118 /// [r+imm*4]. Suitable for use by STD and friends.
1119 bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp,
1121 SelectionDAG &DAG) const {
1122 // FIXME dl should come from the parent load or store, not the address
1123 DebugLoc dl = N.getDebugLoc();
1124 // If this can be more profitably realized as r+r, fail.
1125 if (SelectAddressRegReg(N, Disp, Base, DAG))
1128 if (N.getOpcode() == ISD::ADD) {
1130 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
1131 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
1132 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1133 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1135 Base = N.getOperand(0);
1137 return true; // [r+i]
1138 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1139 // Match LOAD (ADD (X, Lo(G))).
1140 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1141 && "Cannot handle constant offsets yet!");
1142 Disp = N.getOperand(1).getOperand(0); // The global address.
1143 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1144 Disp.getOpcode() == ISD::TargetConstantPool ||
1145 Disp.getOpcode() == ISD::TargetJumpTable);
1146 Base = N.getOperand(0);
1147 return true; // [&g+r]
1149 } else if (N.getOpcode() == ISD::OR) {
1151 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
1152 // If this is an or of disjoint bitfields, we can codegen this as an add
1153 // (for better address arithmetic) if the LHS and RHS of the OR are
1154 // provably disjoint.
1155 APInt LHSKnownZero, LHSKnownOne;
1156 DAG.ComputeMaskedBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1157 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1158 // If all of the bits are known zero on the LHS or RHS, the add won't
1160 Base = N.getOperand(0);
1161 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
1165 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1166 // Loading from a constant address. Verify low two bits are clear.
1167 if ((CN->getZExtValue() & 3) == 0) {
1168 // If this address fits entirely in a 14-bit sext immediate field, codegen
1171 if (isIntS16Immediate(CN, Imm)) {
1172 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
1173 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1174 CN->getValueType(0));
1178 // Fold the low-part of 32-bit absolute addresses into addr mode.
1179 if (CN->getValueType(0) == MVT::i32 ||
1180 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
1181 int Addr = (int)CN->getZExtValue();
1183 // Otherwise, break this down into an LIS + disp.
1184 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
1185 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
1186 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1187 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base),0);
1193 Disp = DAG.getTargetConstant(0, getPointerTy());
1194 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
1195 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1198 return true; // [r+0]
1202 /// getPreIndexedAddressParts - returns true by value, base pointer and
1203 /// offset pointer and addressing mode by reference if the node's address
1204 /// can be legally represented as pre-indexed load / store address.
1205 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1207 ISD::MemIndexedMode &AM,
1208 SelectionDAG &DAG) const {
1209 if (DisablePPCPreinc) return false;
1215 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1216 Ptr = LD->getBasePtr();
1217 VT = LD->getMemoryVT();
1218 Alignment = LD->getAlignment();
1219 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1220 Ptr = ST->getBasePtr();
1221 VT = ST->getMemoryVT();
1222 Alignment = ST->getAlignment();
1227 // PowerPC doesn't have preinc load/store instructions for vectors.
1231 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1233 // Common code will reject creating a pre-inc form if the base pointer
1234 // is a frame index, or if N is a store and the base pointer is either
1235 // the same as or a predecessor of the value being stored. Check for
1236 // those situations here, and try with swapped Base/Offset instead.
1239 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1242 SDValue Val = cast<StoreSDNode>(N)->getValue();
1243 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1248 std::swap(Base, Offset);
1254 // LDU/STU use reg+imm*4, others use reg+imm.
1255 if (VT != MVT::i64) {
1257 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
1260 // LDU/STU need an address with at least 4-byte alignment.
1265 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
1269 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1270 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1271 // sext i32 to i64 when addr mode is r+i.
1272 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1273 LD->getExtensionType() == ISD::SEXTLOAD &&
1274 isa<ConstantSDNode>(Offset))
1282 //===----------------------------------------------------------------------===//
1283 // LowerOperation implementation
1284 //===----------------------------------------------------------------------===//
1286 /// GetLabelAccessInfo - Return true if we should reference labels using a
1287 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1288 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1289 unsigned &LoOpFlags, const GlobalValue *GV = 0) {
1290 HiOpFlags = PPCII::MO_HA16;
1291 LoOpFlags = PPCII::MO_LO16;
1293 // Don't use the pic base if not in PIC relocation model. Or if we are on a
1294 // non-darwin platform. We don't support PIC on other platforms yet.
1295 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ &&
1296 TM.getSubtarget<PPCSubtarget>().isDarwin();
1298 HiOpFlags |= PPCII::MO_PIC_FLAG;
1299 LoOpFlags |= PPCII::MO_PIC_FLAG;
1302 // If this is a reference to a global value that requires a non-lazy-ptr, make
1303 // sure that instruction lowering adds it.
1304 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1305 HiOpFlags |= PPCII::MO_NLP_FLAG;
1306 LoOpFlags |= PPCII::MO_NLP_FLAG;
1308 if (GV->hasHiddenVisibility()) {
1309 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1310 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1317 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1318 SelectionDAG &DAG) {
1319 EVT PtrVT = HiPart.getValueType();
1320 SDValue Zero = DAG.getConstant(0, PtrVT);
1321 DebugLoc DL = HiPart.getDebugLoc();
1323 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1324 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1326 // With PIC, the first instruction is actually "GR+hi(&G)".
1328 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1329 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1331 // Generate non-pic code that has direct accesses to the constant pool.
1332 // The address of the global is just (hi(&g)+lo(&g)).
1333 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1336 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1337 SelectionDAG &DAG) const {
1338 EVT PtrVT = Op.getValueType();
1339 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1340 const Constant *C = CP->getConstVal();
1342 // 64-bit SVR4 ABI code is always position-independent.
1343 // The actual address of the GlobalValue is stored in the TOC.
1344 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1345 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1346 return DAG.getNode(PPCISD::TOC_ENTRY, CP->getDebugLoc(), MVT::i64, GA,
1347 DAG.getRegister(PPC::X2, MVT::i64));
1350 unsigned MOHiFlag, MOLoFlag;
1351 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1353 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1355 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1356 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1359 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1360 EVT PtrVT = Op.getValueType();
1361 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1363 // 64-bit SVR4 ABI code is always position-independent.
1364 // The actual address of the GlobalValue is stored in the TOC.
1365 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1366 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1367 return DAG.getNode(PPCISD::TOC_ENTRY, JT->getDebugLoc(), MVT::i64, GA,
1368 DAG.getRegister(PPC::X2, MVT::i64));
1371 unsigned MOHiFlag, MOLoFlag;
1372 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1373 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1374 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1375 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1378 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1379 SelectionDAG &DAG) const {
1380 EVT PtrVT = Op.getValueType();
1382 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1384 unsigned MOHiFlag, MOLoFlag;
1385 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1386 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1387 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1388 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1391 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1392 SelectionDAG &DAG) const {
1394 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1395 DebugLoc dl = GA->getDebugLoc();
1396 const GlobalValue *GV = GA->getGlobal();
1397 EVT PtrVT = getPointerTy();
1398 bool is64bit = PPCSubTarget.isPPC64();
1400 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1402 if (Model == TLSModel::LocalExec) {
1403 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1404 PPCII::MO_TPREL16_HA);
1405 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1406 PPCII::MO_TPREL16_LO);
1407 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1408 is64bit ? MVT::i64 : MVT::i32);
1409 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1410 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1414 llvm_unreachable("only local-exec is currently supported for ppc32");
1416 if (Model == TLSModel::InitialExec) {
1417 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1418 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1419 SDValue TPOffsetHi = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1420 PtrVT, GOTReg, TGA);
1421 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1422 PtrVT, TGA, TPOffsetHi);
1423 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGA);
1426 if (Model == TLSModel::GeneralDynamic) {
1427 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1428 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1429 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1431 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1434 // We need a chain node, and don't have one handy. The underlying
1435 // call has no side effects, so using the function entry node
1437 SDValue Chain = DAG.getEntryNode();
1438 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1439 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1440 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl,
1441 PtrVT, ParmReg, TGA);
1442 // The return value from GET_TLS_ADDR really is in X3 already, but
1443 // some hacks are needed here to tie everything together. The extra
1444 // copies dissolve during subsequent transforms.
1445 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1446 return DAG.getCopyFromReg(Chain, dl, PPC::X3, PtrVT);
1449 if (Model == TLSModel::LocalDynamic) {
1450 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1451 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1452 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1454 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1457 // We need a chain node, and don't have one handy. The underlying
1458 // call has no side effects, so using the function entry node
1460 SDValue Chain = DAG.getEntryNode();
1461 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1462 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1463 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl,
1464 PtrVT, ParmReg, TGA);
1465 // The return value from GET_TLSLD_ADDR really is in X3 already, but
1466 // some hacks are needed here to tie everything together. The extra
1467 // copies dissolve during subsequent transforms.
1468 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1469 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1470 Chain, ParmReg, TGA);
1471 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1474 llvm_unreachable("Unknown TLS model!");
1477 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1478 SelectionDAG &DAG) const {
1479 EVT PtrVT = Op.getValueType();
1480 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1481 DebugLoc DL = GSDN->getDebugLoc();
1482 const GlobalValue *GV = GSDN->getGlobal();
1484 // 64-bit SVR4 ABI code is always position-independent.
1485 // The actual address of the GlobalValue is stored in the TOC.
1486 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1487 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1488 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1489 DAG.getRegister(PPC::X2, MVT::i64));
1492 unsigned MOHiFlag, MOLoFlag;
1493 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1496 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1498 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1500 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1502 // If the global reference is actually to a non-lazy-pointer, we have to do an
1503 // extra load to get the address of the global.
1504 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1505 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1506 false, false, false, 0);
1510 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1511 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1512 DebugLoc dl = Op.getDebugLoc();
1514 // If we're comparing for equality to zero, expose the fact that this is
1515 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1516 // fold the new nodes.
1517 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1518 if (C->isNullValue() && CC == ISD::SETEQ) {
1519 EVT VT = Op.getOperand(0).getValueType();
1520 SDValue Zext = Op.getOperand(0);
1521 if (VT.bitsLT(MVT::i32)) {
1523 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1525 unsigned Log2b = Log2_32(VT.getSizeInBits());
1526 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1527 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1528 DAG.getConstant(Log2b, MVT::i32));
1529 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1531 // Leave comparisons against 0 and -1 alone for now, since they're usually
1532 // optimized. FIXME: revisit this when we can custom lower all setcc
1534 if (C->isAllOnesValue() || C->isNullValue())
1538 // If we have an integer seteq/setne, turn it into a compare against zero
1539 // by xor'ing the rhs with the lhs, which is faster than setting a
1540 // condition register, reading it back out, and masking the correct bit. The
1541 // normal approach here uses sub to do this instead of xor. Using xor exposes
1542 // the result to other bit-twiddling opportunities.
1543 EVT LHSVT = Op.getOperand(0).getValueType();
1544 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1545 EVT VT = Op.getValueType();
1546 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1548 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1553 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1554 const PPCSubtarget &Subtarget) const {
1555 SDNode *Node = Op.getNode();
1556 EVT VT = Node->getValueType(0);
1557 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1558 SDValue InChain = Node->getOperand(0);
1559 SDValue VAListPtr = Node->getOperand(1);
1560 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1561 DebugLoc dl = Node->getDebugLoc();
1563 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1566 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1567 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1569 InChain = GprIndex.getValue(1);
1571 if (VT == MVT::i64) {
1572 // Check if GprIndex is even
1573 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1574 DAG.getConstant(1, MVT::i32));
1575 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1576 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1577 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1578 DAG.getConstant(1, MVT::i32));
1579 // Align GprIndex to be even if it isn't
1580 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1584 // fpr index is 1 byte after gpr
1585 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1586 DAG.getConstant(1, MVT::i32));
1589 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1590 FprPtr, MachinePointerInfo(SV), MVT::i8,
1592 InChain = FprIndex.getValue(1);
1594 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1595 DAG.getConstant(8, MVT::i32));
1597 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1598 DAG.getConstant(4, MVT::i32));
1601 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1602 MachinePointerInfo(), false, false,
1604 InChain = OverflowArea.getValue(1);
1606 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1607 MachinePointerInfo(), false, false,
1609 InChain = RegSaveArea.getValue(1);
1611 // select overflow_area if index > 8
1612 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1613 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1615 // adjustment constant gpr_index * 4/8
1616 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1617 VT.isInteger() ? GprIndex : FprIndex,
1618 DAG.getConstant(VT.isInteger() ? 4 : 8,
1621 // OurReg = RegSaveArea + RegConstant
1622 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1625 // Floating types are 32 bytes into RegSaveArea
1626 if (VT.isFloatingPoint())
1627 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1628 DAG.getConstant(32, MVT::i32));
1630 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1631 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1632 VT.isInteger() ? GprIndex : FprIndex,
1633 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1636 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1637 VT.isInteger() ? VAListPtr : FprPtr,
1638 MachinePointerInfo(SV),
1639 MVT::i8, false, false, 0);
1641 // determine if we should load from reg_save_area or overflow_area
1642 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1644 // increase overflow_area by 4/8 if gpr/fpr > 8
1645 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1646 DAG.getConstant(VT.isInteger() ? 4 : 8,
1649 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1652 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1654 MachinePointerInfo(),
1655 MVT::i32, false, false, 0);
1657 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1658 false, false, false, 0);
1661 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
1662 SelectionDAG &DAG) const {
1663 return Op.getOperand(0);
1666 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
1667 SelectionDAG &DAG) const {
1668 SDValue Chain = Op.getOperand(0);
1669 SDValue Trmp = Op.getOperand(1); // trampoline
1670 SDValue FPtr = Op.getOperand(2); // nested function
1671 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1672 DebugLoc dl = Op.getDebugLoc();
1674 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1675 bool isPPC64 = (PtrVT == MVT::i64);
1677 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
1680 TargetLowering::ArgListTy Args;
1681 TargetLowering::ArgListEntry Entry;
1683 Entry.Ty = IntPtrTy;
1684 Entry.Node = Trmp; Args.push_back(Entry);
1686 // TrampSize == (isPPC64 ? 48 : 40);
1687 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1688 isPPC64 ? MVT::i64 : MVT::i32);
1689 Args.push_back(Entry);
1691 Entry.Node = FPtr; Args.push_back(Entry);
1692 Entry.Node = Nest; Args.push_back(Entry);
1694 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1695 TargetLowering::CallLoweringInfo CLI(Chain,
1696 Type::getVoidTy(*DAG.getContext()),
1697 false, false, false, false, 0,
1699 /*isTailCall=*/false,
1700 /*doesNotRet=*/false,
1701 /*isReturnValueUsed=*/true,
1702 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1704 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1706 return CallResult.second;
1709 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1710 const PPCSubtarget &Subtarget) const {
1711 MachineFunction &MF = DAG.getMachineFunction();
1712 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1714 DebugLoc dl = Op.getDebugLoc();
1716 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
1717 // vastart just stores the address of the VarArgsFrameIndex slot into the
1718 // memory location argument.
1719 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1720 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1721 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1722 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
1723 MachinePointerInfo(SV),
1727 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
1728 // We suppose the given va_list is already allocated.
1731 // char gpr; /* index into the array of 8 GPRs
1732 // * stored in the register save area
1733 // * gpr=0 corresponds to r3,
1734 // * gpr=1 to r4, etc.
1736 // char fpr; /* index into the array of 8 FPRs
1737 // * stored in the register save area
1738 // * fpr=0 corresponds to f1,
1739 // * fpr=1 to f2, etc.
1741 // char *overflow_arg_area;
1742 // /* location on stack that holds
1743 // * the next overflow argument
1745 // char *reg_save_area;
1746 // /* where r3:r10 and f1:f8 (if saved)
1752 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
1753 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
1756 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1758 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
1760 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1763 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
1764 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1766 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
1767 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1769 uint64_t FPROffset = 1;
1770 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1772 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1774 // Store first byte : number of int regs
1775 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
1777 MachinePointerInfo(SV),
1778 MVT::i8, false, false, 0);
1779 uint64_t nextOffset = FPROffset;
1780 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
1783 // Store second byte : number of float regs
1784 SDValue secondStore =
1785 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
1786 MachinePointerInfo(SV, nextOffset), MVT::i8,
1788 nextOffset += StackOffset;
1789 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
1791 // Store second word : arguments given on stack
1792 SDValue thirdStore =
1793 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
1794 MachinePointerInfo(SV, nextOffset),
1796 nextOffset += FrameOffset;
1797 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
1799 // Store third word : arguments given in registers
1800 return DAG.getStore(thirdStore, dl, FR, nextPtr,
1801 MachinePointerInfo(SV, nextOffset),
1806 #include "PPCGenCallingConv.inc"
1808 static bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
1809 CCValAssign::LocInfo &LocInfo,
1810 ISD::ArgFlagsTy &ArgFlags,
1815 static bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
1817 CCValAssign::LocInfo &LocInfo,
1818 ISD::ArgFlagsTy &ArgFlags,
1820 static const uint16_t ArgRegs[] = {
1821 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1822 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1824 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1826 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1828 // Skip one register if the first unallocated register has an even register
1829 // number and there are still argument registers available which have not been
1830 // allocated yet. RegNum is actually an index into ArgRegs, which means we
1831 // need to skip a register if RegNum is odd.
1832 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
1833 State.AllocateReg(ArgRegs[RegNum]);
1836 // Always return false here, as this function only makes sure that the first
1837 // unallocated register has an odd register number and does not actually
1838 // allocate a register for the current argument.
1842 static bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
1844 CCValAssign::LocInfo &LocInfo,
1845 ISD::ArgFlagsTy &ArgFlags,
1847 static const uint16_t ArgRegs[] = {
1848 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1852 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1854 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1856 // If there is only one Floating-point register left we need to put both f64
1857 // values of a split ppc_fp128 value on the stack.
1858 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
1859 State.AllocateReg(ArgRegs[RegNum]);
1862 // Always return false here, as this function only makes sure that the two f64
1863 // values a ppc_fp128 value is split into are both passed in registers or both
1864 // passed on the stack and does not actually allocate a register for the
1865 // current argument.
1869 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1871 static const uint16_t *GetFPR() {
1872 static const uint16_t FPR[] = {
1873 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1874 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1880 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
1882 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
1883 unsigned PtrByteSize) {
1884 unsigned ArgSize = ArgVT.getSizeInBits()/8;
1885 if (Flags.isByVal())
1886 ArgSize = Flags.getByValSize();
1887 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1893 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
1894 CallingConv::ID CallConv, bool isVarArg,
1895 const SmallVectorImpl<ISD::InputArg>
1897 DebugLoc dl, SelectionDAG &DAG,
1898 SmallVectorImpl<SDValue> &InVals)
1900 if (PPCSubTarget.isSVR4ABI()) {
1901 if (PPCSubTarget.isPPC64())
1902 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
1905 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
1908 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
1914 PPCTargetLowering::LowerFormalArguments_32SVR4(
1916 CallingConv::ID CallConv, bool isVarArg,
1917 const SmallVectorImpl<ISD::InputArg>
1919 DebugLoc dl, SelectionDAG &DAG,
1920 SmallVectorImpl<SDValue> &InVals) const {
1922 // 32-bit SVR4 ABI Stack Frame Layout:
1923 // +-----------------------------------+
1924 // +--> | Back chain |
1925 // | +-----------------------------------+
1926 // | | Floating-point register save area |
1927 // | +-----------------------------------+
1928 // | | General register save area |
1929 // | +-----------------------------------+
1930 // | | CR save word |
1931 // | +-----------------------------------+
1932 // | | VRSAVE save word |
1933 // | +-----------------------------------+
1934 // | | Alignment padding |
1935 // | +-----------------------------------+
1936 // | | Vector register save area |
1937 // | +-----------------------------------+
1938 // | | Local variable space |
1939 // | +-----------------------------------+
1940 // | | Parameter list area |
1941 // | +-----------------------------------+
1942 // | | LR save word |
1943 // | +-----------------------------------+
1944 // SP--> +--- | Back chain |
1945 // +-----------------------------------+
1948 // System V Application Binary Interface PowerPC Processor Supplement
1949 // AltiVec Technology Programming Interface Manual
1951 MachineFunction &MF = DAG.getMachineFunction();
1952 MachineFrameInfo *MFI = MF.getFrameInfo();
1953 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1955 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1956 // Potential tail calls could cause overwriting of argument stack slots.
1957 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
1958 (CallConv == CallingConv::Fast));
1959 unsigned PtrByteSize = 4;
1961 // Assign locations to all of the incoming arguments.
1962 SmallVector<CCValAssign, 16> ArgLocs;
1963 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1964 getTargetMachine(), ArgLocs, *DAG.getContext());
1966 // Reserve space for the linkage area on the stack.
1967 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
1969 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
1971 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1972 CCValAssign &VA = ArgLocs[i];
1974 // Arguments stored in registers.
1975 if (VA.isRegLoc()) {
1976 const TargetRegisterClass *RC;
1977 EVT ValVT = VA.getValVT();
1979 switch (ValVT.getSimpleVT().SimpleTy) {
1981 llvm_unreachable("ValVT not supported by formal arguments Lowering");
1983 RC = &PPC::GPRCRegClass;
1986 RC = &PPC::F4RCRegClass;
1989 RC = &PPC::F8RCRegClass;
1995 RC = &PPC::VRRCRegClass;
1999 // Transform the arguments stored in physical registers into virtual ones.
2000 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2001 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT);
2003 InVals.push_back(ArgValue);
2005 // Argument stored in memory.
2006 assert(VA.isMemLoc());
2008 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
2009 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2012 // Create load nodes to retrieve arguments from the stack.
2013 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2014 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2015 MachinePointerInfo(),
2016 false, false, false, 0));
2020 // Assign locations to all of the incoming aggregate by value arguments.
2021 // Aggregates passed by value are stored in the local variable space of the
2022 // caller's stack frame, right above the parameter list area.
2023 SmallVector<CCValAssign, 16> ByValArgLocs;
2024 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2025 getTargetMachine(), ByValArgLocs, *DAG.getContext());
2027 // Reserve stack space for the allocations in CCInfo.
2028 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2030 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2032 // Area that is at least reserved in the caller of this function.
2033 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2035 // Set the size that is at least reserved in caller of this function. Tail
2036 // call optimized function's reserved stack space needs to be aligned so that
2037 // taking the difference between two stack areas will result in an aligned
2039 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2042 std::max(MinReservedArea,
2043 PPCFrameLowering::getMinCallFrameSize(false, false));
2045 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
2046 getStackAlignment();
2047 unsigned AlignMask = TargetAlign-1;
2048 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2050 FI->setMinReservedArea(MinReservedArea);
2052 SmallVector<SDValue, 8> MemOps;
2054 // If the function takes variable number of arguments, make a frame index for
2055 // the start of the first vararg value... for expansion of llvm.va_start.
2057 static const uint16_t GPArgRegs[] = {
2058 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2059 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2061 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2063 static const uint16_t FPArgRegs[] = {
2064 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2067 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2069 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2071 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2074 // Make room for NumGPArgRegs and NumFPArgRegs.
2075 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2076 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
2078 FuncInfo->setVarArgsStackOffset(
2079 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2080 CCInfo.getNextStackOffset(), true));
2082 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2083 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2085 // The fixed integer arguments of a variadic function are stored to the
2086 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2087 // the result of va_next.
2088 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2089 // Get an existing live-in vreg, or add a new one.
2090 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2092 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2094 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2095 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2096 MachinePointerInfo(), false, false, 0);
2097 MemOps.push_back(Store);
2098 // Increment the address by four for the next argument to store
2099 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2100 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2103 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2105 // The double arguments are stored to the VarArgsFrameIndex
2107 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2108 // Get an existing live-in vreg, or add a new one.
2109 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2111 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2113 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2114 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2115 MachinePointerInfo(), false, false, 0);
2116 MemOps.push_back(Store);
2117 // Increment the address by eight for the next argument to store
2118 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
2120 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2124 if (!MemOps.empty())
2125 Chain = DAG.getNode(ISD::TokenFactor, dl,
2126 MVT::Other, &MemOps[0], MemOps.size());
2131 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2132 // value to MVT::i64 and then truncate to the correct register size.
2134 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2135 SelectionDAG &DAG, SDValue ArgVal,
2136 DebugLoc dl) const {
2138 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2139 DAG.getValueType(ObjectVT));
2140 else if (Flags.isZExt())
2141 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2142 DAG.getValueType(ObjectVT));
2144 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2147 // Set the size that is at least reserved in caller of this function. Tail
2148 // call optimized functions' reserved stack space needs to be aligned so that
2149 // taking the difference between two stack areas will result in an aligned
2152 PPCTargetLowering::setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG,
2153 unsigned nAltivecParamsAtEnd,
2154 unsigned MinReservedArea,
2155 bool isPPC64) const {
2156 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2157 // Add the Altivec parameters at the end, if needed.
2158 if (nAltivecParamsAtEnd) {
2159 MinReservedArea = ((MinReservedArea+15)/16)*16;
2160 MinReservedArea += 16*nAltivecParamsAtEnd;
2163 std::max(MinReservedArea,
2164 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2165 unsigned TargetAlign
2166 = DAG.getMachineFunction().getTarget().getFrameLowering()->
2167 getStackAlignment();
2168 unsigned AlignMask = TargetAlign-1;
2169 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2170 FI->setMinReservedArea(MinReservedArea);
2174 PPCTargetLowering::LowerFormalArguments_64SVR4(
2176 CallingConv::ID CallConv, bool isVarArg,
2177 const SmallVectorImpl<ISD::InputArg>
2179 DebugLoc dl, SelectionDAG &DAG,
2180 SmallVectorImpl<SDValue> &InVals) const {
2181 // TODO: add description of PPC stack frame format, or at least some docs.
2183 MachineFunction &MF = DAG.getMachineFunction();
2184 MachineFrameInfo *MFI = MF.getFrameInfo();
2185 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2187 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2188 // Potential tail calls could cause overwriting of argument stack slots.
2189 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2190 (CallConv == CallingConv::Fast));
2191 unsigned PtrByteSize = 8;
2193 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
2194 // Area that is at least reserved in caller of this function.
2195 unsigned MinReservedArea = ArgOffset;
2197 static const uint16_t GPR[] = {
2198 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2199 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2202 static const uint16_t *FPR = GetFPR();
2204 static const uint16_t VR[] = {
2205 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2206 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2209 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2210 const unsigned Num_FPR_Regs = 13;
2211 const unsigned Num_VR_Regs = array_lengthof(VR);
2213 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2215 // Add DAG nodes to load the arguments or copy them out of registers. On
2216 // entry to a function on PPC, the arguments start after the linkage area,
2217 // although the first ones are often in registers.
2219 SmallVector<SDValue, 8> MemOps;
2220 unsigned nAltivecParamsAtEnd = 0;
2221 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2222 unsigned CurArgIdx = 0;
2223 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2225 bool needsLoad = false;
2226 EVT ObjectVT = Ins[ArgNo].VT;
2227 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2228 unsigned ArgSize = ObjSize;
2229 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2230 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2231 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2233 unsigned CurArgOffset = ArgOffset;
2235 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2236 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2237 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2239 MinReservedArea = ((MinReservedArea+15)/16)*16;
2240 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2244 nAltivecParamsAtEnd++;
2246 // Calculate min reserved area.
2247 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2251 // FIXME the codegen can be much improved in some cases.
2252 // We do not have to keep everything in memory.
2253 if (Flags.isByVal()) {
2254 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2255 ObjSize = Flags.getByValSize();
2256 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2257 // Empty aggregate parameters do not take up registers. Examples:
2261 // etc. However, we have to provide a place-holder in InVals, so
2262 // pretend we have an 8-byte item at the current address for that
2265 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2266 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2267 InVals.push_back(FIN);
2270 // All aggregates smaller than 8 bytes must be passed right-justified.
2271 if (ObjSize < PtrByteSize)
2272 CurArgOffset = CurArgOffset + (PtrByteSize - ObjSize);
2273 // The value of the object is its address.
2274 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2275 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2276 InVals.push_back(FIN);
2279 if (GPR_idx != Num_GPR_Regs) {
2280 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2281 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2284 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2285 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2286 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2287 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2288 MachinePointerInfo(FuncArg, CurArgOffset),
2289 ObjType, false, false, 0);
2291 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2292 // store the whole register as-is to the parameter save area
2293 // slot. The address of the parameter was already calculated
2294 // above (InVals.push_back(FIN)) to be the right-justified
2295 // offset within the slot. For this store, we need a new
2296 // frame index that points at the beginning of the slot.
2297 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2298 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2299 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2300 MachinePointerInfo(FuncArg, ArgOffset),
2304 MemOps.push_back(Store);
2307 // Whether we copied from a register or not, advance the offset
2308 // into the parameter save area by a full doubleword.
2309 ArgOffset += PtrByteSize;
2313 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2314 // Store whatever pieces of the object are in registers
2315 // to memory. ArgOffset will be the address of the beginning
2317 if (GPR_idx != Num_GPR_Regs) {
2319 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2320 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2321 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2322 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2323 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2324 MachinePointerInfo(FuncArg, ArgOffset),
2326 MemOps.push_back(Store);
2328 ArgOffset += PtrByteSize;
2330 ArgOffset += ArgSize - j;
2337 switch (ObjectVT.getSimpleVT().SimpleTy) {
2338 default: llvm_unreachable("Unhandled argument type!");
2341 if (GPR_idx != Num_GPR_Regs) {
2342 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2343 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2345 if (ObjectVT == MVT::i32)
2346 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2347 // value to MVT::i64 and then truncate to the correct register size.
2348 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2353 ArgSize = PtrByteSize;
2360 // Every 8 bytes of argument space consumes one of the GPRs available for
2361 // argument passing.
2362 if (GPR_idx != Num_GPR_Regs) {
2365 if (FPR_idx != Num_FPR_Regs) {
2368 if (ObjectVT == MVT::f32)
2369 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2371 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2373 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2377 ArgSize = PtrByteSize;
2386 // Note that vector arguments in registers don't reserve stack space,
2387 // except in varargs functions.
2388 if (VR_idx != Num_VR_Regs) {
2389 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2390 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2392 while ((ArgOffset % 16) != 0) {
2393 ArgOffset += PtrByteSize;
2394 if (GPR_idx != Num_GPR_Regs)
2398 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2402 // Vectors are aligned.
2403 ArgOffset = ((ArgOffset+15)/16)*16;
2404 CurArgOffset = ArgOffset;
2411 // We need to load the argument to a virtual register if we determined
2412 // above that we ran out of physical registers of the appropriate type.
2414 int FI = MFI->CreateFixedObject(ObjSize,
2415 CurArgOffset + (ArgSize - ObjSize),
2417 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2418 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2419 false, false, false, 0);
2422 InVals.push_back(ArgVal);
2425 // Set the size that is at least reserved in caller of this function. Tail
2426 // call optimized functions' reserved stack space needs to be aligned so that
2427 // taking the difference between two stack areas will result in an aligned
2429 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, true);
2431 // If the function takes variable number of arguments, make a frame index for
2432 // the start of the first vararg value... for expansion of llvm.va_start.
2434 int Depth = ArgOffset;
2436 FuncInfo->setVarArgsFrameIndex(
2437 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2438 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2440 // If this function is vararg, store any remaining integer argument regs
2441 // to their spots on the stack so that they may be loaded by deferencing the
2442 // result of va_next.
2443 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2444 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2445 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2446 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2447 MachinePointerInfo(), false, false, 0);
2448 MemOps.push_back(Store);
2449 // Increment the address by four for the next argument to store
2450 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2451 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2455 if (!MemOps.empty())
2456 Chain = DAG.getNode(ISD::TokenFactor, dl,
2457 MVT::Other, &MemOps[0], MemOps.size());
2463 PPCTargetLowering::LowerFormalArguments_Darwin(
2465 CallingConv::ID CallConv, bool isVarArg,
2466 const SmallVectorImpl<ISD::InputArg>
2468 DebugLoc dl, SelectionDAG &DAG,
2469 SmallVectorImpl<SDValue> &InVals) const {
2470 // TODO: add description of PPC stack frame format, or at least some docs.
2472 MachineFunction &MF = DAG.getMachineFunction();
2473 MachineFrameInfo *MFI = MF.getFrameInfo();
2474 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2476 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2477 bool isPPC64 = PtrVT == MVT::i64;
2478 // Potential tail calls could cause overwriting of argument stack slots.
2479 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2480 (CallConv == CallingConv::Fast));
2481 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2483 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
2484 // Area that is at least reserved in caller of this function.
2485 unsigned MinReservedArea = ArgOffset;
2487 static const uint16_t GPR_32[] = { // 32-bit registers.
2488 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2489 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2491 static const uint16_t GPR_64[] = { // 64-bit registers.
2492 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2493 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2496 static const uint16_t *FPR = GetFPR();
2498 static const uint16_t VR[] = {
2499 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2500 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2503 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2504 const unsigned Num_FPR_Regs = 13;
2505 const unsigned Num_VR_Regs = array_lengthof( VR);
2507 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2509 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
2511 // In 32-bit non-varargs functions, the stack space for vectors is after the
2512 // stack space for non-vectors. We do not use this space unless we have
2513 // too many vectors to fit in registers, something that only occurs in
2514 // constructed examples:), but we have to walk the arglist to figure
2515 // that out...for the pathological case, compute VecArgOffset as the
2516 // start of the vector parameter area. Computing VecArgOffset is the
2517 // entire point of the following loop.
2518 unsigned VecArgOffset = ArgOffset;
2519 if (!isVarArg && !isPPC64) {
2520 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
2522 EVT ObjectVT = Ins[ArgNo].VT;
2523 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2525 if (Flags.isByVal()) {
2526 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
2527 unsigned ObjSize = Flags.getByValSize();
2529 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2530 VecArgOffset += ArgSize;
2534 switch(ObjectVT.getSimpleVT().SimpleTy) {
2535 default: llvm_unreachable("Unhandled argument type!");
2540 case MVT::i64: // PPC64
2542 // FIXME: We are guaranteed to be !isPPC64 at this point.
2543 // Does MVT::i64 apply?
2550 // Nothing to do, we're only looking at Nonvector args here.
2555 // We've found where the vector parameter area in memory is. Skip the
2556 // first 12 parameters; these don't use that memory.
2557 VecArgOffset = ((VecArgOffset+15)/16)*16;
2558 VecArgOffset += 12*16;
2560 // Add DAG nodes to load the arguments or copy them out of registers. On
2561 // entry to a function on PPC, the arguments start after the linkage area,
2562 // although the first ones are often in registers.
2564 SmallVector<SDValue, 8> MemOps;
2565 unsigned nAltivecParamsAtEnd = 0;
2566 // FIXME: FuncArg and Ins[ArgNo] must reference the same argument.
2567 // When passing anonymous aggregates, this is currently not true.
2568 // See LowerFormalArguments_64SVR4 for a fix.
2569 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2570 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo, ++FuncArg) {
2572 bool needsLoad = false;
2573 EVT ObjectVT = Ins[ArgNo].VT;
2574 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2575 unsigned ArgSize = ObjSize;
2576 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2578 unsigned CurArgOffset = ArgOffset;
2580 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2581 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2582 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2583 if (isVarArg || isPPC64) {
2584 MinReservedArea = ((MinReservedArea+15)/16)*16;
2585 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2588 } else nAltivecParamsAtEnd++;
2590 // Calculate min reserved area.
2591 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2595 // FIXME the codegen can be much improved in some cases.
2596 // We do not have to keep everything in memory.
2597 if (Flags.isByVal()) {
2598 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2599 ObjSize = Flags.getByValSize();
2600 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2601 // Objects of size 1 and 2 are right justified, everything else is
2602 // left justified. This means the memory address is adjusted forwards.
2603 if (ObjSize==1 || ObjSize==2) {
2604 CurArgOffset = CurArgOffset + (4 - ObjSize);
2606 // The value of the object is its address.
2607 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2608 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2609 InVals.push_back(FIN);
2610 if (ObjSize==1 || ObjSize==2) {
2611 if (GPR_idx != Num_GPR_Regs) {
2614 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2616 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2617 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2618 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
2619 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2620 MachinePointerInfo(FuncArg,
2622 ObjType, false, false, 0);
2623 MemOps.push_back(Store);
2627 ArgOffset += PtrByteSize;
2631 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2632 // Store whatever pieces of the object are in registers
2633 // to memory. ArgOffset will be the address of the beginning
2635 if (GPR_idx != Num_GPR_Regs) {
2638 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2640 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2641 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2642 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2643 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2644 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2645 MachinePointerInfo(FuncArg, ArgOffset),
2647 MemOps.push_back(Store);
2649 ArgOffset += PtrByteSize;
2651 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
2658 switch (ObjectVT.getSimpleVT().SimpleTy) {
2659 default: llvm_unreachable("Unhandled argument type!");
2662 if (GPR_idx != Num_GPR_Regs) {
2663 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2664 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2668 ArgSize = PtrByteSize;
2670 // All int arguments reserve stack space in the Darwin ABI.
2671 ArgOffset += PtrByteSize;
2675 case MVT::i64: // PPC64
2676 if (GPR_idx != Num_GPR_Regs) {
2677 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2678 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2680 if (ObjectVT == MVT::i32)
2681 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2682 // value to MVT::i64 and then truncate to the correct register size.
2683 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2688 ArgSize = PtrByteSize;
2690 // All int arguments reserve stack space in the Darwin ABI.
2696 // Every 4 bytes of argument space consumes one of the GPRs available for
2697 // argument passing.
2698 if (GPR_idx != Num_GPR_Regs) {
2700 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
2703 if (FPR_idx != Num_FPR_Regs) {
2706 if (ObjectVT == MVT::f32)
2707 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2709 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2711 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2717 // All FP arguments reserve stack space in the Darwin ABI.
2718 ArgOffset += isPPC64 ? 8 : ObjSize;
2724 // Note that vector arguments in registers don't reserve stack space,
2725 // except in varargs functions.
2726 if (VR_idx != Num_VR_Regs) {
2727 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2728 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2730 while ((ArgOffset % 16) != 0) {
2731 ArgOffset += PtrByteSize;
2732 if (GPR_idx != Num_GPR_Regs)
2736 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2740 if (!isVarArg && !isPPC64) {
2741 // Vectors go after all the nonvectors.
2742 CurArgOffset = VecArgOffset;
2745 // Vectors are aligned.
2746 ArgOffset = ((ArgOffset+15)/16)*16;
2747 CurArgOffset = ArgOffset;
2755 // We need to load the argument to a virtual register if we determined above
2756 // that we ran out of physical registers of the appropriate type.
2758 int FI = MFI->CreateFixedObject(ObjSize,
2759 CurArgOffset + (ArgSize - ObjSize),
2761 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2762 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2763 false, false, false, 0);
2766 InVals.push_back(ArgVal);
2769 // Set the size that is at least reserved in caller of this function. Tail
2770 // call optimized functions' reserved stack space needs to be aligned so that
2771 // taking the difference between two stack areas will result in an aligned
2773 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, isPPC64);
2775 // If the function takes variable number of arguments, make a frame index for
2776 // the start of the first vararg value... for expansion of llvm.va_start.
2778 int Depth = ArgOffset;
2780 FuncInfo->setVarArgsFrameIndex(
2781 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2783 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2785 // If this function is vararg, store any remaining integer argument regs
2786 // to their spots on the stack so that they may be loaded by deferencing the
2787 // result of va_next.
2788 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2792 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2794 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2796 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2797 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2798 MachinePointerInfo(), false, false, 0);
2799 MemOps.push_back(Store);
2800 // Increment the address by four for the next argument to store
2801 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2802 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2806 if (!MemOps.empty())
2807 Chain = DAG.getNode(ISD::TokenFactor, dl,
2808 MVT::Other, &MemOps[0], MemOps.size());
2813 /// CalculateParameterAndLinkageAreaSize - Get the size of the parameter plus
2814 /// linkage area for the Darwin ABI, or the 64-bit SVR4 ABI.
2816 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
2820 const SmallVectorImpl<ISD::OutputArg>
2822 const SmallVectorImpl<SDValue> &OutVals,
2823 unsigned &nAltivecParamsAtEnd) {
2824 // Count how many bytes are to be pushed on the stack, including the linkage
2825 // area, and parameter passing area. We start with 24/48 bytes, which is
2826 // prereserved space for [SP][CR][LR][3 x unused].
2827 unsigned NumBytes = PPCFrameLowering::getLinkageSize(isPPC64, true);
2828 unsigned NumOps = Outs.size();
2829 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2831 // Add up all the space actually used.
2832 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
2833 // they all go in registers, but we must reserve stack space for them for
2834 // possible use by the caller. In varargs or 64-bit calls, parameters are
2835 // assigned stack space in order, with padding so Altivec parameters are
2837 nAltivecParamsAtEnd = 0;
2838 for (unsigned i = 0; i != NumOps; ++i) {
2839 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2840 EVT ArgVT = Outs[i].VT;
2841 // Varargs Altivec parameters are padded to a 16 byte boundary.
2842 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
2843 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
2844 if (!isVarArg && !isPPC64) {
2845 // Non-varargs Altivec parameters go after all the non-Altivec
2846 // parameters; handle those later so we know how much padding we need.
2847 nAltivecParamsAtEnd++;
2850 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
2851 NumBytes = ((NumBytes+15)/16)*16;
2853 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2856 // Allow for Altivec parameters at the end, if needed.
2857 if (nAltivecParamsAtEnd) {
2858 NumBytes = ((NumBytes+15)/16)*16;
2859 NumBytes += 16*nAltivecParamsAtEnd;
2862 // The prolog code of the callee may store up to 8 GPR argument registers to
2863 // the stack, allowing va_start to index over them in memory if its varargs.
2864 // Because we cannot tell if this is needed on the caller side, we have to
2865 // conservatively assume that it is needed. As such, make sure we have at
2866 // least enough stack space for the caller to store the 8 GPRs.
2867 NumBytes = std::max(NumBytes,
2868 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2870 // Tail call needs the stack to be aligned.
2871 if (CC == CallingConv::Fast && DAG.getTarget().Options.GuaranteedTailCallOpt){
2872 unsigned TargetAlign = DAG.getMachineFunction().getTarget().
2873 getFrameLowering()->getStackAlignment();
2874 unsigned AlignMask = TargetAlign-1;
2875 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2881 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
2882 /// adjusted to accommodate the arguments for the tailcall.
2883 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
2884 unsigned ParamSize) {
2886 if (!isTailCall) return 0;
2888 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
2889 unsigned CallerMinReservedArea = FI->getMinReservedArea();
2890 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
2891 // Remember only if the new adjustement is bigger.
2892 if (SPDiff < FI->getTailCallSPDelta())
2893 FI->setTailCallSPDelta(SPDiff);
2898 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2899 /// for tail call optimization. Targets which want to do tail call
2900 /// optimization should implement this function.
2902 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2903 CallingConv::ID CalleeCC,
2905 const SmallVectorImpl<ISD::InputArg> &Ins,
2906 SelectionDAG& DAG) const {
2907 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
2910 // Variable argument functions are not supported.
2914 MachineFunction &MF = DAG.getMachineFunction();
2915 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
2916 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
2917 // Functions containing by val parameters are not supported.
2918 for (unsigned i = 0; i != Ins.size(); i++) {
2919 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2920 if (Flags.isByVal()) return false;
2923 // Non PIC/GOT tail calls are supported.
2924 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
2927 // At the moment we can only do local tail calls (in same module, hidden
2928 // or protected) if we are generating PIC.
2929 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2930 return G->getGlobal()->hasHiddenVisibility()
2931 || G->getGlobal()->hasProtectedVisibility();
2937 /// isCallCompatibleAddress - Return the immediate to use if the specified
2938 /// 32-bit value is representable in the immediate field of a BxA instruction.
2939 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
2940 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2943 int Addr = C->getZExtValue();
2944 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
2945 SignExtend32<26>(Addr) != Addr)
2946 return 0; // Top 6 bits have to be sext of immediate.
2948 return DAG.getConstant((int)C->getZExtValue() >> 2,
2949 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
2954 struct TailCallArgumentInfo {
2959 TailCallArgumentInfo() : FrameIdx(0) {}
2964 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
2966 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
2968 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs,
2969 SmallVector<SDValue, 8> &MemOpChains,
2971 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
2972 SDValue Arg = TailCallArgs[i].Arg;
2973 SDValue FIN = TailCallArgs[i].FrameIdxOp;
2974 int FI = TailCallArgs[i].FrameIdx;
2975 // Store relative to framepointer.
2976 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
2977 MachinePointerInfo::getFixedStack(FI),
2982 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
2983 /// the appropriate stack slot for the tail call optimized function call.
2984 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
2985 MachineFunction &MF,
2994 // Calculate the new stack slot for the return address.
2995 int SlotSize = isPPC64 ? 8 : 4;
2996 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
2998 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
2999 NewRetAddrLoc, true);
3000 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3001 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3002 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3003 MachinePointerInfo::getFixedStack(NewRetAddr),
3006 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3007 // slot as the FP is never overwritten.
3010 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
3011 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3013 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3014 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3015 MachinePointerInfo::getFixedStack(NewFPIdx),
3022 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3023 /// the position of the argument.
3025 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3026 SDValue Arg, int SPDiff, unsigned ArgOffset,
3027 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
3028 int Offset = ArgOffset + SPDiff;
3029 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3030 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3031 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3032 SDValue FIN = DAG.getFrameIndex(FI, VT);
3033 TailCallArgumentInfo Info;
3035 Info.FrameIdxOp = FIN;
3037 TailCallArguments.push_back(Info);
3040 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3041 /// stack slot. Returns the chain as result and the loaded frame pointers in
3042 /// LROpOut/FPOpout. Used when tail calling.
3043 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3049 DebugLoc dl) const {
3051 // Load the LR and FP stack slot for later adjusting.
3052 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
3053 LROpOut = getReturnAddrFrameIndex(DAG);
3054 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3055 false, false, false, 0);
3056 Chain = SDValue(LROpOut.getNode(), 1);
3058 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3059 // slot as the FP is never overwritten.
3061 FPOpOut = getFramePointerFrameIndex(DAG);
3062 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3063 false, false, false, 0);
3064 Chain = SDValue(FPOpOut.getNode(), 1);
3070 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3071 /// by "Src" to address "Dst" of size "Size". Alignment information is
3072 /// specified by the specific parameter attribute. The copy will be passed as
3073 /// a byval function parameter.
3074 /// Sometimes what we are copying is the end of a larger object, the part that
3075 /// does not fit in registers.
3077 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3078 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3080 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3081 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3082 false, false, MachinePointerInfo(0),
3083 MachinePointerInfo(0));
3086 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3089 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3090 SDValue Arg, SDValue PtrOff, int SPDiff,
3091 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3092 bool isVector, SmallVector<SDValue, 8> &MemOpChains,
3093 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments,
3095 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3100 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3102 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3103 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3104 DAG.getConstant(ArgOffset, PtrVT));
3106 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3107 MachinePointerInfo(), false, false, 0));
3108 // Calculate and remember argument location.
3109 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3114 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3115 DebugLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3116 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3117 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments) {
3118 MachineFunction &MF = DAG.getMachineFunction();
3120 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3121 // might overwrite each other in case of tail call optimization.
3122 SmallVector<SDValue, 8> MemOpChains2;
3123 // Do not flag preceding copytoreg stuff together with the following stuff.
3125 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3127 if (!MemOpChains2.empty())
3128 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3129 &MemOpChains2[0], MemOpChains2.size());
3131 // Store the return address to the appropriate stack slot.
3132 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3133 isPPC64, isDarwinABI, dl);
3135 // Emit callseq_end just before tailcall node.
3136 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3137 DAG.getIntPtrConstant(0, true), InFlag);
3138 InFlag = Chain.getValue(1);
3142 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3143 SDValue &Chain, DebugLoc dl, int SPDiff, bool isTailCall,
3144 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
3145 SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys,
3146 const PPCSubtarget &PPCSubTarget) {
3148 bool isPPC64 = PPCSubTarget.isPPC64();
3149 bool isSVR4ABI = PPCSubTarget.isSVR4ABI();
3151 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3152 NodeTys.push_back(MVT::Other); // Returns a chain
3153 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3155 unsigned CallOpc = PPCISD::CALL;
3157 bool needIndirectCall = true;
3158 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3159 // If this is an absolute destination address, use the munged value.
3160 Callee = SDValue(Dest, 0);
3161 needIndirectCall = false;
3164 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3165 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201
3166 // Use indirect calls for ALL functions calls in JIT mode, since the
3167 // far-call stubs may be outside relocation limits for a BL instruction.
3168 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
3169 unsigned OpFlags = 0;
3170 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3171 (PPCSubTarget.getTargetTriple().isMacOSX() &&
3172 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3173 (G->getGlobal()->isDeclaration() ||
3174 G->getGlobal()->isWeakForLinker())) {
3175 // PC-relative references to external symbols should go through $stub,
3176 // unless we're building with the leopard linker or later, which
3177 // automatically synthesizes these stubs.
3178 OpFlags = PPCII::MO_DARWIN_STUB;
3181 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3182 // every direct call is) turn it into a TargetGlobalAddress /
3183 // TargetExternalSymbol node so that legalize doesn't hack it.
3184 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3185 Callee.getValueType(),
3187 needIndirectCall = false;
3191 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3192 unsigned char OpFlags = 0;
3194 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3195 (PPCSubTarget.getTargetTriple().isMacOSX() &&
3196 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5))) {
3197 // PC-relative references to external symbols should go through $stub,
3198 // unless we're building with the leopard linker or later, which
3199 // automatically synthesizes these stubs.
3200 OpFlags = PPCII::MO_DARWIN_STUB;
3203 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3205 needIndirectCall = false;
3208 if (needIndirectCall) {
3209 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3210 // to do the call, we can't use PPCISD::CALL.
3211 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3213 if (isSVR4ABI && isPPC64) {
3214 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3215 // entry point, but to the function descriptor (the function entry point
3216 // address is part of the function descriptor though).
3217 // The function descriptor is a three doubleword structure with the
3218 // following fields: function entry point, TOC base address and
3219 // environment pointer.
3220 // Thus for a call through a function pointer, the following actions need
3222 // 1. Save the TOC of the caller in the TOC save area of its stack
3223 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3224 // 2. Load the address of the function entry point from the function
3226 // 3. Load the TOC of the callee from the function descriptor into r2.
3227 // 4. Load the environment pointer from the function descriptor into
3229 // 5. Branch to the function entry point address.
3230 // 6. On return of the callee, the TOC of the caller needs to be
3231 // restored (this is done in FinishCall()).
3233 // All those operations are flagged together to ensure that no other
3234 // operations can be scheduled in between. E.g. without flagging the
3235 // operations together, a TOC access in the caller could be scheduled
3236 // between the load of the callee TOC and the branch to the callee, which
3237 // results in the TOC access going through the TOC of the callee instead
3238 // of going through the TOC of the caller, which leads to incorrect code.
3240 // Load the address of the function entry point from the function
3242 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3243 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps,
3244 InFlag.getNode() ? 3 : 2);
3245 Chain = LoadFuncPtr.getValue(1);
3246 InFlag = LoadFuncPtr.getValue(2);
3248 // Load environment pointer into r11.
3249 // Offset of the environment pointer within the function descriptor.
3250 SDValue PtrOff = DAG.getIntPtrConstant(16);
3252 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3253 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
3255 Chain = LoadEnvPtr.getValue(1);
3256 InFlag = LoadEnvPtr.getValue(2);
3258 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3260 Chain = EnvVal.getValue(0);
3261 InFlag = EnvVal.getValue(1);
3263 // Load TOC of the callee into r2. We are using a target-specific load
3264 // with r2 hard coded, because the result of a target-independent load
3265 // would never go directly into r2, since r2 is a reserved register (which
3266 // prevents the register allocator from allocating it), resulting in an
3267 // additional register being allocated and an unnecessary move instruction
3269 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3270 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
3272 Chain = LoadTOCPtr.getValue(0);
3273 InFlag = LoadTOCPtr.getValue(1);
3275 MTCTROps[0] = Chain;
3276 MTCTROps[1] = LoadFuncPtr;
3277 MTCTROps[2] = InFlag;
3280 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps,
3281 2 + (InFlag.getNode() != 0));
3282 InFlag = Chain.getValue(1);
3285 NodeTys.push_back(MVT::Other);
3286 NodeTys.push_back(MVT::Glue);
3287 Ops.push_back(Chain);
3288 CallOpc = PPCISD::BCTRL;
3290 // Add use of X11 (holding environment pointer)
3291 if (isSVR4ABI && isPPC64)
3292 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3293 // Add CTR register as callee so a bctr can be emitted later.
3295 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3298 // If this is a direct call, pass the chain and the callee.
3299 if (Callee.getNode()) {
3300 Ops.push_back(Chain);
3301 Ops.push_back(Callee);
3303 // If this is a tail call add stack pointer delta.
3305 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3307 // Add argument registers to the end of the list so that they are known live
3309 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3310 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3311 RegsToPass[i].second.getValueType()));
3317 bool isLocalCall(const SDValue &Callee)
3319 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3320 return !G->getGlobal()->isDeclaration() &&
3321 !G->getGlobal()->isWeakForLinker();
3326 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3327 CallingConv::ID CallConv, bool isVarArg,
3328 const SmallVectorImpl<ISD::InputArg> &Ins,
3329 DebugLoc dl, SelectionDAG &DAG,
3330 SmallVectorImpl<SDValue> &InVals) const {
3332 SmallVector<CCValAssign, 16> RVLocs;
3333 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3334 getTargetMachine(), RVLocs, *DAG.getContext());
3335 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3337 // Copy all of the result registers out of their specified physreg.
3338 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3339 CCValAssign &VA = RVLocs[i];
3340 assert(VA.isRegLoc() && "Can only return in registers!");
3342 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3343 VA.getLocReg(), VA.getLocVT(), InFlag);
3344 Chain = Val.getValue(1);
3345 InFlag = Val.getValue(2);
3347 switch (VA.getLocInfo()) {
3348 default: llvm_unreachable("Unknown loc info!");
3349 case CCValAssign::Full: break;
3350 case CCValAssign::AExt:
3351 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3353 case CCValAssign::ZExt:
3354 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3355 DAG.getValueType(VA.getValVT()));
3356 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3358 case CCValAssign::SExt:
3359 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3360 DAG.getValueType(VA.getValVT()));
3361 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3365 InVals.push_back(Val);
3372 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, DebugLoc dl,
3373 bool isTailCall, bool isVarArg,
3375 SmallVector<std::pair<unsigned, SDValue>, 8>
3377 SDValue InFlag, SDValue Chain,
3379 int SPDiff, unsigned NumBytes,
3380 const SmallVectorImpl<ISD::InputArg> &Ins,
3381 SmallVectorImpl<SDValue> &InVals) const {
3382 std::vector<EVT> NodeTys;
3383 SmallVector<SDValue, 8> Ops;
3384 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
3385 isTailCall, RegsToPass, Ops, NodeTys,
3388 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3389 if (isVarArg && PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64())
3390 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3392 // When performing tail call optimization the callee pops its arguments off
3393 // the stack. Account for this here so these bytes can be pushed back on in
3394 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3395 int BytesCalleePops =
3396 (CallConv == CallingConv::Fast &&
3397 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3399 // Add a register mask operand representing the call-preserved registers.
3400 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
3401 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3402 assert(Mask && "Missing call preserved mask for calling convention");
3403 Ops.push_back(DAG.getRegisterMask(Mask));
3405 if (InFlag.getNode())
3406 Ops.push_back(InFlag);
3410 assert(((Callee.getOpcode() == ISD::Register &&
3411 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3412 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3413 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3414 isa<ConstantSDNode>(Callee)) &&
3415 "Expecting an global address, external symbol, absolute value or register");
3417 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size());
3420 // Add a NOP immediately after the branch instruction when using the 64-bit
3421 // SVR4 ABI. At link time, if caller and callee are in a different module and
3422 // thus have a different TOC, the call will be replaced with a call to a stub
3423 // function which saves the current TOC, loads the TOC of the callee and
3424 // branches to the callee. The NOP will be replaced with a load instruction
3425 // which restores the TOC of the caller from the TOC save slot of the current
3426 // stack frame. If caller and callee belong to the same module (and have the
3427 // same TOC), the NOP will remain unchanged.
3429 bool needsTOCRestore = false;
3430 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) {
3431 if (CallOpc == PPCISD::BCTRL) {
3432 // This is a call through a function pointer.
3433 // Restore the caller TOC from the save area into R2.
3434 // See PrepareCall() for more information about calls through function
3435 // pointers in the 64-bit SVR4 ABI.
3436 // We are using a target-specific load with r2 hard coded, because the
3437 // result of a target-independent load would never go directly into r2,
3438 // since r2 is a reserved register (which prevents the register allocator
3439 // from allocating it), resulting in an additional register being
3440 // allocated and an unnecessary move instruction being generated.
3441 needsTOCRestore = true;
3442 } else if ((CallOpc == PPCISD::CALL) && !isLocalCall(Callee)) {
3443 // Otherwise insert NOP for non-local calls.
3444 CallOpc = PPCISD::CALL_NOP;
3448 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
3449 InFlag = Chain.getValue(1);
3451 if (needsTOCRestore) {
3452 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3453 Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag);
3454 InFlag = Chain.getValue(1);
3457 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3458 DAG.getIntPtrConstant(BytesCalleePops, true),
3461 InFlag = Chain.getValue(1);
3463 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3464 Ins, dl, DAG, InVals);
3468 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3469 SmallVectorImpl<SDValue> &InVals) const {
3470 SelectionDAG &DAG = CLI.DAG;
3471 DebugLoc &dl = CLI.DL;
3472 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
3473 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
3474 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
3475 SDValue Chain = CLI.Chain;
3476 SDValue Callee = CLI.Callee;
3477 bool &isTailCall = CLI.IsTailCall;
3478 CallingConv::ID CallConv = CLI.CallConv;
3479 bool isVarArg = CLI.IsVarArg;
3482 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3485 if (PPCSubTarget.isSVR4ABI()) {
3486 if (PPCSubTarget.isPPC64())
3487 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3488 isTailCall, Outs, OutVals, Ins,
3491 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3492 isTailCall, Outs, OutVals, Ins,
3496 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
3497 isTailCall, Outs, OutVals, Ins,
3502 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
3503 CallingConv::ID CallConv, bool isVarArg,
3505 const SmallVectorImpl<ISD::OutputArg> &Outs,
3506 const SmallVectorImpl<SDValue> &OutVals,
3507 const SmallVectorImpl<ISD::InputArg> &Ins,
3508 DebugLoc dl, SelectionDAG &DAG,
3509 SmallVectorImpl<SDValue> &InVals) const {
3510 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
3511 // of the 32-bit SVR4 ABI stack frame layout.
3513 assert((CallConv == CallingConv::C ||
3514 CallConv == CallingConv::Fast) && "Unknown calling convention!");
3516 unsigned PtrByteSize = 4;
3518 MachineFunction &MF = DAG.getMachineFunction();
3520 // Mark this function as potentially containing a function that contains a
3521 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3522 // and restoring the callers stack pointer in this functions epilog. This is
3523 // done because by tail calling the called function might overwrite the value
3524 // in this function's (MF) stack pointer stack slot 0(SP).
3525 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3526 CallConv == CallingConv::Fast)
3527 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3529 // Count how many bytes are to be pushed on the stack, including the linkage
3530 // area, parameter list area and the part of the local variable space which
3531 // contains copies of aggregates which are passed by value.
3533 // Assign locations to all of the outgoing arguments.
3534 SmallVector<CCValAssign, 16> ArgLocs;
3535 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3536 getTargetMachine(), ArgLocs, *DAG.getContext());
3538 // Reserve space for the linkage area on the stack.
3539 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
3542 // Handle fixed and variable vector arguments differently.
3543 // Fixed vector arguments go into registers as long as registers are
3544 // available. Variable vector arguments always go into memory.
3545 unsigned NumArgs = Outs.size();
3547 for (unsigned i = 0; i != NumArgs; ++i) {
3548 MVT ArgVT = Outs[i].VT;
3549 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3552 if (Outs[i].IsFixed) {
3553 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
3556 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
3562 errs() << "Call operand #" << i << " has unhandled type "
3563 << EVT(ArgVT).getEVTString() << "\n";
3565 llvm_unreachable(0);
3569 // All arguments are treated the same.
3570 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
3573 // Assign locations to all of the outgoing aggregate by value arguments.
3574 SmallVector<CCValAssign, 16> ByValArgLocs;
3575 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3576 getTargetMachine(), ByValArgLocs, *DAG.getContext());
3578 // Reserve stack space for the allocations in CCInfo.
3579 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
3581 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
3583 // Size of the linkage area, parameter list area and the part of the local
3584 // space variable where copies of aggregates which are passed by value are
3586 unsigned NumBytes = CCByValInfo.getNextStackOffset();
3588 // Calculate by how many bytes the stack has to be adjusted in case of tail
3589 // call optimization.
3590 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3592 // Adjust the stack pointer for the new arguments...
3593 // These operations are automatically eliminated by the prolog/epilog pass
3594 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
3595 SDValue CallSeqStart = Chain;
3597 // Load the return address and frame pointer so it can be moved somewhere else
3600 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
3603 // Set up a copy of the stack pointer for use loading and storing any
3604 // arguments that may not fit in the registers available for argument
3606 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3608 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3609 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3610 SmallVector<SDValue, 8> MemOpChains;
3612 bool seenFloatArg = false;
3613 // Walk the register/memloc assignments, inserting copies/loads.
3614 for (unsigned i = 0, j = 0, e = ArgLocs.size();
3617 CCValAssign &VA = ArgLocs[i];
3618 SDValue Arg = OutVals[i];
3619 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3621 if (Flags.isByVal()) {
3622 // Argument is an aggregate which is passed by value, thus we need to
3623 // create a copy of it in the local variable space of the current stack
3624 // frame (which is the stack frame of the caller) and pass the address of
3625 // this copy to the callee.
3626 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
3627 CCValAssign &ByValVA = ByValArgLocs[j++];
3628 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
3630 // Memory reserved in the local variable space of the callers stack frame.
3631 unsigned LocMemOffset = ByValVA.getLocMemOffset();
3633 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3634 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3636 // Create a copy of the argument in the local area of the current
3638 SDValue MemcpyCall =
3639 CreateCopyOfByValArgument(Arg, PtrOff,
3640 CallSeqStart.getNode()->getOperand(0),
3643 // This must go outside the CALLSEQ_START..END.
3644 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3645 CallSeqStart.getNode()->getOperand(1));
3646 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3647 NewCallSeqStart.getNode());
3648 Chain = CallSeqStart = NewCallSeqStart;
3650 // Pass the address of the aggregate copy on the stack either in a
3651 // physical register or in the parameter list area of the current stack
3652 // frame to the callee.
3656 if (VA.isRegLoc()) {
3657 seenFloatArg |= VA.getLocVT().isFloatingPoint();
3658 // Put argument in a physical register.
3659 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3661 // Put argument in the parameter list area of the current stack frame.
3662 assert(VA.isMemLoc());
3663 unsigned LocMemOffset = VA.getLocMemOffset();
3666 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3667 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3669 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3670 MachinePointerInfo(),
3673 // Calculate and remember argument location.
3674 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
3680 if (!MemOpChains.empty())
3681 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3682 &MemOpChains[0], MemOpChains.size());
3684 // Build a sequence of copy-to-reg nodes chained together with token chain
3685 // and flag operands which copy the outgoing args into the appropriate regs.
3687 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3688 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3689 RegsToPass[i].second, InFlag);
3690 InFlag = Chain.getValue(1);
3693 // Set CR bit 6 to true if this is a vararg call with floating args passed in
3696 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3697 SDValue Ops[] = { Chain, InFlag };
3699 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
3700 dl, VTs, Ops, InFlag.getNode() ? 2 : 1);
3702 InFlag = Chain.getValue(1);
3706 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
3707 false, TailCallArguments);
3709 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3710 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3714 // Copy an argument into memory, being careful to do this outside the
3715 // call sequence for the call to which the argument belongs.
3717 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
3718 SDValue CallSeqStart,
3719 ISD::ArgFlagsTy Flags,
3721 DebugLoc dl) const {
3722 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
3723 CallSeqStart.getNode()->getOperand(0),
3725 // The MEMCPY must go outside the CALLSEQ_START..END.
3726 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3727 CallSeqStart.getNode()->getOperand(1));
3728 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3729 NewCallSeqStart.getNode());
3730 return NewCallSeqStart;
3734 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
3735 CallingConv::ID CallConv, bool isVarArg,
3737 const SmallVectorImpl<ISD::OutputArg> &Outs,
3738 const SmallVectorImpl<SDValue> &OutVals,
3739 const SmallVectorImpl<ISD::InputArg> &Ins,
3740 DebugLoc dl, SelectionDAG &DAG,
3741 SmallVectorImpl<SDValue> &InVals) const {
3743 unsigned NumOps = Outs.size();
3745 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3746 unsigned PtrByteSize = 8;
3748 MachineFunction &MF = DAG.getMachineFunction();
3750 // Mark this function as potentially containing a function that contains a
3751 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3752 // and restoring the callers stack pointer in this functions epilog. This is
3753 // done because by tail calling the called function might overwrite the value
3754 // in this function's (MF) stack pointer stack slot 0(SP).
3755 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3756 CallConv == CallingConv::Fast)
3757 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3759 unsigned nAltivecParamsAtEnd = 0;
3761 // Count how many bytes are to be pushed on the stack, including the linkage
3762 // area, and parameter passing area. We start with at least 48 bytes, which
3763 // is reserved space for [SP][CR][LR][3 x unused].
3764 // NOTE: For PPC64, nAltivecParamsAtEnd always remains zero as a result
3767 CalculateParameterAndLinkageAreaSize(DAG, true, isVarArg, CallConv,
3768 Outs, OutVals, nAltivecParamsAtEnd);
3770 // Calculate by how many bytes the stack has to be adjusted in case of tail
3771 // call optimization.
3772 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3774 // To protect arguments on the stack from being clobbered in a tail call,
3775 // force all the loads to happen before doing any other lowering.
3777 Chain = DAG.getStackArgumentTokenFactor(Chain);
3779 // Adjust the stack pointer for the new arguments...
3780 // These operations are automatically eliminated by the prolog/epilog pass
3781 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
3782 SDValue CallSeqStart = Chain;
3784 // Load the return address and frame pointer so it can be move somewhere else
3787 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
3790 // Set up a copy of the stack pointer for use loading and storing any
3791 // arguments that may not fit in the registers available for argument
3793 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3795 // Figure out which arguments are going to go in registers, and which in
3796 // memory. Also, if this is a vararg function, floating point operations
3797 // must be stored to our stack, and loaded into integer regs as well, if
3798 // any integer regs are available for argument passing.
3799 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
3800 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3802 static const uint16_t GPR[] = {
3803 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3804 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3806 static const uint16_t *FPR = GetFPR();
3808 static const uint16_t VR[] = {
3809 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3810 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3812 const unsigned NumGPRs = array_lengthof(GPR);
3813 const unsigned NumFPRs = 13;
3814 const unsigned NumVRs = array_lengthof(VR);
3816 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3817 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3819 SmallVector<SDValue, 8> MemOpChains;
3820 for (unsigned i = 0; i != NumOps; ++i) {
3821 SDValue Arg = OutVals[i];
3822 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3824 // PtrOff will be used to store the current argument to the stack if a
3825 // register cannot be found for it.
3828 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
3830 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
3832 // Promote integers to 64-bit values.
3833 if (Arg.getValueType() == MVT::i32) {
3834 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
3835 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3836 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
3839 // FIXME memcpy is used way more than necessary. Correctness first.
3840 // Note: "by value" is code for passing a structure by value, not
3842 if (Flags.isByVal()) {
3843 // Note: Size includes alignment padding, so
3844 // struct x { short a; char b; }
3845 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
3846 // These are the proper values we need for right-justifying the
3847 // aggregate in a parameter register.
3848 unsigned Size = Flags.getByValSize();
3850 // An empty aggregate parameter takes up no storage and no
3855 // All aggregates smaller than 8 bytes must be passed right-justified.
3856 if (Size==1 || Size==2 || Size==4) {
3857 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
3858 if (GPR_idx != NumGPRs) {
3859 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
3860 MachinePointerInfo(), VT,
3862 MemOpChains.push_back(Load.getValue(1));
3863 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3865 ArgOffset += PtrByteSize;
3870 if (GPR_idx == NumGPRs && Size < 8) {
3871 SDValue Const = DAG.getConstant(PtrByteSize - Size,
3872 PtrOff.getValueType());
3873 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3874 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
3877 ArgOffset += PtrByteSize;
3880 // Copy entire object into memory. There are cases where gcc-generated
3881 // code assumes it is there, even if it could be put entirely into
3882 // registers. (This is not what the doc says.)
3884 // FIXME: The above statement is likely due to a misunderstanding of the
3885 // documents. All arguments must be copied into the parameter area BY
3886 // THE CALLEE in the event that the callee takes the address of any
3887 // formal argument. That has not yet been implemented. However, it is
3888 // reasonable to use the stack area as a staging area for the register
3891 // Skip this for small aggregates, as we will use the same slot for a
3892 // right-justified copy, below.
3894 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
3898 // When a register is available, pass a small aggregate right-justified.
3899 if (Size < 8 && GPR_idx != NumGPRs) {
3900 // The easiest way to get this right-justified in a register
3901 // is to copy the structure into the rightmost portion of a
3902 // local variable slot, then load the whole slot into the
3904 // FIXME: The memcpy seems to produce pretty awful code for
3905 // small aggregates, particularly for packed ones.
3906 // FIXME: It would be preferable to use the slot in the
3907 // parameter save area instead of a new local variable.
3908 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
3909 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3910 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
3914 // Load the slot into the register.
3915 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
3916 MachinePointerInfo(),
3917 false, false, false, 0);
3918 MemOpChains.push_back(Load.getValue(1));
3919 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3921 // Done with this argument.
3922 ArgOffset += PtrByteSize;
3926 // For aggregates larger than PtrByteSize, copy the pieces of the
3927 // object that fit into registers from the parameter save area.
3928 for (unsigned j=0; j<Size; j+=PtrByteSize) {
3929 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
3930 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
3931 if (GPR_idx != NumGPRs) {
3932 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
3933 MachinePointerInfo(),
3934 false, false, false, 0);
3935 MemOpChains.push_back(Load.getValue(1));
3936 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3937 ArgOffset += PtrByteSize;
3939 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
3946 switch (Arg.getValueType().getSimpleVT().SimpleTy) {
3947 default: llvm_unreachable("Unexpected ValueType for argument!");
3950 if (GPR_idx != NumGPRs) {
3951 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
3953 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3954 true, isTailCall, false, MemOpChains,
3955 TailCallArguments, dl);
3957 ArgOffset += PtrByteSize;
3961 if (FPR_idx != NumFPRs) {
3962 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
3965 // A single float or an aggregate containing only a single float
3966 // must be passed right-justified in the stack doubleword, and
3967 // in the GPR, if one is available.
3969 if (Arg.getValueType().getSimpleVT().SimpleTy == MVT::f32) {
3970 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
3971 StoreOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
3975 SDValue Store = DAG.getStore(Chain, dl, Arg, StoreOff,
3976 MachinePointerInfo(), false, false, 0);
3977 MemOpChains.push_back(Store);
3979 // Float varargs are always shadowed in available integer registers
3980 if (GPR_idx != NumGPRs) {
3981 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
3982 MachinePointerInfo(), false, false,
3984 MemOpChains.push_back(Load.getValue(1));
3985 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3987 } else if (GPR_idx != NumGPRs)
3988 // If we have any FPRs remaining, we may also have GPRs remaining.
3991 // Single-precision floating-point values are mapped to the
3992 // second (rightmost) word of the stack doubleword.
3993 if (Arg.getValueType() == MVT::f32) {
3994 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
3995 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
3998 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3999 true, isTailCall, false, MemOpChains,
4000 TailCallArguments, dl);
4009 // These go aligned on the stack, or in the corresponding R registers
4010 // when within range. The Darwin PPC ABI doc claims they also go in
4011 // V registers; in fact gcc does this only for arguments that are
4012 // prototyped, not for those that match the ... We do it for all
4013 // arguments, seems to work.
4014 while (ArgOffset % 16 !=0) {
4015 ArgOffset += PtrByteSize;
4016 if (GPR_idx != NumGPRs)
4019 // We could elide this store in the case where the object fits
4020 // entirely in R registers. Maybe later.
4021 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4022 DAG.getConstant(ArgOffset, PtrVT));
4023 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4024 MachinePointerInfo(), false, false, 0);
4025 MemOpChains.push_back(Store);
4026 if (VR_idx != NumVRs) {
4027 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4028 MachinePointerInfo(),
4029 false, false, false, 0);
4030 MemOpChains.push_back(Load.getValue(1));
4031 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4034 for (unsigned i=0; i<16; i+=PtrByteSize) {
4035 if (GPR_idx == NumGPRs)
4037 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4038 DAG.getConstant(i, PtrVT));
4039 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4040 false, false, false, 0);
4041 MemOpChains.push_back(Load.getValue(1));
4042 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4047 // Non-varargs Altivec params generally go in registers, but have
4048 // stack space allocated at the end.
4049 if (VR_idx != NumVRs) {
4050 // Doesn't have GPR space allocated.
4051 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4053 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4054 true, isTailCall, true, MemOpChains,
4055 TailCallArguments, dl);
4062 if (!MemOpChains.empty())
4063 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4064 &MemOpChains[0], MemOpChains.size());
4066 // Check if this is an indirect call (MTCTR/BCTRL).
4067 // See PrepareCall() for more information about calls through function
4068 // pointers in the 64-bit SVR4 ABI.
4070 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4071 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4072 !isBLACompatibleAddress(Callee, DAG)) {
4073 // Load r2 into a virtual register and store it to the TOC save area.
4074 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4075 // TOC save area offset.
4076 SDValue PtrOff = DAG.getIntPtrConstant(40);
4077 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4078 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
4080 // R12 must contain the address of an indirect callee. This does not
4081 // mean the MTCTR instruction must use R12; it's easier to model this
4082 // as an extra parameter, so do that.
4083 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
4086 // Build a sequence of copy-to-reg nodes chained together with token chain
4087 // and flag operands which copy the outgoing args into the appropriate regs.
4089 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4090 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4091 RegsToPass[i].second, InFlag);
4092 InFlag = Chain.getValue(1);
4096 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4097 FPOp, true, TailCallArguments);
4099 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4100 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4105 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4106 CallingConv::ID CallConv, bool isVarArg,
4108 const SmallVectorImpl<ISD::OutputArg> &Outs,
4109 const SmallVectorImpl<SDValue> &OutVals,
4110 const SmallVectorImpl<ISD::InputArg> &Ins,
4111 DebugLoc dl, SelectionDAG &DAG,
4112 SmallVectorImpl<SDValue> &InVals) const {
4114 unsigned NumOps = Outs.size();
4116 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4117 bool isPPC64 = PtrVT == MVT::i64;
4118 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4120 MachineFunction &MF = DAG.getMachineFunction();
4122 // Mark this function as potentially containing a function that contains a
4123 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4124 // and restoring the callers stack pointer in this functions epilog. This is
4125 // done because by tail calling the called function might overwrite the value
4126 // in this function's (MF) stack pointer stack slot 0(SP).
4127 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4128 CallConv == CallingConv::Fast)
4129 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4131 unsigned nAltivecParamsAtEnd = 0;
4133 // Count how many bytes are to be pushed on the stack, including the linkage
4134 // area, and parameter passing area. We start with 24/48 bytes, which is
4135 // prereserved space for [SP][CR][LR][3 x unused].
4137 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv,
4139 nAltivecParamsAtEnd);
4141 // Calculate by how many bytes the stack has to be adjusted in case of tail
4142 // call optimization.
4143 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4145 // To protect arguments on the stack from being clobbered in a tail call,
4146 // force all the loads to happen before doing any other lowering.
4148 Chain = DAG.getStackArgumentTokenFactor(Chain);
4150 // Adjust the stack pointer for the new arguments...
4151 // These operations are automatically eliminated by the prolog/epilog pass
4152 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
4153 SDValue CallSeqStart = Chain;
4155 // Load the return address and frame pointer so it can be move somewhere else
4158 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4161 // Set up a copy of the stack pointer for use loading and storing any
4162 // arguments that may not fit in the registers available for argument
4166 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4168 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4170 // Figure out which arguments are going to go in registers, and which in
4171 // memory. Also, if this is a vararg function, floating point operations
4172 // must be stored to our stack, and loaded into integer regs as well, if
4173 // any integer regs are available for argument passing.
4174 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
4175 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4177 static const uint16_t GPR_32[] = { // 32-bit registers.
4178 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4179 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4181 static const uint16_t GPR_64[] = { // 64-bit registers.
4182 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4183 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4185 static const uint16_t *FPR = GetFPR();
4187 static const uint16_t VR[] = {
4188 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4189 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4191 const unsigned NumGPRs = array_lengthof(GPR_32);
4192 const unsigned NumFPRs = 13;
4193 const unsigned NumVRs = array_lengthof(VR);
4195 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
4197 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4198 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4200 SmallVector<SDValue, 8> MemOpChains;
4201 for (unsigned i = 0; i != NumOps; ++i) {
4202 SDValue Arg = OutVals[i];
4203 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4205 // PtrOff will be used to store the current argument to the stack if a
4206 // register cannot be found for it.
4209 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4211 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4213 // On PPC64, promote integers to 64-bit values.
4214 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4215 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4216 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4217 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4220 // FIXME memcpy is used way more than necessary. Correctness first.
4221 // Note: "by value" is code for passing a structure by value, not
4223 if (Flags.isByVal()) {
4224 unsigned Size = Flags.getByValSize();
4225 // Very small objects are passed right-justified. Everything else is
4226 // passed left-justified.
4227 if (Size==1 || Size==2) {
4228 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4229 if (GPR_idx != NumGPRs) {
4230 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4231 MachinePointerInfo(), VT,
4233 MemOpChains.push_back(Load.getValue(1));
4234 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4236 ArgOffset += PtrByteSize;
4238 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4239 PtrOff.getValueType());
4240 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4241 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4244 ArgOffset += PtrByteSize;
4248 // Copy entire object into memory. There are cases where gcc-generated
4249 // code assumes it is there, even if it could be put entirely into
4250 // registers. (This is not what the doc says.)
4251 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4255 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4256 // copy the pieces of the object that fit into registers from the
4257 // parameter save area.
4258 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4259 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4260 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4261 if (GPR_idx != NumGPRs) {
4262 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4263 MachinePointerInfo(),
4264 false, false, false, 0);
4265 MemOpChains.push_back(Load.getValue(1));
4266 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4267 ArgOffset += PtrByteSize;
4269 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4276 switch (Arg.getValueType().getSimpleVT().SimpleTy) {
4277 default: llvm_unreachable("Unexpected ValueType for argument!");
4280 if (GPR_idx != NumGPRs) {
4281 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4283 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4284 isPPC64, isTailCall, false, MemOpChains,
4285 TailCallArguments, dl);
4287 ArgOffset += PtrByteSize;
4291 if (FPR_idx != NumFPRs) {
4292 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4295 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4296 MachinePointerInfo(), false, false, 0);
4297 MemOpChains.push_back(Store);
4299 // Float varargs are always shadowed in available integer registers
4300 if (GPR_idx != NumGPRs) {
4301 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4302 MachinePointerInfo(), false, false,
4304 MemOpChains.push_back(Load.getValue(1));
4305 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4307 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4308 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4309 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4310 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4311 MachinePointerInfo(),
4312 false, false, false, 0);
4313 MemOpChains.push_back(Load.getValue(1));
4314 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4317 // If we have any FPRs remaining, we may also have GPRs remaining.
4318 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4320 if (GPR_idx != NumGPRs)
4322 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4323 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4327 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4328 isPPC64, isTailCall, false, MemOpChains,
4329 TailCallArguments, dl);
4333 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4340 // These go aligned on the stack, or in the corresponding R registers
4341 // when within range. The Darwin PPC ABI doc claims they also go in
4342 // V registers; in fact gcc does this only for arguments that are
4343 // prototyped, not for those that match the ... We do it for all
4344 // arguments, seems to work.
4345 while (ArgOffset % 16 !=0) {
4346 ArgOffset += PtrByteSize;
4347 if (GPR_idx != NumGPRs)
4350 // We could elide this store in the case where the object fits
4351 // entirely in R registers. Maybe later.
4352 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4353 DAG.getConstant(ArgOffset, PtrVT));
4354 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4355 MachinePointerInfo(), false, false, 0);
4356 MemOpChains.push_back(Store);
4357 if (VR_idx != NumVRs) {
4358 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4359 MachinePointerInfo(),
4360 false, false, false, 0);
4361 MemOpChains.push_back(Load.getValue(1));
4362 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4365 for (unsigned i=0; i<16; i+=PtrByteSize) {
4366 if (GPR_idx == NumGPRs)
4368 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4369 DAG.getConstant(i, PtrVT));
4370 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4371 false, false, false, 0);
4372 MemOpChains.push_back(Load.getValue(1));
4373 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4378 // Non-varargs Altivec params generally go in registers, but have
4379 // stack space allocated at the end.
4380 if (VR_idx != NumVRs) {
4381 // Doesn't have GPR space allocated.
4382 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4383 } else if (nAltivecParamsAtEnd==0) {
4384 // We are emitting Altivec params in order.
4385 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4386 isPPC64, isTailCall, true, MemOpChains,
4387 TailCallArguments, dl);
4393 // If all Altivec parameters fit in registers, as they usually do,
4394 // they get stack space following the non-Altivec parameters. We
4395 // don't track this here because nobody below needs it.
4396 // If there are more Altivec parameters than fit in registers emit
4398 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
4400 // Offset is aligned; skip 1st 12 params which go in V registers.
4401 ArgOffset = ((ArgOffset+15)/16)*16;
4403 for (unsigned i = 0; i != NumOps; ++i) {
4404 SDValue Arg = OutVals[i];
4405 EVT ArgType = Outs[i].VT;
4406 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
4407 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
4410 // We are emitting Altivec params in order.
4411 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4412 isPPC64, isTailCall, true, MemOpChains,
4413 TailCallArguments, dl);
4420 if (!MemOpChains.empty())
4421 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4422 &MemOpChains[0], MemOpChains.size());
4424 // On Darwin, R12 must contain the address of an indirect callee. This does
4425 // not mean the MTCTR instruction must use R12; it's easier to model this as
4426 // an extra parameter, so do that.
4428 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4429 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4430 !isBLACompatibleAddress(Callee, DAG))
4431 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
4432 PPC::R12), Callee));
4434 // Build a sequence of copy-to-reg nodes chained together with token chain
4435 // and flag operands which copy the outgoing args into the appropriate regs.
4437 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4438 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4439 RegsToPass[i].second, InFlag);
4440 InFlag = Chain.getValue(1);
4444 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
4445 FPOp, true, TailCallArguments);
4447 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4448 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4453 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
4454 MachineFunction &MF, bool isVarArg,
4455 const SmallVectorImpl<ISD::OutputArg> &Outs,
4456 LLVMContext &Context) const {
4457 SmallVector<CCValAssign, 16> RVLocs;
4458 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
4460 return CCInfo.CheckReturn(Outs, RetCC_PPC);
4464 PPCTargetLowering::LowerReturn(SDValue Chain,
4465 CallingConv::ID CallConv, bool isVarArg,
4466 const SmallVectorImpl<ISD::OutputArg> &Outs,
4467 const SmallVectorImpl<SDValue> &OutVals,
4468 DebugLoc dl, SelectionDAG &DAG) const {
4470 SmallVector<CCValAssign, 16> RVLocs;
4471 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4472 getTargetMachine(), RVLocs, *DAG.getContext());
4473 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
4476 SmallVector<SDValue, 4> RetOps(1, Chain);
4478 // Copy the result values into the output registers.
4479 for (unsigned i = 0; i != RVLocs.size(); ++i) {
4480 CCValAssign &VA = RVLocs[i];
4481 assert(VA.isRegLoc() && "Can only return in registers!");
4483 SDValue Arg = OutVals[i];
4485 switch (VA.getLocInfo()) {
4486 default: llvm_unreachable("Unknown loc info!");
4487 case CCValAssign::Full: break;
4488 case CCValAssign::AExt:
4489 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
4491 case CCValAssign::ZExt:
4492 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
4494 case CCValAssign::SExt:
4495 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
4499 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
4500 Flag = Chain.getValue(1);
4501 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
4504 RetOps[0] = Chain; // Update chain.
4506 // Add the flag if we have it.
4508 RetOps.push_back(Flag);
4510 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other,
4511 &RetOps[0], RetOps.size());
4514 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
4515 const PPCSubtarget &Subtarget) const {
4516 // When we pop the dynamic allocation we need to restore the SP link.
4517 DebugLoc dl = Op.getDebugLoc();
4519 // Get the corect type for pointers.
4520 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4522 // Construct the stack pointer operand.
4523 bool isPPC64 = Subtarget.isPPC64();
4524 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
4525 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
4527 // Get the operands for the STACKRESTORE.
4528 SDValue Chain = Op.getOperand(0);
4529 SDValue SaveSP = Op.getOperand(1);
4531 // Load the old link SP.
4532 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
4533 MachinePointerInfo(),
4534 false, false, false, 0);
4536 // Restore the stack pointer.
4537 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
4539 // Store the old link SP.
4540 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
4547 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
4548 MachineFunction &MF = DAG.getMachineFunction();
4549 bool isPPC64 = PPCSubTarget.isPPC64();
4550 bool isDarwinABI = PPCSubTarget.isDarwinABI();
4551 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4553 // Get current frame pointer save index. The users of this index will be
4554 // primarily DYNALLOC instructions.
4555 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4556 int RASI = FI->getReturnAddrSaveIndex();
4558 // If the frame pointer save index hasn't been defined yet.
4560 // Find out what the fix offset of the frame pointer save area.
4561 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
4562 // Allocate the frame index for frame pointer save area.
4563 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
4565 FI->setReturnAddrSaveIndex(RASI);
4567 return DAG.getFrameIndex(RASI, PtrVT);
4571 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
4572 MachineFunction &MF = DAG.getMachineFunction();
4573 bool isPPC64 = PPCSubTarget.isPPC64();
4574 bool isDarwinABI = PPCSubTarget.isDarwinABI();
4575 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4577 // Get current frame pointer save index. The users of this index will be
4578 // primarily DYNALLOC instructions.
4579 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4580 int FPSI = FI->getFramePointerSaveIndex();
4582 // If the frame pointer save index hasn't been defined yet.
4584 // Find out what the fix offset of the frame pointer save area.
4585 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
4588 // Allocate the frame index for frame pointer save area.
4589 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
4591 FI->setFramePointerSaveIndex(FPSI);
4593 return DAG.getFrameIndex(FPSI, PtrVT);
4596 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
4598 const PPCSubtarget &Subtarget) const {
4600 SDValue Chain = Op.getOperand(0);
4601 SDValue Size = Op.getOperand(1);
4602 DebugLoc dl = Op.getDebugLoc();
4604 // Get the corect type for pointers.
4605 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4607 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
4608 DAG.getConstant(0, PtrVT), Size);
4609 // Construct a node for the frame pointer save index.
4610 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
4611 // Build a DYNALLOC node.
4612 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
4613 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
4614 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3);
4617 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
4618 SelectionDAG &DAG) const {
4619 DebugLoc DL = Op.getDebugLoc();
4620 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
4621 DAG.getVTList(MVT::i32, MVT::Other),
4622 Op.getOperand(0), Op.getOperand(1));
4625 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
4626 SelectionDAG &DAG) const {
4627 DebugLoc DL = Op.getDebugLoc();
4628 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
4629 Op.getOperand(0), Op.getOperand(1));
4632 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
4634 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
4635 // Not FP? Not a fsel.
4636 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
4637 !Op.getOperand(2).getValueType().isFloatingPoint())
4640 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4642 // Cannot handle SETEQ/SETNE.
4643 if (CC == ISD::SETEQ || CC == ISD::SETNE) return Op;
4645 EVT ResVT = Op.getValueType();
4646 EVT CmpVT = Op.getOperand(0).getValueType();
4647 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4648 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
4649 DebugLoc dl = Op.getDebugLoc();
4651 // If the RHS of the comparison is a 0.0, we don't need to do the
4652 // subtraction at all.
4653 if (isFloatingPointZero(RHS))
4655 default: break; // SETUO etc aren't handled by fsel.
4658 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
4661 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4662 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4663 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
4666 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
4669 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4670 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4671 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4672 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
4677 default: break; // SETUO etc aren't handled by fsel.
4680 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4681 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4682 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4683 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
4686 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4687 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4688 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4689 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4692 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
4693 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4694 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4695 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
4698 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
4699 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4700 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4701 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4706 // FIXME: Split this code up when LegalizeDAGTypes lands.
4707 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
4708 DebugLoc dl) const {
4709 assert(Op.getOperand(0).getValueType().isFloatingPoint());
4710 SDValue Src = Op.getOperand(0);
4711 if (Src.getValueType() == MVT::f32)
4712 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
4715 switch (Op.getValueType().getSimpleVT().SimpleTy) {
4716 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
4718 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
4723 Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src);
4727 // Convert the FP value to an int value through memory.
4728 SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64);
4730 // Emit a store to the stack slot.
4731 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
4732 MachinePointerInfo(), false, false, 0);
4734 // Result is a load from the stack slot. If loading 4 bytes, make sure to
4736 if (Op.getValueType() == MVT::i32)
4737 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
4738 DAG.getConstant(4, FIPtr.getValueType()));
4739 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MachinePointerInfo(),
4740 false, false, false, 0);
4743 SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op,
4744 SelectionDAG &DAG) const {
4745 DebugLoc dl = Op.getDebugLoc();
4746 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
4747 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
4750 if (Op.getOperand(0).getValueType() == MVT::i64) {
4751 SDValue SINT = Op.getOperand(0);
4752 // When converting to single-precision, we actually need to convert
4753 // to double-precision first and then round to single-precision.
4754 // To avoid double-rounding effects during that operation, we have
4755 // to prepare the input operand. Bits that might be truncated when
4756 // converting to double-precision are replaced by a bit that won't
4757 // be lost at this stage, but is below the single-precision rounding
4760 // However, if -enable-unsafe-fp-math is in effect, accept double
4761 // rounding to avoid the extra overhead.
4762 if (Op.getValueType() == MVT::f32 &&
4763 !DAG.getTarget().Options.UnsafeFPMath) {
4765 // Twiddle input to make sure the low 11 bits are zero. (If this
4766 // is the case, we are guaranteed the value will fit into the 53 bit
4767 // mantissa of an IEEE double-precision value without rounding.)
4768 // If any of those low 11 bits were not zero originally, make sure
4769 // bit 12 (value 2048) is set instead, so that the final rounding
4770 // to single-precision gets the correct result.
4771 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
4772 SINT, DAG.getConstant(2047, MVT::i64));
4773 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
4774 Round, DAG.getConstant(2047, MVT::i64));
4775 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
4776 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
4777 Round, DAG.getConstant(-2048, MVT::i64));
4779 // However, we cannot use that value unconditionally: if the magnitude
4780 // of the input value is small, the bit-twiddling we did above might
4781 // end up visibly changing the output. Fortunately, in that case, we
4782 // don't need to twiddle bits since the original input will convert
4783 // exactly to double-precision floating-point already. Therefore,
4784 // construct a conditional to use the original value if the top 11
4785 // bits are all sign-bit copies, and use the rounded value computed
4787 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
4788 SINT, DAG.getConstant(53, MVT::i32));
4789 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
4790 Cond, DAG.getConstant(1, MVT::i64));
4791 Cond = DAG.getSetCC(dl, MVT::i32,
4792 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
4794 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
4796 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
4797 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits);
4798 if (Op.getValueType() == MVT::f32)
4799 FP = DAG.getNode(ISD::FP_ROUND, dl,
4800 MVT::f32, FP, DAG.getIntPtrConstant(0));
4804 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
4805 "Unhandled SINT_TO_FP type in custom expander!");
4806 // Since we only generate this in 64-bit mode, we can take advantage of
4807 // 64-bit registers. In particular, sign extend the input value into the
4808 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
4809 // then lfd it and fcfid it.
4810 MachineFunction &MF = DAG.getMachineFunction();
4811 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
4812 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4815 if (PPCSubTarget.hasLFIWAX()) {
4816 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
4817 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4819 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
4820 MachinePointerInfo::getFixedStack(FrameIdx),
4823 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
4824 "Expected an i32 store");
4825 MachineMemOperand *MMO =
4826 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
4827 MachineMemOperand::MOLoad, 4, 4);
4828 SDValue Ops[] = { Store, FIdx };
4829 Ld = DAG.getMemIntrinsicNode(PPCISD::LFIWAX, dl,
4830 DAG.getVTList(MVT::f64, MVT::Other), Ops, 2,
4833 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
4834 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4836 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
4839 // STD the extended value into the stack slot.
4840 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
4841 MachinePointerInfo::getFixedStack(FrameIdx),
4844 // Load the value as a double.
4845 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
4846 MachinePointerInfo::getFixedStack(FrameIdx),
4847 false, false, false, 0);
4850 // FCFID it and return it.
4851 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld);
4852 if (Op.getValueType() == MVT::f32)
4853 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
4857 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
4858 SelectionDAG &DAG) const {
4859 DebugLoc dl = Op.getDebugLoc();
4861 The rounding mode is in bits 30:31 of FPSR, and has the following
4868 FLT_ROUNDS, on the other hand, expects the following:
4875 To perform the conversion, we do:
4876 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
4879 MachineFunction &MF = DAG.getMachineFunction();
4880 EVT VT = Op.getValueType();
4881 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4882 SDValue MFFSreg, InFlag;
4884 // Save FP Control Word to register
4886 MVT::f64, // return register
4887 MVT::Glue // unused in this context
4889 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
4891 // Save FP register to stack slot
4892 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
4893 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
4894 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
4895 StackSlot, MachinePointerInfo(), false, false,0);
4897 // Load FP Control Word from low 32 bits of stack slot.
4898 SDValue Four = DAG.getConstant(4, PtrVT);
4899 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
4900 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
4901 false, false, false, 0);
4903 // Transform as necessary
4905 DAG.getNode(ISD::AND, dl, MVT::i32,
4906 CWD, DAG.getConstant(3, MVT::i32));
4908 DAG.getNode(ISD::SRL, dl, MVT::i32,
4909 DAG.getNode(ISD::AND, dl, MVT::i32,
4910 DAG.getNode(ISD::XOR, dl, MVT::i32,
4911 CWD, DAG.getConstant(3, MVT::i32)),
4912 DAG.getConstant(3, MVT::i32)),
4913 DAG.getConstant(1, MVT::i32));
4916 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
4918 return DAG.getNode((VT.getSizeInBits() < 16 ?
4919 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
4922 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
4923 EVT VT = Op.getValueType();
4924 unsigned BitWidth = VT.getSizeInBits();
4925 DebugLoc dl = Op.getDebugLoc();
4926 assert(Op.getNumOperands() == 3 &&
4927 VT == Op.getOperand(1).getValueType() &&
4930 // Expand into a bunch of logical ops. Note that these ops
4931 // depend on the PPC behavior for oversized shift amounts.
4932 SDValue Lo = Op.getOperand(0);
4933 SDValue Hi = Op.getOperand(1);
4934 SDValue Amt = Op.getOperand(2);
4935 EVT AmtVT = Amt.getValueType();
4937 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
4938 DAG.getConstant(BitWidth, AmtVT), Amt);
4939 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
4940 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
4941 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
4942 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
4943 DAG.getConstant(-BitWidth, AmtVT));
4944 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
4945 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
4946 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
4947 SDValue OutOps[] = { OutLo, OutHi };
4948 return DAG.getMergeValues(OutOps, 2, dl);
4951 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
4952 EVT VT = Op.getValueType();
4953 DebugLoc dl = Op.getDebugLoc();
4954 unsigned BitWidth = VT.getSizeInBits();
4955 assert(Op.getNumOperands() == 3 &&
4956 VT == Op.getOperand(1).getValueType() &&
4959 // Expand into a bunch of logical ops. Note that these ops
4960 // depend on the PPC behavior for oversized shift amounts.
4961 SDValue Lo = Op.getOperand(0);
4962 SDValue Hi = Op.getOperand(1);
4963 SDValue Amt = Op.getOperand(2);
4964 EVT AmtVT = Amt.getValueType();
4966 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
4967 DAG.getConstant(BitWidth, AmtVT), Amt);
4968 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
4969 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
4970 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
4971 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
4972 DAG.getConstant(-BitWidth, AmtVT));
4973 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
4974 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
4975 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
4976 SDValue OutOps[] = { OutLo, OutHi };
4977 return DAG.getMergeValues(OutOps, 2, dl);
4980 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
4981 DebugLoc dl = Op.getDebugLoc();
4982 EVT VT = Op.getValueType();
4983 unsigned BitWidth = VT.getSizeInBits();
4984 assert(Op.getNumOperands() == 3 &&
4985 VT == Op.getOperand(1).getValueType() &&
4988 // Expand into a bunch of logical ops, followed by a select_cc.
4989 SDValue Lo = Op.getOperand(0);
4990 SDValue Hi = Op.getOperand(1);
4991 SDValue Amt = Op.getOperand(2);
4992 EVT AmtVT = Amt.getValueType();
4994 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
4995 DAG.getConstant(BitWidth, AmtVT), Amt);
4996 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
4997 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
4998 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
4999 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5000 DAG.getConstant(-BitWidth, AmtVT));
5001 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
5002 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
5003 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
5004 Tmp4, Tmp6, ISD::SETLE);
5005 SDValue OutOps[] = { OutLo, OutHi };
5006 return DAG.getMergeValues(OutOps, 2, dl);
5009 //===----------------------------------------------------------------------===//
5010 // Vector related lowering.
5013 /// BuildSplatI - Build a canonical splati of Val with an element size of
5014 /// SplatSize. Cast the result to VT.
5015 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
5016 SelectionDAG &DAG, DebugLoc dl) {
5017 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
5019 static const EVT VTys[] = { // canonical VT to use for each size.
5020 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
5023 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
5025 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
5029 EVT CanonicalVT = VTys[SplatSize-1];
5031 // Build a canonical splat for this value.
5032 SDValue Elt = DAG.getConstant(Val, MVT::i32);
5033 SmallVector<SDValue, 8> Ops;
5034 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
5035 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
5036 &Ops[0], Ops.size());
5037 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
5040 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
5041 /// specified intrinsic ID.
5042 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
5043 SelectionDAG &DAG, DebugLoc dl,
5044 EVT DestVT = MVT::Other) {
5045 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
5046 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5047 DAG.getConstant(IID, MVT::i32), LHS, RHS);
5050 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
5051 /// specified intrinsic ID.
5052 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
5053 SDValue Op2, SelectionDAG &DAG,
5054 DebugLoc dl, EVT DestVT = MVT::Other) {
5055 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
5056 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5057 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
5061 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
5062 /// amount. The result has the specified value type.
5063 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
5064 EVT VT, SelectionDAG &DAG, DebugLoc dl) {
5065 // Force LHS/RHS to be the right type.
5066 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
5067 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
5070 for (unsigned i = 0; i != 16; ++i)
5072 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
5073 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5076 // If this is a case we can't handle, return null and let the default
5077 // expansion code take care of it. If we CAN select this case, and if it
5078 // selects to a single instruction, return Op. Otherwise, if we can codegen
5079 // this case more efficiently than a constant pool load, lower it to the
5080 // sequence of ops that should be used.
5081 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
5082 SelectionDAG &DAG) const {
5083 DebugLoc dl = Op.getDebugLoc();
5084 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5085 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
5087 // Check if this is a splat of a constant value.
5088 APInt APSplatBits, APSplatUndef;
5089 unsigned SplatBitSize;
5091 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
5092 HasAnyUndefs, 0, true) || SplatBitSize > 32)
5095 unsigned SplatBits = APSplatBits.getZExtValue();
5096 unsigned SplatUndef = APSplatUndef.getZExtValue();
5097 unsigned SplatSize = SplatBitSize / 8;
5099 // First, handle single instruction cases.
5102 if (SplatBits == 0) {
5103 // Canonicalize all zero vectors to be v4i32.
5104 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5105 SDValue Z = DAG.getConstant(0, MVT::i32);
5106 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5107 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
5112 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
5113 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
5115 if (SextVal >= -16 && SextVal <= 15)
5116 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
5119 // Two instruction sequences.
5121 // If this value is in the range [-32,30] and is even, use:
5122 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
5123 // If this value is in the range [17,31] and is odd, use:
5124 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
5125 // If this value is in the range [-31,-17] and is odd, use:
5126 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
5127 // Note the last two are three-instruction sequences.
5128 if (SextVal >= -32 && SextVal <= 31) {
5129 // To avoid having these optimizations undone by constant folding,
5130 // we convert to a pseudo that will be expanded later into one of
5132 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
5133 EVT VT = Op.getValueType();
5134 int Size = VT == MVT::v16i8 ? 1 : (VT == MVT::v8i16 ? 2 : 4);
5135 SDValue EltSize = DAG.getConstant(Size, MVT::i32);
5136 return DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
5139 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
5140 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
5142 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
5143 // Make -1 and vspltisw -1:
5144 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
5146 // Make the VSLW intrinsic, computing 0x8000_0000.
5147 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
5150 // xor by OnesV to invert it.
5151 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5152 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5155 // Check to see if this is a wide variety of vsplti*, binop self cases.
5156 static const signed char SplatCsts[] = {
5157 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
5158 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
5161 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
5162 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
5163 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
5164 int i = SplatCsts[idx];
5166 // Figure out what shift amount will be used by altivec if shifted by i in
5168 unsigned TypeShiftAmt = i & (SplatBitSize-1);
5170 // vsplti + shl self.
5171 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
5172 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5173 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5174 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
5175 Intrinsic::ppc_altivec_vslw
5177 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5178 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5181 // vsplti + srl self.
5182 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5183 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5184 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5185 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
5186 Intrinsic::ppc_altivec_vsrw
5188 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5189 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5192 // vsplti + sra self.
5193 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5194 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5195 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5196 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
5197 Intrinsic::ppc_altivec_vsraw
5199 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5200 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5203 // vsplti + rol self.
5204 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
5205 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
5206 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5207 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5208 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
5209 Intrinsic::ppc_altivec_vrlw
5211 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5212 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5215 // t = vsplti c, result = vsldoi t, t, 1
5216 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
5217 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5218 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
5220 // t = vsplti c, result = vsldoi t, t, 2
5221 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
5222 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5223 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
5225 // t = vsplti c, result = vsldoi t, t, 3
5226 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
5227 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5228 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
5235 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5236 /// the specified operations to build the shuffle.
5237 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5238 SDValue RHS, SelectionDAG &DAG,
5240 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5241 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5242 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5245 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5257 if (OpNum == OP_COPY) {
5258 if (LHSID == (1*9+2)*9+3) return LHS;
5259 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5263 SDValue OpLHS, OpRHS;
5264 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5265 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5269 default: llvm_unreachable("Unknown i32 permute!");
5271 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
5272 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
5273 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
5274 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
5277 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
5278 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
5279 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
5280 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
5283 for (unsigned i = 0; i != 16; ++i)
5284 ShufIdxs[i] = (i&3)+0;
5287 for (unsigned i = 0; i != 16; ++i)
5288 ShufIdxs[i] = (i&3)+4;
5291 for (unsigned i = 0; i != 16; ++i)
5292 ShufIdxs[i] = (i&3)+8;
5295 for (unsigned i = 0; i != 16; ++i)
5296 ShufIdxs[i] = (i&3)+12;
5299 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
5301 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
5303 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
5305 EVT VT = OpLHS.getValueType();
5306 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
5307 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
5308 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
5309 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5312 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
5313 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
5314 /// return the code it can be lowered into. Worst case, it can always be
5315 /// lowered into a vperm.
5316 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5317 SelectionDAG &DAG) const {
5318 DebugLoc dl = Op.getDebugLoc();
5319 SDValue V1 = Op.getOperand(0);
5320 SDValue V2 = Op.getOperand(1);
5321 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5322 EVT VT = Op.getValueType();
5324 // Cases that are handled by instructions that take permute immediates
5325 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
5326 // selected by the instruction selector.
5327 if (V2.getOpcode() == ISD::UNDEF) {
5328 if (PPC::isSplatShuffleMask(SVOp, 1) ||
5329 PPC::isSplatShuffleMask(SVOp, 2) ||
5330 PPC::isSplatShuffleMask(SVOp, 4) ||
5331 PPC::isVPKUWUMShuffleMask(SVOp, true) ||
5332 PPC::isVPKUHUMShuffleMask(SVOp, true) ||
5333 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 ||
5334 PPC::isVMRGLShuffleMask(SVOp, 1, true) ||
5335 PPC::isVMRGLShuffleMask(SVOp, 2, true) ||
5336 PPC::isVMRGLShuffleMask(SVOp, 4, true) ||
5337 PPC::isVMRGHShuffleMask(SVOp, 1, true) ||
5338 PPC::isVMRGHShuffleMask(SVOp, 2, true) ||
5339 PPC::isVMRGHShuffleMask(SVOp, 4, true)) {
5344 // Altivec has a variety of "shuffle immediates" that take two vector inputs
5345 // and produce a fixed permutation. If any of these match, do not lower to
5347 if (PPC::isVPKUWUMShuffleMask(SVOp, false) ||
5348 PPC::isVPKUHUMShuffleMask(SVOp, false) ||
5349 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 ||
5350 PPC::isVMRGLShuffleMask(SVOp, 1, false) ||
5351 PPC::isVMRGLShuffleMask(SVOp, 2, false) ||
5352 PPC::isVMRGLShuffleMask(SVOp, 4, false) ||
5353 PPC::isVMRGHShuffleMask(SVOp, 1, false) ||
5354 PPC::isVMRGHShuffleMask(SVOp, 2, false) ||
5355 PPC::isVMRGHShuffleMask(SVOp, 4, false))
5358 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
5359 // perfect shuffle table to emit an optimal matching sequence.
5360 ArrayRef<int> PermMask = SVOp->getMask();
5362 unsigned PFIndexes[4];
5363 bool isFourElementShuffle = true;
5364 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
5365 unsigned EltNo = 8; // Start out undef.
5366 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
5367 if (PermMask[i*4+j] < 0)
5368 continue; // Undef, ignore it.
5370 unsigned ByteSource = PermMask[i*4+j];
5371 if ((ByteSource & 3) != j) {
5372 isFourElementShuffle = false;
5377 EltNo = ByteSource/4;
5378 } else if (EltNo != ByteSource/4) {
5379 isFourElementShuffle = false;
5383 PFIndexes[i] = EltNo;
5386 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
5387 // perfect shuffle vector to determine if it is cost effective to do this as
5388 // discrete instructions, or whether we should use a vperm.
5389 if (isFourElementShuffle) {
5390 // Compute the index in the perfect shuffle table.
5391 unsigned PFTableIndex =
5392 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5394 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5395 unsigned Cost = (PFEntry >> 30);
5397 // Determining when to avoid vperm is tricky. Many things affect the cost
5398 // of vperm, particularly how many times the perm mask needs to be computed.
5399 // For example, if the perm mask can be hoisted out of a loop or is already
5400 // used (perhaps because there are multiple permutes with the same shuffle
5401 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
5402 // the loop requires an extra register.
5404 // As a compromise, we only emit discrete instructions if the shuffle can be
5405 // generated in 3 or fewer operations. When we have loop information
5406 // available, if this block is within a loop, we should avoid using vperm
5407 // for 3-operation perms and use a constant pool load instead.
5409 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5412 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
5413 // vector that will get spilled to the constant pool.
5414 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
5416 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
5417 // that it is in input element units, not in bytes. Convert now.
5418 EVT EltVT = V1.getValueType().getVectorElementType();
5419 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
5421 SmallVector<SDValue, 16> ResultMask;
5422 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
5423 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
5425 for (unsigned j = 0; j != BytesPerElement; ++j)
5426 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
5430 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
5431 &ResultMask[0], ResultMask.size());
5432 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
5435 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
5436 /// altivec comparison. If it is, return true and fill in Opc/isDot with
5437 /// information about the intrinsic.
5438 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
5440 unsigned IntrinsicID =
5441 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
5444 switch (IntrinsicID) {
5445 default: return false;
5446 // Comparison predicates.
5447 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
5448 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
5449 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
5450 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
5451 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
5452 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
5453 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
5454 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
5455 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
5456 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
5457 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
5458 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
5459 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
5461 // Normal Comparisons.
5462 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
5463 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
5464 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
5465 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
5466 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
5467 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
5468 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
5469 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
5470 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
5471 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
5472 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
5473 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
5474 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
5479 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
5480 /// lower, do it, otherwise return null.
5481 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
5482 SelectionDAG &DAG) const {
5483 // If this is a lowered altivec predicate compare, CompareOpc is set to the
5484 // opcode number of the comparison.
5485 DebugLoc dl = Op.getDebugLoc();
5488 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
5489 return SDValue(); // Don't custom lower most intrinsics.
5491 // If this is a non-dot comparison, make the VCMP node and we are done.
5493 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
5494 Op.getOperand(1), Op.getOperand(2),
5495 DAG.getConstant(CompareOpc, MVT::i32));
5496 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
5499 // Create the PPCISD altivec 'dot' comparison node.
5501 Op.getOperand(2), // LHS
5502 Op.getOperand(3), // RHS
5503 DAG.getConstant(CompareOpc, MVT::i32)
5505 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
5506 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
5508 // Now that we have the comparison, emit a copy from the CR to a GPR.
5509 // This is flagged to the above dot comparison.
5510 SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32,
5511 DAG.getRegister(PPC::CR6, MVT::i32),
5512 CompNode.getValue(1));
5514 // Unpack the result based on how the target uses it.
5515 unsigned BitNo; // Bit # of CR6.
5516 bool InvertBit; // Invert result?
5517 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
5518 default: // Can't happen, don't crash on invalid number though.
5519 case 0: // Return the value of the EQ bit of CR6.
5520 BitNo = 0; InvertBit = false;
5522 case 1: // Return the inverted value of the EQ bit of CR6.
5523 BitNo = 0; InvertBit = true;
5525 case 2: // Return the value of the LT bit of CR6.
5526 BitNo = 2; InvertBit = false;
5528 case 3: // Return the inverted value of the LT bit of CR6.
5529 BitNo = 2; InvertBit = true;
5533 // Shift the bit into the low position.
5534 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
5535 DAG.getConstant(8-(3-BitNo), MVT::i32));
5537 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
5538 DAG.getConstant(1, MVT::i32));
5540 // If we are supposed to, toggle the bit.
5542 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
5543 DAG.getConstant(1, MVT::i32));
5547 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
5548 SelectionDAG &DAG) const {
5549 DebugLoc dl = Op.getDebugLoc();
5550 // Create a stack slot that is 16-byte aligned.
5551 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
5552 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
5553 EVT PtrVT = getPointerTy();
5554 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5556 // Store the input value into Value#0 of the stack slot.
5557 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
5558 Op.getOperand(0), FIdx, MachinePointerInfo(),
5561 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
5562 false, false, false, 0);
5565 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
5566 DebugLoc dl = Op.getDebugLoc();
5567 if (Op.getValueType() == MVT::v4i32) {
5568 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5570 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
5571 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
5573 SDValue RHSSwap = // = vrlw RHS, 16
5574 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
5576 // Shrinkify inputs to v8i16.
5577 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
5578 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
5579 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
5581 // Low parts multiplied together, generating 32-bit results (we ignore the
5583 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
5584 LHS, RHS, DAG, dl, MVT::v4i32);
5586 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
5587 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
5588 // Shift the high parts up 16 bits.
5589 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
5591 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
5592 } else if (Op.getValueType() == MVT::v8i16) {
5593 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5595 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
5597 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
5598 LHS, RHS, Zero, DAG, dl);
5599 } else if (Op.getValueType() == MVT::v16i8) {
5600 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5602 // Multiply the even 8-bit parts, producing 16-bit sums.
5603 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
5604 LHS, RHS, DAG, dl, MVT::v8i16);
5605 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
5607 // Multiply the odd 8-bit parts, producing 16-bit sums.
5608 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
5609 LHS, RHS, DAG, dl, MVT::v8i16);
5610 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
5612 // Merge the results together.
5614 for (unsigned i = 0; i != 8; ++i) {
5616 Ops[i*2+1] = 2*i+1+16;
5618 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
5620 llvm_unreachable("Unknown mul to lower!");
5624 /// LowerOperation - Provide custom lowering hooks for some operations.
5626 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
5627 switch (Op.getOpcode()) {
5628 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
5629 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
5630 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
5631 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
5632 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
5633 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
5634 case ISD::SETCC: return LowerSETCC(Op, DAG);
5635 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
5636 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
5638 return LowerVASTART(Op, DAG, PPCSubTarget);
5641 return LowerVAARG(Op, DAG, PPCSubTarget);
5643 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
5644 case ISD::DYNAMIC_STACKALLOC:
5645 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
5647 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
5648 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
5650 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
5651 case ISD::FP_TO_UINT:
5652 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
5654 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
5655 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
5657 // Lower 64-bit shifts.
5658 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
5659 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
5660 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
5662 // Vector-related lowering.
5663 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
5664 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
5665 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
5666 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
5667 case ISD::MUL: return LowerMUL(Op, DAG);
5669 // Frame & Return address.
5670 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
5671 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
5675 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
5676 SmallVectorImpl<SDValue>&Results,
5677 SelectionDAG &DAG) const {
5678 const TargetMachine &TM = getTargetMachine();
5679 DebugLoc dl = N->getDebugLoc();
5680 switch (N->getOpcode()) {
5682 llvm_unreachable("Do not know how to custom type legalize this operation!");
5684 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
5685 || TM.getSubtarget<PPCSubtarget>().isPPC64())
5688 EVT VT = N->getValueType(0);
5690 if (VT == MVT::i64) {
5691 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, PPCSubTarget);
5693 Results.push_back(NewNode);
5694 Results.push_back(NewNode.getValue(1));
5698 case ISD::FP_ROUND_INREG: {
5699 assert(N->getValueType(0) == MVT::ppcf128);
5700 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
5701 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
5702 MVT::f64, N->getOperand(0),
5703 DAG.getIntPtrConstant(0));
5704 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
5705 MVT::f64, N->getOperand(0),
5706 DAG.getIntPtrConstant(1));
5708 // Add the two halves of the long double in round-to-zero mode.
5709 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
5711 // We know the low half is about to be thrown away, so just use something
5713 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
5717 case ISD::FP_TO_SINT:
5718 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
5724 //===----------------------------------------------------------------------===//
5725 // Other Lowering Code
5726 //===----------------------------------------------------------------------===//
5729 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
5730 bool is64bit, unsigned BinOpcode) const {
5731 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
5732 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5734 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5735 MachineFunction *F = BB->getParent();
5736 MachineFunction::iterator It = BB;
5739 unsigned dest = MI->getOperand(0).getReg();
5740 unsigned ptrA = MI->getOperand(1).getReg();
5741 unsigned ptrB = MI->getOperand(2).getReg();
5742 unsigned incr = MI->getOperand(3).getReg();
5743 DebugLoc dl = MI->getDebugLoc();
5745 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
5746 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
5747 F->insert(It, loopMBB);
5748 F->insert(It, exitMBB);
5749 exitMBB->splice(exitMBB->begin(), BB,
5750 llvm::next(MachineBasicBlock::iterator(MI)),
5752 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5754 MachineRegisterInfo &RegInfo = F->getRegInfo();
5755 unsigned TmpReg = (!BinOpcode) ? incr :
5756 RegInfo.createVirtualRegister(
5757 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
5758 (const TargetRegisterClass *) &PPC::GPRCRegClass);
5762 // fallthrough --> loopMBB
5763 BB->addSuccessor(loopMBB);
5766 // l[wd]arx dest, ptr
5767 // add r0, dest, incr
5768 // st[wd]cx. r0, ptr
5770 // fallthrough --> exitMBB
5772 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
5773 .addReg(ptrA).addReg(ptrB);
5775 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
5776 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
5777 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
5778 BuildMI(BB, dl, TII->get(PPC::BCC))
5779 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
5780 BB->addSuccessor(loopMBB);
5781 BB->addSuccessor(exitMBB);
5790 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
5791 MachineBasicBlock *BB,
5792 bool is8bit, // operation
5793 unsigned BinOpcode) const {
5794 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
5795 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5796 // In 64 bit mode we have to use 64 bits for addresses, even though the
5797 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
5798 // registers without caring whether they're 32 or 64, but here we're
5799 // doing actual arithmetic on the addresses.
5800 bool is64bit = PPCSubTarget.isPPC64();
5801 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
5803 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5804 MachineFunction *F = BB->getParent();
5805 MachineFunction::iterator It = BB;
5808 unsigned dest = MI->getOperand(0).getReg();
5809 unsigned ptrA = MI->getOperand(1).getReg();
5810 unsigned ptrB = MI->getOperand(2).getReg();
5811 unsigned incr = MI->getOperand(3).getReg();
5812 DebugLoc dl = MI->getDebugLoc();
5814 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
5815 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
5816 F->insert(It, loopMBB);
5817 F->insert(It, exitMBB);
5818 exitMBB->splice(exitMBB->begin(), BB,
5819 llvm::next(MachineBasicBlock::iterator(MI)),
5821 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5823 MachineRegisterInfo &RegInfo = F->getRegInfo();
5824 const TargetRegisterClass *RC =
5825 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
5826 (const TargetRegisterClass *) &PPC::GPRCRegClass;
5827 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
5828 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
5829 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
5830 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
5831 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
5832 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
5833 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
5834 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
5835 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
5836 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
5837 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
5839 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
5843 // fallthrough --> loopMBB
5844 BB->addSuccessor(loopMBB);
5846 // The 4-byte load must be aligned, while a char or short may be
5847 // anywhere in the word. Hence all this nasty bookkeeping code.
5848 // add ptr1, ptrA, ptrB [copy if ptrA==0]
5849 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
5850 // xori shift, shift1, 24 [16]
5851 // rlwinm ptr, ptr1, 0, 0, 29
5852 // slw incr2, incr, shift
5853 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
5854 // slw mask, mask2, shift
5856 // lwarx tmpDest, ptr
5857 // add tmp, tmpDest, incr2
5858 // andc tmp2, tmpDest, mask
5859 // and tmp3, tmp, mask
5860 // or tmp4, tmp3, tmp2
5863 // fallthrough --> exitMBB
5864 // srw dest, tmpDest, shift
5865 if (ptrA != ZeroReg) {
5866 Ptr1Reg = RegInfo.createVirtualRegister(RC);
5867 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
5868 .addReg(ptrA).addReg(ptrB);
5872 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
5873 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
5874 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
5875 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
5877 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
5878 .addReg(Ptr1Reg).addImm(0).addImm(61);
5880 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
5881 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
5882 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
5883 .addReg(incr).addReg(ShiftReg);
5885 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
5887 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
5888 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
5890 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
5891 .addReg(Mask2Reg).addReg(ShiftReg);
5894 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
5895 .addReg(ZeroReg).addReg(PtrReg);
5897 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
5898 .addReg(Incr2Reg).addReg(TmpDestReg);
5899 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
5900 .addReg(TmpDestReg).addReg(MaskReg);
5901 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
5902 .addReg(TmpReg).addReg(MaskReg);
5903 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
5904 .addReg(Tmp3Reg).addReg(Tmp2Reg);
5905 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
5906 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
5907 BuildMI(BB, dl, TII->get(PPC::BCC))
5908 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
5909 BB->addSuccessor(loopMBB);
5910 BB->addSuccessor(exitMBB);
5915 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
5920 llvm::MachineBasicBlock*
5921 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
5922 MachineBasicBlock *MBB) const {
5923 DebugLoc DL = MI->getDebugLoc();
5924 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5926 MachineFunction *MF = MBB->getParent();
5927 MachineRegisterInfo &MRI = MF->getRegInfo();
5929 const BasicBlock *BB = MBB->getBasicBlock();
5930 MachineFunction::iterator I = MBB;
5934 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
5935 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
5937 unsigned DstReg = MI->getOperand(0).getReg();
5938 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
5939 assert(RC->hasType(MVT::i32) && "Invalid destination!");
5940 unsigned mainDstReg = MRI.createVirtualRegister(RC);
5941 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
5943 MVT PVT = getPointerTy();
5944 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
5945 "Invalid Pointer Size!");
5946 // For v = setjmp(buf), we generate
5949 // SjLjSetup mainMBB
5955 // buf[LabelOffset] = LR
5959 // v = phi(main, restore)
5962 MachineBasicBlock *thisMBB = MBB;
5963 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
5964 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
5965 MF->insert(I, mainMBB);
5966 MF->insert(I, sinkMBB);
5968 MachineInstrBuilder MIB;
5970 // Transfer the remainder of BB and its successor edges to sinkMBB.
5971 sinkMBB->splice(sinkMBB->begin(), MBB,
5972 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
5973 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
5975 // Note that the structure of the jmp_buf used here is not compatible
5976 // with that used by libc, and is not designed to be. Specifically, it
5977 // stores only those 'reserved' registers that LLVM does not otherwise
5978 // understand how to spill. Also, by convention, by the time this
5979 // intrinsic is called, Clang has already stored the frame address in the
5980 // first slot of the buffer and stack address in the third. Following the
5981 // X86 target code, we'll store the jump address in the second slot. We also
5982 // need to save the TOC pointer (R2) to handle jumps between shared
5983 // libraries, and that will be stored in the fourth slot. The thread
5984 // identifier (R13) is not affected.
5987 const int64_t LabelOffset = 1 * PVT.getStoreSize();
5988 const int64_t TOCOffset = 3 * PVT.getStoreSize();
5990 // Prepare IP either in reg.
5991 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
5992 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
5993 unsigned BufReg = MI->getOperand(1).getReg();
5995 if (PPCSubTarget.isPPC64() && PPCSubTarget.isSVR4ABI()) {
5996 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
5998 .addImm(TOCOffset / 4)
6001 MIB.setMemRefs(MMOBegin, MMOEnd);
6005 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCL)).addMBB(mainMBB);
6006 MIB.addRegMask(PPCRegInfo->getNoPreservedMask());
6008 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
6010 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
6012 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
6014 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
6015 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
6019 MIB = BuildMI(mainMBB, DL,
6020 TII->get(PPCSubTarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
6023 if (PPCSubTarget.isPPC64()) {
6024 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
6026 .addImm(LabelOffset / 4)
6029 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
6031 .addImm(LabelOffset)
6035 MIB.setMemRefs(MMOBegin, MMOEnd);
6037 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
6038 mainMBB->addSuccessor(sinkMBB);
6041 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
6042 TII->get(PPC::PHI), DstReg)
6043 .addReg(mainDstReg).addMBB(mainMBB)
6044 .addReg(restoreDstReg).addMBB(thisMBB);
6046 MI->eraseFromParent();
6051 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
6052 MachineBasicBlock *MBB) const {
6053 DebugLoc DL = MI->getDebugLoc();
6054 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6056 MachineFunction *MF = MBB->getParent();
6057 MachineRegisterInfo &MRI = MF->getRegInfo();
6060 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6061 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6063 MVT PVT = getPointerTy();
6064 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6065 "Invalid Pointer Size!");
6067 const TargetRegisterClass *RC =
6068 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6069 unsigned Tmp = MRI.createVirtualRegister(RC);
6070 // Since FP is only updated here but NOT referenced, it's treated as GPR.
6071 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6072 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6074 MachineInstrBuilder MIB;
6076 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6077 const int64_t SPOffset = 2 * PVT.getStoreSize();
6078 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6080 unsigned BufReg = MI->getOperand(0).getReg();
6082 // Reload FP (the jumped-to function may not have had a
6083 // frame pointer, and if so, then its r31 will be restored
6085 if (PVT == MVT::i64) {
6086 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
6090 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
6094 MIB.setMemRefs(MMOBegin, MMOEnd);
6097 if (PVT == MVT::i64) {
6098 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
6099 .addImm(LabelOffset / 4)
6102 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
6103 .addImm(LabelOffset)
6106 MIB.setMemRefs(MMOBegin, MMOEnd);
6109 if (PVT == MVT::i64) {
6110 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
6111 .addImm(SPOffset / 4)
6114 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
6118 MIB.setMemRefs(MMOBegin, MMOEnd);
6120 // FIXME: When we also support base pointers, that register must also be
6124 if (PVT == MVT::i64 && PPCSubTarget.isSVR4ABI()) {
6125 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
6126 .addImm(TOCOffset / 4)
6129 MIB.setMemRefs(MMOBegin, MMOEnd);
6133 BuildMI(*MBB, MI, DL,
6134 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
6135 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
6137 MI->eraseFromParent();
6142 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6143 MachineBasicBlock *BB) const {
6144 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
6145 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
6146 return emitEHSjLjSetJmp(MI, BB);
6147 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
6148 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
6149 return emitEHSjLjLongJmp(MI, BB);
6152 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6154 // To "insert" these instructions we actually have to insert their
6155 // control-flow patterns.
6156 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6157 MachineFunction::iterator It = BB;
6160 MachineFunction *F = BB->getParent();
6162 if (PPCSubTarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6163 MI->getOpcode() == PPC::SELECT_CC_I8)) {
6164 unsigned OpCode = MI->getOpcode() == PPC::SELECT_CC_I8 ?
6165 PPC::ISEL8 : PPC::ISEL;
6166 unsigned SelectPred = MI->getOperand(4).getImm();
6167 DebugLoc dl = MI->getDebugLoc();
6171 switch (SelectPred) {
6172 default: llvm_unreachable("invalid predicate for isel");
6173 case PPC::PRED_EQ: SubIdx = PPC::sub_eq; SwapOps = false; break;
6174 case PPC::PRED_NE: SubIdx = PPC::sub_eq; SwapOps = true; break;
6175 case PPC::PRED_LT: SubIdx = PPC::sub_lt; SwapOps = false; break;
6176 case PPC::PRED_GE: SubIdx = PPC::sub_lt; SwapOps = true; break;
6177 case PPC::PRED_GT: SubIdx = PPC::sub_gt; SwapOps = false; break;
6178 case PPC::PRED_LE: SubIdx = PPC::sub_gt; SwapOps = true; break;
6179 case PPC::PRED_UN: SubIdx = PPC::sub_un; SwapOps = false; break;
6180 case PPC::PRED_NU: SubIdx = PPC::sub_un; SwapOps = true; break;
6183 BuildMI(*BB, MI, dl, TII->get(OpCode), MI->getOperand(0).getReg())
6184 .addReg(MI->getOperand(SwapOps? 3 : 2).getReg())
6185 .addReg(MI->getOperand(SwapOps? 2 : 3).getReg())
6186 .addReg(MI->getOperand(1).getReg(), 0, SubIdx);
6187 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6188 MI->getOpcode() == PPC::SELECT_CC_I8 ||
6189 MI->getOpcode() == PPC::SELECT_CC_F4 ||
6190 MI->getOpcode() == PPC::SELECT_CC_F8 ||
6191 MI->getOpcode() == PPC::SELECT_CC_VRRC) {
6194 // The incoming instruction knows the destination vreg to set, the
6195 // condition code register to branch on, the true/false values to
6196 // select between, and a branch opcode to use.
6201 // cmpTY ccX, r1, r2
6203 // fallthrough --> copy0MBB
6204 MachineBasicBlock *thisMBB = BB;
6205 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
6206 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
6207 unsigned SelectPred = MI->getOperand(4).getImm();
6208 DebugLoc dl = MI->getDebugLoc();
6209 F->insert(It, copy0MBB);
6210 F->insert(It, sinkMBB);
6212 // Transfer the remainder of BB and its successor edges to sinkMBB.
6213 sinkMBB->splice(sinkMBB->begin(), BB,
6214 llvm::next(MachineBasicBlock::iterator(MI)),
6216 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
6218 // Next, add the true and fallthrough blocks as its successors.
6219 BB->addSuccessor(copy0MBB);
6220 BB->addSuccessor(sinkMBB);
6222 BuildMI(BB, dl, TII->get(PPC::BCC))
6223 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
6226 // %FalseValue = ...
6227 // # fallthrough to sinkMBB
6230 // Update machine-CFG edges
6231 BB->addSuccessor(sinkMBB);
6234 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
6237 BuildMI(*BB, BB->begin(), dl,
6238 TII->get(PPC::PHI), MI->getOperand(0).getReg())
6239 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
6240 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
6242 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
6243 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
6244 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
6245 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
6246 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
6247 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
6248 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
6249 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
6251 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
6252 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
6253 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
6254 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
6255 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
6256 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
6257 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
6258 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
6260 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
6261 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
6262 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
6263 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
6264 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
6265 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
6266 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
6267 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
6269 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
6270 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
6271 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
6272 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
6273 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
6274 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
6275 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
6276 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
6278 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
6279 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
6280 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
6281 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
6282 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
6283 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
6284 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
6285 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
6287 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
6288 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
6289 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
6290 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
6291 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
6292 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
6293 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
6294 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
6296 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
6297 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
6298 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
6299 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
6300 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
6301 BB = EmitAtomicBinary(MI, BB, false, 0);
6302 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
6303 BB = EmitAtomicBinary(MI, BB, true, 0);
6305 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
6306 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
6307 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
6309 unsigned dest = MI->getOperand(0).getReg();
6310 unsigned ptrA = MI->getOperand(1).getReg();
6311 unsigned ptrB = MI->getOperand(2).getReg();
6312 unsigned oldval = MI->getOperand(3).getReg();
6313 unsigned newval = MI->getOperand(4).getReg();
6314 DebugLoc dl = MI->getDebugLoc();
6316 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6317 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6318 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6319 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6320 F->insert(It, loop1MBB);
6321 F->insert(It, loop2MBB);
6322 F->insert(It, midMBB);
6323 F->insert(It, exitMBB);
6324 exitMBB->splice(exitMBB->begin(), BB,
6325 llvm::next(MachineBasicBlock::iterator(MI)),
6327 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6331 // fallthrough --> loopMBB
6332 BB->addSuccessor(loop1MBB);
6335 // l[wd]arx dest, ptr
6336 // cmp[wd] dest, oldval
6339 // st[wd]cx. newval, ptr
6343 // st[wd]cx. dest, ptr
6346 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6347 .addReg(ptrA).addReg(ptrB);
6348 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
6349 .addReg(oldval).addReg(dest);
6350 BuildMI(BB, dl, TII->get(PPC::BCC))
6351 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6352 BB->addSuccessor(loop2MBB);
6353 BB->addSuccessor(midMBB);
6356 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6357 .addReg(newval).addReg(ptrA).addReg(ptrB);
6358 BuildMI(BB, dl, TII->get(PPC::BCC))
6359 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6360 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6361 BB->addSuccessor(loop1MBB);
6362 BB->addSuccessor(exitMBB);
6365 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6366 .addReg(dest).addReg(ptrA).addReg(ptrB);
6367 BB->addSuccessor(exitMBB);
6372 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
6373 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
6374 // We must use 64-bit registers for addresses when targeting 64-bit,
6375 // since we're actually doing arithmetic on them. Other registers
6377 bool is64bit = PPCSubTarget.isPPC64();
6378 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
6380 unsigned dest = MI->getOperand(0).getReg();
6381 unsigned ptrA = MI->getOperand(1).getReg();
6382 unsigned ptrB = MI->getOperand(2).getReg();
6383 unsigned oldval = MI->getOperand(3).getReg();
6384 unsigned newval = MI->getOperand(4).getReg();
6385 DebugLoc dl = MI->getDebugLoc();
6387 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6388 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6389 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6390 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6391 F->insert(It, loop1MBB);
6392 F->insert(It, loop2MBB);
6393 F->insert(It, midMBB);
6394 F->insert(It, exitMBB);
6395 exitMBB->splice(exitMBB->begin(), BB,
6396 llvm::next(MachineBasicBlock::iterator(MI)),
6398 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6400 MachineRegisterInfo &RegInfo = F->getRegInfo();
6401 const TargetRegisterClass *RC =
6402 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6403 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6404 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6405 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6406 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6407 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
6408 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
6409 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
6410 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
6411 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6412 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6413 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6414 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6415 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6416 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6418 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
6419 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6422 // fallthrough --> loopMBB
6423 BB->addSuccessor(loop1MBB);
6425 // The 4-byte load must be aligned, while a char or short may be
6426 // anywhere in the word. Hence all this nasty bookkeeping code.
6427 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6428 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6429 // xori shift, shift1, 24 [16]
6430 // rlwinm ptr, ptr1, 0, 0, 29
6431 // slw newval2, newval, shift
6432 // slw oldval2, oldval,shift
6433 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6434 // slw mask, mask2, shift
6435 // and newval3, newval2, mask
6436 // and oldval3, oldval2, mask
6438 // lwarx tmpDest, ptr
6439 // and tmp, tmpDest, mask
6440 // cmpw tmp, oldval3
6443 // andc tmp2, tmpDest, mask
6444 // or tmp4, tmp2, newval3
6449 // stwcx. tmpDest, ptr
6451 // srw dest, tmpDest, shift
6452 if (ptrA != ZeroReg) {
6453 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6454 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6455 .addReg(ptrA).addReg(ptrB);
6459 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6460 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6461 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6462 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6464 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6465 .addReg(Ptr1Reg).addImm(0).addImm(61);
6467 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6468 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6469 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
6470 .addReg(newval).addReg(ShiftReg);
6471 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
6472 .addReg(oldval).addReg(ShiftReg);
6474 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6476 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6477 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
6478 .addReg(Mask3Reg).addImm(65535);
6480 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6481 .addReg(Mask2Reg).addReg(ShiftReg);
6482 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
6483 .addReg(NewVal2Reg).addReg(MaskReg);
6484 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
6485 .addReg(OldVal2Reg).addReg(MaskReg);
6488 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6489 .addReg(ZeroReg).addReg(PtrReg);
6490 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
6491 .addReg(TmpDestReg).addReg(MaskReg);
6492 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
6493 .addReg(TmpReg).addReg(OldVal3Reg);
6494 BuildMI(BB, dl, TII->get(PPC::BCC))
6495 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6496 BB->addSuccessor(loop2MBB);
6497 BB->addSuccessor(midMBB);
6500 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
6501 .addReg(TmpDestReg).addReg(MaskReg);
6502 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
6503 .addReg(Tmp2Reg).addReg(NewVal3Reg);
6504 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
6505 .addReg(ZeroReg).addReg(PtrReg);
6506 BuildMI(BB, dl, TII->get(PPC::BCC))
6507 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6508 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6509 BB->addSuccessor(loop1MBB);
6510 BB->addSuccessor(exitMBB);
6513 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
6514 .addReg(ZeroReg).addReg(PtrReg);
6515 BB->addSuccessor(exitMBB);
6520 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
6522 } else if (MI->getOpcode() == PPC::FADDrtz) {
6523 // This pseudo performs an FADD with rounding mode temporarily forced
6524 // to round-to-zero. We emit this via custom inserter since the FPSCR
6525 // is not modeled at the SelectionDAG level.
6526 unsigned Dest = MI->getOperand(0).getReg();
6527 unsigned Src1 = MI->getOperand(1).getReg();
6528 unsigned Src2 = MI->getOperand(2).getReg();
6529 DebugLoc dl = MI->getDebugLoc();
6531 MachineRegisterInfo &RegInfo = F->getRegInfo();
6532 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
6534 // Save FPSCR value.
6535 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
6537 // Set rounding mode to round-to-zero.
6538 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
6539 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
6541 // Perform addition.
6542 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
6544 // Restore FPSCR value.
6545 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg);
6546 } else if (MI->getOpcode() == PPC::FRINDrint ||
6547 MI->getOpcode() == PPC::FRINSrint) {
6548 bool isf32 = MI->getOpcode() == PPC::FRINSrint;
6549 unsigned Dest = MI->getOperand(0).getReg();
6550 unsigned Src = MI->getOperand(1).getReg();
6551 DebugLoc dl = MI->getDebugLoc();
6553 MachineRegisterInfo &RegInfo = F->getRegInfo();
6554 unsigned CRReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
6556 // Perform the rounding.
6557 BuildMI(*BB, MI, dl, TII->get(isf32 ? PPC::FRINS : PPC::FRIND), Dest)
6560 // Compare the results.
6561 BuildMI(*BB, MI, dl, TII->get(isf32 ? PPC::FCMPUS : PPC::FCMPUD), CRReg)
6562 .addReg(Dest).addReg(Src);
6564 // If the results were not equal, then set the FPSCR XX bit.
6565 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6566 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6567 F->insert(It, midMBB);
6568 F->insert(It, exitMBB);
6569 exitMBB->splice(exitMBB->begin(), BB,
6570 llvm::next(MachineBasicBlock::iterator(MI)),
6572 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6574 BuildMI(*BB, MI, dl, TII->get(PPC::BCC))
6575 .addImm(PPC::PRED_EQ).addReg(CRReg).addMBB(exitMBB);
6577 BB->addSuccessor(midMBB);
6578 BB->addSuccessor(exitMBB);
6582 // Set the FPSCR XX bit (FE_INEXACT). Note that we cannot just set
6583 // the FI bit here because that will not automatically set XX also,
6584 // and XX is what libm interprets as the FE_INEXACT flag.
6585 BuildMI(BB, dl, TII->get(PPC::MTFSB1)).addImm(/* 38 - 32 = */ 6);
6586 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6588 BB->addSuccessor(exitMBB);
6592 llvm_unreachable("Unexpected instr type to insert");
6595 MI->eraseFromParent(); // The pseudo instruction is gone now.
6599 //===----------------------------------------------------------------------===//
6600 // Target Optimization Hooks
6601 //===----------------------------------------------------------------------===//
6603 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
6604 DAGCombinerInfo &DCI) const {
6605 const TargetMachine &TM = getTargetMachine();
6606 SelectionDAG &DAG = DCI.DAG;
6607 DebugLoc dl = N->getDebugLoc();
6608 switch (N->getOpcode()) {
6611 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6612 if (C->isNullValue()) // 0 << V -> 0.
6613 return N->getOperand(0);
6617 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6618 if (C->isNullValue()) // 0 >>u V -> 0.
6619 return N->getOperand(0);
6623 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6624 if (C->isNullValue() || // 0 >>s V -> 0.
6625 C->isAllOnesValue()) // -1 >>s V -> -1.
6626 return N->getOperand(0);
6630 case ISD::SINT_TO_FP:
6631 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
6632 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
6633 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
6634 // We allow the src/dst to be either f32/f64, but the intermediate
6635 // type must be i64.
6636 if (N->getOperand(0).getValueType() == MVT::i64 &&
6637 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
6638 SDValue Val = N->getOperand(0).getOperand(0);
6639 if (Val.getValueType() == MVT::f32) {
6640 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
6641 DCI.AddToWorklist(Val.getNode());
6644 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
6645 DCI.AddToWorklist(Val.getNode());
6646 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
6647 DCI.AddToWorklist(Val.getNode());
6648 if (N->getValueType(0) == MVT::f32) {
6649 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
6650 DAG.getIntPtrConstant(0));
6651 DCI.AddToWorklist(Val.getNode());
6654 } else if (N->getOperand(0).getValueType() == MVT::i32) {
6655 // If the intermediate type is i32, we can avoid the load/store here
6662 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
6663 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
6664 !cast<StoreSDNode>(N)->isTruncatingStore() &&
6665 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
6666 N->getOperand(1).getValueType() == MVT::i32 &&
6667 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
6668 SDValue Val = N->getOperand(1).getOperand(0);
6669 if (Val.getValueType() == MVT::f32) {
6670 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
6671 DCI.AddToWorklist(Val.getNode());
6673 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
6674 DCI.AddToWorklist(Val.getNode());
6677 N->getOperand(0), Val, N->getOperand(2),
6678 DAG.getValueType(N->getOperand(1).getValueType())
6681 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
6682 DAG.getVTList(MVT::Other), Ops, array_lengthof(Ops),
6683 cast<StoreSDNode>(N)->getMemoryVT(),
6684 cast<StoreSDNode>(N)->getMemOperand());
6685 DCI.AddToWorklist(Val.getNode());
6689 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
6690 if (cast<StoreSDNode>(N)->isUnindexed() &&
6691 N->getOperand(1).getOpcode() == ISD::BSWAP &&
6692 N->getOperand(1).getNode()->hasOneUse() &&
6693 (N->getOperand(1).getValueType() == MVT::i32 ||
6694 N->getOperand(1).getValueType() == MVT::i16 ||
6695 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
6696 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
6697 N->getOperand(1).getValueType() == MVT::i64))) {
6698 SDValue BSwapOp = N->getOperand(1).getOperand(0);
6699 // Do an any-extend to 32-bits if this is a half-word input.
6700 if (BSwapOp.getValueType() == MVT::i16)
6701 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
6704 N->getOperand(0), BSwapOp, N->getOperand(2),
6705 DAG.getValueType(N->getOperand(1).getValueType())
6708 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
6709 Ops, array_lengthof(Ops),
6710 cast<StoreSDNode>(N)->getMemoryVT(),
6711 cast<StoreSDNode>(N)->getMemOperand());
6715 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
6716 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
6717 N->getOperand(0).hasOneUse() &&
6718 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
6719 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
6720 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
6721 N->getValueType(0) == MVT::i64))) {
6722 SDValue Load = N->getOperand(0);
6723 LoadSDNode *LD = cast<LoadSDNode>(Load);
6724 // Create the byte-swapping load.
6726 LD->getChain(), // Chain
6727 LD->getBasePtr(), // Ptr
6728 DAG.getValueType(N->getValueType(0)) // VT
6731 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
6732 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
6733 MVT::i64 : MVT::i32, MVT::Other),
6734 Ops, 3, LD->getMemoryVT(), LD->getMemOperand());
6736 // If this is an i16 load, insert the truncate.
6737 SDValue ResVal = BSLoad;
6738 if (N->getValueType(0) == MVT::i16)
6739 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
6741 // First, combine the bswap away. This makes the value produced by the
6743 DCI.CombineTo(N, ResVal);
6745 // Next, combine the load away, we give it a bogus result value but a real
6746 // chain result. The result value is dead because the bswap is dead.
6747 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
6749 // Return N so it doesn't get rechecked!
6750 return SDValue(N, 0);
6754 case PPCISD::VCMP: {
6755 // If a VCMPo node already exists with exactly the same operands as this
6756 // node, use its result instead of this node (VCMPo computes both a CR6 and
6757 // a normal output).
6759 if (!N->getOperand(0).hasOneUse() &&
6760 !N->getOperand(1).hasOneUse() &&
6761 !N->getOperand(2).hasOneUse()) {
6763 // Scan all of the users of the LHS, looking for VCMPo's that match.
6764 SDNode *VCMPoNode = 0;
6766 SDNode *LHSN = N->getOperand(0).getNode();
6767 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
6769 if (UI->getOpcode() == PPCISD::VCMPo &&
6770 UI->getOperand(1) == N->getOperand(1) &&
6771 UI->getOperand(2) == N->getOperand(2) &&
6772 UI->getOperand(0) == N->getOperand(0)) {
6777 // If there is no VCMPo node, or if the flag value has a single use, don't
6779 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
6782 // Look at the (necessarily single) use of the flag value. If it has a
6783 // chain, this transformation is more complex. Note that multiple things
6784 // could use the value result, which we should ignore.
6785 SDNode *FlagUser = 0;
6786 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
6787 FlagUser == 0; ++UI) {
6788 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
6790 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
6791 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
6798 // If the user is a MFCR instruction, we know this is safe. Otherwise we
6799 // give up for right now.
6800 if (FlagUser->getOpcode() == PPCISD::MFCR)
6801 return SDValue(VCMPoNode, 0);
6806 // If this is a branch on an altivec predicate comparison, lower this so
6807 // that we don't have to do a MFCR: instead, branch directly on CR6. This
6808 // lowering is done pre-legalize, because the legalizer lowers the predicate
6809 // compare down to code that is difficult to reassemble.
6810 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
6811 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
6815 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
6816 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
6817 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
6818 assert(isDot && "Can't compare against a vector result!");
6820 // If this is a comparison against something other than 0/1, then we know
6821 // that the condition is never/always true.
6822 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
6823 if (Val != 0 && Val != 1) {
6824 if (CC == ISD::SETEQ) // Cond never true, remove branch.
6825 return N->getOperand(0);
6826 // Always !=, turn it into an unconditional branch.
6827 return DAG.getNode(ISD::BR, dl, MVT::Other,
6828 N->getOperand(0), N->getOperand(4));
6831 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
6833 // Create the PPCISD altivec 'dot' comparison node.
6835 LHS.getOperand(2), // LHS of compare
6836 LHS.getOperand(3), // RHS of compare
6837 DAG.getConstant(CompareOpc, MVT::i32)
6839 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
6840 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
6842 // Unpack the result based on how the target uses it.
6843 PPC::Predicate CompOpc;
6844 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
6845 default: // Can't happen, don't crash on invalid number though.
6846 case 0: // Branch on the value of the EQ bit of CR6.
6847 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
6849 case 1: // Branch on the inverted value of the EQ bit of CR6.
6850 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
6852 case 2: // Branch on the value of the LT bit of CR6.
6853 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
6855 case 3: // Branch on the inverted value of the LT bit of CR6.
6856 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
6860 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
6861 DAG.getConstant(CompOpc, MVT::i32),
6862 DAG.getRegister(PPC::CR6, MVT::i32),
6863 N->getOperand(4), CompNode.getValue(1));
6872 //===----------------------------------------------------------------------===//
6873 // Inline Assembly Support
6874 //===----------------------------------------------------------------------===//
6876 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
6879 const SelectionDAG &DAG,
6880 unsigned Depth) const {
6881 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
6882 switch (Op.getOpcode()) {
6884 case PPCISD::LBRX: {
6885 // lhbrx is known to have the top bits cleared out.
6886 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
6887 KnownZero = 0xFFFF0000;
6890 case ISD::INTRINSIC_WO_CHAIN: {
6891 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
6893 case Intrinsic::ppc_altivec_vcmpbfp_p:
6894 case Intrinsic::ppc_altivec_vcmpeqfp_p:
6895 case Intrinsic::ppc_altivec_vcmpequb_p:
6896 case Intrinsic::ppc_altivec_vcmpequh_p:
6897 case Intrinsic::ppc_altivec_vcmpequw_p:
6898 case Intrinsic::ppc_altivec_vcmpgefp_p:
6899 case Intrinsic::ppc_altivec_vcmpgtfp_p:
6900 case Intrinsic::ppc_altivec_vcmpgtsb_p:
6901 case Intrinsic::ppc_altivec_vcmpgtsh_p:
6902 case Intrinsic::ppc_altivec_vcmpgtsw_p:
6903 case Intrinsic::ppc_altivec_vcmpgtub_p:
6904 case Intrinsic::ppc_altivec_vcmpgtuh_p:
6905 case Intrinsic::ppc_altivec_vcmpgtuw_p:
6906 KnownZero = ~1U; // All bits but the low one are known to be zero.
6914 /// getConstraintType - Given a constraint, return the type of
6915 /// constraint it is for this target.
6916 PPCTargetLowering::ConstraintType
6917 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
6918 if (Constraint.size() == 1) {
6919 switch (Constraint[0]) {
6926 return C_RegisterClass;
6928 // FIXME: While Z does indicate a memory constraint, it specifically
6929 // indicates an r+r address (used in conjunction with the 'y' modifier
6930 // in the replacement string). Currently, we're forcing the base
6931 // register to be r0 in the asm printer (which is interpreted as zero)
6932 // and forming the complete address in the second register. This is
6937 return TargetLowering::getConstraintType(Constraint);
6940 /// Examine constraint type and operand type and determine a weight value.
6941 /// This object must already have been set up with the operand type
6942 /// and the current alternative constraint selected.
6943 TargetLowering::ConstraintWeight
6944 PPCTargetLowering::getSingleConstraintMatchWeight(
6945 AsmOperandInfo &info, const char *constraint) const {
6946 ConstraintWeight weight = CW_Invalid;
6947 Value *CallOperandVal = info.CallOperandVal;
6948 // If we don't have a value, we can't do a match,
6949 // but allow it at the lowest weight.
6950 if (CallOperandVal == NULL)
6952 Type *type = CallOperandVal->getType();
6953 // Look at the constraint type.
6954 switch (*constraint) {
6956 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
6959 if (type->isIntegerTy())
6960 weight = CW_Register;
6963 if (type->isFloatTy())
6964 weight = CW_Register;
6967 if (type->isDoubleTy())
6968 weight = CW_Register;
6971 if (type->isVectorTy())
6972 weight = CW_Register;
6975 weight = CW_Register;
6984 std::pair<unsigned, const TargetRegisterClass*>
6985 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
6987 if (Constraint.size() == 1) {
6988 // GCC RS6000 Constraint Letters
6989 switch (Constraint[0]) {
6991 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
6992 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
6993 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
6995 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
6996 return std::make_pair(0U, &PPC::G8RCRegClass);
6997 return std::make_pair(0U, &PPC::GPRCRegClass);
6999 if (VT == MVT::f32 || VT == MVT::i32)
7000 return std::make_pair(0U, &PPC::F4RCRegClass);
7001 if (VT == MVT::f64 || VT == MVT::i64)
7002 return std::make_pair(0U, &PPC::F8RCRegClass);
7005 return std::make_pair(0U, &PPC::VRRCRegClass);
7007 return std::make_pair(0U, &PPC::CRRCRegClass);
7011 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
7015 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
7016 /// vector. If it is invalid, don't add anything to Ops.
7017 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
7018 std::string &Constraint,
7019 std::vector<SDValue>&Ops,
7020 SelectionDAG &DAG) const {
7021 SDValue Result(0,0);
7023 // Only support length 1 constraints.
7024 if (Constraint.length() > 1) return;
7026 char Letter = Constraint[0];
7037 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
7038 if (!CST) return; // Must be an immediate to match.
7039 unsigned Value = CST->getZExtValue();
7041 default: llvm_unreachable("Unknown constraint letter!");
7042 case 'I': // "I" is a signed 16-bit constant.
7043 if ((short)Value == (int)Value)
7044 Result = DAG.getTargetConstant(Value, Op.getValueType());
7046 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
7047 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
7048 if ((short)Value == 0)
7049 Result = DAG.getTargetConstant(Value, Op.getValueType());
7051 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
7052 if ((Value >> 16) == 0)
7053 Result = DAG.getTargetConstant(Value, Op.getValueType());
7055 case 'M': // "M" is a constant that is greater than 31.
7057 Result = DAG.getTargetConstant(Value, Op.getValueType());
7059 case 'N': // "N" is a positive constant that is an exact power of two.
7060 if ((int)Value > 0 && isPowerOf2_32(Value))
7061 Result = DAG.getTargetConstant(Value, Op.getValueType());
7063 case 'O': // "O" is the constant zero.
7065 Result = DAG.getTargetConstant(Value, Op.getValueType());
7067 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
7068 if ((short)-Value == (int)-Value)
7069 Result = DAG.getTargetConstant(Value, Op.getValueType());
7076 if (Result.getNode()) {
7077 Ops.push_back(Result);
7081 // Handle standard constraint letters.
7082 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
7085 // isLegalAddressingMode - Return true if the addressing mode represented
7086 // by AM is legal for this target, for a load/store of the specified type.
7087 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
7089 // FIXME: PPC does not allow r+i addressing modes for vectors!
7091 // PPC allows a sign-extended 16-bit immediate field.
7092 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
7095 // No global is ever allowed as a base.
7099 // PPC only support r+r,
7101 case 0: // "r+i" or just "i", depending on HasBaseReg.
7104 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
7106 // Otherwise we have r+r or r+i.
7109 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
7111 // Allow 2*r as r+r.
7114 // No other scales are supported.
7121 /// isLegalAddressImmediate - Return true if the integer value can be used
7122 /// as the offset of the target addressing mode for load / store of the
7124 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,Type *Ty) const{
7125 // PPC allows a sign-extended 16-bit immediate field.
7126 return (V > -(1 << 16) && V < (1 << 16)-1);
7129 bool PPCTargetLowering::isLegalAddressImmediate(GlobalValue* GV) const {
7133 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
7134 SelectionDAG &DAG) const {
7135 MachineFunction &MF = DAG.getMachineFunction();
7136 MachineFrameInfo *MFI = MF.getFrameInfo();
7137 MFI->setReturnAddressIsTaken(true);
7139 DebugLoc dl = Op.getDebugLoc();
7140 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7142 // Make sure the function does not optimize away the store of the RA to
7144 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
7145 FuncInfo->setLRStoreRequired();
7146 bool isPPC64 = PPCSubTarget.isPPC64();
7147 bool isDarwinABI = PPCSubTarget.isDarwinABI();
7150 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
7153 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
7154 isPPC64? MVT::i64 : MVT::i32);
7155 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7156 DAG.getNode(ISD::ADD, dl, getPointerTy(),
7158 MachinePointerInfo(), false, false, false, 0);
7161 // Just load the return address off the stack.
7162 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
7163 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7164 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
7167 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
7168 SelectionDAG &DAG) const {
7169 DebugLoc dl = Op.getDebugLoc();
7170 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7172 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
7173 bool isPPC64 = PtrVT == MVT::i64;
7175 MachineFunction &MF = DAG.getMachineFunction();
7176 MachineFrameInfo *MFI = MF.getFrameInfo();
7177 MFI->setFrameAddressIsTaken(true);
7179 // Naked functions never have a frame pointer, and so we use r1. For all
7180 // other functions, this decision must be delayed until during PEI.
7182 if (MF.getFunction()->getAttributes().hasAttribute(
7183 AttributeSet::FunctionIndex, Attribute::Naked))
7184 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
7186 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
7188 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
7191 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
7192 FrameAddr, MachinePointerInfo(), false, false,
7198 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
7199 // The PowerPC target isn't yet aware of offsets.
7203 /// getOptimalMemOpType - Returns the target specific optimal type for load
7204 /// and store operations as a result of memset, memcpy, and memmove
7205 /// lowering. If DstAlign is zero that means it's safe to destination
7206 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
7207 /// means there isn't a need to check it against alignment requirement,
7208 /// probably because the source does not need to be loaded. If 'IsMemset' is
7209 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
7210 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
7211 /// source is constant so it does not need to be loaded.
7212 /// It returns EVT::Other if the type should be determined using generic
7213 /// target-independent logic.
7214 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
7215 unsigned DstAlign, unsigned SrcAlign,
7216 bool IsMemset, bool ZeroMemset,
7218 MachineFunction &MF) const {
7219 if (this->PPCSubTarget.isPPC64()) {
7226 bool PPCTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
7228 if (DisablePPCUnaligned)
7231 // PowerPC supports unaligned memory access for simple non-vector types.
7232 // Although accessing unaligned addresses is not as efficient as accessing
7233 // aligned addresses, it is generally more efficient than manual expansion,
7234 // and generally only traps for software emulation when crossing page
7240 if (VT.getSimpleVT().isVector())
7243 if (VT == MVT::ppcf128)
7252 /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than
7253 /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to
7254 /// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd
7255 /// is expanded to mul + add.
7256 bool PPCTargetLowering::isFMAFasterThanMulAndAdd(EVT VT) const {
7260 switch (VT.getSimpleVT().SimpleTy) {
7272 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
7274 return TargetLowering::getSchedulingPreference(N);