1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPerfectShuffle.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCTargetObjectFile.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/StringSwitch.h"
22 #include "llvm/ADT/Triple.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
30 #include "llvm/IR/CallingConv.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/DerivedTypes.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/IR/Intrinsics.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/Target/TargetOptions.h"
42 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
43 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
45 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
46 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
48 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
49 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
51 // FIXME: Remove this once the bug has been fixed!
52 extern cl::opt<bool> ANDIGlueBug;
54 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
55 // If it isn't a Mach-O file then it's going to be a linux ELF
58 return new TargetLoweringObjectFileMachO();
60 return new PPC64LinuxTargetObjectFile();
63 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
64 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))),
65 Subtarget(*TM.getSubtargetImpl()) {
68 // Use _setjmp/_longjmp instead of setjmp/longjmp.
69 setUseUnderscoreSetJmp(true);
70 setUseUnderscoreLongJmp(true);
72 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
73 // arguments are at least 4/8 bytes aligned.
74 bool isPPC64 = Subtarget.isPPC64();
75 setMinStackArgumentAlignment(isPPC64 ? 8:4);
77 // Set up the register classes.
78 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
79 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
80 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
82 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
83 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
84 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
86 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
88 // PowerPC has pre-inc load and store's.
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
91 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
92 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
93 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
100 if (Subtarget.useCRBits()) {
101 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
103 if (isPPC64 || Subtarget.hasFPCVT()) {
104 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
105 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
106 isPPC64 ? MVT::i64 : MVT::i32);
107 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
108 AddPromotedToType (ISD::UINT_TO_FP, MVT::i1,
109 isPPC64 ? MVT::i64 : MVT::i32);
111 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
112 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
115 // PowerPC does not support direct load / store of condition registers
116 setOperationAction(ISD::LOAD, MVT::i1, Custom);
117 setOperationAction(ISD::STORE, MVT::i1, Custom);
119 // FIXME: Remove this once the ANDI glue bug is fixed:
121 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
123 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
124 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
125 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
126 setTruncStoreAction(MVT::i32, MVT::i1, Expand);
127 setTruncStoreAction(MVT::i16, MVT::i1, Expand);
128 setTruncStoreAction(MVT::i8, MVT::i1, Expand);
130 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
133 // This is used in the ppcf128->int sequence. Note it has different semantics
134 // from FP_ROUND: that rounds to nearest, this rounds to zero.
135 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
137 // We do not currently implement these libm ops for PowerPC.
138 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
139 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
140 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
141 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
142 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
143 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
145 // PowerPC has no SREM/UREM instructions
146 setOperationAction(ISD::SREM, MVT::i32, Expand);
147 setOperationAction(ISD::UREM, MVT::i32, Expand);
148 setOperationAction(ISD::SREM, MVT::i64, Expand);
149 setOperationAction(ISD::UREM, MVT::i64, Expand);
151 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
152 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
153 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
154 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
155 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
156 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
157 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
158 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
159 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
161 // We don't support sin/cos/sqrt/fmod/pow
162 setOperationAction(ISD::FSIN , MVT::f64, Expand);
163 setOperationAction(ISD::FCOS , MVT::f64, Expand);
164 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
165 setOperationAction(ISD::FREM , MVT::f64, Expand);
166 setOperationAction(ISD::FPOW , MVT::f64, Expand);
167 setOperationAction(ISD::FMA , MVT::f64, Legal);
168 setOperationAction(ISD::FSIN , MVT::f32, Expand);
169 setOperationAction(ISD::FCOS , MVT::f32, Expand);
170 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
171 setOperationAction(ISD::FREM , MVT::f32, Expand);
172 setOperationAction(ISD::FPOW , MVT::f32, Expand);
173 setOperationAction(ISD::FMA , MVT::f32, Legal);
175 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
177 // If we're enabling GP optimizations, use hardware square root
178 if (!Subtarget.hasFSQRT() &&
179 !(TM.Options.UnsafeFPMath &&
180 Subtarget.hasFRSQRTE() && Subtarget.hasFRE()))
181 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
183 if (!Subtarget.hasFSQRT() &&
184 !(TM.Options.UnsafeFPMath &&
185 Subtarget.hasFRSQRTES() && Subtarget.hasFRES()))
186 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
188 if (Subtarget.hasFCPSGN()) {
189 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
190 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
192 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
193 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
196 if (Subtarget.hasFPRND()) {
197 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
198 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
199 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
200 setOperationAction(ISD::FROUND, MVT::f64, Legal);
202 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
203 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
204 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
205 setOperationAction(ISD::FROUND, MVT::f32, Legal);
208 // PowerPC does not have BSWAP, CTPOP or CTTZ
209 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
210 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
211 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
212 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
213 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
214 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
215 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
216 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
218 if (Subtarget.hasPOPCNTD()) {
219 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
220 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
222 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
223 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
226 // PowerPC does not have ROTR
227 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
228 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
230 if (!Subtarget.useCRBits()) {
231 // PowerPC does not have Select
232 setOperationAction(ISD::SELECT, MVT::i32, Expand);
233 setOperationAction(ISD::SELECT, MVT::i64, Expand);
234 setOperationAction(ISD::SELECT, MVT::f32, Expand);
235 setOperationAction(ISD::SELECT, MVT::f64, Expand);
238 // PowerPC wants to turn select_cc of FP into fsel when possible.
239 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
240 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
242 // PowerPC wants to optimize integer setcc a bit
243 if (!Subtarget.useCRBits())
244 setOperationAction(ISD::SETCC, MVT::i32, Custom);
246 // PowerPC does not have BRCOND which requires SetCC
247 if (!Subtarget.useCRBits())
248 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
250 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
252 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
253 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
255 // PowerPC does not have [U|S]INT_TO_FP
256 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
257 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
259 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
260 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
261 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
262 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
264 // We cannot sextinreg(i1). Expand to shifts.
265 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
267 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
268 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
269 // support continuation, user-level threading, and etc.. As a result, no
270 // other SjLj exception interfaces are implemented and please don't build
271 // your own exception handling based on them.
272 // LLVM/Clang supports zero-cost DWARF exception handling.
273 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
274 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
276 // We want to legalize GlobalAddress and ConstantPool nodes into the
277 // appropriate instructions to materialize the address.
278 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
279 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
280 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
281 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
282 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
283 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
284 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
285 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
286 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
287 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
290 setOperationAction(ISD::TRAP, MVT::Other, Legal);
292 // TRAMPOLINE is custom lowered.
293 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
294 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
296 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
297 setOperationAction(ISD::VASTART , MVT::Other, Custom);
299 if (Subtarget.isSVR4ABI()) {
301 // VAARG always uses double-word chunks, so promote anything smaller.
302 setOperationAction(ISD::VAARG, MVT::i1, Promote);
303 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
304 setOperationAction(ISD::VAARG, MVT::i8, Promote);
305 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
306 setOperationAction(ISD::VAARG, MVT::i16, Promote);
307 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
308 setOperationAction(ISD::VAARG, MVT::i32, Promote);
309 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
310 setOperationAction(ISD::VAARG, MVT::Other, Expand);
312 // VAARG is custom lowered with the 32-bit SVR4 ABI.
313 setOperationAction(ISD::VAARG, MVT::Other, Custom);
314 setOperationAction(ISD::VAARG, MVT::i64, Custom);
317 setOperationAction(ISD::VAARG, MVT::Other, Expand);
319 if (Subtarget.isSVR4ABI() && !isPPC64)
320 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
321 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
323 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
325 // Use the default implementation.
326 setOperationAction(ISD::VAEND , MVT::Other, Expand);
327 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
328 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
329 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
330 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
332 // We want to custom lower some of our intrinsics.
333 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
335 // To handle counter-based loop conditions.
336 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
338 // Comparisons that require checking two conditions.
339 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
340 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
341 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
342 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
343 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
344 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
345 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
346 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
347 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
348 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
349 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
350 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
352 if (Subtarget.has64BitSupport()) {
353 // They also have instructions for converting between i64 and fp.
354 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
355 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
356 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
357 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
358 // This is just the low 32 bits of a (signed) fp->i64 conversion.
359 // We cannot do this with Promote because i64 is not a legal type.
360 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
362 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
363 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
365 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
366 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
369 // With the instructions enabled under FPCVT, we can do everything.
370 if (Subtarget.hasFPCVT()) {
371 if (Subtarget.has64BitSupport()) {
372 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
373 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
374 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
375 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
378 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
379 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
380 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
381 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
384 if (Subtarget.use64BitRegs()) {
385 // 64-bit PowerPC implementations can support i64 types directly
386 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
387 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
388 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
389 // 64-bit PowerPC wants to expand i128 shifts itself.
390 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
391 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
392 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
394 // 32-bit PowerPC wants to expand i64 shifts itself.
395 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
396 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
397 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
400 if (Subtarget.hasAltivec()) {
401 // First set operation action for all vector types to expand. Then we
402 // will selectively turn on ones that can be effectively codegen'd.
403 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
404 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
405 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
407 // add/sub are legal for all supported vector VT's.
408 setOperationAction(ISD::ADD , VT, Legal);
409 setOperationAction(ISD::SUB , VT, Legal);
411 // We promote all shuffles to v16i8.
412 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
413 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
415 // We promote all non-typed operations to v4i32.
416 setOperationAction(ISD::AND , VT, Promote);
417 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
418 setOperationAction(ISD::OR , VT, Promote);
419 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
420 setOperationAction(ISD::XOR , VT, Promote);
421 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
422 setOperationAction(ISD::LOAD , VT, Promote);
423 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
424 setOperationAction(ISD::SELECT, VT, Promote);
425 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
426 setOperationAction(ISD::STORE, VT, Promote);
427 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
429 // No other operations are legal.
430 setOperationAction(ISD::MUL , VT, Expand);
431 setOperationAction(ISD::SDIV, VT, Expand);
432 setOperationAction(ISD::SREM, VT, Expand);
433 setOperationAction(ISD::UDIV, VT, Expand);
434 setOperationAction(ISD::UREM, VT, Expand);
435 setOperationAction(ISD::FDIV, VT, Expand);
436 setOperationAction(ISD::FREM, VT, Expand);
437 setOperationAction(ISD::FNEG, VT, Expand);
438 setOperationAction(ISD::FSQRT, VT, Expand);
439 setOperationAction(ISD::FLOG, VT, Expand);
440 setOperationAction(ISD::FLOG10, VT, Expand);
441 setOperationAction(ISD::FLOG2, VT, Expand);
442 setOperationAction(ISD::FEXP, VT, Expand);
443 setOperationAction(ISD::FEXP2, VT, Expand);
444 setOperationAction(ISD::FSIN, VT, Expand);
445 setOperationAction(ISD::FCOS, VT, Expand);
446 setOperationAction(ISD::FABS, VT, Expand);
447 setOperationAction(ISD::FPOWI, VT, Expand);
448 setOperationAction(ISD::FFLOOR, VT, Expand);
449 setOperationAction(ISD::FCEIL, VT, Expand);
450 setOperationAction(ISD::FTRUNC, VT, Expand);
451 setOperationAction(ISD::FRINT, VT, Expand);
452 setOperationAction(ISD::FNEARBYINT, VT, Expand);
453 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
454 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
455 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
456 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
457 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
458 setOperationAction(ISD::UDIVREM, VT, Expand);
459 setOperationAction(ISD::SDIVREM, VT, Expand);
460 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
461 setOperationAction(ISD::FPOW, VT, Expand);
462 setOperationAction(ISD::BSWAP, VT, Expand);
463 setOperationAction(ISD::CTPOP, VT, Expand);
464 setOperationAction(ISD::CTLZ, VT, Expand);
465 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
466 setOperationAction(ISD::CTTZ, VT, Expand);
467 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
468 setOperationAction(ISD::VSELECT, VT, Expand);
469 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
471 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
472 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
473 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
474 setTruncStoreAction(VT, InnerVT, Expand);
476 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
477 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
478 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
481 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
482 // with merges, splats, etc.
483 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
485 setOperationAction(ISD::AND , MVT::v4i32, Legal);
486 setOperationAction(ISD::OR , MVT::v4i32, Legal);
487 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
488 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
489 setOperationAction(ISD::SELECT, MVT::v4i32,
490 Subtarget.useCRBits() ? Legal : Expand);
491 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
492 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
493 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
494 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
495 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
496 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
497 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
498 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
499 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
501 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
502 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
503 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
504 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
506 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
507 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
509 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
510 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
511 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
514 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
515 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
516 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
518 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
519 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
521 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
522 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
523 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
524 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
526 // Altivec does not contain unordered floating-point compare instructions
527 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
528 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
529 setCondCodeAction(ISD::SETUGT, MVT::v4f32, Expand);
530 setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand);
531 setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand);
532 setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand);
534 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
535 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
537 if (Subtarget.hasVSX()) {
538 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
539 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
541 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
542 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
543 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
544 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
545 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
547 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
549 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
550 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
552 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
553 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
555 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
556 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
557 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
558 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
559 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
561 // Share the Altivec comparison restrictions.
562 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
563 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
564 setCondCodeAction(ISD::SETUGT, MVT::v2f64, Expand);
565 setCondCodeAction(ISD::SETUGE, MVT::v2f64, Expand);
566 setCondCodeAction(ISD::SETULT, MVT::v2f64, Expand);
567 setCondCodeAction(ISD::SETULE, MVT::v2f64, Expand);
569 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
570 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
572 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
573 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
575 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
577 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
579 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
580 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
582 // VSX v2i64 only supports non-arithmetic operations.
583 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
584 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
586 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
587 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
588 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
590 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
592 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
593 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
594 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
595 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
597 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
599 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
600 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
601 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
602 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
604 // Vector operation legalization checks the result type of
605 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
606 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
607 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
608 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
609 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
611 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
615 if (Subtarget.has64BitSupport()) {
616 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
617 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
620 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
621 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
622 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
623 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
625 setBooleanContents(ZeroOrOneBooleanContent);
626 // Altivec instructions set fields to all zeros or all ones.
627 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
630 // These libcalls are not available in 32-bit.
631 setLibcallName(RTLIB::SHL_I128, nullptr);
632 setLibcallName(RTLIB::SRL_I128, nullptr);
633 setLibcallName(RTLIB::SRA_I128, nullptr);
637 setStackPointerRegisterToSaveRestore(PPC::X1);
638 setExceptionPointerRegister(PPC::X3);
639 setExceptionSelectorRegister(PPC::X4);
641 setStackPointerRegisterToSaveRestore(PPC::R1);
642 setExceptionPointerRegister(PPC::R3);
643 setExceptionSelectorRegister(PPC::R4);
646 // We have target-specific dag combine patterns for the following nodes:
647 setTargetDAGCombine(ISD::SINT_TO_FP);
648 setTargetDAGCombine(ISD::LOAD);
649 setTargetDAGCombine(ISD::STORE);
650 setTargetDAGCombine(ISD::BR_CC);
651 if (Subtarget.useCRBits())
652 setTargetDAGCombine(ISD::BRCOND);
653 setTargetDAGCombine(ISD::BSWAP);
654 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
656 setTargetDAGCombine(ISD::SIGN_EXTEND);
657 setTargetDAGCombine(ISD::ZERO_EXTEND);
658 setTargetDAGCombine(ISD::ANY_EXTEND);
660 if (Subtarget.useCRBits()) {
661 setTargetDAGCombine(ISD::TRUNCATE);
662 setTargetDAGCombine(ISD::SETCC);
663 setTargetDAGCombine(ISD::SELECT_CC);
666 // Use reciprocal estimates.
667 if (TM.Options.UnsafeFPMath) {
668 setTargetDAGCombine(ISD::FDIV);
669 setTargetDAGCombine(ISD::FSQRT);
672 // Darwin long double math library functions have $LDBL128 appended.
673 if (Subtarget.isDarwin()) {
674 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
675 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
676 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
677 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
678 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
679 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
680 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
681 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
682 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
683 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
686 // With 32 condition bits, we don't need to sink (and duplicate) compares
687 // aggressively in CodeGenPrep.
688 if (Subtarget.useCRBits())
689 setHasMultipleConditionRegisters();
691 setMinFunctionAlignment(2);
692 if (Subtarget.isDarwin())
693 setPrefFunctionAlignment(4);
695 if (isPPC64 && Subtarget.isJITCodeModel())
696 // Temporary workaround for the inability of PPC64 JIT to handle jump
698 setSupportJumpTables(false);
700 setInsertFencesForAtomic(true);
702 if (Subtarget.enableMachineScheduler())
703 setSchedulingPreference(Sched::Source);
705 setSchedulingPreference(Sched::Hybrid);
707 computeRegisterProperties();
709 // The Freescale cores does better with aggressive inlining of memcpy and
710 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores).
711 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
712 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
713 MaxStoresPerMemset = 32;
714 MaxStoresPerMemsetOptSize = 16;
715 MaxStoresPerMemcpy = 32;
716 MaxStoresPerMemcpyOptSize = 8;
717 MaxStoresPerMemmove = 32;
718 MaxStoresPerMemmoveOptSize = 8;
720 setPrefFunctionAlignment(4);
724 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
725 /// the desired ByVal argument alignment.
726 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
727 unsigned MaxMaxAlign) {
728 if (MaxAlign == MaxMaxAlign)
730 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
731 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
733 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
735 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
736 unsigned EltAlign = 0;
737 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
738 if (EltAlign > MaxAlign)
740 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
741 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
742 unsigned EltAlign = 0;
743 getMaxByValAlign(STy->getElementType(i), EltAlign, MaxMaxAlign);
744 if (EltAlign > MaxAlign)
746 if (MaxAlign == MaxMaxAlign)
752 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
753 /// function arguments in the caller parameter area.
754 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
755 // Darwin passes everything on 4 byte boundary.
756 if (Subtarget.isDarwin())
759 // 16byte and wider vectors are passed on 16byte boundary.
760 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
761 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
762 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
763 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
767 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
769 default: return nullptr;
770 case PPCISD::FSEL: return "PPCISD::FSEL";
771 case PPCISD::FCFID: return "PPCISD::FCFID";
772 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
773 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
774 case PPCISD::FRE: return "PPCISD::FRE";
775 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
776 case PPCISD::STFIWX: return "PPCISD::STFIWX";
777 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
778 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
779 case PPCISD::VPERM: return "PPCISD::VPERM";
780 case PPCISD::Hi: return "PPCISD::Hi";
781 case PPCISD::Lo: return "PPCISD::Lo";
782 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
783 case PPCISD::LOAD: return "PPCISD::LOAD";
784 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
785 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
786 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
787 case PPCISD::SRL: return "PPCISD::SRL";
788 case PPCISD::SRA: return "PPCISD::SRA";
789 case PPCISD::SHL: return "PPCISD::SHL";
790 case PPCISD::CALL: return "PPCISD::CALL";
791 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
792 case PPCISD::MTCTR: return "PPCISD::MTCTR";
793 case PPCISD::BCTRL: return "PPCISD::BCTRL";
794 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
795 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
796 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
797 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
798 case PPCISD::VCMP: return "PPCISD::VCMP";
799 case PPCISD::VCMPo: return "PPCISD::VCMPo";
800 case PPCISD::LBRX: return "PPCISD::LBRX";
801 case PPCISD::STBRX: return "PPCISD::STBRX";
802 case PPCISD::LARX: return "PPCISD::LARX";
803 case PPCISD::STCX: return "PPCISD::STCX";
804 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
805 case PPCISD::BDNZ: return "PPCISD::BDNZ";
806 case PPCISD::BDZ: return "PPCISD::BDZ";
807 case PPCISD::MFFS: return "PPCISD::MFFS";
808 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
809 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
810 case PPCISD::CR6SET: return "PPCISD::CR6SET";
811 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
812 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
813 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
814 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
815 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
816 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
817 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
818 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
819 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
820 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
821 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
822 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
823 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
824 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
825 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
826 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
827 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
828 case PPCISD::SC: return "PPCISD::SC";
832 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
834 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
835 return VT.changeVectorElementTypeToInteger();
838 //===----------------------------------------------------------------------===//
839 // Node matching predicates, for use by the tblgen matching code.
840 //===----------------------------------------------------------------------===//
842 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
843 static bool isFloatingPointZero(SDValue Op) {
844 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
845 return CFP->getValueAPF().isZero();
846 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
847 // Maybe this has already been legalized into the constant pool?
848 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
849 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
850 return CFP->getValueAPF().isZero();
855 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
856 /// true if Op is undef or if it matches the specified value.
857 static bool isConstantOrUndef(int Op, int Val) {
858 return Op < 0 || Op == Val;
861 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
862 /// VPKUHUM instruction.
863 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary,
865 unsigned j = DAG.getTarget().getDataLayout()->isLittleEndian() ? 0 : 1;
867 for (unsigned i = 0; i != 16; ++i)
868 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j))
871 for (unsigned i = 0; i != 8; ++i)
872 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
873 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
879 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
880 /// VPKUWUM instruction.
881 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary,
884 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
892 for (unsigned i = 0; i != 16; i += 2)
893 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
894 !isConstantOrUndef(N->getMaskElt(i+1), i*2+k))
897 for (unsigned i = 0; i != 8; i += 2)
898 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
899 !isConstantOrUndef(N->getMaskElt(i+1), i*2+k) ||
900 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
901 !isConstantOrUndef(N->getMaskElt(i+9), i*2+k))
907 /// isVMerge - Common function, used to match vmrg* shuffles.
909 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
910 unsigned LHSStart, unsigned RHSStart) {
911 if (N->getValueType(0) != MVT::v16i8)
913 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
914 "Unsupported merge size!");
916 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
917 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
918 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
919 LHSStart+j+i*UnitSize) ||
920 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
921 RHSStart+j+i*UnitSize))
927 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
928 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
929 /// The ShuffleKind distinguishes between big-endian merges with two
930 /// different inputs (0), either-endian merges with two identical inputs (1),
931 /// and little-endian merges with two different inputs (2). For the latter,
932 /// the input operands are swapped (see PPCInstrAltivec.td).
933 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
934 unsigned ShuffleKind, SelectionDAG &DAG) {
935 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
936 if (ShuffleKind == 1) // unary
937 return isVMerge(N, UnitSize, 0, 0);
938 else if (ShuffleKind == 2) // swapped
939 return isVMerge(N, UnitSize, 0, 16);
943 if (ShuffleKind == 1) // unary
944 return isVMerge(N, UnitSize, 8, 8);
945 else if (ShuffleKind == 0) // normal
946 return isVMerge(N, UnitSize, 8, 24);
952 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
953 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
954 /// The ShuffleKind distinguishes between big-endian merges with two
955 /// different inputs (0), either-endian merges with two identical inputs (1),
956 /// and little-endian merges with two different inputs (2). For the latter,
957 /// the input operands are swapped (see PPCInstrAltivec.td).
958 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
959 unsigned ShuffleKind, SelectionDAG &DAG) {
960 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
961 if (ShuffleKind == 1) // unary
962 return isVMerge(N, UnitSize, 8, 8);
963 else if (ShuffleKind == 2) // swapped
964 return isVMerge(N, UnitSize, 8, 24);
968 if (ShuffleKind == 1) // unary
969 return isVMerge(N, UnitSize, 0, 0);
970 else if (ShuffleKind == 0) // normal
971 return isVMerge(N, UnitSize, 0, 16);
978 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
979 /// amount, otherwise return -1.
980 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary, SelectionDAG &DAG) {
981 if (N->getValueType(0) != MVT::v16i8)
984 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
986 // Find the first non-undef value in the shuffle mask.
988 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
991 if (i == 16) return -1; // all undef.
993 // Otherwise, check to see if the rest of the elements are consecutively
994 // numbered from this value.
995 unsigned ShiftAmt = SVOp->getMaskElt(i);
996 if (ShiftAmt < i) return -1;
998 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
1003 // Check the rest of the elements to see if they are consecutive.
1004 for (++i; i != 16; ++i)
1005 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt - i))
1008 // Check the rest of the elements to see if they are consecutive.
1009 for (++i; i != 16; ++i)
1010 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt - i) & 15))
1014 } else { // Big Endian
1019 // Check the rest of the elements to see if they are consecutive.
1020 for (++i; i != 16; ++i)
1021 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1024 // Check the rest of the elements to see if they are consecutive.
1025 for (++i; i != 16; ++i)
1026 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1033 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1034 /// specifies a splat of a single element that is suitable for input to
1035 /// VSPLTB/VSPLTH/VSPLTW.
1036 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1037 assert(N->getValueType(0) == MVT::v16i8 &&
1038 (EltSize == 1 || EltSize == 2 || EltSize == 4));
1040 // This is a splat operation if each element of the permute is the same, and
1041 // if the value doesn't reference the second vector.
1042 unsigned ElementBase = N->getMaskElt(0);
1044 // FIXME: Handle UNDEF elements too!
1045 if (ElementBase >= 16)
1048 // Check that the indices are consecutive, in the case of a multi-byte element
1049 // splatted with a v16i8 mask.
1050 for (unsigned i = 1; i != EltSize; ++i)
1051 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1054 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1055 if (N->getMaskElt(i) < 0) continue;
1056 for (unsigned j = 0; j != EltSize; ++j)
1057 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1063 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
1065 bool PPC::isAllNegativeZeroVector(SDNode *N) {
1066 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
1068 APInt APVal, APUndef;
1072 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
1073 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
1074 return CFP->getValueAPF().isNegZero();
1079 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1080 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1081 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1082 SelectionDAG &DAG) {
1083 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1084 assert(isSplatShuffleMask(SVOp, EltSize));
1085 if (DAG.getTarget().getDataLayout()->isLittleEndian())
1086 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1088 return SVOp->getMaskElt(0) / EltSize;
1091 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1092 /// by using a vspltis[bhw] instruction of the specified element size, return
1093 /// the constant being splatted. The ByteSize field indicates the number of
1094 /// bytes of each element [124] -> [bhw].
1095 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1096 SDValue OpVal(nullptr, 0);
1098 // If ByteSize of the splat is bigger than the element size of the
1099 // build_vector, then we have a case where we are checking for a splat where
1100 // multiple elements of the buildvector are folded together into a single
1101 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1102 unsigned EltSize = 16/N->getNumOperands();
1103 if (EltSize < ByteSize) {
1104 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1105 SDValue UniquedVals[4];
1106 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1108 // See if all of the elements in the buildvector agree across.
1109 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1110 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1111 // If the element isn't a constant, bail fully out.
1112 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1115 if (!UniquedVals[i&(Multiple-1)].getNode())
1116 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1117 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1118 return SDValue(); // no match.
1121 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1122 // either constant or undef values that are identical for each chunk. See
1123 // if these chunks can form into a larger vspltis*.
1125 // Check to see if all of the leading entries are either 0 or -1. If
1126 // neither, then this won't fit into the immediate field.
1127 bool LeadingZero = true;
1128 bool LeadingOnes = true;
1129 for (unsigned i = 0; i != Multiple-1; ++i) {
1130 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1132 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
1133 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
1135 // Finally, check the least significant entry.
1137 if (!UniquedVals[Multiple-1].getNode())
1138 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
1139 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1141 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
1144 if (!UniquedVals[Multiple-1].getNode())
1145 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
1146 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1147 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1148 return DAG.getTargetConstant(Val, MVT::i32);
1154 // Check to see if this buildvec has a single non-undef value in its elements.
1155 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1156 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1157 if (!OpVal.getNode())
1158 OpVal = N->getOperand(i);
1159 else if (OpVal != N->getOperand(i))
1163 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1165 unsigned ValSizeInBytes = EltSize;
1167 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1168 Value = CN->getZExtValue();
1169 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1170 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1171 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1174 // If the splat value is larger than the element value, then we can never do
1175 // this splat. The only case that we could fit the replicated bits into our
1176 // immediate field for would be zero, and we prefer to use vxor for it.
1177 if (ValSizeInBytes < ByteSize) return SDValue();
1179 // If the element value is larger than the splat value, cut it in half and
1180 // check to see if the two halves are equal. Continue doing this until we
1181 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
1182 while (ValSizeInBytes > ByteSize) {
1183 ValSizeInBytes >>= 1;
1185 // If the top half equals the bottom half, we're still ok.
1186 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
1187 (Value & ((1 << (8*ValSizeInBytes))-1)))
1191 // Properly sign extend the value.
1192 int MaskVal = SignExtend32(Value, ByteSize * 8);
1194 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1195 if (MaskVal == 0) return SDValue();
1197 // Finally, if this value fits in a 5 bit sext field, return it
1198 if (SignExtend32<5>(MaskVal) == MaskVal)
1199 return DAG.getTargetConstant(MaskVal, MVT::i32);
1203 //===----------------------------------------------------------------------===//
1204 // Addressing Mode Selection
1205 //===----------------------------------------------------------------------===//
1207 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1208 /// or 64-bit immediate, and if the value can be accurately represented as a
1209 /// sign extension from a 16-bit value. If so, this returns true and the
1211 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1212 if (!isa<ConstantSDNode>(N))
1215 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1216 if (N->getValueType(0) == MVT::i32)
1217 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1219 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1221 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1222 return isIntS16Immediate(Op.getNode(), Imm);
1226 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1227 /// can be represented as an indexed [r+r] operation. Returns false if it
1228 /// can be more efficiently represented with [r+imm].
1229 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1231 SelectionDAG &DAG) const {
1233 if (N.getOpcode() == ISD::ADD) {
1234 if (isIntS16Immediate(N.getOperand(1), imm))
1235 return false; // r+i
1236 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1237 return false; // r+i
1239 Base = N.getOperand(0);
1240 Index = N.getOperand(1);
1242 } else if (N.getOpcode() == ISD::OR) {
1243 if (isIntS16Immediate(N.getOperand(1), imm))
1244 return false; // r+i can fold it if we can.
1246 // If this is an or of disjoint bitfields, we can codegen this as an add
1247 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1249 APInt LHSKnownZero, LHSKnownOne;
1250 APInt RHSKnownZero, RHSKnownOne;
1251 DAG.computeKnownBits(N.getOperand(0),
1252 LHSKnownZero, LHSKnownOne);
1254 if (LHSKnownZero.getBoolValue()) {
1255 DAG.computeKnownBits(N.getOperand(1),
1256 RHSKnownZero, RHSKnownOne);
1257 // If all of the bits are known zero on the LHS or RHS, the add won't
1259 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1260 Base = N.getOperand(0);
1261 Index = N.getOperand(1);
1270 // If we happen to be doing an i64 load or store into a stack slot that has
1271 // less than a 4-byte alignment, then the frame-index elimination may need to
1272 // use an indexed load or store instruction (because the offset may not be a
1273 // multiple of 4). The extra register needed to hold the offset comes from the
1274 // register scavenger, and it is possible that the scavenger will need to use
1275 // an emergency spill slot. As a result, we need to make sure that a spill slot
1276 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1278 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1279 // FIXME: This does not handle the LWA case.
1283 // NOTE: We'll exclude negative FIs here, which come from argument
1284 // lowering, because there are no known test cases triggering this problem
1285 // using packed structures (or similar). We can remove this exclusion if
1286 // we find such a test case. The reason why this is so test-case driven is
1287 // because this entire 'fixup' is only to prevent crashes (from the
1288 // register scavenger) on not-really-valid inputs. For example, if we have:
1290 // %b = bitcast i1* %a to i64*
1291 // store i64* a, i64 b
1292 // then the store should really be marked as 'align 1', but is not. If it
1293 // were marked as 'align 1' then the indexed form would have been
1294 // instruction-selected initially, and the problem this 'fixup' is preventing
1295 // won't happen regardless.
1299 MachineFunction &MF = DAG.getMachineFunction();
1300 MachineFrameInfo *MFI = MF.getFrameInfo();
1302 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1306 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1307 FuncInfo->setHasNonRISpills();
1310 /// Returns true if the address N can be represented by a base register plus
1311 /// a signed 16-bit displacement [r+imm], and if it is not better
1312 /// represented as reg+reg. If Aligned is true, only accept displacements
1313 /// suitable for STD and friends, i.e. multiples of 4.
1314 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1317 bool Aligned) const {
1318 // FIXME dl should come from parent load or store, not from address
1320 // If this can be more profitably realized as r+r, fail.
1321 if (SelectAddressRegReg(N, Disp, Base, DAG))
1324 if (N.getOpcode() == ISD::ADD) {
1326 if (isIntS16Immediate(N.getOperand(1), imm) &&
1327 (!Aligned || (imm & 3) == 0)) {
1328 Disp = DAG.getTargetConstant(imm, N.getValueType());
1329 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1330 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1331 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1333 Base = N.getOperand(0);
1335 return true; // [r+i]
1336 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1337 // Match LOAD (ADD (X, Lo(G))).
1338 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1339 && "Cannot handle constant offsets yet!");
1340 Disp = N.getOperand(1).getOperand(0); // The global address.
1341 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1342 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1343 Disp.getOpcode() == ISD::TargetConstantPool ||
1344 Disp.getOpcode() == ISD::TargetJumpTable);
1345 Base = N.getOperand(0);
1346 return true; // [&g+r]
1348 } else if (N.getOpcode() == ISD::OR) {
1350 if (isIntS16Immediate(N.getOperand(1), imm) &&
1351 (!Aligned || (imm & 3) == 0)) {
1352 // If this is an or of disjoint bitfields, we can codegen this as an add
1353 // (for better address arithmetic) if the LHS and RHS of the OR are
1354 // provably disjoint.
1355 APInt LHSKnownZero, LHSKnownOne;
1356 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1358 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1359 // If all of the bits are known zero on the LHS or RHS, the add won't
1361 if (FrameIndexSDNode *FI =
1362 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1363 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1364 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1366 Base = N.getOperand(0);
1368 Disp = DAG.getTargetConstant(imm, N.getValueType());
1372 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1373 // Loading from a constant address.
1375 // If this address fits entirely in a 16-bit sext immediate field, codegen
1378 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1379 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1380 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1381 CN->getValueType(0));
1385 // Handle 32-bit sext immediates with LIS + addr mode.
1386 if ((CN->getValueType(0) == MVT::i32 ||
1387 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1388 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1389 int Addr = (int)CN->getZExtValue();
1391 // Otherwise, break this down into an LIS + disp.
1392 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1394 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1395 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1396 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1401 Disp = DAG.getTargetConstant(0, getPointerTy());
1402 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1403 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1404 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1407 return true; // [r+0]
1410 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1411 /// represented as an indexed [r+r] operation.
1412 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1414 SelectionDAG &DAG) const {
1415 // Check to see if we can easily represent this as an [r+r] address. This
1416 // will fail if it thinks that the address is more profitably represented as
1417 // reg+imm, e.g. where imm = 0.
1418 if (SelectAddressRegReg(N, Base, Index, DAG))
1421 // If the operand is an addition, always emit this as [r+r], since this is
1422 // better (for code size, and execution, as the memop does the add for free)
1423 // than emitting an explicit add.
1424 if (N.getOpcode() == ISD::ADD) {
1425 Base = N.getOperand(0);
1426 Index = N.getOperand(1);
1430 // Otherwise, do it the hard way, using R0 as the base register.
1431 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1437 /// getPreIndexedAddressParts - returns true by value, base pointer and
1438 /// offset pointer and addressing mode by reference if the node's address
1439 /// can be legally represented as pre-indexed load / store address.
1440 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1442 ISD::MemIndexedMode &AM,
1443 SelectionDAG &DAG) const {
1444 if (DisablePPCPreinc) return false;
1450 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1451 Ptr = LD->getBasePtr();
1452 VT = LD->getMemoryVT();
1453 Alignment = LD->getAlignment();
1454 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1455 Ptr = ST->getBasePtr();
1456 VT = ST->getMemoryVT();
1457 Alignment = ST->getAlignment();
1462 // PowerPC doesn't have preinc load/store instructions for vectors.
1466 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1468 // Common code will reject creating a pre-inc form if the base pointer
1469 // is a frame index, or if N is a store and the base pointer is either
1470 // the same as or a predecessor of the value being stored. Check for
1471 // those situations here, and try with swapped Base/Offset instead.
1474 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1477 SDValue Val = cast<StoreSDNode>(N)->getValue();
1478 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1483 std::swap(Base, Offset);
1489 // LDU/STU can only handle immediates that are a multiple of 4.
1490 if (VT != MVT::i64) {
1491 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1494 // LDU/STU need an address with at least 4-byte alignment.
1498 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1502 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1503 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1504 // sext i32 to i64 when addr mode is r+i.
1505 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1506 LD->getExtensionType() == ISD::SEXTLOAD &&
1507 isa<ConstantSDNode>(Offset))
1515 //===----------------------------------------------------------------------===//
1516 // LowerOperation implementation
1517 //===----------------------------------------------------------------------===//
1519 /// GetLabelAccessInfo - Return true if we should reference labels using a
1520 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1521 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1522 unsigned &LoOpFlags,
1523 const GlobalValue *GV = nullptr) {
1524 HiOpFlags = PPCII::MO_HA;
1525 LoOpFlags = PPCII::MO_LO;
1527 // Don't use the pic base if not in PIC relocation model.
1528 bool isPIC = TM.getRelocationModel() == Reloc::PIC_;
1531 HiOpFlags |= PPCII::MO_PIC_FLAG;
1532 LoOpFlags |= PPCII::MO_PIC_FLAG;
1535 // If this is a reference to a global value that requires a non-lazy-ptr, make
1536 // sure that instruction lowering adds it.
1537 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1538 HiOpFlags |= PPCII::MO_NLP_FLAG;
1539 LoOpFlags |= PPCII::MO_NLP_FLAG;
1541 if (GV->hasHiddenVisibility()) {
1542 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1543 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1550 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1551 SelectionDAG &DAG) {
1552 EVT PtrVT = HiPart.getValueType();
1553 SDValue Zero = DAG.getConstant(0, PtrVT);
1556 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1557 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1559 // With PIC, the first instruction is actually "GR+hi(&G)".
1561 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1562 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1564 // Generate non-pic code that has direct accesses to the constant pool.
1565 // The address of the global is just (hi(&g)+lo(&g)).
1566 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1569 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1570 SelectionDAG &DAG) const {
1571 EVT PtrVT = Op.getValueType();
1572 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1573 const Constant *C = CP->getConstVal();
1575 // 64-bit SVR4 ABI code is always position-independent.
1576 // The actual address of the GlobalValue is stored in the TOC.
1577 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1578 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1579 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1580 DAG.getRegister(PPC::X2, MVT::i64));
1583 unsigned MOHiFlag, MOLoFlag;
1584 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1586 if (isPIC && Subtarget.isSVR4ABI()) {
1587 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
1588 PPCII::MO_PIC_FLAG);
1590 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1591 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1595 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1597 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1598 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1601 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1602 EVT PtrVT = Op.getValueType();
1603 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1605 // 64-bit SVR4 ABI code is always position-independent.
1606 // The actual address of the GlobalValue is stored in the TOC.
1607 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1608 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1609 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1610 DAG.getRegister(PPC::X2, MVT::i64));
1613 unsigned MOHiFlag, MOLoFlag;
1614 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1616 if (isPIC && Subtarget.isSVR4ABI()) {
1617 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
1618 PPCII::MO_PIC_FLAG);
1620 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), PtrVT, GA,
1621 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1624 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1625 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1626 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1629 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1630 SelectionDAG &DAG) const {
1631 EVT PtrVT = Op.getValueType();
1633 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1635 unsigned MOHiFlag, MOLoFlag;
1636 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1637 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1638 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1639 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1642 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1643 SelectionDAG &DAG) const {
1645 // FIXME: TLS addresses currently use medium model code sequences,
1646 // which is the most useful form. Eventually support for small and
1647 // large models could be added if users need it, at the cost of
1648 // additional complexity.
1649 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1651 const GlobalValue *GV = GA->getGlobal();
1652 EVT PtrVT = getPointerTy();
1653 bool is64bit = Subtarget.isPPC64();
1655 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1657 if (Model == TLSModel::LocalExec) {
1658 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1659 PPCII::MO_TPREL_HA);
1660 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1661 PPCII::MO_TPREL_LO);
1662 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1663 is64bit ? MVT::i64 : MVT::i32);
1664 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1665 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1668 if (Model == TLSModel::InitialExec) {
1669 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1670 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1674 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1675 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1676 PtrVT, GOTReg, TGA);
1678 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
1679 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1680 PtrVT, TGA, GOTPtr);
1681 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
1684 if (Model == TLSModel::GeneralDynamic) {
1685 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1686 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1687 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1689 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1692 // We need a chain node, and don't have one handy. The underlying
1693 // call has no side effects, so using the function entry node
1695 SDValue Chain = DAG.getEntryNode();
1696 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1697 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1698 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl,
1699 PtrVT, ParmReg, TGA);
1700 // The return value from GET_TLS_ADDR really is in X3 already, but
1701 // some hacks are needed here to tie everything together. The extra
1702 // copies dissolve during subsequent transforms.
1703 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1704 return DAG.getCopyFromReg(Chain, dl, PPC::X3, PtrVT);
1707 if (Model == TLSModel::LocalDynamic) {
1708 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1709 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1710 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1712 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1715 // We need a chain node, and don't have one handy. The underlying
1716 // call has no side effects, so using the function entry node
1718 SDValue Chain = DAG.getEntryNode();
1719 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1720 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1721 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl,
1722 PtrVT, ParmReg, TGA);
1723 // The return value from GET_TLSLD_ADDR really is in X3 already, but
1724 // some hacks are needed here to tie everything together. The extra
1725 // copies dissolve during subsequent transforms.
1726 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1727 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1728 Chain, ParmReg, TGA);
1729 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1732 llvm_unreachable("Unknown TLS model!");
1735 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1736 SelectionDAG &DAG) const {
1737 EVT PtrVT = Op.getValueType();
1738 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1740 const GlobalValue *GV = GSDN->getGlobal();
1742 // 64-bit SVR4 ABI code is always position-independent.
1743 // The actual address of the GlobalValue is stored in the TOC.
1744 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1745 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1746 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1747 DAG.getRegister(PPC::X2, MVT::i64));
1750 unsigned MOHiFlag, MOLoFlag;
1751 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1753 if (isPIC && Subtarget.isSVR4ABI()) {
1754 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
1756 PPCII::MO_PIC_FLAG);
1757 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1758 DAG.getNode(PPCISD::GlobalBaseReg, DL, MVT::i32));
1762 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1764 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1766 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1768 // If the global reference is actually to a non-lazy-pointer, we have to do an
1769 // extra load to get the address of the global.
1770 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1771 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1772 false, false, false, 0);
1776 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1777 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1780 if (Op.getValueType() == MVT::v2i64) {
1781 // When the operands themselves are v2i64 values, we need to do something
1782 // special because VSX has no underlying comparison operations for these.
1783 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
1784 // Equality can be handled by casting to the legal type for Altivec
1785 // comparisons, everything else needs to be expanded.
1786 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1787 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
1788 DAG.getSetCC(dl, MVT::v4i32,
1789 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
1790 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
1797 // We handle most of these in the usual way.
1801 // If we're comparing for equality to zero, expose the fact that this is
1802 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1803 // fold the new nodes.
1804 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1805 if (C->isNullValue() && CC == ISD::SETEQ) {
1806 EVT VT = Op.getOperand(0).getValueType();
1807 SDValue Zext = Op.getOperand(0);
1808 if (VT.bitsLT(MVT::i32)) {
1810 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1812 unsigned Log2b = Log2_32(VT.getSizeInBits());
1813 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1814 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1815 DAG.getConstant(Log2b, MVT::i32));
1816 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1818 // Leave comparisons against 0 and -1 alone for now, since they're usually
1819 // optimized. FIXME: revisit this when we can custom lower all setcc
1821 if (C->isAllOnesValue() || C->isNullValue())
1825 // If we have an integer seteq/setne, turn it into a compare against zero
1826 // by xor'ing the rhs with the lhs, which is faster than setting a
1827 // condition register, reading it back out, and masking the correct bit. The
1828 // normal approach here uses sub to do this instead of xor. Using xor exposes
1829 // the result to other bit-twiddling opportunities.
1830 EVT LHSVT = Op.getOperand(0).getValueType();
1831 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1832 EVT VT = Op.getValueType();
1833 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1835 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1840 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1841 const PPCSubtarget &Subtarget) const {
1842 SDNode *Node = Op.getNode();
1843 EVT VT = Node->getValueType(0);
1844 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1845 SDValue InChain = Node->getOperand(0);
1846 SDValue VAListPtr = Node->getOperand(1);
1847 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1850 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1853 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1854 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1856 InChain = GprIndex.getValue(1);
1858 if (VT == MVT::i64) {
1859 // Check if GprIndex is even
1860 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1861 DAG.getConstant(1, MVT::i32));
1862 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1863 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1864 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1865 DAG.getConstant(1, MVT::i32));
1866 // Align GprIndex to be even if it isn't
1867 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1871 // fpr index is 1 byte after gpr
1872 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1873 DAG.getConstant(1, MVT::i32));
1876 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1877 FprPtr, MachinePointerInfo(SV), MVT::i8,
1879 InChain = FprIndex.getValue(1);
1881 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1882 DAG.getConstant(8, MVT::i32));
1884 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1885 DAG.getConstant(4, MVT::i32));
1888 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1889 MachinePointerInfo(), false, false,
1891 InChain = OverflowArea.getValue(1);
1893 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1894 MachinePointerInfo(), false, false,
1896 InChain = RegSaveArea.getValue(1);
1898 // select overflow_area if index > 8
1899 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1900 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1902 // adjustment constant gpr_index * 4/8
1903 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1904 VT.isInteger() ? GprIndex : FprIndex,
1905 DAG.getConstant(VT.isInteger() ? 4 : 8,
1908 // OurReg = RegSaveArea + RegConstant
1909 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1912 // Floating types are 32 bytes into RegSaveArea
1913 if (VT.isFloatingPoint())
1914 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1915 DAG.getConstant(32, MVT::i32));
1917 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1918 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1919 VT.isInteger() ? GprIndex : FprIndex,
1920 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1923 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1924 VT.isInteger() ? VAListPtr : FprPtr,
1925 MachinePointerInfo(SV),
1926 MVT::i8, false, false, 0);
1928 // determine if we should load from reg_save_area or overflow_area
1929 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1931 // increase overflow_area by 4/8 if gpr/fpr > 8
1932 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1933 DAG.getConstant(VT.isInteger() ? 4 : 8,
1936 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1939 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1941 MachinePointerInfo(),
1942 MVT::i32, false, false, 0);
1944 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1945 false, false, false, 0);
1948 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
1949 const PPCSubtarget &Subtarget) const {
1950 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
1952 // We have to copy the entire va_list struct:
1953 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
1954 return DAG.getMemcpy(Op.getOperand(0), Op,
1955 Op.getOperand(1), Op.getOperand(2),
1956 DAG.getConstant(12, MVT::i32), 8, false, true,
1957 MachinePointerInfo(), MachinePointerInfo());
1960 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
1961 SelectionDAG &DAG) const {
1962 return Op.getOperand(0);
1965 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
1966 SelectionDAG &DAG) const {
1967 SDValue Chain = Op.getOperand(0);
1968 SDValue Trmp = Op.getOperand(1); // trampoline
1969 SDValue FPtr = Op.getOperand(2); // nested function
1970 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1973 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1974 bool isPPC64 = (PtrVT == MVT::i64);
1976 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
1979 TargetLowering::ArgListTy Args;
1980 TargetLowering::ArgListEntry Entry;
1982 Entry.Ty = IntPtrTy;
1983 Entry.Node = Trmp; Args.push_back(Entry);
1985 // TrampSize == (isPPC64 ? 48 : 40);
1986 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1987 isPPC64 ? MVT::i64 : MVT::i32);
1988 Args.push_back(Entry);
1990 Entry.Node = FPtr; Args.push_back(Entry);
1991 Entry.Node = Nest; Args.push_back(Entry);
1993 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1994 TargetLowering::CallLoweringInfo CLI(DAG);
1995 CLI.setDebugLoc(dl).setChain(Chain)
1996 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
1997 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1998 std::move(Args), 0);
2000 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2001 return CallResult.second;
2004 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
2005 const PPCSubtarget &Subtarget) const {
2006 MachineFunction &MF = DAG.getMachineFunction();
2007 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2011 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
2012 // vastart just stores the address of the VarArgsFrameIndex slot into the
2013 // memory location argument.
2014 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2015 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2016 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2017 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2018 MachinePointerInfo(SV),
2022 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
2023 // We suppose the given va_list is already allocated.
2026 // char gpr; /* index into the array of 8 GPRs
2027 // * stored in the register save area
2028 // * gpr=0 corresponds to r3,
2029 // * gpr=1 to r4, etc.
2031 // char fpr; /* index into the array of 8 FPRs
2032 // * stored in the register save area
2033 // * fpr=0 corresponds to f1,
2034 // * fpr=1 to f2, etc.
2036 // char *overflow_arg_area;
2037 // /* location on stack that holds
2038 // * the next overflow argument
2040 // char *reg_save_area;
2041 // /* where r3:r10 and f1:f8 (if saved)
2047 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
2048 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
2051 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2053 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
2055 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2058 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2059 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
2061 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2062 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
2064 uint64_t FPROffset = 1;
2065 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
2067 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2069 // Store first byte : number of int regs
2070 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
2072 MachinePointerInfo(SV),
2073 MVT::i8, false, false, 0);
2074 uint64_t nextOffset = FPROffset;
2075 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2078 // Store second byte : number of float regs
2079 SDValue secondStore =
2080 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2081 MachinePointerInfo(SV, nextOffset), MVT::i8,
2083 nextOffset += StackOffset;
2084 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2086 // Store second word : arguments given on stack
2087 SDValue thirdStore =
2088 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2089 MachinePointerInfo(SV, nextOffset),
2091 nextOffset += FrameOffset;
2092 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2094 // Store third word : arguments given in registers
2095 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2096 MachinePointerInfo(SV, nextOffset),
2101 #include "PPCGenCallingConv.inc"
2103 // Function whose sole purpose is to kill compiler warnings
2104 // stemming from unused functions included from PPCGenCallingConv.inc.
2105 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2106 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2109 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2110 CCValAssign::LocInfo &LocInfo,
2111 ISD::ArgFlagsTy &ArgFlags,
2116 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2118 CCValAssign::LocInfo &LocInfo,
2119 ISD::ArgFlagsTy &ArgFlags,
2121 static const MCPhysReg ArgRegs[] = {
2122 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2123 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2125 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2127 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2129 // Skip one register if the first unallocated register has an even register
2130 // number and there are still argument registers available which have not been
2131 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2132 // need to skip a register if RegNum is odd.
2133 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2134 State.AllocateReg(ArgRegs[RegNum]);
2137 // Always return false here, as this function only makes sure that the first
2138 // unallocated register has an odd register number and does not actually
2139 // allocate a register for the current argument.
2143 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2145 CCValAssign::LocInfo &LocInfo,
2146 ISD::ArgFlagsTy &ArgFlags,
2148 static const MCPhysReg ArgRegs[] = {
2149 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2153 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2155 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2157 // If there is only one Floating-point register left we need to put both f64
2158 // values of a split ppc_fp128 value on the stack.
2159 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2160 State.AllocateReg(ArgRegs[RegNum]);
2163 // Always return false here, as this function only makes sure that the two f64
2164 // values a ppc_fp128 value is split into are both passed in registers or both
2165 // passed on the stack and does not actually allocate a register for the
2166 // current argument.
2170 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
2172 static const MCPhysReg *GetFPR() {
2173 static const MCPhysReg FPR[] = {
2174 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2175 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
2181 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2183 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2184 unsigned PtrByteSize) {
2185 unsigned ArgSize = ArgVT.getStoreSize();
2186 if (Flags.isByVal())
2187 ArgSize = Flags.getByValSize();
2189 // Round up to multiples of the pointer size, except for array members,
2190 // which are always packed.
2191 if (!Flags.isInConsecutiveRegs())
2192 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2197 /// CalculateStackSlotAlignment - Calculates the alignment of this argument
2199 static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
2200 ISD::ArgFlagsTy Flags,
2201 unsigned PtrByteSize) {
2202 unsigned Align = PtrByteSize;
2204 // Altivec parameters are padded to a 16 byte boundary.
2205 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2206 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2207 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2210 // ByVal parameters are aligned as requested.
2211 if (Flags.isByVal()) {
2212 unsigned BVAlign = Flags.getByValAlign();
2213 if (BVAlign > PtrByteSize) {
2214 if (BVAlign % PtrByteSize != 0)
2216 "ByVal alignment is not a multiple of the pointer size");
2222 // Array members are always packed to their original alignment.
2223 if (Flags.isInConsecutiveRegs()) {
2224 // If the array member was split into multiple registers, the first
2225 // needs to be aligned to the size of the full type. (Except for
2226 // ppcf128, which is only aligned as its f64 components.)
2227 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
2228 Align = OrigVT.getStoreSize();
2230 Align = ArgVT.getStoreSize();
2236 /// CalculateStackSlotUsed - Return whether this argument will use its
2237 /// stack slot (instead of being passed in registers). ArgOffset,
2238 /// AvailableFPRs, and AvailableVRs must hold the current argument
2239 /// position, and will be updated to account for this argument.
2240 static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT,
2241 ISD::ArgFlagsTy Flags,
2242 unsigned PtrByteSize,
2243 unsigned LinkageSize,
2244 unsigned ParamAreaSize,
2245 unsigned &ArgOffset,
2246 unsigned &AvailableFPRs,
2247 unsigned &AvailableVRs) {
2248 bool UseMemory = false;
2250 // Respect alignment of argument on the stack.
2252 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
2253 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2254 // If there's no space left in the argument save area, we must
2255 // use memory (this check also catches zero-sized arguments).
2256 if (ArgOffset >= LinkageSize + ParamAreaSize)
2259 // Allocate argument on the stack.
2260 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2261 if (Flags.isInConsecutiveRegsLast())
2262 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2263 // If we overran the argument save area, we must use memory
2264 // (this check catches arguments passed partially in memory)
2265 if (ArgOffset > LinkageSize + ParamAreaSize)
2268 // However, if the argument is actually passed in an FPR or a VR,
2269 // we don't use memory after all.
2270 if (!Flags.isByVal()) {
2271 if (ArgVT == MVT::f32 || ArgVT == MVT::f64)
2272 if (AvailableFPRs > 0) {
2276 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2277 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2278 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2279 if (AvailableVRs > 0) {
2288 /// EnsureStackAlignment - Round stack frame size up from NumBytes to
2289 /// ensure minimum alignment required for target.
2290 static unsigned EnsureStackAlignment(const TargetMachine &Target,
2291 unsigned NumBytes) {
2292 unsigned TargetAlign = Target.getFrameLowering()->getStackAlignment();
2293 unsigned AlignMask = TargetAlign - 1;
2294 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2299 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
2300 CallingConv::ID CallConv, bool isVarArg,
2301 const SmallVectorImpl<ISD::InputArg>
2303 SDLoc dl, SelectionDAG &DAG,
2304 SmallVectorImpl<SDValue> &InVals)
2306 if (Subtarget.isSVR4ABI()) {
2307 if (Subtarget.isPPC64())
2308 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2311 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2314 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2320 PPCTargetLowering::LowerFormalArguments_32SVR4(
2322 CallingConv::ID CallConv, bool isVarArg,
2323 const SmallVectorImpl<ISD::InputArg>
2325 SDLoc dl, SelectionDAG &DAG,
2326 SmallVectorImpl<SDValue> &InVals) const {
2328 // 32-bit SVR4 ABI Stack Frame Layout:
2329 // +-----------------------------------+
2330 // +--> | Back chain |
2331 // | +-----------------------------------+
2332 // | | Floating-point register save area |
2333 // | +-----------------------------------+
2334 // | | General register save area |
2335 // | +-----------------------------------+
2336 // | | CR save word |
2337 // | +-----------------------------------+
2338 // | | VRSAVE save word |
2339 // | +-----------------------------------+
2340 // | | Alignment padding |
2341 // | +-----------------------------------+
2342 // | | Vector register save area |
2343 // | +-----------------------------------+
2344 // | | Local variable space |
2345 // | +-----------------------------------+
2346 // | | Parameter list area |
2347 // | +-----------------------------------+
2348 // | | LR save word |
2349 // | +-----------------------------------+
2350 // SP--> +--- | Back chain |
2351 // +-----------------------------------+
2354 // System V Application Binary Interface PowerPC Processor Supplement
2355 // AltiVec Technology Programming Interface Manual
2357 MachineFunction &MF = DAG.getMachineFunction();
2358 MachineFrameInfo *MFI = MF.getFrameInfo();
2359 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2361 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2362 // Potential tail calls could cause overwriting of argument stack slots.
2363 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2364 (CallConv == CallingConv::Fast));
2365 unsigned PtrByteSize = 4;
2367 // Assign locations to all of the incoming arguments.
2368 SmallVector<CCValAssign, 16> ArgLocs;
2369 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2370 getTargetMachine(), ArgLocs, *DAG.getContext());
2372 // Reserve space for the linkage area on the stack.
2373 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(false, false, false);
2374 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
2376 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2378 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2379 CCValAssign &VA = ArgLocs[i];
2381 // Arguments stored in registers.
2382 if (VA.isRegLoc()) {
2383 const TargetRegisterClass *RC;
2384 EVT ValVT = VA.getValVT();
2386 switch (ValVT.getSimpleVT().SimpleTy) {
2388 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2391 RC = &PPC::GPRCRegClass;
2394 RC = &PPC::F4RCRegClass;
2397 if (Subtarget.hasVSX())
2398 RC = &PPC::VSFRCRegClass;
2400 RC = &PPC::F8RCRegClass;
2406 RC = &PPC::VRRCRegClass;
2410 RC = &PPC::VSHRCRegClass;
2414 // Transform the arguments stored in physical registers into virtual ones.
2415 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2416 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2417 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2419 if (ValVT == MVT::i1)
2420 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2422 InVals.push_back(ArgValue);
2424 // Argument stored in memory.
2425 assert(VA.isMemLoc());
2427 unsigned ArgSize = VA.getLocVT().getStoreSize();
2428 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2431 // Create load nodes to retrieve arguments from the stack.
2432 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2433 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2434 MachinePointerInfo(),
2435 false, false, false, 0));
2439 // Assign locations to all of the incoming aggregate by value arguments.
2440 // Aggregates passed by value are stored in the local variable space of the
2441 // caller's stack frame, right above the parameter list area.
2442 SmallVector<CCValAssign, 16> ByValArgLocs;
2443 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2444 getTargetMachine(), ByValArgLocs, *DAG.getContext());
2446 // Reserve stack space for the allocations in CCInfo.
2447 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2449 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2451 // Area that is at least reserved in the caller of this function.
2452 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2453 MinReservedArea = std::max(MinReservedArea, LinkageSize);
2455 // Set the size that is at least reserved in caller of this function. Tail
2456 // call optimized function's reserved stack space needs to be aligned so that
2457 // taking the difference between two stack areas will result in an aligned
2459 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2460 FuncInfo->setMinReservedArea(MinReservedArea);
2462 SmallVector<SDValue, 8> MemOps;
2464 // If the function takes variable number of arguments, make a frame index for
2465 // the start of the first vararg value... for expansion of llvm.va_start.
2467 static const MCPhysReg GPArgRegs[] = {
2468 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2469 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2471 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2473 static const MCPhysReg FPArgRegs[] = {
2474 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2477 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2479 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2481 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2484 // Make room for NumGPArgRegs and NumFPArgRegs.
2485 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2486 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
2488 FuncInfo->setVarArgsStackOffset(
2489 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2490 CCInfo.getNextStackOffset(), true));
2492 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2493 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2495 // The fixed integer arguments of a variadic function are stored to the
2496 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2497 // the result of va_next.
2498 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2499 // Get an existing live-in vreg, or add a new one.
2500 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2502 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2504 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2505 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2506 MachinePointerInfo(), false, false, 0);
2507 MemOps.push_back(Store);
2508 // Increment the address by four for the next argument to store
2509 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2510 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2513 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2515 // The double arguments are stored to the VarArgsFrameIndex
2517 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2518 // Get an existing live-in vreg, or add a new one.
2519 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2521 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2523 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2524 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2525 MachinePointerInfo(), false, false, 0);
2526 MemOps.push_back(Store);
2527 // Increment the address by eight for the next argument to store
2528 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
2530 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2534 if (!MemOps.empty())
2535 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2540 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2541 // value to MVT::i64 and then truncate to the correct register size.
2543 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2544 SelectionDAG &DAG, SDValue ArgVal,
2547 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2548 DAG.getValueType(ObjectVT));
2549 else if (Flags.isZExt())
2550 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2551 DAG.getValueType(ObjectVT));
2553 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
2557 PPCTargetLowering::LowerFormalArguments_64SVR4(
2559 CallingConv::ID CallConv, bool isVarArg,
2560 const SmallVectorImpl<ISD::InputArg>
2562 SDLoc dl, SelectionDAG &DAG,
2563 SmallVectorImpl<SDValue> &InVals) const {
2564 // TODO: add description of PPC stack frame format, or at least some docs.
2566 bool isELFv2ABI = Subtarget.isELFv2ABI();
2567 bool isLittleEndian = Subtarget.isLittleEndian();
2568 MachineFunction &MF = DAG.getMachineFunction();
2569 MachineFrameInfo *MFI = MF.getFrameInfo();
2570 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2572 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2573 // Potential tail calls could cause overwriting of argument stack slots.
2574 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2575 (CallConv == CallingConv::Fast));
2576 unsigned PtrByteSize = 8;
2578 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
2581 static const MCPhysReg GPR[] = {
2582 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2583 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2586 static const MCPhysReg *FPR = GetFPR();
2588 static const MCPhysReg VR[] = {
2589 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2590 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2592 static const MCPhysReg VSRH[] = {
2593 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
2594 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
2597 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2598 const unsigned Num_FPR_Regs = 13;
2599 const unsigned Num_VR_Regs = array_lengthof(VR);
2601 // Do a first pass over the arguments to determine whether the ABI
2602 // guarantees that our caller has allocated the parameter save area
2603 // on its stack frame. In the ELFv1 ABI, this is always the case;
2604 // in the ELFv2 ABI, it is true if this is a vararg function or if
2605 // any parameter is located in a stack slot.
2607 bool HasParameterArea = !isELFv2ABI || isVarArg;
2608 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
2609 unsigned NumBytes = LinkageSize;
2610 unsigned AvailableFPRs = Num_FPR_Regs;
2611 unsigned AvailableVRs = Num_VR_Regs;
2612 for (unsigned i = 0, e = Ins.size(); i != e; ++i)
2613 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
2614 PtrByteSize, LinkageSize, ParamAreaSize,
2615 NumBytes, AvailableFPRs, AvailableVRs))
2616 HasParameterArea = true;
2618 // Add DAG nodes to load the arguments or copy them out of registers. On
2619 // entry to a function on PPC, the arguments start after the linkage area,
2620 // although the first ones are often in registers.
2622 unsigned ArgOffset = LinkageSize;
2623 unsigned GPR_idx, FPR_idx = 0, VR_idx = 0;
2624 SmallVector<SDValue, 8> MemOps;
2625 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2626 unsigned CurArgIdx = 0;
2627 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2629 bool needsLoad = false;
2630 EVT ObjectVT = Ins[ArgNo].VT;
2631 EVT OrigVT = Ins[ArgNo].ArgVT;
2632 unsigned ObjSize = ObjectVT.getStoreSize();
2633 unsigned ArgSize = ObjSize;
2634 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2635 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2636 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2638 /* Respect alignment of argument on the stack. */
2640 CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
2641 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2642 unsigned CurArgOffset = ArgOffset;
2644 /* Compute GPR index associated with argument offset. */
2645 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2646 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
2648 // FIXME the codegen can be much improved in some cases.
2649 // We do not have to keep everything in memory.
2650 if (Flags.isByVal()) {
2651 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2652 ObjSize = Flags.getByValSize();
2653 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2654 // Empty aggregate parameters do not take up registers. Examples:
2658 // etc. However, we have to provide a place-holder in InVals, so
2659 // pretend we have an 8-byte item at the current address for that
2662 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2663 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2664 InVals.push_back(FIN);
2668 // Create a stack object covering all stack doublewords occupied
2669 // by the argument. If the argument is (fully or partially) on
2670 // the stack, or if the argument is fully in registers but the
2671 // caller has allocated the parameter save anyway, we can refer
2672 // directly to the caller's stack frame. Otherwise, create a
2673 // local copy in our own frame.
2675 if (HasParameterArea ||
2676 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
2677 FI = MFI->CreateFixedObject(ArgSize, ArgOffset, true);
2679 FI = MFI->CreateStackObject(ArgSize, Align, false);
2680 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2682 // Handle aggregates smaller than 8 bytes.
2683 if (ObjSize < PtrByteSize) {
2684 // The value of the object is its address, which differs from the
2685 // address of the enclosing doubleword on big-endian systems.
2687 if (!isLittleEndian) {
2688 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, PtrVT);
2689 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
2691 InVals.push_back(Arg);
2693 if (GPR_idx != Num_GPR_Regs) {
2694 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2695 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2698 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2699 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2700 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2701 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
2702 MachinePointerInfo(FuncArg),
2703 ObjType, false, false, 0);
2705 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2706 // store the whole register as-is to the parameter save area
2708 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2709 MachinePointerInfo(FuncArg),
2713 MemOps.push_back(Store);
2715 // Whether we copied from a register or not, advance the offset
2716 // into the parameter save area by a full doubleword.
2717 ArgOffset += PtrByteSize;
2721 // The value of the object is its address, which is the address of
2722 // its first stack doubleword.
2723 InVals.push_back(FIN);
2725 // Store whatever pieces of the object are in registers to memory.
2726 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2727 if (GPR_idx == Num_GPR_Regs)
2730 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2731 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2734 SDValue Off = DAG.getConstant(j, PtrVT);
2735 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
2737 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
2738 MachinePointerInfo(FuncArg, j),
2740 MemOps.push_back(Store);
2743 ArgOffset += ArgSize;
2747 switch (ObjectVT.getSimpleVT().SimpleTy) {
2748 default: llvm_unreachable("Unhandled argument type!");
2752 // These can be scalar arguments or elements of an integer array type
2753 // passed directly. Clang may use those instead of "byval" aggregate
2754 // types to avoid forcing arguments to memory unnecessarily.
2755 if (GPR_idx != Num_GPR_Regs) {
2756 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2757 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2759 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
2760 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2761 // value to MVT::i64 and then truncate to the correct register size.
2762 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2765 ArgSize = PtrByteSize;
2772 // These can be scalar arguments or elements of a float array type
2773 // passed directly. The latter are used to implement ELFv2 homogenous
2774 // float aggregates.
2775 if (FPR_idx != Num_FPR_Regs) {
2778 if (ObjectVT == MVT::f32)
2779 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2781 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX() ?
2782 &PPC::VSFRCRegClass :
2783 &PPC::F8RCRegClass);
2785 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2787 } else if (GPR_idx != Num_GPR_Regs) {
2788 // This can only ever happen in the presence of f32 array types,
2789 // since otherwise we never run out of FPRs before running out
2791 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2792 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2794 if (ObjectVT == MVT::f32) {
2795 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
2796 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
2797 DAG.getConstant(32, MVT::i32));
2798 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2801 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
2806 // When passing an array of floats, the array occupies consecutive
2807 // space in the argument area; only round up to the next doubleword
2808 // at the end of the array. Otherwise, each float takes 8 bytes.
2809 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
2810 ArgOffset += ArgSize;
2811 if (Flags.isInConsecutiveRegsLast())
2812 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2820 // These can be scalar arguments or elements of a vector array type
2821 // passed directly. The latter are used to implement ELFv2 homogenous
2822 // vector aggregates.
2823 if (VR_idx != Num_VR_Regs) {
2824 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
2825 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
2826 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2827 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2836 // We need to load the argument to a virtual register if we determined
2837 // above that we ran out of physical registers of the appropriate type.
2839 if (ObjSize < ArgSize && !isLittleEndian)
2840 CurArgOffset += ArgSize - ObjSize;
2841 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
2842 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2843 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2844 false, false, false, 0);
2847 InVals.push_back(ArgVal);
2850 // Area that is at least reserved in the caller of this function.
2851 unsigned MinReservedArea;
2852 if (HasParameterArea)
2853 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
2855 MinReservedArea = LinkageSize;
2857 // Set the size that is at least reserved in caller of this function. Tail
2858 // call optimized functions' reserved stack space needs to be aligned so that
2859 // taking the difference between two stack areas will result in an aligned
2861 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2862 FuncInfo->setMinReservedArea(MinReservedArea);
2864 // If the function takes variable number of arguments, make a frame index for
2865 // the start of the first vararg value... for expansion of llvm.va_start.
2867 int Depth = ArgOffset;
2869 FuncInfo->setVarArgsFrameIndex(
2870 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2871 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2873 // If this function is vararg, store any remaining integer argument regs
2874 // to their spots on the stack so that they may be loaded by deferencing the
2875 // result of va_next.
2876 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2877 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
2878 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2879 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2880 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2881 MachinePointerInfo(), false, false, 0);
2882 MemOps.push_back(Store);
2883 // Increment the address by four for the next argument to store
2884 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2885 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2889 if (!MemOps.empty())
2890 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2896 PPCTargetLowering::LowerFormalArguments_Darwin(
2898 CallingConv::ID CallConv, bool isVarArg,
2899 const SmallVectorImpl<ISD::InputArg>
2901 SDLoc dl, SelectionDAG &DAG,
2902 SmallVectorImpl<SDValue> &InVals) const {
2903 // TODO: add description of PPC stack frame format, or at least some docs.
2905 MachineFunction &MF = DAG.getMachineFunction();
2906 MachineFrameInfo *MFI = MF.getFrameInfo();
2907 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2909 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2910 bool isPPC64 = PtrVT == MVT::i64;
2911 // Potential tail calls could cause overwriting of argument stack slots.
2912 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2913 (CallConv == CallingConv::Fast));
2914 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2916 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true,
2918 unsigned ArgOffset = LinkageSize;
2919 // Area that is at least reserved in caller of this function.
2920 unsigned MinReservedArea = ArgOffset;
2922 static const MCPhysReg GPR_32[] = { // 32-bit registers.
2923 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2924 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2926 static const MCPhysReg GPR_64[] = { // 64-bit registers.
2927 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2928 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2931 static const MCPhysReg *FPR = GetFPR();
2933 static const MCPhysReg VR[] = {
2934 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2935 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2938 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2939 const unsigned Num_FPR_Regs = 13;
2940 const unsigned Num_VR_Regs = array_lengthof( VR);
2942 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2944 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
2946 // In 32-bit non-varargs functions, the stack space for vectors is after the
2947 // stack space for non-vectors. We do not use this space unless we have
2948 // too many vectors to fit in registers, something that only occurs in
2949 // constructed examples:), but we have to walk the arglist to figure
2950 // that out...for the pathological case, compute VecArgOffset as the
2951 // start of the vector parameter area. Computing VecArgOffset is the
2952 // entire point of the following loop.
2953 unsigned VecArgOffset = ArgOffset;
2954 if (!isVarArg && !isPPC64) {
2955 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
2957 EVT ObjectVT = Ins[ArgNo].VT;
2958 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2960 if (Flags.isByVal()) {
2961 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
2962 unsigned ObjSize = Flags.getByValSize();
2964 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2965 VecArgOffset += ArgSize;
2969 switch(ObjectVT.getSimpleVT().SimpleTy) {
2970 default: llvm_unreachable("Unhandled argument type!");
2976 case MVT::i64: // PPC64
2978 // FIXME: We are guaranteed to be !isPPC64 at this point.
2979 // Does MVT::i64 apply?
2986 // Nothing to do, we're only looking at Nonvector args here.
2991 // We've found where the vector parameter area in memory is. Skip the
2992 // first 12 parameters; these don't use that memory.
2993 VecArgOffset = ((VecArgOffset+15)/16)*16;
2994 VecArgOffset += 12*16;
2996 // Add DAG nodes to load the arguments or copy them out of registers. On
2997 // entry to a function on PPC, the arguments start after the linkage area,
2998 // although the first ones are often in registers.
3000 SmallVector<SDValue, 8> MemOps;
3001 unsigned nAltivecParamsAtEnd = 0;
3002 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3003 unsigned CurArgIdx = 0;
3004 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3006 bool needsLoad = false;
3007 EVT ObjectVT = Ins[ArgNo].VT;
3008 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
3009 unsigned ArgSize = ObjSize;
3010 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3011 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
3012 CurArgIdx = Ins[ArgNo].OrigArgIndex;
3014 unsigned CurArgOffset = ArgOffset;
3016 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
3017 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
3018 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
3019 if (isVarArg || isPPC64) {
3020 MinReservedArea = ((MinReservedArea+15)/16)*16;
3021 MinReservedArea += CalculateStackSlotSize(ObjectVT,
3024 } else nAltivecParamsAtEnd++;
3026 // Calculate min reserved area.
3027 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
3031 // FIXME the codegen can be much improved in some cases.
3032 // We do not have to keep everything in memory.
3033 if (Flags.isByVal()) {
3034 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3035 ObjSize = Flags.getByValSize();
3036 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3037 // Objects of size 1 and 2 are right justified, everything else is
3038 // left justified. This means the memory address is adjusted forwards.
3039 if (ObjSize==1 || ObjSize==2) {
3040 CurArgOffset = CurArgOffset + (4 - ObjSize);
3042 // The value of the object is its address.
3043 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
3044 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3045 InVals.push_back(FIN);
3046 if (ObjSize==1 || ObjSize==2) {
3047 if (GPR_idx != Num_GPR_Regs) {
3050 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3052 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3053 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3054 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
3055 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
3056 MachinePointerInfo(FuncArg),
3057 ObjType, false, false, 0);
3058 MemOps.push_back(Store);
3062 ArgOffset += PtrByteSize;
3066 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3067 // Store whatever pieces of the object are in registers
3068 // to memory. ArgOffset will be the address of the beginning
3070 if (GPR_idx != Num_GPR_Regs) {
3073 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3075 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3076 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3077 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3078 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3079 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3080 MachinePointerInfo(FuncArg, j),
3082 MemOps.push_back(Store);
3084 ArgOffset += PtrByteSize;
3086 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
3093 switch (ObjectVT.getSimpleVT().SimpleTy) {
3094 default: llvm_unreachable("Unhandled argument type!");
3098 if (GPR_idx != Num_GPR_Regs) {
3099 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3100 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3102 if (ObjectVT == MVT::i1)
3103 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
3108 ArgSize = PtrByteSize;
3110 // All int arguments reserve stack space in the Darwin ABI.
3111 ArgOffset += PtrByteSize;
3115 case MVT::i64: // PPC64
3116 if (GPR_idx != Num_GPR_Regs) {
3117 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3118 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3120 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3121 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3122 // value to MVT::i64 and then truncate to the correct register size.
3123 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3128 ArgSize = PtrByteSize;
3130 // All int arguments reserve stack space in the Darwin ABI.
3136 // Every 4 bytes of argument space consumes one of the GPRs available for
3137 // argument passing.
3138 if (GPR_idx != Num_GPR_Regs) {
3140 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
3143 if (FPR_idx != Num_FPR_Regs) {
3146 if (ObjectVT == MVT::f32)
3147 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
3149 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
3151 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3157 // All FP arguments reserve stack space in the Darwin ABI.
3158 ArgOffset += isPPC64 ? 8 : ObjSize;
3164 // Note that vector arguments in registers don't reserve stack space,
3165 // except in varargs functions.
3166 if (VR_idx != Num_VR_Regs) {
3167 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3168 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3170 while ((ArgOffset % 16) != 0) {
3171 ArgOffset += PtrByteSize;
3172 if (GPR_idx != Num_GPR_Regs)
3176 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
3180 if (!isVarArg && !isPPC64) {
3181 // Vectors go after all the nonvectors.
3182 CurArgOffset = VecArgOffset;
3185 // Vectors are aligned.
3186 ArgOffset = ((ArgOffset+15)/16)*16;
3187 CurArgOffset = ArgOffset;
3195 // We need to load the argument to a virtual register if we determined above
3196 // that we ran out of physical registers of the appropriate type.
3198 int FI = MFI->CreateFixedObject(ObjSize,
3199 CurArgOffset + (ArgSize - ObjSize),
3201 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3202 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3203 false, false, false, 0);
3206 InVals.push_back(ArgVal);
3209 // Allow for Altivec parameters at the end, if needed.
3210 if (nAltivecParamsAtEnd) {
3211 MinReservedArea = ((MinReservedArea+15)/16)*16;
3212 MinReservedArea += 16*nAltivecParamsAtEnd;
3215 // Area that is at least reserved in the caller of this function.
3216 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
3218 // Set the size that is at least reserved in caller of this function. Tail
3219 // call optimized functions' reserved stack space needs to be aligned so that
3220 // taking the difference between two stack areas will result in an aligned
3222 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
3223 FuncInfo->setMinReservedArea(MinReservedArea);
3225 // If the function takes variable number of arguments, make a frame index for
3226 // the start of the first vararg value... for expansion of llvm.va_start.
3228 int Depth = ArgOffset;
3230 FuncInfo->setVarArgsFrameIndex(
3231 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3233 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3235 // If this function is vararg, store any remaining integer argument regs
3236 // to their spots on the stack so that they may be loaded by deferencing the
3237 // result of va_next.
3238 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3242 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3244 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3246 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3247 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3248 MachinePointerInfo(), false, false, 0);
3249 MemOps.push_back(Store);
3250 // Increment the address by four for the next argument to store
3251 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
3252 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3256 if (!MemOps.empty())
3257 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3262 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3263 /// adjusted to accommodate the arguments for the tailcall.
3264 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3265 unsigned ParamSize) {
3267 if (!isTailCall) return 0;
3269 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3270 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3271 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3272 // Remember only if the new adjustement is bigger.
3273 if (SPDiff < FI->getTailCallSPDelta())
3274 FI->setTailCallSPDelta(SPDiff);
3279 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3280 /// for tail call optimization. Targets which want to do tail call
3281 /// optimization should implement this function.
3283 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3284 CallingConv::ID CalleeCC,
3286 const SmallVectorImpl<ISD::InputArg> &Ins,
3287 SelectionDAG& DAG) const {
3288 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3291 // Variable argument functions are not supported.
3295 MachineFunction &MF = DAG.getMachineFunction();
3296 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3297 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3298 // Functions containing by val parameters are not supported.
3299 for (unsigned i = 0; i != Ins.size(); i++) {
3300 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3301 if (Flags.isByVal()) return false;
3304 // Non-PIC/GOT tail calls are supported.
3305 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3308 // At the moment we can only do local tail calls (in same module, hidden
3309 // or protected) if we are generating PIC.
3310 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3311 return G->getGlobal()->hasHiddenVisibility()
3312 || G->getGlobal()->hasProtectedVisibility();
3318 /// isCallCompatibleAddress - Return the immediate to use if the specified
3319 /// 32-bit value is representable in the immediate field of a BxA instruction.
3320 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3321 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3322 if (!C) return nullptr;
3324 int Addr = C->getZExtValue();
3325 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3326 SignExtend32<26>(Addr) != Addr)
3327 return nullptr; // Top 6 bits have to be sext of immediate.
3329 return DAG.getConstant((int)C->getZExtValue() >> 2,
3330 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
3335 struct TailCallArgumentInfo {
3340 TailCallArgumentInfo() : FrameIdx(0) {}
3345 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3347 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3349 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3350 SmallVectorImpl<SDValue> &MemOpChains,
3352 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3353 SDValue Arg = TailCallArgs[i].Arg;
3354 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3355 int FI = TailCallArgs[i].FrameIdx;
3356 // Store relative to framepointer.
3357 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
3358 MachinePointerInfo::getFixedStack(FI),
3363 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3364 /// the appropriate stack slot for the tail call optimized function call.
3365 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3366 MachineFunction &MF,
3375 // Calculate the new stack slot for the return address.
3376 int SlotSize = isPPC64 ? 8 : 4;
3377 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
3379 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3380 NewRetAddrLoc, true);
3381 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3382 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3383 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3384 MachinePointerInfo::getFixedStack(NewRetAddr),
3387 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3388 // slot as the FP is never overwritten.
3391 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
3392 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3394 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3395 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3396 MachinePointerInfo::getFixedStack(NewFPIdx),
3403 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3404 /// the position of the argument.
3406 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3407 SDValue Arg, int SPDiff, unsigned ArgOffset,
3408 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3409 int Offset = ArgOffset + SPDiff;
3410 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3411 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3412 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3413 SDValue FIN = DAG.getFrameIndex(FI, VT);
3414 TailCallArgumentInfo Info;
3416 Info.FrameIdxOp = FIN;
3418 TailCallArguments.push_back(Info);
3421 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3422 /// stack slot. Returns the chain as result and the loaded frame pointers in
3423 /// LROpOut/FPOpout. Used when tail calling.
3424 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3432 // Load the LR and FP stack slot for later adjusting.
3433 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
3434 LROpOut = getReturnAddrFrameIndex(DAG);
3435 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3436 false, false, false, 0);
3437 Chain = SDValue(LROpOut.getNode(), 1);
3439 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3440 // slot as the FP is never overwritten.
3442 FPOpOut = getFramePointerFrameIndex(DAG);
3443 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3444 false, false, false, 0);
3445 Chain = SDValue(FPOpOut.getNode(), 1);
3451 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3452 /// by "Src" to address "Dst" of size "Size". Alignment information is
3453 /// specified by the specific parameter attribute. The copy will be passed as
3454 /// a byval function parameter.
3455 /// Sometimes what we are copying is the end of a larger object, the part that
3456 /// does not fit in registers.
3458 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3459 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3461 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3462 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3463 false, false, MachinePointerInfo(),
3464 MachinePointerInfo());
3467 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3470 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3471 SDValue Arg, SDValue PtrOff, int SPDiff,
3472 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3473 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
3474 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
3476 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3481 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3483 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3484 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3485 DAG.getConstant(ArgOffset, PtrVT));
3487 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3488 MachinePointerInfo(), false, false, 0));
3489 // Calculate and remember argument location.
3490 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3495 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3496 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3497 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3498 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
3499 MachineFunction &MF = DAG.getMachineFunction();
3501 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3502 // might overwrite each other in case of tail call optimization.
3503 SmallVector<SDValue, 8> MemOpChains2;
3504 // Do not flag preceding copytoreg stuff together with the following stuff.
3506 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3508 if (!MemOpChains2.empty())
3509 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3511 // Store the return address to the appropriate stack slot.
3512 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3513 isPPC64, isDarwinABI, dl);
3515 // Emit callseq_end just before tailcall node.
3516 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3517 DAG.getIntPtrConstant(0, true), InFlag, dl);
3518 InFlag = Chain.getValue(1);
3522 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3523 SDValue &Chain, SDLoc dl, int SPDiff, bool isTailCall,
3524 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
3525 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
3526 const PPCSubtarget &Subtarget) {
3528 bool isPPC64 = Subtarget.isPPC64();
3529 bool isSVR4ABI = Subtarget.isSVR4ABI();
3530 bool isELFv2ABI = Subtarget.isELFv2ABI();
3532 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3533 NodeTys.push_back(MVT::Other); // Returns a chain
3534 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3536 unsigned CallOpc = PPCISD::CALL;
3538 bool needIndirectCall = true;
3539 if (!isSVR4ABI || !isPPC64)
3540 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3541 // If this is an absolute destination address, use the munged value.
3542 Callee = SDValue(Dest, 0);
3543 needIndirectCall = false;
3546 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3547 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201
3548 // Use indirect calls for ALL functions calls in JIT mode, since the
3549 // far-call stubs may be outside relocation limits for a BL instruction.
3550 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
3551 unsigned OpFlags = 0;
3552 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3553 (Subtarget.getTargetTriple().isMacOSX() &&
3554 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3555 (G->getGlobal()->isDeclaration() ||
3556 G->getGlobal()->isWeakForLinker())) ||
3557 (Subtarget.isTargetELF() && !isPPC64 &&
3558 !G->getGlobal()->hasLocalLinkage() &&
3559 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3560 // PC-relative references to external symbols should go through $stub,
3561 // unless we're building with the leopard linker or later, which
3562 // automatically synthesizes these stubs.
3563 OpFlags = PPCII::MO_PLT_OR_STUB;
3566 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3567 // every direct call is) turn it into a TargetGlobalAddress /
3568 // TargetExternalSymbol node so that legalize doesn't hack it.
3569 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3570 Callee.getValueType(),
3572 needIndirectCall = false;
3576 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3577 unsigned char OpFlags = 0;
3579 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3580 (Subtarget.getTargetTriple().isMacOSX() &&
3581 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) ||
3582 (Subtarget.isTargetELF() && !isPPC64 &&
3583 DAG.getTarget().getRelocationModel() == Reloc::PIC_) ) {
3584 // PC-relative references to external symbols should go through $stub,
3585 // unless we're building with the leopard linker or later, which
3586 // automatically synthesizes these stubs.
3587 OpFlags = PPCII::MO_PLT_OR_STUB;
3590 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3592 needIndirectCall = false;
3595 if (needIndirectCall) {
3596 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3597 // to do the call, we can't use PPCISD::CALL.
3598 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3600 if (isSVR4ABI && isPPC64 && !isELFv2ABI) {
3601 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3602 // entry point, but to the function descriptor (the function entry point
3603 // address is part of the function descriptor though).
3604 // The function descriptor is a three doubleword structure with the
3605 // following fields: function entry point, TOC base address and
3606 // environment pointer.
3607 // Thus for a call through a function pointer, the following actions need
3609 // 1. Save the TOC of the caller in the TOC save area of its stack
3610 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3611 // 2. Load the address of the function entry point from the function
3613 // 3. Load the TOC of the callee from the function descriptor into r2.
3614 // 4. Load the environment pointer from the function descriptor into
3616 // 5. Branch to the function entry point address.
3617 // 6. On return of the callee, the TOC of the caller needs to be
3618 // restored (this is done in FinishCall()).
3620 // All those operations are flagged together to ensure that no other
3621 // operations can be scheduled in between. E.g. without flagging the
3622 // operations together, a TOC access in the caller could be scheduled
3623 // between the load of the callee TOC and the branch to the callee, which
3624 // results in the TOC access going through the TOC of the callee instead
3625 // of going through the TOC of the caller, which leads to incorrect code.
3627 // Load the address of the function entry point from the function
3629 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3630 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs,
3631 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3632 Chain = LoadFuncPtr.getValue(1);
3633 InFlag = LoadFuncPtr.getValue(2);
3635 // Load environment pointer into r11.
3636 // Offset of the environment pointer within the function descriptor.
3637 SDValue PtrOff = DAG.getIntPtrConstant(16);
3639 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3640 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
3642 Chain = LoadEnvPtr.getValue(1);
3643 InFlag = LoadEnvPtr.getValue(2);
3645 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3647 Chain = EnvVal.getValue(0);
3648 InFlag = EnvVal.getValue(1);
3650 // Load TOC of the callee into r2. We are using a target-specific load
3651 // with r2 hard coded, because the result of a target-independent load
3652 // would never go directly into r2, since r2 is a reserved register (which
3653 // prevents the register allocator from allocating it), resulting in an
3654 // additional register being allocated and an unnecessary move instruction
3656 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3657 SDValue TOCOff = DAG.getIntPtrConstant(8);
3658 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
3659 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
3661 Chain = LoadTOCPtr.getValue(0);
3662 InFlag = LoadTOCPtr.getValue(1);
3664 MTCTROps[0] = Chain;
3665 MTCTROps[1] = LoadFuncPtr;
3666 MTCTROps[2] = InFlag;
3669 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
3670 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3671 InFlag = Chain.getValue(1);
3674 NodeTys.push_back(MVT::Other);
3675 NodeTys.push_back(MVT::Glue);
3676 Ops.push_back(Chain);
3677 CallOpc = PPCISD::BCTRL;
3678 Callee.setNode(nullptr);
3679 // Add use of X11 (holding environment pointer)
3680 if (isSVR4ABI && isPPC64 && !isELFv2ABI)
3681 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3682 // Add CTR register as callee so a bctr can be emitted later.
3684 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3687 // If this is a direct call, pass the chain and the callee.
3688 if (Callee.getNode()) {
3689 Ops.push_back(Chain);
3690 Ops.push_back(Callee);
3692 // If this is a tail call add stack pointer delta.
3694 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3696 // Add argument registers to the end of the list so that they are known live
3698 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3699 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3700 RegsToPass[i].second.getValueType()));
3702 // Direct calls in the ELFv2 ABI need the TOC register live into the call.
3703 if (Callee.getNode() && isELFv2ABI)
3704 Ops.push_back(DAG.getRegister(PPC::X2, PtrVT));
3710 bool isLocalCall(const SDValue &Callee)
3712 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3713 return !G->getGlobal()->isDeclaration() &&
3714 !G->getGlobal()->isWeakForLinker();
3719 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3720 CallingConv::ID CallConv, bool isVarArg,
3721 const SmallVectorImpl<ISD::InputArg> &Ins,
3722 SDLoc dl, SelectionDAG &DAG,
3723 SmallVectorImpl<SDValue> &InVals) const {
3725 SmallVector<CCValAssign, 16> RVLocs;
3726 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3727 getTargetMachine(), RVLocs, *DAG.getContext());
3728 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3730 // Copy all of the result registers out of their specified physreg.
3731 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3732 CCValAssign &VA = RVLocs[i];
3733 assert(VA.isRegLoc() && "Can only return in registers!");
3735 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3736 VA.getLocReg(), VA.getLocVT(), InFlag);
3737 Chain = Val.getValue(1);
3738 InFlag = Val.getValue(2);
3740 switch (VA.getLocInfo()) {
3741 default: llvm_unreachable("Unknown loc info!");
3742 case CCValAssign::Full: break;
3743 case CCValAssign::AExt:
3744 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3746 case CCValAssign::ZExt:
3747 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3748 DAG.getValueType(VA.getValVT()));
3749 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3751 case CCValAssign::SExt:
3752 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3753 DAG.getValueType(VA.getValVT()));
3754 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3758 InVals.push_back(Val);
3765 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
3766 bool isTailCall, bool isVarArg,
3768 SmallVector<std::pair<unsigned, SDValue>, 8>
3770 SDValue InFlag, SDValue Chain,
3772 int SPDiff, unsigned NumBytes,
3773 const SmallVectorImpl<ISD::InputArg> &Ins,
3774 SmallVectorImpl<SDValue> &InVals) const {
3776 bool isELFv2ABI = Subtarget.isELFv2ABI();
3777 std::vector<EVT> NodeTys;
3778 SmallVector<SDValue, 8> Ops;
3779 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
3780 isTailCall, RegsToPass, Ops, NodeTys,
3783 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3784 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
3785 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3787 // When performing tail call optimization the callee pops its arguments off
3788 // the stack. Account for this here so these bytes can be pushed back on in
3789 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3790 int BytesCalleePops =
3791 (CallConv == CallingConv::Fast &&
3792 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3794 // Add a register mask operand representing the call-preserved registers.
3795 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
3796 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3797 assert(Mask && "Missing call preserved mask for calling convention");
3798 Ops.push_back(DAG.getRegisterMask(Mask));
3800 if (InFlag.getNode())
3801 Ops.push_back(InFlag);
3805 assert(((Callee.getOpcode() == ISD::Register &&
3806 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3807 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3808 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3809 isa<ConstantSDNode>(Callee)) &&
3810 "Expecting an global address, external symbol, absolute value or register");
3812 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
3815 // Add a NOP immediately after the branch instruction when using the 64-bit
3816 // SVR4 ABI. At link time, if caller and callee are in a different module and
3817 // thus have a different TOC, the call will be replaced with a call to a stub
3818 // function which saves the current TOC, loads the TOC of the callee and
3819 // branches to the callee. The NOP will be replaced with a load instruction
3820 // which restores the TOC of the caller from the TOC save slot of the current
3821 // stack frame. If caller and callee belong to the same module (and have the
3822 // same TOC), the NOP will remain unchanged.
3824 bool needsTOCRestore = false;
3825 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64()) {
3826 if (CallOpc == PPCISD::BCTRL) {
3827 // This is a call through a function pointer.
3828 // Restore the caller TOC from the save area into R2.
3829 // See PrepareCall() for more information about calls through function
3830 // pointers in the 64-bit SVR4 ABI.
3831 // We are using a target-specific load with r2 hard coded, because the
3832 // result of a target-independent load would never go directly into r2,
3833 // since r2 is a reserved register (which prevents the register allocator
3834 // from allocating it), resulting in an additional register being
3835 // allocated and an unnecessary move instruction being generated.
3836 needsTOCRestore = true;
3837 } else if ((CallOpc == PPCISD::CALL) &&
3838 (!isLocalCall(Callee) ||
3839 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3840 // Otherwise insert NOP for non-local calls.
3841 CallOpc = PPCISD::CALL_NOP;
3845 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
3846 InFlag = Chain.getValue(1);
3848 if (needsTOCRestore) {
3849 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3850 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3851 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
3852 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset(isELFv2ABI);
3853 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset);
3854 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
3855 Chain = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain, AddTOC, InFlag);
3856 InFlag = Chain.getValue(1);
3859 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3860 DAG.getIntPtrConstant(BytesCalleePops, true),
3863 InFlag = Chain.getValue(1);
3865 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3866 Ins, dl, DAG, InVals);
3870 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3871 SmallVectorImpl<SDValue> &InVals) const {
3872 SelectionDAG &DAG = CLI.DAG;
3874 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3875 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3876 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3877 SDValue Chain = CLI.Chain;
3878 SDValue Callee = CLI.Callee;
3879 bool &isTailCall = CLI.IsTailCall;
3880 CallingConv::ID CallConv = CLI.CallConv;
3881 bool isVarArg = CLI.IsVarArg;
3884 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3887 if (!isTailCall && CLI.CS && CLI.CS->isMustTailCall())
3888 report_fatal_error("failed to perform tail call elimination on a call "
3889 "site marked musttail");
3891 if (Subtarget.isSVR4ABI()) {
3892 if (Subtarget.isPPC64())
3893 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3894 isTailCall, Outs, OutVals, Ins,
3897 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3898 isTailCall, Outs, OutVals, Ins,
3902 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
3903 isTailCall, Outs, OutVals, Ins,
3908 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
3909 CallingConv::ID CallConv, bool isVarArg,
3911 const SmallVectorImpl<ISD::OutputArg> &Outs,
3912 const SmallVectorImpl<SDValue> &OutVals,
3913 const SmallVectorImpl<ISD::InputArg> &Ins,
3914 SDLoc dl, SelectionDAG &DAG,
3915 SmallVectorImpl<SDValue> &InVals) const {
3916 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
3917 // of the 32-bit SVR4 ABI stack frame layout.
3919 assert((CallConv == CallingConv::C ||
3920 CallConv == CallingConv::Fast) && "Unknown calling convention!");
3922 unsigned PtrByteSize = 4;
3924 MachineFunction &MF = DAG.getMachineFunction();
3926 // Mark this function as potentially containing a function that contains a
3927 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3928 // and restoring the callers stack pointer in this functions epilog. This is
3929 // done because by tail calling the called function might overwrite the value
3930 // in this function's (MF) stack pointer stack slot 0(SP).
3931 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3932 CallConv == CallingConv::Fast)
3933 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3935 // Count how many bytes are to be pushed on the stack, including the linkage
3936 // area, parameter list area and the part of the local variable space which
3937 // contains copies of aggregates which are passed by value.
3939 // Assign locations to all of the outgoing arguments.
3940 SmallVector<CCValAssign, 16> ArgLocs;
3941 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3942 getTargetMachine(), ArgLocs, *DAG.getContext());
3944 // Reserve space for the linkage area on the stack.
3945 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false, false),
3949 // Handle fixed and variable vector arguments differently.
3950 // Fixed vector arguments go into registers as long as registers are
3951 // available. Variable vector arguments always go into memory.
3952 unsigned NumArgs = Outs.size();
3954 for (unsigned i = 0; i != NumArgs; ++i) {
3955 MVT ArgVT = Outs[i].VT;
3956 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3959 if (Outs[i].IsFixed) {
3960 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
3963 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
3969 errs() << "Call operand #" << i << " has unhandled type "
3970 << EVT(ArgVT).getEVTString() << "\n";
3972 llvm_unreachable(nullptr);
3976 // All arguments are treated the same.
3977 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
3980 // Assign locations to all of the outgoing aggregate by value arguments.
3981 SmallVector<CCValAssign, 16> ByValArgLocs;
3982 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3983 getTargetMachine(), ByValArgLocs, *DAG.getContext());
3985 // Reserve stack space for the allocations in CCInfo.
3986 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
3988 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
3990 // Size of the linkage area, parameter list area and the part of the local
3991 // space variable where copies of aggregates which are passed by value are
3993 unsigned NumBytes = CCByValInfo.getNextStackOffset();
3995 // Calculate by how many bytes the stack has to be adjusted in case of tail
3996 // call optimization.
3997 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3999 // Adjust the stack pointer for the new arguments...
4000 // These operations are automatically eliminated by the prolog/epilog pass
4001 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4003 SDValue CallSeqStart = Chain;
4005 // Load the return address and frame pointer so it can be moved somewhere else
4008 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
4011 // Set up a copy of the stack pointer for use loading and storing any
4012 // arguments that may not fit in the registers available for argument
4014 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4016 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4017 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4018 SmallVector<SDValue, 8> MemOpChains;
4020 bool seenFloatArg = false;
4021 // Walk the register/memloc assignments, inserting copies/loads.
4022 for (unsigned i = 0, j = 0, e = ArgLocs.size();
4025 CCValAssign &VA = ArgLocs[i];
4026 SDValue Arg = OutVals[i];
4027 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4029 if (Flags.isByVal()) {
4030 // Argument is an aggregate which is passed by value, thus we need to
4031 // create a copy of it in the local variable space of the current stack
4032 // frame (which is the stack frame of the caller) and pass the address of
4033 // this copy to the callee.
4034 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
4035 CCValAssign &ByValVA = ByValArgLocs[j++];
4036 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
4038 // Memory reserved in the local variable space of the callers stack frame.
4039 unsigned LocMemOffset = ByValVA.getLocMemOffset();
4041 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4042 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4044 // Create a copy of the argument in the local area of the current
4046 SDValue MemcpyCall =
4047 CreateCopyOfByValArgument(Arg, PtrOff,
4048 CallSeqStart.getNode()->getOperand(0),
4051 // This must go outside the CALLSEQ_START..END.
4052 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4053 CallSeqStart.getNode()->getOperand(1),
4055 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4056 NewCallSeqStart.getNode());
4057 Chain = CallSeqStart = NewCallSeqStart;
4059 // Pass the address of the aggregate copy on the stack either in a
4060 // physical register or in the parameter list area of the current stack
4061 // frame to the callee.
4065 if (VA.isRegLoc()) {
4066 if (Arg.getValueType() == MVT::i1)
4067 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
4069 seenFloatArg |= VA.getLocVT().isFloatingPoint();
4070 // Put argument in a physical register.
4071 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
4073 // Put argument in the parameter list area of the current stack frame.
4074 assert(VA.isMemLoc());
4075 unsigned LocMemOffset = VA.getLocMemOffset();
4078 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4079 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4081 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4082 MachinePointerInfo(),
4085 // Calculate and remember argument location.
4086 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
4092 if (!MemOpChains.empty())
4093 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4095 // Build a sequence of copy-to-reg nodes chained together with token chain
4096 // and flag operands which copy the outgoing args into the appropriate regs.
4098 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4099 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4100 RegsToPass[i].second, InFlag);
4101 InFlag = Chain.getValue(1);
4104 // Set CR bit 6 to true if this is a vararg call with floating args passed in
4107 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
4108 SDValue Ops[] = { Chain, InFlag };
4110 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
4111 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
4113 InFlag = Chain.getValue(1);
4117 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
4118 false, TailCallArguments);
4120 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4121 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4125 // Copy an argument into memory, being careful to do this outside the
4126 // call sequence for the call to which the argument belongs.
4128 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
4129 SDValue CallSeqStart,
4130 ISD::ArgFlagsTy Flags,
4133 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
4134 CallSeqStart.getNode()->getOperand(0),
4136 // The MEMCPY must go outside the CALLSEQ_START..END.
4137 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4138 CallSeqStart.getNode()->getOperand(1),
4140 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4141 NewCallSeqStart.getNode());
4142 return NewCallSeqStart;
4146 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
4147 CallingConv::ID CallConv, bool isVarArg,
4149 const SmallVectorImpl<ISD::OutputArg> &Outs,
4150 const SmallVectorImpl<SDValue> &OutVals,
4151 const SmallVectorImpl<ISD::InputArg> &Ins,
4152 SDLoc dl, SelectionDAG &DAG,
4153 SmallVectorImpl<SDValue> &InVals) const {
4155 bool isELFv2ABI = Subtarget.isELFv2ABI();
4156 bool isLittleEndian = Subtarget.isLittleEndian();
4157 unsigned NumOps = Outs.size();
4159 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4160 unsigned PtrByteSize = 8;
4162 MachineFunction &MF = DAG.getMachineFunction();
4164 // Mark this function as potentially containing a function that contains a
4165 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4166 // and restoring the callers stack pointer in this functions epilog. This is
4167 // done because by tail calling the called function might overwrite the value
4168 // in this function's (MF) stack pointer stack slot 0(SP).
4169 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4170 CallConv == CallingConv::Fast)
4171 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4173 // Count how many bytes are to be pushed on the stack, including the linkage
4174 // area, and parameter passing area. On ELFv1, the linkage area is 48 bytes
4175 // reserved space for [SP][CR][LR][2 x unused][TOC]; on ELFv2, the linkage
4176 // area is 32 bytes reserved space for [SP][CR][LR][TOC].
4177 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
4179 unsigned NumBytes = LinkageSize;
4181 // Add up all the space actually used.
4182 for (unsigned i = 0; i != NumOps; ++i) {
4183 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4184 EVT ArgVT = Outs[i].VT;
4185 EVT OrigVT = Outs[i].ArgVT;
4187 /* Respect alignment of argument on the stack. */
4189 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4190 NumBytes = ((NumBytes + Align - 1) / Align) * Align;
4192 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4193 if (Flags.isInConsecutiveRegsLast())
4194 NumBytes = ((NumBytes + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4197 unsigned NumBytesActuallyUsed = NumBytes;
4199 // The prolog code of the callee may store up to 8 GPR argument registers to
4200 // the stack, allowing va_start to index over them in memory if its varargs.
4201 // Because we cannot tell if this is needed on the caller side, we have to
4202 // conservatively assume that it is needed. As such, make sure we have at
4203 // least enough stack space for the caller to store the 8 GPRs.
4204 // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
4205 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4207 // Tail call needs the stack to be aligned.
4208 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4209 CallConv == CallingConv::Fast)
4210 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
4212 // Calculate by how many bytes the stack has to be adjusted in case of tail
4213 // call optimization.
4214 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4216 // To protect arguments on the stack from being clobbered in a tail call,
4217 // force all the loads to happen before doing any other lowering.
4219 Chain = DAG.getStackArgumentTokenFactor(Chain);
4221 // Adjust the stack pointer for the new arguments...
4222 // These operations are automatically eliminated by the prolog/epilog pass
4223 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4225 SDValue CallSeqStart = Chain;
4227 // Load the return address and frame pointer so it can be move somewhere else
4230 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4233 // Set up a copy of the stack pointer for use loading and storing any
4234 // arguments that may not fit in the registers available for argument
4236 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4238 // Figure out which arguments are going to go in registers, and which in
4239 // memory. Also, if this is a vararg function, floating point operations
4240 // must be stored to our stack, and loaded into integer regs as well, if
4241 // any integer regs are available for argument passing.
4242 unsigned ArgOffset = LinkageSize;
4243 unsigned GPR_idx, FPR_idx = 0, VR_idx = 0;
4245 static const MCPhysReg GPR[] = {
4246 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4247 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4249 static const MCPhysReg *FPR = GetFPR();
4251 static const MCPhysReg VR[] = {
4252 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4253 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4255 static const MCPhysReg VSRH[] = {
4256 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4257 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4260 const unsigned NumGPRs = array_lengthof(GPR);
4261 const unsigned NumFPRs = 13;
4262 const unsigned NumVRs = array_lengthof(VR);
4264 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4265 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4267 SmallVector<SDValue, 8> MemOpChains;
4268 for (unsigned i = 0; i != NumOps; ++i) {
4269 SDValue Arg = OutVals[i];
4270 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4271 EVT ArgVT = Outs[i].VT;
4272 EVT OrigVT = Outs[i].ArgVT;
4274 /* Respect alignment of argument on the stack. */
4276 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4277 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
4279 /* Compute GPR index associated with argument offset. */
4280 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4281 GPR_idx = std::min(GPR_idx, NumGPRs);
4283 // PtrOff will be used to store the current argument to the stack if a
4284 // register cannot be found for it.
4287 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4289 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4291 // Promote integers to 64-bit values.
4292 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4293 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4294 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4295 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4298 // FIXME memcpy is used way more than necessary. Correctness first.
4299 // Note: "by value" is code for passing a structure by value, not
4301 if (Flags.isByVal()) {
4302 // Note: Size includes alignment padding, so
4303 // struct x { short a; char b; }
4304 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4305 // These are the proper values we need for right-justifying the
4306 // aggregate in a parameter register.
4307 unsigned Size = Flags.getByValSize();
4309 // An empty aggregate parameter takes up no storage and no
4314 // All aggregates smaller than 8 bytes must be passed right-justified.
4315 if (Size==1 || Size==2 || Size==4) {
4316 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4317 if (GPR_idx != NumGPRs) {
4318 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4319 MachinePointerInfo(), VT,
4321 MemOpChains.push_back(Load.getValue(1));
4322 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Load));
4324 ArgOffset += PtrByteSize;
4329 if (GPR_idx == NumGPRs && Size < 8) {
4330 SDValue AddPtr = PtrOff;
4331 if (!isLittleEndian) {
4332 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4333 PtrOff.getValueType());
4334 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4336 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4339 ArgOffset += PtrByteSize;
4342 // Copy entire object into memory. There are cases where gcc-generated
4343 // code assumes it is there, even if it could be put entirely into
4344 // registers. (This is not what the doc says.)
4346 // FIXME: The above statement is likely due to a misunderstanding of the
4347 // documents. All arguments must be copied into the parameter area BY
4348 // THE CALLEE in the event that the callee takes the address of any
4349 // formal argument. That has not yet been implemented. However, it is
4350 // reasonable to use the stack area as a staging area for the register
4353 // Skip this for small aggregates, as we will use the same slot for a
4354 // right-justified copy, below.
4356 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4360 // When a register is available, pass a small aggregate right-justified.
4361 if (Size < 8 && GPR_idx != NumGPRs) {
4362 // The easiest way to get this right-justified in a register
4363 // is to copy the structure into the rightmost portion of a
4364 // local variable slot, then load the whole slot into the
4366 // FIXME: The memcpy seems to produce pretty awful code for
4367 // small aggregates, particularly for packed ones.
4368 // FIXME: It would be preferable to use the slot in the
4369 // parameter save area instead of a new local variable.
4370 SDValue AddPtr = PtrOff;
4371 if (!isLittleEndian) {
4372 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
4373 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4375 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4379 // Load the slot into the register.
4380 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
4381 MachinePointerInfo(),
4382 false, false, false, 0);
4383 MemOpChains.push_back(Load.getValue(1));
4384 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Load));
4386 // Done with this argument.
4387 ArgOffset += PtrByteSize;
4391 // For aggregates larger than PtrByteSize, copy the pieces of the
4392 // object that fit into registers from the parameter save area.
4393 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4394 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4395 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4396 if (GPR_idx != NumGPRs) {
4397 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4398 MachinePointerInfo(),
4399 false, false, false, 0);
4400 MemOpChains.push_back(Load.getValue(1));
4401 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4402 ArgOffset += PtrByteSize;
4404 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4411 switch (Arg.getSimpleValueType().SimpleTy) {
4412 default: llvm_unreachable("Unexpected ValueType for argument!");
4416 // These can be scalar arguments or elements of an integer array type
4417 // passed directly. Clang may use those instead of "byval" aggregate
4418 // types to avoid forcing arguments to memory unnecessarily.
4419 if (GPR_idx != NumGPRs) {
4420 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Arg));
4422 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4423 true, isTailCall, false, MemOpChains,
4424 TailCallArguments, dl);
4426 ArgOffset += PtrByteSize;
4430 // These can be scalar arguments or elements of a float array type
4431 // passed directly. The latter are used to implement ELFv2 homogenous
4432 // float aggregates.
4434 // Named arguments go into FPRs first, and once they overflow, the
4435 // remaining arguments go into GPRs and then the parameter save area.
4436 // Unnamed arguments for vararg functions always go to GPRs and
4437 // then the parameter save area. For now, put all arguments to vararg
4438 // routines always in both locations (FPR *and* GPR or stack slot).
4439 bool NeedGPROrStack = isVarArg || FPR_idx == NumFPRs;
4441 // First load the argument into the next available FPR.
4442 if (FPR_idx != NumFPRs)
4443 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4445 // Next, load the argument into GPR or stack slot if needed.
4446 if (!NeedGPROrStack)
4448 else if (GPR_idx != NumGPRs) {
4449 // In the non-vararg case, this can only ever happen in the
4450 // presence of f32 array types, since otherwise we never run
4451 // out of FPRs before running out of GPRs.
4454 // Double values are always passed in a single GPR.
4455 if (Arg.getValueType() != MVT::f32) {
4456 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
4458 // Non-array float values are extended and passed in a GPR.
4459 } else if (!Flags.isInConsecutiveRegs()) {
4460 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4461 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4463 // If we have an array of floats, we collect every odd element
4464 // together with its predecessor into one GPR.
4465 } else if (ArgOffset % PtrByteSize != 0) {
4467 Lo = DAG.getNode(ISD::BITCAST, dl, MVT::i32, OutVals[i - 1]);
4468 Hi = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4469 if (!isLittleEndian)
4471 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
4473 // The final element, if even, goes into the first half of a GPR.
4474 } else if (Flags.isInConsecutiveRegsLast()) {
4475 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4476 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4477 if (!isLittleEndian)
4478 ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal,
4479 DAG.getConstant(32, MVT::i32));
4481 // Non-final even elements are skipped; they will be handled
4482 // together the with subsequent argument on the next go-around.
4486 if (ArgVal.getNode())
4487 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], ArgVal));
4489 // Single-precision floating-point values are mapped to the
4490 // second (rightmost) word of the stack doubleword.
4491 if (Arg.getValueType() == MVT::f32 &&
4492 !isLittleEndian && !Flags.isInConsecutiveRegs()) {
4493 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4494 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4497 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4498 true, isTailCall, false, MemOpChains,
4499 TailCallArguments, dl);
4501 // When passing an array of floats, the array occupies consecutive
4502 // space in the argument area; only round up to the next doubleword
4503 // at the end of the array. Otherwise, each float takes 8 bytes.
4504 ArgOffset += (Arg.getValueType() == MVT::f32 &&
4505 Flags.isInConsecutiveRegs()) ? 4 : 8;
4506 if (Flags.isInConsecutiveRegsLast())
4507 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4516 // These can be scalar arguments or elements of a vector array type
4517 // passed directly. The latter are used to implement ELFv2 homogenous
4518 // vector aggregates.
4520 // For a varargs call, named arguments go into VRs or on the stack as
4521 // usual; unnamed arguments always go to the stack or the corresponding
4522 // GPRs when within range. For now, we always put the value in both
4523 // locations (or even all three).
4525 // We could elide this store in the case where the object fits
4526 // entirely in R registers. Maybe later.
4527 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4528 MachinePointerInfo(), false, false, 0);
4529 MemOpChains.push_back(Store);
4530 if (VR_idx != NumVRs) {
4531 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4532 MachinePointerInfo(),
4533 false, false, false, 0);
4534 MemOpChains.push_back(Load.getValue(1));
4536 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4537 Arg.getSimpleValueType() == MVT::v2i64) ?
4538 VSRH[VR_idx] : VR[VR_idx];
4541 RegsToPass.push_back(std::make_pair(VReg, Load));
4544 for (unsigned i=0; i<16; i+=PtrByteSize) {
4545 if (GPR_idx == NumGPRs)
4547 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4548 DAG.getConstant(i, PtrVT));
4549 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4550 false, false, false, 0);
4551 MemOpChains.push_back(Load.getValue(1));
4552 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4557 // Non-varargs Altivec params go into VRs or on the stack.
4558 if (VR_idx != NumVRs) {
4559 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4560 Arg.getSimpleValueType() == MVT::v2i64) ?
4561 VSRH[VR_idx] : VR[VR_idx];
4564 RegsToPass.push_back(std::make_pair(VReg, Arg));
4566 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4567 true, isTailCall, true, MemOpChains,
4568 TailCallArguments, dl);
4575 assert(NumBytesActuallyUsed == ArgOffset);
4576 (void)NumBytesActuallyUsed;
4578 if (!MemOpChains.empty())
4579 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4581 // Check if this is an indirect call (MTCTR/BCTRL).
4582 // See PrepareCall() for more information about calls through function
4583 // pointers in the 64-bit SVR4 ABI.
4585 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4586 !dyn_cast<ExternalSymbolSDNode>(Callee)) {
4587 // Load r2 into a virtual register and store it to the TOC save area.
4588 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4589 // TOC save area offset.
4590 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset(isELFv2ABI);
4591 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset);
4592 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4593 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
4595 // In the ELFv2 ABI, R12 must contain the address of an indirect callee.
4596 // This does not mean the MTCTR instruction must use R12; it's easier
4597 // to model this as an extra parameter, so do that.
4599 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
4602 // Build a sequence of copy-to-reg nodes chained together with token chain
4603 // and flag operands which copy the outgoing args into the appropriate regs.
4605 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4606 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4607 RegsToPass[i].second, InFlag);
4608 InFlag = Chain.getValue(1);
4612 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4613 FPOp, true, TailCallArguments);
4615 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4616 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4621 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4622 CallingConv::ID CallConv, bool isVarArg,
4624 const SmallVectorImpl<ISD::OutputArg> &Outs,
4625 const SmallVectorImpl<SDValue> &OutVals,
4626 const SmallVectorImpl<ISD::InputArg> &Ins,
4627 SDLoc dl, SelectionDAG &DAG,
4628 SmallVectorImpl<SDValue> &InVals) const {
4630 unsigned NumOps = Outs.size();
4632 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4633 bool isPPC64 = PtrVT == MVT::i64;
4634 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4636 MachineFunction &MF = DAG.getMachineFunction();
4638 // Mark this function as potentially containing a function that contains a
4639 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4640 // and restoring the callers stack pointer in this functions epilog. This is
4641 // done because by tail calling the called function might overwrite the value
4642 // in this function's (MF) stack pointer stack slot 0(SP).
4643 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4644 CallConv == CallingConv::Fast)
4645 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4647 // Count how many bytes are to be pushed on the stack, including the linkage
4648 // area, and parameter passing area. We start with 24/48 bytes, which is
4649 // prereserved space for [SP][CR][LR][3 x unused].
4650 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true,
4652 unsigned NumBytes = LinkageSize;
4654 // Add up all the space actually used.
4655 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
4656 // they all go in registers, but we must reserve stack space for them for
4657 // possible use by the caller. In varargs or 64-bit calls, parameters are
4658 // assigned stack space in order, with padding so Altivec parameters are
4660 unsigned nAltivecParamsAtEnd = 0;
4661 for (unsigned i = 0; i != NumOps; ++i) {
4662 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4663 EVT ArgVT = Outs[i].VT;
4664 // Varargs Altivec parameters are padded to a 16 byte boundary.
4665 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
4666 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
4667 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) {
4668 if (!isVarArg && !isPPC64) {
4669 // Non-varargs Altivec parameters go after all the non-Altivec
4670 // parameters; handle those later so we know how much padding we need.
4671 nAltivecParamsAtEnd++;
4674 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
4675 NumBytes = ((NumBytes+15)/16)*16;
4677 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4680 // Allow for Altivec parameters at the end, if needed.
4681 if (nAltivecParamsAtEnd) {
4682 NumBytes = ((NumBytes+15)/16)*16;
4683 NumBytes += 16*nAltivecParamsAtEnd;
4686 // The prolog code of the callee may store up to 8 GPR argument registers to
4687 // the stack, allowing va_start to index over them in memory if its varargs.
4688 // Because we cannot tell if this is needed on the caller side, we have to
4689 // conservatively assume that it is needed. As such, make sure we have at
4690 // least enough stack space for the caller to store the 8 GPRs.
4691 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4693 // Tail call needs the stack to be aligned.
4694 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4695 CallConv == CallingConv::Fast)
4696 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
4698 // Calculate by how many bytes the stack has to be adjusted in case of tail
4699 // call optimization.
4700 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4702 // To protect arguments on the stack from being clobbered in a tail call,
4703 // force all the loads to happen before doing any other lowering.
4705 Chain = DAG.getStackArgumentTokenFactor(Chain);
4707 // Adjust the stack pointer for the new arguments...
4708 // These operations are automatically eliminated by the prolog/epilog pass
4709 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4711 SDValue CallSeqStart = Chain;
4713 // Load the return address and frame pointer so it can be move somewhere else
4716 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4719 // Set up a copy of the stack pointer for use loading and storing any
4720 // arguments that may not fit in the registers available for argument
4724 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4726 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4728 // Figure out which arguments are going to go in registers, and which in
4729 // memory. Also, if this is a vararg function, floating point operations
4730 // must be stored to our stack, and loaded into integer regs as well, if
4731 // any integer regs are available for argument passing.
4732 unsigned ArgOffset = LinkageSize;
4733 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4735 static const MCPhysReg GPR_32[] = { // 32-bit registers.
4736 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4737 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4739 static const MCPhysReg GPR_64[] = { // 64-bit registers.
4740 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4741 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4743 static const MCPhysReg *FPR = GetFPR();
4745 static const MCPhysReg VR[] = {
4746 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4747 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4749 const unsigned NumGPRs = array_lengthof(GPR_32);
4750 const unsigned NumFPRs = 13;
4751 const unsigned NumVRs = array_lengthof(VR);
4753 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
4755 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4756 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4758 SmallVector<SDValue, 8> MemOpChains;
4759 for (unsigned i = 0; i != NumOps; ++i) {
4760 SDValue Arg = OutVals[i];
4761 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4763 // PtrOff will be used to store the current argument to the stack if a
4764 // register cannot be found for it.
4767 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4769 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4771 // On PPC64, promote integers to 64-bit values.
4772 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4773 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4774 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4775 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4778 // FIXME memcpy is used way more than necessary. Correctness first.
4779 // Note: "by value" is code for passing a structure by value, not
4781 if (Flags.isByVal()) {
4782 unsigned Size = Flags.getByValSize();
4783 // Very small objects are passed right-justified. Everything else is
4784 // passed left-justified.
4785 if (Size==1 || Size==2) {
4786 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4787 if (GPR_idx != NumGPRs) {
4788 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4789 MachinePointerInfo(), VT,
4791 MemOpChains.push_back(Load.getValue(1));
4792 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4794 ArgOffset += PtrByteSize;
4796 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4797 PtrOff.getValueType());
4798 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4799 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4802 ArgOffset += PtrByteSize;
4806 // Copy entire object into memory. There are cases where gcc-generated
4807 // code assumes it is there, even if it could be put entirely into
4808 // registers. (This is not what the doc says.)
4809 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4813 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4814 // copy the pieces of the object that fit into registers from the
4815 // parameter save area.
4816 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4817 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4818 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4819 if (GPR_idx != NumGPRs) {
4820 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4821 MachinePointerInfo(),
4822 false, false, false, 0);
4823 MemOpChains.push_back(Load.getValue(1));
4824 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4825 ArgOffset += PtrByteSize;
4827 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4834 switch (Arg.getSimpleValueType().SimpleTy) {
4835 default: llvm_unreachable("Unexpected ValueType for argument!");
4839 if (GPR_idx != NumGPRs) {
4840 if (Arg.getValueType() == MVT::i1)
4841 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
4843 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4845 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4846 isPPC64, isTailCall, false, MemOpChains,
4847 TailCallArguments, dl);
4849 ArgOffset += PtrByteSize;
4853 if (FPR_idx != NumFPRs) {
4854 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4857 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4858 MachinePointerInfo(), false, false, 0);
4859 MemOpChains.push_back(Store);
4861 // Float varargs are always shadowed in available integer registers
4862 if (GPR_idx != NumGPRs) {
4863 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4864 MachinePointerInfo(), false, false,
4866 MemOpChains.push_back(Load.getValue(1));
4867 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4869 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4870 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4871 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4872 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4873 MachinePointerInfo(),
4874 false, false, false, 0);
4875 MemOpChains.push_back(Load.getValue(1));
4876 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4879 // If we have any FPRs remaining, we may also have GPRs remaining.
4880 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4882 if (GPR_idx != NumGPRs)
4884 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4885 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4889 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4890 isPPC64, isTailCall, false, MemOpChains,
4891 TailCallArguments, dl);
4895 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4902 // These go aligned on the stack, or in the corresponding R registers
4903 // when within range. The Darwin PPC ABI doc claims they also go in
4904 // V registers; in fact gcc does this only for arguments that are
4905 // prototyped, not for those that match the ... We do it for all
4906 // arguments, seems to work.
4907 while (ArgOffset % 16 !=0) {
4908 ArgOffset += PtrByteSize;
4909 if (GPR_idx != NumGPRs)
4912 // We could elide this store in the case where the object fits
4913 // entirely in R registers. Maybe later.
4914 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4915 DAG.getConstant(ArgOffset, PtrVT));
4916 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4917 MachinePointerInfo(), false, false, 0);
4918 MemOpChains.push_back(Store);
4919 if (VR_idx != NumVRs) {
4920 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4921 MachinePointerInfo(),
4922 false, false, false, 0);
4923 MemOpChains.push_back(Load.getValue(1));
4924 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4927 for (unsigned i=0; i<16; i+=PtrByteSize) {
4928 if (GPR_idx == NumGPRs)
4930 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4931 DAG.getConstant(i, PtrVT));
4932 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4933 false, false, false, 0);
4934 MemOpChains.push_back(Load.getValue(1));
4935 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4940 // Non-varargs Altivec params generally go in registers, but have
4941 // stack space allocated at the end.
4942 if (VR_idx != NumVRs) {
4943 // Doesn't have GPR space allocated.
4944 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4945 } else if (nAltivecParamsAtEnd==0) {
4946 // We are emitting Altivec params in order.
4947 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4948 isPPC64, isTailCall, true, MemOpChains,
4949 TailCallArguments, dl);
4955 // If all Altivec parameters fit in registers, as they usually do,
4956 // they get stack space following the non-Altivec parameters. We
4957 // don't track this here because nobody below needs it.
4958 // If there are more Altivec parameters than fit in registers emit
4960 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
4962 // Offset is aligned; skip 1st 12 params which go in V registers.
4963 ArgOffset = ((ArgOffset+15)/16)*16;
4965 for (unsigned i = 0; i != NumOps; ++i) {
4966 SDValue Arg = OutVals[i];
4967 EVT ArgType = Outs[i].VT;
4968 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
4969 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
4972 // We are emitting Altivec params in order.
4973 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4974 isPPC64, isTailCall, true, MemOpChains,
4975 TailCallArguments, dl);
4982 if (!MemOpChains.empty())
4983 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4985 // On Darwin, R12 must contain the address of an indirect callee. This does
4986 // not mean the MTCTR instruction must use R12; it's easier to model this as
4987 // an extra parameter, so do that.
4989 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4990 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4991 !isBLACompatibleAddress(Callee, DAG))
4992 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
4993 PPC::R12), Callee));
4995 // Build a sequence of copy-to-reg nodes chained together with token chain
4996 // and flag operands which copy the outgoing args into the appropriate regs.
4998 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4999 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5000 RegsToPass[i].second, InFlag);
5001 InFlag = Chain.getValue(1);
5005 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
5006 FPOp, true, TailCallArguments);
5008 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
5009 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
5014 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
5015 MachineFunction &MF, bool isVarArg,
5016 const SmallVectorImpl<ISD::OutputArg> &Outs,
5017 LLVMContext &Context) const {
5018 SmallVector<CCValAssign, 16> RVLocs;
5019 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
5021 return CCInfo.CheckReturn(Outs, RetCC_PPC);
5025 PPCTargetLowering::LowerReturn(SDValue Chain,
5026 CallingConv::ID CallConv, bool isVarArg,
5027 const SmallVectorImpl<ISD::OutputArg> &Outs,
5028 const SmallVectorImpl<SDValue> &OutVals,
5029 SDLoc dl, SelectionDAG &DAG) const {
5031 SmallVector<CCValAssign, 16> RVLocs;
5032 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
5033 getTargetMachine(), RVLocs, *DAG.getContext());
5034 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
5037 SmallVector<SDValue, 4> RetOps(1, Chain);
5039 // Copy the result values into the output registers.
5040 for (unsigned i = 0; i != RVLocs.size(); ++i) {
5041 CCValAssign &VA = RVLocs[i];
5042 assert(VA.isRegLoc() && "Can only return in registers!");
5044 SDValue Arg = OutVals[i];
5046 switch (VA.getLocInfo()) {
5047 default: llvm_unreachable("Unknown loc info!");
5048 case CCValAssign::Full: break;
5049 case CCValAssign::AExt:
5050 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
5052 case CCValAssign::ZExt:
5053 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
5055 case CCValAssign::SExt:
5056 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
5060 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
5061 Flag = Chain.getValue(1);
5062 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
5065 RetOps[0] = Chain; // Update chain.
5067 // Add the flag if we have it.
5069 RetOps.push_back(Flag);
5071 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
5074 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
5075 const PPCSubtarget &Subtarget) const {
5076 // When we pop the dynamic allocation we need to restore the SP link.
5079 // Get the corect type for pointers.
5080 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5082 // Construct the stack pointer operand.
5083 bool isPPC64 = Subtarget.isPPC64();
5084 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
5085 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
5087 // Get the operands for the STACKRESTORE.
5088 SDValue Chain = Op.getOperand(0);
5089 SDValue SaveSP = Op.getOperand(1);
5091 // Load the old link SP.
5092 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
5093 MachinePointerInfo(),
5094 false, false, false, 0);
5096 // Restore the stack pointer.
5097 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
5099 // Store the old link SP.
5100 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
5107 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
5108 MachineFunction &MF = DAG.getMachineFunction();
5109 bool isPPC64 = Subtarget.isPPC64();
5110 bool isDarwinABI = Subtarget.isDarwinABI();
5111 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5113 // Get current frame pointer save index. The users of this index will be
5114 // primarily DYNALLOC instructions.
5115 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5116 int RASI = FI->getReturnAddrSaveIndex();
5118 // If the frame pointer save index hasn't been defined yet.
5120 // Find out what the fix offset of the frame pointer save area.
5121 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
5122 // Allocate the frame index for frame pointer save area.
5123 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
5125 FI->setReturnAddrSaveIndex(RASI);
5127 return DAG.getFrameIndex(RASI, PtrVT);
5131 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
5132 MachineFunction &MF = DAG.getMachineFunction();
5133 bool isPPC64 = Subtarget.isPPC64();
5134 bool isDarwinABI = Subtarget.isDarwinABI();
5135 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5137 // Get current frame pointer save index. The users of this index will be
5138 // primarily DYNALLOC instructions.
5139 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5140 int FPSI = FI->getFramePointerSaveIndex();
5142 // If the frame pointer save index hasn't been defined yet.
5144 // Find out what the fix offset of the frame pointer save area.
5145 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
5148 // Allocate the frame index for frame pointer save area.
5149 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
5151 FI->setFramePointerSaveIndex(FPSI);
5153 return DAG.getFrameIndex(FPSI, PtrVT);
5156 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5158 const PPCSubtarget &Subtarget) const {
5160 SDValue Chain = Op.getOperand(0);
5161 SDValue Size = Op.getOperand(1);
5164 // Get the corect type for pointers.
5165 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5167 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
5168 DAG.getConstant(0, PtrVT), Size);
5169 // Construct a node for the frame pointer save index.
5170 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
5171 // Build a DYNALLOC node.
5172 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
5173 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
5174 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
5177 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
5178 SelectionDAG &DAG) const {
5180 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
5181 DAG.getVTList(MVT::i32, MVT::Other),
5182 Op.getOperand(0), Op.getOperand(1));
5185 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
5186 SelectionDAG &DAG) const {
5188 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
5189 Op.getOperand(0), Op.getOperand(1));
5192 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
5193 assert(Op.getValueType() == MVT::i1 &&
5194 "Custom lowering only for i1 loads");
5196 // First, load 8 bits into 32 bits, then truncate to 1 bit.
5199 LoadSDNode *LD = cast<LoadSDNode>(Op);
5201 SDValue Chain = LD->getChain();
5202 SDValue BasePtr = LD->getBasePtr();
5203 MachineMemOperand *MMO = LD->getMemOperand();
5205 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(), Chain,
5206 BasePtr, MVT::i8, MMO);
5207 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
5209 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
5210 return DAG.getMergeValues(Ops, dl);
5213 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
5214 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
5215 "Custom lowering only for i1 stores");
5217 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
5220 StoreSDNode *ST = cast<StoreSDNode>(Op);
5222 SDValue Chain = ST->getChain();
5223 SDValue BasePtr = ST->getBasePtr();
5224 SDValue Value = ST->getValue();
5225 MachineMemOperand *MMO = ST->getMemOperand();
5227 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(), Value);
5228 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
5231 // FIXME: Remove this once the ANDI glue bug is fixed:
5232 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
5233 assert(Op.getValueType() == MVT::i1 &&
5234 "Custom lowering only for i1 results");
5237 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
5241 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
5243 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5244 // Not FP? Not a fsel.
5245 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
5246 !Op.getOperand(2).getValueType().isFloatingPoint())
5249 // We might be able to do better than this under some circumstances, but in
5250 // general, fsel-based lowering of select is a finite-math-only optimization.
5251 // For more information, see section F.3 of the 2.06 ISA specification.
5252 if (!DAG.getTarget().Options.NoInfsFPMath ||
5253 !DAG.getTarget().Options.NoNaNsFPMath)
5256 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5258 EVT ResVT = Op.getValueType();
5259 EVT CmpVT = Op.getOperand(0).getValueType();
5260 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5261 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
5264 // If the RHS of the comparison is a 0.0, we don't need to do the
5265 // subtraction at all.
5267 if (isFloatingPointZero(RHS))
5269 default: break; // SETUO etc aren't handled by fsel.
5273 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5274 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5275 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5276 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5277 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5278 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5279 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
5282 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5285 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5286 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5287 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5290 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5293 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5294 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5295 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5296 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
5301 default: break; // SETUO etc aren't handled by fsel.
5305 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5306 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5307 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5308 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5309 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5310 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5311 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5312 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
5315 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5316 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5317 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5318 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5321 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5322 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5323 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5324 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5327 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5328 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5329 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5330 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5333 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5334 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5335 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5336 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5341 // FIXME: Split this code up when LegalizeDAGTypes lands.
5342 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
5344 assert(Op.getOperand(0).getValueType().isFloatingPoint());
5345 SDValue Src = Op.getOperand(0);
5346 if (Src.getValueType() == MVT::f32)
5347 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
5350 switch (Op.getSimpleValueType().SimpleTy) {
5351 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
5353 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
5354 (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ :
5359 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
5360 "i64 FP_TO_UINT is supported only with FPCVT");
5361 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
5367 // Convert the FP value to an int value through memory.
5368 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
5369 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
5370 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
5371 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
5372 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
5374 // Emit a store to the stack slot.
5377 MachineFunction &MF = DAG.getMachineFunction();
5378 MachineMemOperand *MMO =
5379 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
5380 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
5381 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
5382 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
5384 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
5385 MPI, false, false, 0);
5387 // Result is a load from the stack slot. If loading 4 bytes, make sure to
5389 if (Op.getValueType() == MVT::i32 && !i32Stack) {
5390 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
5391 DAG.getConstant(4, FIPtr.getValueType()));
5392 MPI = MachinePointerInfo();
5395 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MPI,
5396 false, false, false, 0);
5399 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
5400 SelectionDAG &DAG) const {
5402 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
5403 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
5406 if (Op.getOperand(0).getValueType() == MVT::i1)
5407 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
5408 DAG.getConstantFP(1.0, Op.getValueType()),
5409 DAG.getConstantFP(0.0, Op.getValueType()));
5411 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
5412 "UINT_TO_FP is supported only with FPCVT");
5414 // If we have FCFIDS, then use it when converting to single-precision.
5415 // Otherwise, convert to double-precision and then round.
5416 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5417 (Op.getOpcode() == ISD::UINT_TO_FP ?
5418 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
5419 (Op.getOpcode() == ISD::UINT_TO_FP ?
5420 PPCISD::FCFIDU : PPCISD::FCFID);
5421 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5422 MVT::f32 : MVT::f64;
5424 if (Op.getOperand(0).getValueType() == MVT::i64) {
5425 SDValue SINT = Op.getOperand(0);
5426 // When converting to single-precision, we actually need to convert
5427 // to double-precision first and then round to single-precision.
5428 // To avoid double-rounding effects during that operation, we have
5429 // to prepare the input operand. Bits that might be truncated when
5430 // converting to double-precision are replaced by a bit that won't
5431 // be lost at this stage, but is below the single-precision rounding
5434 // However, if -enable-unsafe-fp-math is in effect, accept double
5435 // rounding to avoid the extra overhead.
5436 if (Op.getValueType() == MVT::f32 &&
5437 !Subtarget.hasFPCVT() &&
5438 !DAG.getTarget().Options.UnsafeFPMath) {
5440 // Twiddle input to make sure the low 11 bits are zero. (If this
5441 // is the case, we are guaranteed the value will fit into the 53 bit
5442 // mantissa of an IEEE double-precision value without rounding.)
5443 // If any of those low 11 bits were not zero originally, make sure
5444 // bit 12 (value 2048) is set instead, so that the final rounding
5445 // to single-precision gets the correct result.
5446 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5447 SINT, DAG.getConstant(2047, MVT::i64));
5448 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
5449 Round, DAG.getConstant(2047, MVT::i64));
5450 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
5451 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5452 Round, DAG.getConstant(-2048, MVT::i64));
5454 // However, we cannot use that value unconditionally: if the magnitude
5455 // of the input value is small, the bit-twiddling we did above might
5456 // end up visibly changing the output. Fortunately, in that case, we
5457 // don't need to twiddle bits since the original input will convert
5458 // exactly to double-precision floating-point already. Therefore,
5459 // construct a conditional to use the original value if the top 11
5460 // bits are all sign-bit copies, and use the rounded value computed
5462 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
5463 SINT, DAG.getConstant(53, MVT::i32));
5464 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
5465 Cond, DAG.getConstant(1, MVT::i64));
5466 Cond = DAG.getSetCC(dl, MVT::i32,
5467 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
5469 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
5472 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
5473 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
5475 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5476 FP = DAG.getNode(ISD::FP_ROUND, dl,
5477 MVT::f32, FP, DAG.getIntPtrConstant(0));
5481 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
5482 "Unhandled INT_TO_FP type in custom expander!");
5483 // Since we only generate this in 64-bit mode, we can take advantage of
5484 // 64-bit registers. In particular, sign extend the input value into the
5485 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
5486 // then lfd it and fcfid it.
5487 MachineFunction &MF = DAG.getMachineFunction();
5488 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
5489 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5492 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
5493 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
5494 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5496 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
5497 MachinePointerInfo::getFixedStack(FrameIdx),
5500 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
5501 "Expected an i32 store");
5502 MachineMemOperand *MMO =
5503 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
5504 MachineMemOperand::MOLoad, 4, 4);
5505 SDValue Ops[] = { Store, FIdx };
5506 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
5507 PPCISD::LFIWZX : PPCISD::LFIWAX,
5508 dl, DAG.getVTList(MVT::f64, MVT::Other),
5509 Ops, MVT::i32, MMO);
5511 assert(Subtarget.isPPC64() &&
5512 "i32->FP without LFIWAX supported only on PPC64");
5514 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
5515 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5517 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
5520 // STD the extended value into the stack slot.
5521 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
5522 MachinePointerInfo::getFixedStack(FrameIdx),
5525 // Load the value as a double.
5526 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
5527 MachinePointerInfo::getFixedStack(FrameIdx),
5528 false, false, false, 0);
5531 // FCFID it and return it.
5532 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
5533 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5534 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
5538 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
5539 SelectionDAG &DAG) const {
5542 The rounding mode is in bits 30:31 of FPSR, and has the following
5549 FLT_ROUNDS, on the other hand, expects the following:
5556 To perform the conversion, we do:
5557 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
5560 MachineFunction &MF = DAG.getMachineFunction();
5561 EVT VT = Op.getValueType();
5562 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5564 // Save FP Control Word to register
5566 MVT::f64, // return register
5567 MVT::Glue // unused in this context
5569 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
5571 // Save FP register to stack slot
5572 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5573 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
5574 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
5575 StackSlot, MachinePointerInfo(), false, false,0);
5577 // Load FP Control Word from low 32 bits of stack slot.
5578 SDValue Four = DAG.getConstant(4, PtrVT);
5579 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
5580 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
5581 false, false, false, 0);
5583 // Transform as necessary
5585 DAG.getNode(ISD::AND, dl, MVT::i32,
5586 CWD, DAG.getConstant(3, MVT::i32));
5588 DAG.getNode(ISD::SRL, dl, MVT::i32,
5589 DAG.getNode(ISD::AND, dl, MVT::i32,
5590 DAG.getNode(ISD::XOR, dl, MVT::i32,
5591 CWD, DAG.getConstant(3, MVT::i32)),
5592 DAG.getConstant(3, MVT::i32)),
5593 DAG.getConstant(1, MVT::i32));
5596 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
5598 return DAG.getNode((VT.getSizeInBits() < 16 ?
5599 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
5602 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5603 EVT VT = Op.getValueType();
5604 unsigned BitWidth = VT.getSizeInBits();
5606 assert(Op.getNumOperands() == 3 &&
5607 VT == Op.getOperand(1).getValueType() &&
5610 // Expand into a bunch of logical ops. Note that these ops
5611 // depend on the PPC behavior for oversized shift amounts.
5612 SDValue Lo = Op.getOperand(0);
5613 SDValue Hi = Op.getOperand(1);
5614 SDValue Amt = Op.getOperand(2);
5615 EVT AmtVT = Amt.getValueType();
5617 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5618 DAG.getConstant(BitWidth, AmtVT), Amt);
5619 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
5620 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5621 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5622 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5623 DAG.getConstant(-BitWidth, AmtVT));
5624 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5625 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5626 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
5627 SDValue OutOps[] = { OutLo, OutHi };
5628 return DAG.getMergeValues(OutOps, dl);
5631 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5632 EVT VT = Op.getValueType();
5634 unsigned BitWidth = VT.getSizeInBits();
5635 assert(Op.getNumOperands() == 3 &&
5636 VT == Op.getOperand(1).getValueType() &&
5639 // Expand into a bunch of logical ops. Note that these ops
5640 // depend on the PPC behavior for oversized shift amounts.
5641 SDValue Lo = Op.getOperand(0);
5642 SDValue Hi = Op.getOperand(1);
5643 SDValue Amt = Op.getOperand(2);
5644 EVT AmtVT = Amt.getValueType();
5646 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5647 DAG.getConstant(BitWidth, AmtVT), Amt);
5648 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5649 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5650 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5651 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5652 DAG.getConstant(-BitWidth, AmtVT));
5653 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
5654 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5655 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
5656 SDValue OutOps[] = { OutLo, OutHi };
5657 return DAG.getMergeValues(OutOps, dl);
5660 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
5662 EVT VT = Op.getValueType();
5663 unsigned BitWidth = VT.getSizeInBits();
5664 assert(Op.getNumOperands() == 3 &&
5665 VT == Op.getOperand(1).getValueType() &&
5668 // Expand into a bunch of logical ops, followed by a select_cc.
5669 SDValue Lo = Op.getOperand(0);
5670 SDValue Hi = Op.getOperand(1);
5671 SDValue Amt = Op.getOperand(2);
5672 EVT AmtVT = Amt.getValueType();
5674 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5675 DAG.getConstant(BitWidth, AmtVT), Amt);
5676 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5677 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5678 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5679 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5680 DAG.getConstant(-BitWidth, AmtVT));
5681 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
5682 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
5683 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
5684 Tmp4, Tmp6, ISD::SETLE);
5685 SDValue OutOps[] = { OutLo, OutHi };
5686 return DAG.getMergeValues(OutOps, dl);
5689 //===----------------------------------------------------------------------===//
5690 // Vector related lowering.
5693 /// BuildSplatI - Build a canonical splati of Val with an element size of
5694 /// SplatSize. Cast the result to VT.
5695 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
5696 SelectionDAG &DAG, SDLoc dl) {
5697 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
5699 static const EVT VTys[] = { // canonical VT to use for each size.
5700 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
5703 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
5705 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
5709 EVT CanonicalVT = VTys[SplatSize-1];
5711 // Build a canonical splat for this value.
5712 SDValue Elt = DAG.getConstant(Val, MVT::i32);
5713 SmallVector<SDValue, 8> Ops;
5714 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
5715 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
5716 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
5719 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
5720 /// specified intrinsic ID.
5721 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
5722 SelectionDAG &DAG, SDLoc dl,
5723 EVT DestVT = MVT::Other) {
5724 if (DestVT == MVT::Other) DestVT = Op.getValueType();
5725 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5726 DAG.getConstant(IID, MVT::i32), Op);
5729 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
5730 /// specified intrinsic ID.
5731 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
5732 SelectionDAG &DAG, SDLoc dl,
5733 EVT DestVT = MVT::Other) {
5734 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
5735 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5736 DAG.getConstant(IID, MVT::i32), LHS, RHS);
5739 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
5740 /// specified intrinsic ID.
5741 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
5742 SDValue Op2, SelectionDAG &DAG,
5743 SDLoc dl, EVT DestVT = MVT::Other) {
5744 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
5745 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5746 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
5750 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
5751 /// amount. The result has the specified value type.
5752 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
5753 EVT VT, SelectionDAG &DAG, SDLoc dl) {
5754 // Force LHS/RHS to be the right type.
5755 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
5756 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
5759 for (unsigned i = 0; i != 16; ++i)
5761 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
5762 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5765 // If this is a case we can't handle, return null and let the default
5766 // expansion code take care of it. If we CAN select this case, and if it
5767 // selects to a single instruction, return Op. Otherwise, if we can codegen
5768 // this case more efficiently than a constant pool load, lower it to the
5769 // sequence of ops that should be used.
5770 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
5771 SelectionDAG &DAG) const {
5773 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5774 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
5776 // Check if this is a splat of a constant value.
5777 APInt APSplatBits, APSplatUndef;
5778 unsigned SplatBitSize;
5780 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
5781 HasAnyUndefs, 0, true) || SplatBitSize > 32)
5784 unsigned SplatBits = APSplatBits.getZExtValue();
5785 unsigned SplatUndef = APSplatUndef.getZExtValue();
5786 unsigned SplatSize = SplatBitSize / 8;
5788 // First, handle single instruction cases.
5791 if (SplatBits == 0) {
5792 // Canonicalize all zero vectors to be v4i32.
5793 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5794 SDValue Z = DAG.getConstant(0, MVT::i32);
5795 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5796 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
5801 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
5802 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
5804 if (SextVal >= -16 && SextVal <= 15)
5805 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
5808 // Two instruction sequences.
5810 // If this value is in the range [-32,30] and is even, use:
5811 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
5812 // If this value is in the range [17,31] and is odd, use:
5813 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
5814 // If this value is in the range [-31,-17] and is odd, use:
5815 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
5816 // Note the last two are three-instruction sequences.
5817 if (SextVal >= -32 && SextVal <= 31) {
5818 // To avoid having these optimizations undone by constant folding,
5819 // we convert to a pseudo that will be expanded later into one of
5821 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
5822 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
5823 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
5824 SDValue EltSize = DAG.getConstant(SplatSize, MVT::i32);
5825 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
5826 if (VT == Op.getValueType())
5829 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
5832 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
5833 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
5835 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
5836 // Make -1 and vspltisw -1:
5837 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
5839 // Make the VSLW intrinsic, computing 0x8000_0000.
5840 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
5843 // xor by OnesV to invert it.
5844 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5845 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5848 // The remaining cases assume either big endian element order or
5849 // a splat-size that equates to the element size of the vector
5850 // to be built. An example that doesn't work for little endian is
5851 // {0, -1, 0, -1, 0, -1, 0, -1} which has a splat size of 32 bits
5852 // and a vector element size of 16 bits. The code below will
5853 // produce the vector in big endian element order, which for little
5854 // endian is {-1, 0, -1, 0, -1, 0, -1, 0}.
5856 // For now, just avoid these optimizations in that case.
5857 // FIXME: Develop correct optimizations for LE with mismatched
5858 // splat and element sizes.
5860 if (Subtarget.isLittleEndian() &&
5861 SplatSize != Op.getValueType().getVectorElementType().getSizeInBits())
5864 // Check to see if this is a wide variety of vsplti*, binop self cases.
5865 static const signed char SplatCsts[] = {
5866 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
5867 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
5870 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
5871 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
5872 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
5873 int i = SplatCsts[idx];
5875 // Figure out what shift amount will be used by altivec if shifted by i in
5877 unsigned TypeShiftAmt = i & (SplatBitSize-1);
5879 // vsplti + shl self.
5880 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
5881 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5882 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5883 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
5884 Intrinsic::ppc_altivec_vslw
5886 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5887 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5890 // vsplti + srl self.
5891 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5892 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5893 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5894 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
5895 Intrinsic::ppc_altivec_vsrw
5897 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5898 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5901 // vsplti + sra self.
5902 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5903 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5904 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5905 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
5906 Intrinsic::ppc_altivec_vsraw
5908 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5909 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5912 // vsplti + rol self.
5913 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
5914 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
5915 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5916 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5917 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
5918 Intrinsic::ppc_altivec_vrlw
5920 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5921 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5924 // t = vsplti c, result = vsldoi t, t, 1
5925 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
5926 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5927 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
5929 // t = vsplti c, result = vsldoi t, t, 2
5930 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
5931 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5932 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
5934 // t = vsplti c, result = vsldoi t, t, 3
5935 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
5936 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5937 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
5944 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5945 /// the specified operations to build the shuffle.
5946 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5947 SDValue RHS, SelectionDAG &DAG,
5949 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5950 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5951 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5954 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5966 if (OpNum == OP_COPY) {
5967 if (LHSID == (1*9+2)*9+3) return LHS;
5968 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5972 SDValue OpLHS, OpRHS;
5973 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5974 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5978 default: llvm_unreachable("Unknown i32 permute!");
5980 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
5981 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
5982 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
5983 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
5986 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
5987 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
5988 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
5989 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
5992 for (unsigned i = 0; i != 16; ++i)
5993 ShufIdxs[i] = (i&3)+0;
5996 for (unsigned i = 0; i != 16; ++i)
5997 ShufIdxs[i] = (i&3)+4;
6000 for (unsigned i = 0; i != 16; ++i)
6001 ShufIdxs[i] = (i&3)+8;
6004 for (unsigned i = 0; i != 16; ++i)
6005 ShufIdxs[i] = (i&3)+12;
6008 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
6010 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
6012 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
6014 EVT VT = OpLHS.getValueType();
6015 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
6016 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
6017 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
6018 return DAG.getNode(ISD::BITCAST, dl, VT, T);
6021 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
6022 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
6023 /// return the code it can be lowered into. Worst case, it can always be
6024 /// lowered into a vperm.
6025 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
6026 SelectionDAG &DAG) const {
6028 SDValue V1 = Op.getOperand(0);
6029 SDValue V2 = Op.getOperand(1);
6030 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6031 EVT VT = Op.getValueType();
6032 bool isLittleEndian = Subtarget.isLittleEndian();
6034 // Cases that are handled by instructions that take permute immediates
6035 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
6036 // selected by the instruction selector.
6037 if (V2.getOpcode() == ISD::UNDEF) {
6038 if (PPC::isSplatShuffleMask(SVOp, 1) ||
6039 PPC::isSplatShuffleMask(SVOp, 2) ||
6040 PPC::isSplatShuffleMask(SVOp, 4) ||
6041 PPC::isVPKUWUMShuffleMask(SVOp, true, DAG) ||
6042 PPC::isVPKUHUMShuffleMask(SVOp, true, DAG) ||
6043 PPC::isVSLDOIShuffleMask(SVOp, true, DAG) != -1 ||
6044 PPC::isVMRGLShuffleMask(SVOp, 1, 1, DAG) ||
6045 PPC::isVMRGLShuffleMask(SVOp, 2, 1, DAG) ||
6046 PPC::isVMRGLShuffleMask(SVOp, 4, 1, DAG) ||
6047 PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) ||
6048 PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) ||
6049 PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG)) {
6054 // Altivec has a variety of "shuffle immediates" that take two vector inputs
6055 // and produce a fixed permutation. If any of these match, do not lower to
6057 unsigned int ShuffleKind = isLittleEndian ? 2 : 0;
6058 if (PPC::isVPKUWUMShuffleMask(SVOp, false, DAG) ||
6059 PPC::isVPKUHUMShuffleMask(SVOp, false, DAG) ||
6060 PPC::isVSLDOIShuffleMask(SVOp, false, DAG) != -1 ||
6061 PPC::isVMRGLShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6062 PPC::isVMRGLShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6063 PPC::isVMRGLShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
6064 PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6065 PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6066 PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG))
6069 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
6070 // perfect shuffle table to emit an optimal matching sequence.
6071 ArrayRef<int> PermMask = SVOp->getMask();
6073 unsigned PFIndexes[4];
6074 bool isFourElementShuffle = true;
6075 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
6076 unsigned EltNo = 8; // Start out undef.
6077 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
6078 if (PermMask[i*4+j] < 0)
6079 continue; // Undef, ignore it.
6081 unsigned ByteSource = PermMask[i*4+j];
6082 if ((ByteSource & 3) != j) {
6083 isFourElementShuffle = false;
6088 EltNo = ByteSource/4;
6089 } else if (EltNo != ByteSource/4) {
6090 isFourElementShuffle = false;
6094 PFIndexes[i] = EltNo;
6097 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
6098 // perfect shuffle vector to determine if it is cost effective to do this as
6099 // discrete instructions, or whether we should use a vperm.
6100 // For now, we skip this for little endian until such time as we have a
6101 // little-endian perfect shuffle table.
6102 if (isFourElementShuffle && !isLittleEndian) {
6103 // Compute the index in the perfect shuffle table.
6104 unsigned PFTableIndex =
6105 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
6107 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6108 unsigned Cost = (PFEntry >> 30);
6110 // Determining when to avoid vperm is tricky. Many things affect the cost
6111 // of vperm, particularly how many times the perm mask needs to be computed.
6112 // For example, if the perm mask can be hoisted out of a loop or is already
6113 // used (perhaps because there are multiple permutes with the same shuffle
6114 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
6115 // the loop requires an extra register.
6117 // As a compromise, we only emit discrete instructions if the shuffle can be
6118 // generated in 3 or fewer operations. When we have loop information
6119 // available, if this block is within a loop, we should avoid using vperm
6120 // for 3-operation perms and use a constant pool load instead.
6122 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
6125 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
6126 // vector that will get spilled to the constant pool.
6127 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
6129 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
6130 // that it is in input element units, not in bytes. Convert now.
6132 // For little endian, the order of the input vectors is reversed, and
6133 // the permutation mask is complemented with respect to 31. This is
6134 // necessary to produce proper semantics with the big-endian-biased vperm
6136 EVT EltVT = V1.getValueType().getVectorElementType();
6137 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
6139 SmallVector<SDValue, 16> ResultMask;
6140 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
6141 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
6143 for (unsigned j = 0; j != BytesPerElement; ++j)
6145 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement+j),
6148 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
6152 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
6155 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
6158 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
6162 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
6163 /// altivec comparison. If it is, return true and fill in Opc/isDot with
6164 /// information about the intrinsic.
6165 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
6167 unsigned IntrinsicID =
6168 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
6171 switch (IntrinsicID) {
6172 default: return false;
6173 // Comparison predicates.
6174 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
6175 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
6176 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
6177 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
6178 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
6179 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
6180 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
6181 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
6182 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
6183 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
6184 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
6185 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
6186 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
6188 // Normal Comparisons.
6189 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
6190 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
6191 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
6192 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
6193 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
6194 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
6195 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
6196 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
6197 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
6198 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
6199 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
6200 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
6201 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
6206 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
6207 /// lower, do it, otherwise return null.
6208 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
6209 SelectionDAG &DAG) const {
6210 // If this is a lowered altivec predicate compare, CompareOpc is set to the
6211 // opcode number of the comparison.
6215 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
6216 return SDValue(); // Don't custom lower most intrinsics.
6218 // If this is a non-dot comparison, make the VCMP node and we are done.
6220 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
6221 Op.getOperand(1), Op.getOperand(2),
6222 DAG.getConstant(CompareOpc, MVT::i32));
6223 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
6226 // Create the PPCISD altivec 'dot' comparison node.
6228 Op.getOperand(2), // LHS
6229 Op.getOperand(3), // RHS
6230 DAG.getConstant(CompareOpc, MVT::i32)
6232 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
6233 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
6235 // Now that we have the comparison, emit a copy from the CR to a GPR.
6236 // This is flagged to the above dot comparison.
6237 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
6238 DAG.getRegister(PPC::CR6, MVT::i32),
6239 CompNode.getValue(1));
6241 // Unpack the result based on how the target uses it.
6242 unsigned BitNo; // Bit # of CR6.
6243 bool InvertBit; // Invert result?
6244 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
6245 default: // Can't happen, don't crash on invalid number though.
6246 case 0: // Return the value of the EQ bit of CR6.
6247 BitNo = 0; InvertBit = false;
6249 case 1: // Return the inverted value of the EQ bit of CR6.
6250 BitNo = 0; InvertBit = true;
6252 case 2: // Return the value of the LT bit of CR6.
6253 BitNo = 2; InvertBit = false;
6255 case 3: // Return the inverted value of the LT bit of CR6.
6256 BitNo = 2; InvertBit = true;
6260 // Shift the bit into the low position.
6261 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
6262 DAG.getConstant(8-(3-BitNo), MVT::i32));
6264 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
6265 DAG.getConstant(1, MVT::i32));
6267 // If we are supposed to, toggle the bit.
6269 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
6270 DAG.getConstant(1, MVT::i32));
6274 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
6275 SelectionDAG &DAG) const {
6277 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
6278 // instructions), but for smaller types, we need to first extend up to v2i32
6279 // before doing going farther.
6280 if (Op.getValueType() == MVT::v2i64) {
6281 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
6282 if (ExtVT != MVT::v2i32) {
6283 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
6284 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
6285 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
6286 ExtVT.getVectorElementType(), 4)));
6287 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
6288 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
6289 DAG.getValueType(MVT::v2i32));
6298 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
6299 SelectionDAG &DAG) const {
6301 // Create a stack slot that is 16-byte aligned.
6302 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6303 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
6304 EVT PtrVT = getPointerTy();
6305 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6307 // Store the input value into Value#0 of the stack slot.
6308 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
6309 Op.getOperand(0), FIdx, MachinePointerInfo(),
6312 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
6313 false, false, false, 0);
6316 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
6318 if (Op.getValueType() == MVT::v4i32) {
6319 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6321 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
6322 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
6324 SDValue RHSSwap = // = vrlw RHS, 16
6325 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
6327 // Shrinkify inputs to v8i16.
6328 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
6329 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
6330 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
6332 // Low parts multiplied together, generating 32-bit results (we ignore the
6334 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
6335 LHS, RHS, DAG, dl, MVT::v4i32);
6337 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
6338 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
6339 // Shift the high parts up 16 bits.
6340 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
6342 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
6343 } else if (Op.getValueType() == MVT::v8i16) {
6344 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6346 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
6348 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
6349 LHS, RHS, Zero, DAG, dl);
6350 } else if (Op.getValueType() == MVT::v16i8) {
6351 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6352 bool isLittleEndian = Subtarget.isLittleEndian();
6354 // Multiply the even 8-bit parts, producing 16-bit sums.
6355 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
6356 LHS, RHS, DAG, dl, MVT::v8i16);
6357 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
6359 // Multiply the odd 8-bit parts, producing 16-bit sums.
6360 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
6361 LHS, RHS, DAG, dl, MVT::v8i16);
6362 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
6364 // Merge the results together. Because vmuleub and vmuloub are
6365 // instructions with a big-endian bias, we must reverse the
6366 // element numbering and reverse the meaning of "odd" and "even"
6367 // when generating little endian code.
6369 for (unsigned i = 0; i != 8; ++i) {
6370 if (isLittleEndian) {
6372 Ops[i*2+1] = 2*i+16;
6375 Ops[i*2+1] = 2*i+1+16;
6379 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
6381 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
6383 llvm_unreachable("Unknown mul to lower!");
6387 /// LowerOperation - Provide custom lowering hooks for some operations.
6389 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6390 switch (Op.getOpcode()) {
6391 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
6392 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6393 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
6394 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6395 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6396 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6397 case ISD::SETCC: return LowerSETCC(Op, DAG);
6398 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
6399 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
6401 return LowerVASTART(Op, DAG, Subtarget);
6404 return LowerVAARG(Op, DAG, Subtarget);
6407 return LowerVACOPY(Op, DAG, Subtarget);
6409 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget);
6410 case ISD::DYNAMIC_STACKALLOC:
6411 return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget);
6413 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
6414 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
6416 case ISD::LOAD: return LowerLOAD(Op, DAG);
6417 case ISD::STORE: return LowerSTORE(Op, DAG);
6418 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
6419 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6420 case ISD::FP_TO_UINT:
6421 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
6423 case ISD::UINT_TO_FP:
6424 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6425 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6427 // Lower 64-bit shifts.
6428 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
6429 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
6430 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
6432 // Vector-related lowering.
6433 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6434 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6435 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6436 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6437 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
6438 case ISD::MUL: return LowerMUL(Op, DAG);
6440 // For counter-based loop handling.
6441 case ISD::INTRINSIC_W_CHAIN: return SDValue();
6443 // Frame & Return address.
6444 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6445 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6449 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
6450 SmallVectorImpl<SDValue>&Results,
6451 SelectionDAG &DAG) const {
6452 const TargetMachine &TM = getTargetMachine();
6454 switch (N->getOpcode()) {
6456 llvm_unreachable("Do not know how to custom type legalize this operation!");
6457 case ISD::INTRINSIC_W_CHAIN: {
6458 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
6459 Intrinsic::ppc_is_decremented_ctr_nonzero)
6462 assert(N->getValueType(0) == MVT::i1 &&
6463 "Unexpected result type for CTR decrement intrinsic");
6464 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
6465 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
6466 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
6469 Results.push_back(NewInt);
6470 Results.push_back(NewInt.getValue(1));
6474 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
6475 || TM.getSubtarget<PPCSubtarget>().isPPC64())
6478 EVT VT = N->getValueType(0);
6480 if (VT == MVT::i64) {
6481 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget);
6483 Results.push_back(NewNode);
6484 Results.push_back(NewNode.getValue(1));
6488 case ISD::FP_ROUND_INREG: {
6489 assert(N->getValueType(0) == MVT::ppcf128);
6490 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
6491 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6492 MVT::f64, N->getOperand(0),
6493 DAG.getIntPtrConstant(0));
6494 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6495 MVT::f64, N->getOperand(0),
6496 DAG.getIntPtrConstant(1));
6498 // Add the two halves of the long double in round-to-zero mode.
6499 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
6501 // We know the low half is about to be thrown away, so just use something
6503 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
6507 case ISD::FP_TO_SINT:
6508 // LowerFP_TO_INT() can only handle f32 and f64.
6509 if (N->getOperand(0).getValueType() == MVT::ppcf128)
6511 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
6517 //===----------------------------------------------------------------------===//
6518 // Other Lowering Code
6519 //===----------------------------------------------------------------------===//
6522 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
6523 bool is64bit, unsigned BinOpcode) const {
6524 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6525 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6527 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6528 MachineFunction *F = BB->getParent();
6529 MachineFunction::iterator It = BB;
6532 unsigned dest = MI->getOperand(0).getReg();
6533 unsigned ptrA = MI->getOperand(1).getReg();
6534 unsigned ptrB = MI->getOperand(2).getReg();
6535 unsigned incr = MI->getOperand(3).getReg();
6536 DebugLoc dl = MI->getDebugLoc();
6538 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6539 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6540 F->insert(It, loopMBB);
6541 F->insert(It, exitMBB);
6542 exitMBB->splice(exitMBB->begin(), BB,
6543 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6544 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6546 MachineRegisterInfo &RegInfo = F->getRegInfo();
6547 unsigned TmpReg = (!BinOpcode) ? incr :
6548 RegInfo.createVirtualRegister(
6549 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6550 (const TargetRegisterClass *) &PPC::GPRCRegClass);
6554 // fallthrough --> loopMBB
6555 BB->addSuccessor(loopMBB);
6558 // l[wd]arx dest, ptr
6559 // add r0, dest, incr
6560 // st[wd]cx. r0, ptr
6562 // fallthrough --> exitMBB
6564 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6565 .addReg(ptrA).addReg(ptrB);
6567 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
6568 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6569 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
6570 BuildMI(BB, dl, TII->get(PPC::BCC))
6571 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6572 BB->addSuccessor(loopMBB);
6573 BB->addSuccessor(exitMBB);
6582 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
6583 MachineBasicBlock *BB,
6584 bool is8bit, // operation
6585 unsigned BinOpcode) const {
6586 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6587 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6588 // In 64 bit mode we have to use 64 bits for addresses, even though the
6589 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
6590 // registers without caring whether they're 32 or 64, but here we're
6591 // doing actual arithmetic on the addresses.
6592 bool is64bit = Subtarget.isPPC64();
6593 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6595 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6596 MachineFunction *F = BB->getParent();
6597 MachineFunction::iterator It = BB;
6600 unsigned dest = MI->getOperand(0).getReg();
6601 unsigned ptrA = MI->getOperand(1).getReg();
6602 unsigned ptrB = MI->getOperand(2).getReg();
6603 unsigned incr = MI->getOperand(3).getReg();
6604 DebugLoc dl = MI->getDebugLoc();
6606 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6607 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6608 F->insert(It, loopMBB);
6609 F->insert(It, exitMBB);
6610 exitMBB->splice(exitMBB->begin(), BB,
6611 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6612 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6614 MachineRegisterInfo &RegInfo = F->getRegInfo();
6615 const TargetRegisterClass *RC =
6616 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6617 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6618 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6619 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6620 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6621 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
6622 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6623 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6624 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6625 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6626 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
6627 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6628 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6630 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
6634 // fallthrough --> loopMBB
6635 BB->addSuccessor(loopMBB);
6637 // The 4-byte load must be aligned, while a char or short may be
6638 // anywhere in the word. Hence all this nasty bookkeeping code.
6639 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6640 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6641 // xori shift, shift1, 24 [16]
6642 // rlwinm ptr, ptr1, 0, 0, 29
6643 // slw incr2, incr, shift
6644 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6645 // slw mask, mask2, shift
6647 // lwarx tmpDest, ptr
6648 // add tmp, tmpDest, incr2
6649 // andc tmp2, tmpDest, mask
6650 // and tmp3, tmp, mask
6651 // or tmp4, tmp3, tmp2
6654 // fallthrough --> exitMBB
6655 // srw dest, tmpDest, shift
6656 if (ptrA != ZeroReg) {
6657 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6658 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6659 .addReg(ptrA).addReg(ptrB);
6663 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6664 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6665 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6666 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6668 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6669 .addReg(Ptr1Reg).addImm(0).addImm(61);
6671 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6672 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6673 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
6674 .addReg(incr).addReg(ShiftReg);
6676 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6678 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6679 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
6681 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6682 .addReg(Mask2Reg).addReg(ShiftReg);
6685 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6686 .addReg(ZeroReg).addReg(PtrReg);
6688 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
6689 .addReg(Incr2Reg).addReg(TmpDestReg);
6690 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
6691 .addReg(TmpDestReg).addReg(MaskReg);
6692 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
6693 .addReg(TmpReg).addReg(MaskReg);
6694 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
6695 .addReg(Tmp3Reg).addReg(Tmp2Reg);
6696 BuildMI(BB, dl, TII->get(PPC::STWCX))
6697 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
6698 BuildMI(BB, dl, TII->get(PPC::BCC))
6699 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6700 BB->addSuccessor(loopMBB);
6701 BB->addSuccessor(exitMBB);
6706 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
6711 llvm::MachineBasicBlock*
6712 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
6713 MachineBasicBlock *MBB) const {
6714 DebugLoc DL = MI->getDebugLoc();
6715 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6717 MachineFunction *MF = MBB->getParent();
6718 MachineRegisterInfo &MRI = MF->getRegInfo();
6720 const BasicBlock *BB = MBB->getBasicBlock();
6721 MachineFunction::iterator I = MBB;
6725 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6726 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6728 unsigned DstReg = MI->getOperand(0).getReg();
6729 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
6730 assert(RC->hasType(MVT::i32) && "Invalid destination!");
6731 unsigned mainDstReg = MRI.createVirtualRegister(RC);
6732 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
6734 MVT PVT = getPointerTy();
6735 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6736 "Invalid Pointer Size!");
6737 // For v = setjmp(buf), we generate
6740 // SjLjSetup mainMBB
6746 // buf[LabelOffset] = LR
6750 // v = phi(main, restore)
6753 MachineBasicBlock *thisMBB = MBB;
6754 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
6755 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
6756 MF->insert(I, mainMBB);
6757 MF->insert(I, sinkMBB);
6759 MachineInstrBuilder MIB;
6761 // Transfer the remainder of BB and its successor edges to sinkMBB.
6762 sinkMBB->splice(sinkMBB->begin(), MBB,
6763 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
6764 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
6766 // Note that the structure of the jmp_buf used here is not compatible
6767 // with that used by libc, and is not designed to be. Specifically, it
6768 // stores only those 'reserved' registers that LLVM does not otherwise
6769 // understand how to spill. Also, by convention, by the time this
6770 // intrinsic is called, Clang has already stored the frame address in the
6771 // first slot of the buffer and stack address in the third. Following the
6772 // X86 target code, we'll store the jump address in the second slot. We also
6773 // need to save the TOC pointer (R2) to handle jumps between shared
6774 // libraries, and that will be stored in the fourth slot. The thread
6775 // identifier (R13) is not affected.
6778 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6779 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6780 const int64_t BPOffset = 4 * PVT.getStoreSize();
6782 // Prepare IP either in reg.
6783 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
6784 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
6785 unsigned BufReg = MI->getOperand(1).getReg();
6787 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
6788 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
6792 MIB.setMemRefs(MMOBegin, MMOEnd);
6795 // Naked functions never have a base pointer, and so we use r1. For all
6796 // other functions, this decision must be delayed until during PEI.
6798 if (MF->getFunction()->getAttributes().hasAttribute(
6799 AttributeSet::FunctionIndex, Attribute::Naked))
6800 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
6802 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
6804 MIB = BuildMI(*thisMBB, MI, DL,
6805 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
6809 MIB.setMemRefs(MMOBegin, MMOEnd);
6812 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
6813 const PPCRegisterInfo *TRI =
6814 static_cast<const PPCRegisterInfo*>(getTargetMachine().getRegisterInfo());
6815 MIB.addRegMask(TRI->getNoPreservedMask());
6817 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
6819 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
6821 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
6823 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
6824 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
6828 MIB = BuildMI(mainMBB, DL,
6829 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
6832 if (Subtarget.isPPC64()) {
6833 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
6835 .addImm(LabelOffset)
6838 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
6840 .addImm(LabelOffset)
6844 MIB.setMemRefs(MMOBegin, MMOEnd);
6846 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
6847 mainMBB->addSuccessor(sinkMBB);
6850 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
6851 TII->get(PPC::PHI), DstReg)
6852 .addReg(mainDstReg).addMBB(mainMBB)
6853 .addReg(restoreDstReg).addMBB(thisMBB);
6855 MI->eraseFromParent();
6860 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
6861 MachineBasicBlock *MBB) const {
6862 DebugLoc DL = MI->getDebugLoc();
6863 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6865 MachineFunction *MF = MBB->getParent();
6866 MachineRegisterInfo &MRI = MF->getRegInfo();
6869 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6870 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6872 MVT PVT = getPointerTy();
6873 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6874 "Invalid Pointer Size!");
6876 const TargetRegisterClass *RC =
6877 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6878 unsigned Tmp = MRI.createVirtualRegister(RC);
6879 // Since FP is only updated here but NOT referenced, it's treated as GPR.
6880 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6881 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6882 unsigned BP = (PVT == MVT::i64) ? PPC::X30 :
6883 (Subtarget.isSVR4ABI() &&
6884 MF->getTarget().getRelocationModel() == Reloc::PIC_ ?
6885 PPC::R29 : PPC::R30);
6887 MachineInstrBuilder MIB;
6889 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6890 const int64_t SPOffset = 2 * PVT.getStoreSize();
6891 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6892 const int64_t BPOffset = 4 * PVT.getStoreSize();
6894 unsigned BufReg = MI->getOperand(0).getReg();
6896 // Reload FP (the jumped-to function may not have had a
6897 // frame pointer, and if so, then its r31 will be restored
6899 if (PVT == MVT::i64) {
6900 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
6904 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
6908 MIB.setMemRefs(MMOBegin, MMOEnd);
6911 if (PVT == MVT::i64) {
6912 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
6913 .addImm(LabelOffset)
6916 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
6917 .addImm(LabelOffset)
6920 MIB.setMemRefs(MMOBegin, MMOEnd);
6923 if (PVT == MVT::i64) {
6924 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
6928 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
6932 MIB.setMemRefs(MMOBegin, MMOEnd);
6935 if (PVT == MVT::i64) {
6936 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
6940 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
6944 MIB.setMemRefs(MMOBegin, MMOEnd);
6947 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
6948 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
6952 MIB.setMemRefs(MMOBegin, MMOEnd);
6956 BuildMI(*MBB, MI, DL,
6957 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
6958 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
6960 MI->eraseFromParent();
6965 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6966 MachineBasicBlock *BB) const {
6967 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
6968 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
6969 return emitEHSjLjSetJmp(MI, BB);
6970 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
6971 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
6972 return emitEHSjLjLongJmp(MI, BB);
6975 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6977 // To "insert" these instructions we actually have to insert their
6978 // control-flow patterns.
6979 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6980 MachineFunction::iterator It = BB;
6983 MachineFunction *F = BB->getParent();
6985 if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6986 MI->getOpcode() == PPC::SELECT_CC_I8 ||
6987 MI->getOpcode() == PPC::SELECT_I4 ||
6988 MI->getOpcode() == PPC::SELECT_I8)) {
6989 SmallVector<MachineOperand, 2> Cond;
6990 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6991 MI->getOpcode() == PPC::SELECT_CC_I8)
6992 Cond.push_back(MI->getOperand(4));
6994 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
6995 Cond.push_back(MI->getOperand(1));
6997 DebugLoc dl = MI->getDebugLoc();
6998 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6999 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
7000 Cond, MI->getOperand(2).getReg(),
7001 MI->getOperand(3).getReg());
7002 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7003 MI->getOpcode() == PPC::SELECT_CC_I8 ||
7004 MI->getOpcode() == PPC::SELECT_CC_F4 ||
7005 MI->getOpcode() == PPC::SELECT_CC_F8 ||
7006 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
7007 MI->getOpcode() == PPC::SELECT_I4 ||
7008 MI->getOpcode() == PPC::SELECT_I8 ||
7009 MI->getOpcode() == PPC::SELECT_F4 ||
7010 MI->getOpcode() == PPC::SELECT_F8 ||
7011 MI->getOpcode() == PPC::SELECT_VRRC) {
7012 // The incoming instruction knows the destination vreg to set, the
7013 // condition code register to branch on, the true/false values to
7014 // select between, and a branch opcode to use.
7019 // cmpTY ccX, r1, r2
7021 // fallthrough --> copy0MBB
7022 MachineBasicBlock *thisMBB = BB;
7023 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7024 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7025 DebugLoc dl = MI->getDebugLoc();
7026 F->insert(It, copy0MBB);
7027 F->insert(It, sinkMBB);
7029 // Transfer the remainder of BB and its successor edges to sinkMBB.
7030 sinkMBB->splice(sinkMBB->begin(), BB,
7031 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7032 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7034 // Next, add the true and fallthrough blocks as its successors.
7035 BB->addSuccessor(copy0MBB);
7036 BB->addSuccessor(sinkMBB);
7038 if (MI->getOpcode() == PPC::SELECT_I4 ||
7039 MI->getOpcode() == PPC::SELECT_I8 ||
7040 MI->getOpcode() == PPC::SELECT_F4 ||
7041 MI->getOpcode() == PPC::SELECT_F8 ||
7042 MI->getOpcode() == PPC::SELECT_VRRC) {
7043 BuildMI(BB, dl, TII->get(PPC::BC))
7044 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
7046 unsigned SelectPred = MI->getOperand(4).getImm();
7047 BuildMI(BB, dl, TII->get(PPC::BCC))
7048 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
7052 // %FalseValue = ...
7053 // # fallthrough to sinkMBB
7056 // Update machine-CFG edges
7057 BB->addSuccessor(sinkMBB);
7060 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7063 BuildMI(*BB, BB->begin(), dl,
7064 TII->get(PPC::PHI), MI->getOperand(0).getReg())
7065 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
7066 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7068 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
7069 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
7070 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
7071 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
7072 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
7073 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
7074 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
7075 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
7077 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
7078 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
7079 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
7080 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
7081 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
7082 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
7083 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
7084 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
7086 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
7087 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
7088 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
7089 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
7090 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
7091 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
7092 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
7093 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
7095 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
7096 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
7097 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
7098 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
7099 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
7100 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
7101 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
7102 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
7104 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
7105 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND);
7106 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
7107 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND);
7108 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
7109 BB = EmitAtomicBinary(MI, BB, false, PPC::NAND);
7110 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
7111 BB = EmitAtomicBinary(MI, BB, true, PPC::NAND8);
7113 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
7114 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
7115 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
7116 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
7117 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
7118 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
7119 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
7120 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
7122 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
7123 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
7124 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
7125 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
7126 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
7127 BB = EmitAtomicBinary(MI, BB, false, 0);
7128 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
7129 BB = EmitAtomicBinary(MI, BB, true, 0);
7131 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
7132 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
7133 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
7135 unsigned dest = MI->getOperand(0).getReg();
7136 unsigned ptrA = MI->getOperand(1).getReg();
7137 unsigned ptrB = MI->getOperand(2).getReg();
7138 unsigned oldval = MI->getOperand(3).getReg();
7139 unsigned newval = MI->getOperand(4).getReg();
7140 DebugLoc dl = MI->getDebugLoc();
7142 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
7143 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
7144 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
7145 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7146 F->insert(It, loop1MBB);
7147 F->insert(It, loop2MBB);
7148 F->insert(It, midMBB);
7149 F->insert(It, exitMBB);
7150 exitMBB->splice(exitMBB->begin(), BB,
7151 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7152 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7156 // fallthrough --> loopMBB
7157 BB->addSuccessor(loop1MBB);
7160 // l[wd]arx dest, ptr
7161 // cmp[wd] dest, oldval
7164 // st[wd]cx. newval, ptr
7168 // st[wd]cx. dest, ptr
7171 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
7172 .addReg(ptrA).addReg(ptrB);
7173 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
7174 .addReg(oldval).addReg(dest);
7175 BuildMI(BB, dl, TII->get(PPC::BCC))
7176 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7177 BB->addSuccessor(loop2MBB);
7178 BB->addSuccessor(midMBB);
7181 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7182 .addReg(newval).addReg(ptrA).addReg(ptrB);
7183 BuildMI(BB, dl, TII->get(PPC::BCC))
7184 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7185 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7186 BB->addSuccessor(loop1MBB);
7187 BB->addSuccessor(exitMBB);
7190 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7191 .addReg(dest).addReg(ptrA).addReg(ptrB);
7192 BB->addSuccessor(exitMBB);
7197 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
7198 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
7199 // We must use 64-bit registers for addresses when targeting 64-bit,
7200 // since we're actually doing arithmetic on them. Other registers
7202 bool is64bit = Subtarget.isPPC64();
7203 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
7205 unsigned dest = MI->getOperand(0).getReg();
7206 unsigned ptrA = MI->getOperand(1).getReg();
7207 unsigned ptrB = MI->getOperand(2).getReg();
7208 unsigned oldval = MI->getOperand(3).getReg();
7209 unsigned newval = MI->getOperand(4).getReg();
7210 DebugLoc dl = MI->getDebugLoc();
7212 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
7213 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
7214 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
7215 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7216 F->insert(It, loop1MBB);
7217 F->insert(It, loop2MBB);
7218 F->insert(It, midMBB);
7219 F->insert(It, exitMBB);
7220 exitMBB->splice(exitMBB->begin(), BB,
7221 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7222 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7224 MachineRegisterInfo &RegInfo = F->getRegInfo();
7225 const TargetRegisterClass *RC =
7226 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
7227 (const TargetRegisterClass *) &PPC::GPRCRegClass;
7228 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
7229 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
7230 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
7231 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
7232 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
7233 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
7234 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
7235 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
7236 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
7237 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
7238 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
7239 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
7240 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
7242 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
7243 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
7246 // fallthrough --> loopMBB
7247 BB->addSuccessor(loop1MBB);
7249 // The 4-byte load must be aligned, while a char or short may be
7250 // anywhere in the word. Hence all this nasty bookkeeping code.
7251 // add ptr1, ptrA, ptrB [copy if ptrA==0]
7252 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
7253 // xori shift, shift1, 24 [16]
7254 // rlwinm ptr, ptr1, 0, 0, 29
7255 // slw newval2, newval, shift
7256 // slw oldval2, oldval,shift
7257 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
7258 // slw mask, mask2, shift
7259 // and newval3, newval2, mask
7260 // and oldval3, oldval2, mask
7262 // lwarx tmpDest, ptr
7263 // and tmp, tmpDest, mask
7264 // cmpw tmp, oldval3
7267 // andc tmp2, tmpDest, mask
7268 // or tmp4, tmp2, newval3
7273 // stwcx. tmpDest, ptr
7275 // srw dest, tmpDest, shift
7276 if (ptrA != ZeroReg) {
7277 Ptr1Reg = RegInfo.createVirtualRegister(RC);
7278 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
7279 .addReg(ptrA).addReg(ptrB);
7283 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
7284 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
7285 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
7286 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
7288 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
7289 .addReg(Ptr1Reg).addImm(0).addImm(61);
7291 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
7292 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
7293 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
7294 .addReg(newval).addReg(ShiftReg);
7295 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
7296 .addReg(oldval).addReg(ShiftReg);
7298 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
7300 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
7301 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
7302 .addReg(Mask3Reg).addImm(65535);
7304 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
7305 .addReg(Mask2Reg).addReg(ShiftReg);
7306 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
7307 .addReg(NewVal2Reg).addReg(MaskReg);
7308 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
7309 .addReg(OldVal2Reg).addReg(MaskReg);
7312 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
7313 .addReg(ZeroReg).addReg(PtrReg);
7314 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
7315 .addReg(TmpDestReg).addReg(MaskReg);
7316 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
7317 .addReg(TmpReg).addReg(OldVal3Reg);
7318 BuildMI(BB, dl, TII->get(PPC::BCC))
7319 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7320 BB->addSuccessor(loop2MBB);
7321 BB->addSuccessor(midMBB);
7324 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
7325 .addReg(TmpDestReg).addReg(MaskReg);
7326 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
7327 .addReg(Tmp2Reg).addReg(NewVal3Reg);
7328 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
7329 .addReg(ZeroReg).addReg(PtrReg);
7330 BuildMI(BB, dl, TII->get(PPC::BCC))
7331 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7332 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7333 BB->addSuccessor(loop1MBB);
7334 BB->addSuccessor(exitMBB);
7337 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
7338 .addReg(ZeroReg).addReg(PtrReg);
7339 BB->addSuccessor(exitMBB);
7344 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
7346 } else if (MI->getOpcode() == PPC::FADDrtz) {
7347 // This pseudo performs an FADD with rounding mode temporarily forced
7348 // to round-to-zero. We emit this via custom inserter since the FPSCR
7349 // is not modeled at the SelectionDAG level.
7350 unsigned Dest = MI->getOperand(0).getReg();
7351 unsigned Src1 = MI->getOperand(1).getReg();
7352 unsigned Src2 = MI->getOperand(2).getReg();
7353 DebugLoc dl = MI->getDebugLoc();
7355 MachineRegisterInfo &RegInfo = F->getRegInfo();
7356 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
7358 // Save FPSCR value.
7359 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
7361 // Set rounding mode to round-to-zero.
7362 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
7363 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
7365 // Perform addition.
7366 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
7368 // Restore FPSCR value.
7369 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg);
7370 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7371 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
7372 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7373 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
7374 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7375 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
7376 PPC::ANDIo8 : PPC::ANDIo;
7377 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7378 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
7380 MachineRegisterInfo &RegInfo = F->getRegInfo();
7381 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
7382 &PPC::GPRCRegClass :
7383 &PPC::G8RCRegClass);
7385 DebugLoc dl = MI->getDebugLoc();
7386 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
7387 .addReg(MI->getOperand(1).getReg()).addImm(1);
7388 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
7389 MI->getOperand(0).getReg())
7390 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
7392 llvm_unreachable("Unexpected instr type to insert");
7395 MI->eraseFromParent(); // The pseudo instruction is gone now.
7399 //===----------------------------------------------------------------------===//
7400 // Target Optimization Hooks
7401 //===----------------------------------------------------------------------===//
7403 SDValue PPCTargetLowering::DAGCombineFastRecip(SDValue Op,
7404 DAGCombinerInfo &DCI) const {
7405 if (DCI.isAfterLegalizeVectorOps())
7408 EVT VT = Op.getValueType();
7410 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
7411 (VT == MVT::f64 && Subtarget.hasFRE()) ||
7412 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7413 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7415 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
7416 // For the reciprocal, we need to find the zero of the function:
7417 // F(X) = A X - 1 [which has a zero at X = 1/A]
7419 // X_{i+1} = X_i (2 - A X_i) = X_i + X_i (1 - A X_i) [this second form
7420 // does not require additional intermediate precision]
7422 // Convergence is quadratic, so we essentially double the number of digits
7423 // correct after every iteration. The minimum architected relative
7424 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
7425 // 23 digits and double has 52 digits.
7426 int Iterations = Subtarget.hasRecipPrec() ? 1 : 3;
7427 if (VT.getScalarType() == MVT::f64)
7430 SelectionDAG &DAG = DCI.DAG;
7434 DAG.getConstantFP(1.0, VT.getScalarType());
7435 if (VT.isVector()) {
7436 assert(VT.getVectorNumElements() == 4 &&
7437 "Unknown vector type");
7438 FPOne = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
7439 FPOne, FPOne, FPOne, FPOne);
7442 SDValue Est = DAG.getNode(PPCISD::FRE, dl, VT, Op);
7443 DCI.AddToWorklist(Est.getNode());
7445 // Newton iterations: Est = Est + Est (1 - Arg * Est)
7446 for (int i = 0; i < Iterations; ++i) {
7447 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Op, Est);
7448 DCI.AddToWorklist(NewEst.getNode());
7450 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPOne, NewEst);
7451 DCI.AddToWorklist(NewEst.getNode());
7453 NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
7454 DCI.AddToWorklist(NewEst.getNode());
7456 Est = DAG.getNode(ISD::FADD, dl, VT, Est, NewEst);
7457 DCI.AddToWorklist(Est.getNode());
7466 SDValue PPCTargetLowering::DAGCombineFastRecipFSQRT(SDValue Op,
7467 DAGCombinerInfo &DCI) const {
7468 if (DCI.isAfterLegalizeVectorOps())
7471 EVT VT = Op.getValueType();
7473 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
7474 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
7475 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7476 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7478 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
7479 // For the reciprocal sqrt, we need to find the zero of the function:
7480 // F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
7482 // X_{i+1} = X_i (1.5 - A X_i^2 / 2)
7483 // As a result, we precompute A/2 prior to the iteration loop.
7485 // Convergence is quadratic, so we essentially double the number of digits
7486 // correct after every iteration. The minimum architected relative
7487 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
7488 // 23 digits and double has 52 digits.
7489 int Iterations = Subtarget.hasRecipPrec() ? 1 : 3;
7490 if (VT.getScalarType() == MVT::f64)
7493 SelectionDAG &DAG = DCI.DAG;
7496 SDValue FPThreeHalves =
7497 DAG.getConstantFP(1.5, VT.getScalarType());
7498 if (VT.isVector()) {
7499 assert(VT.getVectorNumElements() == 4 &&
7500 "Unknown vector type");
7501 FPThreeHalves = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
7502 FPThreeHalves, FPThreeHalves,
7503 FPThreeHalves, FPThreeHalves);
7506 SDValue Est = DAG.getNode(PPCISD::FRSQRTE, dl, VT, Op);
7507 DCI.AddToWorklist(Est.getNode());
7509 // We now need 0.5*Arg which we can write as (1.5*Arg - Arg) so that
7510 // this entire sequence requires only one FP constant.
7511 SDValue HalfArg = DAG.getNode(ISD::FMUL, dl, VT, FPThreeHalves, Op);
7512 DCI.AddToWorklist(HalfArg.getNode());
7514 HalfArg = DAG.getNode(ISD::FSUB, dl, VT, HalfArg, Op);
7515 DCI.AddToWorklist(HalfArg.getNode());
7517 // Newton iterations: Est = Est * (1.5 - HalfArg * Est * Est)
7518 for (int i = 0; i < Iterations; ++i) {
7519 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, Est);
7520 DCI.AddToWorklist(NewEst.getNode());
7522 NewEst = DAG.getNode(ISD::FMUL, dl, VT, HalfArg, NewEst);
7523 DCI.AddToWorklist(NewEst.getNode());
7525 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPThreeHalves, NewEst);
7526 DCI.AddToWorklist(NewEst.getNode());
7528 Est = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
7529 DCI.AddToWorklist(Est.getNode());
7538 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
7539 // not enforce equality of the chain operands.
7540 static bool isConsecutiveLS(LSBaseSDNode *LS, LSBaseSDNode *Base,
7541 unsigned Bytes, int Dist,
7542 SelectionDAG &DAG) {
7543 EVT VT = LS->getMemoryVT();
7544 if (VT.getSizeInBits() / 8 != Bytes)
7547 SDValue Loc = LS->getBasePtr();
7548 SDValue BaseLoc = Base->getBasePtr();
7549 if (Loc.getOpcode() == ISD::FrameIndex) {
7550 if (BaseLoc.getOpcode() != ISD::FrameIndex)
7552 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7553 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
7554 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
7555 int FS = MFI->getObjectSize(FI);
7556 int BFS = MFI->getObjectSize(BFI);
7557 if (FS != BFS || FS != (int)Bytes) return false;
7558 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
7562 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
7563 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
7566 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7567 const GlobalValue *GV1 = nullptr;
7568 const GlobalValue *GV2 = nullptr;
7569 int64_t Offset1 = 0;
7570 int64_t Offset2 = 0;
7571 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
7572 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
7573 if (isGA1 && isGA2 && GV1 == GV2)
7574 return Offset1 == (Offset2 + Dist*Bytes);
7578 // Return true is there is a nearyby consecutive load to the one provided
7579 // (regardless of alignment). We search up and down the chain, looking though
7580 // token factors and other loads (but nothing else). As a result, a true
7581 // results indicates that it is safe to create a new consecutive load adjacent
7582 // to the load provided.
7583 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
7584 SDValue Chain = LD->getChain();
7585 EVT VT = LD->getMemoryVT();
7587 SmallSet<SDNode *, 16> LoadRoots;
7588 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
7589 SmallSet<SDNode *, 16> Visited;
7591 // First, search up the chain, branching to follow all token-factor operands.
7592 // If we find a consecutive load, then we're done, otherwise, record all
7593 // nodes just above the top-level loads and token factors.
7594 while (!Queue.empty()) {
7595 SDNode *ChainNext = Queue.pop_back_val();
7596 if (!Visited.insert(ChainNext))
7599 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(ChainNext)) {
7600 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7603 if (!Visited.count(ChainLD->getChain().getNode()))
7604 Queue.push_back(ChainLD->getChain().getNode());
7605 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
7606 for (const SDUse &O : ChainNext->ops())
7607 if (!Visited.count(O.getNode()))
7608 Queue.push_back(O.getNode());
7610 LoadRoots.insert(ChainNext);
7613 // Second, search down the chain, starting from the top-level nodes recorded
7614 // in the first phase. These top-level nodes are the nodes just above all
7615 // loads and token factors. Starting with their uses, recursively look though
7616 // all loads (just the chain uses) and token factors to find a consecutive
7621 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
7622 IE = LoadRoots.end(); I != IE; ++I) {
7623 Queue.push_back(*I);
7625 while (!Queue.empty()) {
7626 SDNode *LoadRoot = Queue.pop_back_val();
7627 if (!Visited.insert(LoadRoot))
7630 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(LoadRoot))
7631 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7634 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
7635 UE = LoadRoot->use_end(); UI != UE; ++UI)
7636 if (((isa<LoadSDNode>(*UI) &&
7637 cast<LoadSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
7638 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
7639 Queue.push_back(*UI);
7646 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
7647 DAGCombinerInfo &DCI) const {
7648 SelectionDAG &DAG = DCI.DAG;
7651 assert(Subtarget.useCRBits() &&
7652 "Expecting to be tracking CR bits");
7653 // If we're tracking CR bits, we need to be careful that we don't have:
7654 // trunc(binary-ops(zext(x), zext(y)))
7656 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
7657 // such that we're unnecessarily moving things into GPRs when it would be
7658 // better to keep them in CR bits.
7660 // Note that trunc here can be an actual i1 trunc, or can be the effective
7661 // truncation that comes from a setcc or select_cc.
7662 if (N->getOpcode() == ISD::TRUNCATE &&
7663 N->getValueType(0) != MVT::i1)
7666 if (N->getOperand(0).getValueType() != MVT::i32 &&
7667 N->getOperand(0).getValueType() != MVT::i64)
7670 if (N->getOpcode() == ISD::SETCC ||
7671 N->getOpcode() == ISD::SELECT_CC) {
7672 // If we're looking at a comparison, then we need to make sure that the
7673 // high bits (all except for the first) don't matter the result.
7675 cast<CondCodeSDNode>(N->getOperand(
7676 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
7677 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
7679 if (ISD::isSignedIntSetCC(CC)) {
7680 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
7681 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
7683 } else if (ISD::isUnsignedIntSetCC(CC)) {
7684 if (!DAG.MaskedValueIsZero(N->getOperand(0),
7685 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
7686 !DAG.MaskedValueIsZero(N->getOperand(1),
7687 APInt::getHighBitsSet(OpBits, OpBits-1)))
7690 // This is neither a signed nor an unsigned comparison, just make sure
7691 // that the high bits are equal.
7692 APInt Op1Zero, Op1One;
7693 APInt Op2Zero, Op2One;
7694 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
7695 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
7697 // We don't really care about what is known about the first bit (if
7698 // anything), so clear it in all masks prior to comparing them.
7699 Op1Zero.clearBit(0); Op1One.clearBit(0);
7700 Op2Zero.clearBit(0); Op2One.clearBit(0);
7702 if (Op1Zero != Op2Zero || Op1One != Op2One)
7707 // We now know that the higher-order bits are irrelevant, we just need to
7708 // make sure that all of the intermediate operations are bit operations, and
7709 // all inputs are extensions.
7710 if (N->getOperand(0).getOpcode() != ISD::AND &&
7711 N->getOperand(0).getOpcode() != ISD::OR &&
7712 N->getOperand(0).getOpcode() != ISD::XOR &&
7713 N->getOperand(0).getOpcode() != ISD::SELECT &&
7714 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
7715 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
7716 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
7717 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
7718 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
7721 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
7722 N->getOperand(1).getOpcode() != ISD::AND &&
7723 N->getOperand(1).getOpcode() != ISD::OR &&
7724 N->getOperand(1).getOpcode() != ISD::XOR &&
7725 N->getOperand(1).getOpcode() != ISD::SELECT &&
7726 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
7727 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
7728 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
7729 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
7730 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
7733 SmallVector<SDValue, 4> Inputs;
7734 SmallVector<SDValue, 8> BinOps, PromOps;
7735 SmallPtrSet<SDNode *, 16> Visited;
7737 for (unsigned i = 0; i < 2; ++i) {
7738 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7739 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7740 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7741 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7742 isa<ConstantSDNode>(N->getOperand(i)))
7743 Inputs.push_back(N->getOperand(i));
7745 BinOps.push_back(N->getOperand(i));
7747 if (N->getOpcode() == ISD::TRUNCATE)
7751 // Visit all inputs, collect all binary operations (and, or, xor and
7752 // select) that are all fed by extensions.
7753 while (!BinOps.empty()) {
7754 SDValue BinOp = BinOps.back();
7757 if (!Visited.insert(BinOp.getNode()))
7760 PromOps.push_back(BinOp);
7762 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
7763 // The condition of the select is not promoted.
7764 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
7766 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
7769 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7770 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7771 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7772 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7773 isa<ConstantSDNode>(BinOp.getOperand(i))) {
7774 Inputs.push_back(BinOp.getOperand(i));
7775 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
7776 BinOp.getOperand(i).getOpcode() == ISD::OR ||
7777 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
7778 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
7779 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
7780 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
7781 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7782 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7783 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
7784 BinOps.push_back(BinOp.getOperand(i));
7786 // We have an input that is not an extension or another binary
7787 // operation; we'll abort this transformation.
7793 // Make sure that this is a self-contained cluster of operations (which
7794 // is not quite the same thing as saying that everything has only one
7796 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7797 if (isa<ConstantSDNode>(Inputs[i]))
7800 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
7801 UE = Inputs[i].getNode()->use_end();
7804 if (User != N && !Visited.count(User))
7807 // Make sure that we're not going to promote the non-output-value
7808 // operand(s) or SELECT or SELECT_CC.
7809 // FIXME: Although we could sometimes handle this, and it does occur in
7810 // practice that one of the condition inputs to the select is also one of
7811 // the outputs, we currently can't deal with this.
7812 if (User->getOpcode() == ISD::SELECT) {
7813 if (User->getOperand(0) == Inputs[i])
7815 } else if (User->getOpcode() == ISD::SELECT_CC) {
7816 if (User->getOperand(0) == Inputs[i] ||
7817 User->getOperand(1) == Inputs[i])
7823 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
7824 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
7825 UE = PromOps[i].getNode()->use_end();
7828 if (User != N && !Visited.count(User))
7831 // Make sure that we're not going to promote the non-output-value
7832 // operand(s) or SELECT or SELECT_CC.
7833 // FIXME: Although we could sometimes handle this, and it does occur in
7834 // practice that one of the condition inputs to the select is also one of
7835 // the outputs, we currently can't deal with this.
7836 if (User->getOpcode() == ISD::SELECT) {
7837 if (User->getOperand(0) == PromOps[i])
7839 } else if (User->getOpcode() == ISD::SELECT_CC) {
7840 if (User->getOperand(0) == PromOps[i] ||
7841 User->getOperand(1) == PromOps[i])
7847 // Replace all inputs with the extension operand.
7848 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7849 // Constants may have users outside the cluster of to-be-promoted nodes,
7850 // and so we need to replace those as we do the promotions.
7851 if (isa<ConstantSDNode>(Inputs[i]))
7854 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
7857 // Replace all operations (these are all the same, but have a different
7858 // (i1) return type). DAG.getNode will validate that the types of
7859 // a binary operator match, so go through the list in reverse so that
7860 // we've likely promoted both operands first. Any intermediate truncations or
7861 // extensions disappear.
7862 while (!PromOps.empty()) {
7863 SDValue PromOp = PromOps.back();
7866 if (PromOp.getOpcode() == ISD::TRUNCATE ||
7867 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
7868 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
7869 PromOp.getOpcode() == ISD::ANY_EXTEND) {
7870 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
7871 PromOp.getOperand(0).getValueType() != MVT::i1) {
7872 // The operand is not yet ready (see comment below).
7873 PromOps.insert(PromOps.begin(), PromOp);
7877 SDValue RepValue = PromOp.getOperand(0);
7878 if (isa<ConstantSDNode>(RepValue))
7879 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
7881 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
7886 switch (PromOp.getOpcode()) {
7887 default: C = 0; break;
7888 case ISD::SELECT: C = 1; break;
7889 case ISD::SELECT_CC: C = 2; break;
7892 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
7893 PromOp.getOperand(C).getValueType() != MVT::i1) ||
7894 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
7895 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
7896 // The to-be-promoted operands of this node have not yet been
7897 // promoted (this should be rare because we're going through the
7898 // list backward, but if one of the operands has several users in
7899 // this cluster of to-be-promoted nodes, it is possible).
7900 PromOps.insert(PromOps.begin(), PromOp);
7904 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
7905 PromOp.getNode()->op_end());
7907 // If there are any constant inputs, make sure they're replaced now.
7908 for (unsigned i = 0; i < 2; ++i)
7909 if (isa<ConstantSDNode>(Ops[C+i]))
7910 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
7912 DAG.ReplaceAllUsesOfValueWith(PromOp,
7913 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
7916 // Now we're left with the initial truncation itself.
7917 if (N->getOpcode() == ISD::TRUNCATE)
7918 return N->getOperand(0);
7920 // Otherwise, this is a comparison. The operands to be compared have just
7921 // changed type (to i1), but everything else is the same.
7922 return SDValue(N, 0);
7925 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
7926 DAGCombinerInfo &DCI) const {
7927 SelectionDAG &DAG = DCI.DAG;
7930 // If we're tracking CR bits, we need to be careful that we don't have:
7931 // zext(binary-ops(trunc(x), trunc(y)))
7933 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
7934 // such that we're unnecessarily moving things into CR bits that can more
7935 // efficiently stay in GPRs. Note that if we're not certain that the high
7936 // bits are set as required by the final extension, we still may need to do
7937 // some masking to get the proper behavior.
7939 // This same functionality is important on PPC64 when dealing with
7940 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
7941 // the return values of functions. Because it is so similar, it is handled
7944 if (N->getValueType(0) != MVT::i32 &&
7945 N->getValueType(0) != MVT::i64)
7948 if (!((N->getOperand(0).getValueType() == MVT::i1 &&
7949 Subtarget.useCRBits()) ||
7950 (N->getOperand(0).getValueType() == MVT::i32 &&
7951 Subtarget.isPPC64())))
7954 if (N->getOperand(0).getOpcode() != ISD::AND &&
7955 N->getOperand(0).getOpcode() != ISD::OR &&
7956 N->getOperand(0).getOpcode() != ISD::XOR &&
7957 N->getOperand(0).getOpcode() != ISD::SELECT &&
7958 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
7961 SmallVector<SDValue, 4> Inputs;
7962 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
7963 SmallPtrSet<SDNode *, 16> Visited;
7965 // Visit all inputs, collect all binary operations (and, or, xor and
7966 // select) that are all fed by truncations.
7967 while (!BinOps.empty()) {
7968 SDValue BinOp = BinOps.back();
7971 if (!Visited.insert(BinOp.getNode()))
7974 PromOps.push_back(BinOp);
7976 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
7977 // The condition of the select is not promoted.
7978 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
7980 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
7983 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
7984 isa<ConstantSDNode>(BinOp.getOperand(i))) {
7985 Inputs.push_back(BinOp.getOperand(i));
7986 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
7987 BinOp.getOperand(i).getOpcode() == ISD::OR ||
7988 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
7989 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
7990 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
7991 BinOps.push_back(BinOp.getOperand(i));
7993 // We have an input that is not a truncation or another binary
7994 // operation; we'll abort this transformation.
8000 // Make sure that this is a self-contained cluster of operations (which
8001 // is not quite the same thing as saying that everything has only one
8003 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8004 if (isa<ConstantSDNode>(Inputs[i]))
8007 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
8008 UE = Inputs[i].getNode()->use_end();
8011 if (User != N && !Visited.count(User))
8014 // Make sure that we're not going to promote the non-output-value
8015 // operand(s) or SELECT or SELECT_CC.
8016 // FIXME: Although we could sometimes handle this, and it does occur in
8017 // practice that one of the condition inputs to the select is also one of
8018 // the outputs, we currently can't deal with this.
8019 if (User->getOpcode() == ISD::SELECT) {
8020 if (User->getOperand(0) == Inputs[i])
8022 } else if (User->getOpcode() == ISD::SELECT_CC) {
8023 if (User->getOperand(0) == Inputs[i] ||
8024 User->getOperand(1) == Inputs[i])
8030 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
8031 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
8032 UE = PromOps[i].getNode()->use_end();
8035 if (User != N && !Visited.count(User))
8038 // Make sure that we're not going to promote the non-output-value
8039 // operand(s) or SELECT or SELECT_CC.
8040 // FIXME: Although we could sometimes handle this, and it does occur in
8041 // practice that one of the condition inputs to the select is also one of
8042 // the outputs, we currently can't deal with this.
8043 if (User->getOpcode() == ISD::SELECT) {
8044 if (User->getOperand(0) == PromOps[i])
8046 } else if (User->getOpcode() == ISD::SELECT_CC) {
8047 if (User->getOperand(0) == PromOps[i] ||
8048 User->getOperand(1) == PromOps[i])
8054 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
8055 bool ReallyNeedsExt = false;
8056 if (N->getOpcode() != ISD::ANY_EXTEND) {
8057 // If all of the inputs are not already sign/zero extended, then
8058 // we'll still need to do that at the end.
8059 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8060 if (isa<ConstantSDNode>(Inputs[i]))
8064 Inputs[i].getOperand(0).getValueSizeInBits();
8065 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
8067 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
8068 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
8069 APInt::getHighBitsSet(OpBits,
8070 OpBits-PromBits))) ||
8071 (N->getOpcode() == ISD::SIGN_EXTEND &&
8072 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
8073 (OpBits-(PromBits-1)))) {
8074 ReallyNeedsExt = true;
8080 // Replace all inputs, either with the truncation operand, or a
8081 // truncation or extension to the final output type.
8082 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8083 // Constant inputs need to be replaced with the to-be-promoted nodes that
8084 // use them because they might have users outside of the cluster of
8086 if (isa<ConstantSDNode>(Inputs[i]))
8089 SDValue InSrc = Inputs[i].getOperand(0);
8090 if (Inputs[i].getValueType() == N->getValueType(0))
8091 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
8092 else if (N->getOpcode() == ISD::SIGN_EXTEND)
8093 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8094 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
8095 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8096 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8097 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
8099 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8100 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
8103 // Replace all operations (these are all the same, but have a different
8104 // (promoted) return type). DAG.getNode will validate that the types of
8105 // a binary operator match, so go through the list in reverse so that
8106 // we've likely promoted both operands first.
8107 while (!PromOps.empty()) {
8108 SDValue PromOp = PromOps.back();
8112 switch (PromOp.getOpcode()) {
8113 default: C = 0; break;
8114 case ISD::SELECT: C = 1; break;
8115 case ISD::SELECT_CC: C = 2; break;
8118 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
8119 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
8120 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
8121 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
8122 // The to-be-promoted operands of this node have not yet been
8123 // promoted (this should be rare because we're going through the
8124 // list backward, but if one of the operands has several users in
8125 // this cluster of to-be-promoted nodes, it is possible).
8126 PromOps.insert(PromOps.begin(), PromOp);
8130 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
8131 PromOp.getNode()->op_end());
8133 // If this node has constant inputs, then they'll need to be promoted here.
8134 for (unsigned i = 0; i < 2; ++i) {
8135 if (!isa<ConstantSDNode>(Ops[C+i]))
8137 if (Ops[C+i].getValueType() == N->getValueType(0))
8140 if (N->getOpcode() == ISD::SIGN_EXTEND)
8141 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8142 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8143 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8145 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8148 DAG.ReplaceAllUsesOfValueWith(PromOp,
8149 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
8152 // Now we're left with the initial extension itself.
8153 if (!ReallyNeedsExt)
8154 return N->getOperand(0);
8156 // To zero extend, just mask off everything except for the first bit (in the
8158 if (N->getOpcode() == ISD::ZERO_EXTEND)
8159 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
8160 DAG.getConstant(APInt::getLowBitsSet(
8161 N->getValueSizeInBits(0), PromBits),
8162 N->getValueType(0)));
8164 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
8165 "Invalid extension type");
8166 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0));
8168 DAG.getConstant(N->getValueSizeInBits(0)-PromBits, ShiftAmountTy);
8169 return DAG.getNode(ISD::SRA, dl, N->getValueType(0),
8170 DAG.getNode(ISD::SHL, dl, N->getValueType(0),
8171 N->getOperand(0), ShiftCst), ShiftCst);
8174 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
8175 DAGCombinerInfo &DCI) const {
8176 const TargetMachine &TM = getTargetMachine();
8177 SelectionDAG &DAG = DCI.DAG;
8179 switch (N->getOpcode()) {
8182 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8183 if (C->isNullValue()) // 0 << V -> 0.
8184 return N->getOperand(0);
8188 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8189 if (C->isNullValue()) // 0 >>u V -> 0.
8190 return N->getOperand(0);
8194 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8195 if (C->isNullValue() || // 0 >>s V -> 0.
8196 C->isAllOnesValue()) // -1 >>s V -> -1.
8197 return N->getOperand(0);
8200 case ISD::SIGN_EXTEND:
8201 case ISD::ZERO_EXTEND:
8202 case ISD::ANY_EXTEND:
8203 return DAGCombineExtBoolTrunc(N, DCI);
8206 case ISD::SELECT_CC:
8207 return DAGCombineTruncBoolExt(N, DCI);
8209 assert(TM.Options.UnsafeFPMath &&
8210 "Reciprocal estimates require UnsafeFPMath");
8212 if (N->getOperand(1).getOpcode() == ISD::FSQRT) {
8214 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0), DCI);
8216 DCI.AddToWorklist(RV.getNode());
8217 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
8218 N->getOperand(0), RV);
8220 } else if (N->getOperand(1).getOpcode() == ISD::FP_EXTEND &&
8221 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
8223 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
8226 DCI.AddToWorklist(RV.getNode());
8227 RV = DAG.getNode(ISD::FP_EXTEND, SDLoc(N->getOperand(1)),
8228 N->getValueType(0), RV);
8229 DCI.AddToWorklist(RV.getNode());
8230 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
8231 N->getOperand(0), RV);
8233 } else if (N->getOperand(1).getOpcode() == ISD::FP_ROUND &&
8234 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
8236 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
8239 DCI.AddToWorklist(RV.getNode());
8240 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N->getOperand(1)),
8241 N->getValueType(0), RV,
8242 N->getOperand(1).getOperand(1));
8243 DCI.AddToWorklist(RV.getNode());
8244 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
8245 N->getOperand(0), RV);
8249 SDValue RV = DAGCombineFastRecip(N->getOperand(1), DCI);
8251 DCI.AddToWorklist(RV.getNode());
8252 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
8253 N->getOperand(0), RV);
8259 assert(TM.Options.UnsafeFPMath &&
8260 "Reciprocal estimates require UnsafeFPMath");
8262 // Compute this as 1/(1/sqrt(X)), which is the reciprocal of the
8264 SDValue RV = DAGCombineFastRecipFSQRT(N->getOperand(0), DCI);
8266 DCI.AddToWorklist(RV.getNode());
8267 RV = DAGCombineFastRecip(RV, DCI);
8269 // Unfortunately, RV is now NaN if the input was exactly 0. Select out
8270 // this case and force the answer to 0.
8272 EVT VT = RV.getValueType();
8274 SDValue Zero = DAG.getConstantFP(0.0, VT.getScalarType());
8275 if (VT.isVector()) {
8276 assert(VT.getVectorNumElements() == 4 && "Unknown vector type");
8277 Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Zero, Zero, Zero, Zero);
8281 DAG.getSetCC(dl, getSetCCResultType(*DAG.getContext(), VT),
8282 N->getOperand(0), Zero, ISD::SETEQ);
8283 DCI.AddToWorklist(ZeroCmp.getNode());
8284 DCI.AddToWorklist(RV.getNode());
8286 RV = DAG.getNode(VT.isVector() ? ISD::VSELECT : ISD::SELECT, dl, VT,
8294 case ISD::SINT_TO_FP:
8295 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
8296 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
8297 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
8298 // We allow the src/dst to be either f32/f64, but the intermediate
8299 // type must be i64.
8300 if (N->getOperand(0).getValueType() == MVT::i64 &&
8301 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
8302 SDValue Val = N->getOperand(0).getOperand(0);
8303 if (Val.getValueType() == MVT::f32) {
8304 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8305 DCI.AddToWorklist(Val.getNode());
8308 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
8309 DCI.AddToWorklist(Val.getNode());
8310 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
8311 DCI.AddToWorklist(Val.getNode());
8312 if (N->getValueType(0) == MVT::f32) {
8313 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
8314 DAG.getIntPtrConstant(0));
8315 DCI.AddToWorklist(Val.getNode());
8318 } else if (N->getOperand(0).getValueType() == MVT::i32) {
8319 // If the intermediate type is i32, we can avoid the load/store here
8326 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
8327 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
8328 !cast<StoreSDNode>(N)->isTruncatingStore() &&
8329 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
8330 N->getOperand(1).getValueType() == MVT::i32 &&
8331 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
8332 SDValue Val = N->getOperand(1).getOperand(0);
8333 if (Val.getValueType() == MVT::f32) {
8334 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8335 DCI.AddToWorklist(Val.getNode());
8337 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
8338 DCI.AddToWorklist(Val.getNode());
8341 N->getOperand(0), Val, N->getOperand(2),
8342 DAG.getValueType(N->getOperand(1).getValueType())
8345 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
8346 DAG.getVTList(MVT::Other), Ops,
8347 cast<StoreSDNode>(N)->getMemoryVT(),
8348 cast<StoreSDNode>(N)->getMemOperand());
8349 DCI.AddToWorklist(Val.getNode());
8353 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
8354 if (cast<StoreSDNode>(N)->isUnindexed() &&
8355 N->getOperand(1).getOpcode() == ISD::BSWAP &&
8356 N->getOperand(1).getNode()->hasOneUse() &&
8357 (N->getOperand(1).getValueType() == MVT::i32 ||
8358 N->getOperand(1).getValueType() == MVT::i16 ||
8359 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8360 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8361 N->getOperand(1).getValueType() == MVT::i64))) {
8362 SDValue BSwapOp = N->getOperand(1).getOperand(0);
8363 // Do an any-extend to 32-bits if this is a half-word input.
8364 if (BSwapOp.getValueType() == MVT::i16)
8365 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
8368 N->getOperand(0), BSwapOp, N->getOperand(2),
8369 DAG.getValueType(N->getOperand(1).getValueType())
8372 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
8373 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
8374 cast<StoreSDNode>(N)->getMemOperand());
8378 LoadSDNode *LD = cast<LoadSDNode>(N);
8379 EVT VT = LD->getValueType(0);
8380 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
8381 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
8382 if (ISD::isNON_EXTLoad(N) && VT.isVector() &&
8383 TM.getSubtarget<PPCSubtarget>().hasAltivec() &&
8384 (VT == MVT::v16i8 || VT == MVT::v8i16 ||
8385 VT == MVT::v4i32 || VT == MVT::v4f32) &&
8386 LD->getAlignment() < ABIAlignment) {
8387 // This is a type-legal unaligned Altivec load.
8388 SDValue Chain = LD->getChain();
8389 SDValue Ptr = LD->getBasePtr();
8390 bool isLittleEndian = Subtarget.isLittleEndian();
8392 // This implements the loading of unaligned vectors as described in
8393 // the venerable Apple Velocity Engine overview. Specifically:
8394 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
8395 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
8397 // The general idea is to expand a sequence of one or more unaligned
8398 // loads into an alignment-based permutation-control instruction (lvsl
8399 // or lvsr), a series of regular vector loads (which always truncate
8400 // their input address to an aligned address), and a series of
8401 // permutations. The results of these permutations are the requested
8402 // loaded values. The trick is that the last "extra" load is not taken
8403 // from the address you might suspect (sizeof(vector) bytes after the
8404 // last requested load), but rather sizeof(vector) - 1 bytes after the
8405 // last requested vector. The point of this is to avoid a page fault if
8406 // the base address happened to be aligned. This works because if the
8407 // base address is aligned, then adding less than a full vector length
8408 // will cause the last vector in the sequence to be (re)loaded.
8409 // Otherwise, the next vector will be fetched as you might suspect was
8412 // We might be able to reuse the permutation generation from
8413 // a different base address offset from this one by an aligned amount.
8414 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
8415 // optimization later.
8416 Intrinsic::ID Intr = (isLittleEndian ?
8417 Intrinsic::ppc_altivec_lvsr :
8418 Intrinsic::ppc_altivec_lvsl);
8419 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, MVT::v16i8);
8421 // Refine the alignment of the original load (a "new" load created here
8422 // which was identical to the first except for the alignment would be
8423 // merged with the existing node regardless).
8424 MachineFunction &MF = DAG.getMachineFunction();
8425 MachineMemOperand *MMO =
8426 MF.getMachineMemOperand(LD->getPointerInfo(),
8427 LD->getMemOperand()->getFlags(),
8428 LD->getMemoryVT().getStoreSize(),
8430 LD->refineAlignment(MMO);
8431 SDValue BaseLoad = SDValue(LD, 0);
8433 // Note that the value of IncOffset (which is provided to the next
8434 // load's pointer info offset value, and thus used to calculate the
8435 // alignment), and the value of IncValue (which is actually used to
8436 // increment the pointer value) are different! This is because we
8437 // require the next load to appear to be aligned, even though it
8438 // is actually offset from the base pointer by a lesser amount.
8439 int IncOffset = VT.getSizeInBits() / 8;
8440 int IncValue = IncOffset;
8442 // Walk (both up and down) the chain looking for another load at the real
8443 // (aligned) offset (the alignment of the other load does not matter in
8444 // this case). If found, then do not use the offset reduction trick, as
8445 // that will prevent the loads from being later combined (as they would
8446 // otherwise be duplicates).
8447 if (!findConsecutiveLoad(LD, DAG))
8450 SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
8451 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
8454 DAG.getLoad(VT, dl, Chain, Ptr,
8455 LD->getPointerInfo().getWithOffset(IncOffset),
8456 LD->isVolatile(), LD->isNonTemporal(),
8457 LD->isInvariant(), ABIAlignment);
8459 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
8460 BaseLoad.getValue(1), ExtraLoad.getValue(1));
8462 if (BaseLoad.getValueType() != MVT::v4i32)
8463 BaseLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, BaseLoad);
8465 if (ExtraLoad.getValueType() != MVT::v4i32)
8466 ExtraLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, ExtraLoad);
8468 // Because vperm has a big-endian bias, we must reverse the order
8469 // of the input vectors and complement the permute control vector
8470 // when generating little endian code. We have already handled the
8471 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
8472 // and ExtraLoad here.
8475 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8476 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
8478 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8479 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
8481 if (VT != MVT::v4i32)
8482 Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm);
8484 // Now we need to be really careful about how we update the users of the
8485 // original load. We cannot just call DCI.CombineTo (or
8486 // DAG.ReplaceAllUsesWith for that matter), because the load still has
8487 // uses created here (the permutation for example) that need to stay.
8488 SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
8490 SDUse &Use = UI.getUse();
8492 // Note: BaseLoad is checked here because it might not be N, but a
8494 if (User == Perm.getNode() || User == BaseLoad.getNode() ||
8495 User == TF.getNode() || Use.getResNo() > 1) {
8500 SDValue To = Use.getResNo() ? TF : Perm;
8503 SmallVector<SDValue, 8> Ops;
8504 for (const SDUse &O : User->ops()) {
8511 DAG.UpdateNodeOperands(User, Ops);
8514 return SDValue(N, 0);
8518 case ISD::INTRINSIC_WO_CHAIN: {
8519 bool isLittleEndian = Subtarget.isLittleEndian();
8520 Intrinsic::ID Intr = (isLittleEndian ?
8521 Intrinsic::ppc_altivec_lvsr :
8522 Intrinsic::ppc_altivec_lvsl);
8523 if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() == Intr &&
8524 N->getOperand(1)->getOpcode() == ISD::ADD) {
8525 SDValue Add = N->getOperand(1);
8527 if (DAG.MaskedValueIsZero(Add->getOperand(1),
8528 APInt::getAllOnesValue(4 /* 16 byte alignment */).zext(
8529 Add.getValueType().getScalarType().getSizeInBits()))) {
8530 SDNode *BasePtr = Add->getOperand(0).getNode();
8531 for (SDNode::use_iterator UI = BasePtr->use_begin(),
8532 UE = BasePtr->use_end(); UI != UE; ++UI) {
8533 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8534 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() ==
8536 // We've found another LVSL/LVSR, and this address is an aligned
8537 // multiple of that one. The results will be the same, so use the
8538 // one we've just found instead.
8540 return SDValue(*UI, 0);
8549 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
8550 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
8551 N->getOperand(0).hasOneUse() &&
8552 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
8553 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8554 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8555 N->getValueType(0) == MVT::i64))) {
8556 SDValue Load = N->getOperand(0);
8557 LoadSDNode *LD = cast<LoadSDNode>(Load);
8558 // Create the byte-swapping load.
8560 LD->getChain(), // Chain
8561 LD->getBasePtr(), // Ptr
8562 DAG.getValueType(N->getValueType(0)) // VT
8565 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
8566 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
8567 MVT::i64 : MVT::i32, MVT::Other),
8568 Ops, LD->getMemoryVT(), LD->getMemOperand());
8570 // If this is an i16 load, insert the truncate.
8571 SDValue ResVal = BSLoad;
8572 if (N->getValueType(0) == MVT::i16)
8573 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
8575 // First, combine the bswap away. This makes the value produced by the
8577 DCI.CombineTo(N, ResVal);
8579 // Next, combine the load away, we give it a bogus result value but a real
8580 // chain result. The result value is dead because the bswap is dead.
8581 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
8583 // Return N so it doesn't get rechecked!
8584 return SDValue(N, 0);
8588 case PPCISD::VCMP: {
8589 // If a VCMPo node already exists with exactly the same operands as this
8590 // node, use its result instead of this node (VCMPo computes both a CR6 and
8591 // a normal output).
8593 if (!N->getOperand(0).hasOneUse() &&
8594 !N->getOperand(1).hasOneUse() &&
8595 !N->getOperand(2).hasOneUse()) {
8597 // Scan all of the users of the LHS, looking for VCMPo's that match.
8598 SDNode *VCMPoNode = nullptr;
8600 SDNode *LHSN = N->getOperand(0).getNode();
8601 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
8603 if (UI->getOpcode() == PPCISD::VCMPo &&
8604 UI->getOperand(1) == N->getOperand(1) &&
8605 UI->getOperand(2) == N->getOperand(2) &&
8606 UI->getOperand(0) == N->getOperand(0)) {
8611 // If there is no VCMPo node, or if the flag value has a single use, don't
8613 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
8616 // Look at the (necessarily single) use of the flag value. If it has a
8617 // chain, this transformation is more complex. Note that multiple things
8618 // could use the value result, which we should ignore.
8619 SDNode *FlagUser = nullptr;
8620 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
8621 FlagUser == nullptr; ++UI) {
8622 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
8624 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
8625 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
8632 // If the user is a MFOCRF instruction, we know this is safe.
8633 // Otherwise we give up for right now.
8634 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
8635 return SDValue(VCMPoNode, 0);
8640 SDValue Cond = N->getOperand(1);
8641 SDValue Target = N->getOperand(2);
8643 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8644 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
8645 Intrinsic::ppc_is_decremented_ctr_nonzero) {
8647 // We now need to make the intrinsic dead (it cannot be instruction
8649 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
8650 assert(Cond.getNode()->hasOneUse() &&
8651 "Counter decrement has more than one use");
8653 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
8654 N->getOperand(0), Target);
8659 // If this is a branch on an altivec predicate comparison, lower this so
8660 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
8661 // lowering is done pre-legalize, because the legalizer lowers the predicate
8662 // compare down to code that is difficult to reassemble.
8663 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
8664 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
8666 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
8667 // value. If so, pass-through the AND to get to the intrinsic.
8668 if (LHS.getOpcode() == ISD::AND &&
8669 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8670 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
8671 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8672 isa<ConstantSDNode>(LHS.getOperand(1)) &&
8673 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
8675 LHS = LHS.getOperand(0);
8677 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8678 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
8679 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8680 isa<ConstantSDNode>(RHS)) {
8681 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
8682 "Counter decrement comparison is not EQ or NE");
8684 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8685 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
8686 (CC == ISD::SETNE && !Val);
8688 // We now need to make the intrinsic dead (it cannot be instruction
8690 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
8691 assert(LHS.getNode()->hasOneUse() &&
8692 "Counter decrement has more than one use");
8694 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
8695 N->getOperand(0), N->getOperand(4));
8701 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8702 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
8703 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
8704 assert(isDot && "Can't compare against a vector result!");
8706 // If this is a comparison against something other than 0/1, then we know
8707 // that the condition is never/always true.
8708 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8709 if (Val != 0 && Val != 1) {
8710 if (CC == ISD::SETEQ) // Cond never true, remove branch.
8711 return N->getOperand(0);
8712 // Always !=, turn it into an unconditional branch.
8713 return DAG.getNode(ISD::BR, dl, MVT::Other,
8714 N->getOperand(0), N->getOperand(4));
8717 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
8719 // Create the PPCISD altivec 'dot' comparison node.
8721 LHS.getOperand(2), // LHS of compare
8722 LHS.getOperand(3), // RHS of compare
8723 DAG.getConstant(CompareOpc, MVT::i32)
8725 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
8726 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
8728 // Unpack the result based on how the target uses it.
8729 PPC::Predicate CompOpc;
8730 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
8731 default: // Can't happen, don't crash on invalid number though.
8732 case 0: // Branch on the value of the EQ bit of CR6.
8733 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
8735 case 1: // Branch on the inverted value of the EQ bit of CR6.
8736 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
8738 case 2: // Branch on the value of the LT bit of CR6.
8739 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
8741 case 3: // Branch on the inverted value of the LT bit of CR6.
8742 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
8746 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
8747 DAG.getConstant(CompOpc, MVT::i32),
8748 DAG.getRegister(PPC::CR6, MVT::i32),
8749 N->getOperand(4), CompNode.getValue(1));
8758 //===----------------------------------------------------------------------===//
8759 // Inline Assembly Support
8760 //===----------------------------------------------------------------------===//
8762 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
8765 const SelectionDAG &DAG,
8766 unsigned Depth) const {
8767 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
8768 switch (Op.getOpcode()) {
8770 case PPCISD::LBRX: {
8771 // lhbrx is known to have the top bits cleared out.
8772 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
8773 KnownZero = 0xFFFF0000;
8776 case ISD::INTRINSIC_WO_CHAIN: {
8777 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
8779 case Intrinsic::ppc_altivec_vcmpbfp_p:
8780 case Intrinsic::ppc_altivec_vcmpeqfp_p:
8781 case Intrinsic::ppc_altivec_vcmpequb_p:
8782 case Intrinsic::ppc_altivec_vcmpequh_p:
8783 case Intrinsic::ppc_altivec_vcmpequw_p:
8784 case Intrinsic::ppc_altivec_vcmpgefp_p:
8785 case Intrinsic::ppc_altivec_vcmpgtfp_p:
8786 case Intrinsic::ppc_altivec_vcmpgtsb_p:
8787 case Intrinsic::ppc_altivec_vcmpgtsh_p:
8788 case Intrinsic::ppc_altivec_vcmpgtsw_p:
8789 case Intrinsic::ppc_altivec_vcmpgtub_p:
8790 case Intrinsic::ppc_altivec_vcmpgtuh_p:
8791 case Intrinsic::ppc_altivec_vcmpgtuw_p:
8792 KnownZero = ~1U; // All bits but the low one are known to be zero.
8800 /// getConstraintType - Given a constraint, return the type of
8801 /// constraint it is for this target.
8802 PPCTargetLowering::ConstraintType
8803 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
8804 if (Constraint.size() == 1) {
8805 switch (Constraint[0]) {
8812 return C_RegisterClass;
8814 // FIXME: While Z does indicate a memory constraint, it specifically
8815 // indicates an r+r address (used in conjunction with the 'y' modifier
8816 // in the replacement string). Currently, we're forcing the base
8817 // register to be r0 in the asm printer (which is interpreted as zero)
8818 // and forming the complete address in the second register. This is
8822 } else if (Constraint == "wc") { // individual CR bits.
8823 return C_RegisterClass;
8824 } else if (Constraint == "wa" || Constraint == "wd" ||
8825 Constraint == "wf" || Constraint == "ws") {
8826 return C_RegisterClass; // VSX registers.
8828 return TargetLowering::getConstraintType(Constraint);
8831 /// Examine constraint type and operand type and determine a weight value.
8832 /// This object must already have been set up with the operand type
8833 /// and the current alternative constraint selected.
8834 TargetLowering::ConstraintWeight
8835 PPCTargetLowering::getSingleConstraintMatchWeight(
8836 AsmOperandInfo &info, const char *constraint) const {
8837 ConstraintWeight weight = CW_Invalid;
8838 Value *CallOperandVal = info.CallOperandVal;
8839 // If we don't have a value, we can't do a match,
8840 // but allow it at the lowest weight.
8841 if (!CallOperandVal)
8843 Type *type = CallOperandVal->getType();
8845 // Look at the constraint type.
8846 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
8847 return CW_Register; // an individual CR bit.
8848 else if ((StringRef(constraint) == "wa" ||
8849 StringRef(constraint) == "wd" ||
8850 StringRef(constraint) == "wf") &&
8853 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
8856 switch (*constraint) {
8858 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
8861 if (type->isIntegerTy())
8862 weight = CW_Register;
8865 if (type->isFloatTy())
8866 weight = CW_Register;
8869 if (type->isDoubleTy())
8870 weight = CW_Register;
8873 if (type->isVectorTy())
8874 weight = CW_Register;
8877 weight = CW_Register;
8886 std::pair<unsigned, const TargetRegisterClass*>
8887 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
8889 if (Constraint.size() == 1) {
8890 // GCC RS6000 Constraint Letters
8891 switch (Constraint[0]) {
8893 if (VT == MVT::i64 && Subtarget.isPPC64())
8894 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
8895 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
8897 if (VT == MVT::i64 && Subtarget.isPPC64())
8898 return std::make_pair(0U, &PPC::G8RCRegClass);
8899 return std::make_pair(0U, &PPC::GPRCRegClass);
8901 if (VT == MVT::f32 || VT == MVT::i32)
8902 return std::make_pair(0U, &PPC::F4RCRegClass);
8903 if (VT == MVT::f64 || VT == MVT::i64)
8904 return std::make_pair(0U, &PPC::F8RCRegClass);
8907 return std::make_pair(0U, &PPC::VRRCRegClass);
8909 return std::make_pair(0U, &PPC::CRRCRegClass);
8911 } else if (Constraint == "wc") { // an individual CR bit.
8912 return std::make_pair(0U, &PPC::CRBITRCRegClass);
8913 } else if (Constraint == "wa" || Constraint == "wd" ||
8914 Constraint == "wf") {
8915 return std::make_pair(0U, &PPC::VSRCRegClass);
8916 } else if (Constraint == "ws") {
8917 return std::make_pair(0U, &PPC::VSFRCRegClass);
8920 std::pair<unsigned, const TargetRegisterClass*> R =
8921 TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
8923 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
8924 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
8925 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
8927 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
8928 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
8929 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
8930 PPC::GPRCRegClass.contains(R.first)) {
8931 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
8932 return std::make_pair(TRI->getMatchingSuperReg(R.first,
8933 PPC::sub_32, &PPC::G8RCRegClass),
8934 &PPC::G8RCRegClass);
8941 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
8942 /// vector. If it is invalid, don't add anything to Ops.
8943 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
8944 std::string &Constraint,
8945 std::vector<SDValue>&Ops,
8946 SelectionDAG &DAG) const {
8949 // Only support length 1 constraints.
8950 if (Constraint.length() > 1) return;
8952 char Letter = Constraint[0];
8963 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
8964 if (!CST) return; // Must be an immediate to match.
8965 unsigned Value = CST->getZExtValue();
8967 default: llvm_unreachable("Unknown constraint letter!");
8968 case 'I': // "I" is a signed 16-bit constant.
8969 if ((short)Value == (int)Value)
8970 Result = DAG.getTargetConstant(Value, Op.getValueType());
8972 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
8973 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
8974 if ((short)Value == 0)
8975 Result = DAG.getTargetConstant(Value, Op.getValueType());
8977 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
8978 if ((Value >> 16) == 0)
8979 Result = DAG.getTargetConstant(Value, Op.getValueType());
8981 case 'M': // "M" is a constant that is greater than 31.
8983 Result = DAG.getTargetConstant(Value, Op.getValueType());
8985 case 'N': // "N" is a positive constant that is an exact power of two.
8986 if ((int)Value > 0 && isPowerOf2_32(Value))
8987 Result = DAG.getTargetConstant(Value, Op.getValueType());
8989 case 'O': // "O" is the constant zero.
8991 Result = DAG.getTargetConstant(Value, Op.getValueType());
8993 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
8994 if ((short)-Value == (int)-Value)
8995 Result = DAG.getTargetConstant(Value, Op.getValueType());
9002 if (Result.getNode()) {
9003 Ops.push_back(Result);
9007 // Handle standard constraint letters.
9008 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
9011 // isLegalAddressingMode - Return true if the addressing mode represented
9012 // by AM is legal for this target, for a load/store of the specified type.
9013 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
9015 // FIXME: PPC does not allow r+i addressing modes for vectors!
9017 // PPC allows a sign-extended 16-bit immediate field.
9018 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
9021 // No global is ever allowed as a base.
9025 // PPC only support r+r,
9027 case 0: // "r+i" or just "i", depending on HasBaseReg.
9030 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
9032 // Otherwise we have r+r or r+i.
9035 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
9037 // Allow 2*r as r+r.
9040 // No other scales are supported.
9047 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
9048 SelectionDAG &DAG) const {
9049 MachineFunction &MF = DAG.getMachineFunction();
9050 MachineFrameInfo *MFI = MF.getFrameInfo();
9051 MFI->setReturnAddressIsTaken(true);
9053 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
9057 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9059 // Make sure the function does not optimize away the store of the RA to
9061 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
9062 FuncInfo->setLRStoreRequired();
9063 bool isPPC64 = Subtarget.isPPC64();
9064 bool isDarwinABI = Subtarget.isDarwinABI();
9067 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9070 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
9071 isPPC64? MVT::i64 : MVT::i32);
9072 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9073 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9075 MachinePointerInfo(), false, false, false, 0);
9078 // Just load the return address off the stack.
9079 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
9080 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9081 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9084 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
9085 SelectionDAG &DAG) const {
9087 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9089 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
9090 bool isPPC64 = PtrVT == MVT::i64;
9092 MachineFunction &MF = DAG.getMachineFunction();
9093 MachineFrameInfo *MFI = MF.getFrameInfo();
9094 MFI->setFrameAddressIsTaken(true);
9096 // Naked functions never have a frame pointer, and so we use r1. For all
9097 // other functions, this decision must be delayed until during PEI.
9099 if (MF.getFunction()->getAttributes().hasAttribute(
9100 AttributeSet::FunctionIndex, Attribute::Naked))
9101 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
9103 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
9105 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
9108 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
9109 FrameAddr, MachinePointerInfo(), false, false,
9114 // FIXME? Maybe this could be a TableGen attribute on some registers and
9115 // this table could be generated automatically from RegInfo.
9116 unsigned PPCTargetLowering::getRegisterByName(const char* RegName,
9118 bool isPPC64 = Subtarget.isPPC64();
9119 bool isDarwinABI = Subtarget.isDarwinABI();
9121 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
9122 (!isPPC64 && VT != MVT::i32))
9123 report_fatal_error("Invalid register global variable type");
9125 bool is64Bit = isPPC64 && VT == MVT::i64;
9126 unsigned Reg = StringSwitch<unsigned>(RegName)
9127 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
9128 .Case("r2", isDarwinABI ? 0 : (is64Bit ? PPC::X2 : PPC::R2))
9129 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
9130 (is64Bit ? PPC::X13 : PPC::R13))
9135 report_fatal_error("Invalid register name global variable");
9139 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
9140 // The PowerPC target isn't yet aware of offsets.
9144 /// getOptimalMemOpType - Returns the target specific optimal type for load
9145 /// and store operations as a result of memset, memcpy, and memmove
9146 /// lowering. If DstAlign is zero that means it's safe to destination
9147 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
9148 /// means there isn't a need to check it against alignment requirement,
9149 /// probably because the source does not need to be loaded. If 'IsMemset' is
9150 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
9151 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
9152 /// source is constant so it does not need to be loaded.
9153 /// It returns EVT::Other if the type should be determined using generic
9154 /// target-independent logic.
9155 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
9156 unsigned DstAlign, unsigned SrcAlign,
9157 bool IsMemset, bool ZeroMemset,
9159 MachineFunction &MF) const {
9160 if (Subtarget.isPPC64()) {
9167 /// \brief Returns true if it is beneficial to convert a load of a constant
9168 /// to just the constant itself.
9169 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
9171 assert(Ty->isIntegerTy());
9173 unsigned BitSize = Ty->getPrimitiveSizeInBits();
9174 if (BitSize == 0 || BitSize > 64)
9179 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
9180 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
9182 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
9183 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
9184 return NumBits1 == 64 && NumBits2 == 32;
9187 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
9188 if (!VT1.isInteger() || !VT2.isInteger())
9190 unsigned NumBits1 = VT1.getSizeInBits();
9191 unsigned NumBits2 = VT2.getSizeInBits();
9192 return NumBits1 == 64 && NumBits2 == 32;
9195 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
9196 return isInt<16>(Imm) || isUInt<16>(Imm);
9199 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
9200 return isInt<16>(Imm) || isUInt<16>(Imm);
9203 bool PPCTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
9206 if (DisablePPCUnaligned)
9209 // PowerPC supports unaligned memory access for simple non-vector types.
9210 // Although accessing unaligned addresses is not as efficient as accessing
9211 // aligned addresses, it is generally more efficient than manual expansion,
9212 // and generally only traps for software emulation when crossing page
9218 if (VT.getSimpleVT().isVector()) {
9219 if (Subtarget.hasVSX()) {
9220 if (VT != MVT::v2f64 && VT != MVT::v2i64)
9227 if (VT == MVT::ppcf128)
9236 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
9237 VT = VT.getScalarType();
9242 switch (VT.getSimpleVT().SimpleTy) {
9254 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
9255 EVT VT , unsigned DefinedValues) const {
9256 if (VT == MVT::v2i64)
9259 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
9262 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
9263 if (DisableILPPref || Subtarget.enableMachineScheduler())
9264 return TargetLowering::getSchedulingPreference(N);
9269 // Create a fast isel object.
9271 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
9272 const TargetLibraryInfo *LibInfo) const {
9273 return PPC::createFastISel(FuncInfo, LibInfo);