1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPerfectShuffle.h"
18 #include "PPCTargetMachine.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
27 #include "llvm/IR/CallingConv.h"
28 #include "llvm/IR/Constants.h"
29 #include "llvm/IR/DerivedTypes.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/IR/Intrinsics.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetOptions.h"
39 static bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
40 CCValAssign::LocInfo &LocInfo,
41 ISD::ArgFlagsTy &ArgFlags,
43 static bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
45 CCValAssign::LocInfo &LocInfo,
46 ISD::ArgFlagsTy &ArgFlags,
48 static bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
50 CCValAssign::LocInfo &LocInfo,
51 ISD::ArgFlagsTy &ArgFlags,
54 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
55 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
57 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
58 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
60 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
61 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
63 static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) {
64 if (TM.getSubtargetImpl()->isDarwin())
65 return new TargetLoweringObjectFileMachO();
67 return new TargetLoweringObjectFileELF();
70 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
71 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) {
72 const PPCSubtarget *Subtarget = &TM.getSubtarget<PPCSubtarget>();
73 PPCRegInfo = TM.getRegisterInfo();
77 // Use _setjmp/_longjmp instead of setjmp/longjmp.
78 setUseUnderscoreSetJmp(true);
79 setUseUnderscoreLongJmp(true);
81 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
82 // arguments are at least 4/8 bytes aligned.
83 bool isPPC64 = Subtarget->isPPC64();
84 setMinStackArgumentAlignment(isPPC64 ? 8:4);
86 // Set up the register classes.
87 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
88 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
89 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
91 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
92 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
93 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
95 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
97 // PowerPC has pre-inc load and store's.
98 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
99 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
100 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
101 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
102 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
103 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
104 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
105 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
106 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
107 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
109 // This is used in the ppcf128->int sequence. Note it has different semantics
110 // from FP_ROUND: that rounds to nearest, this rounds to zero.
111 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
113 // We do not currently implement these libm ops for PowerPC.
114 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
115 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
116 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
117 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
118 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
120 // PowerPC has no SREM/UREM instructions
121 setOperationAction(ISD::SREM, MVT::i32, Expand);
122 setOperationAction(ISD::UREM, MVT::i32, Expand);
123 setOperationAction(ISD::SREM, MVT::i64, Expand);
124 setOperationAction(ISD::UREM, MVT::i64, Expand);
126 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
127 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
128 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
129 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
130 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
131 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
132 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
133 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
134 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
136 // We don't support sin/cos/sqrt/fmod/pow
137 setOperationAction(ISD::FSIN , MVT::f64, Expand);
138 setOperationAction(ISD::FCOS , MVT::f64, Expand);
139 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
140 setOperationAction(ISD::FREM , MVT::f64, Expand);
141 setOperationAction(ISD::FPOW , MVT::f64, Expand);
142 setOperationAction(ISD::FMA , MVT::f64, Legal);
143 setOperationAction(ISD::FSIN , MVT::f32, Expand);
144 setOperationAction(ISD::FCOS , MVT::f32, Expand);
145 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
146 setOperationAction(ISD::FREM , MVT::f32, Expand);
147 setOperationAction(ISD::FPOW , MVT::f32, Expand);
148 setOperationAction(ISD::FMA , MVT::f32, Legal);
150 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
152 // If we're enabling GP optimizations, use hardware square root
153 if (!Subtarget->hasFSQRT()) {
154 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
155 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
158 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
159 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
161 if (Subtarget->hasFPRND()) {
162 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
163 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
164 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
166 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
167 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
168 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
170 // frin does not implement "ties to even." Thus, this is safe only in
172 if (TM.Options.UnsafeFPMath) {
173 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
174 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
176 // These need to set FE_INEXACT, and use a custom inserter.
177 setOperationAction(ISD::FRINT, MVT::f64, Legal);
178 setOperationAction(ISD::FRINT, MVT::f32, Legal);
182 // PowerPC does not have BSWAP, CTPOP or CTTZ
183 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
184 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
185 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
186 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
187 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
188 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
189 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
190 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
192 if (Subtarget->hasPOPCNTD()) {
193 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
194 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
196 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
197 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
200 // PowerPC does not have ROTR
201 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
202 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
204 // PowerPC does not have Select
205 setOperationAction(ISD::SELECT, MVT::i32, Expand);
206 setOperationAction(ISD::SELECT, MVT::i64, Expand);
207 setOperationAction(ISD::SELECT, MVT::f32, Expand);
208 setOperationAction(ISD::SELECT, MVT::f64, Expand);
210 // PowerPC wants to turn select_cc of FP into fsel when possible.
211 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
212 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
214 // PowerPC wants to optimize integer setcc a bit
215 setOperationAction(ISD::SETCC, MVT::i32, Custom);
217 // PowerPC does not have BRCOND which requires SetCC
218 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
220 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
222 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
223 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
225 // PowerPC does not have [U|S]INT_TO_FP
226 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
227 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
229 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
230 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
231 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
232 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
234 // We cannot sextinreg(i1). Expand to shifts.
235 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
237 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
238 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
239 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
240 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
242 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
243 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
244 // support continuation, user-level threading, and etc.. As a result, no
245 // other SjLj exception interfaces are implemented and please don't build
246 // your own exception handling based on them.
247 // LLVM/Clang supports zero-cost DWARF exception handling.
248 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
249 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
251 // We want to legalize GlobalAddress and ConstantPool nodes into the
252 // appropriate instructions to materialize the address.
253 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
254 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
255 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
256 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
257 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
258 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
259 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
260 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
261 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
262 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
265 setOperationAction(ISD::TRAP, MVT::Other, Legal);
267 // TRAMPOLINE is custom lowered.
268 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
269 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
271 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
272 setOperationAction(ISD::VASTART , MVT::Other, Custom);
274 if (Subtarget->isSVR4ABI()) {
276 // VAARG always uses double-word chunks, so promote anything smaller.
277 setOperationAction(ISD::VAARG, MVT::i1, Promote);
278 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
279 setOperationAction(ISD::VAARG, MVT::i8, Promote);
280 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
281 setOperationAction(ISD::VAARG, MVT::i16, Promote);
282 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
283 setOperationAction(ISD::VAARG, MVT::i32, Promote);
284 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
285 setOperationAction(ISD::VAARG, MVT::Other, Expand);
287 // VAARG is custom lowered with the 32-bit SVR4 ABI.
288 setOperationAction(ISD::VAARG, MVT::Other, Custom);
289 setOperationAction(ISD::VAARG, MVT::i64, Custom);
292 setOperationAction(ISD::VAARG, MVT::Other, Expand);
294 // Use the default implementation.
295 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
296 setOperationAction(ISD::VAEND , MVT::Other, Expand);
297 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
298 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
299 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
300 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
302 // We want to custom lower some of our intrinsics.
303 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
305 // Comparisons that require checking two conditions.
306 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
307 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
308 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
309 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
310 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
311 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
312 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
313 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
314 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
315 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
316 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
317 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
319 if (Subtarget->has64BitSupport()) {
320 // They also have instructions for converting between i64 and fp.
321 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
322 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
323 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
324 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
325 // This is just the low 32 bits of a (signed) fp->i64 conversion.
326 // We cannot do this with Promote because i64 is not a legal type.
327 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
329 if (PPCSubTarget.hasLFIWAX() || Subtarget->isPPC64())
330 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
332 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
333 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
336 // With the instructions enabled under FPCVT, we can do everything.
337 if (PPCSubTarget.hasFPCVT()) {
338 if (Subtarget->has64BitSupport()) {
339 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
340 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
341 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
342 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
345 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
346 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
347 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
348 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
351 if (Subtarget->use64BitRegs()) {
352 // 64-bit PowerPC implementations can support i64 types directly
353 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
354 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
355 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
356 // 64-bit PowerPC wants to expand i128 shifts itself.
357 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
358 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
359 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
361 // 32-bit PowerPC wants to expand i64 shifts itself.
362 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
363 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
364 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
367 if (Subtarget->hasAltivec()) {
368 // First set operation action for all vector types to expand. Then we
369 // will selectively turn on ones that can be effectively codegen'd.
370 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
371 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
372 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
374 // add/sub are legal for all supported vector VT's.
375 setOperationAction(ISD::ADD , VT, Legal);
376 setOperationAction(ISD::SUB , VT, Legal);
378 // We promote all shuffles to v16i8.
379 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
380 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
382 // We promote all non-typed operations to v4i32.
383 setOperationAction(ISD::AND , VT, Promote);
384 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
385 setOperationAction(ISD::OR , VT, Promote);
386 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
387 setOperationAction(ISD::XOR , VT, Promote);
388 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
389 setOperationAction(ISD::LOAD , VT, Promote);
390 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
391 setOperationAction(ISD::SELECT, VT, Promote);
392 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
393 setOperationAction(ISD::STORE, VT, Promote);
394 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
396 // No other operations are legal.
397 setOperationAction(ISD::MUL , VT, Expand);
398 setOperationAction(ISD::SDIV, VT, Expand);
399 setOperationAction(ISD::SREM, VT, Expand);
400 setOperationAction(ISD::UDIV, VT, Expand);
401 setOperationAction(ISD::UREM, VT, Expand);
402 setOperationAction(ISD::FDIV, VT, Expand);
403 setOperationAction(ISD::FNEG, VT, Expand);
404 setOperationAction(ISD::FSQRT, VT, Expand);
405 setOperationAction(ISD::FLOG, VT, Expand);
406 setOperationAction(ISD::FLOG10, VT, Expand);
407 setOperationAction(ISD::FLOG2, VT, Expand);
408 setOperationAction(ISD::FEXP, VT, Expand);
409 setOperationAction(ISD::FEXP2, VT, Expand);
410 setOperationAction(ISD::FSIN, VT, Expand);
411 setOperationAction(ISD::FCOS, VT, Expand);
412 setOperationAction(ISD::FABS, VT, Expand);
413 setOperationAction(ISD::FPOWI, VT, Expand);
414 setOperationAction(ISD::FFLOOR, VT, Expand);
415 setOperationAction(ISD::FCEIL, VT, Expand);
416 setOperationAction(ISD::FTRUNC, VT, Expand);
417 setOperationAction(ISD::FRINT, VT, Expand);
418 setOperationAction(ISD::FNEARBYINT, VT, Expand);
419 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
420 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
421 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
422 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
423 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
424 setOperationAction(ISD::UDIVREM, VT, Expand);
425 setOperationAction(ISD::SDIVREM, VT, Expand);
426 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
427 setOperationAction(ISD::FPOW, VT, Expand);
428 setOperationAction(ISD::CTPOP, VT, Expand);
429 setOperationAction(ISD::CTLZ, VT, Expand);
430 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
431 setOperationAction(ISD::CTTZ, VT, Expand);
432 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
433 setOperationAction(ISD::VSELECT, VT, Expand);
434 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
436 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
437 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
438 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
439 setTruncStoreAction(VT, InnerVT, Expand);
441 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
442 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
443 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
446 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
447 // with merges, splats, etc.
448 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
450 setOperationAction(ISD::AND , MVT::v4i32, Legal);
451 setOperationAction(ISD::OR , MVT::v4i32, Legal);
452 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
453 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
454 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
455 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
456 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
457 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
458 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
459 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
460 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
461 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
462 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
463 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
465 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
466 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
467 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
468 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
470 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
471 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
472 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
473 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
474 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
476 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
477 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
479 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
480 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
481 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
482 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
484 // Altivec does not contain unordered floating-point compare instructions
485 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
486 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
487 setCondCodeAction(ISD::SETUGT, MVT::v4f32, Expand);
488 setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand);
489 setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand);
490 setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand);
493 if (Subtarget->has64BitSupport()) {
494 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
495 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
498 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
499 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
500 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
501 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
503 setBooleanContents(ZeroOrOneBooleanContent);
504 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
507 setStackPointerRegisterToSaveRestore(PPC::X1);
508 setExceptionPointerRegister(PPC::X3);
509 setExceptionSelectorRegister(PPC::X4);
511 setStackPointerRegisterToSaveRestore(PPC::R1);
512 setExceptionPointerRegister(PPC::R3);
513 setExceptionSelectorRegister(PPC::R4);
516 // We have target-specific dag combine patterns for the following nodes:
517 setTargetDAGCombine(ISD::SINT_TO_FP);
518 setTargetDAGCombine(ISD::STORE);
519 setTargetDAGCombine(ISD::BR_CC);
520 setTargetDAGCombine(ISD::BSWAP);
522 // Darwin long double math library functions have $LDBL128 appended.
523 if (Subtarget->isDarwin()) {
524 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
525 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
526 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
527 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
528 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
529 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
530 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
531 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
532 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
533 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
536 setMinFunctionAlignment(2);
537 if (PPCSubTarget.isDarwin())
538 setPrefFunctionAlignment(4);
540 if (isPPC64 && Subtarget->isJITCodeModel())
541 // Temporary workaround for the inability of PPC64 JIT to handle jump
543 setSupportJumpTables(false);
545 setInsertFencesForAtomic(true);
547 setSchedulingPreference(Sched::Hybrid);
549 computeRegisterProperties();
551 // The Freescale cores does better with aggressive inlining of memcpy and
552 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores).
553 if (Subtarget->getDarwinDirective() == PPC::DIR_E500mc ||
554 Subtarget->getDarwinDirective() == PPC::DIR_E5500) {
555 MaxStoresPerMemset = 32;
556 MaxStoresPerMemsetOptSize = 16;
557 MaxStoresPerMemcpy = 32;
558 MaxStoresPerMemcpyOptSize = 8;
559 MaxStoresPerMemmove = 32;
560 MaxStoresPerMemmoveOptSize = 8;
562 setPrefFunctionAlignment(4);
566 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
567 /// function arguments in the caller parameter area.
568 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
569 const TargetMachine &TM = getTargetMachine();
570 // Darwin passes everything on 4 byte boundary.
571 if (TM.getSubtarget<PPCSubtarget>().isDarwin())
574 // 16byte and wider vectors are passed on 16byte boundary.
575 if (VectorType *VTy = dyn_cast<VectorType>(Ty))
576 if (VTy->getBitWidth() >= 128)
579 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
580 if (PPCSubTarget.isPPC64())
586 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
589 case PPCISD::FSEL: return "PPCISD::FSEL";
590 case PPCISD::FCFID: return "PPCISD::FCFID";
591 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
592 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
593 case PPCISD::STFIWX: return "PPCISD::STFIWX";
594 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
595 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
596 case PPCISD::VPERM: return "PPCISD::VPERM";
597 case PPCISD::Hi: return "PPCISD::Hi";
598 case PPCISD::Lo: return "PPCISD::Lo";
599 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
600 case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE";
601 case PPCISD::LOAD: return "PPCISD::LOAD";
602 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
603 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
604 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
605 case PPCISD::SRL: return "PPCISD::SRL";
606 case PPCISD::SRA: return "PPCISD::SRA";
607 case PPCISD::SHL: return "PPCISD::SHL";
608 case PPCISD::CALL: return "PPCISD::CALL";
609 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
610 case PPCISD::MTCTR: return "PPCISD::MTCTR";
611 case PPCISD::BCTRL: return "PPCISD::BCTRL";
612 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
613 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
614 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
615 case PPCISD::MFCR: return "PPCISD::MFCR";
616 case PPCISD::VCMP: return "PPCISD::VCMP";
617 case PPCISD::VCMPo: return "PPCISD::VCMPo";
618 case PPCISD::LBRX: return "PPCISD::LBRX";
619 case PPCISD::STBRX: return "PPCISD::STBRX";
620 case PPCISD::LARX: return "PPCISD::LARX";
621 case PPCISD::STCX: return "PPCISD::STCX";
622 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
623 case PPCISD::MFFS: return "PPCISD::MFFS";
624 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
625 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
626 case PPCISD::CR6SET: return "PPCISD::CR6SET";
627 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
628 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
629 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
630 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
631 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
632 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
633 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
634 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
635 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
636 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
637 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
638 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
639 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
640 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
641 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
642 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
646 EVT PPCTargetLowering::getSetCCResultType(EVT VT) const {
649 return VT.changeVectorElementTypeToInteger();
652 //===----------------------------------------------------------------------===//
653 // Node matching predicates, for use by the tblgen matching code.
654 //===----------------------------------------------------------------------===//
656 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
657 static bool isFloatingPointZero(SDValue Op) {
658 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
659 return CFP->getValueAPF().isZero();
660 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
661 // Maybe this has already been legalized into the constant pool?
662 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
663 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
664 return CFP->getValueAPF().isZero();
669 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
670 /// true if Op is undef or if it matches the specified value.
671 static bool isConstantOrUndef(int Op, int Val) {
672 return Op < 0 || Op == Val;
675 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
676 /// VPKUHUM instruction.
677 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
679 for (unsigned i = 0; i != 16; ++i)
680 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
683 for (unsigned i = 0; i != 8; ++i)
684 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) ||
685 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1))
691 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
692 /// VPKUWUM instruction.
693 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
695 for (unsigned i = 0; i != 16; i += 2)
696 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
697 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
700 for (unsigned i = 0; i != 8; i += 2)
701 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
702 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) ||
703 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) ||
704 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3))
710 /// isVMerge - Common function, used to match vmrg* shuffles.
712 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
713 unsigned LHSStart, unsigned RHSStart) {
714 assert(N->getValueType(0) == MVT::v16i8 &&
715 "PPC only supports shuffles by bytes!");
716 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
717 "Unsupported merge size!");
719 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
720 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
721 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
722 LHSStart+j+i*UnitSize) ||
723 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
724 RHSStart+j+i*UnitSize))
730 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
731 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
732 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
735 return isVMerge(N, UnitSize, 8, 24);
736 return isVMerge(N, UnitSize, 8, 8);
739 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
740 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
741 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
744 return isVMerge(N, UnitSize, 0, 16);
745 return isVMerge(N, UnitSize, 0, 0);
749 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
750 /// amount, otherwise return -1.
751 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
752 assert(N->getValueType(0) == MVT::v16i8 &&
753 "PPC only supports shuffles by bytes!");
755 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
757 // Find the first non-undef value in the shuffle mask.
759 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
762 if (i == 16) return -1; // all undef.
764 // Otherwise, check to see if the rest of the elements are consecutively
765 // numbered from this value.
766 unsigned ShiftAmt = SVOp->getMaskElt(i);
767 if (ShiftAmt < i) return -1;
771 // Check the rest of the elements to see if they are consecutive.
772 for (++i; i != 16; ++i)
773 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
776 // Check the rest of the elements to see if they are consecutive.
777 for (++i; i != 16; ++i)
778 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
784 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
785 /// specifies a splat of a single element that is suitable for input to
786 /// VSPLTB/VSPLTH/VSPLTW.
787 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
788 assert(N->getValueType(0) == MVT::v16i8 &&
789 (EltSize == 1 || EltSize == 2 || EltSize == 4));
791 // This is a splat operation if each element of the permute is the same, and
792 // if the value doesn't reference the second vector.
793 unsigned ElementBase = N->getMaskElt(0);
795 // FIXME: Handle UNDEF elements too!
796 if (ElementBase >= 16)
799 // Check that the indices are consecutive, in the case of a multi-byte element
800 // splatted with a v16i8 mask.
801 for (unsigned i = 1; i != EltSize; ++i)
802 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
805 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
806 if (N->getMaskElt(i) < 0) continue;
807 for (unsigned j = 0; j != EltSize; ++j)
808 if (N->getMaskElt(i+j) != N->getMaskElt(j))
814 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
816 bool PPC::isAllNegativeZeroVector(SDNode *N) {
817 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
819 APInt APVal, APUndef;
823 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
824 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
825 return CFP->getValueAPF().isNegZero();
830 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
831 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
832 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
833 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
834 assert(isSplatShuffleMask(SVOp, EltSize));
835 return SVOp->getMaskElt(0) / EltSize;
838 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
839 /// by using a vspltis[bhw] instruction of the specified element size, return
840 /// the constant being splatted. The ByteSize field indicates the number of
841 /// bytes of each element [124] -> [bhw].
842 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
845 // If ByteSize of the splat is bigger than the element size of the
846 // build_vector, then we have a case where we are checking for a splat where
847 // multiple elements of the buildvector are folded together into a single
848 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
849 unsigned EltSize = 16/N->getNumOperands();
850 if (EltSize < ByteSize) {
851 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
852 SDValue UniquedVals[4];
853 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
855 // See if all of the elements in the buildvector agree across.
856 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
857 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
858 // If the element isn't a constant, bail fully out.
859 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
862 if (UniquedVals[i&(Multiple-1)].getNode() == 0)
863 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
864 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
865 return SDValue(); // no match.
868 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
869 // either constant or undef values that are identical for each chunk. See
870 // if these chunks can form into a larger vspltis*.
872 // Check to see if all of the leading entries are either 0 or -1. If
873 // neither, then this won't fit into the immediate field.
874 bool LeadingZero = true;
875 bool LeadingOnes = true;
876 for (unsigned i = 0; i != Multiple-1; ++i) {
877 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs.
879 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
880 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
882 // Finally, check the least significant entry.
884 if (UniquedVals[Multiple-1].getNode() == 0)
885 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
886 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
888 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
891 if (UniquedVals[Multiple-1].getNode() == 0)
892 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
893 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
894 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
895 return DAG.getTargetConstant(Val, MVT::i32);
901 // Check to see if this buildvec has a single non-undef value in its elements.
902 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
903 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
904 if (OpVal.getNode() == 0)
905 OpVal = N->getOperand(i);
906 else if (OpVal != N->getOperand(i))
910 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def.
912 unsigned ValSizeInBytes = EltSize;
914 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
915 Value = CN->getZExtValue();
916 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
917 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
918 Value = FloatToBits(CN->getValueAPF().convertToFloat());
921 // If the splat value is larger than the element value, then we can never do
922 // this splat. The only case that we could fit the replicated bits into our
923 // immediate field for would be zero, and we prefer to use vxor for it.
924 if (ValSizeInBytes < ByteSize) return SDValue();
926 // If the element value is larger than the splat value, cut it in half and
927 // check to see if the two halves are equal. Continue doing this until we
928 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
929 while (ValSizeInBytes > ByteSize) {
930 ValSizeInBytes >>= 1;
932 // If the top half equals the bottom half, we're still ok.
933 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
934 (Value & ((1 << (8*ValSizeInBytes))-1)))
938 // Properly sign extend the value.
939 int MaskVal = SignExtend32(Value, ByteSize * 8);
941 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
942 if (MaskVal == 0) return SDValue();
944 // Finally, if this value fits in a 5 bit sext field, return it
945 if (SignExtend32<5>(MaskVal) == MaskVal)
946 return DAG.getTargetConstant(MaskVal, MVT::i32);
950 //===----------------------------------------------------------------------===//
951 // Addressing Mode Selection
952 //===----------------------------------------------------------------------===//
954 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
955 /// or 64-bit immediate, and if the value can be accurately represented as a
956 /// sign extension from a 16-bit value. If so, this returns true and the
958 static bool isIntS16Immediate(SDNode *N, short &Imm) {
959 if (N->getOpcode() != ISD::Constant)
962 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
963 if (N->getValueType(0) == MVT::i32)
964 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
966 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
968 static bool isIntS16Immediate(SDValue Op, short &Imm) {
969 return isIntS16Immediate(Op.getNode(), Imm);
973 /// SelectAddressRegReg - Given the specified addressed, check to see if it
974 /// can be represented as an indexed [r+r] operation. Returns false if it
975 /// can be more efficiently represented with [r+imm].
976 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
978 SelectionDAG &DAG) const {
980 if (N.getOpcode() == ISD::ADD) {
981 if (isIntS16Immediate(N.getOperand(1), imm))
983 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
986 Base = N.getOperand(0);
987 Index = N.getOperand(1);
989 } else if (N.getOpcode() == ISD::OR) {
990 if (isIntS16Immediate(N.getOperand(1), imm))
991 return false; // r+i can fold it if we can.
993 // If this is an or of disjoint bitfields, we can codegen this as an add
994 // (for better address arithmetic) if the LHS and RHS of the OR are provably
996 APInt LHSKnownZero, LHSKnownOne;
997 APInt RHSKnownZero, RHSKnownOne;
998 DAG.ComputeMaskedBits(N.getOperand(0),
999 LHSKnownZero, LHSKnownOne);
1001 if (LHSKnownZero.getBoolValue()) {
1002 DAG.ComputeMaskedBits(N.getOperand(1),
1003 RHSKnownZero, RHSKnownOne);
1004 // If all of the bits are known zero on the LHS or RHS, the add won't
1006 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1007 Base = N.getOperand(0);
1008 Index = N.getOperand(1);
1017 /// Returns true if the address N can be represented by a base register plus
1018 /// a signed 16-bit displacement [r+imm], and if it is not better
1019 /// represented as reg+reg.
1020 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1022 SelectionDAG &DAG) const {
1023 // FIXME dl should come from parent load or store, not from address
1024 DebugLoc dl = N.getDebugLoc();
1025 // If this can be more profitably realized as r+r, fail.
1026 if (SelectAddressRegReg(N, Disp, Base, DAG))
1029 if (N.getOpcode() == ISD::ADD) {
1031 if (isIntS16Immediate(N.getOperand(1), imm)) {
1032 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
1033 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1034 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1036 Base = N.getOperand(0);
1038 return true; // [r+i]
1039 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1040 // Match LOAD (ADD (X, Lo(G))).
1041 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1042 && "Cannot handle constant offsets yet!");
1043 Disp = N.getOperand(1).getOperand(0); // The global address.
1044 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1045 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1046 Disp.getOpcode() == ISD::TargetConstantPool ||
1047 Disp.getOpcode() == ISD::TargetJumpTable);
1048 Base = N.getOperand(0);
1049 return true; // [&g+r]
1051 } else if (N.getOpcode() == ISD::OR) {
1053 if (isIntS16Immediate(N.getOperand(1), imm)) {
1054 // If this is an or of disjoint bitfields, we can codegen this as an add
1055 // (for better address arithmetic) if the LHS and RHS of the OR are
1056 // provably disjoint.
1057 APInt LHSKnownZero, LHSKnownOne;
1058 DAG.ComputeMaskedBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1060 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1061 // If all of the bits are known zero on the LHS or RHS, the add won't
1063 Base = N.getOperand(0);
1064 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
1068 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1069 // Loading from a constant address.
1071 // If this address fits entirely in a 16-bit sext immediate field, codegen
1074 if (isIntS16Immediate(CN, Imm)) {
1075 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1076 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1077 CN->getValueType(0));
1081 // Handle 32-bit sext immediates with LIS + addr mode.
1082 if (CN->getValueType(0) == MVT::i32 ||
1083 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
1084 int Addr = (int)CN->getZExtValue();
1086 // Otherwise, break this down into an LIS + disp.
1087 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1089 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1090 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1091 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1096 Disp = DAG.getTargetConstant(0, getPointerTy());
1097 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
1098 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1101 return true; // [r+0]
1104 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1105 /// represented as an indexed [r+r] operation.
1106 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1108 SelectionDAG &DAG) const {
1109 // Check to see if we can easily represent this as an [r+r] address. This
1110 // will fail if it thinks that the address is more profitably represented as
1111 // reg+imm, e.g. where imm = 0.
1112 if (SelectAddressRegReg(N, Base, Index, DAG))
1115 // If the operand is an addition, always emit this as [r+r], since this is
1116 // better (for code size, and execution, as the memop does the add for free)
1117 // than emitting an explicit add.
1118 if (N.getOpcode() == ISD::ADD) {
1119 Base = N.getOperand(0);
1120 Index = N.getOperand(1);
1124 // Otherwise, do it the hard way, using R0 as the base register.
1125 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1131 /// SelectAddressRegImmShift - Returns true if the address N can be
1132 /// represented by a base register plus a signed 14-bit displacement
1133 /// [r+imm*4]. Suitable for use by STD and friends.
1134 bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp,
1136 SelectionDAG &DAG) const {
1137 // FIXME dl should come from the parent load or store, not the address
1138 DebugLoc dl = N.getDebugLoc();
1139 // If this can be more profitably realized as r+r, fail.
1140 if (SelectAddressRegReg(N, Disp, Base, DAG))
1143 if (N.getOpcode() == ISD::ADD) {
1145 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
1146 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
1147 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1148 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1150 Base = N.getOperand(0);
1152 return true; // [r+i]
1153 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1154 // Match LOAD (ADD (X, Lo(G))).
1155 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1156 && "Cannot handle constant offsets yet!");
1157 Disp = N.getOperand(1).getOperand(0); // The global address.
1158 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1159 Disp.getOpcode() == ISD::TargetConstantPool ||
1160 Disp.getOpcode() == ISD::TargetJumpTable);
1161 Base = N.getOperand(0);
1162 return true; // [&g+r]
1164 } else if (N.getOpcode() == ISD::OR) {
1166 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
1167 // If this is an or of disjoint bitfields, we can codegen this as an add
1168 // (for better address arithmetic) if the LHS and RHS of the OR are
1169 // provably disjoint.
1170 APInt LHSKnownZero, LHSKnownOne;
1171 DAG.ComputeMaskedBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1172 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1173 // If all of the bits are known zero on the LHS or RHS, the add won't
1175 Base = N.getOperand(0);
1176 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
1180 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1181 // Loading from a constant address. Verify low two bits are clear.
1182 if ((CN->getZExtValue() & 3) == 0) {
1183 // If this address fits entirely in a 14-bit sext immediate field, codegen
1186 if (isIntS16Immediate(CN, Imm)) {
1187 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
1188 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1189 CN->getValueType(0));
1193 // Fold the low-part of 32-bit absolute addresses into addr mode.
1194 if (CN->getValueType(0) == MVT::i32 ||
1195 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
1196 int Addr = (int)CN->getZExtValue();
1198 // Otherwise, break this down into an LIS + disp.
1199 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
1200 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
1201 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1202 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base),0);
1208 Disp = DAG.getTargetConstant(0, getPointerTy());
1209 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
1210 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1213 return true; // [r+0]
1217 /// getPreIndexedAddressParts - returns true by value, base pointer and
1218 /// offset pointer and addressing mode by reference if the node's address
1219 /// can be legally represented as pre-indexed load / store address.
1220 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1222 ISD::MemIndexedMode &AM,
1223 SelectionDAG &DAG) const {
1224 if (DisablePPCPreinc) return false;
1230 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1231 Ptr = LD->getBasePtr();
1232 VT = LD->getMemoryVT();
1233 Alignment = LD->getAlignment();
1234 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1235 Ptr = ST->getBasePtr();
1236 VT = ST->getMemoryVT();
1237 Alignment = ST->getAlignment();
1242 // PowerPC doesn't have preinc load/store instructions for vectors.
1246 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1248 // Common code will reject creating a pre-inc form if the base pointer
1249 // is a frame index, or if N is a store and the base pointer is either
1250 // the same as or a predecessor of the value being stored. Check for
1251 // those situations here, and try with swapped Base/Offset instead.
1254 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1257 SDValue Val = cast<StoreSDNode>(N)->getValue();
1258 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1263 std::swap(Base, Offset);
1269 // LDU/STU use reg+imm*4, others use reg+imm.
1270 if (VT != MVT::i64) {
1272 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
1275 // LDU/STU need an address with at least 4-byte alignment.
1280 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
1284 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1285 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1286 // sext i32 to i64 when addr mode is r+i.
1287 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1288 LD->getExtensionType() == ISD::SEXTLOAD &&
1289 isa<ConstantSDNode>(Offset))
1297 //===----------------------------------------------------------------------===//
1298 // LowerOperation implementation
1299 //===----------------------------------------------------------------------===//
1301 /// GetLabelAccessInfo - Return true if we should reference labels using a
1302 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1303 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1304 unsigned &LoOpFlags, const GlobalValue *GV = 0) {
1305 HiOpFlags = PPCII::MO_HA16;
1306 LoOpFlags = PPCII::MO_LO16;
1308 // Don't use the pic base if not in PIC relocation model. Or if we are on a
1309 // non-darwin platform. We don't support PIC on other platforms yet.
1310 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ &&
1311 TM.getSubtarget<PPCSubtarget>().isDarwin();
1313 HiOpFlags |= PPCII::MO_PIC_FLAG;
1314 LoOpFlags |= PPCII::MO_PIC_FLAG;
1317 // If this is a reference to a global value that requires a non-lazy-ptr, make
1318 // sure that instruction lowering adds it.
1319 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1320 HiOpFlags |= PPCII::MO_NLP_FLAG;
1321 LoOpFlags |= PPCII::MO_NLP_FLAG;
1323 if (GV->hasHiddenVisibility()) {
1324 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1325 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1332 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1333 SelectionDAG &DAG) {
1334 EVT PtrVT = HiPart.getValueType();
1335 SDValue Zero = DAG.getConstant(0, PtrVT);
1336 DebugLoc DL = HiPart.getDebugLoc();
1338 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1339 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1341 // With PIC, the first instruction is actually "GR+hi(&G)".
1343 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1344 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1346 // Generate non-pic code that has direct accesses to the constant pool.
1347 // The address of the global is just (hi(&g)+lo(&g)).
1348 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1351 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1352 SelectionDAG &DAG) const {
1353 EVT PtrVT = Op.getValueType();
1354 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1355 const Constant *C = CP->getConstVal();
1357 // 64-bit SVR4 ABI code is always position-independent.
1358 // The actual address of the GlobalValue is stored in the TOC.
1359 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1360 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1361 return DAG.getNode(PPCISD::TOC_ENTRY, CP->getDebugLoc(), MVT::i64, GA,
1362 DAG.getRegister(PPC::X2, MVT::i64));
1365 unsigned MOHiFlag, MOLoFlag;
1366 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1368 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1370 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1371 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1374 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1375 EVT PtrVT = Op.getValueType();
1376 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1378 // 64-bit SVR4 ABI code is always position-independent.
1379 // The actual address of the GlobalValue is stored in the TOC.
1380 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1381 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1382 return DAG.getNode(PPCISD::TOC_ENTRY, JT->getDebugLoc(), MVT::i64, GA,
1383 DAG.getRegister(PPC::X2, MVT::i64));
1386 unsigned MOHiFlag, MOLoFlag;
1387 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1388 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1389 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1390 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1393 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1394 SelectionDAG &DAG) const {
1395 EVT PtrVT = Op.getValueType();
1397 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1399 unsigned MOHiFlag, MOLoFlag;
1400 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1401 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1402 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1403 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1406 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1407 SelectionDAG &DAG) const {
1409 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1410 DebugLoc dl = GA->getDebugLoc();
1411 const GlobalValue *GV = GA->getGlobal();
1412 EVT PtrVT = getPointerTy();
1413 bool is64bit = PPCSubTarget.isPPC64();
1415 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1417 if (Model == TLSModel::LocalExec) {
1418 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1419 PPCII::MO_TPREL16_HA);
1420 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1421 PPCII::MO_TPREL16_LO);
1422 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1423 is64bit ? MVT::i64 : MVT::i32);
1424 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1425 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1429 llvm_unreachable("only local-exec is currently supported for ppc32");
1431 if (Model == TLSModel::InitialExec) {
1432 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1433 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1434 SDValue TPOffsetHi = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1435 PtrVT, GOTReg, TGA);
1436 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1437 PtrVT, TGA, TPOffsetHi);
1438 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGA);
1441 if (Model == TLSModel::GeneralDynamic) {
1442 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1443 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1444 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1446 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1449 // We need a chain node, and don't have one handy. The underlying
1450 // call has no side effects, so using the function entry node
1452 SDValue Chain = DAG.getEntryNode();
1453 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1454 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1455 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl,
1456 PtrVT, ParmReg, TGA);
1457 // The return value from GET_TLS_ADDR really is in X3 already, but
1458 // some hacks are needed here to tie everything together. The extra
1459 // copies dissolve during subsequent transforms.
1460 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1461 return DAG.getCopyFromReg(Chain, dl, PPC::X3, PtrVT);
1464 if (Model == TLSModel::LocalDynamic) {
1465 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1466 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1467 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1469 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1472 // We need a chain node, and don't have one handy. The underlying
1473 // call has no side effects, so using the function entry node
1475 SDValue Chain = DAG.getEntryNode();
1476 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1477 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1478 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl,
1479 PtrVT, ParmReg, TGA);
1480 // The return value from GET_TLSLD_ADDR really is in X3 already, but
1481 // some hacks are needed here to tie everything together. The extra
1482 // copies dissolve during subsequent transforms.
1483 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1484 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1485 Chain, ParmReg, TGA);
1486 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1489 llvm_unreachable("Unknown TLS model!");
1492 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1493 SelectionDAG &DAG) const {
1494 EVT PtrVT = Op.getValueType();
1495 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1496 DebugLoc DL = GSDN->getDebugLoc();
1497 const GlobalValue *GV = GSDN->getGlobal();
1499 // 64-bit SVR4 ABI code is always position-independent.
1500 // The actual address of the GlobalValue is stored in the TOC.
1501 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1502 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1503 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1504 DAG.getRegister(PPC::X2, MVT::i64));
1507 unsigned MOHiFlag, MOLoFlag;
1508 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1511 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1513 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1515 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1517 // If the global reference is actually to a non-lazy-pointer, we have to do an
1518 // extra load to get the address of the global.
1519 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1520 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1521 false, false, false, 0);
1525 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1526 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1527 DebugLoc dl = Op.getDebugLoc();
1529 // If we're comparing for equality to zero, expose the fact that this is
1530 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1531 // fold the new nodes.
1532 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1533 if (C->isNullValue() && CC == ISD::SETEQ) {
1534 EVT VT = Op.getOperand(0).getValueType();
1535 SDValue Zext = Op.getOperand(0);
1536 if (VT.bitsLT(MVT::i32)) {
1538 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1540 unsigned Log2b = Log2_32(VT.getSizeInBits());
1541 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1542 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1543 DAG.getConstant(Log2b, MVT::i32));
1544 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1546 // Leave comparisons against 0 and -1 alone for now, since they're usually
1547 // optimized. FIXME: revisit this when we can custom lower all setcc
1549 if (C->isAllOnesValue() || C->isNullValue())
1553 // If we have an integer seteq/setne, turn it into a compare against zero
1554 // by xor'ing the rhs with the lhs, which is faster than setting a
1555 // condition register, reading it back out, and masking the correct bit. The
1556 // normal approach here uses sub to do this instead of xor. Using xor exposes
1557 // the result to other bit-twiddling opportunities.
1558 EVT LHSVT = Op.getOperand(0).getValueType();
1559 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1560 EVT VT = Op.getValueType();
1561 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1563 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1568 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1569 const PPCSubtarget &Subtarget) const {
1570 SDNode *Node = Op.getNode();
1571 EVT VT = Node->getValueType(0);
1572 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1573 SDValue InChain = Node->getOperand(0);
1574 SDValue VAListPtr = Node->getOperand(1);
1575 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1576 DebugLoc dl = Node->getDebugLoc();
1578 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1581 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1582 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1584 InChain = GprIndex.getValue(1);
1586 if (VT == MVT::i64) {
1587 // Check if GprIndex is even
1588 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1589 DAG.getConstant(1, MVT::i32));
1590 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1591 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1592 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1593 DAG.getConstant(1, MVT::i32));
1594 // Align GprIndex to be even if it isn't
1595 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1599 // fpr index is 1 byte after gpr
1600 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1601 DAG.getConstant(1, MVT::i32));
1604 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1605 FprPtr, MachinePointerInfo(SV), MVT::i8,
1607 InChain = FprIndex.getValue(1);
1609 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1610 DAG.getConstant(8, MVT::i32));
1612 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1613 DAG.getConstant(4, MVT::i32));
1616 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1617 MachinePointerInfo(), false, false,
1619 InChain = OverflowArea.getValue(1);
1621 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1622 MachinePointerInfo(), false, false,
1624 InChain = RegSaveArea.getValue(1);
1626 // select overflow_area if index > 8
1627 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1628 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1630 // adjustment constant gpr_index * 4/8
1631 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1632 VT.isInteger() ? GprIndex : FprIndex,
1633 DAG.getConstant(VT.isInteger() ? 4 : 8,
1636 // OurReg = RegSaveArea + RegConstant
1637 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1640 // Floating types are 32 bytes into RegSaveArea
1641 if (VT.isFloatingPoint())
1642 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1643 DAG.getConstant(32, MVT::i32));
1645 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1646 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1647 VT.isInteger() ? GprIndex : FprIndex,
1648 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1651 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1652 VT.isInteger() ? VAListPtr : FprPtr,
1653 MachinePointerInfo(SV),
1654 MVT::i8, false, false, 0);
1656 // determine if we should load from reg_save_area or overflow_area
1657 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1659 // increase overflow_area by 4/8 if gpr/fpr > 8
1660 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1661 DAG.getConstant(VT.isInteger() ? 4 : 8,
1664 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1667 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1669 MachinePointerInfo(),
1670 MVT::i32, false, false, 0);
1672 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1673 false, false, false, 0);
1676 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
1677 SelectionDAG &DAG) const {
1678 return Op.getOperand(0);
1681 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
1682 SelectionDAG &DAG) const {
1683 SDValue Chain = Op.getOperand(0);
1684 SDValue Trmp = Op.getOperand(1); // trampoline
1685 SDValue FPtr = Op.getOperand(2); // nested function
1686 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1687 DebugLoc dl = Op.getDebugLoc();
1689 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1690 bool isPPC64 = (PtrVT == MVT::i64);
1692 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
1695 TargetLowering::ArgListTy Args;
1696 TargetLowering::ArgListEntry Entry;
1698 Entry.Ty = IntPtrTy;
1699 Entry.Node = Trmp; Args.push_back(Entry);
1701 // TrampSize == (isPPC64 ? 48 : 40);
1702 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1703 isPPC64 ? MVT::i64 : MVT::i32);
1704 Args.push_back(Entry);
1706 Entry.Node = FPtr; Args.push_back(Entry);
1707 Entry.Node = Nest; Args.push_back(Entry);
1709 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1710 TargetLowering::CallLoweringInfo CLI(Chain,
1711 Type::getVoidTy(*DAG.getContext()),
1712 false, false, false, false, 0,
1714 /*isTailCall=*/false,
1715 /*doesNotRet=*/false,
1716 /*isReturnValueUsed=*/true,
1717 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1719 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1721 return CallResult.second;
1724 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1725 const PPCSubtarget &Subtarget) const {
1726 MachineFunction &MF = DAG.getMachineFunction();
1727 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1729 DebugLoc dl = Op.getDebugLoc();
1731 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
1732 // vastart just stores the address of the VarArgsFrameIndex slot into the
1733 // memory location argument.
1734 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1735 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1736 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1737 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
1738 MachinePointerInfo(SV),
1742 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
1743 // We suppose the given va_list is already allocated.
1746 // char gpr; /* index into the array of 8 GPRs
1747 // * stored in the register save area
1748 // * gpr=0 corresponds to r3,
1749 // * gpr=1 to r4, etc.
1751 // char fpr; /* index into the array of 8 FPRs
1752 // * stored in the register save area
1753 // * fpr=0 corresponds to f1,
1754 // * fpr=1 to f2, etc.
1756 // char *overflow_arg_area;
1757 // /* location on stack that holds
1758 // * the next overflow argument
1760 // char *reg_save_area;
1761 // /* where r3:r10 and f1:f8 (if saved)
1767 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
1768 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
1771 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1773 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
1775 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1778 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
1779 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1781 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
1782 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1784 uint64_t FPROffset = 1;
1785 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1787 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1789 // Store first byte : number of int regs
1790 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
1792 MachinePointerInfo(SV),
1793 MVT::i8, false, false, 0);
1794 uint64_t nextOffset = FPROffset;
1795 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
1798 // Store second byte : number of float regs
1799 SDValue secondStore =
1800 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
1801 MachinePointerInfo(SV, nextOffset), MVT::i8,
1803 nextOffset += StackOffset;
1804 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
1806 // Store second word : arguments given on stack
1807 SDValue thirdStore =
1808 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
1809 MachinePointerInfo(SV, nextOffset),
1811 nextOffset += FrameOffset;
1812 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
1814 // Store third word : arguments given in registers
1815 return DAG.getStore(thirdStore, dl, FR, nextPtr,
1816 MachinePointerInfo(SV, nextOffset),
1821 #include "PPCGenCallingConv.inc"
1823 static bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
1824 CCValAssign::LocInfo &LocInfo,
1825 ISD::ArgFlagsTy &ArgFlags,
1830 static bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
1832 CCValAssign::LocInfo &LocInfo,
1833 ISD::ArgFlagsTy &ArgFlags,
1835 static const uint16_t ArgRegs[] = {
1836 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1837 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1839 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1841 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1843 // Skip one register if the first unallocated register has an even register
1844 // number and there are still argument registers available which have not been
1845 // allocated yet. RegNum is actually an index into ArgRegs, which means we
1846 // need to skip a register if RegNum is odd.
1847 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
1848 State.AllocateReg(ArgRegs[RegNum]);
1851 // Always return false here, as this function only makes sure that the first
1852 // unallocated register has an odd register number and does not actually
1853 // allocate a register for the current argument.
1857 static bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
1859 CCValAssign::LocInfo &LocInfo,
1860 ISD::ArgFlagsTy &ArgFlags,
1862 static const uint16_t ArgRegs[] = {
1863 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1867 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1869 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1871 // If there is only one Floating-point register left we need to put both f64
1872 // values of a split ppc_fp128 value on the stack.
1873 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
1874 State.AllocateReg(ArgRegs[RegNum]);
1877 // Always return false here, as this function only makes sure that the two f64
1878 // values a ppc_fp128 value is split into are both passed in registers or both
1879 // passed on the stack and does not actually allocate a register for the
1880 // current argument.
1884 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1886 static const uint16_t *GetFPR() {
1887 static const uint16_t FPR[] = {
1888 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1889 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1895 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
1897 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
1898 unsigned PtrByteSize) {
1899 unsigned ArgSize = ArgVT.getSizeInBits()/8;
1900 if (Flags.isByVal())
1901 ArgSize = Flags.getByValSize();
1902 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1908 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
1909 CallingConv::ID CallConv, bool isVarArg,
1910 const SmallVectorImpl<ISD::InputArg>
1912 DebugLoc dl, SelectionDAG &DAG,
1913 SmallVectorImpl<SDValue> &InVals)
1915 if (PPCSubTarget.isSVR4ABI()) {
1916 if (PPCSubTarget.isPPC64())
1917 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
1920 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
1923 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
1929 PPCTargetLowering::LowerFormalArguments_32SVR4(
1931 CallingConv::ID CallConv, bool isVarArg,
1932 const SmallVectorImpl<ISD::InputArg>
1934 DebugLoc dl, SelectionDAG &DAG,
1935 SmallVectorImpl<SDValue> &InVals) const {
1937 // 32-bit SVR4 ABI Stack Frame Layout:
1938 // +-----------------------------------+
1939 // +--> | Back chain |
1940 // | +-----------------------------------+
1941 // | | Floating-point register save area |
1942 // | +-----------------------------------+
1943 // | | General register save area |
1944 // | +-----------------------------------+
1945 // | | CR save word |
1946 // | +-----------------------------------+
1947 // | | VRSAVE save word |
1948 // | +-----------------------------------+
1949 // | | Alignment padding |
1950 // | +-----------------------------------+
1951 // | | Vector register save area |
1952 // | +-----------------------------------+
1953 // | | Local variable space |
1954 // | +-----------------------------------+
1955 // | | Parameter list area |
1956 // | +-----------------------------------+
1957 // | | LR save word |
1958 // | +-----------------------------------+
1959 // SP--> +--- | Back chain |
1960 // +-----------------------------------+
1963 // System V Application Binary Interface PowerPC Processor Supplement
1964 // AltiVec Technology Programming Interface Manual
1966 MachineFunction &MF = DAG.getMachineFunction();
1967 MachineFrameInfo *MFI = MF.getFrameInfo();
1968 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1970 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1971 // Potential tail calls could cause overwriting of argument stack slots.
1972 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
1973 (CallConv == CallingConv::Fast));
1974 unsigned PtrByteSize = 4;
1976 // Assign locations to all of the incoming arguments.
1977 SmallVector<CCValAssign, 16> ArgLocs;
1978 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1979 getTargetMachine(), ArgLocs, *DAG.getContext());
1981 // Reserve space for the linkage area on the stack.
1982 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
1984 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
1986 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1987 CCValAssign &VA = ArgLocs[i];
1989 // Arguments stored in registers.
1990 if (VA.isRegLoc()) {
1991 const TargetRegisterClass *RC;
1992 EVT ValVT = VA.getValVT();
1994 switch (ValVT.getSimpleVT().SimpleTy) {
1996 llvm_unreachable("ValVT not supported by formal arguments Lowering");
1998 RC = &PPC::GPRCRegClass;
2001 RC = &PPC::F4RCRegClass;
2004 RC = &PPC::F8RCRegClass;
2010 RC = &PPC::VRRCRegClass;
2014 // Transform the arguments stored in physical registers into virtual ones.
2015 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2016 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT);
2018 InVals.push_back(ArgValue);
2020 // Argument stored in memory.
2021 assert(VA.isMemLoc());
2023 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
2024 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2027 // Create load nodes to retrieve arguments from the stack.
2028 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2029 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2030 MachinePointerInfo(),
2031 false, false, false, 0));
2035 // Assign locations to all of the incoming aggregate by value arguments.
2036 // Aggregates passed by value are stored in the local variable space of the
2037 // caller's stack frame, right above the parameter list area.
2038 SmallVector<CCValAssign, 16> ByValArgLocs;
2039 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2040 getTargetMachine(), ByValArgLocs, *DAG.getContext());
2042 // Reserve stack space for the allocations in CCInfo.
2043 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2045 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2047 // Area that is at least reserved in the caller of this function.
2048 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2050 // Set the size that is at least reserved in caller of this function. Tail
2051 // call optimized function's reserved stack space needs to be aligned so that
2052 // taking the difference between two stack areas will result in an aligned
2054 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2057 std::max(MinReservedArea,
2058 PPCFrameLowering::getMinCallFrameSize(false, false));
2060 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
2061 getStackAlignment();
2062 unsigned AlignMask = TargetAlign-1;
2063 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2065 FI->setMinReservedArea(MinReservedArea);
2067 SmallVector<SDValue, 8> MemOps;
2069 // If the function takes variable number of arguments, make a frame index for
2070 // the start of the first vararg value... for expansion of llvm.va_start.
2072 static const uint16_t GPArgRegs[] = {
2073 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2074 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2076 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2078 static const uint16_t FPArgRegs[] = {
2079 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2082 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2084 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2086 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2089 // Make room for NumGPArgRegs and NumFPArgRegs.
2090 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2091 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
2093 FuncInfo->setVarArgsStackOffset(
2094 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2095 CCInfo.getNextStackOffset(), true));
2097 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2098 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2100 // The fixed integer arguments of a variadic function are stored to the
2101 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2102 // the result of va_next.
2103 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2104 // Get an existing live-in vreg, or add a new one.
2105 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2107 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2109 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2110 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2111 MachinePointerInfo(), false, false, 0);
2112 MemOps.push_back(Store);
2113 // Increment the address by four for the next argument to store
2114 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2115 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2118 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2120 // The double arguments are stored to the VarArgsFrameIndex
2122 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2123 // Get an existing live-in vreg, or add a new one.
2124 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2126 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2128 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2129 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2130 MachinePointerInfo(), false, false, 0);
2131 MemOps.push_back(Store);
2132 // Increment the address by eight for the next argument to store
2133 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
2135 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2139 if (!MemOps.empty())
2140 Chain = DAG.getNode(ISD::TokenFactor, dl,
2141 MVT::Other, &MemOps[0], MemOps.size());
2146 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2147 // value to MVT::i64 and then truncate to the correct register size.
2149 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2150 SelectionDAG &DAG, SDValue ArgVal,
2151 DebugLoc dl) const {
2153 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2154 DAG.getValueType(ObjectVT));
2155 else if (Flags.isZExt())
2156 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2157 DAG.getValueType(ObjectVT));
2159 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2162 // Set the size that is at least reserved in caller of this function. Tail
2163 // call optimized functions' reserved stack space needs to be aligned so that
2164 // taking the difference between two stack areas will result in an aligned
2167 PPCTargetLowering::setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG,
2168 unsigned nAltivecParamsAtEnd,
2169 unsigned MinReservedArea,
2170 bool isPPC64) const {
2171 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2172 // Add the Altivec parameters at the end, if needed.
2173 if (nAltivecParamsAtEnd) {
2174 MinReservedArea = ((MinReservedArea+15)/16)*16;
2175 MinReservedArea += 16*nAltivecParamsAtEnd;
2178 std::max(MinReservedArea,
2179 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2180 unsigned TargetAlign
2181 = DAG.getMachineFunction().getTarget().getFrameLowering()->
2182 getStackAlignment();
2183 unsigned AlignMask = TargetAlign-1;
2184 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2185 FI->setMinReservedArea(MinReservedArea);
2189 PPCTargetLowering::LowerFormalArguments_64SVR4(
2191 CallingConv::ID CallConv, bool isVarArg,
2192 const SmallVectorImpl<ISD::InputArg>
2194 DebugLoc dl, SelectionDAG &DAG,
2195 SmallVectorImpl<SDValue> &InVals) const {
2196 // TODO: add description of PPC stack frame format, or at least some docs.
2198 MachineFunction &MF = DAG.getMachineFunction();
2199 MachineFrameInfo *MFI = MF.getFrameInfo();
2200 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2202 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2203 // Potential tail calls could cause overwriting of argument stack slots.
2204 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2205 (CallConv == CallingConv::Fast));
2206 unsigned PtrByteSize = 8;
2208 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
2209 // Area that is at least reserved in caller of this function.
2210 unsigned MinReservedArea = ArgOffset;
2212 static const uint16_t GPR[] = {
2213 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2214 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2217 static const uint16_t *FPR = GetFPR();
2219 static const uint16_t VR[] = {
2220 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2221 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2224 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2225 const unsigned Num_FPR_Regs = 13;
2226 const unsigned Num_VR_Regs = array_lengthof(VR);
2228 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2230 // Add DAG nodes to load the arguments or copy them out of registers. On
2231 // entry to a function on PPC, the arguments start after the linkage area,
2232 // although the first ones are often in registers.
2234 SmallVector<SDValue, 8> MemOps;
2235 unsigned nAltivecParamsAtEnd = 0;
2236 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2237 unsigned CurArgIdx = 0;
2238 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2240 bool needsLoad = false;
2241 EVT ObjectVT = Ins[ArgNo].VT;
2242 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2243 unsigned ArgSize = ObjSize;
2244 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2245 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2246 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2248 unsigned CurArgOffset = ArgOffset;
2250 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2251 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2252 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2254 MinReservedArea = ((MinReservedArea+15)/16)*16;
2255 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2259 nAltivecParamsAtEnd++;
2261 // Calculate min reserved area.
2262 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2266 // FIXME the codegen can be much improved in some cases.
2267 // We do not have to keep everything in memory.
2268 if (Flags.isByVal()) {
2269 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2270 ObjSize = Flags.getByValSize();
2271 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2272 // Empty aggregate parameters do not take up registers. Examples:
2276 // etc. However, we have to provide a place-holder in InVals, so
2277 // pretend we have an 8-byte item at the current address for that
2280 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2281 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2282 InVals.push_back(FIN);
2285 // All aggregates smaller than 8 bytes must be passed right-justified.
2286 if (ObjSize < PtrByteSize)
2287 CurArgOffset = CurArgOffset + (PtrByteSize - ObjSize);
2288 // The value of the object is its address.
2289 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2290 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2291 InVals.push_back(FIN);
2294 if (GPR_idx != Num_GPR_Regs) {
2295 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2296 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2299 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2300 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2301 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2302 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2303 MachinePointerInfo(FuncArg, CurArgOffset),
2304 ObjType, false, false, 0);
2306 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2307 // store the whole register as-is to the parameter save area
2308 // slot. The address of the parameter was already calculated
2309 // above (InVals.push_back(FIN)) to be the right-justified
2310 // offset within the slot. For this store, we need a new
2311 // frame index that points at the beginning of the slot.
2312 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2313 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2314 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2315 MachinePointerInfo(FuncArg, ArgOffset),
2319 MemOps.push_back(Store);
2322 // Whether we copied from a register or not, advance the offset
2323 // into the parameter save area by a full doubleword.
2324 ArgOffset += PtrByteSize;
2328 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2329 // Store whatever pieces of the object are in registers
2330 // to memory. ArgOffset will be the address of the beginning
2332 if (GPR_idx != Num_GPR_Regs) {
2334 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2335 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2336 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2337 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2338 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2339 MachinePointerInfo(FuncArg, ArgOffset),
2341 MemOps.push_back(Store);
2343 ArgOffset += PtrByteSize;
2345 ArgOffset += ArgSize - j;
2352 switch (ObjectVT.getSimpleVT().SimpleTy) {
2353 default: llvm_unreachable("Unhandled argument type!");
2356 if (GPR_idx != Num_GPR_Regs) {
2357 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2358 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2360 if (ObjectVT == MVT::i32)
2361 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2362 // value to MVT::i64 and then truncate to the correct register size.
2363 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2368 ArgSize = PtrByteSize;
2375 // Every 8 bytes of argument space consumes one of the GPRs available for
2376 // argument passing.
2377 if (GPR_idx != Num_GPR_Regs) {
2380 if (FPR_idx != Num_FPR_Regs) {
2383 if (ObjectVT == MVT::f32)
2384 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2386 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2388 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2392 ArgSize = PtrByteSize;
2401 // Note that vector arguments in registers don't reserve stack space,
2402 // except in varargs functions.
2403 if (VR_idx != Num_VR_Regs) {
2404 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2405 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2407 while ((ArgOffset % 16) != 0) {
2408 ArgOffset += PtrByteSize;
2409 if (GPR_idx != Num_GPR_Regs)
2413 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2417 // Vectors are aligned.
2418 ArgOffset = ((ArgOffset+15)/16)*16;
2419 CurArgOffset = ArgOffset;
2426 // We need to load the argument to a virtual register if we determined
2427 // above that we ran out of physical registers of the appropriate type.
2429 int FI = MFI->CreateFixedObject(ObjSize,
2430 CurArgOffset + (ArgSize - ObjSize),
2432 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2433 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2434 false, false, false, 0);
2437 InVals.push_back(ArgVal);
2440 // Set the size that is at least reserved in caller of this function. Tail
2441 // call optimized functions' reserved stack space needs to be aligned so that
2442 // taking the difference between two stack areas will result in an aligned
2444 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, true);
2446 // If the function takes variable number of arguments, make a frame index for
2447 // the start of the first vararg value... for expansion of llvm.va_start.
2449 int Depth = ArgOffset;
2451 FuncInfo->setVarArgsFrameIndex(
2452 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2453 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2455 // If this function is vararg, store any remaining integer argument regs
2456 // to their spots on the stack so that they may be loaded by deferencing the
2457 // result of va_next.
2458 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2459 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2460 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2461 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2462 MachinePointerInfo(), false, false, 0);
2463 MemOps.push_back(Store);
2464 // Increment the address by four for the next argument to store
2465 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2466 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2470 if (!MemOps.empty())
2471 Chain = DAG.getNode(ISD::TokenFactor, dl,
2472 MVT::Other, &MemOps[0], MemOps.size());
2478 PPCTargetLowering::LowerFormalArguments_Darwin(
2480 CallingConv::ID CallConv, bool isVarArg,
2481 const SmallVectorImpl<ISD::InputArg>
2483 DebugLoc dl, SelectionDAG &DAG,
2484 SmallVectorImpl<SDValue> &InVals) const {
2485 // TODO: add description of PPC stack frame format, or at least some docs.
2487 MachineFunction &MF = DAG.getMachineFunction();
2488 MachineFrameInfo *MFI = MF.getFrameInfo();
2489 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2491 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2492 bool isPPC64 = PtrVT == MVT::i64;
2493 // Potential tail calls could cause overwriting of argument stack slots.
2494 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2495 (CallConv == CallingConv::Fast));
2496 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2498 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
2499 // Area that is at least reserved in caller of this function.
2500 unsigned MinReservedArea = ArgOffset;
2502 static const uint16_t GPR_32[] = { // 32-bit registers.
2503 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2504 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2506 static const uint16_t GPR_64[] = { // 64-bit registers.
2507 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2508 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2511 static const uint16_t *FPR = GetFPR();
2513 static const uint16_t VR[] = {
2514 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2515 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2518 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2519 const unsigned Num_FPR_Regs = 13;
2520 const unsigned Num_VR_Regs = array_lengthof( VR);
2522 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2524 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
2526 // In 32-bit non-varargs functions, the stack space for vectors is after the
2527 // stack space for non-vectors. We do not use this space unless we have
2528 // too many vectors to fit in registers, something that only occurs in
2529 // constructed examples:), but we have to walk the arglist to figure
2530 // that out...for the pathological case, compute VecArgOffset as the
2531 // start of the vector parameter area. Computing VecArgOffset is the
2532 // entire point of the following loop.
2533 unsigned VecArgOffset = ArgOffset;
2534 if (!isVarArg && !isPPC64) {
2535 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
2537 EVT ObjectVT = Ins[ArgNo].VT;
2538 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2540 if (Flags.isByVal()) {
2541 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
2542 unsigned ObjSize = Flags.getByValSize();
2544 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2545 VecArgOffset += ArgSize;
2549 switch(ObjectVT.getSimpleVT().SimpleTy) {
2550 default: llvm_unreachable("Unhandled argument type!");
2555 case MVT::i64: // PPC64
2557 // FIXME: We are guaranteed to be !isPPC64 at this point.
2558 // Does MVT::i64 apply?
2565 // Nothing to do, we're only looking at Nonvector args here.
2570 // We've found where the vector parameter area in memory is. Skip the
2571 // first 12 parameters; these don't use that memory.
2572 VecArgOffset = ((VecArgOffset+15)/16)*16;
2573 VecArgOffset += 12*16;
2575 // Add DAG nodes to load the arguments or copy them out of registers. On
2576 // entry to a function on PPC, the arguments start after the linkage area,
2577 // although the first ones are often in registers.
2579 SmallVector<SDValue, 8> MemOps;
2580 unsigned nAltivecParamsAtEnd = 0;
2581 // FIXME: FuncArg and Ins[ArgNo] must reference the same argument.
2582 // When passing anonymous aggregates, this is currently not true.
2583 // See LowerFormalArguments_64SVR4 for a fix.
2584 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2585 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo, ++FuncArg) {
2587 bool needsLoad = false;
2588 EVT ObjectVT = Ins[ArgNo].VT;
2589 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2590 unsigned ArgSize = ObjSize;
2591 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2593 unsigned CurArgOffset = ArgOffset;
2595 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2596 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2597 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2598 if (isVarArg || isPPC64) {
2599 MinReservedArea = ((MinReservedArea+15)/16)*16;
2600 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2603 } else nAltivecParamsAtEnd++;
2605 // Calculate min reserved area.
2606 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2610 // FIXME the codegen can be much improved in some cases.
2611 // We do not have to keep everything in memory.
2612 if (Flags.isByVal()) {
2613 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2614 ObjSize = Flags.getByValSize();
2615 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2616 // Objects of size 1 and 2 are right justified, everything else is
2617 // left justified. This means the memory address is adjusted forwards.
2618 if (ObjSize==1 || ObjSize==2) {
2619 CurArgOffset = CurArgOffset + (4 - ObjSize);
2621 // The value of the object is its address.
2622 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2623 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2624 InVals.push_back(FIN);
2625 if (ObjSize==1 || ObjSize==2) {
2626 if (GPR_idx != Num_GPR_Regs) {
2629 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2631 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2632 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2633 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
2634 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2635 MachinePointerInfo(FuncArg,
2637 ObjType, false, false, 0);
2638 MemOps.push_back(Store);
2642 ArgOffset += PtrByteSize;
2646 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2647 // Store whatever pieces of the object are in registers
2648 // to memory. ArgOffset will be the address of the beginning
2650 if (GPR_idx != Num_GPR_Regs) {
2653 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2655 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2656 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2657 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2658 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2659 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2660 MachinePointerInfo(FuncArg, ArgOffset),
2662 MemOps.push_back(Store);
2664 ArgOffset += PtrByteSize;
2666 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
2673 switch (ObjectVT.getSimpleVT().SimpleTy) {
2674 default: llvm_unreachable("Unhandled argument type!");
2677 if (GPR_idx != Num_GPR_Regs) {
2678 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2679 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2683 ArgSize = PtrByteSize;
2685 // All int arguments reserve stack space in the Darwin ABI.
2686 ArgOffset += PtrByteSize;
2690 case MVT::i64: // PPC64
2691 if (GPR_idx != Num_GPR_Regs) {
2692 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2693 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2695 if (ObjectVT == MVT::i32)
2696 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2697 // value to MVT::i64 and then truncate to the correct register size.
2698 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2703 ArgSize = PtrByteSize;
2705 // All int arguments reserve stack space in the Darwin ABI.
2711 // Every 4 bytes of argument space consumes one of the GPRs available for
2712 // argument passing.
2713 if (GPR_idx != Num_GPR_Regs) {
2715 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
2718 if (FPR_idx != Num_FPR_Regs) {
2721 if (ObjectVT == MVT::f32)
2722 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2724 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2726 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2732 // All FP arguments reserve stack space in the Darwin ABI.
2733 ArgOffset += isPPC64 ? 8 : ObjSize;
2739 // Note that vector arguments in registers don't reserve stack space,
2740 // except in varargs functions.
2741 if (VR_idx != Num_VR_Regs) {
2742 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2743 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2745 while ((ArgOffset % 16) != 0) {
2746 ArgOffset += PtrByteSize;
2747 if (GPR_idx != Num_GPR_Regs)
2751 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2755 if (!isVarArg && !isPPC64) {
2756 // Vectors go after all the nonvectors.
2757 CurArgOffset = VecArgOffset;
2760 // Vectors are aligned.
2761 ArgOffset = ((ArgOffset+15)/16)*16;
2762 CurArgOffset = ArgOffset;
2770 // We need to load the argument to a virtual register if we determined above
2771 // that we ran out of physical registers of the appropriate type.
2773 int FI = MFI->CreateFixedObject(ObjSize,
2774 CurArgOffset + (ArgSize - ObjSize),
2776 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2777 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2778 false, false, false, 0);
2781 InVals.push_back(ArgVal);
2784 // Set the size that is at least reserved in caller of this function. Tail
2785 // call optimized functions' reserved stack space needs to be aligned so that
2786 // taking the difference between two stack areas will result in an aligned
2788 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, isPPC64);
2790 // If the function takes variable number of arguments, make a frame index for
2791 // the start of the first vararg value... for expansion of llvm.va_start.
2793 int Depth = ArgOffset;
2795 FuncInfo->setVarArgsFrameIndex(
2796 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2798 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2800 // If this function is vararg, store any remaining integer argument regs
2801 // to their spots on the stack so that they may be loaded by deferencing the
2802 // result of va_next.
2803 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2807 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2809 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2811 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2812 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2813 MachinePointerInfo(), false, false, 0);
2814 MemOps.push_back(Store);
2815 // Increment the address by four for the next argument to store
2816 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2817 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2821 if (!MemOps.empty())
2822 Chain = DAG.getNode(ISD::TokenFactor, dl,
2823 MVT::Other, &MemOps[0], MemOps.size());
2828 /// CalculateParameterAndLinkageAreaSize - Get the size of the parameter plus
2829 /// linkage area for the Darwin ABI, or the 64-bit SVR4 ABI.
2831 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
2835 const SmallVectorImpl<ISD::OutputArg>
2837 const SmallVectorImpl<SDValue> &OutVals,
2838 unsigned &nAltivecParamsAtEnd) {
2839 // Count how many bytes are to be pushed on the stack, including the linkage
2840 // area, and parameter passing area. We start with 24/48 bytes, which is
2841 // prereserved space for [SP][CR][LR][3 x unused].
2842 unsigned NumBytes = PPCFrameLowering::getLinkageSize(isPPC64, true);
2843 unsigned NumOps = Outs.size();
2844 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2846 // Add up all the space actually used.
2847 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
2848 // they all go in registers, but we must reserve stack space for them for
2849 // possible use by the caller. In varargs or 64-bit calls, parameters are
2850 // assigned stack space in order, with padding so Altivec parameters are
2852 nAltivecParamsAtEnd = 0;
2853 for (unsigned i = 0; i != NumOps; ++i) {
2854 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2855 EVT ArgVT = Outs[i].VT;
2856 // Varargs Altivec parameters are padded to a 16 byte boundary.
2857 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
2858 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
2859 if (!isVarArg && !isPPC64) {
2860 // Non-varargs Altivec parameters go after all the non-Altivec
2861 // parameters; handle those later so we know how much padding we need.
2862 nAltivecParamsAtEnd++;
2865 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
2866 NumBytes = ((NumBytes+15)/16)*16;
2868 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2871 // Allow for Altivec parameters at the end, if needed.
2872 if (nAltivecParamsAtEnd) {
2873 NumBytes = ((NumBytes+15)/16)*16;
2874 NumBytes += 16*nAltivecParamsAtEnd;
2877 // The prolog code of the callee may store up to 8 GPR argument registers to
2878 // the stack, allowing va_start to index over them in memory if its varargs.
2879 // Because we cannot tell if this is needed on the caller side, we have to
2880 // conservatively assume that it is needed. As such, make sure we have at
2881 // least enough stack space for the caller to store the 8 GPRs.
2882 NumBytes = std::max(NumBytes,
2883 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2885 // Tail call needs the stack to be aligned.
2886 if (CC == CallingConv::Fast && DAG.getTarget().Options.GuaranteedTailCallOpt){
2887 unsigned TargetAlign = DAG.getMachineFunction().getTarget().
2888 getFrameLowering()->getStackAlignment();
2889 unsigned AlignMask = TargetAlign-1;
2890 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2896 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
2897 /// adjusted to accommodate the arguments for the tailcall.
2898 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
2899 unsigned ParamSize) {
2901 if (!isTailCall) return 0;
2903 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
2904 unsigned CallerMinReservedArea = FI->getMinReservedArea();
2905 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
2906 // Remember only if the new adjustement is bigger.
2907 if (SPDiff < FI->getTailCallSPDelta())
2908 FI->setTailCallSPDelta(SPDiff);
2913 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2914 /// for tail call optimization. Targets which want to do tail call
2915 /// optimization should implement this function.
2917 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2918 CallingConv::ID CalleeCC,
2920 const SmallVectorImpl<ISD::InputArg> &Ins,
2921 SelectionDAG& DAG) const {
2922 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
2925 // Variable argument functions are not supported.
2929 MachineFunction &MF = DAG.getMachineFunction();
2930 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
2931 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
2932 // Functions containing by val parameters are not supported.
2933 for (unsigned i = 0; i != Ins.size(); i++) {
2934 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2935 if (Flags.isByVal()) return false;
2938 // Non PIC/GOT tail calls are supported.
2939 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
2942 // At the moment we can only do local tail calls (in same module, hidden
2943 // or protected) if we are generating PIC.
2944 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2945 return G->getGlobal()->hasHiddenVisibility()
2946 || G->getGlobal()->hasProtectedVisibility();
2952 /// isCallCompatibleAddress - Return the immediate to use if the specified
2953 /// 32-bit value is representable in the immediate field of a BxA instruction.
2954 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
2955 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2958 int Addr = C->getZExtValue();
2959 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
2960 SignExtend32<26>(Addr) != Addr)
2961 return 0; // Top 6 bits have to be sext of immediate.
2963 return DAG.getConstant((int)C->getZExtValue() >> 2,
2964 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
2969 struct TailCallArgumentInfo {
2974 TailCallArgumentInfo() : FrameIdx(0) {}
2979 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
2981 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
2983 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs,
2984 SmallVector<SDValue, 8> &MemOpChains,
2986 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
2987 SDValue Arg = TailCallArgs[i].Arg;
2988 SDValue FIN = TailCallArgs[i].FrameIdxOp;
2989 int FI = TailCallArgs[i].FrameIdx;
2990 // Store relative to framepointer.
2991 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
2992 MachinePointerInfo::getFixedStack(FI),
2997 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
2998 /// the appropriate stack slot for the tail call optimized function call.
2999 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3000 MachineFunction &MF,
3009 // Calculate the new stack slot for the return address.
3010 int SlotSize = isPPC64 ? 8 : 4;
3011 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
3013 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3014 NewRetAddrLoc, true);
3015 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3016 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3017 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3018 MachinePointerInfo::getFixedStack(NewRetAddr),
3021 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3022 // slot as the FP is never overwritten.
3025 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
3026 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3028 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3029 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3030 MachinePointerInfo::getFixedStack(NewFPIdx),
3037 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3038 /// the position of the argument.
3040 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3041 SDValue Arg, int SPDiff, unsigned ArgOffset,
3042 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
3043 int Offset = ArgOffset + SPDiff;
3044 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3045 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3046 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3047 SDValue FIN = DAG.getFrameIndex(FI, VT);
3048 TailCallArgumentInfo Info;
3050 Info.FrameIdxOp = FIN;
3052 TailCallArguments.push_back(Info);
3055 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3056 /// stack slot. Returns the chain as result and the loaded frame pointers in
3057 /// LROpOut/FPOpout. Used when tail calling.
3058 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3064 DebugLoc dl) const {
3066 // Load the LR and FP stack slot for later adjusting.
3067 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
3068 LROpOut = getReturnAddrFrameIndex(DAG);
3069 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3070 false, false, false, 0);
3071 Chain = SDValue(LROpOut.getNode(), 1);
3073 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3074 // slot as the FP is never overwritten.
3076 FPOpOut = getFramePointerFrameIndex(DAG);
3077 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3078 false, false, false, 0);
3079 Chain = SDValue(FPOpOut.getNode(), 1);
3085 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3086 /// by "Src" to address "Dst" of size "Size". Alignment information is
3087 /// specified by the specific parameter attribute. The copy will be passed as
3088 /// a byval function parameter.
3089 /// Sometimes what we are copying is the end of a larger object, the part that
3090 /// does not fit in registers.
3092 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3093 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3095 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3096 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3097 false, false, MachinePointerInfo(0),
3098 MachinePointerInfo(0));
3101 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3104 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3105 SDValue Arg, SDValue PtrOff, int SPDiff,
3106 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3107 bool isVector, SmallVector<SDValue, 8> &MemOpChains,
3108 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments,
3110 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3115 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3117 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3118 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3119 DAG.getConstant(ArgOffset, PtrVT));
3121 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3122 MachinePointerInfo(), false, false, 0));
3123 // Calculate and remember argument location.
3124 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3129 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3130 DebugLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3131 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3132 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments) {
3133 MachineFunction &MF = DAG.getMachineFunction();
3135 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3136 // might overwrite each other in case of tail call optimization.
3137 SmallVector<SDValue, 8> MemOpChains2;
3138 // Do not flag preceding copytoreg stuff together with the following stuff.
3140 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3142 if (!MemOpChains2.empty())
3143 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3144 &MemOpChains2[0], MemOpChains2.size());
3146 // Store the return address to the appropriate stack slot.
3147 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3148 isPPC64, isDarwinABI, dl);
3150 // Emit callseq_end just before tailcall node.
3151 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3152 DAG.getIntPtrConstant(0, true), InFlag);
3153 InFlag = Chain.getValue(1);
3157 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3158 SDValue &Chain, DebugLoc dl, int SPDiff, bool isTailCall,
3159 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
3160 SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys,
3161 const PPCSubtarget &PPCSubTarget) {
3163 bool isPPC64 = PPCSubTarget.isPPC64();
3164 bool isSVR4ABI = PPCSubTarget.isSVR4ABI();
3166 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3167 NodeTys.push_back(MVT::Other); // Returns a chain
3168 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3170 unsigned CallOpc = PPCISD::CALL;
3172 bool needIndirectCall = true;
3173 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3174 // If this is an absolute destination address, use the munged value.
3175 Callee = SDValue(Dest, 0);
3176 needIndirectCall = false;
3179 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3180 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201
3181 // Use indirect calls for ALL functions calls in JIT mode, since the
3182 // far-call stubs may be outside relocation limits for a BL instruction.
3183 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
3184 unsigned OpFlags = 0;
3185 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3186 (PPCSubTarget.getTargetTriple().isMacOSX() &&
3187 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3188 (G->getGlobal()->isDeclaration() ||
3189 G->getGlobal()->isWeakForLinker())) {
3190 // PC-relative references to external symbols should go through $stub,
3191 // unless we're building with the leopard linker or later, which
3192 // automatically synthesizes these stubs.
3193 OpFlags = PPCII::MO_DARWIN_STUB;
3196 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3197 // every direct call is) turn it into a TargetGlobalAddress /
3198 // TargetExternalSymbol node so that legalize doesn't hack it.
3199 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3200 Callee.getValueType(),
3202 needIndirectCall = false;
3206 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3207 unsigned char OpFlags = 0;
3209 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3210 (PPCSubTarget.getTargetTriple().isMacOSX() &&
3211 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5))) {
3212 // PC-relative references to external symbols should go through $stub,
3213 // unless we're building with the leopard linker or later, which
3214 // automatically synthesizes these stubs.
3215 OpFlags = PPCII::MO_DARWIN_STUB;
3218 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3220 needIndirectCall = false;
3223 if (needIndirectCall) {
3224 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3225 // to do the call, we can't use PPCISD::CALL.
3226 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3228 if (isSVR4ABI && isPPC64) {
3229 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3230 // entry point, but to the function descriptor (the function entry point
3231 // address is part of the function descriptor though).
3232 // The function descriptor is a three doubleword structure with the
3233 // following fields: function entry point, TOC base address and
3234 // environment pointer.
3235 // Thus for a call through a function pointer, the following actions need
3237 // 1. Save the TOC of the caller in the TOC save area of its stack
3238 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3239 // 2. Load the address of the function entry point from the function
3241 // 3. Load the TOC of the callee from the function descriptor into r2.
3242 // 4. Load the environment pointer from the function descriptor into
3244 // 5. Branch to the function entry point address.
3245 // 6. On return of the callee, the TOC of the caller needs to be
3246 // restored (this is done in FinishCall()).
3248 // All those operations are flagged together to ensure that no other
3249 // operations can be scheduled in between. E.g. without flagging the
3250 // operations together, a TOC access in the caller could be scheduled
3251 // between the load of the callee TOC and the branch to the callee, which
3252 // results in the TOC access going through the TOC of the callee instead
3253 // of going through the TOC of the caller, which leads to incorrect code.
3255 // Load the address of the function entry point from the function
3257 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3258 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps,
3259 InFlag.getNode() ? 3 : 2);
3260 Chain = LoadFuncPtr.getValue(1);
3261 InFlag = LoadFuncPtr.getValue(2);
3263 // Load environment pointer into r11.
3264 // Offset of the environment pointer within the function descriptor.
3265 SDValue PtrOff = DAG.getIntPtrConstant(16);
3267 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3268 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
3270 Chain = LoadEnvPtr.getValue(1);
3271 InFlag = LoadEnvPtr.getValue(2);
3273 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3275 Chain = EnvVal.getValue(0);
3276 InFlag = EnvVal.getValue(1);
3278 // Load TOC of the callee into r2. We are using a target-specific load
3279 // with r2 hard coded, because the result of a target-independent load
3280 // would never go directly into r2, since r2 is a reserved register (which
3281 // prevents the register allocator from allocating it), resulting in an
3282 // additional register being allocated and an unnecessary move instruction
3284 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3285 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
3287 Chain = LoadTOCPtr.getValue(0);
3288 InFlag = LoadTOCPtr.getValue(1);
3290 MTCTROps[0] = Chain;
3291 MTCTROps[1] = LoadFuncPtr;
3292 MTCTROps[2] = InFlag;
3295 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps,
3296 2 + (InFlag.getNode() != 0));
3297 InFlag = Chain.getValue(1);
3300 NodeTys.push_back(MVT::Other);
3301 NodeTys.push_back(MVT::Glue);
3302 Ops.push_back(Chain);
3303 CallOpc = PPCISD::BCTRL;
3305 // Add use of X11 (holding environment pointer)
3306 if (isSVR4ABI && isPPC64)
3307 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3308 // Add CTR register as callee so a bctr can be emitted later.
3310 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3313 // If this is a direct call, pass the chain and the callee.
3314 if (Callee.getNode()) {
3315 Ops.push_back(Chain);
3316 Ops.push_back(Callee);
3318 // If this is a tail call add stack pointer delta.
3320 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3322 // Add argument registers to the end of the list so that they are known live
3324 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3325 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3326 RegsToPass[i].second.getValueType()));
3332 bool isLocalCall(const SDValue &Callee)
3334 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3335 return !G->getGlobal()->isDeclaration() &&
3336 !G->getGlobal()->isWeakForLinker();
3341 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3342 CallingConv::ID CallConv, bool isVarArg,
3343 const SmallVectorImpl<ISD::InputArg> &Ins,
3344 DebugLoc dl, SelectionDAG &DAG,
3345 SmallVectorImpl<SDValue> &InVals) const {
3347 SmallVector<CCValAssign, 16> RVLocs;
3348 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3349 getTargetMachine(), RVLocs, *DAG.getContext());
3350 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3352 // Copy all of the result registers out of their specified physreg.
3353 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3354 CCValAssign &VA = RVLocs[i];
3355 assert(VA.isRegLoc() && "Can only return in registers!");
3357 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3358 VA.getLocReg(), VA.getLocVT(), InFlag);
3359 Chain = Val.getValue(1);
3360 InFlag = Val.getValue(2);
3362 switch (VA.getLocInfo()) {
3363 default: llvm_unreachable("Unknown loc info!");
3364 case CCValAssign::Full: break;
3365 case CCValAssign::AExt:
3366 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3368 case CCValAssign::ZExt:
3369 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3370 DAG.getValueType(VA.getValVT()));
3371 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3373 case CCValAssign::SExt:
3374 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3375 DAG.getValueType(VA.getValVT()));
3376 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3380 InVals.push_back(Val);
3387 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, DebugLoc dl,
3388 bool isTailCall, bool isVarArg,
3390 SmallVector<std::pair<unsigned, SDValue>, 8>
3392 SDValue InFlag, SDValue Chain,
3394 int SPDiff, unsigned NumBytes,
3395 const SmallVectorImpl<ISD::InputArg> &Ins,
3396 SmallVectorImpl<SDValue> &InVals) const {
3397 std::vector<EVT> NodeTys;
3398 SmallVector<SDValue, 8> Ops;
3399 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
3400 isTailCall, RegsToPass, Ops, NodeTys,
3403 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3404 if (isVarArg && PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64())
3405 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3407 // When performing tail call optimization the callee pops its arguments off
3408 // the stack. Account for this here so these bytes can be pushed back on in
3409 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3410 int BytesCalleePops =
3411 (CallConv == CallingConv::Fast &&
3412 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3414 // Add a register mask operand representing the call-preserved registers.
3415 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
3416 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3417 assert(Mask && "Missing call preserved mask for calling convention");
3418 Ops.push_back(DAG.getRegisterMask(Mask));
3420 if (InFlag.getNode())
3421 Ops.push_back(InFlag);
3425 assert(((Callee.getOpcode() == ISD::Register &&
3426 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3427 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3428 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3429 isa<ConstantSDNode>(Callee)) &&
3430 "Expecting an global address, external symbol, absolute value or register");
3432 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size());
3435 // Add a NOP immediately after the branch instruction when using the 64-bit
3436 // SVR4 ABI. At link time, if caller and callee are in a different module and
3437 // thus have a different TOC, the call will be replaced with a call to a stub
3438 // function which saves the current TOC, loads the TOC of the callee and
3439 // branches to the callee. The NOP will be replaced with a load instruction
3440 // which restores the TOC of the caller from the TOC save slot of the current
3441 // stack frame. If caller and callee belong to the same module (and have the
3442 // same TOC), the NOP will remain unchanged.
3444 bool needsTOCRestore = false;
3445 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) {
3446 if (CallOpc == PPCISD::BCTRL) {
3447 // This is a call through a function pointer.
3448 // Restore the caller TOC from the save area into R2.
3449 // See PrepareCall() for more information about calls through function
3450 // pointers in the 64-bit SVR4 ABI.
3451 // We are using a target-specific load with r2 hard coded, because the
3452 // result of a target-independent load would never go directly into r2,
3453 // since r2 is a reserved register (which prevents the register allocator
3454 // from allocating it), resulting in an additional register being
3455 // allocated and an unnecessary move instruction being generated.
3456 needsTOCRestore = true;
3457 } else if ((CallOpc == PPCISD::CALL) && !isLocalCall(Callee)) {
3458 // Otherwise insert NOP for non-local calls.
3459 CallOpc = PPCISD::CALL_NOP;
3463 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
3464 InFlag = Chain.getValue(1);
3466 if (needsTOCRestore) {
3467 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3468 Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag);
3469 InFlag = Chain.getValue(1);
3472 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3473 DAG.getIntPtrConstant(BytesCalleePops, true),
3476 InFlag = Chain.getValue(1);
3478 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3479 Ins, dl, DAG, InVals);
3483 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3484 SmallVectorImpl<SDValue> &InVals) const {
3485 SelectionDAG &DAG = CLI.DAG;
3486 DebugLoc &dl = CLI.DL;
3487 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
3488 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
3489 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
3490 SDValue Chain = CLI.Chain;
3491 SDValue Callee = CLI.Callee;
3492 bool &isTailCall = CLI.IsTailCall;
3493 CallingConv::ID CallConv = CLI.CallConv;
3494 bool isVarArg = CLI.IsVarArg;
3497 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3500 if (PPCSubTarget.isSVR4ABI()) {
3501 if (PPCSubTarget.isPPC64())
3502 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3503 isTailCall, Outs, OutVals, Ins,
3506 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3507 isTailCall, Outs, OutVals, Ins,
3511 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
3512 isTailCall, Outs, OutVals, Ins,
3517 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
3518 CallingConv::ID CallConv, bool isVarArg,
3520 const SmallVectorImpl<ISD::OutputArg> &Outs,
3521 const SmallVectorImpl<SDValue> &OutVals,
3522 const SmallVectorImpl<ISD::InputArg> &Ins,
3523 DebugLoc dl, SelectionDAG &DAG,
3524 SmallVectorImpl<SDValue> &InVals) const {
3525 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
3526 // of the 32-bit SVR4 ABI stack frame layout.
3528 assert((CallConv == CallingConv::C ||
3529 CallConv == CallingConv::Fast) && "Unknown calling convention!");
3531 unsigned PtrByteSize = 4;
3533 MachineFunction &MF = DAG.getMachineFunction();
3535 // Mark this function as potentially containing a function that contains a
3536 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3537 // and restoring the callers stack pointer in this functions epilog. This is
3538 // done because by tail calling the called function might overwrite the value
3539 // in this function's (MF) stack pointer stack slot 0(SP).
3540 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3541 CallConv == CallingConv::Fast)
3542 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3544 // Count how many bytes are to be pushed on the stack, including the linkage
3545 // area, parameter list area and the part of the local variable space which
3546 // contains copies of aggregates which are passed by value.
3548 // Assign locations to all of the outgoing arguments.
3549 SmallVector<CCValAssign, 16> ArgLocs;
3550 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3551 getTargetMachine(), ArgLocs, *DAG.getContext());
3553 // Reserve space for the linkage area on the stack.
3554 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
3557 // Handle fixed and variable vector arguments differently.
3558 // Fixed vector arguments go into registers as long as registers are
3559 // available. Variable vector arguments always go into memory.
3560 unsigned NumArgs = Outs.size();
3562 for (unsigned i = 0; i != NumArgs; ++i) {
3563 MVT ArgVT = Outs[i].VT;
3564 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3567 if (Outs[i].IsFixed) {
3568 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
3571 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
3577 errs() << "Call operand #" << i << " has unhandled type "
3578 << EVT(ArgVT).getEVTString() << "\n";
3580 llvm_unreachable(0);
3584 // All arguments are treated the same.
3585 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
3588 // Assign locations to all of the outgoing aggregate by value arguments.
3589 SmallVector<CCValAssign, 16> ByValArgLocs;
3590 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3591 getTargetMachine(), ByValArgLocs, *DAG.getContext());
3593 // Reserve stack space for the allocations in CCInfo.
3594 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
3596 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
3598 // Size of the linkage area, parameter list area and the part of the local
3599 // space variable where copies of aggregates which are passed by value are
3601 unsigned NumBytes = CCByValInfo.getNextStackOffset();
3603 // Calculate by how many bytes the stack has to be adjusted in case of tail
3604 // call optimization.
3605 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3607 // Adjust the stack pointer for the new arguments...
3608 // These operations are automatically eliminated by the prolog/epilog pass
3609 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
3610 SDValue CallSeqStart = Chain;
3612 // Load the return address and frame pointer so it can be moved somewhere else
3615 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
3618 // Set up a copy of the stack pointer for use loading and storing any
3619 // arguments that may not fit in the registers available for argument
3621 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3623 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3624 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3625 SmallVector<SDValue, 8> MemOpChains;
3627 bool seenFloatArg = false;
3628 // Walk the register/memloc assignments, inserting copies/loads.
3629 for (unsigned i = 0, j = 0, e = ArgLocs.size();
3632 CCValAssign &VA = ArgLocs[i];
3633 SDValue Arg = OutVals[i];
3634 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3636 if (Flags.isByVal()) {
3637 // Argument is an aggregate which is passed by value, thus we need to
3638 // create a copy of it in the local variable space of the current stack
3639 // frame (which is the stack frame of the caller) and pass the address of
3640 // this copy to the callee.
3641 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
3642 CCValAssign &ByValVA = ByValArgLocs[j++];
3643 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
3645 // Memory reserved in the local variable space of the callers stack frame.
3646 unsigned LocMemOffset = ByValVA.getLocMemOffset();
3648 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3649 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3651 // Create a copy of the argument in the local area of the current
3653 SDValue MemcpyCall =
3654 CreateCopyOfByValArgument(Arg, PtrOff,
3655 CallSeqStart.getNode()->getOperand(0),
3658 // This must go outside the CALLSEQ_START..END.
3659 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3660 CallSeqStart.getNode()->getOperand(1));
3661 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3662 NewCallSeqStart.getNode());
3663 Chain = CallSeqStart = NewCallSeqStart;
3665 // Pass the address of the aggregate copy on the stack either in a
3666 // physical register or in the parameter list area of the current stack
3667 // frame to the callee.
3671 if (VA.isRegLoc()) {
3672 seenFloatArg |= VA.getLocVT().isFloatingPoint();
3673 // Put argument in a physical register.
3674 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3676 // Put argument in the parameter list area of the current stack frame.
3677 assert(VA.isMemLoc());
3678 unsigned LocMemOffset = VA.getLocMemOffset();
3681 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3682 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3684 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3685 MachinePointerInfo(),
3688 // Calculate and remember argument location.
3689 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
3695 if (!MemOpChains.empty())
3696 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3697 &MemOpChains[0], MemOpChains.size());
3699 // Build a sequence of copy-to-reg nodes chained together with token chain
3700 // and flag operands which copy the outgoing args into the appropriate regs.
3702 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3703 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3704 RegsToPass[i].second, InFlag);
3705 InFlag = Chain.getValue(1);
3708 // Set CR bit 6 to true if this is a vararg call with floating args passed in
3711 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3712 SDValue Ops[] = { Chain, InFlag };
3714 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
3715 dl, VTs, Ops, InFlag.getNode() ? 2 : 1);
3717 InFlag = Chain.getValue(1);
3721 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
3722 false, TailCallArguments);
3724 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3725 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3729 // Copy an argument into memory, being careful to do this outside the
3730 // call sequence for the call to which the argument belongs.
3732 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
3733 SDValue CallSeqStart,
3734 ISD::ArgFlagsTy Flags,
3736 DebugLoc dl) const {
3737 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
3738 CallSeqStart.getNode()->getOperand(0),
3740 // The MEMCPY must go outside the CALLSEQ_START..END.
3741 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3742 CallSeqStart.getNode()->getOperand(1));
3743 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3744 NewCallSeqStart.getNode());
3745 return NewCallSeqStart;
3749 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
3750 CallingConv::ID CallConv, bool isVarArg,
3752 const SmallVectorImpl<ISD::OutputArg> &Outs,
3753 const SmallVectorImpl<SDValue> &OutVals,
3754 const SmallVectorImpl<ISD::InputArg> &Ins,
3755 DebugLoc dl, SelectionDAG &DAG,
3756 SmallVectorImpl<SDValue> &InVals) const {
3758 unsigned NumOps = Outs.size();
3760 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3761 unsigned PtrByteSize = 8;
3763 MachineFunction &MF = DAG.getMachineFunction();
3765 // Mark this function as potentially containing a function that contains a
3766 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3767 // and restoring the callers stack pointer in this functions epilog. This is
3768 // done because by tail calling the called function might overwrite the value
3769 // in this function's (MF) stack pointer stack slot 0(SP).
3770 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3771 CallConv == CallingConv::Fast)
3772 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3774 unsigned nAltivecParamsAtEnd = 0;
3776 // Count how many bytes are to be pushed on the stack, including the linkage
3777 // area, and parameter passing area. We start with at least 48 bytes, which
3778 // is reserved space for [SP][CR][LR][3 x unused].
3779 // NOTE: For PPC64, nAltivecParamsAtEnd always remains zero as a result
3782 CalculateParameterAndLinkageAreaSize(DAG, true, isVarArg, CallConv,
3783 Outs, OutVals, nAltivecParamsAtEnd);
3785 // Calculate by how many bytes the stack has to be adjusted in case of tail
3786 // call optimization.
3787 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3789 // To protect arguments on the stack from being clobbered in a tail call,
3790 // force all the loads to happen before doing any other lowering.
3792 Chain = DAG.getStackArgumentTokenFactor(Chain);
3794 // Adjust the stack pointer for the new arguments...
3795 // These operations are automatically eliminated by the prolog/epilog pass
3796 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
3797 SDValue CallSeqStart = Chain;
3799 // Load the return address and frame pointer so it can be move somewhere else
3802 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
3805 // Set up a copy of the stack pointer for use loading and storing any
3806 // arguments that may not fit in the registers available for argument
3808 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3810 // Figure out which arguments are going to go in registers, and which in
3811 // memory. Also, if this is a vararg function, floating point operations
3812 // must be stored to our stack, and loaded into integer regs as well, if
3813 // any integer regs are available for argument passing.
3814 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
3815 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3817 static const uint16_t GPR[] = {
3818 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3819 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3821 static const uint16_t *FPR = GetFPR();
3823 static const uint16_t VR[] = {
3824 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3825 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3827 const unsigned NumGPRs = array_lengthof(GPR);
3828 const unsigned NumFPRs = 13;
3829 const unsigned NumVRs = array_lengthof(VR);
3831 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3832 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3834 SmallVector<SDValue, 8> MemOpChains;
3835 for (unsigned i = 0; i != NumOps; ++i) {
3836 SDValue Arg = OutVals[i];
3837 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3839 // PtrOff will be used to store the current argument to the stack if a
3840 // register cannot be found for it.
3843 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
3845 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
3847 // Promote integers to 64-bit values.
3848 if (Arg.getValueType() == MVT::i32) {
3849 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
3850 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3851 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
3854 // FIXME memcpy is used way more than necessary. Correctness first.
3855 // Note: "by value" is code for passing a structure by value, not
3857 if (Flags.isByVal()) {
3858 // Note: Size includes alignment padding, so
3859 // struct x { short a; char b; }
3860 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
3861 // These are the proper values we need for right-justifying the
3862 // aggregate in a parameter register.
3863 unsigned Size = Flags.getByValSize();
3865 // An empty aggregate parameter takes up no storage and no
3870 // All aggregates smaller than 8 bytes must be passed right-justified.
3871 if (Size==1 || Size==2 || Size==4) {
3872 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
3873 if (GPR_idx != NumGPRs) {
3874 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
3875 MachinePointerInfo(), VT,
3877 MemOpChains.push_back(Load.getValue(1));
3878 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3880 ArgOffset += PtrByteSize;
3885 if (GPR_idx == NumGPRs && Size < 8) {
3886 SDValue Const = DAG.getConstant(PtrByteSize - Size,
3887 PtrOff.getValueType());
3888 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3889 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
3892 ArgOffset += PtrByteSize;
3895 // Copy entire object into memory. There are cases where gcc-generated
3896 // code assumes it is there, even if it could be put entirely into
3897 // registers. (This is not what the doc says.)
3899 // FIXME: The above statement is likely due to a misunderstanding of the
3900 // documents. All arguments must be copied into the parameter area BY
3901 // THE CALLEE in the event that the callee takes the address of any
3902 // formal argument. That has not yet been implemented. However, it is
3903 // reasonable to use the stack area as a staging area for the register
3906 // Skip this for small aggregates, as we will use the same slot for a
3907 // right-justified copy, below.
3909 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
3913 // When a register is available, pass a small aggregate right-justified.
3914 if (Size < 8 && GPR_idx != NumGPRs) {
3915 // The easiest way to get this right-justified in a register
3916 // is to copy the structure into the rightmost portion of a
3917 // local variable slot, then load the whole slot into the
3919 // FIXME: The memcpy seems to produce pretty awful code for
3920 // small aggregates, particularly for packed ones.
3921 // FIXME: It would be preferable to use the slot in the
3922 // parameter save area instead of a new local variable.
3923 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
3924 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3925 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
3929 // Load the slot into the register.
3930 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
3931 MachinePointerInfo(),
3932 false, false, false, 0);
3933 MemOpChains.push_back(Load.getValue(1));
3934 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3936 // Done with this argument.
3937 ArgOffset += PtrByteSize;
3941 // For aggregates larger than PtrByteSize, copy the pieces of the
3942 // object that fit into registers from the parameter save area.
3943 for (unsigned j=0; j<Size; j+=PtrByteSize) {
3944 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
3945 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
3946 if (GPR_idx != NumGPRs) {
3947 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
3948 MachinePointerInfo(),
3949 false, false, false, 0);
3950 MemOpChains.push_back(Load.getValue(1));
3951 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3952 ArgOffset += PtrByteSize;
3954 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
3961 switch (Arg.getValueType().getSimpleVT().SimpleTy) {
3962 default: llvm_unreachable("Unexpected ValueType for argument!");
3965 if (GPR_idx != NumGPRs) {
3966 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
3968 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3969 true, isTailCall, false, MemOpChains,
3970 TailCallArguments, dl);
3972 ArgOffset += PtrByteSize;
3976 if (FPR_idx != NumFPRs) {
3977 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
3980 // A single float or an aggregate containing only a single float
3981 // must be passed right-justified in the stack doubleword, and
3982 // in the GPR, if one is available.
3984 if (Arg.getValueType().getSimpleVT().SimpleTy == MVT::f32) {
3985 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
3986 StoreOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
3990 SDValue Store = DAG.getStore(Chain, dl, Arg, StoreOff,
3991 MachinePointerInfo(), false, false, 0);
3992 MemOpChains.push_back(Store);
3994 // Float varargs are always shadowed in available integer registers
3995 if (GPR_idx != NumGPRs) {
3996 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
3997 MachinePointerInfo(), false, false,
3999 MemOpChains.push_back(Load.getValue(1));
4000 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4002 } else if (GPR_idx != NumGPRs)
4003 // If we have any FPRs remaining, we may also have GPRs remaining.
4006 // Single-precision floating-point values are mapped to the
4007 // second (rightmost) word of the stack doubleword.
4008 if (Arg.getValueType() == MVT::f32) {
4009 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4010 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4013 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4014 true, isTailCall, false, MemOpChains,
4015 TailCallArguments, dl);
4024 // These go aligned on the stack, or in the corresponding R registers
4025 // when within range. The Darwin PPC ABI doc claims they also go in
4026 // V registers; in fact gcc does this only for arguments that are
4027 // prototyped, not for those that match the ... We do it for all
4028 // arguments, seems to work.
4029 while (ArgOffset % 16 !=0) {
4030 ArgOffset += PtrByteSize;
4031 if (GPR_idx != NumGPRs)
4034 // We could elide this store in the case where the object fits
4035 // entirely in R registers. Maybe later.
4036 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4037 DAG.getConstant(ArgOffset, PtrVT));
4038 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4039 MachinePointerInfo(), false, false, 0);
4040 MemOpChains.push_back(Store);
4041 if (VR_idx != NumVRs) {
4042 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4043 MachinePointerInfo(),
4044 false, false, false, 0);
4045 MemOpChains.push_back(Load.getValue(1));
4046 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4049 for (unsigned i=0; i<16; i+=PtrByteSize) {
4050 if (GPR_idx == NumGPRs)
4052 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4053 DAG.getConstant(i, PtrVT));
4054 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4055 false, false, false, 0);
4056 MemOpChains.push_back(Load.getValue(1));
4057 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4062 // Non-varargs Altivec params generally go in registers, but have
4063 // stack space allocated at the end.
4064 if (VR_idx != NumVRs) {
4065 // Doesn't have GPR space allocated.
4066 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4068 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4069 true, isTailCall, true, MemOpChains,
4070 TailCallArguments, dl);
4077 if (!MemOpChains.empty())
4078 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4079 &MemOpChains[0], MemOpChains.size());
4081 // Check if this is an indirect call (MTCTR/BCTRL).
4082 // See PrepareCall() for more information about calls through function
4083 // pointers in the 64-bit SVR4 ABI.
4085 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4086 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4087 !isBLACompatibleAddress(Callee, DAG)) {
4088 // Load r2 into a virtual register and store it to the TOC save area.
4089 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4090 // TOC save area offset.
4091 SDValue PtrOff = DAG.getIntPtrConstant(40);
4092 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4093 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
4095 // R12 must contain the address of an indirect callee. This does not
4096 // mean the MTCTR instruction must use R12; it's easier to model this
4097 // as an extra parameter, so do that.
4098 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
4101 // Build a sequence of copy-to-reg nodes chained together with token chain
4102 // and flag operands which copy the outgoing args into the appropriate regs.
4104 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4105 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4106 RegsToPass[i].second, InFlag);
4107 InFlag = Chain.getValue(1);
4111 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4112 FPOp, true, TailCallArguments);
4114 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4115 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4120 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4121 CallingConv::ID CallConv, bool isVarArg,
4123 const SmallVectorImpl<ISD::OutputArg> &Outs,
4124 const SmallVectorImpl<SDValue> &OutVals,
4125 const SmallVectorImpl<ISD::InputArg> &Ins,
4126 DebugLoc dl, SelectionDAG &DAG,
4127 SmallVectorImpl<SDValue> &InVals) const {
4129 unsigned NumOps = Outs.size();
4131 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4132 bool isPPC64 = PtrVT == MVT::i64;
4133 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4135 MachineFunction &MF = DAG.getMachineFunction();
4137 // Mark this function as potentially containing a function that contains a
4138 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4139 // and restoring the callers stack pointer in this functions epilog. This is
4140 // done because by tail calling the called function might overwrite the value
4141 // in this function's (MF) stack pointer stack slot 0(SP).
4142 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4143 CallConv == CallingConv::Fast)
4144 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4146 unsigned nAltivecParamsAtEnd = 0;
4148 // Count how many bytes are to be pushed on the stack, including the linkage
4149 // area, and parameter passing area. We start with 24/48 bytes, which is
4150 // prereserved space for [SP][CR][LR][3 x unused].
4152 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv,
4154 nAltivecParamsAtEnd);
4156 // Calculate by how many bytes the stack has to be adjusted in case of tail
4157 // call optimization.
4158 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4160 // To protect arguments on the stack from being clobbered in a tail call,
4161 // force all the loads to happen before doing any other lowering.
4163 Chain = DAG.getStackArgumentTokenFactor(Chain);
4165 // Adjust the stack pointer for the new arguments...
4166 // These operations are automatically eliminated by the prolog/epilog pass
4167 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
4168 SDValue CallSeqStart = Chain;
4170 // Load the return address and frame pointer so it can be move somewhere else
4173 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4176 // Set up a copy of the stack pointer for use loading and storing any
4177 // arguments that may not fit in the registers available for argument
4181 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4183 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4185 // Figure out which arguments are going to go in registers, and which in
4186 // memory. Also, if this is a vararg function, floating point operations
4187 // must be stored to our stack, and loaded into integer regs as well, if
4188 // any integer regs are available for argument passing.
4189 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
4190 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4192 static const uint16_t GPR_32[] = { // 32-bit registers.
4193 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4194 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4196 static const uint16_t GPR_64[] = { // 64-bit registers.
4197 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4198 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4200 static const uint16_t *FPR = GetFPR();
4202 static const uint16_t VR[] = {
4203 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4204 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4206 const unsigned NumGPRs = array_lengthof(GPR_32);
4207 const unsigned NumFPRs = 13;
4208 const unsigned NumVRs = array_lengthof(VR);
4210 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
4212 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4213 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4215 SmallVector<SDValue, 8> MemOpChains;
4216 for (unsigned i = 0; i != NumOps; ++i) {
4217 SDValue Arg = OutVals[i];
4218 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4220 // PtrOff will be used to store the current argument to the stack if a
4221 // register cannot be found for it.
4224 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4226 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4228 // On PPC64, promote integers to 64-bit values.
4229 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4230 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4231 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4232 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4235 // FIXME memcpy is used way more than necessary. Correctness first.
4236 // Note: "by value" is code for passing a structure by value, not
4238 if (Flags.isByVal()) {
4239 unsigned Size = Flags.getByValSize();
4240 // Very small objects are passed right-justified. Everything else is
4241 // passed left-justified.
4242 if (Size==1 || Size==2) {
4243 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4244 if (GPR_idx != NumGPRs) {
4245 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4246 MachinePointerInfo(), VT,
4248 MemOpChains.push_back(Load.getValue(1));
4249 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4251 ArgOffset += PtrByteSize;
4253 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4254 PtrOff.getValueType());
4255 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4256 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4259 ArgOffset += PtrByteSize;
4263 // Copy entire object into memory. There are cases where gcc-generated
4264 // code assumes it is there, even if it could be put entirely into
4265 // registers. (This is not what the doc says.)
4266 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4270 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4271 // copy the pieces of the object that fit into registers from the
4272 // parameter save area.
4273 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4274 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4275 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4276 if (GPR_idx != NumGPRs) {
4277 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4278 MachinePointerInfo(),
4279 false, false, false, 0);
4280 MemOpChains.push_back(Load.getValue(1));
4281 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4282 ArgOffset += PtrByteSize;
4284 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4291 switch (Arg.getValueType().getSimpleVT().SimpleTy) {
4292 default: llvm_unreachable("Unexpected ValueType for argument!");
4295 if (GPR_idx != NumGPRs) {
4296 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4298 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4299 isPPC64, isTailCall, false, MemOpChains,
4300 TailCallArguments, dl);
4302 ArgOffset += PtrByteSize;
4306 if (FPR_idx != NumFPRs) {
4307 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4310 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4311 MachinePointerInfo(), false, false, 0);
4312 MemOpChains.push_back(Store);
4314 // Float varargs are always shadowed in available integer registers
4315 if (GPR_idx != NumGPRs) {
4316 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4317 MachinePointerInfo(), false, false,
4319 MemOpChains.push_back(Load.getValue(1));
4320 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4322 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4323 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4324 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4325 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4326 MachinePointerInfo(),
4327 false, false, false, 0);
4328 MemOpChains.push_back(Load.getValue(1));
4329 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4332 // If we have any FPRs remaining, we may also have GPRs remaining.
4333 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4335 if (GPR_idx != NumGPRs)
4337 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4338 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4342 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4343 isPPC64, isTailCall, false, MemOpChains,
4344 TailCallArguments, dl);
4348 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4355 // These go aligned on the stack, or in the corresponding R registers
4356 // when within range. The Darwin PPC ABI doc claims they also go in
4357 // V registers; in fact gcc does this only for arguments that are
4358 // prototyped, not for those that match the ... We do it for all
4359 // arguments, seems to work.
4360 while (ArgOffset % 16 !=0) {
4361 ArgOffset += PtrByteSize;
4362 if (GPR_idx != NumGPRs)
4365 // We could elide this store in the case where the object fits
4366 // entirely in R registers. Maybe later.
4367 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4368 DAG.getConstant(ArgOffset, PtrVT));
4369 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4370 MachinePointerInfo(), false, false, 0);
4371 MemOpChains.push_back(Store);
4372 if (VR_idx != NumVRs) {
4373 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4374 MachinePointerInfo(),
4375 false, false, false, 0);
4376 MemOpChains.push_back(Load.getValue(1));
4377 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4380 for (unsigned i=0; i<16; i+=PtrByteSize) {
4381 if (GPR_idx == NumGPRs)
4383 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4384 DAG.getConstant(i, PtrVT));
4385 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4386 false, false, false, 0);
4387 MemOpChains.push_back(Load.getValue(1));
4388 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4393 // Non-varargs Altivec params generally go in registers, but have
4394 // stack space allocated at the end.
4395 if (VR_idx != NumVRs) {
4396 // Doesn't have GPR space allocated.
4397 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4398 } else if (nAltivecParamsAtEnd==0) {
4399 // We are emitting Altivec params in order.
4400 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4401 isPPC64, isTailCall, true, MemOpChains,
4402 TailCallArguments, dl);
4408 // If all Altivec parameters fit in registers, as they usually do,
4409 // they get stack space following the non-Altivec parameters. We
4410 // don't track this here because nobody below needs it.
4411 // If there are more Altivec parameters than fit in registers emit
4413 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
4415 // Offset is aligned; skip 1st 12 params which go in V registers.
4416 ArgOffset = ((ArgOffset+15)/16)*16;
4418 for (unsigned i = 0; i != NumOps; ++i) {
4419 SDValue Arg = OutVals[i];
4420 EVT ArgType = Outs[i].VT;
4421 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
4422 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
4425 // We are emitting Altivec params in order.
4426 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4427 isPPC64, isTailCall, true, MemOpChains,
4428 TailCallArguments, dl);
4435 if (!MemOpChains.empty())
4436 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4437 &MemOpChains[0], MemOpChains.size());
4439 // On Darwin, R12 must contain the address of an indirect callee. This does
4440 // not mean the MTCTR instruction must use R12; it's easier to model this as
4441 // an extra parameter, so do that.
4443 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4444 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4445 !isBLACompatibleAddress(Callee, DAG))
4446 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
4447 PPC::R12), Callee));
4449 // Build a sequence of copy-to-reg nodes chained together with token chain
4450 // and flag operands which copy the outgoing args into the appropriate regs.
4452 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4453 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4454 RegsToPass[i].second, InFlag);
4455 InFlag = Chain.getValue(1);
4459 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
4460 FPOp, true, TailCallArguments);
4462 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4463 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4468 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
4469 MachineFunction &MF, bool isVarArg,
4470 const SmallVectorImpl<ISD::OutputArg> &Outs,
4471 LLVMContext &Context) const {
4472 SmallVector<CCValAssign, 16> RVLocs;
4473 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
4475 return CCInfo.CheckReturn(Outs, RetCC_PPC);
4479 PPCTargetLowering::LowerReturn(SDValue Chain,
4480 CallingConv::ID CallConv, bool isVarArg,
4481 const SmallVectorImpl<ISD::OutputArg> &Outs,
4482 const SmallVectorImpl<SDValue> &OutVals,
4483 DebugLoc dl, SelectionDAG &DAG) const {
4485 SmallVector<CCValAssign, 16> RVLocs;
4486 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4487 getTargetMachine(), RVLocs, *DAG.getContext());
4488 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
4491 SmallVector<SDValue, 4> RetOps(1, Chain);
4493 // Copy the result values into the output registers.
4494 for (unsigned i = 0; i != RVLocs.size(); ++i) {
4495 CCValAssign &VA = RVLocs[i];
4496 assert(VA.isRegLoc() && "Can only return in registers!");
4498 SDValue Arg = OutVals[i];
4500 switch (VA.getLocInfo()) {
4501 default: llvm_unreachable("Unknown loc info!");
4502 case CCValAssign::Full: break;
4503 case CCValAssign::AExt:
4504 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
4506 case CCValAssign::ZExt:
4507 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
4509 case CCValAssign::SExt:
4510 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
4514 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
4515 Flag = Chain.getValue(1);
4516 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
4519 RetOps[0] = Chain; // Update chain.
4521 // Add the flag if we have it.
4523 RetOps.push_back(Flag);
4525 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other,
4526 &RetOps[0], RetOps.size());
4529 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
4530 const PPCSubtarget &Subtarget) const {
4531 // When we pop the dynamic allocation we need to restore the SP link.
4532 DebugLoc dl = Op.getDebugLoc();
4534 // Get the corect type for pointers.
4535 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4537 // Construct the stack pointer operand.
4538 bool isPPC64 = Subtarget.isPPC64();
4539 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
4540 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
4542 // Get the operands for the STACKRESTORE.
4543 SDValue Chain = Op.getOperand(0);
4544 SDValue SaveSP = Op.getOperand(1);
4546 // Load the old link SP.
4547 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
4548 MachinePointerInfo(),
4549 false, false, false, 0);
4551 // Restore the stack pointer.
4552 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
4554 // Store the old link SP.
4555 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
4562 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
4563 MachineFunction &MF = DAG.getMachineFunction();
4564 bool isPPC64 = PPCSubTarget.isPPC64();
4565 bool isDarwinABI = PPCSubTarget.isDarwinABI();
4566 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4568 // Get current frame pointer save index. The users of this index will be
4569 // primarily DYNALLOC instructions.
4570 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4571 int RASI = FI->getReturnAddrSaveIndex();
4573 // If the frame pointer save index hasn't been defined yet.
4575 // Find out what the fix offset of the frame pointer save area.
4576 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
4577 // Allocate the frame index for frame pointer save area.
4578 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
4580 FI->setReturnAddrSaveIndex(RASI);
4582 return DAG.getFrameIndex(RASI, PtrVT);
4586 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
4587 MachineFunction &MF = DAG.getMachineFunction();
4588 bool isPPC64 = PPCSubTarget.isPPC64();
4589 bool isDarwinABI = PPCSubTarget.isDarwinABI();
4590 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4592 // Get current frame pointer save index. The users of this index will be
4593 // primarily DYNALLOC instructions.
4594 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4595 int FPSI = FI->getFramePointerSaveIndex();
4597 // If the frame pointer save index hasn't been defined yet.
4599 // Find out what the fix offset of the frame pointer save area.
4600 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
4603 // Allocate the frame index for frame pointer save area.
4604 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
4606 FI->setFramePointerSaveIndex(FPSI);
4608 return DAG.getFrameIndex(FPSI, PtrVT);
4611 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
4613 const PPCSubtarget &Subtarget) const {
4615 SDValue Chain = Op.getOperand(0);
4616 SDValue Size = Op.getOperand(1);
4617 DebugLoc dl = Op.getDebugLoc();
4619 // Get the corect type for pointers.
4620 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4622 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
4623 DAG.getConstant(0, PtrVT), Size);
4624 // Construct a node for the frame pointer save index.
4625 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
4626 // Build a DYNALLOC node.
4627 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
4628 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
4629 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3);
4632 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
4633 SelectionDAG &DAG) const {
4634 DebugLoc DL = Op.getDebugLoc();
4635 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
4636 DAG.getVTList(MVT::i32, MVT::Other),
4637 Op.getOperand(0), Op.getOperand(1));
4640 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
4641 SelectionDAG &DAG) const {
4642 DebugLoc DL = Op.getDebugLoc();
4643 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
4644 Op.getOperand(0), Op.getOperand(1));
4647 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
4649 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
4650 // Not FP? Not a fsel.
4651 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
4652 !Op.getOperand(2).getValueType().isFloatingPoint())
4655 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4657 // Cannot handle SETEQ/SETNE.
4658 if (CC == ISD::SETEQ || CC == ISD::SETNE) return Op;
4660 EVT ResVT = Op.getValueType();
4661 EVT CmpVT = Op.getOperand(0).getValueType();
4662 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4663 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
4664 DebugLoc dl = Op.getDebugLoc();
4666 // If the RHS of the comparison is a 0.0, we don't need to do the
4667 // subtraction at all.
4668 if (isFloatingPointZero(RHS))
4670 default: break; // SETUO etc aren't handled by fsel.
4673 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
4676 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4677 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4678 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
4681 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
4684 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4685 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4686 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4687 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
4692 default: break; // SETUO etc aren't handled by fsel.
4695 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4696 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4697 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4698 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
4701 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4702 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4703 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4704 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4707 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
4708 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4709 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4710 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
4713 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
4714 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4715 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4716 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4721 // FIXME: Split this code up when LegalizeDAGTypes lands.
4722 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
4723 DebugLoc dl) const {
4724 assert(Op.getOperand(0).getValueType().isFloatingPoint());
4725 SDValue Src = Op.getOperand(0);
4726 if (Src.getValueType() == MVT::f32)
4727 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
4730 switch (Op.getValueType().getSimpleVT().SimpleTy) {
4731 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
4733 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
4734 (PPCSubTarget.hasFPCVT() ? PPCISD::FCTIWUZ :
4739 assert((Op.getOpcode() == ISD::FP_TO_SINT || PPCSubTarget.hasFPCVT()) &&
4740 "i64 FP_TO_UINT is supported only with FPCVT");
4741 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
4747 // Convert the FP value to an int value through memory.
4748 bool i32Stack = Op.getValueType() == MVT::i32 && PPCSubTarget.hasSTFIWX() &&
4749 (Op.getOpcode() == ISD::FP_TO_SINT || PPCSubTarget.hasFPCVT());
4750 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
4751 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
4752 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
4754 // Emit a store to the stack slot.
4757 MachineFunction &MF = DAG.getMachineFunction();
4758 MachineMemOperand *MMO =
4759 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
4760 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
4761 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
4762 DAG.getVTList(MVT::Other), Ops, array_lengthof(Ops),
4765 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
4766 MPI, false, false, 0);
4768 // Result is a load from the stack slot. If loading 4 bytes, make sure to
4770 if (Op.getValueType() == MVT::i32 && !i32Stack) {
4771 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
4772 DAG.getConstant(4, FIPtr.getValueType()));
4773 MPI = MachinePointerInfo();
4776 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MPI,
4777 false, false, false, 0);
4780 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
4781 SelectionDAG &DAG) const {
4782 DebugLoc dl = Op.getDebugLoc();
4783 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
4784 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
4787 assert((Op.getOpcode() == ISD::SINT_TO_FP || PPCSubTarget.hasFPCVT()) &&
4788 "UINT_TO_FP is supported only with FPCVT");
4790 // If we have FCFIDS, then use it when converting to single-precision.
4791 // Otherwise, convert to double-precision and then round.
4792 unsigned FCFOp = (PPCSubTarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
4793 (Op.getOpcode() == ISD::UINT_TO_FP ?
4794 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
4795 (Op.getOpcode() == ISD::UINT_TO_FP ?
4796 PPCISD::FCFIDU : PPCISD::FCFID);
4797 MVT FCFTy = (PPCSubTarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
4798 MVT::f32 : MVT::f64;
4800 if (Op.getOperand(0).getValueType() == MVT::i64) {
4801 SDValue SINT = Op.getOperand(0);
4802 // When converting to single-precision, we actually need to convert
4803 // to double-precision first and then round to single-precision.
4804 // To avoid double-rounding effects during that operation, we have
4805 // to prepare the input operand. Bits that might be truncated when
4806 // converting to double-precision are replaced by a bit that won't
4807 // be lost at this stage, but is below the single-precision rounding
4810 // However, if -enable-unsafe-fp-math is in effect, accept double
4811 // rounding to avoid the extra overhead.
4812 if (Op.getValueType() == MVT::f32 &&
4813 !PPCSubTarget.hasFPCVT() &&
4814 !DAG.getTarget().Options.UnsafeFPMath) {
4816 // Twiddle input to make sure the low 11 bits are zero. (If this
4817 // is the case, we are guaranteed the value will fit into the 53 bit
4818 // mantissa of an IEEE double-precision value without rounding.)
4819 // If any of those low 11 bits were not zero originally, make sure
4820 // bit 12 (value 2048) is set instead, so that the final rounding
4821 // to single-precision gets the correct result.
4822 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
4823 SINT, DAG.getConstant(2047, MVT::i64));
4824 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
4825 Round, DAG.getConstant(2047, MVT::i64));
4826 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
4827 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
4828 Round, DAG.getConstant(-2048, MVT::i64));
4830 // However, we cannot use that value unconditionally: if the magnitude
4831 // of the input value is small, the bit-twiddling we did above might
4832 // end up visibly changing the output. Fortunately, in that case, we
4833 // don't need to twiddle bits since the original input will convert
4834 // exactly to double-precision floating-point already. Therefore,
4835 // construct a conditional to use the original value if the top 11
4836 // bits are all sign-bit copies, and use the rounded value computed
4838 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
4839 SINT, DAG.getConstant(53, MVT::i32));
4840 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
4841 Cond, DAG.getConstant(1, MVT::i64));
4842 Cond = DAG.getSetCC(dl, MVT::i32,
4843 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
4845 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
4848 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
4849 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
4851 if (Op.getValueType() == MVT::f32 && !PPCSubTarget.hasFPCVT())
4852 FP = DAG.getNode(ISD::FP_ROUND, dl,
4853 MVT::f32, FP, DAG.getIntPtrConstant(0));
4857 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
4858 "Unhandled INT_TO_FP type in custom expander!");
4859 // Since we only generate this in 64-bit mode, we can take advantage of
4860 // 64-bit registers. In particular, sign extend the input value into the
4861 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
4862 // then lfd it and fcfid it.
4863 MachineFunction &MF = DAG.getMachineFunction();
4864 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
4865 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4868 if (PPCSubTarget.hasLFIWAX() || PPCSubTarget.hasFPCVT()) {
4869 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
4870 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4872 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
4873 MachinePointerInfo::getFixedStack(FrameIdx),
4876 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
4877 "Expected an i32 store");
4878 MachineMemOperand *MMO =
4879 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
4880 MachineMemOperand::MOLoad, 4, 4);
4881 SDValue Ops[] = { Store, FIdx };
4882 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
4883 PPCISD::LFIWZX : PPCISD::LFIWAX,
4884 dl, DAG.getVTList(MVT::f64, MVT::Other),
4885 Ops, 2, MVT::i32, MMO);
4887 assert(PPCSubTarget.isPPC64() &&
4888 "i32->FP without LFIWAX supported only on PPC64");
4890 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
4891 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4893 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
4896 // STD the extended value into the stack slot.
4897 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
4898 MachinePointerInfo::getFixedStack(FrameIdx),
4901 // Load the value as a double.
4902 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
4903 MachinePointerInfo::getFixedStack(FrameIdx),
4904 false, false, false, 0);
4907 // FCFID it and return it.
4908 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
4909 if (Op.getValueType() == MVT::f32 && !PPCSubTarget.hasFPCVT())
4910 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
4914 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
4915 SelectionDAG &DAG) const {
4916 DebugLoc dl = Op.getDebugLoc();
4918 The rounding mode is in bits 30:31 of FPSR, and has the following
4925 FLT_ROUNDS, on the other hand, expects the following:
4932 To perform the conversion, we do:
4933 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
4936 MachineFunction &MF = DAG.getMachineFunction();
4937 EVT VT = Op.getValueType();
4938 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4939 SDValue MFFSreg, InFlag;
4941 // Save FP Control Word to register
4943 MVT::f64, // return register
4944 MVT::Glue // unused in this context
4946 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
4948 // Save FP register to stack slot
4949 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
4950 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
4951 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
4952 StackSlot, MachinePointerInfo(), false, false,0);
4954 // Load FP Control Word from low 32 bits of stack slot.
4955 SDValue Four = DAG.getConstant(4, PtrVT);
4956 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
4957 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
4958 false, false, false, 0);
4960 // Transform as necessary
4962 DAG.getNode(ISD::AND, dl, MVT::i32,
4963 CWD, DAG.getConstant(3, MVT::i32));
4965 DAG.getNode(ISD::SRL, dl, MVT::i32,
4966 DAG.getNode(ISD::AND, dl, MVT::i32,
4967 DAG.getNode(ISD::XOR, dl, MVT::i32,
4968 CWD, DAG.getConstant(3, MVT::i32)),
4969 DAG.getConstant(3, MVT::i32)),
4970 DAG.getConstant(1, MVT::i32));
4973 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
4975 return DAG.getNode((VT.getSizeInBits() < 16 ?
4976 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
4979 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
4980 EVT VT = Op.getValueType();
4981 unsigned BitWidth = VT.getSizeInBits();
4982 DebugLoc dl = Op.getDebugLoc();
4983 assert(Op.getNumOperands() == 3 &&
4984 VT == Op.getOperand(1).getValueType() &&
4987 // Expand into a bunch of logical ops. Note that these ops
4988 // depend on the PPC behavior for oversized shift amounts.
4989 SDValue Lo = Op.getOperand(0);
4990 SDValue Hi = Op.getOperand(1);
4991 SDValue Amt = Op.getOperand(2);
4992 EVT AmtVT = Amt.getValueType();
4994 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
4995 DAG.getConstant(BitWidth, AmtVT), Amt);
4996 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
4997 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
4998 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
4999 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5000 DAG.getConstant(-BitWidth, AmtVT));
5001 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5002 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5003 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
5004 SDValue OutOps[] = { OutLo, OutHi };
5005 return DAG.getMergeValues(OutOps, 2, dl);
5008 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5009 EVT VT = Op.getValueType();
5010 DebugLoc dl = Op.getDebugLoc();
5011 unsigned BitWidth = VT.getSizeInBits();
5012 assert(Op.getNumOperands() == 3 &&
5013 VT == Op.getOperand(1).getValueType() &&
5016 // Expand into a bunch of logical ops. Note that these ops
5017 // depend on the PPC behavior for oversized shift amounts.
5018 SDValue Lo = Op.getOperand(0);
5019 SDValue Hi = Op.getOperand(1);
5020 SDValue Amt = Op.getOperand(2);
5021 EVT AmtVT = Amt.getValueType();
5023 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5024 DAG.getConstant(BitWidth, AmtVT), Amt);
5025 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5026 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5027 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5028 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5029 DAG.getConstant(-BitWidth, AmtVT));
5030 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
5031 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5032 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
5033 SDValue OutOps[] = { OutLo, OutHi };
5034 return DAG.getMergeValues(OutOps, 2, dl);
5037 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
5038 DebugLoc dl = Op.getDebugLoc();
5039 EVT VT = Op.getValueType();
5040 unsigned BitWidth = VT.getSizeInBits();
5041 assert(Op.getNumOperands() == 3 &&
5042 VT == Op.getOperand(1).getValueType() &&
5045 // Expand into a bunch of logical ops, followed by a select_cc.
5046 SDValue Lo = Op.getOperand(0);
5047 SDValue Hi = Op.getOperand(1);
5048 SDValue Amt = Op.getOperand(2);
5049 EVT AmtVT = Amt.getValueType();
5051 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5052 DAG.getConstant(BitWidth, AmtVT), Amt);
5053 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5054 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5055 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5056 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5057 DAG.getConstant(-BitWidth, AmtVT));
5058 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
5059 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
5060 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
5061 Tmp4, Tmp6, ISD::SETLE);
5062 SDValue OutOps[] = { OutLo, OutHi };
5063 return DAG.getMergeValues(OutOps, 2, dl);
5066 //===----------------------------------------------------------------------===//
5067 // Vector related lowering.
5070 /// BuildSplatI - Build a canonical splati of Val with an element size of
5071 /// SplatSize. Cast the result to VT.
5072 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
5073 SelectionDAG &DAG, DebugLoc dl) {
5074 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
5076 static const EVT VTys[] = { // canonical VT to use for each size.
5077 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
5080 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
5082 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
5086 EVT CanonicalVT = VTys[SplatSize-1];
5088 // Build a canonical splat for this value.
5089 SDValue Elt = DAG.getConstant(Val, MVT::i32);
5090 SmallVector<SDValue, 8> Ops;
5091 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
5092 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
5093 &Ops[0], Ops.size());
5094 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
5097 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
5098 /// specified intrinsic ID.
5099 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
5100 SelectionDAG &DAG, DebugLoc dl,
5101 EVT DestVT = MVT::Other) {
5102 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
5103 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5104 DAG.getConstant(IID, MVT::i32), LHS, RHS);
5107 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
5108 /// specified intrinsic ID.
5109 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
5110 SDValue Op2, SelectionDAG &DAG,
5111 DebugLoc dl, EVT DestVT = MVT::Other) {
5112 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
5113 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5114 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
5118 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
5119 /// amount. The result has the specified value type.
5120 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
5121 EVT VT, SelectionDAG &DAG, DebugLoc dl) {
5122 // Force LHS/RHS to be the right type.
5123 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
5124 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
5127 for (unsigned i = 0; i != 16; ++i)
5129 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
5130 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5133 // If this is a case we can't handle, return null and let the default
5134 // expansion code take care of it. If we CAN select this case, and if it
5135 // selects to a single instruction, return Op. Otherwise, if we can codegen
5136 // this case more efficiently than a constant pool load, lower it to the
5137 // sequence of ops that should be used.
5138 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
5139 SelectionDAG &DAG) const {
5140 DebugLoc dl = Op.getDebugLoc();
5141 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5142 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
5144 // Check if this is a splat of a constant value.
5145 APInt APSplatBits, APSplatUndef;
5146 unsigned SplatBitSize;
5148 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
5149 HasAnyUndefs, 0, true) || SplatBitSize > 32)
5152 unsigned SplatBits = APSplatBits.getZExtValue();
5153 unsigned SplatUndef = APSplatUndef.getZExtValue();
5154 unsigned SplatSize = SplatBitSize / 8;
5156 // First, handle single instruction cases.
5159 if (SplatBits == 0) {
5160 // Canonicalize all zero vectors to be v4i32.
5161 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5162 SDValue Z = DAG.getConstant(0, MVT::i32);
5163 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5164 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
5169 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
5170 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
5172 if (SextVal >= -16 && SextVal <= 15)
5173 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
5176 // Two instruction sequences.
5178 // If this value is in the range [-32,30] and is even, use:
5179 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
5180 // If this value is in the range [17,31] and is odd, use:
5181 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
5182 // If this value is in the range [-31,-17] and is odd, use:
5183 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
5184 // Note the last two are three-instruction sequences.
5185 if (SextVal >= -32 && SextVal <= 31) {
5186 // To avoid having these optimizations undone by constant folding,
5187 // we convert to a pseudo that will be expanded later into one of
5189 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
5190 EVT VT = Op.getValueType();
5191 int Size = VT == MVT::v16i8 ? 1 : (VT == MVT::v8i16 ? 2 : 4);
5192 SDValue EltSize = DAG.getConstant(Size, MVT::i32);
5193 return DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
5196 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
5197 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
5199 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
5200 // Make -1 and vspltisw -1:
5201 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
5203 // Make the VSLW intrinsic, computing 0x8000_0000.
5204 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
5207 // xor by OnesV to invert it.
5208 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5209 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5212 // Check to see if this is a wide variety of vsplti*, binop self cases.
5213 static const signed char SplatCsts[] = {
5214 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
5215 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
5218 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
5219 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
5220 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
5221 int i = SplatCsts[idx];
5223 // Figure out what shift amount will be used by altivec if shifted by i in
5225 unsigned TypeShiftAmt = i & (SplatBitSize-1);
5227 // vsplti + shl self.
5228 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
5229 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5230 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5231 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
5232 Intrinsic::ppc_altivec_vslw
5234 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5235 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5238 // vsplti + srl self.
5239 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5240 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5241 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5242 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
5243 Intrinsic::ppc_altivec_vsrw
5245 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5246 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5249 // vsplti + sra self.
5250 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5251 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5252 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5253 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
5254 Intrinsic::ppc_altivec_vsraw
5256 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5257 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5260 // vsplti + rol self.
5261 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
5262 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
5263 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5264 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5265 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
5266 Intrinsic::ppc_altivec_vrlw
5268 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5269 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5272 // t = vsplti c, result = vsldoi t, t, 1
5273 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
5274 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5275 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
5277 // t = vsplti c, result = vsldoi t, t, 2
5278 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
5279 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5280 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
5282 // t = vsplti c, result = vsldoi t, t, 3
5283 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
5284 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5285 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
5292 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5293 /// the specified operations to build the shuffle.
5294 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5295 SDValue RHS, SelectionDAG &DAG,
5297 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5298 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5299 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5302 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5314 if (OpNum == OP_COPY) {
5315 if (LHSID == (1*9+2)*9+3) return LHS;
5316 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5320 SDValue OpLHS, OpRHS;
5321 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5322 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5326 default: llvm_unreachable("Unknown i32 permute!");
5328 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
5329 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
5330 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
5331 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
5334 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
5335 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
5336 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
5337 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
5340 for (unsigned i = 0; i != 16; ++i)
5341 ShufIdxs[i] = (i&3)+0;
5344 for (unsigned i = 0; i != 16; ++i)
5345 ShufIdxs[i] = (i&3)+4;
5348 for (unsigned i = 0; i != 16; ++i)
5349 ShufIdxs[i] = (i&3)+8;
5352 for (unsigned i = 0; i != 16; ++i)
5353 ShufIdxs[i] = (i&3)+12;
5356 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
5358 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
5360 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
5362 EVT VT = OpLHS.getValueType();
5363 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
5364 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
5365 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
5366 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5369 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
5370 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
5371 /// return the code it can be lowered into. Worst case, it can always be
5372 /// lowered into a vperm.
5373 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5374 SelectionDAG &DAG) const {
5375 DebugLoc dl = Op.getDebugLoc();
5376 SDValue V1 = Op.getOperand(0);
5377 SDValue V2 = Op.getOperand(1);
5378 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5379 EVT VT = Op.getValueType();
5381 // Cases that are handled by instructions that take permute immediates
5382 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
5383 // selected by the instruction selector.
5384 if (V2.getOpcode() == ISD::UNDEF) {
5385 if (PPC::isSplatShuffleMask(SVOp, 1) ||
5386 PPC::isSplatShuffleMask(SVOp, 2) ||
5387 PPC::isSplatShuffleMask(SVOp, 4) ||
5388 PPC::isVPKUWUMShuffleMask(SVOp, true) ||
5389 PPC::isVPKUHUMShuffleMask(SVOp, true) ||
5390 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 ||
5391 PPC::isVMRGLShuffleMask(SVOp, 1, true) ||
5392 PPC::isVMRGLShuffleMask(SVOp, 2, true) ||
5393 PPC::isVMRGLShuffleMask(SVOp, 4, true) ||
5394 PPC::isVMRGHShuffleMask(SVOp, 1, true) ||
5395 PPC::isVMRGHShuffleMask(SVOp, 2, true) ||
5396 PPC::isVMRGHShuffleMask(SVOp, 4, true)) {
5401 // Altivec has a variety of "shuffle immediates" that take two vector inputs
5402 // and produce a fixed permutation. If any of these match, do not lower to
5404 if (PPC::isVPKUWUMShuffleMask(SVOp, false) ||
5405 PPC::isVPKUHUMShuffleMask(SVOp, false) ||
5406 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 ||
5407 PPC::isVMRGLShuffleMask(SVOp, 1, false) ||
5408 PPC::isVMRGLShuffleMask(SVOp, 2, false) ||
5409 PPC::isVMRGLShuffleMask(SVOp, 4, false) ||
5410 PPC::isVMRGHShuffleMask(SVOp, 1, false) ||
5411 PPC::isVMRGHShuffleMask(SVOp, 2, false) ||
5412 PPC::isVMRGHShuffleMask(SVOp, 4, false))
5415 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
5416 // perfect shuffle table to emit an optimal matching sequence.
5417 ArrayRef<int> PermMask = SVOp->getMask();
5419 unsigned PFIndexes[4];
5420 bool isFourElementShuffle = true;
5421 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
5422 unsigned EltNo = 8; // Start out undef.
5423 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
5424 if (PermMask[i*4+j] < 0)
5425 continue; // Undef, ignore it.
5427 unsigned ByteSource = PermMask[i*4+j];
5428 if ((ByteSource & 3) != j) {
5429 isFourElementShuffle = false;
5434 EltNo = ByteSource/4;
5435 } else if (EltNo != ByteSource/4) {
5436 isFourElementShuffle = false;
5440 PFIndexes[i] = EltNo;
5443 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
5444 // perfect shuffle vector to determine if it is cost effective to do this as
5445 // discrete instructions, or whether we should use a vperm.
5446 if (isFourElementShuffle) {
5447 // Compute the index in the perfect shuffle table.
5448 unsigned PFTableIndex =
5449 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5451 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5452 unsigned Cost = (PFEntry >> 30);
5454 // Determining when to avoid vperm is tricky. Many things affect the cost
5455 // of vperm, particularly how many times the perm mask needs to be computed.
5456 // For example, if the perm mask can be hoisted out of a loop or is already
5457 // used (perhaps because there are multiple permutes with the same shuffle
5458 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
5459 // the loop requires an extra register.
5461 // As a compromise, we only emit discrete instructions if the shuffle can be
5462 // generated in 3 or fewer operations. When we have loop information
5463 // available, if this block is within a loop, we should avoid using vperm
5464 // for 3-operation perms and use a constant pool load instead.
5466 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5469 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
5470 // vector that will get spilled to the constant pool.
5471 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
5473 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
5474 // that it is in input element units, not in bytes. Convert now.
5475 EVT EltVT = V1.getValueType().getVectorElementType();
5476 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
5478 SmallVector<SDValue, 16> ResultMask;
5479 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
5480 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
5482 for (unsigned j = 0; j != BytesPerElement; ++j)
5483 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
5487 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
5488 &ResultMask[0], ResultMask.size());
5489 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
5492 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
5493 /// altivec comparison. If it is, return true and fill in Opc/isDot with
5494 /// information about the intrinsic.
5495 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
5497 unsigned IntrinsicID =
5498 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
5501 switch (IntrinsicID) {
5502 default: return false;
5503 // Comparison predicates.
5504 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
5505 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
5506 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
5507 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
5508 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
5509 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
5510 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
5511 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
5512 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
5513 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
5514 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
5515 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
5516 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
5518 // Normal Comparisons.
5519 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
5520 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
5521 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
5522 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
5523 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
5524 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
5525 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
5526 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
5527 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
5528 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
5529 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
5530 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
5531 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
5536 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
5537 /// lower, do it, otherwise return null.
5538 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
5539 SelectionDAG &DAG) const {
5540 // If this is a lowered altivec predicate compare, CompareOpc is set to the
5541 // opcode number of the comparison.
5542 DebugLoc dl = Op.getDebugLoc();
5545 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
5546 return SDValue(); // Don't custom lower most intrinsics.
5548 // If this is a non-dot comparison, make the VCMP node and we are done.
5550 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
5551 Op.getOperand(1), Op.getOperand(2),
5552 DAG.getConstant(CompareOpc, MVT::i32));
5553 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
5556 // Create the PPCISD altivec 'dot' comparison node.
5558 Op.getOperand(2), // LHS
5559 Op.getOperand(3), // RHS
5560 DAG.getConstant(CompareOpc, MVT::i32)
5562 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
5563 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
5565 // Now that we have the comparison, emit a copy from the CR to a GPR.
5566 // This is flagged to the above dot comparison.
5567 SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32,
5568 DAG.getRegister(PPC::CR6, MVT::i32),
5569 CompNode.getValue(1));
5571 // Unpack the result based on how the target uses it.
5572 unsigned BitNo; // Bit # of CR6.
5573 bool InvertBit; // Invert result?
5574 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
5575 default: // Can't happen, don't crash on invalid number though.
5576 case 0: // Return the value of the EQ bit of CR6.
5577 BitNo = 0; InvertBit = false;
5579 case 1: // Return the inverted value of the EQ bit of CR6.
5580 BitNo = 0; InvertBit = true;
5582 case 2: // Return the value of the LT bit of CR6.
5583 BitNo = 2; InvertBit = false;
5585 case 3: // Return the inverted value of the LT bit of CR6.
5586 BitNo = 2; InvertBit = true;
5590 // Shift the bit into the low position.
5591 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
5592 DAG.getConstant(8-(3-BitNo), MVT::i32));
5594 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
5595 DAG.getConstant(1, MVT::i32));
5597 // If we are supposed to, toggle the bit.
5599 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
5600 DAG.getConstant(1, MVT::i32));
5604 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
5605 SelectionDAG &DAG) const {
5606 DebugLoc dl = Op.getDebugLoc();
5607 // Create a stack slot that is 16-byte aligned.
5608 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
5609 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
5610 EVT PtrVT = getPointerTy();
5611 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5613 // Store the input value into Value#0 of the stack slot.
5614 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
5615 Op.getOperand(0), FIdx, MachinePointerInfo(),
5618 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
5619 false, false, false, 0);
5622 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
5623 DebugLoc dl = Op.getDebugLoc();
5624 if (Op.getValueType() == MVT::v4i32) {
5625 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5627 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
5628 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
5630 SDValue RHSSwap = // = vrlw RHS, 16
5631 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
5633 // Shrinkify inputs to v8i16.
5634 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
5635 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
5636 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
5638 // Low parts multiplied together, generating 32-bit results (we ignore the
5640 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
5641 LHS, RHS, DAG, dl, MVT::v4i32);
5643 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
5644 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
5645 // Shift the high parts up 16 bits.
5646 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
5648 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
5649 } else if (Op.getValueType() == MVT::v8i16) {
5650 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5652 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
5654 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
5655 LHS, RHS, Zero, DAG, dl);
5656 } else if (Op.getValueType() == MVT::v16i8) {
5657 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5659 // Multiply the even 8-bit parts, producing 16-bit sums.
5660 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
5661 LHS, RHS, DAG, dl, MVT::v8i16);
5662 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
5664 // Multiply the odd 8-bit parts, producing 16-bit sums.
5665 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
5666 LHS, RHS, DAG, dl, MVT::v8i16);
5667 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
5669 // Merge the results together.
5671 for (unsigned i = 0; i != 8; ++i) {
5673 Ops[i*2+1] = 2*i+1+16;
5675 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
5677 llvm_unreachable("Unknown mul to lower!");
5681 /// LowerOperation - Provide custom lowering hooks for some operations.
5683 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
5684 switch (Op.getOpcode()) {
5685 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
5686 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
5687 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
5688 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
5689 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
5690 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
5691 case ISD::SETCC: return LowerSETCC(Op, DAG);
5692 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
5693 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
5695 return LowerVASTART(Op, DAG, PPCSubTarget);
5698 return LowerVAARG(Op, DAG, PPCSubTarget);
5700 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
5701 case ISD::DYNAMIC_STACKALLOC:
5702 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
5704 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
5705 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
5707 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
5708 case ISD::FP_TO_UINT:
5709 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
5711 case ISD::UINT_TO_FP:
5712 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
5713 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
5715 // Lower 64-bit shifts.
5716 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
5717 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
5718 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
5720 // Vector-related lowering.
5721 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
5722 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
5723 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
5724 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
5725 case ISD::MUL: return LowerMUL(Op, DAG);
5727 // Frame & Return address.
5728 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
5729 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
5733 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
5734 SmallVectorImpl<SDValue>&Results,
5735 SelectionDAG &DAG) const {
5736 const TargetMachine &TM = getTargetMachine();
5737 DebugLoc dl = N->getDebugLoc();
5738 switch (N->getOpcode()) {
5740 llvm_unreachable("Do not know how to custom type legalize this operation!");
5742 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
5743 || TM.getSubtarget<PPCSubtarget>().isPPC64())
5746 EVT VT = N->getValueType(0);
5748 if (VT == MVT::i64) {
5749 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, PPCSubTarget);
5751 Results.push_back(NewNode);
5752 Results.push_back(NewNode.getValue(1));
5756 case ISD::FP_ROUND_INREG: {
5757 assert(N->getValueType(0) == MVT::ppcf128);
5758 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
5759 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
5760 MVT::f64, N->getOperand(0),
5761 DAG.getIntPtrConstant(0));
5762 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
5763 MVT::f64, N->getOperand(0),
5764 DAG.getIntPtrConstant(1));
5766 // Add the two halves of the long double in round-to-zero mode.
5767 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
5769 // We know the low half is about to be thrown away, so just use something
5771 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
5775 case ISD::FP_TO_SINT:
5776 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
5782 //===----------------------------------------------------------------------===//
5783 // Other Lowering Code
5784 //===----------------------------------------------------------------------===//
5787 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
5788 bool is64bit, unsigned BinOpcode) const {
5789 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
5790 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5792 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5793 MachineFunction *F = BB->getParent();
5794 MachineFunction::iterator It = BB;
5797 unsigned dest = MI->getOperand(0).getReg();
5798 unsigned ptrA = MI->getOperand(1).getReg();
5799 unsigned ptrB = MI->getOperand(2).getReg();
5800 unsigned incr = MI->getOperand(3).getReg();
5801 DebugLoc dl = MI->getDebugLoc();
5803 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
5804 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
5805 F->insert(It, loopMBB);
5806 F->insert(It, exitMBB);
5807 exitMBB->splice(exitMBB->begin(), BB,
5808 llvm::next(MachineBasicBlock::iterator(MI)),
5810 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5812 MachineRegisterInfo &RegInfo = F->getRegInfo();
5813 unsigned TmpReg = (!BinOpcode) ? incr :
5814 RegInfo.createVirtualRegister(
5815 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
5816 (const TargetRegisterClass *) &PPC::GPRCRegClass);
5820 // fallthrough --> loopMBB
5821 BB->addSuccessor(loopMBB);
5824 // l[wd]arx dest, ptr
5825 // add r0, dest, incr
5826 // st[wd]cx. r0, ptr
5828 // fallthrough --> exitMBB
5830 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
5831 .addReg(ptrA).addReg(ptrB);
5833 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
5834 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
5835 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
5836 BuildMI(BB, dl, TII->get(PPC::BCC))
5837 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
5838 BB->addSuccessor(loopMBB);
5839 BB->addSuccessor(exitMBB);
5848 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
5849 MachineBasicBlock *BB,
5850 bool is8bit, // operation
5851 unsigned BinOpcode) const {
5852 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
5853 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5854 // In 64 bit mode we have to use 64 bits for addresses, even though the
5855 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
5856 // registers without caring whether they're 32 or 64, but here we're
5857 // doing actual arithmetic on the addresses.
5858 bool is64bit = PPCSubTarget.isPPC64();
5859 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
5861 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5862 MachineFunction *F = BB->getParent();
5863 MachineFunction::iterator It = BB;
5866 unsigned dest = MI->getOperand(0).getReg();
5867 unsigned ptrA = MI->getOperand(1).getReg();
5868 unsigned ptrB = MI->getOperand(2).getReg();
5869 unsigned incr = MI->getOperand(3).getReg();
5870 DebugLoc dl = MI->getDebugLoc();
5872 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
5873 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
5874 F->insert(It, loopMBB);
5875 F->insert(It, exitMBB);
5876 exitMBB->splice(exitMBB->begin(), BB,
5877 llvm::next(MachineBasicBlock::iterator(MI)),
5879 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5881 MachineRegisterInfo &RegInfo = F->getRegInfo();
5882 const TargetRegisterClass *RC =
5883 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
5884 (const TargetRegisterClass *) &PPC::GPRCRegClass;
5885 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
5886 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
5887 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
5888 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
5889 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
5890 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
5891 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
5892 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
5893 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
5894 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
5895 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
5897 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
5901 // fallthrough --> loopMBB
5902 BB->addSuccessor(loopMBB);
5904 // The 4-byte load must be aligned, while a char or short may be
5905 // anywhere in the word. Hence all this nasty bookkeeping code.
5906 // add ptr1, ptrA, ptrB [copy if ptrA==0]
5907 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
5908 // xori shift, shift1, 24 [16]
5909 // rlwinm ptr, ptr1, 0, 0, 29
5910 // slw incr2, incr, shift
5911 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
5912 // slw mask, mask2, shift
5914 // lwarx tmpDest, ptr
5915 // add tmp, tmpDest, incr2
5916 // andc tmp2, tmpDest, mask
5917 // and tmp3, tmp, mask
5918 // or tmp4, tmp3, tmp2
5921 // fallthrough --> exitMBB
5922 // srw dest, tmpDest, shift
5923 if (ptrA != ZeroReg) {
5924 Ptr1Reg = RegInfo.createVirtualRegister(RC);
5925 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
5926 .addReg(ptrA).addReg(ptrB);
5930 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
5931 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
5932 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
5933 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
5935 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
5936 .addReg(Ptr1Reg).addImm(0).addImm(61);
5938 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
5939 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
5940 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
5941 .addReg(incr).addReg(ShiftReg);
5943 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
5945 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
5946 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
5948 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
5949 .addReg(Mask2Reg).addReg(ShiftReg);
5952 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
5953 .addReg(ZeroReg).addReg(PtrReg);
5955 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
5956 .addReg(Incr2Reg).addReg(TmpDestReg);
5957 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
5958 .addReg(TmpDestReg).addReg(MaskReg);
5959 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
5960 .addReg(TmpReg).addReg(MaskReg);
5961 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
5962 .addReg(Tmp3Reg).addReg(Tmp2Reg);
5963 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
5964 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
5965 BuildMI(BB, dl, TII->get(PPC::BCC))
5966 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
5967 BB->addSuccessor(loopMBB);
5968 BB->addSuccessor(exitMBB);
5973 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
5978 llvm::MachineBasicBlock*
5979 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
5980 MachineBasicBlock *MBB) const {
5981 DebugLoc DL = MI->getDebugLoc();
5982 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5984 MachineFunction *MF = MBB->getParent();
5985 MachineRegisterInfo &MRI = MF->getRegInfo();
5987 const BasicBlock *BB = MBB->getBasicBlock();
5988 MachineFunction::iterator I = MBB;
5992 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
5993 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
5995 unsigned DstReg = MI->getOperand(0).getReg();
5996 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
5997 assert(RC->hasType(MVT::i32) && "Invalid destination!");
5998 unsigned mainDstReg = MRI.createVirtualRegister(RC);
5999 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
6001 MVT PVT = getPointerTy();
6002 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6003 "Invalid Pointer Size!");
6004 // For v = setjmp(buf), we generate
6007 // SjLjSetup mainMBB
6013 // buf[LabelOffset] = LR
6017 // v = phi(main, restore)
6020 MachineBasicBlock *thisMBB = MBB;
6021 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
6022 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
6023 MF->insert(I, mainMBB);
6024 MF->insert(I, sinkMBB);
6026 MachineInstrBuilder MIB;
6028 // Transfer the remainder of BB and its successor edges to sinkMBB.
6029 sinkMBB->splice(sinkMBB->begin(), MBB,
6030 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
6031 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
6033 // Note that the structure of the jmp_buf used here is not compatible
6034 // with that used by libc, and is not designed to be. Specifically, it
6035 // stores only those 'reserved' registers that LLVM does not otherwise
6036 // understand how to spill. Also, by convention, by the time this
6037 // intrinsic is called, Clang has already stored the frame address in the
6038 // first slot of the buffer and stack address in the third. Following the
6039 // X86 target code, we'll store the jump address in the second slot. We also
6040 // need to save the TOC pointer (R2) to handle jumps between shared
6041 // libraries, and that will be stored in the fourth slot. The thread
6042 // identifier (R13) is not affected.
6045 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6046 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6048 // Prepare IP either in reg.
6049 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
6050 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
6051 unsigned BufReg = MI->getOperand(1).getReg();
6053 if (PPCSubTarget.isPPC64() && PPCSubTarget.isSVR4ABI()) {
6054 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
6056 .addImm(TOCOffset / 4)
6059 MIB.setMemRefs(MMOBegin, MMOEnd);
6063 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCL)).addMBB(mainMBB);
6064 MIB.addRegMask(PPCRegInfo->getNoPreservedMask());
6066 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
6068 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
6070 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
6072 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
6073 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
6077 MIB = BuildMI(mainMBB, DL,
6078 TII->get(PPCSubTarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
6081 if (PPCSubTarget.isPPC64()) {
6082 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
6084 .addImm(LabelOffset / 4)
6087 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
6089 .addImm(LabelOffset)
6093 MIB.setMemRefs(MMOBegin, MMOEnd);
6095 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
6096 mainMBB->addSuccessor(sinkMBB);
6099 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
6100 TII->get(PPC::PHI), DstReg)
6101 .addReg(mainDstReg).addMBB(mainMBB)
6102 .addReg(restoreDstReg).addMBB(thisMBB);
6104 MI->eraseFromParent();
6109 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
6110 MachineBasicBlock *MBB) const {
6111 DebugLoc DL = MI->getDebugLoc();
6112 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6114 MachineFunction *MF = MBB->getParent();
6115 MachineRegisterInfo &MRI = MF->getRegInfo();
6118 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6119 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6121 MVT PVT = getPointerTy();
6122 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6123 "Invalid Pointer Size!");
6125 const TargetRegisterClass *RC =
6126 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6127 unsigned Tmp = MRI.createVirtualRegister(RC);
6128 // Since FP is only updated here but NOT referenced, it's treated as GPR.
6129 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6130 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6132 MachineInstrBuilder MIB;
6134 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6135 const int64_t SPOffset = 2 * PVT.getStoreSize();
6136 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6138 unsigned BufReg = MI->getOperand(0).getReg();
6140 // Reload FP (the jumped-to function may not have had a
6141 // frame pointer, and if so, then its r31 will be restored
6143 if (PVT == MVT::i64) {
6144 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
6148 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
6152 MIB.setMemRefs(MMOBegin, MMOEnd);
6155 if (PVT == MVT::i64) {
6156 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
6157 .addImm(LabelOffset / 4)
6160 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
6161 .addImm(LabelOffset)
6164 MIB.setMemRefs(MMOBegin, MMOEnd);
6167 if (PVT == MVT::i64) {
6168 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
6169 .addImm(SPOffset / 4)
6172 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
6176 MIB.setMemRefs(MMOBegin, MMOEnd);
6178 // FIXME: When we also support base pointers, that register must also be
6182 if (PVT == MVT::i64 && PPCSubTarget.isSVR4ABI()) {
6183 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
6184 .addImm(TOCOffset / 4)
6187 MIB.setMemRefs(MMOBegin, MMOEnd);
6191 BuildMI(*MBB, MI, DL,
6192 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
6193 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
6195 MI->eraseFromParent();
6200 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6201 MachineBasicBlock *BB) const {
6202 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
6203 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
6204 return emitEHSjLjSetJmp(MI, BB);
6205 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
6206 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
6207 return emitEHSjLjLongJmp(MI, BB);
6210 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6212 // To "insert" these instructions we actually have to insert their
6213 // control-flow patterns.
6214 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6215 MachineFunction::iterator It = BB;
6218 MachineFunction *F = BB->getParent();
6220 if (PPCSubTarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6221 MI->getOpcode() == PPC::SELECT_CC_I8)) {
6222 unsigned OpCode = MI->getOpcode() == PPC::SELECT_CC_I8 ?
6223 PPC::ISEL8 : PPC::ISEL;
6224 unsigned SelectPred = MI->getOperand(4).getImm();
6225 DebugLoc dl = MI->getDebugLoc();
6229 switch (SelectPred) {
6230 default: llvm_unreachable("invalid predicate for isel");
6231 case PPC::PRED_EQ: SubIdx = PPC::sub_eq; SwapOps = false; break;
6232 case PPC::PRED_NE: SubIdx = PPC::sub_eq; SwapOps = true; break;
6233 case PPC::PRED_LT: SubIdx = PPC::sub_lt; SwapOps = false; break;
6234 case PPC::PRED_GE: SubIdx = PPC::sub_lt; SwapOps = true; break;
6235 case PPC::PRED_GT: SubIdx = PPC::sub_gt; SwapOps = false; break;
6236 case PPC::PRED_LE: SubIdx = PPC::sub_gt; SwapOps = true; break;
6237 case PPC::PRED_UN: SubIdx = PPC::sub_un; SwapOps = false; break;
6238 case PPC::PRED_NU: SubIdx = PPC::sub_un; SwapOps = true; break;
6241 BuildMI(*BB, MI, dl, TII->get(OpCode), MI->getOperand(0).getReg())
6242 .addReg(MI->getOperand(SwapOps? 3 : 2).getReg())
6243 .addReg(MI->getOperand(SwapOps? 2 : 3).getReg())
6244 .addReg(MI->getOperand(1).getReg(), 0, SubIdx);
6245 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6246 MI->getOpcode() == PPC::SELECT_CC_I8 ||
6247 MI->getOpcode() == PPC::SELECT_CC_F4 ||
6248 MI->getOpcode() == PPC::SELECT_CC_F8 ||
6249 MI->getOpcode() == PPC::SELECT_CC_VRRC) {
6252 // The incoming instruction knows the destination vreg to set, the
6253 // condition code register to branch on, the true/false values to
6254 // select between, and a branch opcode to use.
6259 // cmpTY ccX, r1, r2
6261 // fallthrough --> copy0MBB
6262 MachineBasicBlock *thisMBB = BB;
6263 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
6264 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
6265 unsigned SelectPred = MI->getOperand(4).getImm();
6266 DebugLoc dl = MI->getDebugLoc();
6267 F->insert(It, copy0MBB);
6268 F->insert(It, sinkMBB);
6270 // Transfer the remainder of BB and its successor edges to sinkMBB.
6271 sinkMBB->splice(sinkMBB->begin(), BB,
6272 llvm::next(MachineBasicBlock::iterator(MI)),
6274 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
6276 // Next, add the true and fallthrough blocks as its successors.
6277 BB->addSuccessor(copy0MBB);
6278 BB->addSuccessor(sinkMBB);
6280 BuildMI(BB, dl, TII->get(PPC::BCC))
6281 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
6284 // %FalseValue = ...
6285 // # fallthrough to sinkMBB
6288 // Update machine-CFG edges
6289 BB->addSuccessor(sinkMBB);
6292 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
6295 BuildMI(*BB, BB->begin(), dl,
6296 TII->get(PPC::PHI), MI->getOperand(0).getReg())
6297 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
6298 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
6300 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
6301 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
6302 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
6303 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
6304 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
6305 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
6306 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
6307 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
6309 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
6310 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
6311 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
6312 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
6313 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
6314 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
6315 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
6316 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
6318 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
6319 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
6320 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
6321 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
6322 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
6323 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
6324 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
6325 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
6327 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
6328 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
6329 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
6330 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
6331 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
6332 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
6333 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
6334 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
6336 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
6337 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
6338 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
6339 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
6340 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
6341 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
6342 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
6343 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
6345 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
6346 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
6347 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
6348 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
6349 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
6350 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
6351 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
6352 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
6354 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
6355 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
6356 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
6357 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
6358 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
6359 BB = EmitAtomicBinary(MI, BB, false, 0);
6360 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
6361 BB = EmitAtomicBinary(MI, BB, true, 0);
6363 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
6364 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
6365 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
6367 unsigned dest = MI->getOperand(0).getReg();
6368 unsigned ptrA = MI->getOperand(1).getReg();
6369 unsigned ptrB = MI->getOperand(2).getReg();
6370 unsigned oldval = MI->getOperand(3).getReg();
6371 unsigned newval = MI->getOperand(4).getReg();
6372 DebugLoc dl = MI->getDebugLoc();
6374 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6375 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6376 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6377 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6378 F->insert(It, loop1MBB);
6379 F->insert(It, loop2MBB);
6380 F->insert(It, midMBB);
6381 F->insert(It, exitMBB);
6382 exitMBB->splice(exitMBB->begin(), BB,
6383 llvm::next(MachineBasicBlock::iterator(MI)),
6385 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6389 // fallthrough --> loopMBB
6390 BB->addSuccessor(loop1MBB);
6393 // l[wd]arx dest, ptr
6394 // cmp[wd] dest, oldval
6397 // st[wd]cx. newval, ptr
6401 // st[wd]cx. dest, ptr
6404 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6405 .addReg(ptrA).addReg(ptrB);
6406 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
6407 .addReg(oldval).addReg(dest);
6408 BuildMI(BB, dl, TII->get(PPC::BCC))
6409 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6410 BB->addSuccessor(loop2MBB);
6411 BB->addSuccessor(midMBB);
6414 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6415 .addReg(newval).addReg(ptrA).addReg(ptrB);
6416 BuildMI(BB, dl, TII->get(PPC::BCC))
6417 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6418 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6419 BB->addSuccessor(loop1MBB);
6420 BB->addSuccessor(exitMBB);
6423 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6424 .addReg(dest).addReg(ptrA).addReg(ptrB);
6425 BB->addSuccessor(exitMBB);
6430 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
6431 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
6432 // We must use 64-bit registers for addresses when targeting 64-bit,
6433 // since we're actually doing arithmetic on them. Other registers
6435 bool is64bit = PPCSubTarget.isPPC64();
6436 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
6438 unsigned dest = MI->getOperand(0).getReg();
6439 unsigned ptrA = MI->getOperand(1).getReg();
6440 unsigned ptrB = MI->getOperand(2).getReg();
6441 unsigned oldval = MI->getOperand(3).getReg();
6442 unsigned newval = MI->getOperand(4).getReg();
6443 DebugLoc dl = MI->getDebugLoc();
6445 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6446 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6447 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6448 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6449 F->insert(It, loop1MBB);
6450 F->insert(It, loop2MBB);
6451 F->insert(It, midMBB);
6452 F->insert(It, exitMBB);
6453 exitMBB->splice(exitMBB->begin(), BB,
6454 llvm::next(MachineBasicBlock::iterator(MI)),
6456 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6458 MachineRegisterInfo &RegInfo = F->getRegInfo();
6459 const TargetRegisterClass *RC =
6460 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6461 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6462 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6463 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6464 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6465 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
6466 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
6467 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
6468 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
6469 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6470 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6471 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6472 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6473 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6474 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6476 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
6477 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6480 // fallthrough --> loopMBB
6481 BB->addSuccessor(loop1MBB);
6483 // The 4-byte load must be aligned, while a char or short may be
6484 // anywhere in the word. Hence all this nasty bookkeeping code.
6485 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6486 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6487 // xori shift, shift1, 24 [16]
6488 // rlwinm ptr, ptr1, 0, 0, 29
6489 // slw newval2, newval, shift
6490 // slw oldval2, oldval,shift
6491 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6492 // slw mask, mask2, shift
6493 // and newval3, newval2, mask
6494 // and oldval3, oldval2, mask
6496 // lwarx tmpDest, ptr
6497 // and tmp, tmpDest, mask
6498 // cmpw tmp, oldval3
6501 // andc tmp2, tmpDest, mask
6502 // or tmp4, tmp2, newval3
6507 // stwcx. tmpDest, ptr
6509 // srw dest, tmpDest, shift
6510 if (ptrA != ZeroReg) {
6511 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6512 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6513 .addReg(ptrA).addReg(ptrB);
6517 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6518 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6519 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6520 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6522 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6523 .addReg(Ptr1Reg).addImm(0).addImm(61);
6525 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6526 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6527 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
6528 .addReg(newval).addReg(ShiftReg);
6529 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
6530 .addReg(oldval).addReg(ShiftReg);
6532 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6534 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6535 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
6536 .addReg(Mask3Reg).addImm(65535);
6538 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6539 .addReg(Mask2Reg).addReg(ShiftReg);
6540 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
6541 .addReg(NewVal2Reg).addReg(MaskReg);
6542 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
6543 .addReg(OldVal2Reg).addReg(MaskReg);
6546 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6547 .addReg(ZeroReg).addReg(PtrReg);
6548 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
6549 .addReg(TmpDestReg).addReg(MaskReg);
6550 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
6551 .addReg(TmpReg).addReg(OldVal3Reg);
6552 BuildMI(BB, dl, TII->get(PPC::BCC))
6553 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6554 BB->addSuccessor(loop2MBB);
6555 BB->addSuccessor(midMBB);
6558 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
6559 .addReg(TmpDestReg).addReg(MaskReg);
6560 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
6561 .addReg(Tmp2Reg).addReg(NewVal3Reg);
6562 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
6563 .addReg(ZeroReg).addReg(PtrReg);
6564 BuildMI(BB, dl, TII->get(PPC::BCC))
6565 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6566 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6567 BB->addSuccessor(loop1MBB);
6568 BB->addSuccessor(exitMBB);
6571 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
6572 .addReg(ZeroReg).addReg(PtrReg);
6573 BB->addSuccessor(exitMBB);
6578 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
6580 } else if (MI->getOpcode() == PPC::FADDrtz) {
6581 // This pseudo performs an FADD with rounding mode temporarily forced
6582 // to round-to-zero. We emit this via custom inserter since the FPSCR
6583 // is not modeled at the SelectionDAG level.
6584 unsigned Dest = MI->getOperand(0).getReg();
6585 unsigned Src1 = MI->getOperand(1).getReg();
6586 unsigned Src2 = MI->getOperand(2).getReg();
6587 DebugLoc dl = MI->getDebugLoc();
6589 MachineRegisterInfo &RegInfo = F->getRegInfo();
6590 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
6592 // Save FPSCR value.
6593 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
6595 // Set rounding mode to round-to-zero.
6596 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
6597 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
6599 // Perform addition.
6600 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
6602 // Restore FPSCR value.
6603 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg);
6604 } else if (MI->getOpcode() == PPC::FRINDrint ||
6605 MI->getOpcode() == PPC::FRINSrint) {
6606 bool isf32 = MI->getOpcode() == PPC::FRINSrint;
6607 unsigned Dest = MI->getOperand(0).getReg();
6608 unsigned Src = MI->getOperand(1).getReg();
6609 DebugLoc dl = MI->getDebugLoc();
6611 MachineRegisterInfo &RegInfo = F->getRegInfo();
6612 unsigned CRReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
6614 // Perform the rounding.
6615 BuildMI(*BB, MI, dl, TII->get(isf32 ? PPC::FRINS : PPC::FRIND), Dest)
6618 // Compare the results.
6619 BuildMI(*BB, MI, dl, TII->get(isf32 ? PPC::FCMPUS : PPC::FCMPUD), CRReg)
6620 .addReg(Dest).addReg(Src);
6622 // If the results were not equal, then set the FPSCR XX bit.
6623 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6624 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6625 F->insert(It, midMBB);
6626 F->insert(It, exitMBB);
6627 exitMBB->splice(exitMBB->begin(), BB,
6628 llvm::next(MachineBasicBlock::iterator(MI)),
6630 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6632 BuildMI(*BB, MI, dl, TII->get(PPC::BCC))
6633 .addImm(PPC::PRED_EQ).addReg(CRReg).addMBB(exitMBB);
6635 BB->addSuccessor(midMBB);
6636 BB->addSuccessor(exitMBB);
6640 // Set the FPSCR XX bit (FE_INEXACT). Note that we cannot just set
6641 // the FI bit here because that will not automatically set XX also,
6642 // and XX is what libm interprets as the FE_INEXACT flag.
6643 BuildMI(BB, dl, TII->get(PPC::MTFSB1)).addImm(/* 38 - 32 = */ 6);
6644 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6646 BB->addSuccessor(exitMBB);
6650 llvm_unreachable("Unexpected instr type to insert");
6653 MI->eraseFromParent(); // The pseudo instruction is gone now.
6657 //===----------------------------------------------------------------------===//
6658 // Target Optimization Hooks
6659 //===----------------------------------------------------------------------===//
6661 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
6662 DAGCombinerInfo &DCI) const {
6663 const TargetMachine &TM = getTargetMachine();
6664 SelectionDAG &DAG = DCI.DAG;
6665 DebugLoc dl = N->getDebugLoc();
6666 switch (N->getOpcode()) {
6669 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6670 if (C->isNullValue()) // 0 << V -> 0.
6671 return N->getOperand(0);
6675 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6676 if (C->isNullValue()) // 0 >>u V -> 0.
6677 return N->getOperand(0);
6681 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6682 if (C->isNullValue() || // 0 >>s V -> 0.
6683 C->isAllOnesValue()) // -1 >>s V -> -1.
6684 return N->getOperand(0);
6688 case ISD::SINT_TO_FP:
6689 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
6690 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
6691 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
6692 // We allow the src/dst to be either f32/f64, but the intermediate
6693 // type must be i64.
6694 if (N->getOperand(0).getValueType() == MVT::i64 &&
6695 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
6696 SDValue Val = N->getOperand(0).getOperand(0);
6697 if (Val.getValueType() == MVT::f32) {
6698 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
6699 DCI.AddToWorklist(Val.getNode());
6702 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
6703 DCI.AddToWorklist(Val.getNode());
6704 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
6705 DCI.AddToWorklist(Val.getNode());
6706 if (N->getValueType(0) == MVT::f32) {
6707 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
6708 DAG.getIntPtrConstant(0));
6709 DCI.AddToWorklist(Val.getNode());
6712 } else if (N->getOperand(0).getValueType() == MVT::i32) {
6713 // If the intermediate type is i32, we can avoid the load/store here
6720 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
6721 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
6722 !cast<StoreSDNode>(N)->isTruncatingStore() &&
6723 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
6724 N->getOperand(1).getValueType() == MVT::i32 &&
6725 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
6726 SDValue Val = N->getOperand(1).getOperand(0);
6727 if (Val.getValueType() == MVT::f32) {
6728 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
6729 DCI.AddToWorklist(Val.getNode());
6731 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
6732 DCI.AddToWorklist(Val.getNode());
6735 N->getOperand(0), Val, N->getOperand(2),
6736 DAG.getValueType(N->getOperand(1).getValueType())
6739 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
6740 DAG.getVTList(MVT::Other), Ops, array_lengthof(Ops),
6741 cast<StoreSDNode>(N)->getMemoryVT(),
6742 cast<StoreSDNode>(N)->getMemOperand());
6743 DCI.AddToWorklist(Val.getNode());
6747 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
6748 if (cast<StoreSDNode>(N)->isUnindexed() &&
6749 N->getOperand(1).getOpcode() == ISD::BSWAP &&
6750 N->getOperand(1).getNode()->hasOneUse() &&
6751 (N->getOperand(1).getValueType() == MVT::i32 ||
6752 N->getOperand(1).getValueType() == MVT::i16 ||
6753 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
6754 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
6755 N->getOperand(1).getValueType() == MVT::i64))) {
6756 SDValue BSwapOp = N->getOperand(1).getOperand(0);
6757 // Do an any-extend to 32-bits if this is a half-word input.
6758 if (BSwapOp.getValueType() == MVT::i16)
6759 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
6762 N->getOperand(0), BSwapOp, N->getOperand(2),
6763 DAG.getValueType(N->getOperand(1).getValueType())
6766 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
6767 Ops, array_lengthof(Ops),
6768 cast<StoreSDNode>(N)->getMemoryVT(),
6769 cast<StoreSDNode>(N)->getMemOperand());
6773 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
6774 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
6775 N->getOperand(0).hasOneUse() &&
6776 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
6777 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
6778 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
6779 N->getValueType(0) == MVT::i64))) {
6780 SDValue Load = N->getOperand(0);
6781 LoadSDNode *LD = cast<LoadSDNode>(Load);
6782 // Create the byte-swapping load.
6784 LD->getChain(), // Chain
6785 LD->getBasePtr(), // Ptr
6786 DAG.getValueType(N->getValueType(0)) // VT
6789 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
6790 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
6791 MVT::i64 : MVT::i32, MVT::Other),
6792 Ops, 3, LD->getMemoryVT(), LD->getMemOperand());
6794 // If this is an i16 load, insert the truncate.
6795 SDValue ResVal = BSLoad;
6796 if (N->getValueType(0) == MVT::i16)
6797 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
6799 // First, combine the bswap away. This makes the value produced by the
6801 DCI.CombineTo(N, ResVal);
6803 // Next, combine the load away, we give it a bogus result value but a real
6804 // chain result. The result value is dead because the bswap is dead.
6805 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
6807 // Return N so it doesn't get rechecked!
6808 return SDValue(N, 0);
6812 case PPCISD::VCMP: {
6813 // If a VCMPo node already exists with exactly the same operands as this
6814 // node, use its result instead of this node (VCMPo computes both a CR6 and
6815 // a normal output).
6817 if (!N->getOperand(0).hasOneUse() &&
6818 !N->getOperand(1).hasOneUse() &&
6819 !N->getOperand(2).hasOneUse()) {
6821 // Scan all of the users of the LHS, looking for VCMPo's that match.
6822 SDNode *VCMPoNode = 0;
6824 SDNode *LHSN = N->getOperand(0).getNode();
6825 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
6827 if (UI->getOpcode() == PPCISD::VCMPo &&
6828 UI->getOperand(1) == N->getOperand(1) &&
6829 UI->getOperand(2) == N->getOperand(2) &&
6830 UI->getOperand(0) == N->getOperand(0)) {
6835 // If there is no VCMPo node, or if the flag value has a single use, don't
6837 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
6840 // Look at the (necessarily single) use of the flag value. If it has a
6841 // chain, this transformation is more complex. Note that multiple things
6842 // could use the value result, which we should ignore.
6843 SDNode *FlagUser = 0;
6844 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
6845 FlagUser == 0; ++UI) {
6846 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
6848 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
6849 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
6856 // If the user is a MFCR instruction, we know this is safe. Otherwise we
6857 // give up for right now.
6858 if (FlagUser->getOpcode() == PPCISD::MFCR)
6859 return SDValue(VCMPoNode, 0);
6864 // If this is a branch on an altivec predicate comparison, lower this so
6865 // that we don't have to do a MFCR: instead, branch directly on CR6. This
6866 // lowering is done pre-legalize, because the legalizer lowers the predicate
6867 // compare down to code that is difficult to reassemble.
6868 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
6869 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
6873 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
6874 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
6875 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
6876 assert(isDot && "Can't compare against a vector result!");
6878 // If this is a comparison against something other than 0/1, then we know
6879 // that the condition is never/always true.
6880 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
6881 if (Val != 0 && Val != 1) {
6882 if (CC == ISD::SETEQ) // Cond never true, remove branch.
6883 return N->getOperand(0);
6884 // Always !=, turn it into an unconditional branch.
6885 return DAG.getNode(ISD::BR, dl, MVT::Other,
6886 N->getOperand(0), N->getOperand(4));
6889 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
6891 // Create the PPCISD altivec 'dot' comparison node.
6893 LHS.getOperand(2), // LHS of compare
6894 LHS.getOperand(3), // RHS of compare
6895 DAG.getConstant(CompareOpc, MVT::i32)
6897 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
6898 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
6900 // Unpack the result based on how the target uses it.
6901 PPC::Predicate CompOpc;
6902 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
6903 default: // Can't happen, don't crash on invalid number though.
6904 case 0: // Branch on the value of the EQ bit of CR6.
6905 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
6907 case 1: // Branch on the inverted value of the EQ bit of CR6.
6908 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
6910 case 2: // Branch on the value of the LT bit of CR6.
6911 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
6913 case 3: // Branch on the inverted value of the LT bit of CR6.
6914 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
6918 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
6919 DAG.getConstant(CompOpc, MVT::i32),
6920 DAG.getRegister(PPC::CR6, MVT::i32),
6921 N->getOperand(4), CompNode.getValue(1));
6930 //===----------------------------------------------------------------------===//
6931 // Inline Assembly Support
6932 //===----------------------------------------------------------------------===//
6934 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
6937 const SelectionDAG &DAG,
6938 unsigned Depth) const {
6939 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
6940 switch (Op.getOpcode()) {
6942 case PPCISD::LBRX: {
6943 // lhbrx is known to have the top bits cleared out.
6944 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
6945 KnownZero = 0xFFFF0000;
6948 case ISD::INTRINSIC_WO_CHAIN: {
6949 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
6951 case Intrinsic::ppc_altivec_vcmpbfp_p:
6952 case Intrinsic::ppc_altivec_vcmpeqfp_p:
6953 case Intrinsic::ppc_altivec_vcmpequb_p:
6954 case Intrinsic::ppc_altivec_vcmpequh_p:
6955 case Intrinsic::ppc_altivec_vcmpequw_p:
6956 case Intrinsic::ppc_altivec_vcmpgefp_p:
6957 case Intrinsic::ppc_altivec_vcmpgtfp_p:
6958 case Intrinsic::ppc_altivec_vcmpgtsb_p:
6959 case Intrinsic::ppc_altivec_vcmpgtsh_p:
6960 case Intrinsic::ppc_altivec_vcmpgtsw_p:
6961 case Intrinsic::ppc_altivec_vcmpgtub_p:
6962 case Intrinsic::ppc_altivec_vcmpgtuh_p:
6963 case Intrinsic::ppc_altivec_vcmpgtuw_p:
6964 KnownZero = ~1U; // All bits but the low one are known to be zero.
6972 /// getConstraintType - Given a constraint, return the type of
6973 /// constraint it is for this target.
6974 PPCTargetLowering::ConstraintType
6975 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
6976 if (Constraint.size() == 1) {
6977 switch (Constraint[0]) {
6984 return C_RegisterClass;
6986 // FIXME: While Z does indicate a memory constraint, it specifically
6987 // indicates an r+r address (used in conjunction with the 'y' modifier
6988 // in the replacement string). Currently, we're forcing the base
6989 // register to be r0 in the asm printer (which is interpreted as zero)
6990 // and forming the complete address in the second register. This is
6995 return TargetLowering::getConstraintType(Constraint);
6998 /// Examine constraint type and operand type and determine a weight value.
6999 /// This object must already have been set up with the operand type
7000 /// and the current alternative constraint selected.
7001 TargetLowering::ConstraintWeight
7002 PPCTargetLowering::getSingleConstraintMatchWeight(
7003 AsmOperandInfo &info, const char *constraint) const {
7004 ConstraintWeight weight = CW_Invalid;
7005 Value *CallOperandVal = info.CallOperandVal;
7006 // If we don't have a value, we can't do a match,
7007 // but allow it at the lowest weight.
7008 if (CallOperandVal == NULL)
7010 Type *type = CallOperandVal->getType();
7011 // Look at the constraint type.
7012 switch (*constraint) {
7014 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
7017 if (type->isIntegerTy())
7018 weight = CW_Register;
7021 if (type->isFloatTy())
7022 weight = CW_Register;
7025 if (type->isDoubleTy())
7026 weight = CW_Register;
7029 if (type->isVectorTy())
7030 weight = CW_Register;
7033 weight = CW_Register;
7042 std::pair<unsigned, const TargetRegisterClass*>
7043 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
7045 if (Constraint.size() == 1) {
7046 // GCC RS6000 Constraint Letters
7047 switch (Constraint[0]) {
7049 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
7050 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
7051 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
7053 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
7054 return std::make_pair(0U, &PPC::G8RCRegClass);
7055 return std::make_pair(0U, &PPC::GPRCRegClass);
7057 if (VT == MVT::f32 || VT == MVT::i32)
7058 return std::make_pair(0U, &PPC::F4RCRegClass);
7059 if (VT == MVT::f64 || VT == MVT::i64)
7060 return std::make_pair(0U, &PPC::F8RCRegClass);
7063 return std::make_pair(0U, &PPC::VRRCRegClass);
7065 return std::make_pair(0U, &PPC::CRRCRegClass);
7069 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
7073 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
7074 /// vector. If it is invalid, don't add anything to Ops.
7075 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
7076 std::string &Constraint,
7077 std::vector<SDValue>&Ops,
7078 SelectionDAG &DAG) const {
7079 SDValue Result(0,0);
7081 // Only support length 1 constraints.
7082 if (Constraint.length() > 1) return;
7084 char Letter = Constraint[0];
7095 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
7096 if (!CST) return; // Must be an immediate to match.
7097 unsigned Value = CST->getZExtValue();
7099 default: llvm_unreachable("Unknown constraint letter!");
7100 case 'I': // "I" is a signed 16-bit constant.
7101 if ((short)Value == (int)Value)
7102 Result = DAG.getTargetConstant(Value, Op.getValueType());
7104 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
7105 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
7106 if ((short)Value == 0)
7107 Result = DAG.getTargetConstant(Value, Op.getValueType());
7109 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
7110 if ((Value >> 16) == 0)
7111 Result = DAG.getTargetConstant(Value, Op.getValueType());
7113 case 'M': // "M" is a constant that is greater than 31.
7115 Result = DAG.getTargetConstant(Value, Op.getValueType());
7117 case 'N': // "N" is a positive constant that is an exact power of two.
7118 if ((int)Value > 0 && isPowerOf2_32(Value))
7119 Result = DAG.getTargetConstant(Value, Op.getValueType());
7121 case 'O': // "O" is the constant zero.
7123 Result = DAG.getTargetConstant(Value, Op.getValueType());
7125 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
7126 if ((short)-Value == (int)-Value)
7127 Result = DAG.getTargetConstant(Value, Op.getValueType());
7134 if (Result.getNode()) {
7135 Ops.push_back(Result);
7139 // Handle standard constraint letters.
7140 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
7143 // isLegalAddressingMode - Return true if the addressing mode represented
7144 // by AM is legal for this target, for a load/store of the specified type.
7145 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
7147 // FIXME: PPC does not allow r+i addressing modes for vectors!
7149 // PPC allows a sign-extended 16-bit immediate field.
7150 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
7153 // No global is ever allowed as a base.
7157 // PPC only support r+r,
7159 case 0: // "r+i" or just "i", depending on HasBaseReg.
7162 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
7164 // Otherwise we have r+r or r+i.
7167 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
7169 // Allow 2*r as r+r.
7172 // No other scales are supported.
7179 /// isLegalAddressImmediate - Return true if the integer value can be used
7180 /// as the offset of the target addressing mode for load / store of the
7182 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,Type *Ty) const{
7183 // PPC allows a sign-extended 16-bit immediate field.
7184 return (V > -(1 << 16) && V < (1 << 16)-1);
7187 bool PPCTargetLowering::isLegalAddressImmediate(GlobalValue* GV) const {
7191 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
7192 SelectionDAG &DAG) const {
7193 MachineFunction &MF = DAG.getMachineFunction();
7194 MachineFrameInfo *MFI = MF.getFrameInfo();
7195 MFI->setReturnAddressIsTaken(true);
7197 DebugLoc dl = Op.getDebugLoc();
7198 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7200 // Make sure the function does not optimize away the store of the RA to
7202 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
7203 FuncInfo->setLRStoreRequired();
7204 bool isPPC64 = PPCSubTarget.isPPC64();
7205 bool isDarwinABI = PPCSubTarget.isDarwinABI();
7208 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
7211 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
7212 isPPC64? MVT::i64 : MVT::i32);
7213 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7214 DAG.getNode(ISD::ADD, dl, getPointerTy(),
7216 MachinePointerInfo(), false, false, false, 0);
7219 // Just load the return address off the stack.
7220 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
7221 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7222 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
7225 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
7226 SelectionDAG &DAG) const {
7227 DebugLoc dl = Op.getDebugLoc();
7228 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7230 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
7231 bool isPPC64 = PtrVT == MVT::i64;
7233 MachineFunction &MF = DAG.getMachineFunction();
7234 MachineFrameInfo *MFI = MF.getFrameInfo();
7235 MFI->setFrameAddressIsTaken(true);
7237 // Naked functions never have a frame pointer, and so we use r1. For all
7238 // other functions, this decision must be delayed until during PEI.
7240 if (MF.getFunction()->getAttributes().hasAttribute(
7241 AttributeSet::FunctionIndex, Attribute::Naked))
7242 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
7244 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
7246 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
7249 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
7250 FrameAddr, MachinePointerInfo(), false, false,
7256 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
7257 // The PowerPC target isn't yet aware of offsets.
7261 /// getOptimalMemOpType - Returns the target specific optimal type for load
7262 /// and store operations as a result of memset, memcpy, and memmove
7263 /// lowering. If DstAlign is zero that means it's safe to destination
7264 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
7265 /// means there isn't a need to check it against alignment requirement,
7266 /// probably because the source does not need to be loaded. If 'IsMemset' is
7267 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
7268 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
7269 /// source is constant so it does not need to be loaded.
7270 /// It returns EVT::Other if the type should be determined using generic
7271 /// target-independent logic.
7272 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
7273 unsigned DstAlign, unsigned SrcAlign,
7274 bool IsMemset, bool ZeroMemset,
7276 MachineFunction &MF) const {
7277 if (this->PPCSubTarget.isPPC64()) {
7284 bool PPCTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
7286 if (DisablePPCUnaligned)
7289 // PowerPC supports unaligned memory access for simple non-vector types.
7290 // Although accessing unaligned addresses is not as efficient as accessing
7291 // aligned addresses, it is generally more efficient than manual expansion,
7292 // and generally only traps for software emulation when crossing page
7298 if (VT.getSimpleVT().isVector())
7301 if (VT == MVT::ppcf128)
7310 /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than
7311 /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to
7312 /// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd
7313 /// is expanded to mul + add.
7314 bool PPCTargetLowering::isFMAFasterThanMulAndAdd(EVT VT) const {
7318 switch (VT.getSimpleVT().SimpleTy) {
7330 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
7332 return TargetLowering::getSchedulingPreference(N);