1 //===-- PPC32ISelLowering.cpp - PPC32 DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPC32ISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPC32ISelLowering.h"
15 #include "PPC32TargetMachine.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/Constants.h"
21 #include "llvm/Function.h"
24 PPC32TargetLowering::PPC32TargetLowering(TargetMachine &TM)
25 : TargetLowering(TM) {
27 // Fold away setcc operations if possible.
28 setSetCCIsExpensive();
30 // Set up the register classes.
31 addRegisterClass(MVT::i32, PPC32::GPRCRegisterClass);
32 addRegisterClass(MVT::f32, PPC32::FPRCRegisterClass);
33 addRegisterClass(MVT::f64, PPC32::FPRCRegisterClass);
35 // PowerPC has no intrinsics for these particular operations
36 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
37 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
38 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
40 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
41 setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
42 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
44 // PowerPC has no SREM/UREM instructions
45 setOperationAction(ISD::SREM, MVT::i32, Expand);
46 setOperationAction(ISD::UREM, MVT::i32, Expand);
48 // We don't support sin/cos/sqrt/fmod
49 setOperationAction(ISD::FSIN , MVT::f64, Expand);
50 setOperationAction(ISD::FCOS , MVT::f64, Expand);
51 setOperationAction(ISD::SREM , MVT::f64, Expand);
52 setOperationAction(ISD::FSIN , MVT::f32, Expand);
53 setOperationAction(ISD::FCOS , MVT::f32, Expand);
54 setOperationAction(ISD::SREM , MVT::f32, Expand);
56 // If we're enabling GP optimizations, use hardware square root
57 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
58 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
59 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
62 // PowerPC does not have CTPOP or CTTZ
63 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
64 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
66 // PowerPC does not have Select
67 setOperationAction(ISD::SELECT, MVT::i32, Expand);
68 setOperationAction(ISD::SELECT, MVT::f32, Expand);
69 setOperationAction(ISD::SELECT, MVT::f64, Expand);
71 // PowerPC wants to turn select_cc of FP into fsel when possible.
72 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
73 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
75 // PowerPC wants to expand i64 shifts itself.
76 setOperationAction(ISD::SHL, MVT::i64, Custom);
77 setOperationAction(ISD::SRL, MVT::i64, Custom);
78 setOperationAction(ISD::SRA, MVT::i64, Custom);
80 // PowerPC does not have BRCOND* which requires SetCC
81 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
82 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
84 // PowerPC does not have FP_TO_UINT
85 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
87 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
88 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
90 // PowerPC does not have [U|S]INT_TO_FP
91 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
92 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
94 // PowerPC does not have truncstore for i1.
95 setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
97 // 64 bit PowerPC implementations have instructions to facilitate conversion
98 // between i64 and fp.
99 if (TM.getSubtarget<PPCSubtarget>().is64Bit()) {
100 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
101 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
104 setSetCCResultContents(ZeroOrOneSetCCResult);
106 computeRegisterProperties();
109 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
110 static bool isFloatingPointZero(SDOperand Op) {
111 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
112 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
113 else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) {
114 // Maybe this has already been legalized into the constant pool?
115 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
116 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->get()))
117 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
122 /// LowerOperation - Provide custom lowering hooks for some operations.
124 SDOperand PPC32TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
125 switch (Op.getOpcode()) {
126 default: assert(0 && "Wasn't expecting to be able to lower this!");
127 case ISD::FP_TO_SINT: {
128 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType()));
129 switch (Op.getValueType()) {
130 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
132 Op = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Op.getOperand(0));
135 Op = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Op.getOperand(0));
140 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
141 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i32);
142 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
143 Op, FI, DAG.getSrcValue(0));
144 if (Op.getOpcode() == PPCISD::FCTIDZ) {
145 Op = DAG.getLoad(MVT::i64, ST, FI, DAG.getSrcValue(0));
147 FI = DAG.getNode(ISD::ADD, MVT::i32, FI, DAG.getConstant(4, MVT::i32));
148 Op = DAG.getLoad(MVT::i32, ST, FI, DAG.getSrcValue(0));
152 case ISD::SINT_TO_FP: {
153 assert(MVT::i64 == Op.getOperand(0).getValueType() &&
154 "Unhandled SINT_TO_FP type in custom expander!");
156 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
157 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i32);
158 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
159 Op.getOperand(0), FI, DAG.getSrcValue(0));
160 SDOperand LD = DAG.getLoad(MVT::f64, ST, FI, DAG.getSrcValue(0));
161 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, LD);
162 if (MVT::f32 == Op.getValueType())
163 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
166 case ISD::SELECT_CC: {
167 // Turn FP only select_cc's into fsel instructions.
168 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) ||
169 !MVT::isFloatingPoint(Op.getOperand(2).getValueType()))
172 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
174 // Cannot handle SETEQ/SETNE.
175 if (CC == ISD::SETEQ || CC == ISD::SETNE) break;
177 MVT::ValueType ResVT = Op.getValueType();
178 MVT::ValueType CmpVT = Op.getOperand(0).getValueType();
179 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
180 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3);
182 // If the RHS of the comparison is a 0.0, we don't need to do the
183 // subtraction at all.
184 if (isFloatingPointZero(RHS))
186 default: assert(0 && "Invalid FSEL condition"); abort();
189 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
192 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
195 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
198 return DAG.getNode(PPCISD::FSEL, ResVT,
199 DAG.getNode(ISD::FNEG, ResVT, LHS), TV, FV);
203 default: assert(0 && "Invalid FSEL condition"); abort();
206 return DAG.getNode(PPCISD::FSEL, ResVT,
207 DAG.getNode(ISD::SUB, CmpVT, LHS, RHS), FV, TV);
210 return DAG.getNode(PPCISD::FSEL, ResVT,
211 DAG.getNode(ISD::SUB, CmpVT, LHS, RHS), TV, FV);
214 return DAG.getNode(PPCISD::FSEL, ResVT,
215 DAG.getNode(ISD::SUB, CmpVT, RHS, LHS), FV, TV);
218 return DAG.getNode(PPCISD::FSEL, ResVT,
219 DAG.getNode(ISD::SUB, CmpVT, RHS, LHS), TV, FV);
224 assert(Op.getValueType() == MVT::i64 &&
225 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
226 // The generic code does a fine job expanding shift by a constant.
227 if (isa<ConstantSDNode>(Op.getOperand(1))) break;
229 // Otherwise, expand into a bunch of logical ops. Note that these ops
230 // depend on the PPC behavior for oversized shift amounts.
231 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
232 DAG.getConstant(0, MVT::i32));
233 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
234 DAG.getConstant(1, MVT::i32));
235 SDOperand Amt = Op.getOperand(1);
237 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
238 DAG.getConstant(32, MVT::i32), Amt);
239 SDOperand Tmp2 = DAG.getNode(ISD::SHL, MVT::i32, Hi, Amt);
240 SDOperand Tmp3 = DAG.getNode(ISD::SRL, MVT::i32, Lo, Tmp1);
241 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
242 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
243 DAG.getConstant(-32U, MVT::i32));
244 SDOperand Tmp6 = DAG.getNode(ISD::SHL, MVT::i32, Lo, Tmp5);
245 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
246 SDOperand OutLo = DAG.getNode(ISD::SHL, MVT::i32, Lo, Amt);
247 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
250 assert(Op.getValueType() == MVT::i64 &&
251 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
252 // The generic code does a fine job expanding shift by a constant.
253 if (isa<ConstantSDNode>(Op.getOperand(1))) break;
255 // Otherwise, expand into a bunch of logical ops. Note that these ops
256 // depend on the PPC behavior for oversized shift amounts.
257 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
258 DAG.getConstant(0, MVT::i32));
259 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
260 DAG.getConstant(1, MVT::i32));
261 SDOperand Amt = Op.getOperand(1);
263 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
264 DAG.getConstant(32, MVT::i32), Amt);
265 SDOperand Tmp2 = DAG.getNode(ISD::SRL, MVT::i32, Lo, Amt);
266 SDOperand Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, Hi, Tmp1);
267 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
268 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
269 DAG.getConstant(-32U, MVT::i32));
270 SDOperand Tmp6 = DAG.getNode(ISD::SRL, MVT::i32, Hi, Tmp5);
271 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
272 SDOperand OutHi = DAG.getNode(ISD::SRL, MVT::i32, Hi, Amt);
273 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
276 assert(Op.getValueType() == MVT::i64 &&
277 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!");
278 // The generic code does a fine job expanding shift by a constant.
279 if (isa<ConstantSDNode>(Op.getOperand(1))) break;
281 // Otherwise, expand into a bunch of logical ops, followed by a select_cc.
282 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
283 DAG.getConstant(0, MVT::i32));
284 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
285 DAG.getConstant(1, MVT::i32));
286 SDOperand Amt = Op.getOperand(1);
288 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
289 DAG.getConstant(32, MVT::i32), Amt);
290 SDOperand Tmp2 = DAG.getNode(ISD::SRL, MVT::i32, Lo, Amt);
291 SDOperand Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, Hi, Tmp1);
292 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
293 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
294 DAG.getConstant(-32U, MVT::i32));
295 SDOperand Tmp6 = DAG.getNode(ISD::SRA, MVT::i32, Hi, Tmp5);
296 SDOperand OutHi = DAG.getNode(ISD::SRA, MVT::i32, Hi, Amt);
297 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32),
298 Tmp4, Tmp6, ISD::SETLE);
299 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
305 std::vector<SDOperand>
306 PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
308 // add beautiful description of PPC stack frame format, or at least some docs
310 MachineFunction &MF = DAG.getMachineFunction();
311 MachineFrameInfo *MFI = MF.getFrameInfo();
312 MachineBasicBlock& BB = MF.front();
313 std::vector<SDOperand> ArgValues;
315 unsigned ArgOffset = 24;
316 unsigned GPR_remaining = 8;
317 unsigned FPR_remaining = 13;
318 unsigned GPR_idx = 0, FPR_idx = 0;
319 static const unsigned GPR[] = {
320 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
321 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
323 static const unsigned FPR[] = {
324 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
325 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
328 // Add DAG nodes to load the arguments... On entry to a function on PPC,
329 // the arguments start at offset 24, although they are likely to be passed
331 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
332 SDOperand newroot, argt;
334 bool needsLoad = false;
335 bool ArgLive = !I->use_empty();
336 MVT::ValueType ObjectVT = getValueType(I->getType());
339 default: assert(0 && "Unhandled argument type!");
346 if (GPR_remaining > 0) {
347 MF.addLiveIn(GPR[GPR_idx]);
348 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(),
349 GPR[GPR_idx], MVT::i32);
350 if (ObjectVT != MVT::i32) {
351 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
353 argt = DAG.getNode(AssertOp, MVT::i32, argt,
354 DAG.getValueType(ObjectVT));
355 argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, argt);
361 case MVT::i64: ObjSize = 8;
363 if (GPR_remaining > 0) {
364 SDOperand argHi, argLo;
365 MF.addLiveIn(GPR[GPR_idx]);
366 argHi = DAG.getCopyFromReg(DAG.getRoot(), GPR[GPR_idx], MVT::i32);
367 // If we have two or more remaining argument registers, then both halves
368 // of the i64 can be sourced from there. Otherwise, the lower half will
369 // have to come off the stack. This can happen when an i64 is preceded
370 // by 28 bytes of arguments.
371 if (GPR_remaining > 1) {
372 MF.addLiveIn(GPR[GPR_idx+1]);
373 argLo = DAG.getCopyFromReg(argHi, GPR[GPR_idx+1], MVT::i32);
375 int FI = MFI->CreateFixedObject(4, ArgOffset+4);
376 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
377 argLo = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
378 DAG.getSrcValue(NULL));
380 // Build the outgoing arg thingy
381 argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi);
389 ObjSize = (ObjectVT == MVT::f64) ? 8 : 4;
391 if (FPR_remaining > 0) {
392 MF.addLiveIn(FPR[FPR_idx]);
393 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(),
394 FPR[FPR_idx], ObjectVT);
403 // We need to load the argument to a virtual register if we determined above
404 // that we ran out of physical registers of the appropriate type
406 unsigned SubregOffset = 0;
407 if (ObjectVT == MVT::i8 || ObjectVT == MVT::i1) SubregOffset = 3;
408 if (ObjectVT == MVT::i16) SubregOffset = 2;
409 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
410 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
411 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN,
412 DAG.getConstant(SubregOffset, MVT::i32));
413 argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
414 DAG.getSrcValue(NULL));
417 // Every 4 bytes of argument space consumes one of the GPRs available for
419 if (GPR_remaining > 0) {
420 unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1;
421 GPR_remaining -= delta;
424 ArgOffset += ObjSize;
426 DAG.setRoot(newroot.getValue(1));
428 ArgValues.push_back(argt);
431 // If the function takes variable number of arguments, make a frame index for
432 // the start of the first vararg value... for expansion of llvm.va_start.
434 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
435 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
436 // If this function is vararg, store any remaining integer argument regs
437 // to their spots on the stack so that they may be loaded by deferencing the
438 // result of va_next.
439 std::vector<SDOperand> MemOps;
440 for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) {
441 MF.addLiveIn(GPR[GPR_idx]);
442 SDOperand Val = DAG.getCopyFromReg(DAG.getRoot(), GPR[GPR_idx], MVT::i32);
443 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
444 Val, FIN, DAG.getSrcValue(NULL));
445 MemOps.push_back(Store);
446 // Increment the address by four for the next argument to store
447 SDOperand PtrOff = DAG.getConstant(4, getPointerTy());
448 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, PtrOff);
450 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps));
453 // Finally, inform the code generator which regs we return values in.
454 switch (getValueType(F.getReturnType())) {
455 default: assert(0 && "Unknown type!");
456 case MVT::isVoid: break;
461 MF.addLiveOut(PPC::R3);
464 MF.addLiveOut(PPC::R3);
465 MF.addLiveOut(PPC::R4);
469 MF.addLiveOut(PPC::F1);
476 std::pair<SDOperand, SDOperand>
477 PPC32TargetLowering::LowerCallTo(SDOperand Chain,
478 const Type *RetTy, bool isVarArg,
479 unsigned CallingConv, bool isTailCall,
480 SDOperand Callee, ArgListTy &Args,
482 // args_to_use will accumulate outgoing args for the ISD::CALL case in
483 // SelectExpr to use to put the arguments in the appropriate registers.
484 std::vector<SDOperand> args_to_use;
486 // Count how many bytes are to be pushed on the stack, including the linkage
487 // area, and parameter passing area.
488 unsigned NumBytes = 24;
491 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
492 DAG.getConstant(NumBytes, getPointerTy()));
494 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
495 switch (getValueType(Args[i].second)) {
496 default: assert(0 && "Unknown value type!");
511 // Just to be safe, we'll always reserve the full 24 bytes of linkage area
512 // plus 32 bytes of argument space in case any called code gets funky on us.
513 // (Required by ABI to support var arg)
514 if (NumBytes < 56) NumBytes = 56;
516 // Adjust the stack pointer for the new arguments...
517 // These operations are automatically eliminated by the prolog/epilog pass
518 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
519 DAG.getConstant(NumBytes, getPointerTy()));
521 // Set up a copy of the stack pointer for use loading and storing any
522 // arguments that may not fit in the registers available for argument
524 SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
527 // Figure out which arguments are going to go in registers, and which in
528 // memory. Also, if this is a vararg function, floating point operations
529 // must be stored to our stack, and loaded into integer regs as well, if
530 // any integer regs are available for argument passing.
531 unsigned ArgOffset = 24;
532 unsigned GPR_remaining = 8;
533 unsigned FPR_remaining = 13;
535 std::vector<SDOperand> MemOps;
536 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
537 // PtrOff will be used to store the current argument to the stack if a
538 // register cannot be found for it.
539 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
540 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
541 MVT::ValueType ArgVT = getValueType(Args[i].second);
544 default: assert(0 && "Unexpected ValueType for argument!");
548 // Promote the integer to 32 bits. If the input type is signed use a
549 // sign extend, otherwise use a zero extend.
550 if (Args[i].second->isSigned())
551 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
553 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
556 if (GPR_remaining > 0) {
557 args_to_use.push_back(Args[i].first);
560 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
561 Args[i].first, PtrOff,
562 DAG.getSrcValue(NULL)));
567 // If we have one free GPR left, we can place the upper half of the i64
568 // in it, and store the other half to the stack. If we have two or more
569 // free GPRs, then we can pass both halves of the i64 in registers.
570 if (GPR_remaining > 0) {
571 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
572 Args[i].first, DAG.getConstant(1, MVT::i32));
573 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
574 Args[i].first, DAG.getConstant(0, MVT::i32));
575 args_to_use.push_back(Hi);
577 if (GPR_remaining > 0) {
578 args_to_use.push_back(Lo);
581 SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
582 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
583 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
584 Lo, PtrOff, DAG.getSrcValue(NULL)));
587 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
588 Args[i].first, PtrOff,
589 DAG.getSrcValue(NULL)));
595 if (FPR_remaining > 0) {
596 args_to_use.push_back(Args[i].first);
599 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
600 Args[i].first, PtrOff,
601 DAG.getSrcValue(NULL));
602 MemOps.push_back(Store);
603 // Float varargs are always shadowed in available integer registers
604 if (GPR_remaining > 0) {
605 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
606 DAG.getSrcValue(NULL));
607 MemOps.push_back(Load);
608 args_to_use.push_back(Load);
611 if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
612 SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
613 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
614 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
615 DAG.getSrcValue(NULL));
616 MemOps.push_back(Load);
617 args_to_use.push_back(Load);
621 // If we have any FPRs remaining, we may also have GPRs remaining.
622 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
624 if (GPR_remaining > 0) {
625 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
628 if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
629 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
634 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
635 Args[i].first, PtrOff,
636 DAG.getSrcValue(NULL)));
638 ArgOffset += (ArgVT == MVT::f32) ? 4 : 8;
643 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps);
646 std::vector<MVT::ValueType> RetVals;
647 MVT::ValueType RetTyVT = getValueType(RetTy);
648 MVT::ValueType ActualRetTyVT = RetTyVT;
649 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i16)
650 ActualRetTyVT = MVT::i32; // Promote result to i32.
652 if (RetTyVT != MVT::isVoid)
653 RetVals.push_back(ActualRetTyVT);
654 RetVals.push_back(MVT::Other);
656 SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
657 Chain, Callee, args_to_use), 0);
658 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
659 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
660 DAG.getConstant(NumBytes, getPointerTy()));
661 SDOperand RetVal = TheCall;
663 // If the result is a small value, add a note so that we keep track of the
664 // information about whether it is sign or zero extended.
665 if (RetTyVT != ActualRetTyVT) {
666 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext,
667 MVT::i32, RetVal, DAG.getValueType(RetTyVT));
668 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
671 return std::make_pair(RetVal, Chain);
674 SDOperand PPC32TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
675 Value *VAListV, SelectionDAG &DAG) {
676 // vastart just stores the address of the VarArgsFrameIndex slot into the
677 // memory location argument.
678 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
679 return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
680 DAG.getSrcValue(VAListV));
683 std::pair<SDOperand,SDOperand>
684 PPC32TargetLowering::LowerVAArg(SDOperand Chain,
685 SDOperand VAListP, Value *VAListV,
686 const Type *ArgTy, SelectionDAG &DAG) {
687 MVT::ValueType ArgVT = getValueType(ArgTy);
690 DAG.getLoad(MVT::i32, Chain, VAListP, DAG.getSrcValue(VAListV));
691 SDOperand Result = DAG.getLoad(ArgVT, Chain, VAList, DAG.getSrcValue(NULL));
693 if (ArgVT == MVT::i32 || ArgVT == MVT::f32)
696 assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
697 "Other types should have been promoted for varargs!");
700 VAList = DAG.getNode(ISD::ADD, VAList.getValueType(), VAList,
701 DAG.getConstant(Amt, VAList.getValueType()));
702 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
703 VAList, VAListP, DAG.getSrcValue(VAListV));
704 return std::make_pair(Result, Chain);
708 std::pair<SDOperand, SDOperand> PPC32TargetLowering::
709 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
711 assert(0 && "LowerFrameReturnAddress unimplemented");
716 PPC32TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
717 MachineBasicBlock *BB) {
718 assert((MI->getOpcode() == PPC::SELECT_CC_Int ||
719 MI->getOpcode() == PPC::SELECT_CC_FP) &&
720 "Unexpected instr type to insert");
722 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
723 // control-flow pattern. The incoming instruction knows the destination vreg
724 // to set, the condition code register to branch on, the true/false values to
725 // select between, and a branch opcode to use.
726 const BasicBlock *LLVM_BB = BB->getBasicBlock();
727 ilist<MachineBasicBlock>::iterator It = BB;
735 // fallthrough --> copy0MBB
736 MachineBasicBlock *thisMBB = BB;
737 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
738 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
739 BuildMI(BB, MI->getOperand(4).getImmedValue(), 2)
740 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
741 MachineFunction *F = BB->getParent();
742 F->getBasicBlockList().insert(It, copy0MBB);
743 F->getBasicBlockList().insert(It, sinkMBB);
744 // Update machine-CFG edges
745 BB->addSuccessor(copy0MBB);
746 BB->addSuccessor(sinkMBB);
750 // # fallthrough to sinkMBB
753 // Update machine-CFG edges
754 BB->addSuccessor(sinkMBB);
757 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
760 BuildMI(BB, PPC::PHI, 4, MI->getOperand(0).getReg())
761 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
762 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
764 delete MI; // The pseudo instruction is gone now.