1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCMachineFunctionInfo.h"
16 #include "PPCPredicates.h"
17 #include "PPCTargetMachine.h"
18 #include "PPCPerfectShuffle.h"
19 #include "llvm/ADT/VectorExtras.h"
20 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/CodeGen/SSARegMap.h"
27 #include "llvm/Constants.h"
28 #include "llvm/Function.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/Support/MathExtras.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Support/CommandLine.h"
35 static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc",
36 cl::desc("enable preincrement load/store generation on PPC (experimental)"),
39 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
40 : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) {
44 // Use _setjmp/_longjmp instead of setjmp/longjmp.
45 setUseUnderscoreSetJmp(true);
46 setUseUnderscoreLongJmp(true);
48 // Set up the register classes.
49 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
50 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
51 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
53 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
54 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand);
55 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand);
57 // PowerPC does not have truncstore for i1.
58 setStoreXAction(MVT::i1, Promote);
60 // PowerPC has pre-inc load and store's.
61 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
62 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
63 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
64 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
65 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
66 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
67 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
68 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
69 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
70 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
72 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
73 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
75 // PowerPC has no intrinsics for these particular operations
76 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
77 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
78 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
80 // PowerPC has no SREM/UREM instructions
81 setOperationAction(ISD::SREM, MVT::i32, Expand);
82 setOperationAction(ISD::UREM, MVT::i32, Expand);
83 setOperationAction(ISD::SREM, MVT::i64, Expand);
84 setOperationAction(ISD::UREM, MVT::i64, Expand);
86 // We don't support sin/cos/sqrt/fmod
87 setOperationAction(ISD::FSIN , MVT::f64, Expand);
88 setOperationAction(ISD::FCOS , MVT::f64, Expand);
89 setOperationAction(ISD::FREM , MVT::f64, Expand);
90 setOperationAction(ISD::FSIN , MVT::f32, Expand);
91 setOperationAction(ISD::FCOS , MVT::f32, Expand);
92 setOperationAction(ISD::FREM , MVT::f32, Expand);
94 // If we're enabling GP optimizations, use hardware square root
95 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
96 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
97 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
100 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
101 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
103 // PowerPC does not have BSWAP, CTPOP or CTTZ
104 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
105 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
106 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
107 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
108 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
109 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
111 // PowerPC does not have ROTR
112 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
114 // PowerPC does not have Select
115 setOperationAction(ISD::SELECT, MVT::i32, Expand);
116 setOperationAction(ISD::SELECT, MVT::i64, Expand);
117 setOperationAction(ISD::SELECT, MVT::f32, Expand);
118 setOperationAction(ISD::SELECT, MVT::f64, Expand);
120 // PowerPC wants to turn select_cc of FP into fsel when possible.
121 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
122 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
124 // PowerPC wants to optimize integer setcc a bit
125 setOperationAction(ISD::SETCC, MVT::i32, Custom);
127 // PowerPC does not have BRCOND which requires SetCC
128 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
130 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
132 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
133 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
135 // PowerPC does not have [U|S]INT_TO_FP
136 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
137 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
139 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
140 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
141 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
142 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
144 // We cannot sextinreg(i1). Expand to shifts.
145 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
147 // Support label based line numbers.
148 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
149 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
150 if (!TM.getSubtarget<PPCSubtarget>().isDarwin()) {
151 setOperationAction(ISD::LABEL, MVT::Other, Expand);
153 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
154 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
155 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
156 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
159 // We want to legalize GlobalAddress and ConstantPool nodes into the
160 // appropriate instructions to materialize the address.
161 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
162 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
163 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
164 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
165 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
166 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
167 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
168 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
170 // RET must be custom lowered, to meet ABI requirements
171 setOperationAction(ISD::RET , MVT::Other, Custom);
173 setOperationAction(ISD::ADJUST_TRAMP, MVT::i32, Expand);
174 setOperationAction(ISD::ADJUST_TRAMP, MVT::i64, Expand);
176 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
177 setOperationAction(ISD::VASTART , MVT::Other, Custom);
179 // VAARG is custom lowered with ELF 32 ABI
180 if (TM.getSubtarget<PPCSubtarget>().isELF32_ABI())
181 setOperationAction(ISD::VAARG, MVT::Other, Custom);
183 setOperationAction(ISD::VAARG, MVT::Other, Expand);
185 // Use the default implementation.
186 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
187 setOperationAction(ISD::VAEND , MVT::Other, Expand);
188 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
189 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
190 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
191 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
193 // We want to custom lower some of our intrinsics.
194 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
196 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
197 // They also have instructions for converting between i64 and fp.
198 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
199 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
200 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
201 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
202 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
204 // FIXME: disable this lowered code. This generates 64-bit register values,
205 // and we don't model the fact that the top part is clobbered by calls. We
206 // need to flag these together so that the value isn't live across a call.
207 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
209 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
210 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
212 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
213 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
216 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
217 // 64 bit PowerPC implementations can support i64 types directly
218 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
219 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
220 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
222 // 32 bit PowerPC wants to expand i64 shifts itself.
223 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
224 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
225 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
228 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
229 // First set operation action for all vector types to expand. Then we
230 // will selectively turn on ones that can be effectively codegen'd.
231 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
232 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
233 // add/sub are legal for all supported vector VT's.
234 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal);
235 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal);
237 // We promote all shuffles to v16i8.
238 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote);
239 AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8);
241 // We promote all non-typed operations to v4i32.
242 setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote);
243 AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32);
244 setOperationAction(ISD::OR , (MVT::ValueType)VT, Promote);
245 AddPromotedToType (ISD::OR , (MVT::ValueType)VT, MVT::v4i32);
246 setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote);
247 AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32);
248 setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote);
249 AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32);
250 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
251 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32);
252 setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote);
253 AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32);
255 // No other operations are legal.
256 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
257 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
258 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
259 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
260 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
261 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
262 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
263 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
264 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
266 setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand);
269 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
270 // with merges, splats, etc.
271 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
273 setOperationAction(ISD::AND , MVT::v4i32, Legal);
274 setOperationAction(ISD::OR , MVT::v4i32, Legal);
275 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
276 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
277 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
278 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
280 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
281 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
282 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
283 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
285 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
286 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
287 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
288 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
290 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
291 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
293 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
294 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
295 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
296 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
299 setSetCCResultType(MVT::i32);
300 setShiftAmountType(MVT::i32);
301 setSetCCResultContents(ZeroOrOneSetCCResult);
303 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
304 setStackPointerRegisterToSaveRestore(PPC::X1);
305 setExceptionPointerRegister(PPC::X3);
306 setExceptionSelectorRegister(PPC::X4);
308 setStackPointerRegisterToSaveRestore(PPC::R1);
309 setExceptionPointerRegister(PPC::R3);
310 setExceptionSelectorRegister(PPC::R4);
313 // We have target-specific dag combine patterns for the following nodes:
314 setTargetDAGCombine(ISD::SINT_TO_FP);
315 setTargetDAGCombine(ISD::STORE);
316 setTargetDAGCombine(ISD::BR_CC);
317 setTargetDAGCombine(ISD::BSWAP);
319 computeRegisterProperties();
322 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
325 case PPCISD::FSEL: return "PPCISD::FSEL";
326 case PPCISD::FCFID: return "PPCISD::FCFID";
327 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
328 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
329 case PPCISD::STFIWX: return "PPCISD::STFIWX";
330 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
331 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
332 case PPCISD::VPERM: return "PPCISD::VPERM";
333 case PPCISD::Hi: return "PPCISD::Hi";
334 case PPCISD::Lo: return "PPCISD::Lo";
335 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
336 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
337 case PPCISD::SRL: return "PPCISD::SRL";
338 case PPCISD::SRA: return "PPCISD::SRA";
339 case PPCISD::SHL: return "PPCISD::SHL";
340 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
341 case PPCISD::STD_32: return "PPCISD::STD_32";
342 case PPCISD::CALL_ELF: return "PPCISD::CALL_ELF";
343 case PPCISD::CALL_Macho: return "PPCISD::CALL_Macho";
344 case PPCISD::MTCTR: return "PPCISD::MTCTR";
345 case PPCISD::BCTRL_Macho: return "PPCISD::BCTRL_Macho";
346 case PPCISD::BCTRL_ELF: return "PPCISD::BCTRL_ELF";
347 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
348 case PPCISD::MFCR: return "PPCISD::MFCR";
349 case PPCISD::VCMP: return "PPCISD::VCMP";
350 case PPCISD::VCMPo: return "PPCISD::VCMPo";
351 case PPCISD::LBRX: return "PPCISD::LBRX";
352 case PPCISD::STBRX: return "PPCISD::STBRX";
353 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
357 //===----------------------------------------------------------------------===//
358 // Node matching predicates, for use by the tblgen matching code.
359 //===----------------------------------------------------------------------===//
361 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
362 static bool isFloatingPointZero(SDOperand Op) {
363 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
364 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
365 else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
366 // Maybe this has already been legalized into the constant pool?
367 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
368 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
369 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
374 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
375 /// true if Op is undef or if it matches the specified value.
376 static bool isConstantOrUndef(SDOperand Op, unsigned Val) {
377 return Op.getOpcode() == ISD::UNDEF ||
378 cast<ConstantSDNode>(Op)->getValue() == Val;
381 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
382 /// VPKUHUM instruction.
383 bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) {
385 for (unsigned i = 0; i != 16; ++i)
386 if (!isConstantOrUndef(N->getOperand(i), i*2+1))
389 for (unsigned i = 0; i != 8; ++i)
390 if (!isConstantOrUndef(N->getOperand(i), i*2+1) ||
391 !isConstantOrUndef(N->getOperand(i+8), i*2+1))
397 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
398 /// VPKUWUM instruction.
399 bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) {
401 for (unsigned i = 0; i != 16; i += 2)
402 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
403 !isConstantOrUndef(N->getOperand(i+1), i*2+3))
406 for (unsigned i = 0; i != 8; i += 2)
407 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
408 !isConstantOrUndef(N->getOperand(i+1), i*2+3) ||
409 !isConstantOrUndef(N->getOperand(i+8), i*2+2) ||
410 !isConstantOrUndef(N->getOperand(i+9), i*2+3))
416 /// isVMerge - Common function, used to match vmrg* shuffles.
418 static bool isVMerge(SDNode *N, unsigned UnitSize,
419 unsigned LHSStart, unsigned RHSStart) {
420 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
421 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
422 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
423 "Unsupported merge size!");
425 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
426 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
427 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j),
428 LHSStart+j+i*UnitSize) ||
429 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j),
430 RHSStart+j+i*UnitSize))
436 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
437 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
438 bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
440 return isVMerge(N, UnitSize, 8, 24);
441 return isVMerge(N, UnitSize, 8, 8);
444 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
445 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
446 bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
448 return isVMerge(N, UnitSize, 0, 16);
449 return isVMerge(N, UnitSize, 0, 0);
453 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
454 /// amount, otherwise return -1.
455 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
456 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
457 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
458 // Find the first non-undef value in the shuffle mask.
460 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i)
463 if (i == 16) return -1; // all undef.
465 // Otherwise, check to see if the rest of the elements are consequtively
466 // numbered from this value.
467 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue();
468 if (ShiftAmt < i) return -1;
472 // Check the rest of the elements to see if they are consequtive.
473 for (++i; i != 16; ++i)
474 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i))
477 // Check the rest of the elements to see if they are consequtive.
478 for (++i; i != 16; ++i)
479 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15))
486 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
487 /// specifies a splat of a single element that is suitable for input to
488 /// VSPLTB/VSPLTH/VSPLTW.
489 bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) {
490 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
491 N->getNumOperands() == 16 &&
492 (EltSize == 1 || EltSize == 2 || EltSize == 4));
494 // This is a splat operation if each element of the permute is the same, and
495 // if the value doesn't reference the second vector.
496 unsigned ElementBase = 0;
497 SDOperand Elt = N->getOperand(0);
498 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt))
499 ElementBase = EltV->getValue();
501 return false; // FIXME: Handle UNDEF elements too!
503 if (cast<ConstantSDNode>(Elt)->getValue() >= 16)
506 // Check that they are consequtive.
507 for (unsigned i = 1; i != EltSize; ++i) {
508 if (!isa<ConstantSDNode>(N->getOperand(i)) ||
509 cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase)
513 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
514 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
515 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
516 assert(isa<ConstantSDNode>(N->getOperand(i)) &&
517 "Invalid VECTOR_SHUFFLE mask!");
518 for (unsigned j = 0; j != EltSize; ++j)
519 if (N->getOperand(i+j) != N->getOperand(j))
526 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
527 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
528 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
529 assert(isSplatShuffleMask(N, EltSize));
530 return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize;
533 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
534 /// by using a vspltis[bhw] instruction of the specified element size, return
535 /// the constant being splatted. The ByteSize field indicates the number of
536 /// bytes of each element [124] -> [bhw].
537 SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
538 SDOperand OpVal(0, 0);
540 // If ByteSize of the splat is bigger than the element size of the
541 // build_vector, then we have a case where we are checking for a splat where
542 // multiple elements of the buildvector are folded together into a single
543 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
544 unsigned EltSize = 16/N->getNumOperands();
545 if (EltSize < ByteSize) {
546 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
547 SDOperand UniquedVals[4];
548 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
550 // See if all of the elements in the buildvector agree across.
551 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
552 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
553 // If the element isn't a constant, bail fully out.
554 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand();
557 if (UniquedVals[i&(Multiple-1)].Val == 0)
558 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
559 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
560 return SDOperand(); // no match.
563 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
564 // either constant or undef values that are identical for each chunk. See
565 // if these chunks can form into a larger vspltis*.
567 // Check to see if all of the leading entries are either 0 or -1. If
568 // neither, then this won't fit into the immediate field.
569 bool LeadingZero = true;
570 bool LeadingOnes = true;
571 for (unsigned i = 0; i != Multiple-1; ++i) {
572 if (UniquedVals[i].Val == 0) continue; // Must have been undefs.
574 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
575 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
577 // Finally, check the least significant entry.
579 if (UniquedVals[Multiple-1].Val == 0)
580 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
581 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue();
583 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
586 if (UniquedVals[Multiple-1].Val == 0)
587 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
588 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended();
589 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
590 return DAG.getTargetConstant(Val, MVT::i32);
596 // Check to see if this buildvec has a single non-undef value in its elements.
597 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
598 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
600 OpVal = N->getOperand(i);
601 else if (OpVal != N->getOperand(i))
605 if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def.
607 unsigned ValSizeInBytes = 0;
609 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
610 Value = CN->getValue();
611 ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8;
612 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
613 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
614 Value = FloatToBits(CN->getValue());
618 // If the splat value is larger than the element value, then we can never do
619 // this splat. The only case that we could fit the replicated bits into our
620 // immediate field for would be zero, and we prefer to use vxor for it.
621 if (ValSizeInBytes < ByteSize) return SDOperand();
623 // If the element value is larger than the splat value, cut it in half and
624 // check to see if the two halves are equal. Continue doing this until we
625 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
626 while (ValSizeInBytes > ByteSize) {
627 ValSizeInBytes >>= 1;
629 // If the top half equals the bottom half, we're still ok.
630 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
631 (Value & ((1 << (8*ValSizeInBytes))-1)))
635 // Properly sign extend the value.
636 int ShAmt = (4-ByteSize)*8;
637 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
639 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
640 if (MaskVal == 0) return SDOperand();
642 // Finally, if this value fits in a 5 bit sext field, return it
643 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
644 return DAG.getTargetConstant(MaskVal, MVT::i32);
648 //===----------------------------------------------------------------------===//
649 // Addressing Mode Selection
650 //===----------------------------------------------------------------------===//
652 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
653 /// or 64-bit immediate, and if the value can be accurately represented as a
654 /// sign extension from a 16-bit value. If so, this returns true and the
656 static bool isIntS16Immediate(SDNode *N, short &Imm) {
657 if (N->getOpcode() != ISD::Constant)
660 Imm = (short)cast<ConstantSDNode>(N)->getValue();
661 if (N->getValueType(0) == MVT::i32)
662 return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue();
664 return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue();
666 static bool isIntS16Immediate(SDOperand Op, short &Imm) {
667 return isIntS16Immediate(Op.Val, Imm);
671 /// SelectAddressRegReg - Given the specified addressed, check to see if it
672 /// can be represented as an indexed [r+r] operation. Returns false if it
673 /// can be more efficiently represented with [r+imm].
674 bool PPCTargetLowering::SelectAddressRegReg(SDOperand N, SDOperand &Base,
678 if (N.getOpcode() == ISD::ADD) {
679 if (isIntS16Immediate(N.getOperand(1), imm))
681 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
684 Base = N.getOperand(0);
685 Index = N.getOperand(1);
687 } else if (N.getOpcode() == ISD::OR) {
688 if (isIntS16Immediate(N.getOperand(1), imm))
689 return false; // r+i can fold it if we can.
691 // If this is an or of disjoint bitfields, we can codegen this as an add
692 // (for better address arithmetic) if the LHS and RHS of the OR are provably
694 uint64_t LHSKnownZero, LHSKnownOne;
695 uint64_t RHSKnownZero, RHSKnownOne;
696 DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne);
699 DAG.ComputeMaskedBits(N.getOperand(1), ~0U, RHSKnownZero, RHSKnownOne);
700 // If all of the bits are known zero on the LHS or RHS, the add won't
702 if ((LHSKnownZero | RHSKnownZero) == ~0U) {
703 Base = N.getOperand(0);
704 Index = N.getOperand(1);
713 /// Returns true if the address N can be represented by a base register plus
714 /// a signed 16-bit displacement [r+imm], and if it is not better
715 /// represented as reg+reg.
716 bool PPCTargetLowering::SelectAddressRegImm(SDOperand N, SDOperand &Disp,
717 SDOperand &Base, SelectionDAG &DAG){
718 // If this can be more profitably realized as r+r, fail.
719 if (SelectAddressRegReg(N, Disp, Base, DAG))
722 if (N.getOpcode() == ISD::ADD) {
724 if (isIntS16Immediate(N.getOperand(1), imm)) {
725 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
726 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
727 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
729 Base = N.getOperand(0);
731 return true; // [r+i]
732 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
733 // Match LOAD (ADD (X, Lo(G))).
734 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
735 && "Cannot handle constant offsets yet!");
736 Disp = N.getOperand(1).getOperand(0); // The global address.
737 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
738 Disp.getOpcode() == ISD::TargetConstantPool ||
739 Disp.getOpcode() == ISD::TargetJumpTable);
740 Base = N.getOperand(0);
741 return true; // [&g+r]
743 } else if (N.getOpcode() == ISD::OR) {
745 if (isIntS16Immediate(N.getOperand(1), imm)) {
746 // If this is an or of disjoint bitfields, we can codegen this as an add
747 // (for better address arithmetic) if the LHS and RHS of the OR are
748 // provably disjoint.
749 uint64_t LHSKnownZero, LHSKnownOne;
750 DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne);
751 if ((LHSKnownZero|~(unsigned)imm) == ~0U) {
752 // If all of the bits are known zero on the LHS or RHS, the add won't
754 Base = N.getOperand(0);
755 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
759 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
760 // Loading from a constant address.
762 // If this address fits entirely in a 16-bit sext immediate field, codegen
765 if (isIntS16Immediate(CN, Imm)) {
766 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
767 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
771 // Handle 32-bit sext immediates with LIS + addr mode.
772 if (CN->getValueType(0) == MVT::i32 ||
773 (int64_t)CN->getValue() == (int)CN->getValue()) {
774 int Addr = (int)CN->getValue();
776 // Otherwise, break this down into an LIS + disp.
777 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
779 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
780 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
781 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
786 Disp = DAG.getTargetConstant(0, getPointerTy());
787 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
788 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
791 return true; // [r+0]
794 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
795 /// represented as an indexed [r+r] operation.
796 bool PPCTargetLowering::SelectAddressRegRegOnly(SDOperand N, SDOperand &Base,
799 // Check to see if we can easily represent this as an [r+r] address. This
800 // will fail if it thinks that the address is more profitably represented as
801 // reg+imm, e.g. where imm = 0.
802 if (SelectAddressRegReg(N, Base, Index, DAG))
805 // If the operand is an addition, always emit this as [r+r], since this is
806 // better (for code size, and execution, as the memop does the add for free)
807 // than emitting an explicit add.
808 if (N.getOpcode() == ISD::ADD) {
809 Base = N.getOperand(0);
810 Index = N.getOperand(1);
814 // Otherwise, do it the hard way, using R0 as the base register.
815 Base = DAG.getRegister(PPC::R0, N.getValueType());
820 /// SelectAddressRegImmShift - Returns true if the address N can be
821 /// represented by a base register plus a signed 14-bit displacement
822 /// [r+imm*4]. Suitable for use by STD and friends.
823 bool PPCTargetLowering::SelectAddressRegImmShift(SDOperand N, SDOperand &Disp,
826 // If this can be more profitably realized as r+r, fail.
827 if (SelectAddressRegReg(N, Disp, Base, DAG))
830 if (N.getOpcode() == ISD::ADD) {
832 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
833 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
834 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
835 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
837 Base = N.getOperand(0);
839 return true; // [r+i]
840 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
841 // Match LOAD (ADD (X, Lo(G))).
842 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
843 && "Cannot handle constant offsets yet!");
844 Disp = N.getOperand(1).getOperand(0); // The global address.
845 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
846 Disp.getOpcode() == ISD::TargetConstantPool ||
847 Disp.getOpcode() == ISD::TargetJumpTable);
848 Base = N.getOperand(0);
849 return true; // [&g+r]
851 } else if (N.getOpcode() == ISD::OR) {
853 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
854 // If this is an or of disjoint bitfields, we can codegen this as an add
855 // (for better address arithmetic) if the LHS and RHS of the OR are
856 // provably disjoint.
857 uint64_t LHSKnownZero, LHSKnownOne;
858 DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne);
859 if ((LHSKnownZero|~(unsigned)imm) == ~0U) {
860 // If all of the bits are known zero on the LHS or RHS, the add won't
862 Base = N.getOperand(0);
863 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
867 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
868 // Loading from a constant address. Verify low two bits are clear.
869 if ((CN->getValue() & 3) == 0) {
870 // If this address fits entirely in a 14-bit sext immediate field, codegen
873 if (isIntS16Immediate(CN, Imm)) {
874 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
875 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
879 // Fold the low-part of 32-bit absolute addresses into addr mode.
880 if (CN->getValueType(0) == MVT::i32 ||
881 (int64_t)CN->getValue() == (int)CN->getValue()) {
882 int Addr = (int)CN->getValue();
884 // Otherwise, break this down into an LIS + disp.
885 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
887 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
888 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
889 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
895 Disp = DAG.getTargetConstant(0, getPointerTy());
896 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
897 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
900 return true; // [r+0]
904 /// getPreIndexedAddressParts - returns true by value, base pointer and
905 /// offset pointer and addressing mode by reference if the node's address
906 /// can be legally represented as pre-indexed load / store address.
907 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
909 ISD::MemIndexedMode &AM,
911 // Disabled by default for now.
912 if (!EnablePPCPreinc) return false;
916 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
917 Ptr = LD->getBasePtr();
918 VT = LD->getLoadedVT();
920 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
922 Ptr = ST->getBasePtr();
923 VT = ST->getStoredVT();
927 // PowerPC doesn't have preinc load/store instructions for vectors.
928 if (MVT::isVector(VT))
931 // TODO: Check reg+reg first.
933 // LDU/STU use reg+imm*4, others use reg+imm.
934 if (VT != MVT::i64) {
936 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
940 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
944 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
945 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
946 // sext i32 to i64 when addr mode is r+i.
947 if (LD->getValueType(0) == MVT::i64 && LD->getLoadedVT() == MVT::i32 &&
948 LD->getExtensionType() == ISD::SEXTLOAD &&
949 isa<ConstantSDNode>(Offset))
957 //===----------------------------------------------------------------------===//
958 // LowerOperation implementation
959 //===----------------------------------------------------------------------===//
961 static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
962 MVT::ValueType PtrVT = Op.getValueType();
963 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
964 Constant *C = CP->getConstVal();
965 SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
966 SDOperand Zero = DAG.getConstant(0, PtrVT);
968 const TargetMachine &TM = DAG.getTarget();
970 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero);
971 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero);
973 // If this is a non-darwin platform, we don't support non-static relo models
975 if (TM.getRelocationModel() == Reloc::Static ||
976 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
977 // Generate non-pic code that has direct accesses to the constant pool.
978 // The address of the global is just (hi(&g)+lo(&g)).
979 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
982 if (TM.getRelocationModel() == Reloc::PIC_) {
983 // With PIC, the first instruction is actually "GR+hi(&G)".
984 Hi = DAG.getNode(ISD::ADD, PtrVT,
985 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
988 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
992 static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
993 MVT::ValueType PtrVT = Op.getValueType();
994 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
995 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
996 SDOperand Zero = DAG.getConstant(0, PtrVT);
998 const TargetMachine &TM = DAG.getTarget();
1000 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero);
1001 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero);
1003 // If this is a non-darwin platform, we don't support non-static relo models
1005 if (TM.getRelocationModel() == Reloc::Static ||
1006 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1007 // Generate non-pic code that has direct accesses to the constant pool.
1008 // The address of the global is just (hi(&g)+lo(&g)).
1009 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1012 if (TM.getRelocationModel() == Reloc::PIC_) {
1013 // With PIC, the first instruction is actually "GR+hi(&G)".
1014 Hi = DAG.getNode(ISD::ADD, PtrVT,
1015 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1018 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1022 static SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) {
1023 assert(0 && "TLS not implemented for PPC.");
1026 static SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
1027 MVT::ValueType PtrVT = Op.getValueType();
1028 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1029 GlobalValue *GV = GSDN->getGlobal();
1030 SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
1031 SDOperand Zero = DAG.getConstant(0, PtrVT);
1033 const TargetMachine &TM = DAG.getTarget();
1035 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero);
1036 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero);
1038 // If this is a non-darwin platform, we don't support non-static relo models
1040 if (TM.getRelocationModel() == Reloc::Static ||
1041 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1042 // Generate non-pic code that has direct accesses to globals.
1043 // The address of the global is just (hi(&g)+lo(&g)).
1044 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1047 if (TM.getRelocationModel() == Reloc::PIC_) {
1048 // With PIC, the first instruction is actually "GR+hi(&G)".
1049 Hi = DAG.getNode(ISD::ADD, PtrVT,
1050 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1053 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1055 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV))
1058 // If the global is weak or external, we have to go through the lazy
1060 return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0);
1063 static SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
1064 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1066 // If we're comparing for equality to zero, expose the fact that this is
1067 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1068 // fold the new nodes.
1069 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1070 if (C->isNullValue() && CC == ISD::SETEQ) {
1071 MVT::ValueType VT = Op.getOperand(0).getValueType();
1072 SDOperand Zext = Op.getOperand(0);
1073 if (VT < MVT::i32) {
1075 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0));
1077 unsigned Log2b = Log2_32(MVT::getSizeInBits(VT));
1078 SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext);
1079 SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz,
1080 DAG.getConstant(Log2b, MVT::i32));
1081 return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc);
1083 // Leave comparisons against 0 and -1 alone for now, since they're usually
1084 // optimized. FIXME: revisit this when we can custom lower all setcc
1086 if (C->isAllOnesValue() || C->isNullValue())
1090 // If we have an integer seteq/setne, turn it into a compare against zero
1091 // by xor'ing the rhs with the lhs, which is faster than setting a
1092 // condition register, reading it back out, and masking the correct bit. The
1093 // normal approach here uses sub to do this instead of xor. Using xor exposes
1094 // the result to other bit-twiddling opportunities.
1095 MVT::ValueType LHSVT = Op.getOperand(0).getValueType();
1096 if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1097 MVT::ValueType VT = Op.getValueType();
1098 SDOperand Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0),
1100 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC);
1105 static SDOperand LowerVAARG(SDOperand Op, SelectionDAG &DAG,
1106 int VarArgsFrameIndex,
1107 int VarArgsStackOffset,
1108 unsigned VarArgsNumGPR,
1109 unsigned VarArgsNumFPR,
1110 const PPCSubtarget &Subtarget) {
1112 assert(0 && "VAARG in ELF32 ABI not implemented yet!");
1115 static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
1116 int VarArgsFrameIndex,
1117 int VarArgsStackOffset,
1118 unsigned VarArgsNumGPR,
1119 unsigned VarArgsNumFPR,
1120 const PPCSubtarget &Subtarget) {
1122 if (Subtarget.isMachoABI()) {
1123 // vastart just stores the address of the VarArgsFrameIndex slot into the
1124 // memory location argument.
1125 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1126 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1127 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
1128 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(),
1132 // For ELF 32 ABI we follow the layout of the va_list struct.
1133 // We suppose the given va_list is already allocated.
1136 // char gpr; /* index into the array of 8 GPRs
1137 // * stored in the register save area
1138 // * gpr=0 corresponds to r3,
1139 // * gpr=1 to r4, etc.
1141 // char fpr; /* index into the array of 8 FPRs
1142 // * stored in the register save area
1143 // * fpr=0 corresponds to f1,
1144 // * fpr=1 to f2, etc.
1146 // char *overflow_arg_area;
1147 // /* location on stack that holds
1148 // * the next overflow argument
1150 // char *reg_save_area;
1151 // /* where r3:r10 and f1:f8 (if saved)
1157 SDOperand ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i8);
1158 SDOperand ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i8);
1161 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1163 SDOperand StackOffset = DAG.getFrameIndex(VarArgsStackOffset, PtrVT);
1164 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1166 SDOperand ConstFrameOffset = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8,
1168 SDOperand ConstStackOffset = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8 - 1,
1170 SDOperand ConstFPROffset = DAG.getConstant(1, PtrVT);
1172 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
1174 // Store first byte : number of int regs
1175 SDOperand firstStore = DAG.getStore(Op.getOperand(0), ArgGPR,
1176 Op.getOperand(1), SV->getValue(),
1178 SDOperand nextPtr = DAG.getNode(ISD::ADD, PtrVT, Op.getOperand(1),
1181 // Store second byte : number of float regs
1182 SDOperand secondStore = DAG.getStore(firstStore, ArgFPR, nextPtr,
1183 SV->getValue(), SV->getOffset());
1184 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstStackOffset);
1186 // Store second word : arguments given on stack
1187 SDOperand thirdStore = DAG.getStore(secondStore, StackOffset, nextPtr,
1188 SV->getValue(), SV->getOffset());
1189 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstFrameOffset);
1191 // Store third word : arguments given in registers
1192 return DAG.getStore(thirdStore, FR, nextPtr, SV->getValue(),
1197 #include "PPCGenCallingConv.inc"
1199 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1200 /// depending on which subtarget is selected.
1201 static const unsigned *GetFPR(const PPCSubtarget &Subtarget) {
1202 if (Subtarget.isMachoABI()) {
1203 static const unsigned FPR[] = {
1204 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1205 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1211 static const unsigned FPR[] = {
1212 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1218 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
1219 int &VarArgsFrameIndex,
1220 int &VarArgsStackOffset,
1221 unsigned &VarArgsNumGPR,
1222 unsigned &VarArgsNumFPR,
1223 const PPCSubtarget &Subtarget) {
1224 // TODO: add description of PPC stack frame format, or at least some docs.
1226 MachineFunction &MF = DAG.getMachineFunction();
1227 MachineFrameInfo *MFI = MF.getFrameInfo();
1228 SSARegMap *RegMap = MF.getSSARegMap();
1229 SmallVector<SDOperand, 8> ArgValues;
1230 SDOperand Root = Op.getOperand(0);
1232 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1233 bool isPPC64 = PtrVT == MVT::i64;
1234 bool isMachoABI = Subtarget.isMachoABI();
1235 bool isELF32_ABI = Subtarget.isELF32_ABI();
1236 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1238 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1240 static const unsigned GPR_32[] = { // 32-bit registers.
1241 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1242 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1244 static const unsigned GPR_64[] = { // 64-bit registers.
1245 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1246 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1249 static const unsigned *FPR = GetFPR(Subtarget);
1251 static const unsigned VR[] = {
1252 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1253 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1256 const unsigned Num_GPR_Regs = sizeof(GPR_32)/sizeof(GPR_32[0]);
1257 const unsigned Num_FPR_Regs = isMachoABI ? 13 : 8;
1258 const unsigned Num_VR_Regs = sizeof( VR)/sizeof( VR[0]);
1260 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1262 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1264 // Add DAG nodes to load the arguments or copy them out of registers. On
1265 // entry to a function on PPC, the arguments start after the linkage area,
1266 // although the first ones are often in registers.
1268 // In the ELF 32 ABI, GPRs and stack are double word align: an argument
1269 // represented with two words (long long or double) must be copied to an
1270 // even GPR_idx value or to an even ArgOffset value.
1272 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
1274 bool needsLoad = false;
1275 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
1276 unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8;
1277 unsigned ArgSize = ObjSize;
1278 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(ArgNo+3))->getValue();
1279 unsigned AlignFlag = 1 << ISD::ParamFlags::OrigAlignmentOffs;
1280 // See if next argument requires stack alignment in ELF
1281 bool Expand = (ObjectVT == MVT::f64) || ((ArgNo + 1 < e) &&
1282 (cast<ConstantSDNode>(Op.getOperand(ArgNo+4))->getValue() & AlignFlag) &&
1283 (!(Flags & AlignFlag)));
1285 unsigned CurArgOffset = ArgOffset;
1287 default: assert(0 && "Unhandled argument type!");
1289 // Double word align in ELF
1290 if (Expand && isELF32_ABI) GPR_idx += (GPR_idx % 2);
1291 if (GPR_idx != Num_GPR_Regs) {
1292 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
1293 MF.addLiveIn(GPR[GPR_idx], VReg);
1294 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32);
1298 ArgSize = PtrByteSize;
1300 // Stack align in ELF
1301 if (needsLoad && Expand && isELF32_ABI)
1302 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1303 // All int arguments reserve stack space in Macho ABI.
1304 if (isMachoABI || needsLoad) ArgOffset += PtrByteSize;
1307 case MVT::i64: // PPC64
1308 if (GPR_idx != Num_GPR_Regs) {
1309 unsigned VReg = RegMap->createVirtualRegister(&PPC::G8RCRegClass);
1310 MF.addLiveIn(GPR[GPR_idx], VReg);
1311 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1316 // All int arguments reserve stack space in Macho ABI.
1317 if (isMachoABI || needsLoad) ArgOffset += 8;
1322 // Every 4 bytes of argument space consumes one of the GPRs available for
1323 // argument passing.
1324 if (GPR_idx != Num_GPR_Regs && isMachoABI) {
1326 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
1329 if (FPR_idx != Num_FPR_Regs) {
1331 if (ObjectVT == MVT::f32)
1332 VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass);
1334 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass);
1335 MF.addLiveIn(FPR[FPR_idx], VReg);
1336 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
1342 // Stack align in ELF
1343 if (needsLoad && Expand && isELF32_ABI)
1344 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1345 // All FP arguments reserve stack space in Macho ABI.
1346 if (isMachoABI || needsLoad) ArgOffset += isPPC64 ? 8 : ObjSize;
1352 // Note that vector arguments in registers don't reserve stack space.
1353 if (VR_idx != Num_VR_Regs) {
1354 unsigned VReg = RegMap->createVirtualRegister(&PPC::VRRCRegClass);
1355 MF.addLiveIn(VR[VR_idx], VReg);
1356 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
1359 // This should be simple, but requires getting 16-byte aligned stack
1361 assert(0 && "Loading VR argument not implemented yet!");
1367 // We need to load the argument to a virtual register if we determined above
1368 // that we ran out of physical registers of the appropriate type
1370 // If the argument is actually used, emit a load from the right stack
1372 if (!Op.Val->hasNUsesOfValue(0, ArgNo)) {
1373 int FI = MFI->CreateFixedObject(ObjSize,
1374 CurArgOffset + (ArgSize - ObjSize));
1375 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
1376 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
1378 // Don't emit a dead load.
1379 ArgVal = DAG.getNode(ISD::UNDEF, ObjectVT);
1383 ArgValues.push_back(ArgVal);
1386 // If the function takes variable number of arguments, make a frame index for
1387 // the start of the first vararg value... for expansion of llvm.va_start.
1388 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1393 VarArgsNumGPR = GPR_idx;
1394 VarArgsNumFPR = FPR_idx;
1396 // Make room for Num_GPR_Regs, Num_FPR_Regs and for a possible frame
1398 depth = -(Num_GPR_Regs * MVT::getSizeInBits(PtrVT)/8 +
1399 Num_FPR_Regs * MVT::getSizeInBits(MVT::f64)/8 +
1400 MVT::getSizeInBits(PtrVT)/8);
1402 VarArgsStackOffset = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8,
1409 VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8,
1411 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1413 SmallVector<SDOperand, 8> MemOps;
1415 // In ELF 32 ABI, the fixed integer arguments of a variadic function are
1416 // stored to the VarArgsFrameIndex on the stack.
1418 for (GPR_idx = 0; GPR_idx != VarArgsNumGPR; ++GPR_idx) {
1419 SDOperand Val = DAG.getRegister(GPR[GPR_idx], PtrVT);
1420 SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0);
1421 MemOps.push_back(Store);
1422 // Increment the address by four for the next argument to store
1423 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT);
1424 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1428 // If this function is vararg, store any remaining integer argument regs
1429 // to their spots on the stack so that they may be loaded by deferencing the
1430 // result of va_next.
1431 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
1434 VReg = RegMap->createVirtualRegister(&PPC::G8RCRegClass);
1436 VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
1438 MF.addLiveIn(GPR[GPR_idx], VReg);
1439 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
1440 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1441 MemOps.push_back(Store);
1442 // Increment the address by four for the next argument to store
1443 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT);
1444 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1447 // In ELF 32 ABI, the double arguments are stored to the VarArgsFrameIndex
1450 for (FPR_idx = 0; FPR_idx != VarArgsNumFPR; ++FPR_idx) {
1451 SDOperand Val = DAG.getRegister(FPR[FPR_idx], MVT::f64);
1452 SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0);
1453 MemOps.push_back(Store);
1454 // Increment the address by eight for the next argument to store
1455 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8,
1457 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1460 for (; FPR_idx != Num_FPR_Regs; ++FPR_idx) {
1462 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass);
1464 MF.addLiveIn(FPR[FPR_idx], VReg);
1465 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::f64);
1466 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1467 MemOps.push_back(Store);
1468 // Increment the address by eight for the next argument to store
1469 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8,
1471 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1475 if (!MemOps.empty())
1476 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size());
1479 ArgValues.push_back(Root);
1481 // Return the new list of results.
1482 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
1483 Op.Val->value_end());
1484 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
1487 /// isCallCompatibleAddress - Return the immediate to use if the specified
1488 /// 32-bit value is representable in the immediate field of a BxA instruction.
1489 static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) {
1490 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
1493 int Addr = C->getValue();
1494 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
1495 (Addr << 6 >> 6) != Addr)
1496 return 0; // Top 6 bits have to be sext of immediate.
1498 return DAG.getConstant((int)C->getValue() >> 2, MVT::i32).Val;
1502 static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG,
1503 const PPCSubtarget &Subtarget) {
1504 SDOperand Chain = Op.getOperand(0);
1505 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1506 SDOperand Callee = Op.getOperand(4);
1507 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
1509 bool isMachoABI = Subtarget.isMachoABI();
1510 bool isELF32_ABI = Subtarget.isELF32_ABI();
1512 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1513 bool isPPC64 = PtrVT == MVT::i64;
1514 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1516 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in
1517 // SelectExpr to use to put the arguments in the appropriate registers.
1518 std::vector<SDOperand> args_to_use;
1520 // Count how many bytes are to be pushed on the stack, including the linkage
1521 // area, and parameter passing area. We start with 24/48 bytes, which is
1522 // prereserved space for [SP][CR][LR][3 x unused].
1523 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1525 // Add up all the space actually used.
1526 for (unsigned i = 0; i != NumOps; ++i) {
1527 unsigned ArgSize =MVT::getSizeInBits(Op.getOperand(5+2*i).getValueType())/8;
1528 ArgSize = std::max(ArgSize, PtrByteSize);
1529 NumBytes += ArgSize;
1532 // The prolog code of the callee may store up to 8 GPR argument registers to
1533 // the stack, allowing va_start to index over them in memory if its varargs.
1534 // Because we cannot tell if this is needed on the caller side, we have to
1535 // conservatively assume that it is needed. As such, make sure we have at
1536 // least enough stack space for the caller to store the 8 GPRs.
1537 NumBytes = std::max(NumBytes,
1538 PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI));
1540 // Adjust the stack pointer for the new arguments...
1541 // These operations are automatically eliminated by the prolog/epilog pass
1542 Chain = DAG.getCALLSEQ_START(Chain,
1543 DAG.getConstant(NumBytes, PtrVT));
1545 // Set up a copy of the stack pointer for use loading and storing any
1546 // arguments that may not fit in the registers available for argument
1550 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
1552 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
1554 // Figure out which arguments are going to go in registers, and which in
1555 // memory. Also, if this is a vararg function, floating point operations
1556 // must be stored to our stack, and loaded into integer regs as well, if
1557 // any integer regs are available for argument passing.
1558 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1559 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1561 static const unsigned GPR_32[] = { // 32-bit registers.
1562 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1563 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1565 static const unsigned GPR_64[] = { // 64-bit registers.
1566 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1567 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1569 static const unsigned *FPR = GetFPR(Subtarget);
1571 static const unsigned VR[] = {
1572 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1573 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1575 const unsigned NumGPRs = sizeof(GPR_32)/sizeof(GPR_32[0]);
1576 const unsigned NumFPRs = isMachoABI ? 13 : 8;
1577 const unsigned NumVRs = sizeof( VR)/sizeof( VR[0]);
1579 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1581 std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
1582 SmallVector<SDOperand, 8> MemOpChains;
1583 for (unsigned i = 0; i != NumOps; ++i) {
1585 SDOperand Arg = Op.getOperand(5+2*i);
1586 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue();
1587 unsigned AlignFlag = 1 << ISD::ParamFlags::OrigAlignmentOffs;
1588 // See if next argument requires stack alignment in ELF
1589 unsigned next = 5+2*(i+1)+1;
1590 bool Expand = (Arg.getValueType() == MVT::f64) || ((i + 1 < NumOps) &&
1591 (cast<ConstantSDNode>(Op.getOperand(next))->getValue() & AlignFlag) &&
1592 (!(Flags & AlignFlag)));
1594 // PtrOff will be used to store the current argument to the stack if a
1595 // register cannot be found for it.
1598 // Stack align in ELF 32
1599 if (isELF32_ABI && Expand)
1600 PtrOff = DAG.getConstant(ArgOffset + ((ArgOffset/4) % 2) * PtrByteSize,
1601 StackPtr.getValueType());
1603 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
1605 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff);
1607 // On PPC64, promote integers to 64-bit values.
1608 if (isPPC64 && Arg.getValueType() == MVT::i32) {
1609 unsigned ExtOp = (Flags & 1) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1611 Arg = DAG.getNode(ExtOp, MVT::i64, Arg);
1614 switch (Arg.getValueType()) {
1615 default: assert(0 && "Unexpected ValueType for argument!");
1618 // Double word align in ELF
1619 if (isELF32_ABI && Expand) GPR_idx += (GPR_idx % 2);
1620 if (GPR_idx != NumGPRs) {
1621 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
1623 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1626 if (inMem || isMachoABI) {
1627 // Stack align in ELF
1628 if (isELF32_ABI && Expand)
1629 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1631 ArgOffset += PtrByteSize;
1637 // Float varargs need to be promoted to double.
1638 if (Arg.getValueType() == MVT::f32)
1639 Arg = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Arg);
1642 if (FPR_idx != NumFPRs) {
1643 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
1646 SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
1647 MemOpChains.push_back(Store);
1649 // Float varargs are always shadowed in available integer registers
1650 if (GPR_idx != NumGPRs) {
1651 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
1652 MemOpChains.push_back(Load.getValue(1));
1653 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
1656 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
1657 SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType());
1658 PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour);
1659 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
1660 MemOpChains.push_back(Load.getValue(1));
1661 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
1665 // If we have any FPRs remaining, we may also have GPRs remaining.
1666 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
1669 if (GPR_idx != NumGPRs)
1671 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
1672 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
1677 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1680 if (inMem || isMachoABI) {
1681 // Stack align in ELF
1682 if (isELF32_ABI && Expand)
1683 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1687 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
1694 assert(!isVarArg && "Don't support passing vectors to varargs yet!");
1695 assert(VR_idx != NumVRs &&
1696 "Don't support passing more than 12 vector args yet!");
1697 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
1701 if (!MemOpChains.empty())
1702 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1703 &MemOpChains[0], MemOpChains.size());
1705 // Build a sequence of copy-to-reg nodes chained together with token chain
1706 // and flag operands which copy the outgoing args into the appropriate regs.
1708 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1709 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1711 InFlag = Chain.getValue(1);
1714 // With the ELF 32 ABI, set CR6 to true if this is a vararg call.
1715 if (isVarArg && isELF32_ABI) {
1716 SDOperand SetCR(DAG.getTargetNode(PPC::SETCR, MVT::i32), 0);
1717 Chain = DAG.getCopyToReg(Chain, PPC::CR6, SetCR, InFlag);
1718 InFlag = Chain.getValue(1);
1721 std::vector<MVT::ValueType> NodeTys;
1722 NodeTys.push_back(MVT::Other); // Returns a chain
1723 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
1725 SmallVector<SDOperand, 8> Ops;
1726 unsigned CallOpc = isMachoABI? PPCISD::CALL_Macho : PPCISD::CALL_ELF;
1728 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1729 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1730 // node so that legalize doesn't hack it.
1731 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1732 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
1733 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1734 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType());
1735 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
1736 // If this is an absolute destination address, use the munged value.
1737 Callee = SDOperand(Dest, 0);
1739 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
1740 // to do the call, we can't use PPCISD::CALL.
1741 SDOperand MTCTROps[] = {Chain, Callee, InFlag};
1742 Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+(InFlag.Val!=0));
1743 InFlag = Chain.getValue(1);
1745 // Copy the callee address into R12 on darwin.
1747 Chain = DAG.getCopyToReg(Chain, PPC::R12, Callee, InFlag);
1748 InFlag = Chain.getValue(1);
1752 NodeTys.push_back(MVT::Other);
1753 NodeTys.push_back(MVT::Flag);
1754 Ops.push_back(Chain);
1755 CallOpc = isMachoABI ? PPCISD::BCTRL_Macho : PPCISD::BCTRL_ELF;
1759 // If this is a direct call, pass the chain and the callee.
1761 Ops.push_back(Chain);
1762 Ops.push_back(Callee);
1765 // Add argument registers to the end of the list so that they are known live
1767 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1768 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1769 RegsToPass[i].second.getValueType()));
1772 Ops.push_back(InFlag);
1773 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
1774 InFlag = Chain.getValue(1);
1776 SDOperand ResultVals[3];
1777 unsigned NumResults = 0;
1780 // If the call has results, copy the values out of the ret val registers.
1781 switch (Op.Val->getValueType(0)) {
1782 default: assert(0 && "Unexpected ret value!");
1783 case MVT::Other: break;
1785 if (Op.Val->getValueType(1) == MVT::i32) {
1786 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1);
1787 ResultVals[0] = Chain.getValue(0);
1788 Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32,
1789 Chain.getValue(2)).getValue(1);
1790 ResultVals[1] = Chain.getValue(0);
1792 NodeTys.push_back(MVT::i32);
1794 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1);
1795 ResultVals[0] = Chain.getValue(0);
1798 NodeTys.push_back(MVT::i32);
1801 Chain = DAG.getCopyFromReg(Chain, PPC::X3, MVT::i64, InFlag).getValue(1);
1802 ResultVals[0] = Chain.getValue(0);
1804 NodeTys.push_back(MVT::i64);
1808 Chain = DAG.getCopyFromReg(Chain, PPC::F1, Op.Val->getValueType(0),
1809 InFlag).getValue(1);
1810 ResultVals[0] = Chain.getValue(0);
1812 NodeTys.push_back(Op.Val->getValueType(0));
1818 Chain = DAG.getCopyFromReg(Chain, PPC::V2, Op.Val->getValueType(0),
1819 InFlag).getValue(1);
1820 ResultVals[0] = Chain.getValue(0);
1822 NodeTys.push_back(Op.Val->getValueType(0));
1826 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
1827 DAG.getConstant(NumBytes, PtrVT));
1828 NodeTys.push_back(MVT::Other);
1830 // If the function returns void, just return the chain.
1831 if (NumResults == 0)
1834 // Otherwise, merge everything together with a MERGE_VALUES node.
1835 ResultVals[NumResults++] = Chain;
1836 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys,
1837 ResultVals, NumResults);
1838 return Res.getValue(Op.ResNo);
1841 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG, TargetMachine &TM) {
1842 SmallVector<CCValAssign, 16> RVLocs;
1843 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
1844 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1845 CCState CCInfo(CC, isVarArg, TM, RVLocs);
1846 CCInfo.AnalyzeReturn(Op.Val, RetCC_PPC);
1848 // If this is the first return lowered for this function, add the regs to the
1849 // liveout set for the function.
1850 if (DAG.getMachineFunction().liveout_empty()) {
1851 for (unsigned i = 0; i != RVLocs.size(); ++i)
1852 DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg());
1855 SDOperand Chain = Op.getOperand(0);
1858 // Copy the result values into the output registers.
1859 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1860 CCValAssign &VA = RVLocs[i];
1861 assert(VA.isRegLoc() && "Can only return in registers!");
1862 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
1863 Flag = Chain.getValue(1);
1867 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain, Flag);
1869 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain);
1872 static SDOperand LowerSTACKRESTORE(SDOperand Op, SelectionDAG &DAG,
1873 const PPCSubtarget &Subtarget) {
1874 // When we pop the dynamic allocation we need to restore the SP link.
1876 // Get the corect type for pointers.
1877 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1879 // Construct the stack pointer operand.
1880 bool IsPPC64 = Subtarget.isPPC64();
1881 unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1;
1882 SDOperand StackPtr = DAG.getRegister(SP, PtrVT);
1884 // Get the operands for the STACKRESTORE.
1885 SDOperand Chain = Op.getOperand(0);
1886 SDOperand SaveSP = Op.getOperand(1);
1888 // Load the old link SP.
1889 SDOperand LoadLinkSP = DAG.getLoad(PtrVT, Chain, StackPtr, NULL, 0);
1891 // Restore the stack pointer.
1892 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), SP, SaveSP);
1894 // Store the old link SP.
1895 return DAG.getStore(Chain, LoadLinkSP, StackPtr, NULL, 0);
1898 static SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG,
1899 const PPCSubtarget &Subtarget) {
1900 MachineFunction &MF = DAG.getMachineFunction();
1901 bool IsPPC64 = Subtarget.isPPC64();
1902 bool isMachoABI = Subtarget.isMachoABI();
1904 // Get current frame pointer save index. The users of this index will be
1905 // primarily DYNALLOC instructions.
1906 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1907 int FPSI = FI->getFramePointerSaveIndex();
1909 // If the frame pointer save index hasn't been defined yet.
1911 // Find out what the fix offset of the frame pointer save area.
1912 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isMachoABI);
1914 // Allocate the frame index for frame pointer save area.
1915 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
1917 FI->setFramePointerSaveIndex(FPSI);
1921 SDOperand Chain = Op.getOperand(0);
1922 SDOperand Size = Op.getOperand(1);
1924 // Get the corect type for pointers.
1925 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1927 SDOperand NegSize = DAG.getNode(ISD::SUB, PtrVT,
1928 DAG.getConstant(0, PtrVT), Size);
1929 // Construct a node for the frame pointer save index.
1930 SDOperand FPSIdx = DAG.getFrameIndex(FPSI, PtrVT);
1931 // Build a DYNALLOC node.
1932 SDOperand Ops[3] = { Chain, NegSize, FPSIdx };
1933 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
1934 return DAG.getNode(PPCISD::DYNALLOC, VTs, Ops, 3);
1938 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
1940 static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
1941 // Not FP? Not a fsel.
1942 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) ||
1943 !MVT::isFloatingPoint(Op.getOperand(2).getValueType()))
1946 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1948 // Cannot handle SETEQ/SETNE.
1949 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand();
1951 MVT::ValueType ResVT = Op.getValueType();
1952 MVT::ValueType CmpVT = Op.getOperand(0).getValueType();
1953 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
1954 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3);
1956 // If the RHS of the comparison is a 0.0, we don't need to do the
1957 // subtraction at all.
1958 if (isFloatingPointZero(RHS))
1960 default: break; // SETUO etc aren't handled by fsel.
1964 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
1968 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
1969 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
1970 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
1974 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
1978 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
1979 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
1980 return DAG.getNode(PPCISD::FSEL, ResVT,
1981 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV);
1986 default: break; // SETUO etc aren't handled by fsel.
1990 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
1991 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1992 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1993 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
1997 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
1998 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1999 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2000 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
2004 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
2005 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2006 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2007 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
2011 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
2012 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2013 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2014 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
2019 static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
2020 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType()));
2021 SDOperand Src = Op.getOperand(0);
2022 if (Src.getValueType() == MVT::f32)
2023 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src);
2026 switch (Op.getValueType()) {
2027 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
2029 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src);
2032 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src);
2036 // Convert the FP value to an int value through memory.
2037 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Tmp);
2038 if (Op.getValueType() == MVT::i32)
2039 Bits = DAG.getNode(ISD::TRUNCATE, MVT::i32, Bits);
2043 static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
2044 if (Op.getOperand(0).getValueType() == MVT::i64) {
2045 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
2046 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
2047 if (Op.getValueType() == MVT::f32)
2048 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
2052 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
2053 "Unhandled SINT_TO_FP type in custom expander!");
2054 // Since we only generate this in 64-bit mode, we can take advantage of
2055 // 64-bit registers. In particular, sign extend the input value into the
2056 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
2057 // then lfd it and fcfid it.
2058 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
2059 int FrameIdx = FrameInfo->CreateStackObject(8, 8);
2060 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2061 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
2063 SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32,
2066 // STD the extended value into the stack slot.
2067 SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other,
2068 DAG.getEntryNode(), Ext64, FIdx,
2069 DAG.getSrcValue(NULL));
2070 // Load the value as a double.
2071 SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0);
2073 // FCFID it and return it.
2074 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld);
2075 if (Op.getValueType() == MVT::f32)
2076 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
2080 static SDOperand LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) {
2081 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
2082 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
2084 // Expand into a bunch of logical ops. Note that these ops
2085 // depend on the PPC behavior for oversized shift amounts.
2086 SDOperand Lo = Op.getOperand(0);
2087 SDOperand Hi = Op.getOperand(1);
2088 SDOperand Amt = Op.getOperand(2);
2090 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
2091 DAG.getConstant(32, MVT::i32), Amt);
2092 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt);
2093 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1);
2094 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
2095 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
2096 DAG.getConstant(-32U, MVT::i32));
2097 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5);
2098 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
2099 SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt);
2100 SDOperand OutOps[] = { OutLo, OutHi };
2101 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
2105 static SDOperand LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) {
2106 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
2107 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRL!");
2109 // Otherwise, expand into a bunch of logical ops. Note that these ops
2110 // depend on the PPC behavior for oversized shift amounts.
2111 SDOperand Lo = Op.getOperand(0);
2112 SDOperand Hi = Op.getOperand(1);
2113 SDOperand Amt = Op.getOperand(2);
2115 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
2116 DAG.getConstant(32, MVT::i32), Amt);
2117 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
2118 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
2119 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
2120 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
2121 DAG.getConstant(-32U, MVT::i32));
2122 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5);
2123 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
2124 SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt);
2125 SDOperand OutOps[] = { OutLo, OutHi };
2126 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
2130 static SDOperand LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) {
2131 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
2132 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!");
2134 // Otherwise, expand into a bunch of logical ops, followed by a select_cc.
2135 SDOperand Lo = Op.getOperand(0);
2136 SDOperand Hi = Op.getOperand(1);
2137 SDOperand Amt = Op.getOperand(2);
2139 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
2140 DAG.getConstant(32, MVT::i32), Amt);
2141 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
2142 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
2143 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
2144 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
2145 DAG.getConstant(-32U, MVT::i32));
2146 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5);
2147 SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt);
2148 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32),
2149 Tmp4, Tmp6, ISD::SETLE);
2150 SDOperand OutOps[] = { OutLo, OutHi };
2151 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
2155 //===----------------------------------------------------------------------===//
2156 // Vector related lowering.
2159 // If this is a vector of constants or undefs, get the bits. A bit in
2160 // UndefBits is set if the corresponding element of the vector is an
2161 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
2162 // zero. Return true if this is not an array of constants, false if it is.
2164 static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
2165 uint64_t UndefBits[2]) {
2166 // Start with zero'd results.
2167 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0;
2169 unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType());
2170 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
2171 SDOperand OpVal = BV->getOperand(i);
2173 unsigned PartNo = i >= e/2; // In the upper 128 bits?
2174 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t.
2176 uint64_t EltBits = 0;
2177 if (OpVal.getOpcode() == ISD::UNDEF) {
2178 uint64_t EltUndefBits = ~0U >> (32-EltBitSize);
2179 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize);
2181 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
2182 EltBits = CN->getValue() & (~0U >> (32-EltBitSize));
2183 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
2184 assert(CN->getValueType(0) == MVT::f32 &&
2185 "Only one legal FP vector type!");
2186 EltBits = FloatToBits(CN->getValue());
2188 // Nonconstant element.
2192 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize);
2195 //printf("%llx %llx %llx %llx\n",
2196 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]);
2200 // If this is a splat (repetition) of a value across the whole vector, return
2201 // the smallest size that splats it. For example, "0x01010101010101..." is a
2202 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
2203 // SplatSize = 1 byte.
2204 static bool isConstantSplat(const uint64_t Bits128[2],
2205 const uint64_t Undef128[2],
2206 unsigned &SplatBits, unsigned &SplatUndef,
2207 unsigned &SplatSize) {
2209 // Don't let undefs prevent splats from matching. See if the top 64-bits are
2210 // the same as the lower 64-bits, ignoring undefs.
2211 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0]))
2212 return false; // Can't be a splat if two pieces don't match.
2214 uint64_t Bits64 = Bits128[0] | Bits128[1];
2215 uint64_t Undef64 = Undef128[0] & Undef128[1];
2217 // Check that the top 32-bits are the same as the lower 32-bits, ignoring
2219 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64))
2220 return false; // Can't be a splat if two pieces don't match.
2222 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32);
2223 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32);
2225 // If the top 16-bits are different than the lower 16-bits, ignoring
2226 // undefs, we have an i32 splat.
2227 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) {
2229 SplatUndef = Undef32;
2234 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16);
2235 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16);
2237 // If the top 8-bits are different than the lower 8-bits, ignoring
2238 // undefs, we have an i16 splat.
2239 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) {
2241 SplatUndef = Undef16;
2246 // Otherwise, we have an 8-bit splat.
2247 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8);
2248 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8);
2253 /// BuildSplatI - Build a canonical splati of Val with an element size of
2254 /// SplatSize. Cast the result to VT.
2255 static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT,
2256 SelectionDAG &DAG) {
2257 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
2259 static const MVT::ValueType VTys[] = { // canonical VT to use for each size.
2260 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
2263 MVT::ValueType ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
2265 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
2269 MVT::ValueType CanonicalVT = VTys[SplatSize-1];
2271 // Build a canonical splat for this value.
2272 SDOperand Elt = DAG.getConstant(Val, MVT::getVectorElementType(CanonicalVT));
2273 SmallVector<SDOperand, 8> Ops;
2274 Ops.assign(MVT::getVectorNumElements(CanonicalVT), Elt);
2275 SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT,
2276 &Ops[0], Ops.size());
2277 return DAG.getNode(ISD::BIT_CONVERT, ReqVT, Res);
2280 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
2281 /// specified intrinsic ID.
2282 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS,
2284 MVT::ValueType DestVT = MVT::Other) {
2285 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
2286 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
2287 DAG.getConstant(IID, MVT::i32), LHS, RHS);
2290 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
2291 /// specified intrinsic ID.
2292 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1,
2293 SDOperand Op2, SelectionDAG &DAG,
2294 MVT::ValueType DestVT = MVT::Other) {
2295 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
2296 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
2297 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
2301 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
2302 /// amount. The result has the specified value type.
2303 static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt,
2304 MVT::ValueType VT, SelectionDAG &DAG) {
2305 // Force LHS/RHS to be the right type.
2306 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS);
2307 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS);
2310 for (unsigned i = 0; i != 16; ++i)
2311 Ops[i] = DAG.getConstant(i+Amt, MVT::i32);
2312 SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS,
2313 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16));
2314 return DAG.getNode(ISD::BIT_CONVERT, VT, T);
2317 // If this is a case we can't handle, return null and let the default
2318 // expansion code take care of it. If we CAN select this case, and if it
2319 // selects to a single instruction, return Op. Otherwise, if we can codegen
2320 // this case more efficiently than a constant pool load, lower it to the
2321 // sequence of ops that should be used.
2322 static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2323 // If this is a vector of constants or undefs, get the bits. A bit in
2324 // UndefBits is set if the corresponding element of the vector is an
2325 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
2327 uint64_t VectorBits[2];
2328 uint64_t UndefBits[2];
2329 if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits))
2330 return SDOperand(); // Not a constant vector.
2332 // If this is a splat (repetition) of a value across the whole vector, return
2333 // the smallest size that splats it. For example, "0x01010101010101..." is a
2334 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
2335 // SplatSize = 1 byte.
2336 unsigned SplatBits, SplatUndef, SplatSize;
2337 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){
2338 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0;
2340 // First, handle single instruction cases.
2343 if (SplatBits == 0) {
2344 // Canonicalize all zero vectors to be v4i32.
2345 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
2346 SDOperand Z = DAG.getConstant(0, MVT::i32);
2347 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z);
2348 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z);
2353 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
2354 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize);
2355 if (SextVal >= -16 && SextVal <= 15)
2356 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG);
2359 // Two instruction sequences.
2361 // If this value is in the range [-32,30] and is even, use:
2362 // tmp = VSPLTI[bhw], result = add tmp, tmp
2363 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
2364 Op = BuildSplatI(SextVal >> 1, SplatSize, Op.getValueType(), DAG);
2365 return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op);
2368 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
2369 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
2371 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
2372 // Make -1 and vspltisw -1:
2373 SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG);
2375 // Make the VSLW intrinsic, computing 0x8000_0000.
2376 SDOperand Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
2379 // xor by OnesV to invert it.
2380 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV);
2381 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2384 // Check to see if this is a wide variety of vsplti*, binop self cases.
2385 unsigned SplatBitSize = SplatSize*8;
2386 static const signed char SplatCsts[] = {
2387 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
2388 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
2391 for (unsigned idx = 0; idx < sizeof(SplatCsts)/sizeof(SplatCsts[0]); ++idx){
2392 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
2393 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
2394 int i = SplatCsts[idx];
2396 // Figure out what shift amount will be used by altivec if shifted by i in
2398 unsigned TypeShiftAmt = i & (SplatBitSize-1);
2400 // vsplti + shl self.
2401 if (SextVal == (i << (int)TypeShiftAmt)) {
2402 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2403 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2404 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
2405 Intrinsic::ppc_altivec_vslw
2407 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2408 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2411 // vsplti + srl self.
2412 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
2413 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2414 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2415 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
2416 Intrinsic::ppc_altivec_vsrw
2418 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2419 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2422 // vsplti + sra self.
2423 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
2424 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2425 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2426 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
2427 Intrinsic::ppc_altivec_vsraw
2429 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2430 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2433 // vsplti + rol self.
2434 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
2435 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
2436 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2437 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2438 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
2439 Intrinsic::ppc_altivec_vrlw
2441 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2442 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2445 // t = vsplti c, result = vsldoi t, t, 1
2446 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
2447 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2448 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG);
2450 // t = vsplti c, result = vsldoi t, t, 2
2451 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
2452 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2453 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG);
2455 // t = vsplti c, result = vsldoi t, t, 3
2456 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
2457 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2458 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG);
2462 // Three instruction sequences.
2464 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
2465 if (SextVal >= 0 && SextVal <= 31) {
2466 SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG);
2467 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
2468 LHS = DAG.getNode(ISD::SUB, Op.getValueType(), LHS, RHS);
2469 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
2471 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
2472 if (SextVal >= -31 && SextVal <= 0) {
2473 SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG);
2474 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
2475 LHS = DAG.getNode(ISD::ADD, Op.getValueType(), LHS, RHS);
2476 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
2483 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
2484 /// the specified operations to build the shuffle.
2485 static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS,
2486 SDOperand RHS, SelectionDAG &DAG) {
2487 unsigned OpNum = (PFEntry >> 26) & 0x0F;
2488 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
2489 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
2492 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
2504 if (OpNum == OP_COPY) {
2505 if (LHSID == (1*9+2)*9+3) return LHS;
2506 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
2510 SDOperand OpLHS, OpRHS;
2511 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG);
2512 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG);
2514 unsigned ShufIdxs[16];
2516 default: assert(0 && "Unknown i32 permute!");
2518 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
2519 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
2520 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
2521 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
2524 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
2525 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
2526 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
2527 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
2530 for (unsigned i = 0; i != 16; ++i)
2531 ShufIdxs[i] = (i&3)+0;
2534 for (unsigned i = 0; i != 16; ++i)
2535 ShufIdxs[i] = (i&3)+4;
2538 for (unsigned i = 0; i != 16; ++i)
2539 ShufIdxs[i] = (i&3)+8;
2542 for (unsigned i = 0; i != 16; ++i)
2543 ShufIdxs[i] = (i&3)+12;
2546 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG);
2548 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG);
2550 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG);
2553 for (unsigned i = 0; i != 16; ++i)
2554 Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i32);
2556 return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS,
2557 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
2560 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
2561 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
2562 /// return the code it can be lowered into. Worst case, it can always be
2563 /// lowered into a vperm.
2564 static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
2565 SDOperand V1 = Op.getOperand(0);
2566 SDOperand V2 = Op.getOperand(1);
2567 SDOperand PermMask = Op.getOperand(2);
2569 // Cases that are handled by instructions that take permute immediates
2570 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
2571 // selected by the instruction selector.
2572 if (V2.getOpcode() == ISD::UNDEF) {
2573 if (PPC::isSplatShuffleMask(PermMask.Val, 1) ||
2574 PPC::isSplatShuffleMask(PermMask.Val, 2) ||
2575 PPC::isSplatShuffleMask(PermMask.Val, 4) ||
2576 PPC::isVPKUWUMShuffleMask(PermMask.Val, true) ||
2577 PPC::isVPKUHUMShuffleMask(PermMask.Val, true) ||
2578 PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 ||
2579 PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) ||
2580 PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) ||
2581 PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) ||
2582 PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) ||
2583 PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) ||
2584 PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) {
2589 // Altivec has a variety of "shuffle immediates" that take two vector inputs
2590 // and produce a fixed permutation. If any of these match, do not lower to
2592 if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) ||
2593 PPC::isVPKUHUMShuffleMask(PermMask.Val, false) ||
2594 PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 ||
2595 PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) ||
2596 PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) ||
2597 PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) ||
2598 PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) ||
2599 PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) ||
2600 PPC::isVMRGHShuffleMask(PermMask.Val, 4, false))
2603 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
2604 // perfect shuffle table to emit an optimal matching sequence.
2605 unsigned PFIndexes[4];
2606 bool isFourElementShuffle = true;
2607 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
2608 unsigned EltNo = 8; // Start out undef.
2609 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
2610 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF)
2611 continue; // Undef, ignore it.
2613 unsigned ByteSource =
2614 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue();
2615 if ((ByteSource & 3) != j) {
2616 isFourElementShuffle = false;
2621 EltNo = ByteSource/4;
2622 } else if (EltNo != ByteSource/4) {
2623 isFourElementShuffle = false;
2627 PFIndexes[i] = EltNo;
2630 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
2631 // perfect shuffle vector to determine if it is cost effective to do this as
2632 // discrete instructions, or whether we should use a vperm.
2633 if (isFourElementShuffle) {
2634 // Compute the index in the perfect shuffle table.
2635 unsigned PFTableIndex =
2636 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
2638 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
2639 unsigned Cost = (PFEntry >> 30);
2641 // Determining when to avoid vperm is tricky. Many things affect the cost
2642 // of vperm, particularly how many times the perm mask needs to be computed.
2643 // For example, if the perm mask can be hoisted out of a loop or is already
2644 // used (perhaps because there are multiple permutes with the same shuffle
2645 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
2646 // the loop requires an extra register.
2648 // As a compromise, we only emit discrete instructions if the shuffle can be
2649 // generated in 3 or fewer operations. When we have loop information
2650 // available, if this block is within a loop, we should avoid using vperm
2651 // for 3-operation perms and use a constant pool load instead.
2653 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG);
2656 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
2657 // vector that will get spilled to the constant pool.
2658 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
2660 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
2661 // that it is in input element units, not in bytes. Convert now.
2662 MVT::ValueType EltVT = MVT::getVectorElementType(V1.getValueType());
2663 unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8;
2665 SmallVector<SDOperand, 16> ResultMask;
2666 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
2668 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
2671 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue();
2673 for (unsigned j = 0; j != BytesPerElement; ++j)
2674 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
2678 SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8,
2679 &ResultMask[0], ResultMask.size());
2680 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
2683 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
2684 /// altivec comparison. If it is, return true and fill in Opc/isDot with
2685 /// information about the intrinsic.
2686 static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc,
2688 unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue();
2691 switch (IntrinsicID) {
2692 default: return false;
2693 // Comparison predicates.
2694 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
2695 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
2696 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
2697 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
2698 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
2699 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
2700 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
2701 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
2702 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
2703 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
2704 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
2705 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
2706 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
2708 // Normal Comparisons.
2709 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
2710 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
2711 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
2712 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
2713 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
2714 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
2715 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
2716 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
2717 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
2718 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
2719 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
2720 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
2721 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
2726 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
2727 /// lower, do it, otherwise return null.
2728 static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
2729 // If this is a lowered altivec predicate compare, CompareOpc is set to the
2730 // opcode number of the comparison.
2733 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
2734 return SDOperand(); // Don't custom lower most intrinsics.
2736 // If this is a non-dot comparison, make the VCMP node and we are done.
2738 SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(),
2739 Op.getOperand(1), Op.getOperand(2),
2740 DAG.getConstant(CompareOpc, MVT::i32));
2741 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp);
2744 // Create the PPCISD altivec 'dot' comparison node.
2746 Op.getOperand(2), // LHS
2747 Op.getOperand(3), // RHS
2748 DAG.getConstant(CompareOpc, MVT::i32)
2750 std::vector<MVT::ValueType> VTs;
2751 VTs.push_back(Op.getOperand(2).getValueType());
2752 VTs.push_back(MVT::Flag);
2753 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
2755 // Now that we have the comparison, emit a copy from the CR to a GPR.
2756 // This is flagged to the above dot comparison.
2757 SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32,
2758 DAG.getRegister(PPC::CR6, MVT::i32),
2759 CompNode.getValue(1));
2761 // Unpack the result based on how the target uses it.
2762 unsigned BitNo; // Bit # of CR6.
2763 bool InvertBit; // Invert result?
2764 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
2765 default: // Can't happen, don't crash on invalid number though.
2766 case 0: // Return the value of the EQ bit of CR6.
2767 BitNo = 0; InvertBit = false;
2769 case 1: // Return the inverted value of the EQ bit of CR6.
2770 BitNo = 0; InvertBit = true;
2772 case 2: // Return the value of the LT bit of CR6.
2773 BitNo = 2; InvertBit = false;
2775 case 3: // Return the inverted value of the LT bit of CR6.
2776 BitNo = 2; InvertBit = true;
2780 // Shift the bit into the low position.
2781 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags,
2782 DAG.getConstant(8-(3-BitNo), MVT::i32));
2784 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags,
2785 DAG.getConstant(1, MVT::i32));
2787 // If we are supposed to, toggle the bit.
2789 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags,
2790 DAG.getConstant(1, MVT::i32));
2794 static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2795 // Create a stack slot that is 16-byte aligned.
2796 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
2797 int FrameIdx = FrameInfo->CreateStackObject(16, 16);
2798 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2799 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
2801 // Store the input value into Value#0 of the stack slot.
2802 SDOperand Store = DAG.getStore(DAG.getEntryNode(),
2803 Op.getOperand(0), FIdx, NULL, 0);
2805 return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0);
2808 static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) {
2809 if (Op.getValueType() == MVT::v4i32) {
2810 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2812 SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG);
2813 SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt.
2815 SDOperand RHSSwap = // = vrlw RHS, 16
2816 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG);
2818 // Shrinkify inputs to v8i16.
2819 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS);
2820 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS);
2821 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap);
2823 // Low parts multiplied together, generating 32-bit results (we ignore the
2825 SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
2826 LHS, RHS, DAG, MVT::v4i32);
2828 SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
2829 LHS, RHSSwap, Zero, DAG, MVT::v4i32);
2830 // Shift the high parts up 16 bits.
2831 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG);
2832 return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd);
2833 } else if (Op.getValueType() == MVT::v8i16) {
2834 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2836 SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG);
2838 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
2839 LHS, RHS, Zero, DAG);
2840 } else if (Op.getValueType() == MVT::v16i8) {
2841 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2843 // Multiply the even 8-bit parts, producing 16-bit sums.
2844 SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
2845 LHS, RHS, DAG, MVT::v8i16);
2846 EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts);
2848 // Multiply the odd 8-bit parts, producing 16-bit sums.
2849 SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
2850 LHS, RHS, DAG, MVT::v8i16);
2851 OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts);
2853 // Merge the results together.
2855 for (unsigned i = 0; i != 8; ++i) {
2856 Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8);
2857 Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8);
2859 return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts,
2860 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
2862 assert(0 && "Unknown mul to lower!");
2867 /// LowerOperation - Provide custom lowering hooks for some operations.
2869 SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
2870 switch (Op.getOpcode()) {
2871 default: assert(0 && "Wasn't expecting to be able to lower this!");
2872 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2873 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
2874 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
2875 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
2876 case ISD::SETCC: return LowerSETCC(Op, DAG);
2878 return LowerVASTART(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
2879 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
2882 return LowerVAARG(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
2883 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
2885 case ISD::FORMAL_ARGUMENTS:
2886 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex,
2887 VarArgsStackOffset, VarArgsNumGPR,
2888 VarArgsNumFPR, PPCSubTarget);
2890 case ISD::CALL: return LowerCALL(Op, DAG, PPCSubTarget);
2891 case ISD::RET: return LowerRET(Op, DAG, getTargetMachine());
2892 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
2893 case ISD::DYNAMIC_STACKALLOC:
2894 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
2896 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
2897 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
2898 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
2900 // Lower 64-bit shifts.
2901 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
2902 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
2903 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
2905 // Vector-related lowering.
2906 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
2907 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2908 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2909 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
2910 case ISD::MUL: return LowerMUL(Op, DAG);
2912 // Frame & Return address. Currently unimplemented
2913 case ISD::RETURNADDR: break;
2914 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
2919 //===----------------------------------------------------------------------===//
2920 // Other Lowering Code
2921 //===----------------------------------------------------------------------===//
2924 PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
2925 MachineBasicBlock *BB) {
2926 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2927 assert((MI->getOpcode() == PPC::SELECT_CC_I4 ||
2928 MI->getOpcode() == PPC::SELECT_CC_I8 ||
2929 MI->getOpcode() == PPC::SELECT_CC_F4 ||
2930 MI->getOpcode() == PPC::SELECT_CC_F8 ||
2931 MI->getOpcode() == PPC::SELECT_CC_VRRC) &&
2932 "Unexpected instr type to insert");
2934 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
2935 // control-flow pattern. The incoming instruction knows the destination vreg
2936 // to set, the condition code register to branch on, the true/false values to
2937 // select between, and a branch opcode to use.
2938 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2939 ilist<MachineBasicBlock>::iterator It = BB;
2945 // cmpTY ccX, r1, r2
2947 // fallthrough --> copy0MBB
2948 MachineBasicBlock *thisMBB = BB;
2949 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
2950 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
2951 unsigned SelectPred = MI->getOperand(4).getImm();
2952 BuildMI(BB, TII->get(PPC::BCC))
2953 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
2954 MachineFunction *F = BB->getParent();
2955 F->getBasicBlockList().insert(It, copy0MBB);
2956 F->getBasicBlockList().insert(It, sinkMBB);
2957 // Update machine-CFG edges by first adding all successors of the current
2958 // block to the new block which will contain the Phi node for the select.
2959 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
2960 e = BB->succ_end(); i != e; ++i)
2961 sinkMBB->addSuccessor(*i);
2962 // Next, remove all successors of the current block, and add the true
2963 // and fallthrough blocks as its successors.
2964 while(!BB->succ_empty())
2965 BB->removeSuccessor(BB->succ_begin());
2966 BB->addSuccessor(copy0MBB);
2967 BB->addSuccessor(sinkMBB);
2970 // %FalseValue = ...
2971 // # fallthrough to sinkMBB
2974 // Update machine-CFG edges
2975 BB->addSuccessor(sinkMBB);
2978 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
2981 BuildMI(BB, TII->get(PPC::PHI), MI->getOperand(0).getReg())
2982 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
2983 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
2985 delete MI; // The pseudo instruction is gone now.
2989 //===----------------------------------------------------------------------===//
2990 // Target Optimization Hooks
2991 //===----------------------------------------------------------------------===//
2993 SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
2994 DAGCombinerInfo &DCI) const {
2995 TargetMachine &TM = getTargetMachine();
2996 SelectionDAG &DAG = DCI.DAG;
2997 switch (N->getOpcode()) {
3000 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
3001 if (C->getValue() == 0) // 0 << V -> 0.
3002 return N->getOperand(0);
3006 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
3007 if (C->getValue() == 0) // 0 >>u V -> 0.
3008 return N->getOperand(0);
3012 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
3013 if (C->getValue() == 0 || // 0 >>s V -> 0.
3014 C->isAllOnesValue()) // -1 >>s V -> -1.
3015 return N->getOperand(0);
3019 case ISD::SINT_TO_FP:
3020 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
3021 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
3022 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
3023 // We allow the src/dst to be either f32/f64, but the intermediate
3024 // type must be i64.
3025 if (N->getOperand(0).getValueType() == MVT::i64) {
3026 SDOperand Val = N->getOperand(0).getOperand(0);
3027 if (Val.getValueType() == MVT::f32) {
3028 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
3029 DCI.AddToWorklist(Val.Val);
3032 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val);
3033 DCI.AddToWorklist(Val.Val);
3034 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val);
3035 DCI.AddToWorklist(Val.Val);
3036 if (N->getValueType(0) == MVT::f32) {
3037 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val);
3038 DCI.AddToWorklist(Val.Val);
3041 } else if (N->getOperand(0).getValueType() == MVT::i32) {
3042 // If the intermediate type is i32, we can avoid the load/store here
3049 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
3050 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
3051 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
3052 N->getOperand(1).getValueType() == MVT::i32) {
3053 SDOperand Val = N->getOperand(1).getOperand(0);
3054 if (Val.getValueType() == MVT::f32) {
3055 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
3056 DCI.AddToWorklist(Val.Val);
3058 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val);
3059 DCI.AddToWorklist(Val.Val);
3061 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val,
3062 N->getOperand(2), N->getOperand(3));
3063 DCI.AddToWorklist(Val.Val);
3067 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
3068 if (N->getOperand(1).getOpcode() == ISD::BSWAP &&
3069 N->getOperand(1).Val->hasOneUse() &&
3070 (N->getOperand(1).getValueType() == MVT::i32 ||
3071 N->getOperand(1).getValueType() == MVT::i16)) {
3072 SDOperand BSwapOp = N->getOperand(1).getOperand(0);
3073 // Do an any-extend to 32-bits if this is a half-word input.
3074 if (BSwapOp.getValueType() == MVT::i16)
3075 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp);
3077 return DAG.getNode(PPCISD::STBRX, MVT::Other, N->getOperand(0), BSwapOp,
3078 N->getOperand(2), N->getOperand(3),
3079 DAG.getValueType(N->getOperand(1).getValueType()));
3083 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
3084 if (ISD::isNON_EXTLoad(N->getOperand(0).Val) &&
3085 N->getOperand(0).hasOneUse() &&
3086 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
3087 SDOperand Load = N->getOperand(0);
3088 LoadSDNode *LD = cast<LoadSDNode>(Load);
3089 // Create the byte-swapping load.
3090 std::vector<MVT::ValueType> VTs;
3091 VTs.push_back(MVT::i32);
3092 VTs.push_back(MVT::Other);
3093 SDOperand SV = DAG.getSrcValue(LD->getSrcValue(), LD->getSrcValueOffset());
3095 LD->getChain(), // Chain
3096 LD->getBasePtr(), // Ptr
3098 DAG.getValueType(N->getValueType(0)) // VT
3100 SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4);
3102 // If this is an i16 load, insert the truncate.
3103 SDOperand ResVal = BSLoad;
3104 if (N->getValueType(0) == MVT::i16)
3105 ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad);
3107 // First, combine the bswap away. This makes the value produced by the
3109 DCI.CombineTo(N, ResVal);
3111 // Next, combine the load away, we give it a bogus result value but a real
3112 // chain result. The result value is dead because the bswap is dead.
3113 DCI.CombineTo(Load.Val, ResVal, BSLoad.getValue(1));
3115 // Return N so it doesn't get rechecked!
3116 return SDOperand(N, 0);
3120 case PPCISD::VCMP: {
3121 // If a VCMPo node already exists with exactly the same operands as this
3122 // node, use its result instead of this node (VCMPo computes both a CR6 and
3123 // a normal output).
3125 if (!N->getOperand(0).hasOneUse() &&
3126 !N->getOperand(1).hasOneUse() &&
3127 !N->getOperand(2).hasOneUse()) {
3129 // Scan all of the users of the LHS, looking for VCMPo's that match.
3130 SDNode *VCMPoNode = 0;
3132 SDNode *LHSN = N->getOperand(0).Val;
3133 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
3135 if ((*UI)->getOpcode() == PPCISD::VCMPo &&
3136 (*UI)->getOperand(1) == N->getOperand(1) &&
3137 (*UI)->getOperand(2) == N->getOperand(2) &&
3138 (*UI)->getOperand(0) == N->getOperand(0)) {
3143 // If there is no VCMPo node, or if the flag value has a single use, don't
3145 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
3148 // Look at the (necessarily single) use of the flag value. If it has a
3149 // chain, this transformation is more complex. Note that multiple things
3150 // could use the value result, which we should ignore.
3151 SDNode *FlagUser = 0;
3152 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
3153 FlagUser == 0; ++UI) {
3154 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
3156 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
3157 if (User->getOperand(i) == SDOperand(VCMPoNode, 1)) {
3164 // If the user is a MFCR instruction, we know this is safe. Otherwise we
3165 // give up for right now.
3166 if (FlagUser->getOpcode() == PPCISD::MFCR)
3167 return SDOperand(VCMPoNode, 0);
3172 // If this is a branch on an altivec predicate comparison, lower this so
3173 // that we don't have to do a MFCR: instead, branch directly on CR6. This
3174 // lowering is done pre-legalize, because the legalizer lowers the predicate
3175 // compare down to code that is difficult to reassemble.
3176 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
3177 SDOperand LHS = N->getOperand(2), RHS = N->getOperand(3);
3181 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
3182 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
3183 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
3184 assert(isDot && "Can't compare against a vector result!");
3186 // If this is a comparison against something other than 0/1, then we know
3187 // that the condition is never/always true.
3188 unsigned Val = cast<ConstantSDNode>(RHS)->getValue();
3189 if (Val != 0 && Val != 1) {
3190 if (CC == ISD::SETEQ) // Cond never true, remove branch.
3191 return N->getOperand(0);
3192 // Always !=, turn it into an unconditional branch.
3193 return DAG.getNode(ISD::BR, MVT::Other,
3194 N->getOperand(0), N->getOperand(4));
3197 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
3199 // Create the PPCISD altivec 'dot' comparison node.
3200 std::vector<MVT::ValueType> VTs;
3202 LHS.getOperand(2), // LHS of compare
3203 LHS.getOperand(3), // RHS of compare
3204 DAG.getConstant(CompareOpc, MVT::i32)
3206 VTs.push_back(LHS.getOperand(2).getValueType());
3207 VTs.push_back(MVT::Flag);
3208 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
3210 // Unpack the result based on how the target uses it.
3211 PPC::Predicate CompOpc;
3212 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) {
3213 default: // Can't happen, don't crash on invalid number though.
3214 case 0: // Branch on the value of the EQ bit of CR6.
3215 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
3217 case 1: // Branch on the inverted value of the EQ bit of CR6.
3218 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
3220 case 2: // Branch on the value of the LT bit of CR6.
3221 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
3223 case 3: // Branch on the inverted value of the LT bit of CR6.
3224 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
3228 return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0),
3229 DAG.getConstant(CompOpc, MVT::i32),
3230 DAG.getRegister(PPC::CR6, MVT::i32),
3231 N->getOperand(4), CompNode.getValue(1));
3240 //===----------------------------------------------------------------------===//
3241 // Inline Assembly Support
3242 //===----------------------------------------------------------------------===//
3244 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
3246 uint64_t &KnownZero,
3248 const SelectionDAG &DAG,
3249 unsigned Depth) const {
3252 switch (Op.getOpcode()) {
3254 case PPCISD::LBRX: {
3255 // lhbrx is known to have the top bits cleared out.
3256 if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16)
3257 KnownZero = 0xFFFF0000;
3260 case ISD::INTRINSIC_WO_CHAIN: {
3261 switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) {
3263 case Intrinsic::ppc_altivec_vcmpbfp_p:
3264 case Intrinsic::ppc_altivec_vcmpeqfp_p:
3265 case Intrinsic::ppc_altivec_vcmpequb_p:
3266 case Intrinsic::ppc_altivec_vcmpequh_p:
3267 case Intrinsic::ppc_altivec_vcmpequw_p:
3268 case Intrinsic::ppc_altivec_vcmpgefp_p:
3269 case Intrinsic::ppc_altivec_vcmpgtfp_p:
3270 case Intrinsic::ppc_altivec_vcmpgtsb_p:
3271 case Intrinsic::ppc_altivec_vcmpgtsh_p:
3272 case Intrinsic::ppc_altivec_vcmpgtsw_p:
3273 case Intrinsic::ppc_altivec_vcmpgtub_p:
3274 case Intrinsic::ppc_altivec_vcmpgtuh_p:
3275 case Intrinsic::ppc_altivec_vcmpgtuw_p:
3276 KnownZero = ~1U; // All bits but the low one are known to be zero.
3284 /// getConstraintType - Given a constraint, return the type of
3285 /// constraint it is for this target.
3286 PPCTargetLowering::ConstraintType
3287 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
3288 if (Constraint.size() == 1) {
3289 switch (Constraint[0]) {
3296 return C_RegisterClass;
3299 return TargetLowering::getConstraintType(Constraint);
3302 std::pair<unsigned, const TargetRegisterClass*>
3303 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
3304 MVT::ValueType VT) const {
3305 if (Constraint.size() == 1) {
3306 // GCC RS6000 Constraint Letters
3307 switch (Constraint[0]) {
3310 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
3311 return std::make_pair(0U, PPC::G8RCRegisterClass);
3312 return std::make_pair(0U, PPC::GPRCRegisterClass);
3315 return std::make_pair(0U, PPC::F4RCRegisterClass);
3316 else if (VT == MVT::f64)
3317 return std::make_pair(0U, PPC::F8RCRegisterClass);
3320 return std::make_pair(0U, PPC::VRRCRegisterClass);
3322 return std::make_pair(0U, PPC::CRRCRegisterClass);
3326 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3330 // isOperandValidForConstraint
3331 SDOperand PPCTargetLowering::
3332 isOperandValidForConstraint(SDOperand Op, char Letter, SelectionDAG &DAG) {
3343 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
3344 if (!CST) return SDOperand(0, 0); // Must be an immediate to match.
3345 unsigned Value = CST->getValue();
3347 default: assert(0 && "Unknown constraint letter!");
3348 case 'I': // "I" is a signed 16-bit constant.
3349 if ((short)Value == (int)Value)
3350 return DAG.getTargetConstant(Value, Op.getValueType());
3352 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
3353 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
3354 if ((short)Value == 0)
3355 return DAG.getTargetConstant(Value, Op.getValueType());
3357 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
3358 if ((Value >> 16) == 0)
3359 return DAG.getTargetConstant(Value, Op.getValueType());
3361 case 'M': // "M" is a constant that is greater than 31.
3363 return DAG.getTargetConstant(Value, Op.getValueType());
3365 case 'N': // "N" is a positive constant that is an exact power of two.
3366 if ((int)Value > 0 && isPowerOf2_32(Value))
3367 return DAG.getTargetConstant(Value, Op.getValueType());
3369 case 'O': // "O" is the constant zero.
3371 return DAG.getTargetConstant(Value, Op.getValueType());
3373 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
3374 if ((short)-Value == (int)-Value)
3375 return DAG.getTargetConstant(Value, Op.getValueType());
3382 // Handle standard constraint letters.
3383 return TargetLowering::isOperandValidForConstraint(Op, Letter, DAG);
3386 // isLegalAddressingMode - Return true if the addressing mode represented
3387 // by AM is legal for this target, for a load/store of the specified type.
3388 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
3389 const Type *Ty) const {
3390 // FIXME: PPC does not allow r+i addressing modes for vectors!
3392 // PPC allows a sign-extended 16-bit immediate field.
3393 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
3396 // No global is ever allowed as a base.
3400 // PPC only support r+r,
3402 case 0: // "r+i" or just "i", depending on HasBaseReg.
3405 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
3407 // Otherwise we have r+r or r+i.
3410 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
3412 // Allow 2*r as r+r.
3415 // No other scales are supported.
3422 /// isLegalAddressImmediate - Return true if the integer value can be used
3423 /// as the offset of the target addressing mode for load / store of the
3425 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{
3426 // PPC allows a sign-extended 16-bit immediate field.
3427 return (V > -(1 << 16) && V < (1 << 16)-1);
3430 bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
3434 SDOperand PPCTargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG)
3436 // Depths > 0 not supported yet!
3437 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
3440 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3441 bool isPPC64 = PtrVT == MVT::i64;
3443 MachineFunction &MF = DAG.getMachineFunction();
3444 MachineFrameInfo *MFI = MF.getFrameInfo();
3445 bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects())
3446 && MFI->getStackSize();
3449 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::X31 : PPC::X1,
3452 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::R31 : PPC::R1,