1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCMachineFunctionInfo.h"
16 #include "PPCPredicates.h"
17 #include "PPCTargetMachine.h"
18 #include "PPCPerfectShuffle.h"
19 #include "llvm/ADT/VectorExtras.h"
20 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/CodeGen/SSARegMap.h"
27 #include "llvm/Constants.h"
28 #include "llvm/Function.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/Support/MathExtras.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Support/CommandLine.h"
35 static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc",
36 cl::desc("enable preincrement load/store generation on PPC (experimental)"),
39 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
40 : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) {
44 // Use _setjmp/_longjmp instead of setjmp/longjmp.
45 setUseUnderscoreSetJmp(true);
46 setUseUnderscoreLongJmp(true);
48 // Set up the register classes.
49 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
50 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
51 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
53 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
54 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand);
55 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand);
57 // PowerPC does not have truncstore for i1.
58 setStoreXAction(MVT::i1, Promote);
60 // PowerPC has pre-inc load and store's.
61 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
62 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
63 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
64 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
65 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
66 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
67 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
68 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
69 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
70 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
72 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
73 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
75 // PowerPC has no intrinsics for these particular operations
76 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
77 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
78 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
80 // PowerPC has no SREM/UREM instructions
81 setOperationAction(ISD::SREM, MVT::i32, Expand);
82 setOperationAction(ISD::UREM, MVT::i32, Expand);
83 setOperationAction(ISD::SREM, MVT::i64, Expand);
84 setOperationAction(ISD::UREM, MVT::i64, Expand);
86 // We don't support sin/cos/sqrt/fmod
87 setOperationAction(ISD::FSIN , MVT::f64, Expand);
88 setOperationAction(ISD::FCOS , MVT::f64, Expand);
89 setOperationAction(ISD::FREM , MVT::f64, Expand);
90 setOperationAction(ISD::FSIN , MVT::f32, Expand);
91 setOperationAction(ISD::FCOS , MVT::f32, Expand);
92 setOperationAction(ISD::FREM , MVT::f32, Expand);
94 // If we're enabling GP optimizations, use hardware square root
95 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
96 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
97 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
100 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
101 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
103 // PowerPC does not have BSWAP, CTPOP or CTTZ
104 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
105 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
106 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
107 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
108 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
109 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
111 // PowerPC does not have ROTR
112 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
114 // PowerPC does not have Select
115 setOperationAction(ISD::SELECT, MVT::i32, Expand);
116 setOperationAction(ISD::SELECT, MVT::i64, Expand);
117 setOperationAction(ISD::SELECT, MVT::f32, Expand);
118 setOperationAction(ISD::SELECT, MVT::f64, Expand);
120 // PowerPC wants to turn select_cc of FP into fsel when possible.
121 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
122 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
124 // PowerPC wants to optimize integer setcc a bit
125 setOperationAction(ISD::SETCC, MVT::i32, Custom);
127 // PowerPC does not have BRCOND which requires SetCC
128 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
130 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
132 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
133 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
135 // PowerPC does not have [U|S]INT_TO_FP
136 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
137 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
139 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
140 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
141 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
142 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
144 // We cannot sextinreg(i1). Expand to shifts.
145 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
147 // Support label based line numbers.
148 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
149 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
150 if (!TM.getSubtarget<PPCSubtarget>().isDarwin()) {
151 setOperationAction(ISD::LABEL, MVT::Other, Expand);
153 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
154 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
155 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
156 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
159 // We want to legalize GlobalAddress and ConstantPool nodes into the
160 // appropriate instructions to materialize the address.
161 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
162 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
163 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
164 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
165 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
166 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
168 // RET must be custom lowered, to meet ABI requirements
169 setOperationAction(ISD::RET , MVT::Other, Custom);
171 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
172 setOperationAction(ISD::VASTART , MVT::Other, Custom);
174 // VAARG is custom lowered with ELF 32 ABI
175 if (TM.getSubtarget<PPCSubtarget>().isELF32_ABI())
176 setOperationAction(ISD::VAARG, MVT::Other, Custom);
178 setOperationAction(ISD::VAARG, MVT::Other, Expand);
180 // Use the default implementation.
181 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
182 setOperationAction(ISD::VAEND , MVT::Other, Expand);
183 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
184 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
185 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
186 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
188 // We want to custom lower some of our intrinsics.
189 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
191 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
192 // They also have instructions for converting between i64 and fp.
193 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
194 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
195 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
196 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
197 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
199 // FIXME: disable this lowered code. This generates 64-bit register values,
200 // and we don't model the fact that the top part is clobbered by calls. We
201 // need to flag these together so that the value isn't live across a call.
202 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
204 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
205 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
207 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
208 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
211 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
212 // 64 bit PowerPC implementations can support i64 types directly
213 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
214 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
215 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
217 // 32 bit PowerPC wants to expand i64 shifts itself.
218 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
219 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
220 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
223 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
224 // First set operation action for all vector types to expand. Then we
225 // will selectively turn on ones that can be effectively codegen'd.
226 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
227 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
228 // add/sub are legal for all supported vector VT's.
229 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal);
230 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal);
232 // We promote all shuffles to v16i8.
233 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote);
234 AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8);
236 // We promote all non-typed operations to v4i32.
237 setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote);
238 AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32);
239 setOperationAction(ISD::OR , (MVT::ValueType)VT, Promote);
240 AddPromotedToType (ISD::OR , (MVT::ValueType)VT, MVT::v4i32);
241 setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote);
242 AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32);
243 setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote);
244 AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32);
245 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
246 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32);
247 setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote);
248 AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32);
250 // No other operations are legal.
251 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
252 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
253 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
254 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
255 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
256 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
257 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
258 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
259 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
261 setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand);
264 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
265 // with merges, splats, etc.
266 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
268 setOperationAction(ISD::AND , MVT::v4i32, Legal);
269 setOperationAction(ISD::OR , MVT::v4i32, Legal);
270 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
271 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
272 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
273 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
275 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
276 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
277 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
278 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
280 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
281 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
282 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
283 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
285 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
286 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
288 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
289 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
290 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
291 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
294 setSetCCResultType(MVT::i32);
295 setShiftAmountType(MVT::i32);
296 setSetCCResultContents(ZeroOrOneSetCCResult);
298 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
299 setStackPointerRegisterToSaveRestore(PPC::X1);
300 setExceptionPointerRegister(PPC::X3);
301 setExceptionSelectorRegister(PPC::X4);
303 setStackPointerRegisterToSaveRestore(PPC::R1);
304 setExceptionPointerRegister(PPC::R3);
305 setExceptionSelectorRegister(PPC::R4);
308 // We have target-specific dag combine patterns for the following nodes:
309 setTargetDAGCombine(ISD::SINT_TO_FP);
310 setTargetDAGCombine(ISD::STORE);
311 setTargetDAGCombine(ISD::BR_CC);
312 setTargetDAGCombine(ISD::BSWAP);
314 computeRegisterProperties();
317 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
320 case PPCISD::FSEL: return "PPCISD::FSEL";
321 case PPCISD::FCFID: return "PPCISD::FCFID";
322 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
323 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
324 case PPCISD::STFIWX: return "PPCISD::STFIWX";
325 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
326 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
327 case PPCISD::VPERM: return "PPCISD::VPERM";
328 case PPCISD::Hi: return "PPCISD::Hi";
329 case PPCISD::Lo: return "PPCISD::Lo";
330 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
331 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
332 case PPCISD::SRL: return "PPCISD::SRL";
333 case PPCISD::SRA: return "PPCISD::SRA";
334 case PPCISD::SHL: return "PPCISD::SHL";
335 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
336 case PPCISD::STD_32: return "PPCISD::STD_32";
337 case PPCISD::CALL_ELF: return "PPCISD::CALL_ELF";
338 case PPCISD::CALL_Macho: return "PPCISD::CALL_Macho";
339 case PPCISD::MTCTR: return "PPCISD::MTCTR";
340 case PPCISD::BCTRL_Macho: return "PPCISD::BCTRL_Macho";
341 case PPCISD::BCTRL_ELF: return "PPCISD::BCTRL_ELF";
342 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
343 case PPCISD::MFCR: return "PPCISD::MFCR";
344 case PPCISD::VCMP: return "PPCISD::VCMP";
345 case PPCISD::VCMPo: return "PPCISD::VCMPo";
346 case PPCISD::LBRX: return "PPCISD::LBRX";
347 case PPCISD::STBRX: return "PPCISD::STBRX";
348 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
352 //===----------------------------------------------------------------------===//
353 // Node matching predicates, for use by the tblgen matching code.
354 //===----------------------------------------------------------------------===//
356 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
357 static bool isFloatingPointZero(SDOperand Op) {
358 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
359 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
360 else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
361 // Maybe this has already been legalized into the constant pool?
362 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
363 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
364 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
369 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
370 /// true if Op is undef or if it matches the specified value.
371 static bool isConstantOrUndef(SDOperand Op, unsigned Val) {
372 return Op.getOpcode() == ISD::UNDEF ||
373 cast<ConstantSDNode>(Op)->getValue() == Val;
376 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
377 /// VPKUHUM instruction.
378 bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) {
380 for (unsigned i = 0; i != 16; ++i)
381 if (!isConstantOrUndef(N->getOperand(i), i*2+1))
384 for (unsigned i = 0; i != 8; ++i)
385 if (!isConstantOrUndef(N->getOperand(i), i*2+1) ||
386 !isConstantOrUndef(N->getOperand(i+8), i*2+1))
392 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
393 /// VPKUWUM instruction.
394 bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) {
396 for (unsigned i = 0; i != 16; i += 2)
397 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
398 !isConstantOrUndef(N->getOperand(i+1), i*2+3))
401 for (unsigned i = 0; i != 8; i += 2)
402 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
403 !isConstantOrUndef(N->getOperand(i+1), i*2+3) ||
404 !isConstantOrUndef(N->getOperand(i+8), i*2+2) ||
405 !isConstantOrUndef(N->getOperand(i+9), i*2+3))
411 /// isVMerge - Common function, used to match vmrg* shuffles.
413 static bool isVMerge(SDNode *N, unsigned UnitSize,
414 unsigned LHSStart, unsigned RHSStart) {
415 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
416 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
417 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
418 "Unsupported merge size!");
420 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
421 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
422 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j),
423 LHSStart+j+i*UnitSize) ||
424 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j),
425 RHSStart+j+i*UnitSize))
431 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
432 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
433 bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
435 return isVMerge(N, UnitSize, 8, 24);
436 return isVMerge(N, UnitSize, 8, 8);
439 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
440 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
441 bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
443 return isVMerge(N, UnitSize, 0, 16);
444 return isVMerge(N, UnitSize, 0, 0);
448 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
449 /// amount, otherwise return -1.
450 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
451 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
452 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
453 // Find the first non-undef value in the shuffle mask.
455 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i)
458 if (i == 16) return -1; // all undef.
460 // Otherwise, check to see if the rest of the elements are consequtively
461 // numbered from this value.
462 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue();
463 if (ShiftAmt < i) return -1;
467 // Check the rest of the elements to see if they are consequtive.
468 for (++i; i != 16; ++i)
469 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i))
472 // Check the rest of the elements to see if they are consequtive.
473 for (++i; i != 16; ++i)
474 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15))
481 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
482 /// specifies a splat of a single element that is suitable for input to
483 /// VSPLTB/VSPLTH/VSPLTW.
484 bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) {
485 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
486 N->getNumOperands() == 16 &&
487 (EltSize == 1 || EltSize == 2 || EltSize == 4));
489 // This is a splat operation if each element of the permute is the same, and
490 // if the value doesn't reference the second vector.
491 unsigned ElementBase = 0;
492 SDOperand Elt = N->getOperand(0);
493 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt))
494 ElementBase = EltV->getValue();
496 return false; // FIXME: Handle UNDEF elements too!
498 if (cast<ConstantSDNode>(Elt)->getValue() >= 16)
501 // Check that they are consequtive.
502 for (unsigned i = 1; i != EltSize; ++i) {
503 if (!isa<ConstantSDNode>(N->getOperand(i)) ||
504 cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase)
508 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
509 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
510 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
511 assert(isa<ConstantSDNode>(N->getOperand(i)) &&
512 "Invalid VECTOR_SHUFFLE mask!");
513 for (unsigned j = 0; j != EltSize; ++j)
514 if (N->getOperand(i+j) != N->getOperand(j))
521 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
522 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
523 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
524 assert(isSplatShuffleMask(N, EltSize));
525 return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize;
528 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
529 /// by using a vspltis[bhw] instruction of the specified element size, return
530 /// the constant being splatted. The ByteSize field indicates the number of
531 /// bytes of each element [124] -> [bhw].
532 SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
533 SDOperand OpVal(0, 0);
535 // If ByteSize of the splat is bigger than the element size of the
536 // build_vector, then we have a case where we are checking for a splat where
537 // multiple elements of the buildvector are folded together into a single
538 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
539 unsigned EltSize = 16/N->getNumOperands();
540 if (EltSize < ByteSize) {
541 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
542 SDOperand UniquedVals[4];
543 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
545 // See if all of the elements in the buildvector agree across.
546 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
547 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
548 // If the element isn't a constant, bail fully out.
549 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand();
552 if (UniquedVals[i&(Multiple-1)].Val == 0)
553 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
554 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
555 return SDOperand(); // no match.
558 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
559 // either constant or undef values that are identical for each chunk. See
560 // if these chunks can form into a larger vspltis*.
562 // Check to see if all of the leading entries are either 0 or -1. If
563 // neither, then this won't fit into the immediate field.
564 bool LeadingZero = true;
565 bool LeadingOnes = true;
566 for (unsigned i = 0; i != Multiple-1; ++i) {
567 if (UniquedVals[i].Val == 0) continue; // Must have been undefs.
569 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
570 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
572 // Finally, check the least significant entry.
574 if (UniquedVals[Multiple-1].Val == 0)
575 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
576 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue();
578 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
581 if (UniquedVals[Multiple-1].Val == 0)
582 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
583 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended();
584 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
585 return DAG.getTargetConstant(Val, MVT::i32);
591 // Check to see if this buildvec has a single non-undef value in its elements.
592 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
593 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
595 OpVal = N->getOperand(i);
596 else if (OpVal != N->getOperand(i))
600 if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def.
602 unsigned ValSizeInBytes = 0;
604 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
605 Value = CN->getValue();
606 ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8;
607 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
608 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
609 Value = FloatToBits(CN->getValue());
613 // If the splat value is larger than the element value, then we can never do
614 // this splat. The only case that we could fit the replicated bits into our
615 // immediate field for would be zero, and we prefer to use vxor for it.
616 if (ValSizeInBytes < ByteSize) return SDOperand();
618 // If the element value is larger than the splat value, cut it in half and
619 // check to see if the two halves are equal. Continue doing this until we
620 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
621 while (ValSizeInBytes > ByteSize) {
622 ValSizeInBytes >>= 1;
624 // If the top half equals the bottom half, we're still ok.
625 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
626 (Value & ((1 << (8*ValSizeInBytes))-1)))
630 // Properly sign extend the value.
631 int ShAmt = (4-ByteSize)*8;
632 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
634 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
635 if (MaskVal == 0) return SDOperand();
637 // Finally, if this value fits in a 5 bit sext field, return it
638 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
639 return DAG.getTargetConstant(MaskVal, MVT::i32);
643 //===----------------------------------------------------------------------===//
644 // Addressing Mode Selection
645 //===----------------------------------------------------------------------===//
647 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
648 /// or 64-bit immediate, and if the value can be accurately represented as a
649 /// sign extension from a 16-bit value. If so, this returns true and the
651 static bool isIntS16Immediate(SDNode *N, short &Imm) {
652 if (N->getOpcode() != ISD::Constant)
655 Imm = (short)cast<ConstantSDNode>(N)->getValue();
656 if (N->getValueType(0) == MVT::i32)
657 return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue();
659 return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue();
661 static bool isIntS16Immediate(SDOperand Op, short &Imm) {
662 return isIntS16Immediate(Op.Val, Imm);
666 /// SelectAddressRegReg - Given the specified addressed, check to see if it
667 /// can be represented as an indexed [r+r] operation. Returns false if it
668 /// can be more efficiently represented with [r+imm].
669 bool PPCTargetLowering::SelectAddressRegReg(SDOperand N, SDOperand &Base,
673 if (N.getOpcode() == ISD::ADD) {
674 if (isIntS16Immediate(N.getOperand(1), imm))
676 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
679 Base = N.getOperand(0);
680 Index = N.getOperand(1);
682 } else if (N.getOpcode() == ISD::OR) {
683 if (isIntS16Immediate(N.getOperand(1), imm))
684 return false; // r+i can fold it if we can.
686 // If this is an or of disjoint bitfields, we can codegen this as an add
687 // (for better address arithmetic) if the LHS and RHS of the OR are provably
689 uint64_t LHSKnownZero, LHSKnownOne;
690 uint64_t RHSKnownZero, RHSKnownOne;
691 ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne);
694 ComputeMaskedBits(N.getOperand(1), ~0U, RHSKnownZero, RHSKnownOne);
695 // If all of the bits are known zero on the LHS or RHS, the add won't
697 if ((LHSKnownZero | RHSKnownZero) == ~0U) {
698 Base = N.getOperand(0);
699 Index = N.getOperand(1);
708 /// Returns true if the address N can be represented by a base register plus
709 /// a signed 16-bit displacement [r+imm], and if it is not better
710 /// represented as reg+reg.
711 bool PPCTargetLowering::SelectAddressRegImm(SDOperand N, SDOperand &Disp,
712 SDOperand &Base, SelectionDAG &DAG){
713 // If this can be more profitably realized as r+r, fail.
714 if (SelectAddressRegReg(N, Disp, Base, DAG))
717 if (N.getOpcode() == ISD::ADD) {
719 if (isIntS16Immediate(N.getOperand(1), imm)) {
720 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
721 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
722 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
724 Base = N.getOperand(0);
726 return true; // [r+i]
727 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
728 // Match LOAD (ADD (X, Lo(G))).
729 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
730 && "Cannot handle constant offsets yet!");
731 Disp = N.getOperand(1).getOperand(0); // The global address.
732 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
733 Disp.getOpcode() == ISD::TargetConstantPool ||
734 Disp.getOpcode() == ISD::TargetJumpTable);
735 Base = N.getOperand(0);
736 return true; // [&g+r]
738 } else if (N.getOpcode() == ISD::OR) {
740 if (isIntS16Immediate(N.getOperand(1), imm)) {
741 // If this is an or of disjoint bitfields, we can codegen this as an add
742 // (for better address arithmetic) if the LHS and RHS of the OR are
743 // provably disjoint.
744 uint64_t LHSKnownZero, LHSKnownOne;
745 ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne);
746 if ((LHSKnownZero|~(unsigned)imm) == ~0U) {
747 // If all of the bits are known zero on the LHS or RHS, the add won't
749 Base = N.getOperand(0);
750 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
754 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
755 // Loading from a constant address.
757 // If this address fits entirely in a 16-bit sext immediate field, codegen
760 if (isIntS16Immediate(CN, Imm)) {
761 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
762 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
766 // Handle 32-bit sext immediates with LIS + addr mode.
767 if (CN->getValueType(0) == MVT::i32 ||
768 (int64_t)CN->getValue() == (int)CN->getValue()) {
769 int Addr = (int)CN->getValue();
771 // Otherwise, break this down into an LIS + disp.
772 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
774 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
775 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
776 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
781 Disp = DAG.getTargetConstant(0, getPointerTy());
782 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
783 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
786 return true; // [r+0]
789 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
790 /// represented as an indexed [r+r] operation.
791 bool PPCTargetLowering::SelectAddressRegRegOnly(SDOperand N, SDOperand &Base,
794 // Check to see if we can easily represent this as an [r+r] address. This
795 // will fail if it thinks that the address is more profitably represented as
796 // reg+imm, e.g. where imm = 0.
797 if (SelectAddressRegReg(N, Base, Index, DAG))
800 // If the operand is an addition, always emit this as [r+r], since this is
801 // better (for code size, and execution, as the memop does the add for free)
802 // than emitting an explicit add.
803 if (N.getOpcode() == ISD::ADD) {
804 Base = N.getOperand(0);
805 Index = N.getOperand(1);
809 // Otherwise, do it the hard way, using R0 as the base register.
810 Base = DAG.getRegister(PPC::R0, N.getValueType());
815 /// SelectAddressRegImmShift - Returns true if the address N can be
816 /// represented by a base register plus a signed 14-bit displacement
817 /// [r+imm*4]. Suitable for use by STD and friends.
818 bool PPCTargetLowering::SelectAddressRegImmShift(SDOperand N, SDOperand &Disp,
821 // If this can be more profitably realized as r+r, fail.
822 if (SelectAddressRegReg(N, Disp, Base, DAG))
825 if (N.getOpcode() == ISD::ADD) {
827 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
828 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
829 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
830 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
832 Base = N.getOperand(0);
834 return true; // [r+i]
835 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
836 // Match LOAD (ADD (X, Lo(G))).
837 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
838 && "Cannot handle constant offsets yet!");
839 Disp = N.getOperand(1).getOperand(0); // The global address.
840 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
841 Disp.getOpcode() == ISD::TargetConstantPool ||
842 Disp.getOpcode() == ISD::TargetJumpTable);
843 Base = N.getOperand(0);
844 return true; // [&g+r]
846 } else if (N.getOpcode() == ISD::OR) {
848 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
849 // If this is an or of disjoint bitfields, we can codegen this as an add
850 // (for better address arithmetic) if the LHS and RHS of the OR are
851 // provably disjoint.
852 uint64_t LHSKnownZero, LHSKnownOne;
853 ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne);
854 if ((LHSKnownZero|~(unsigned)imm) == ~0U) {
855 // If all of the bits are known zero on the LHS or RHS, the add won't
857 Base = N.getOperand(0);
858 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
862 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
863 // Loading from a constant address. Verify low two bits are clear.
864 if ((CN->getValue() & 3) == 0) {
865 // If this address fits entirely in a 14-bit sext immediate field, codegen
868 if (isIntS16Immediate(CN, Imm)) {
869 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
870 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
874 // Fold the low-part of 32-bit absolute addresses into addr mode.
875 if (CN->getValueType(0) == MVT::i32 ||
876 (int64_t)CN->getValue() == (int)CN->getValue()) {
877 int Addr = (int)CN->getValue();
879 // Otherwise, break this down into an LIS + disp.
880 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
882 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
883 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
884 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
890 Disp = DAG.getTargetConstant(0, getPointerTy());
891 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
892 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
895 return true; // [r+0]
899 /// getPreIndexedAddressParts - returns true by value, base pointer and
900 /// offset pointer and addressing mode by reference if the node's address
901 /// can be legally represented as pre-indexed load / store address.
902 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
904 ISD::MemIndexedMode &AM,
906 // Disabled by default for now.
907 if (!EnablePPCPreinc) return false;
911 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
912 Ptr = LD->getBasePtr();
913 VT = LD->getLoadedVT();
915 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
917 Ptr = ST->getBasePtr();
918 VT = ST->getStoredVT();
922 // PowerPC doesn't have preinc load/store instructions for vectors.
923 if (MVT::isVector(VT))
926 // TODO: Check reg+reg first.
928 // LDU/STU use reg+imm*4, others use reg+imm.
929 if (VT != MVT::i64) {
931 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
935 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
939 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
940 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
941 // sext i32 to i64 when addr mode is r+i.
942 if (LD->getValueType(0) == MVT::i64 && LD->getLoadedVT() == MVT::i32 &&
943 LD->getExtensionType() == ISD::SEXTLOAD &&
944 isa<ConstantSDNode>(Offset))
952 //===----------------------------------------------------------------------===//
953 // LowerOperation implementation
954 //===----------------------------------------------------------------------===//
956 static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
957 MVT::ValueType PtrVT = Op.getValueType();
958 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
959 Constant *C = CP->getConstVal();
960 SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
961 SDOperand Zero = DAG.getConstant(0, PtrVT);
963 const TargetMachine &TM = DAG.getTarget();
965 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero);
966 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero);
968 // If this is a non-darwin platform, we don't support non-static relo models
970 if (TM.getRelocationModel() == Reloc::Static ||
971 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
972 // Generate non-pic code that has direct accesses to the constant pool.
973 // The address of the global is just (hi(&g)+lo(&g)).
974 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
977 if (TM.getRelocationModel() == Reloc::PIC_) {
978 // With PIC, the first instruction is actually "GR+hi(&G)".
979 Hi = DAG.getNode(ISD::ADD, PtrVT,
980 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
983 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
987 static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
988 MVT::ValueType PtrVT = Op.getValueType();
989 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
990 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
991 SDOperand Zero = DAG.getConstant(0, PtrVT);
993 const TargetMachine &TM = DAG.getTarget();
995 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero);
996 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero);
998 // If this is a non-darwin platform, we don't support non-static relo models
1000 if (TM.getRelocationModel() == Reloc::Static ||
1001 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1002 // Generate non-pic code that has direct accesses to the constant pool.
1003 // The address of the global is just (hi(&g)+lo(&g)).
1004 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1007 if (TM.getRelocationModel() == Reloc::PIC_) {
1008 // With PIC, the first instruction is actually "GR+hi(&G)".
1009 Hi = DAG.getNode(ISD::ADD, PtrVT,
1010 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1013 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1017 static SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
1018 MVT::ValueType PtrVT = Op.getValueType();
1019 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1020 GlobalValue *GV = GSDN->getGlobal();
1021 SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
1022 SDOperand Zero = DAG.getConstant(0, PtrVT);
1024 const TargetMachine &TM = DAG.getTarget();
1026 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero);
1027 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero);
1029 // If this is a non-darwin platform, we don't support non-static relo models
1031 if (TM.getRelocationModel() == Reloc::Static ||
1032 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1033 // Generate non-pic code that has direct accesses to globals.
1034 // The address of the global is just (hi(&g)+lo(&g)).
1035 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1038 if (TM.getRelocationModel() == Reloc::PIC_) {
1039 // With PIC, the first instruction is actually "GR+hi(&G)".
1040 Hi = DAG.getNode(ISD::ADD, PtrVT,
1041 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1044 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1046 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV))
1049 // If the global is weak or external, we have to go through the lazy
1051 return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0);
1054 static SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
1055 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1057 // If we're comparing for equality to zero, expose the fact that this is
1058 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1059 // fold the new nodes.
1060 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1061 if (C->isNullValue() && CC == ISD::SETEQ) {
1062 MVT::ValueType VT = Op.getOperand(0).getValueType();
1063 SDOperand Zext = Op.getOperand(0);
1064 if (VT < MVT::i32) {
1066 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0));
1068 unsigned Log2b = Log2_32(MVT::getSizeInBits(VT));
1069 SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext);
1070 SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz,
1071 DAG.getConstant(Log2b, MVT::i32));
1072 return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc);
1074 // Leave comparisons against 0 and -1 alone for now, since they're usually
1075 // optimized. FIXME: revisit this when we can custom lower all setcc
1077 if (C->isAllOnesValue() || C->isNullValue())
1081 // If we have an integer seteq/setne, turn it into a compare against zero
1082 // by xor'ing the rhs with the lhs, which is faster than setting a
1083 // condition register, reading it back out, and masking the correct bit. The
1084 // normal approach here uses sub to do this instead of xor. Using xor exposes
1085 // the result to other bit-twiddling opportunities.
1086 MVT::ValueType LHSVT = Op.getOperand(0).getValueType();
1087 if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1088 MVT::ValueType VT = Op.getValueType();
1089 SDOperand Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0),
1091 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC);
1096 static SDOperand LowerVAARG(SDOperand Op, SelectionDAG &DAG,
1097 int VarArgsFrameIndex,
1098 int VarArgsStackOffset,
1099 unsigned VarArgsNumGPR,
1100 unsigned VarArgsNumFPR,
1101 const PPCSubtarget &Subtarget) {
1103 assert(0 && "VAARG in ELF32 ABI not implemented yet!");
1106 static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
1107 int VarArgsFrameIndex,
1108 int VarArgsStackOffset,
1109 unsigned VarArgsNumGPR,
1110 unsigned VarArgsNumFPR,
1111 const PPCSubtarget &Subtarget) {
1113 if (Subtarget.isMachoABI()) {
1114 // vastart just stores the address of the VarArgsFrameIndex slot into the
1115 // memory location argument.
1116 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1117 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1118 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
1119 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(),
1123 // For ELF 32 ABI we follow the layout of the va_list struct.
1124 // We suppose the given va_list is already allocated.
1127 // char gpr; /* index into the array of 8 GPRs
1128 // * stored in the register save area
1129 // * gpr=0 corresponds to r3,
1130 // * gpr=1 to r4, etc.
1132 // char fpr; /* index into the array of 8 FPRs
1133 // * stored in the register save area
1134 // * fpr=0 corresponds to f1,
1135 // * fpr=1 to f2, etc.
1137 // char *overflow_arg_area;
1138 // /* location on stack that holds
1139 // * the next overflow argument
1141 // char *reg_save_area;
1142 // /* where r3:r10 and f1:f8 (if saved)
1148 SDOperand ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i8);
1149 SDOperand ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i8);
1152 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1154 SDOperand StackOffset = DAG.getFrameIndex(VarArgsStackOffset, PtrVT);
1155 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1157 SDOperand ConstFrameOffset = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8,
1159 SDOperand ConstStackOffset = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8 - 1,
1161 SDOperand ConstFPROffset = DAG.getConstant(1, PtrVT);
1163 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
1165 // Store first byte : number of int regs
1166 SDOperand firstStore = DAG.getStore(Op.getOperand(0), ArgGPR,
1167 Op.getOperand(1), SV->getValue(),
1169 SDOperand nextPtr = DAG.getNode(ISD::ADD, PtrVT, Op.getOperand(1),
1172 // Store second byte : number of float regs
1173 SDOperand secondStore = DAG.getStore(firstStore, ArgFPR, nextPtr,
1174 SV->getValue(), SV->getOffset());
1175 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstStackOffset);
1177 // Store second word : arguments given on stack
1178 SDOperand thirdStore = DAG.getStore(secondStore, StackOffset, nextPtr,
1179 SV->getValue(), SV->getOffset());
1180 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstFrameOffset);
1182 // Store third word : arguments given in registers
1183 return DAG.getStore(thirdStore, FR, nextPtr, SV->getValue(),
1188 #include "PPCGenCallingConv.inc"
1190 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1191 /// depending on which subtarget is selected.
1192 static const unsigned *GetFPR(const PPCSubtarget &Subtarget) {
1193 if (Subtarget.isMachoABI()) {
1194 static const unsigned FPR[] = {
1195 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1196 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1202 static const unsigned FPR[] = {
1203 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1209 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
1210 int &VarArgsFrameIndex,
1211 int &VarArgsStackOffset,
1212 unsigned &VarArgsNumGPR,
1213 unsigned &VarArgsNumFPR,
1214 const PPCSubtarget &Subtarget) {
1215 // TODO: add description of PPC stack frame format, or at least some docs.
1217 MachineFunction &MF = DAG.getMachineFunction();
1218 MachineFrameInfo *MFI = MF.getFrameInfo();
1219 SSARegMap *RegMap = MF.getSSARegMap();
1220 SmallVector<SDOperand, 8> ArgValues;
1221 SDOperand Root = Op.getOperand(0);
1223 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1224 bool isPPC64 = PtrVT == MVT::i64;
1225 bool isMachoABI = Subtarget.isMachoABI();
1226 bool isELF32_ABI = Subtarget.isELF32_ABI();
1227 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1229 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1231 static const unsigned GPR_32[] = { // 32-bit registers.
1232 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1233 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1235 static const unsigned GPR_64[] = { // 64-bit registers.
1236 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1237 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1240 static const unsigned *FPR = GetFPR(Subtarget);
1242 static const unsigned VR[] = {
1243 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1244 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1247 const unsigned Num_GPR_Regs = sizeof(GPR_32)/sizeof(GPR_32[0]);
1248 const unsigned Num_FPR_Regs = isMachoABI ? 13 : 8;
1249 const unsigned Num_VR_Regs = sizeof( VR)/sizeof( VR[0]);
1251 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1253 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1255 // Add DAG nodes to load the arguments or copy them out of registers. On
1256 // entry to a function on PPC, the arguments start after the linkage area,
1257 // although the first ones are often in registers.
1259 // In the ELF 32 ABI, GPRs and stack are double word align: an argument
1260 // represented with two words (long long or double) must be copied to an
1261 // even GPR_idx value or to an even ArgOffset value.
1263 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
1265 bool needsLoad = false;
1266 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
1267 unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8;
1268 unsigned ArgSize = ObjSize;
1269 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(ArgNo+3))->getValue();
1270 unsigned AlignFlag = 1 << ISD::ParamFlags::OrigAlignmentOffs;
1271 // See if next argument requires stack alignment in ELF
1272 bool Expand = (ObjectVT == MVT::f64) || ((ArgNo + 1 < e) &&
1273 (cast<ConstantSDNode>(Op.getOperand(ArgNo+4))->getValue() & AlignFlag) &&
1274 (!(Flags & AlignFlag)));
1276 unsigned CurArgOffset = ArgOffset;
1278 default: assert(0 && "Unhandled argument type!");
1280 // Double word align in ELF
1281 if (Expand && isELF32_ABI) GPR_idx += (GPR_idx % 2);
1282 if (GPR_idx != Num_GPR_Regs) {
1283 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
1284 MF.addLiveIn(GPR[GPR_idx], VReg);
1285 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32);
1289 ArgSize = PtrByteSize;
1291 // Stack align in ELF
1292 if (needsLoad && Expand && isELF32_ABI)
1293 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1294 // All int arguments reserve stack space in Macho ABI.
1295 if (isMachoABI || needsLoad) ArgOffset += PtrByteSize;
1298 case MVT::i64: // PPC64
1299 if (GPR_idx != Num_GPR_Regs) {
1300 unsigned VReg = RegMap->createVirtualRegister(&PPC::G8RCRegClass);
1301 MF.addLiveIn(GPR[GPR_idx], VReg);
1302 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1307 // All int arguments reserve stack space in Macho ABI.
1308 if (isMachoABI || needsLoad) ArgOffset += 8;
1313 // Every 4 bytes of argument space consumes one of the GPRs available for
1314 // argument passing.
1315 if (GPR_idx != Num_GPR_Regs && isMachoABI) {
1317 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
1320 if (FPR_idx != Num_FPR_Regs) {
1322 if (ObjectVT == MVT::f32)
1323 VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass);
1325 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass);
1326 MF.addLiveIn(FPR[FPR_idx], VReg);
1327 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
1333 // Stack align in ELF
1334 if (needsLoad && Expand && isELF32_ABI)
1335 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1336 // All FP arguments reserve stack space in Macho ABI.
1337 if (isMachoABI || needsLoad) ArgOffset += isPPC64 ? 8 : ObjSize;
1343 // Note that vector arguments in registers don't reserve stack space.
1344 if (VR_idx != Num_VR_Regs) {
1345 unsigned VReg = RegMap->createVirtualRegister(&PPC::VRRCRegClass);
1346 MF.addLiveIn(VR[VR_idx], VReg);
1347 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
1350 // This should be simple, but requires getting 16-byte aligned stack
1352 assert(0 && "Loading VR argument not implemented yet!");
1358 // We need to load the argument to a virtual register if we determined above
1359 // that we ran out of physical registers of the appropriate type
1361 // If the argument is actually used, emit a load from the right stack
1363 if (!Op.Val->hasNUsesOfValue(0, ArgNo)) {
1364 int FI = MFI->CreateFixedObject(ObjSize,
1365 CurArgOffset + (ArgSize - ObjSize));
1366 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
1367 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
1369 // Don't emit a dead load.
1370 ArgVal = DAG.getNode(ISD::UNDEF, ObjectVT);
1374 ArgValues.push_back(ArgVal);
1377 // If the function takes variable number of arguments, make a frame index for
1378 // the start of the first vararg value... for expansion of llvm.va_start.
1379 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1384 VarArgsNumGPR = GPR_idx;
1385 VarArgsNumFPR = FPR_idx;
1387 // Make room for Num_GPR_Regs, Num_FPR_Regs and for a possible frame
1389 depth = -(Num_GPR_Regs * MVT::getSizeInBits(PtrVT)/8 +
1390 Num_FPR_Regs * MVT::getSizeInBits(MVT::f64)/8 +
1391 MVT::getSizeInBits(PtrVT)/8);
1393 VarArgsStackOffset = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8,
1400 VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8,
1402 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1404 SmallVector<SDOperand, 8> MemOps;
1406 // In ELF 32 ABI, the fixed integer arguments of a variadic function are
1407 // stored to the VarArgsFrameIndex on the stack.
1409 for (GPR_idx = 0; GPR_idx != VarArgsNumGPR; ++GPR_idx) {
1410 SDOperand Val = DAG.getRegister(GPR[GPR_idx], PtrVT);
1411 SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0);
1412 MemOps.push_back(Store);
1413 // Increment the address by four for the next argument to store
1414 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT);
1415 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1419 // If this function is vararg, store any remaining integer argument regs
1420 // to their spots on the stack so that they may be loaded by deferencing the
1421 // result of va_next.
1422 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
1425 VReg = RegMap->createVirtualRegister(&PPC::G8RCRegClass);
1427 VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
1429 MF.addLiveIn(GPR[GPR_idx], VReg);
1430 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
1431 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1432 MemOps.push_back(Store);
1433 // Increment the address by four for the next argument to store
1434 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT);
1435 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1438 // In ELF 32 ABI, the double arguments are stored to the VarArgsFrameIndex
1441 for (FPR_idx = 0; FPR_idx != VarArgsNumFPR; ++FPR_idx) {
1442 SDOperand Val = DAG.getRegister(FPR[FPR_idx], MVT::f64);
1443 SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0);
1444 MemOps.push_back(Store);
1445 // Increment the address by eight for the next argument to store
1446 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8,
1448 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1451 for (; FPR_idx != Num_FPR_Regs; ++FPR_idx) {
1453 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass);
1455 MF.addLiveIn(FPR[FPR_idx], VReg);
1456 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::f64);
1457 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1458 MemOps.push_back(Store);
1459 // Increment the address by eight for the next argument to store
1460 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8,
1462 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1466 if (!MemOps.empty())
1467 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size());
1470 ArgValues.push_back(Root);
1472 // Return the new list of results.
1473 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
1474 Op.Val->value_end());
1475 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
1478 /// isCallCompatibleAddress - Return the immediate to use if the specified
1479 /// 32-bit value is representable in the immediate field of a BxA instruction.
1480 static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) {
1481 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
1484 int Addr = C->getValue();
1485 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
1486 (Addr << 6 >> 6) != Addr)
1487 return 0; // Top 6 bits have to be sext of immediate.
1489 return DAG.getConstant((int)C->getValue() >> 2, MVT::i32).Val;
1493 static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG,
1494 const PPCSubtarget &Subtarget) {
1495 SDOperand Chain = Op.getOperand(0);
1496 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1497 SDOperand Callee = Op.getOperand(4);
1498 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
1500 bool isMachoABI = Subtarget.isMachoABI();
1501 bool isELF32_ABI = Subtarget.isELF32_ABI();
1503 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1504 bool isPPC64 = PtrVT == MVT::i64;
1505 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1507 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in
1508 // SelectExpr to use to put the arguments in the appropriate registers.
1509 std::vector<SDOperand> args_to_use;
1511 // Count how many bytes are to be pushed on the stack, including the linkage
1512 // area, and parameter passing area. We start with 24/48 bytes, which is
1513 // prereserved space for [SP][CR][LR][3 x unused].
1514 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1516 // Add up all the space actually used.
1517 for (unsigned i = 0; i != NumOps; ++i) {
1518 unsigned ArgSize =MVT::getSizeInBits(Op.getOperand(5+2*i).getValueType())/8;
1519 ArgSize = std::max(ArgSize, PtrByteSize);
1520 NumBytes += ArgSize;
1523 // The prolog code of the callee may store up to 8 GPR argument registers to
1524 // the stack, allowing va_start to index over them in memory if its varargs.
1525 // Because we cannot tell if this is needed on the caller side, we have to
1526 // conservatively assume that it is needed. As such, make sure we have at
1527 // least enough stack space for the caller to store the 8 GPRs.
1528 NumBytes = std::max(NumBytes,
1529 PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI));
1531 // Adjust the stack pointer for the new arguments...
1532 // These operations are automatically eliminated by the prolog/epilog pass
1533 Chain = DAG.getCALLSEQ_START(Chain,
1534 DAG.getConstant(NumBytes, PtrVT));
1536 // Set up a copy of the stack pointer for use loading and storing any
1537 // arguments that may not fit in the registers available for argument
1541 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
1543 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
1545 // Figure out which arguments are going to go in registers, and which in
1546 // memory. Also, if this is a vararg function, floating point operations
1547 // must be stored to our stack, and loaded into integer regs as well, if
1548 // any integer regs are available for argument passing.
1549 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1550 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1552 static const unsigned GPR_32[] = { // 32-bit registers.
1553 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1554 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1556 static const unsigned GPR_64[] = { // 64-bit registers.
1557 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1558 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1560 static const unsigned *FPR = GetFPR(Subtarget);
1562 static const unsigned VR[] = {
1563 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1564 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1566 const unsigned NumGPRs = sizeof(GPR_32)/sizeof(GPR_32[0]);
1567 const unsigned NumFPRs = isMachoABI ? 13 : 8;
1568 const unsigned NumVRs = sizeof( VR)/sizeof( VR[0]);
1570 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1572 std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
1573 SmallVector<SDOperand, 8> MemOpChains;
1574 for (unsigned i = 0; i != NumOps; ++i) {
1576 SDOperand Arg = Op.getOperand(5+2*i);
1577 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue();
1578 unsigned AlignFlag = 1 << ISD::ParamFlags::OrigAlignmentOffs;
1579 // See if next argument requires stack alignment in ELF
1580 unsigned next = 5+2*(i+1)+1;
1581 bool Expand = (Arg.getValueType() == MVT::f64) || ((i + 1 < NumOps) &&
1582 (cast<ConstantSDNode>(Op.getOperand(next))->getValue() & AlignFlag) &&
1583 (!(Flags & AlignFlag)));
1585 // PtrOff will be used to store the current argument to the stack if a
1586 // register cannot be found for it.
1589 // Stack align in ELF 32
1590 if (isELF32_ABI && Expand)
1591 PtrOff = DAG.getConstant(ArgOffset + ((ArgOffset/4) % 2) * PtrByteSize,
1592 StackPtr.getValueType());
1594 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
1596 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff);
1598 // On PPC64, promote integers to 64-bit values.
1599 if (isPPC64 && Arg.getValueType() == MVT::i32) {
1600 unsigned ExtOp = (Flags & 1) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1602 Arg = DAG.getNode(ExtOp, MVT::i64, Arg);
1605 switch (Arg.getValueType()) {
1606 default: assert(0 && "Unexpected ValueType for argument!");
1609 // Double word align in ELF
1610 if (isELF32_ABI && Expand) GPR_idx += (GPR_idx % 2);
1611 if (GPR_idx != NumGPRs) {
1612 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
1614 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1617 if (inMem || isMachoABI) {
1618 // Stack align in ELF
1619 if (isELF32_ABI && Expand)
1620 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1622 ArgOffset += PtrByteSize;
1628 // Float varargs need to be promoted to double.
1629 if (Arg.getValueType() == MVT::f32)
1630 Arg = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Arg);
1633 if (FPR_idx != NumFPRs) {
1634 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
1637 SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
1638 MemOpChains.push_back(Store);
1640 // Float varargs are always shadowed in available integer registers
1641 if (GPR_idx != NumGPRs) {
1642 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
1643 MemOpChains.push_back(Load.getValue(1));
1644 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
1647 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
1648 SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType());
1649 PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour);
1650 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
1651 MemOpChains.push_back(Load.getValue(1));
1652 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
1656 // If we have any FPRs remaining, we may also have GPRs remaining.
1657 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
1660 if (GPR_idx != NumGPRs)
1662 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
1663 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
1668 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1671 if (inMem || isMachoABI) {
1672 // Stack align in ELF
1673 if (isELF32_ABI && Expand)
1674 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1678 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
1685 assert(!isVarArg && "Don't support passing vectors to varargs yet!");
1686 assert(VR_idx != NumVRs &&
1687 "Don't support passing more than 12 vector args yet!");
1688 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
1692 if (!MemOpChains.empty())
1693 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1694 &MemOpChains[0], MemOpChains.size());
1696 // Build a sequence of copy-to-reg nodes chained together with token chain
1697 // and flag operands which copy the outgoing args into the appropriate regs.
1699 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1700 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1702 InFlag = Chain.getValue(1);
1705 // With the ELF 32 ABI, set CR6 to true if this is a vararg call.
1706 if (isVarArg && isELF32_ABI) {
1707 SDOperand SetCR(DAG.getTargetNode(PPC::SETCR, MVT::i32), 0);
1708 Chain = DAG.getCopyToReg(Chain, PPC::CR6, SetCR, InFlag);
1709 InFlag = Chain.getValue(1);
1712 std::vector<MVT::ValueType> NodeTys;
1713 NodeTys.push_back(MVT::Other); // Returns a chain
1714 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
1716 SmallVector<SDOperand, 8> Ops;
1717 unsigned CallOpc = isMachoABI? PPCISD::CALL_Macho : PPCISD::CALL_ELF;
1719 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1720 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1721 // node so that legalize doesn't hack it.
1722 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1723 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
1724 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1725 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType());
1726 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
1727 // If this is an absolute destination address, use the munged value.
1728 Callee = SDOperand(Dest, 0);
1730 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
1731 // to do the call, we can't use PPCISD::CALL.
1732 SDOperand MTCTROps[] = {Chain, Callee, InFlag};
1733 Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+(InFlag.Val!=0));
1734 InFlag = Chain.getValue(1);
1736 // Copy the callee address into R12 on darwin.
1738 Chain = DAG.getCopyToReg(Chain, PPC::R12, Callee, InFlag);
1739 InFlag = Chain.getValue(1);
1743 NodeTys.push_back(MVT::Other);
1744 NodeTys.push_back(MVT::Flag);
1745 Ops.push_back(Chain);
1746 CallOpc = isMachoABI ? PPCISD::BCTRL_Macho : PPCISD::BCTRL_ELF;
1750 // If this is a direct call, pass the chain and the callee.
1752 Ops.push_back(Chain);
1753 Ops.push_back(Callee);
1756 // Add argument registers to the end of the list so that they are known live
1758 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1759 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1760 RegsToPass[i].second.getValueType()));
1763 Ops.push_back(InFlag);
1764 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
1765 InFlag = Chain.getValue(1);
1767 SDOperand ResultVals[3];
1768 unsigned NumResults = 0;
1771 // If the call has results, copy the values out of the ret val registers.
1772 switch (Op.Val->getValueType(0)) {
1773 default: assert(0 && "Unexpected ret value!");
1774 case MVT::Other: break;
1776 if (Op.Val->getValueType(1) == MVT::i32) {
1777 Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32, InFlag).getValue(1);
1778 ResultVals[0] = Chain.getValue(0);
1779 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32,
1780 Chain.getValue(2)).getValue(1);
1781 ResultVals[1] = Chain.getValue(0);
1783 NodeTys.push_back(MVT::i32);
1785 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1);
1786 ResultVals[0] = Chain.getValue(0);
1789 NodeTys.push_back(MVT::i32);
1792 Chain = DAG.getCopyFromReg(Chain, PPC::X3, MVT::i64, InFlag).getValue(1);
1793 ResultVals[0] = Chain.getValue(0);
1795 NodeTys.push_back(MVT::i64);
1799 Chain = DAG.getCopyFromReg(Chain, PPC::F1, Op.Val->getValueType(0),
1800 InFlag).getValue(1);
1801 ResultVals[0] = Chain.getValue(0);
1803 NodeTys.push_back(Op.Val->getValueType(0));
1809 Chain = DAG.getCopyFromReg(Chain, PPC::V2, Op.Val->getValueType(0),
1810 InFlag).getValue(1);
1811 ResultVals[0] = Chain.getValue(0);
1813 NodeTys.push_back(Op.Val->getValueType(0));
1817 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
1818 DAG.getConstant(NumBytes, PtrVT));
1819 NodeTys.push_back(MVT::Other);
1821 // If the function returns void, just return the chain.
1822 if (NumResults == 0)
1825 // Otherwise, merge everything together with a MERGE_VALUES node.
1826 ResultVals[NumResults++] = Chain;
1827 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys,
1828 ResultVals, NumResults);
1829 return Res.getValue(Op.ResNo);
1832 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG, TargetMachine &TM) {
1833 SmallVector<CCValAssign, 16> RVLocs;
1834 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
1835 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1836 CCState CCInfo(CC, isVarArg, TM, RVLocs);
1837 CCInfo.AnalyzeReturn(Op.Val, RetCC_PPC);
1839 // If this is the first return lowered for this function, add the regs to the
1840 // liveout set for the function.
1841 if (DAG.getMachineFunction().liveout_empty()) {
1842 for (unsigned i = 0; i != RVLocs.size(); ++i)
1843 DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg());
1846 SDOperand Chain = Op.getOperand(0);
1849 // Copy the result values into the output registers.
1850 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1851 CCValAssign &VA = RVLocs[i];
1852 assert(VA.isRegLoc() && "Can only return in registers!");
1853 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
1854 Flag = Chain.getValue(1);
1858 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain, Flag);
1860 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain);
1863 static SDOperand LowerSTACKRESTORE(SDOperand Op, SelectionDAG &DAG,
1864 const PPCSubtarget &Subtarget) {
1865 // When we pop the dynamic allocation we need to restore the SP link.
1867 // Get the corect type for pointers.
1868 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1870 // Construct the stack pointer operand.
1871 bool IsPPC64 = Subtarget.isPPC64();
1872 unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1;
1873 SDOperand StackPtr = DAG.getRegister(SP, PtrVT);
1875 // Get the operands for the STACKRESTORE.
1876 SDOperand Chain = Op.getOperand(0);
1877 SDOperand SaveSP = Op.getOperand(1);
1879 // Load the old link SP.
1880 SDOperand LoadLinkSP = DAG.getLoad(PtrVT, Chain, StackPtr, NULL, 0);
1882 // Restore the stack pointer.
1883 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), SP, SaveSP);
1885 // Store the old link SP.
1886 return DAG.getStore(Chain, LoadLinkSP, StackPtr, NULL, 0);
1889 static SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG,
1890 const PPCSubtarget &Subtarget) {
1891 MachineFunction &MF = DAG.getMachineFunction();
1892 bool IsPPC64 = Subtarget.isPPC64();
1893 bool isMachoABI = Subtarget.isMachoABI();
1895 // Get current frame pointer save index. The users of this index will be
1896 // primarily DYNALLOC instructions.
1897 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1898 int FPSI = FI->getFramePointerSaveIndex();
1900 // If the frame pointer save index hasn't been defined yet.
1902 // Find out what the fix offset of the frame pointer save area.
1903 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isMachoABI);
1905 // Allocate the frame index for frame pointer save area.
1906 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
1908 FI->setFramePointerSaveIndex(FPSI);
1912 SDOperand Chain = Op.getOperand(0);
1913 SDOperand Size = Op.getOperand(1);
1915 // Get the corect type for pointers.
1916 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1918 SDOperand NegSize = DAG.getNode(ISD::SUB, PtrVT,
1919 DAG.getConstant(0, PtrVT), Size);
1920 // Construct a node for the frame pointer save index.
1921 SDOperand FPSIdx = DAG.getFrameIndex(FPSI, PtrVT);
1922 // Build a DYNALLOC node.
1923 SDOperand Ops[3] = { Chain, NegSize, FPSIdx };
1924 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
1925 return DAG.getNode(PPCISD::DYNALLOC, VTs, Ops, 3);
1929 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
1931 static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
1932 // Not FP? Not a fsel.
1933 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) ||
1934 !MVT::isFloatingPoint(Op.getOperand(2).getValueType()))
1937 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1939 // Cannot handle SETEQ/SETNE.
1940 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand();
1942 MVT::ValueType ResVT = Op.getValueType();
1943 MVT::ValueType CmpVT = Op.getOperand(0).getValueType();
1944 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
1945 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3);
1947 // If the RHS of the comparison is a 0.0, we don't need to do the
1948 // subtraction at all.
1949 if (isFloatingPointZero(RHS))
1951 default: break; // SETUO etc aren't handled by fsel.
1955 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
1959 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
1960 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
1961 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
1965 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
1969 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
1970 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
1971 return DAG.getNode(PPCISD::FSEL, ResVT,
1972 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV);
1977 default: break; // SETUO etc aren't handled by fsel.
1981 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
1982 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1983 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1984 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
1988 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
1989 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1990 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1991 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
1995 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
1996 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1997 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1998 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
2002 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
2003 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2004 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2005 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
2010 static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
2011 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType()));
2012 SDOperand Src = Op.getOperand(0);
2013 if (Src.getValueType() == MVT::f32)
2014 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src);
2017 switch (Op.getValueType()) {
2018 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
2020 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src);
2023 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src);
2027 // Convert the FP value to an int value through memory.
2028 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Tmp);
2029 if (Op.getValueType() == MVT::i32)
2030 Bits = DAG.getNode(ISD::TRUNCATE, MVT::i32, Bits);
2034 static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
2035 if (Op.getOperand(0).getValueType() == MVT::i64) {
2036 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
2037 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
2038 if (Op.getValueType() == MVT::f32)
2039 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
2043 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
2044 "Unhandled SINT_TO_FP type in custom expander!");
2045 // Since we only generate this in 64-bit mode, we can take advantage of
2046 // 64-bit registers. In particular, sign extend the input value into the
2047 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
2048 // then lfd it and fcfid it.
2049 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
2050 int FrameIdx = FrameInfo->CreateStackObject(8, 8);
2051 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2052 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
2054 SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32,
2057 // STD the extended value into the stack slot.
2058 SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other,
2059 DAG.getEntryNode(), Ext64, FIdx,
2060 DAG.getSrcValue(NULL));
2061 // Load the value as a double.
2062 SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0);
2064 // FCFID it and return it.
2065 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld);
2066 if (Op.getValueType() == MVT::f32)
2067 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
2071 static SDOperand LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) {
2072 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
2073 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
2075 // Expand into a bunch of logical ops. Note that these ops
2076 // depend on the PPC behavior for oversized shift amounts.
2077 SDOperand Lo = Op.getOperand(0);
2078 SDOperand Hi = Op.getOperand(1);
2079 SDOperand Amt = Op.getOperand(2);
2081 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
2082 DAG.getConstant(32, MVT::i32), Amt);
2083 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt);
2084 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1);
2085 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
2086 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
2087 DAG.getConstant(-32U, MVT::i32));
2088 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5);
2089 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
2090 SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt);
2091 SDOperand OutOps[] = { OutLo, OutHi };
2092 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
2096 static SDOperand LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) {
2097 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
2098 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRL!");
2100 // Otherwise, expand into a bunch of logical ops. Note that these ops
2101 // depend on the PPC behavior for oversized shift amounts.
2102 SDOperand Lo = Op.getOperand(0);
2103 SDOperand Hi = Op.getOperand(1);
2104 SDOperand Amt = Op.getOperand(2);
2106 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
2107 DAG.getConstant(32, MVT::i32), Amt);
2108 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
2109 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
2110 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
2111 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
2112 DAG.getConstant(-32U, MVT::i32));
2113 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5);
2114 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
2115 SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt);
2116 SDOperand OutOps[] = { OutLo, OutHi };
2117 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
2121 static SDOperand LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) {
2122 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
2123 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!");
2125 // Otherwise, expand into a bunch of logical ops, followed by a select_cc.
2126 SDOperand Lo = Op.getOperand(0);
2127 SDOperand Hi = Op.getOperand(1);
2128 SDOperand Amt = Op.getOperand(2);
2130 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
2131 DAG.getConstant(32, MVT::i32), Amt);
2132 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
2133 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
2134 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
2135 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
2136 DAG.getConstant(-32U, MVT::i32));
2137 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5);
2138 SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt);
2139 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32),
2140 Tmp4, Tmp6, ISD::SETLE);
2141 SDOperand OutOps[] = { OutLo, OutHi };
2142 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
2146 //===----------------------------------------------------------------------===//
2147 // Vector related lowering.
2150 // If this is a vector of constants or undefs, get the bits. A bit in
2151 // UndefBits is set if the corresponding element of the vector is an
2152 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
2153 // zero. Return true if this is not an array of constants, false if it is.
2155 static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
2156 uint64_t UndefBits[2]) {
2157 // Start with zero'd results.
2158 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0;
2160 unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType());
2161 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
2162 SDOperand OpVal = BV->getOperand(i);
2164 unsigned PartNo = i >= e/2; // In the upper 128 bits?
2165 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t.
2167 uint64_t EltBits = 0;
2168 if (OpVal.getOpcode() == ISD::UNDEF) {
2169 uint64_t EltUndefBits = ~0U >> (32-EltBitSize);
2170 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize);
2172 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
2173 EltBits = CN->getValue() & (~0U >> (32-EltBitSize));
2174 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
2175 assert(CN->getValueType(0) == MVT::f32 &&
2176 "Only one legal FP vector type!");
2177 EltBits = FloatToBits(CN->getValue());
2179 // Nonconstant element.
2183 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize);
2186 //printf("%llx %llx %llx %llx\n",
2187 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]);
2191 // If this is a splat (repetition) of a value across the whole vector, return
2192 // the smallest size that splats it. For example, "0x01010101010101..." is a
2193 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
2194 // SplatSize = 1 byte.
2195 static bool isConstantSplat(const uint64_t Bits128[2],
2196 const uint64_t Undef128[2],
2197 unsigned &SplatBits, unsigned &SplatUndef,
2198 unsigned &SplatSize) {
2200 // Don't let undefs prevent splats from matching. See if the top 64-bits are
2201 // the same as the lower 64-bits, ignoring undefs.
2202 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0]))
2203 return false; // Can't be a splat if two pieces don't match.
2205 uint64_t Bits64 = Bits128[0] | Bits128[1];
2206 uint64_t Undef64 = Undef128[0] & Undef128[1];
2208 // Check that the top 32-bits are the same as the lower 32-bits, ignoring
2210 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64))
2211 return false; // Can't be a splat if two pieces don't match.
2213 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32);
2214 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32);
2216 // If the top 16-bits are different than the lower 16-bits, ignoring
2217 // undefs, we have an i32 splat.
2218 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) {
2220 SplatUndef = Undef32;
2225 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16);
2226 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16);
2228 // If the top 8-bits are different than the lower 8-bits, ignoring
2229 // undefs, we have an i16 splat.
2230 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) {
2232 SplatUndef = Undef16;
2237 // Otherwise, we have an 8-bit splat.
2238 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8);
2239 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8);
2244 /// BuildSplatI - Build a canonical splati of Val with an element size of
2245 /// SplatSize. Cast the result to VT.
2246 static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT,
2247 SelectionDAG &DAG) {
2248 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
2250 static const MVT::ValueType VTys[] = { // canonical VT to use for each size.
2251 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
2254 MVT::ValueType ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
2256 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
2260 MVT::ValueType CanonicalVT = VTys[SplatSize-1];
2262 // Build a canonical splat for this value.
2263 SDOperand Elt = DAG.getConstant(Val, MVT::getVectorElementType(CanonicalVT));
2264 SmallVector<SDOperand, 8> Ops;
2265 Ops.assign(MVT::getVectorNumElements(CanonicalVT), Elt);
2266 SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT,
2267 &Ops[0], Ops.size());
2268 return DAG.getNode(ISD::BIT_CONVERT, ReqVT, Res);
2271 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
2272 /// specified intrinsic ID.
2273 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS,
2275 MVT::ValueType DestVT = MVT::Other) {
2276 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
2277 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
2278 DAG.getConstant(IID, MVT::i32), LHS, RHS);
2281 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
2282 /// specified intrinsic ID.
2283 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1,
2284 SDOperand Op2, SelectionDAG &DAG,
2285 MVT::ValueType DestVT = MVT::Other) {
2286 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
2287 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
2288 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
2292 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
2293 /// amount. The result has the specified value type.
2294 static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt,
2295 MVT::ValueType VT, SelectionDAG &DAG) {
2296 // Force LHS/RHS to be the right type.
2297 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS);
2298 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS);
2301 for (unsigned i = 0; i != 16; ++i)
2302 Ops[i] = DAG.getConstant(i+Amt, MVT::i32);
2303 SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS,
2304 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16));
2305 return DAG.getNode(ISD::BIT_CONVERT, VT, T);
2308 // If this is a case we can't handle, return null and let the default
2309 // expansion code take care of it. If we CAN select this case, and if it
2310 // selects to a single instruction, return Op. Otherwise, if we can codegen
2311 // this case more efficiently than a constant pool load, lower it to the
2312 // sequence of ops that should be used.
2313 static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2314 // If this is a vector of constants or undefs, get the bits. A bit in
2315 // UndefBits is set if the corresponding element of the vector is an
2316 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
2318 uint64_t VectorBits[2];
2319 uint64_t UndefBits[2];
2320 if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits))
2321 return SDOperand(); // Not a constant vector.
2323 // If this is a splat (repetition) of a value across the whole vector, return
2324 // the smallest size that splats it. For example, "0x01010101010101..." is a
2325 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
2326 // SplatSize = 1 byte.
2327 unsigned SplatBits, SplatUndef, SplatSize;
2328 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){
2329 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0;
2331 // First, handle single instruction cases.
2334 if (SplatBits == 0) {
2335 // Canonicalize all zero vectors to be v4i32.
2336 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
2337 SDOperand Z = DAG.getConstant(0, MVT::i32);
2338 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z);
2339 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z);
2344 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
2345 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize);
2346 if (SextVal >= -16 && SextVal <= 15)
2347 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG);
2350 // Two instruction sequences.
2352 // If this value is in the range [-32,30] and is even, use:
2353 // tmp = VSPLTI[bhw], result = add tmp, tmp
2354 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
2355 Op = BuildSplatI(SextVal >> 1, SplatSize, Op.getValueType(), DAG);
2356 return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op);
2359 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
2360 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
2362 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
2363 // Make -1 and vspltisw -1:
2364 SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG);
2366 // Make the VSLW intrinsic, computing 0x8000_0000.
2367 SDOperand Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
2370 // xor by OnesV to invert it.
2371 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV);
2372 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2375 // Check to see if this is a wide variety of vsplti*, binop self cases.
2376 unsigned SplatBitSize = SplatSize*8;
2377 static const signed char SplatCsts[] = {
2378 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
2379 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
2382 for (unsigned idx = 0; idx < sizeof(SplatCsts)/sizeof(SplatCsts[0]); ++idx){
2383 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
2384 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
2385 int i = SplatCsts[idx];
2387 // Figure out what shift amount will be used by altivec if shifted by i in
2389 unsigned TypeShiftAmt = i & (SplatBitSize-1);
2391 // vsplti + shl self.
2392 if (SextVal == (i << (int)TypeShiftAmt)) {
2393 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2394 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2395 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
2396 Intrinsic::ppc_altivec_vslw
2398 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2399 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2402 // vsplti + srl self.
2403 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
2404 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2405 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2406 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
2407 Intrinsic::ppc_altivec_vsrw
2409 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2410 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2413 // vsplti + sra self.
2414 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
2415 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2416 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2417 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
2418 Intrinsic::ppc_altivec_vsraw
2420 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2421 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2424 // vsplti + rol self.
2425 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
2426 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
2427 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2428 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2429 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
2430 Intrinsic::ppc_altivec_vrlw
2432 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2433 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2436 // t = vsplti c, result = vsldoi t, t, 1
2437 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
2438 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2439 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG);
2441 // t = vsplti c, result = vsldoi t, t, 2
2442 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
2443 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2444 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG);
2446 // t = vsplti c, result = vsldoi t, t, 3
2447 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
2448 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2449 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG);
2453 // Three instruction sequences.
2455 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
2456 if (SextVal >= 0 && SextVal <= 31) {
2457 SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG);
2458 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
2459 LHS = DAG.getNode(ISD::SUB, Op.getValueType(), LHS, RHS);
2460 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
2462 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
2463 if (SextVal >= -31 && SextVal <= 0) {
2464 SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG);
2465 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
2466 LHS = DAG.getNode(ISD::ADD, Op.getValueType(), LHS, RHS);
2467 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
2474 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
2475 /// the specified operations to build the shuffle.
2476 static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS,
2477 SDOperand RHS, SelectionDAG &DAG) {
2478 unsigned OpNum = (PFEntry >> 26) & 0x0F;
2479 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
2480 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
2483 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
2495 if (OpNum == OP_COPY) {
2496 if (LHSID == (1*9+2)*9+3) return LHS;
2497 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
2501 SDOperand OpLHS, OpRHS;
2502 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG);
2503 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG);
2505 unsigned ShufIdxs[16];
2507 default: assert(0 && "Unknown i32 permute!");
2509 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
2510 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
2511 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
2512 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
2515 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
2516 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
2517 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
2518 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
2521 for (unsigned i = 0; i != 16; ++i)
2522 ShufIdxs[i] = (i&3)+0;
2525 for (unsigned i = 0; i != 16; ++i)
2526 ShufIdxs[i] = (i&3)+4;
2529 for (unsigned i = 0; i != 16; ++i)
2530 ShufIdxs[i] = (i&3)+8;
2533 for (unsigned i = 0; i != 16; ++i)
2534 ShufIdxs[i] = (i&3)+12;
2537 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG);
2539 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG);
2541 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG);
2544 for (unsigned i = 0; i != 16; ++i)
2545 Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i32);
2547 return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS,
2548 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
2551 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
2552 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
2553 /// return the code it can be lowered into. Worst case, it can always be
2554 /// lowered into a vperm.
2555 static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
2556 SDOperand V1 = Op.getOperand(0);
2557 SDOperand V2 = Op.getOperand(1);
2558 SDOperand PermMask = Op.getOperand(2);
2560 // Cases that are handled by instructions that take permute immediates
2561 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
2562 // selected by the instruction selector.
2563 if (V2.getOpcode() == ISD::UNDEF) {
2564 if (PPC::isSplatShuffleMask(PermMask.Val, 1) ||
2565 PPC::isSplatShuffleMask(PermMask.Val, 2) ||
2566 PPC::isSplatShuffleMask(PermMask.Val, 4) ||
2567 PPC::isVPKUWUMShuffleMask(PermMask.Val, true) ||
2568 PPC::isVPKUHUMShuffleMask(PermMask.Val, true) ||
2569 PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 ||
2570 PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) ||
2571 PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) ||
2572 PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) ||
2573 PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) ||
2574 PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) ||
2575 PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) {
2580 // Altivec has a variety of "shuffle immediates" that take two vector inputs
2581 // and produce a fixed permutation. If any of these match, do not lower to
2583 if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) ||
2584 PPC::isVPKUHUMShuffleMask(PermMask.Val, false) ||
2585 PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 ||
2586 PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) ||
2587 PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) ||
2588 PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) ||
2589 PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) ||
2590 PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) ||
2591 PPC::isVMRGHShuffleMask(PermMask.Val, 4, false))
2594 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
2595 // perfect shuffle table to emit an optimal matching sequence.
2596 unsigned PFIndexes[4];
2597 bool isFourElementShuffle = true;
2598 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
2599 unsigned EltNo = 8; // Start out undef.
2600 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
2601 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF)
2602 continue; // Undef, ignore it.
2604 unsigned ByteSource =
2605 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue();
2606 if ((ByteSource & 3) != j) {
2607 isFourElementShuffle = false;
2612 EltNo = ByteSource/4;
2613 } else if (EltNo != ByteSource/4) {
2614 isFourElementShuffle = false;
2618 PFIndexes[i] = EltNo;
2621 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
2622 // perfect shuffle vector to determine if it is cost effective to do this as
2623 // discrete instructions, or whether we should use a vperm.
2624 if (isFourElementShuffle) {
2625 // Compute the index in the perfect shuffle table.
2626 unsigned PFTableIndex =
2627 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
2629 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
2630 unsigned Cost = (PFEntry >> 30);
2632 // Determining when to avoid vperm is tricky. Many things affect the cost
2633 // of vperm, particularly how many times the perm mask needs to be computed.
2634 // For example, if the perm mask can be hoisted out of a loop or is already
2635 // used (perhaps because there are multiple permutes with the same shuffle
2636 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
2637 // the loop requires an extra register.
2639 // As a compromise, we only emit discrete instructions if the shuffle can be
2640 // generated in 3 or fewer operations. When we have loop information
2641 // available, if this block is within a loop, we should avoid using vperm
2642 // for 3-operation perms and use a constant pool load instead.
2644 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG);
2647 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
2648 // vector that will get spilled to the constant pool.
2649 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
2651 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
2652 // that it is in input element units, not in bytes. Convert now.
2653 MVT::ValueType EltVT = MVT::getVectorElementType(V1.getValueType());
2654 unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8;
2656 SmallVector<SDOperand, 16> ResultMask;
2657 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
2659 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
2662 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue();
2664 for (unsigned j = 0; j != BytesPerElement; ++j)
2665 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
2669 SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8,
2670 &ResultMask[0], ResultMask.size());
2671 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
2674 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
2675 /// altivec comparison. If it is, return true and fill in Opc/isDot with
2676 /// information about the intrinsic.
2677 static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc,
2679 unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue();
2682 switch (IntrinsicID) {
2683 default: return false;
2684 // Comparison predicates.
2685 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
2686 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
2687 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
2688 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
2689 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
2690 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
2691 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
2692 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
2693 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
2694 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
2695 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
2696 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
2697 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
2699 // Normal Comparisons.
2700 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
2701 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
2702 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
2703 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
2704 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
2705 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
2706 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
2707 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
2708 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
2709 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
2710 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
2711 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
2712 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
2717 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
2718 /// lower, do it, otherwise return null.
2719 static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
2720 // If this is a lowered altivec predicate compare, CompareOpc is set to the
2721 // opcode number of the comparison.
2724 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
2725 return SDOperand(); // Don't custom lower most intrinsics.
2727 // If this is a non-dot comparison, make the VCMP node and we are done.
2729 SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(),
2730 Op.getOperand(1), Op.getOperand(2),
2731 DAG.getConstant(CompareOpc, MVT::i32));
2732 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp);
2735 // Create the PPCISD altivec 'dot' comparison node.
2737 Op.getOperand(2), // LHS
2738 Op.getOperand(3), // RHS
2739 DAG.getConstant(CompareOpc, MVT::i32)
2741 std::vector<MVT::ValueType> VTs;
2742 VTs.push_back(Op.getOperand(2).getValueType());
2743 VTs.push_back(MVT::Flag);
2744 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
2746 // Now that we have the comparison, emit a copy from the CR to a GPR.
2747 // This is flagged to the above dot comparison.
2748 SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32,
2749 DAG.getRegister(PPC::CR6, MVT::i32),
2750 CompNode.getValue(1));
2752 // Unpack the result based on how the target uses it.
2753 unsigned BitNo; // Bit # of CR6.
2754 bool InvertBit; // Invert result?
2755 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
2756 default: // Can't happen, don't crash on invalid number though.
2757 case 0: // Return the value of the EQ bit of CR6.
2758 BitNo = 0; InvertBit = false;
2760 case 1: // Return the inverted value of the EQ bit of CR6.
2761 BitNo = 0; InvertBit = true;
2763 case 2: // Return the value of the LT bit of CR6.
2764 BitNo = 2; InvertBit = false;
2766 case 3: // Return the inverted value of the LT bit of CR6.
2767 BitNo = 2; InvertBit = true;
2771 // Shift the bit into the low position.
2772 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags,
2773 DAG.getConstant(8-(3-BitNo), MVT::i32));
2775 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags,
2776 DAG.getConstant(1, MVT::i32));
2778 // If we are supposed to, toggle the bit.
2780 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags,
2781 DAG.getConstant(1, MVT::i32));
2785 static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2786 // Create a stack slot that is 16-byte aligned.
2787 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
2788 int FrameIdx = FrameInfo->CreateStackObject(16, 16);
2789 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2790 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
2792 // Store the input value into Value#0 of the stack slot.
2793 SDOperand Store = DAG.getStore(DAG.getEntryNode(),
2794 Op.getOperand(0), FIdx, NULL, 0);
2796 return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0);
2799 static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) {
2800 if (Op.getValueType() == MVT::v4i32) {
2801 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2803 SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG);
2804 SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt.
2806 SDOperand RHSSwap = // = vrlw RHS, 16
2807 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG);
2809 // Shrinkify inputs to v8i16.
2810 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS);
2811 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS);
2812 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap);
2814 // Low parts multiplied together, generating 32-bit results (we ignore the
2816 SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
2817 LHS, RHS, DAG, MVT::v4i32);
2819 SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
2820 LHS, RHSSwap, Zero, DAG, MVT::v4i32);
2821 // Shift the high parts up 16 bits.
2822 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG);
2823 return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd);
2824 } else if (Op.getValueType() == MVT::v8i16) {
2825 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2827 SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG);
2829 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
2830 LHS, RHS, Zero, DAG);
2831 } else if (Op.getValueType() == MVT::v16i8) {
2832 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2834 // Multiply the even 8-bit parts, producing 16-bit sums.
2835 SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
2836 LHS, RHS, DAG, MVT::v8i16);
2837 EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts);
2839 // Multiply the odd 8-bit parts, producing 16-bit sums.
2840 SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
2841 LHS, RHS, DAG, MVT::v8i16);
2842 OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts);
2844 // Merge the results together.
2846 for (unsigned i = 0; i != 8; ++i) {
2847 Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8);
2848 Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8);
2850 return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts,
2851 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
2853 assert(0 && "Unknown mul to lower!");
2858 /// LowerOperation - Provide custom lowering hooks for some operations.
2860 SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
2861 switch (Op.getOpcode()) {
2862 default: assert(0 && "Wasn't expecting to be able to lower this!");
2863 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2864 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
2865 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
2866 case ISD::SETCC: return LowerSETCC(Op, DAG);
2868 return LowerVASTART(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
2869 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
2872 return LowerVAARG(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
2873 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
2875 case ISD::FORMAL_ARGUMENTS:
2876 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex,
2877 VarArgsStackOffset, VarArgsNumGPR,
2878 VarArgsNumFPR, PPCSubTarget);
2880 case ISD::CALL: return LowerCALL(Op, DAG, PPCSubTarget);
2881 case ISD::RET: return LowerRET(Op, DAG, getTargetMachine());
2882 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
2883 case ISD::DYNAMIC_STACKALLOC:
2884 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
2886 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
2887 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
2888 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
2890 // Lower 64-bit shifts.
2891 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
2892 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
2893 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
2895 // Vector-related lowering.
2896 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
2897 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2898 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2899 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
2900 case ISD::MUL: return LowerMUL(Op, DAG);
2902 // Frame & Return address. Currently unimplemented
2903 case ISD::RETURNADDR: break;
2904 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
2909 //===----------------------------------------------------------------------===//
2910 // Other Lowering Code
2911 //===----------------------------------------------------------------------===//
2914 PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
2915 MachineBasicBlock *BB) {
2916 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2917 assert((MI->getOpcode() == PPC::SELECT_CC_I4 ||
2918 MI->getOpcode() == PPC::SELECT_CC_I8 ||
2919 MI->getOpcode() == PPC::SELECT_CC_F4 ||
2920 MI->getOpcode() == PPC::SELECT_CC_F8 ||
2921 MI->getOpcode() == PPC::SELECT_CC_VRRC) &&
2922 "Unexpected instr type to insert");
2924 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
2925 // control-flow pattern. The incoming instruction knows the destination vreg
2926 // to set, the condition code register to branch on, the true/false values to
2927 // select between, and a branch opcode to use.
2928 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2929 ilist<MachineBasicBlock>::iterator It = BB;
2935 // cmpTY ccX, r1, r2
2937 // fallthrough --> copy0MBB
2938 MachineBasicBlock *thisMBB = BB;
2939 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
2940 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
2941 unsigned SelectPred = MI->getOperand(4).getImm();
2942 BuildMI(BB, TII->get(PPC::BCC))
2943 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
2944 MachineFunction *F = BB->getParent();
2945 F->getBasicBlockList().insert(It, copy0MBB);
2946 F->getBasicBlockList().insert(It, sinkMBB);
2947 // Update machine-CFG edges by first adding all successors of the current
2948 // block to the new block which will contain the Phi node for the select.
2949 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
2950 e = BB->succ_end(); i != e; ++i)
2951 sinkMBB->addSuccessor(*i);
2952 // Next, remove all successors of the current block, and add the true
2953 // and fallthrough blocks as its successors.
2954 while(!BB->succ_empty())
2955 BB->removeSuccessor(BB->succ_begin());
2956 BB->addSuccessor(copy0MBB);
2957 BB->addSuccessor(sinkMBB);
2960 // %FalseValue = ...
2961 // # fallthrough to sinkMBB
2964 // Update machine-CFG edges
2965 BB->addSuccessor(sinkMBB);
2968 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
2971 BuildMI(BB, TII->get(PPC::PHI), MI->getOperand(0).getReg())
2972 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
2973 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
2975 delete MI; // The pseudo instruction is gone now.
2979 //===----------------------------------------------------------------------===//
2980 // Target Optimization Hooks
2981 //===----------------------------------------------------------------------===//
2983 SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
2984 DAGCombinerInfo &DCI) const {
2985 TargetMachine &TM = getTargetMachine();
2986 SelectionDAG &DAG = DCI.DAG;
2987 switch (N->getOpcode()) {
2990 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
2991 if (C->getValue() == 0) // 0 << V -> 0.
2992 return N->getOperand(0);
2996 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
2997 if (C->getValue() == 0) // 0 >>u V -> 0.
2998 return N->getOperand(0);
3002 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
3003 if (C->getValue() == 0 || // 0 >>s V -> 0.
3004 C->isAllOnesValue()) // -1 >>s V -> -1.
3005 return N->getOperand(0);
3009 case ISD::SINT_TO_FP:
3010 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
3011 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
3012 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
3013 // We allow the src/dst to be either f32/f64, but the intermediate
3014 // type must be i64.
3015 if (N->getOperand(0).getValueType() == MVT::i64) {
3016 SDOperand Val = N->getOperand(0).getOperand(0);
3017 if (Val.getValueType() == MVT::f32) {
3018 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
3019 DCI.AddToWorklist(Val.Val);
3022 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val);
3023 DCI.AddToWorklist(Val.Val);
3024 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val);
3025 DCI.AddToWorklist(Val.Val);
3026 if (N->getValueType(0) == MVT::f32) {
3027 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val);
3028 DCI.AddToWorklist(Val.Val);
3031 } else if (N->getOperand(0).getValueType() == MVT::i32) {
3032 // If the intermediate type is i32, we can avoid the load/store here
3039 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
3040 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
3041 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
3042 N->getOperand(1).getValueType() == MVT::i32) {
3043 SDOperand Val = N->getOperand(1).getOperand(0);
3044 if (Val.getValueType() == MVT::f32) {
3045 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
3046 DCI.AddToWorklist(Val.Val);
3048 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val);
3049 DCI.AddToWorklist(Val.Val);
3051 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val,
3052 N->getOperand(2), N->getOperand(3));
3053 DCI.AddToWorklist(Val.Val);
3057 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
3058 if (N->getOperand(1).getOpcode() == ISD::BSWAP &&
3059 N->getOperand(1).Val->hasOneUse() &&
3060 (N->getOperand(1).getValueType() == MVT::i32 ||
3061 N->getOperand(1).getValueType() == MVT::i16)) {
3062 SDOperand BSwapOp = N->getOperand(1).getOperand(0);
3063 // Do an any-extend to 32-bits if this is a half-word input.
3064 if (BSwapOp.getValueType() == MVT::i16)
3065 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp);
3067 return DAG.getNode(PPCISD::STBRX, MVT::Other, N->getOperand(0), BSwapOp,
3068 N->getOperand(2), N->getOperand(3),
3069 DAG.getValueType(N->getOperand(1).getValueType()));
3073 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
3074 if (ISD::isNON_EXTLoad(N->getOperand(0).Val) &&
3075 N->getOperand(0).hasOneUse() &&
3076 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
3077 SDOperand Load = N->getOperand(0);
3078 LoadSDNode *LD = cast<LoadSDNode>(Load);
3079 // Create the byte-swapping load.
3080 std::vector<MVT::ValueType> VTs;
3081 VTs.push_back(MVT::i32);
3082 VTs.push_back(MVT::Other);
3083 SDOperand SV = DAG.getSrcValue(LD->getSrcValue(), LD->getSrcValueOffset());
3085 LD->getChain(), // Chain
3086 LD->getBasePtr(), // Ptr
3088 DAG.getValueType(N->getValueType(0)) // VT
3090 SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4);
3092 // If this is an i16 load, insert the truncate.
3093 SDOperand ResVal = BSLoad;
3094 if (N->getValueType(0) == MVT::i16)
3095 ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad);
3097 // First, combine the bswap away. This makes the value produced by the
3099 DCI.CombineTo(N, ResVal);
3101 // Next, combine the load away, we give it a bogus result value but a real
3102 // chain result. The result value is dead because the bswap is dead.
3103 DCI.CombineTo(Load.Val, ResVal, BSLoad.getValue(1));
3105 // Return N so it doesn't get rechecked!
3106 return SDOperand(N, 0);
3110 case PPCISD::VCMP: {
3111 // If a VCMPo node already exists with exactly the same operands as this
3112 // node, use its result instead of this node (VCMPo computes both a CR6 and
3113 // a normal output).
3115 if (!N->getOperand(0).hasOneUse() &&
3116 !N->getOperand(1).hasOneUse() &&
3117 !N->getOperand(2).hasOneUse()) {
3119 // Scan all of the users of the LHS, looking for VCMPo's that match.
3120 SDNode *VCMPoNode = 0;
3122 SDNode *LHSN = N->getOperand(0).Val;
3123 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
3125 if ((*UI)->getOpcode() == PPCISD::VCMPo &&
3126 (*UI)->getOperand(1) == N->getOperand(1) &&
3127 (*UI)->getOperand(2) == N->getOperand(2) &&
3128 (*UI)->getOperand(0) == N->getOperand(0)) {
3133 // If there is no VCMPo node, or if the flag value has a single use, don't
3135 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
3138 // Look at the (necessarily single) use of the flag value. If it has a
3139 // chain, this transformation is more complex. Note that multiple things
3140 // could use the value result, which we should ignore.
3141 SDNode *FlagUser = 0;
3142 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
3143 FlagUser == 0; ++UI) {
3144 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
3146 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
3147 if (User->getOperand(i) == SDOperand(VCMPoNode, 1)) {
3154 // If the user is a MFCR instruction, we know this is safe. Otherwise we
3155 // give up for right now.
3156 if (FlagUser->getOpcode() == PPCISD::MFCR)
3157 return SDOperand(VCMPoNode, 0);
3162 // If this is a branch on an altivec predicate comparison, lower this so
3163 // that we don't have to do a MFCR: instead, branch directly on CR6. This
3164 // lowering is done pre-legalize, because the legalizer lowers the predicate
3165 // compare down to code that is difficult to reassemble.
3166 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
3167 SDOperand LHS = N->getOperand(2), RHS = N->getOperand(3);
3171 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
3172 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
3173 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
3174 assert(isDot && "Can't compare against a vector result!");
3176 // If this is a comparison against something other than 0/1, then we know
3177 // that the condition is never/always true.
3178 unsigned Val = cast<ConstantSDNode>(RHS)->getValue();
3179 if (Val != 0 && Val != 1) {
3180 if (CC == ISD::SETEQ) // Cond never true, remove branch.
3181 return N->getOperand(0);
3182 // Always !=, turn it into an unconditional branch.
3183 return DAG.getNode(ISD::BR, MVT::Other,
3184 N->getOperand(0), N->getOperand(4));
3187 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
3189 // Create the PPCISD altivec 'dot' comparison node.
3190 std::vector<MVT::ValueType> VTs;
3192 LHS.getOperand(2), // LHS of compare
3193 LHS.getOperand(3), // RHS of compare
3194 DAG.getConstant(CompareOpc, MVT::i32)
3196 VTs.push_back(LHS.getOperand(2).getValueType());
3197 VTs.push_back(MVT::Flag);
3198 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
3200 // Unpack the result based on how the target uses it.
3201 PPC::Predicate CompOpc;
3202 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) {
3203 default: // Can't happen, don't crash on invalid number though.
3204 case 0: // Branch on the value of the EQ bit of CR6.
3205 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
3207 case 1: // Branch on the inverted value of the EQ bit of CR6.
3208 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
3210 case 2: // Branch on the value of the LT bit of CR6.
3211 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
3213 case 3: // Branch on the inverted value of the LT bit of CR6.
3214 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
3218 return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0),
3219 DAG.getConstant(CompOpc, MVT::i32),
3220 DAG.getRegister(PPC::CR6, MVT::i32),
3221 N->getOperand(4), CompNode.getValue(1));
3230 //===----------------------------------------------------------------------===//
3231 // Inline Assembly Support
3232 //===----------------------------------------------------------------------===//
3234 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
3236 uint64_t &KnownZero,
3238 unsigned Depth) const {
3241 switch (Op.getOpcode()) {
3243 case PPCISD::LBRX: {
3244 // lhbrx is known to have the top bits cleared out.
3245 if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16)
3246 KnownZero = 0xFFFF0000;
3249 case ISD::INTRINSIC_WO_CHAIN: {
3250 switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) {
3252 case Intrinsic::ppc_altivec_vcmpbfp_p:
3253 case Intrinsic::ppc_altivec_vcmpeqfp_p:
3254 case Intrinsic::ppc_altivec_vcmpequb_p:
3255 case Intrinsic::ppc_altivec_vcmpequh_p:
3256 case Intrinsic::ppc_altivec_vcmpequw_p:
3257 case Intrinsic::ppc_altivec_vcmpgefp_p:
3258 case Intrinsic::ppc_altivec_vcmpgtfp_p:
3259 case Intrinsic::ppc_altivec_vcmpgtsb_p:
3260 case Intrinsic::ppc_altivec_vcmpgtsh_p:
3261 case Intrinsic::ppc_altivec_vcmpgtsw_p:
3262 case Intrinsic::ppc_altivec_vcmpgtub_p:
3263 case Intrinsic::ppc_altivec_vcmpgtuh_p:
3264 case Intrinsic::ppc_altivec_vcmpgtuw_p:
3265 KnownZero = ~1U; // All bits but the low one are known to be zero.
3273 /// getConstraintType - Given a constraint, return the type of
3274 /// constraint it is for this target.
3275 PPCTargetLowering::ConstraintType
3276 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
3277 if (Constraint.size() == 1) {
3278 switch (Constraint[0]) {
3285 return C_RegisterClass;
3288 return TargetLowering::getConstraintType(Constraint);
3291 std::pair<unsigned, const TargetRegisterClass*>
3292 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
3293 MVT::ValueType VT) const {
3294 if (Constraint.size() == 1) {
3295 // GCC RS6000 Constraint Letters
3296 switch (Constraint[0]) {
3299 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
3300 return std::make_pair(0U, PPC::G8RCRegisterClass);
3301 return std::make_pair(0U, PPC::GPRCRegisterClass);
3304 return std::make_pair(0U, PPC::F4RCRegisterClass);
3305 else if (VT == MVT::f64)
3306 return std::make_pair(0U, PPC::F8RCRegisterClass);
3309 return std::make_pair(0U, PPC::VRRCRegisterClass);
3311 return std::make_pair(0U, PPC::CRRCRegisterClass);
3315 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3319 // isOperandValidForConstraint
3320 SDOperand PPCTargetLowering::
3321 isOperandValidForConstraint(SDOperand Op, char Letter, SelectionDAG &DAG) {
3332 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
3333 if (!CST) return SDOperand(0, 0); // Must be an immediate to match.
3334 unsigned Value = CST->getValue();
3336 default: assert(0 && "Unknown constraint letter!");
3337 case 'I': // "I" is a signed 16-bit constant.
3338 if ((short)Value == (int)Value)
3339 return DAG.getTargetConstant(Value, Op.getValueType());
3341 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
3342 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
3343 if ((short)Value == 0)
3344 return DAG.getTargetConstant(Value, Op.getValueType());
3346 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
3347 if ((Value >> 16) == 0)
3348 return DAG.getTargetConstant(Value, Op.getValueType());
3350 case 'M': // "M" is a constant that is greater than 31.
3352 return DAG.getTargetConstant(Value, Op.getValueType());
3354 case 'N': // "N" is a positive constant that is an exact power of two.
3355 if ((int)Value > 0 && isPowerOf2_32(Value))
3356 return DAG.getTargetConstant(Value, Op.getValueType());
3358 case 'O': // "O" is the constant zero.
3360 return DAG.getTargetConstant(Value, Op.getValueType());
3362 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
3363 if ((short)-Value == (int)-Value)
3364 return DAG.getTargetConstant(Value, Op.getValueType());
3371 // Handle standard constraint letters.
3372 return TargetLowering::isOperandValidForConstraint(Op, Letter, DAG);
3375 // isLegalAddressingMode - Return true if the addressing mode represented
3376 // by AM is legal for this target, for a load/store of the specified type.
3377 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
3378 const Type *Ty) const {
3379 // FIXME: PPC does not allow r+i addressing modes for vectors!
3381 // PPC allows a sign-extended 16-bit immediate field.
3382 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
3385 // No global is ever allowed as a base.
3389 // PPC only support r+r,
3391 case 0: // "r+i" or just "i", depending on HasBaseReg.
3394 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
3396 // Otherwise we have r+r or r+i.
3399 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
3401 // Allow 2*r as r+r.
3404 // No other scales are supported.
3411 /// isLegalAddressImmediate - Return true if the integer value can be used
3412 /// as the offset of the target addressing mode for load / store of the
3414 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{
3415 // PPC allows a sign-extended 16-bit immediate field.
3416 return (V > -(1 << 16) && V < (1 << 16)-1);
3419 bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
3423 SDOperand PPCTargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG)
3425 // Depths > 0 not supported yet!
3426 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
3429 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3430 bool isPPC64 = PtrVT == MVT::i64;
3432 MachineFunction &MF = DAG.getMachineFunction();
3433 MachineFrameInfo *MFI = MF.getFrameInfo();
3434 bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects())
3435 && MFI->getStackSize();
3438 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::X31 : PPC::X1,
3441 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::R31 : PPC::R1,